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Commit 1c1c7506de1051df6d81c51a06a57be6406b534c

Authored by Daniel Hellstrom
1 parent 0986546582
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

leon: use CONFIG_SYS_HZ to config timer prescaler 

Before it was hardcoded to 1000 ticks per second.

Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>

Showing 2 changed files with 18 additions and 16 deletions Inline Diff

arch/sparc/cpu/leon2/cpu_init.c
Diff comments   View file @ 1c1c750
1 /* Initializes CPU and basic hardware such as memory 1 /* Initializes CPU and basic hardware such as memory
2 * controllers, IRQ controller and system timer 0. 2 * controllers, IRQ controller and system timer 0.
3 * 3 *
4 * (C) Copyright 2007 4 * (C) Copyright 2007
5 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com 5 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 #include <common.h> 10 #include <common.h>
11 #include <asm/asi.h> 11 #include <asm/asi.h>
12 #include <asm/leon.h> 12 #include <asm/leon.h>
13 13
14 #include <config.h> 14 #include <config.h>
15 15
16 #define TIMER_BASE_CLK 1000000
17 #define US_PER_TICK (1000000 / CONFIG_SYS_HZ)
18
16 DECLARE_GLOBAL_DATA_PTR; 19 DECLARE_GLOBAL_DATA_PTR;
17 20
18 /* reset CPU (jump to 0, without reset) */ 21 /* reset CPU (jump to 0, without reset) */
19 void start(void); 22 void start(void);
20 23
21 struct { 24 struct {
22 gd_t gd_area; 25 gd_t gd_area;
23 bd_t bd; 26 bd_t bd;
24 } global_data; 27 } global_data;
25 28
26 /* 29 /*
27 * Breath some life into the CPU... 30 * Breath some life into the CPU...
28 * 31 *
29 * Set up the memory map, 32 * Set up the memory map,
30 * initialize a bunch of registers. 33 * initialize a bunch of registers.
31 * 34 *
32 * Run from FLASH/PROM: 35 * Run from FLASH/PROM:
33 * - until memory controller is set up, only registers available 36 * - until memory controller is set up, only registers available
34 * - no global variables available for writing 37 * - no global variables available for writing
35 * - constants available 38 * - constants available
36 */ 39 */
37 40
38 void cpu_init_f(void) 41 void cpu_init_f(void)
39 { 42 {
40 LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; 43 LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
41 44
42 /* initialize the IRQMP */ 45 /* initialize the IRQMP */
43 leon2->Interrupt_Force = 0; 46 leon2->Interrupt_Force = 0;
44 leon2->Interrupt_Pending = 0; 47 leon2->Interrupt_Pending = 0;
45 leon2->Interrupt_Clear = 0xfffe; /* clear all old pending interrupts */ 48 leon2->Interrupt_Clear = 0xfffe; /* clear all old pending interrupts */
46 leon2->Interrupt_Mask = 0xfffe0000; /* mask all IRQs */ 49 leon2->Interrupt_Mask = 0xfffe0000; /* mask all IRQs */
47 50
48 /* cache */ 51 /* cache */
49 52
50 /* I/O port setup */ 53 /* I/O port setup */
51 #ifdef LEON2_IO_PORT_DIR 54 #ifdef LEON2_IO_PORT_DIR
52 leon2->PIO_Direction = LEON2_IO_PORT_DIR; 55 leon2->PIO_Direction = LEON2_IO_PORT_DIR;
53 #endif 56 #endif
54 #ifdef LEON2_IO_PORT_DATA 57 #ifdef LEON2_IO_PORT_DATA
55 leon2->PIO_Data = LEON2_IO_PORT_DATA; 58 leon2->PIO_Data = LEON2_IO_PORT_DATA;
56 #endif 59 #endif
57 #ifdef LEON2_IO_PORT_INT 60 #ifdef LEON2_IO_PORT_INT
58 leon2->PIO_Interrupt = LEON2_IO_PORT_INT; 61 leon2->PIO_Interrupt = LEON2_IO_PORT_INT;
59 #else 62 #else
60 leon2->PIO_Interrupt = 0; 63 leon2->PIO_Interrupt = 0;
61 #endif 64 #endif
62 } 65 }
63 66
64 void cpu_init_f2(void) 67 void cpu_init_f2(void)
65 { 68 {
66 69
67 } 70 }
68 71
69 /* 72 /*
70 * initialize higher level parts of CPU like time base and timers 73 * initialize higher level parts of CPU like time base and timers
71 */ 74 */
72 int cpu_init_r(void) 75 int cpu_init_r(void)
73 { 76 {
74 LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; 77 LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
75 78
76 /* initialize prescaler common to all timers to 1MHz */ 79 /* initialize prescaler common to all timers to 1MHz */
77 leon2->Scaler_Counter = leon2->Scaler_Reload = 80 leon2->Scaler_Counter = leon2->Scaler_Reload =
78 (((CONFIG_SYS_CLK_FREQ / 1000) + 500) / 1000) - 1; 81 (((CONFIG_SYS_CLK_FREQ / 1000) + 500) / 1000) - 1;
79 82
80 return (0); 83 return (0);
81 } 84 }
82 85
83 /* Uses Timer 0 to get accurate 86 /* Uses Timer 0 to get accurate
84 * pauses. Max 2 raised to 32 ticks 87 * pauses. Max 2 raised to 32 ticks
85 * 88 *
86 */ 89 */
87 void cpu_wait_ticks(unsigned long ticks) 90 void cpu_wait_ticks(unsigned long ticks)
88 { 91 {
89 unsigned long start = get_timer(0); 92 unsigned long start = get_timer(0);
90 while (get_timer(start) < ticks) ; 93 while (get_timer(start) < ticks) ;
91 } 94 }
92 95
93 /* initiate and setup timer0 interrupt to 1MHz 96 /* initiate and setup timer0 interrupt to configured HZ. Base clock is 1MHz.
94 * Return irq number for timer int or a negative number for 97 * Return irq number for timer int or a negative number for
95 * dealing with self 98 * dealing with self
96 */ 99 */
97 int timer_interrupt_init_cpu(void) 100 int timer_interrupt_init_cpu(void)
98 { 101 {
99 LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; 102 LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
100 103
101 /* 1ms ticks */ 104 /* SYS_HZ ticks per second */
102 leon2->Timer_Counter_1 = 0; 105 leon2->Timer_Counter_1 = 0;
103 leon2->Timer_Reload_1 = 999; /* (((1000000 / 100) - 1)) */ 106 leon2->Timer_Reload_1 = (TIMER_BASE_CLK / CONFIG_SYS_HZ) - 1;
104 leon2->Timer_Control_1 = 107 leon2->Timer_Control_1 =
105 (LEON2_TIMER_CTRL_EN | LEON2_TIMER_CTRL_RS | LEON2_TIMER_CTRL_LD); 108 (LEON2_TIMER_CTRL_EN | LEON2_TIMER_CTRL_RS | LEON2_TIMER_CTRL_LD);
106 109
107 return LEON2_TIMER1_IRQNO; 110 return LEON2_TIMER1_IRQNO;
108 } 111 }
109 112
110 /* 113 /*
111 * This function is intended for SHORT delays only. 114 * This function is intended for SHORT delays only.
112 */ 115 */
113 unsigned long cpu_usec2ticks(unsigned long usec) 116 unsigned long cpu_usec2ticks(unsigned long usec)
114 { 117 {
115 /* timer set to 1kHz ==> 1 clk tick = 1 msec */ 118 if (usec < US_PER_TICK)
116 if (usec < 1000)
117 return 1; 119 return 1;
118 return (usec / 1000); 120 return usec / US_PER_TICK;
119 } 121 }
120 122
121 unsigned long cpu_ticks2usec(unsigned long ticks) 123 unsigned long cpu_ticks2usec(unsigned long ticks)
122 { 124 {
123 /* 1tick = 1usec */ 125 return ticks * US_PER_TICK;
124 return ticks * 1000;
arch/sparc/cpu/leon3/cpu_init.c
Diff comments   View file @ 1c1c750
1 /* Initializes CPU and basic hardware such as memory 1 /* Initializes CPU and basic hardware such as memory
2 * controllers, IRQ controller and system timer 0. 2 * controllers, IRQ controller and system timer 0.
3 * 3 *
4 * (C) Copyright 2007 4 * (C) Copyright 2007
5 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com 5 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 #include <common.h> 10 #include <common.h>
11 #include <asm/asi.h> 11 #include <asm/asi.h>
12 #include <asm/leon.h> 12 #include <asm/leon.h>
13 #include <ambapp.h> 13 #include <ambapp.h>
14 14
15 #include <config.h> 15 #include <config.h>
16 16
17 #define TIMER_BASE_CLK 1000000
18 #define US_PER_TICK (1000000 / CONFIG_SYS_HZ)
19
17 DECLARE_GLOBAL_DATA_PTR; 20 DECLARE_GLOBAL_DATA_PTR;
18 21
19 /* reset CPU (jump to 0, without reset) */ 22 /* reset CPU (jump to 0, without reset) */
20 void start(void); 23 void start(void);
21 24
22 /* find & initialize the memory controller */ 25 /* find & initialize the memory controller */
23 int init_memory_ctrl(void); 26 int init_memory_ctrl(void);
24 27
25 ambapp_dev_irqmp *irqmp = NULL; 28 ambapp_dev_irqmp *irqmp = NULL;
26 ambapp_dev_mctrl memctrl; 29 ambapp_dev_mctrl memctrl;
27 ambapp_dev_gptimer *gptimer = NULL; 30 ambapp_dev_gptimer *gptimer = NULL;
28 unsigned int gptimer_irq = 0; 31 unsigned int gptimer_irq = 0;
29 int leon3_snooping_avail = 0; 32 int leon3_snooping_avail = 0;
30 33
31 struct { 34 struct {
32 gd_t gd_area; 35 gd_t gd_area;
33 bd_t bd; 36 bd_t bd;
34 } global_data; 37 } global_data;
35 38
36 /* 39 /*
37 * Breath some life into the CPU... 40 * Breath some life into the CPU...
38 * 41 *
39 * Set up the memory map, 42 * Set up the memory map,
40 * initialize a bunch of registers. 43 * initialize a bunch of registers.
41 * 44 *
42 * Run from FLASH/PROM: 45 * Run from FLASH/PROM:
43 * - until memory controller is set up, only registers available 46 * - until memory controller is set up, only registers available
44 * - no global variables available for writing 47 * - no global variables available for writing
45 * - constants available 48 * - constants available
46 */ 49 */
47 50
48 void cpu_init_f(void) 51 void cpu_init_f(void)
49 { 52 {
50 /* these varaiable must not be initialized */ 53 /* these varaiable must not be initialized */
51 ambapp_dev_irqmp *irqmp; 54 ambapp_dev_irqmp *irqmp;
52 ambapp_apbdev apbdev; 55 ambapp_apbdev apbdev;
53 register unsigned int apbmst; 56 register unsigned int apbmst;
54 57
55 /* find AMBA APB Master */ 58 /* find AMBA APB Master */
56 apbmst = (unsigned int) 59 apbmst = (unsigned int)
57 ambapp_ahb_next_nomem(VENDOR_GAISLER, GAISLER_APBMST, 1, 0); 60 ambapp_ahb_next_nomem(VENDOR_GAISLER, GAISLER_APBMST, 1, 0);
58 if (!apbmst) { 61 if (!apbmst) {
59 /* 62 /*
60 * no AHB/APB bridge, something is wrong 63 * no AHB/APB bridge, something is wrong
61 * ==> jump to start (or hang) 64 * ==> jump to start (or hang)
62 */ 65 */
63 while (1) ; 66 while (1) ;
64 } 67 }
65 /* Init memory controller */ 68 /* Init memory controller */
66 if (init_memory_ctrl()) { 69 if (init_memory_ctrl()) {
67 while (1) ; 70 while (1) ;
68 } 71 }
69 72
70 /**************************************************** 73 /****************************************************
71 * From here we can use the main memory and the stack. 74 * From here we can use the main memory and the stack.
72 */ 75 */
73 76
74 /* Find AMBA APB IRQMP Controller */ 77 /* Find AMBA APB IRQMP Controller */
75 if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_IRQMP, &apbdev) != 1) { 78 if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_IRQMP, &apbdev) != 1) {
76 /* no IRQ controller, something is wrong 79 /* no IRQ controller, something is wrong
77 * ==> jump to start (or hang) 80 * ==> jump to start (or hang)
78 */ 81 */
79 while (1) ; 82 while (1) ;
80 } 83 }
81 irqmp = (ambapp_dev_irqmp *) apbdev.address; 84 irqmp = (ambapp_dev_irqmp *) apbdev.address;
82 85
83 /* initialize the IRQMP */ 86 /* initialize the IRQMP */
84 irqmp->ilevel = 0xf; /* all IRQ off */ 87 irqmp->ilevel = 0xf; /* all IRQ off */
85 irqmp->iforce = 0; 88 irqmp->iforce = 0;
86 irqmp->ipend = 0; 89 irqmp->ipend = 0;
87 irqmp->iclear = 0xfffe; /* clear all old pending interrupts */ 90 irqmp->iclear = 0xfffe; /* clear all old pending interrupts */
88 irqmp->cpu_mask[0] = 0; /* mask all IRQs on CPU 0 */ 91 irqmp->cpu_mask[0] = 0; /* mask all IRQs on CPU 0 */
89 irqmp->cpu_force[0] = 0; /* no force IRQ on CPU 0 */ 92 irqmp->cpu_force[0] = 0; /* no force IRQ on CPU 0 */
90 93
91 /* cache */ 94 /* cache */
92 } 95 }
93 96
94 void cpu_init_f2(void) 97 void cpu_init_f2(void)
95 { 98 {
96 99
97 } 100 }
98 101
99 /* 102 /*
100 * initialize higher level parts of CPU like time base and timers 103 * initialize higher level parts of CPU like time base and timers
101 */ 104 */
102 int cpu_init_r(void) 105 int cpu_init_r(void)
103 { 106 {
104 ambapp_apbdev apbdev; 107 ambapp_apbdev apbdev;
105 108
106 /* 109 /*
107 * Find AMBA APB IRQMP Controller, 110 * Find AMBA APB IRQMP Controller,
108 * When we come so far we know there is a IRQMP available 111 * When we come so far we know there is a IRQMP available
109 */ 112 */
110 ambapp_apb_first(VENDOR_GAISLER, GAISLER_IRQMP, &apbdev); 113 ambapp_apb_first(VENDOR_GAISLER, GAISLER_IRQMP, &apbdev);
111 irqmp = (ambapp_dev_irqmp *) apbdev.address; 114 irqmp = (ambapp_dev_irqmp *) apbdev.address;
112 115
113 /* timer */ 116 /* timer */
114 if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_GPTIMER, &apbdev) != 1) { 117 if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_GPTIMER, &apbdev) != 1) {
115 printf("cpu_init_r: gptimer not found!\n"); 118 printf("cpu_init_r: gptimer not found!\n");
116 return 1; 119 return 1;
117 } 120 }
118 gptimer = (ambapp_dev_gptimer *) apbdev.address; 121 gptimer = (ambapp_dev_gptimer *) apbdev.address;
119 gptimer_irq = apbdev.irq; 122 gptimer_irq = apbdev.irq;
120 123
121 /* initialize prescaler common to all timers to 1MHz */ 124 /* initialize prescaler common to all timers to 1MHz */
122 gptimer->scalar = gptimer->scalar_reload = 125 gptimer->scalar = gptimer->scalar_reload =
123 (((CONFIG_SYS_CLK_FREQ / 1000) + 500) / 1000) - 1; 126 (((CONFIG_SYS_CLK_FREQ / 1000) + 500) / 1000) - 1;
124 127
125 return (0); 128 return (0);
126 } 129 }
127 130
128 /* find & setup memory controller */ 131 /* find & setup memory controller */
129 int init_memory_ctrl() 132 int init_memory_ctrl()
130 { 133 {
131 register ambapp_dev_mctrl *mctrl; 134 register ambapp_dev_mctrl *mctrl;
132 register ambapp_dev_sdctrl *sdctrl; 135 register ambapp_dev_sdctrl *sdctrl;
133 register ambapp_dev_ddrspa *ddrspa; 136 register ambapp_dev_ddrspa *ddrspa;
134 register ambapp_dev_ddr2spa *ddr2spa; 137 register ambapp_dev_ddr2spa *ddr2spa;
135 register ahbctrl_pp_dev *ahb; 138 register ahbctrl_pp_dev *ahb;
136 register unsigned int base; 139 register unsigned int base;
137 register int not_found_mctrl = -1; 140 register int not_found_mctrl = -1;
138 141
139 /* find ESA Memory controller */ 142 /* find ESA Memory controller */
140 base = ambapp_apb_next_nomem(VENDOR_ESA, ESA_MCTRL, 0); 143 base = ambapp_apb_next_nomem(VENDOR_ESA, ESA_MCTRL, 0);
141 if (base) { 144 if (base) {
142 mctrl = (ambapp_dev_mctrl *) base; 145 mctrl = (ambapp_dev_mctrl *) base;
143 146
144 /* config MCTRL memory controller */ 147 /* config MCTRL memory controller */
145 mctrl->mcfg1 = CONFIG_SYS_GRLIB_MEMCFG1 | (mctrl->mcfg1 & 0x300); 148 mctrl->mcfg1 = CONFIG_SYS_GRLIB_MEMCFG1 | (mctrl->mcfg1 & 0x300);
146 mctrl->mcfg2 = CONFIG_SYS_GRLIB_MEMCFG2; 149 mctrl->mcfg2 = CONFIG_SYS_GRLIB_MEMCFG2;
147 mctrl->mcfg3 = CONFIG_SYS_GRLIB_MEMCFG3; 150 mctrl->mcfg3 = CONFIG_SYS_GRLIB_MEMCFG3;
148 not_found_mctrl = 0; 151 not_found_mctrl = 0;
149 } 152 }
150 153
151 /* find Gaisler Fault Tolerant Memory controller */ 154 /* find Gaisler Fault Tolerant Memory controller */
152 base = ambapp_apb_next_nomem(VENDOR_GAISLER, GAISLER_FTMCTRL, 0); 155 base = ambapp_apb_next_nomem(VENDOR_GAISLER, GAISLER_FTMCTRL, 0);
153 if (base) { 156 if (base) {
154 mctrl = (ambapp_dev_mctrl *) base; 157 mctrl = (ambapp_dev_mctrl *) base;
155 158
156 /* config MCTRL memory controller */ 159 /* config MCTRL memory controller */
157 mctrl->mcfg1 = CONFIG_SYS_GRLIB_FT_MEMCFG1 | (mctrl->mcfg1 & 0x300); 160 mctrl->mcfg1 = CONFIG_SYS_GRLIB_FT_MEMCFG1 | (mctrl->mcfg1 & 0x300);
158 mctrl->mcfg2 = CONFIG_SYS_GRLIB_FT_MEMCFG2; 161 mctrl->mcfg2 = CONFIG_SYS_GRLIB_FT_MEMCFG2;
159 mctrl->mcfg3 = CONFIG_SYS_GRLIB_FT_MEMCFG3; 162 mctrl->mcfg3 = CONFIG_SYS_GRLIB_FT_MEMCFG3;
160 not_found_mctrl = 0; 163 not_found_mctrl = 0;
161 } 164 }
162 165
163 /* find SDRAM controller */ 166 /* find SDRAM controller */
164 base = ambapp_apb_next_nomem(VENDOR_GAISLER, GAISLER_SDCTRL, 0); 167 base = ambapp_apb_next_nomem(VENDOR_GAISLER, GAISLER_SDCTRL, 0);
165 if (base) { 168 if (base) {
166 sdctrl = (ambapp_dev_sdctrl *) base; 169 sdctrl = (ambapp_dev_sdctrl *) base;
167 170
168 /* config memory controller */ 171 /* config memory controller */
169 sdctrl->sdcfg = CONFIG_SYS_GRLIB_SDRAM; 172 sdctrl->sdcfg = CONFIG_SYS_GRLIB_SDRAM;
170 not_found_mctrl = 0; 173 not_found_mctrl = 0;
171 } 174 }
172 175
173 ahb = ambapp_ahb_next_nomem(VENDOR_GAISLER, GAISLER_DDR2SPA, 1, 0); 176 ahb = ambapp_ahb_next_nomem(VENDOR_GAISLER, GAISLER_DDR2SPA, 1, 0);
174 if (ahb) { 177 if (ahb) {
175 ddr2spa = (ambapp_dev_ddr2spa *) ambapp_ahb_get_info(ahb, 1); 178 ddr2spa = (ambapp_dev_ddr2spa *) ambapp_ahb_get_info(ahb, 1);
176 179
177 /* Config DDR2 memory controller */ 180 /* Config DDR2 memory controller */
178 ddr2spa->cfg1 = CONFIG_SYS_GRLIB_DDR2_CFG1; 181 ddr2spa->cfg1 = CONFIG_SYS_GRLIB_DDR2_CFG1;
179 ddr2spa->cfg3 = CONFIG_SYS_GRLIB_DDR2_CFG3; 182 ddr2spa->cfg3 = CONFIG_SYS_GRLIB_DDR2_CFG3;
180 not_found_mctrl = 0; 183 not_found_mctrl = 0;
181 } 184 }
182 185
183 ahb = ambapp_ahb_next_nomem(VENDOR_GAISLER, GAISLER_DDRSPA, 1, 0); 186 ahb = ambapp_ahb_next_nomem(VENDOR_GAISLER, GAISLER_DDRSPA, 1, 0);
184 if (ahb) { 187 if (ahb) {
185 ddrspa = (ambapp_dev_ddrspa *) ambapp_ahb_get_info(ahb, 1); 188 ddrspa = (ambapp_dev_ddrspa *) ambapp_ahb_get_info(ahb, 1);
186 189
187 /* Config DDR memory controller */ 190 /* Config DDR memory controller */
188 ddrspa->ctrl = CONFIG_SYS_GRLIB_DDR_CFG; 191 ddrspa->ctrl = CONFIG_SYS_GRLIB_DDR_CFG;
189 not_found_mctrl = 0; 192 not_found_mctrl = 0;
190 } 193 }
191 194
192 /* failed to find any memory controller */ 195 /* failed to find any memory controller */
193 return not_found_mctrl; 196 return not_found_mctrl;
194 } 197 }
195 198
196 /* Uses Timer 0 to get accurate 199 /* Uses Timer 0 to get accurate
197 * pauses. Max 2 raised to 32 ticks 200 * pauses. Max 2 raised to 32 ticks
198 * 201 *
199 */ 202 */
200 void cpu_wait_ticks(unsigned long ticks) 203 void cpu_wait_ticks(unsigned long ticks)
201 { 204 {
202 unsigned long start = get_timer(0); 205 unsigned long start = get_timer(0);
203 while (get_timer(start) < ticks) ; 206 while (get_timer(start) < ticks) ;
204 } 207 }
205 208
206 /* initiate and setup timer0 interrupt to 1MHz 209 /* initiate and setup timer0 interrupt to configured HZ. Base clock is 1MHz.
207 * Return irq number for timer int or a negative number for 210 * Return irq number for timer int or a negative number for
208 * dealing with self 211 * dealing with self
209 */ 212 */
210 int timer_interrupt_init_cpu(void) 213 int timer_interrupt_init_cpu(void)
211 { 214 {
212 /* 1ms ticks */ 215 /* SYS_HZ ticks per second */
213 gptimer->e[0].val = 0; 216 gptimer->e[0].val = 0;
214 gptimer->e[0].rld = 999; /* (((1000000 / 100) - 1)) */ 217 gptimer->e[0].rld = (TIMER_BASE_CLK / CONFIG_SYS_HZ) - 1;
215 gptimer->e[0].ctrl = 218 gptimer->e[0].ctrl =
216 (LEON3_GPTIMER_EN | 219 (LEON3_GPTIMER_EN |
217 LEON3_GPTIMER_RL | LEON3_GPTIMER_LD | LEON3_GPTIMER_IRQEN); 220 LEON3_GPTIMER_RL | LEON3_GPTIMER_LD | LEON3_GPTIMER_IRQEN);
218 221
219 return gptimer_irq; 222 return gptimer_irq;
220 } 223 }
221 224
222 /* 225 /*
223 * This function is intended for SHORT delays only. 226 * This function is intended for SHORT delays only.
224 */ 227 */
225 unsigned long cpu_usec2ticks(unsigned long usec) 228 unsigned long cpu_usec2ticks(unsigned long usec)
226 { 229 {
227 /* timer set to 1kHz ==> 1 clk tick = 1 msec */ 230 if (usec < US_PER_TICK)
228 if (usec < 1000)
229 return 1; 231 return 1;
230 return (usec / 1000); 232 return usec / US_PER_TICK;
231 } 233 }
232 234
233 unsigned long cpu_ticks2usec(unsigned long ticks) 235 unsigned long cpu_ticks2usec(unsigned long ticks)
234 { 236 {
235 /* 1tick = 1usec */ 237 return ticks * US_PER_TICK;
236 return ticks * 1000;