Eric Lee / smarc-uboot

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Commit 1f3aebcd52850235a29065c6a1d364907c5f9c80

Authored by Ye Li
1 parent cb72301d65
Exists in smarc_8mq-imx_v2020.04_5.4.24_2.1.0 and in 1 other branch smarc_8mm-imx_v2020.04_5.4.24_2.1.0

MLK-23820 imx8mq/mm: Add config to support secondary image boot 

When primary image boot is failed, ROM will select secondary image to
boot if SIT (secondary image table) exists. However, SPL does not know
the secondary boot, still loads the FIT from the position of primary image.

Introduce a config to add secondary image sector offset to FIT sector
offset. This config is default set to 0. Secondary image should configure
it to the same value of firstSectorNumber field in SIT.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 665972355dfe8156b3aa7bce52845722b15d9922)

Showing 5 changed files with 13 additions and 4 deletions Inline Diff

arch/arm/mach-imx/imx8m/Kconfig
Diff comments   View file @ 1f3aebc
1 if ARCH_IMX8M 1 if ARCH_IMX8M
2 2
3 config IMX8M 3 config IMX8M
4 bool 4 bool
5 select HAS_CAAM 5 select HAS_CAAM
6 select ROM_UNIFIED_SECTIONS 6 select ROM_UNIFIED_SECTIONS
7 7
8 config IMX8MQ 8 config IMX8MQ
9 bool 9 bool
10 select IMX8M 10 select IMX8M
11 select ARMV8_SPL_EXCEPTION_VECTORS 11 select ARMV8_SPL_EXCEPTION_VECTORS
12 12
13 config IMX8MM 13 config IMX8MM
14 bool 14 bool
15 select IMX8M 15 select IMX8M
16 select ARMV8_SPL_EXCEPTION_VECTORS 16 select ARMV8_SPL_EXCEPTION_VECTORS
17 17
18 config IMX8MN 18 config IMX8MN
19 bool 19 bool
20 select IMX8M 20 select IMX8M
21 select ARMV8_SPL_EXCEPTION_VECTORS 21 select ARMV8_SPL_EXCEPTION_VECTORS
22 22
23 config IMX8MP 23 config IMX8MP
24 bool 24 bool
25 select IMX8M 25 select IMX8M
26 26
27 config SYS_SOC 27 config SYS_SOC
28 default "imx8m" 28 default "imx8m"
29 29
30 config SECONDARY_BOOT_SECTOR_OFFSET
31 hex "SD/MMC sector offset used for ROM secondary boot"
32 default 0x0
33 depends on IMX8MQ || IMX8MM
34 help
35 Set the sector offset to non-zero value in SPL used for
36 secondary boot image. This value should be same as the
37 firstSectorNumber in secondary image table.
38
30 config SECURE_STICKY_BITS_LOCKUP 39 config SECURE_STICKY_BITS_LOCKUP
31 bool "Enable workaround to fix sticky bits lock up issue" 40 bool "Enable workaround to fix sticky bits lock up issue"
32 depends on IMX8MQ && IMX_HAB 41 depends on IMX8MQ && IMX_HAB
33 default y 42 default y
34 43
35 config IMX_UNIQUE_ID 44 config IMX_UNIQUE_ID
36 hex "Enable workaround to fix sticky bits lock up issue" 45 hex "Enable workaround to fix sticky bits lock up issue"
37 depends on IMX8MQ && IMX_HAB && !SECURE_STICKY_BITS_LOCKUP 46 depends on IMX8MQ && IMX_HAB && !SECURE_STICKY_BITS_LOCKUP
38 default 0x0 47 default 0x0
39 48
40 choice 49 choice
41 prompt "NXP i.MX8M board select" 50 prompt "NXP i.MX8M board select"
42 optional 51 optional
43 52
44 config TARGET_IMX8MQ_EVK 53 config TARGET_IMX8MQ_EVK
45 bool "imx8mq_evk" 54 bool "imx8mq_evk"
46 select IMX8MQ 55 select IMX8MQ
47 select IMX8M_LPDDR4 56 select IMX8M_LPDDR4
48 57
49 config TARGET_IMX8MQ_DDR3L_VAL 58 config TARGET_IMX8MQ_DDR3L_VAL
50 bool "imx8mq_ddr3l_val" 59 bool "imx8mq_ddr3l_val"
51 select IMX8MQ 60 select IMX8MQ
52 61
53 config TARGET_IMX8MQ_DDR4_VAL 62 config TARGET_IMX8MQ_DDR4_VAL
54 bool "imx8mq_ddr4_val" 63 bool "imx8mq_ddr4_val"
55 select IMX8MQ 64 select IMX8MQ
56 65
57 config TARGET_IMX8MM_DDR4_VAL 66 config TARGET_IMX8MM_DDR4_VAL
58 bool "imx8mm DDR4 validation board" 67 bool "imx8mm DDR4 validation board"
59 select IMX8MM 68 select IMX8MM
60 select SUPPORT_SPL 69 select SUPPORT_SPL
61 select IMX8M_DDR4 70 select IMX8M_DDR4
62 71
63 config TARGET_IMX8MM_DDR3L_VAL 72 config TARGET_IMX8MM_DDR3L_VAL
64 bool "imx8mm DDR3L validation board" 73 bool "imx8mm DDR3L validation board"
65 select IMX8MM 74 select IMX8MM
66 select SUPPORT_SPL 75 select SUPPORT_SPL
67 select IMX8M_DDR3L 76 select IMX8M_DDR3L
68 77
69 config TARGET_IMX8MM_EVK 78 config TARGET_IMX8MM_EVK
70 bool "imx8mm LPDDR4 EVK board" 79 bool "imx8mm LPDDR4 EVK board"
71 select IMX8MM 80 select IMX8MM
72 select SUPPORT_SPL 81 select SUPPORT_SPL
73 select IMX8M_LPDDR4 82 select IMX8M_LPDDR4
74 83
75 config TARGET_IMX8MM_DDR4_EVK 84 config TARGET_IMX8MM_DDR4_EVK
76 bool "imx8mm DDR4 EVK board" 85 bool "imx8mm DDR4 EVK board"
77 select IMX8MM 86 select IMX8MM
78 select SUPPORT_SPL 87 select SUPPORT_SPL
79 select IMX8M_DDR4 88 select IMX8M_DDR4
80 89
81 config TARGET_IMX8MN_EVK 90 config TARGET_IMX8MN_EVK
82 bool "imx8mn LPDDR4 EVK board" 91 bool "imx8mn LPDDR4 EVK board"
83 select IMX8MN 92 select IMX8MN
84 select SUPPORT_SPL 93 select SUPPORT_SPL
85 select IMX8M_LPDDR4 94 select IMX8M_LPDDR4
86 95
87 config TARGET_IMX8MN_DDR4_EVK 96 config TARGET_IMX8MN_DDR4_EVK
88 bool "imx8mn DDR4 EVK board" 97 bool "imx8mn DDR4 EVK board"
89 select IMX8MN 98 select IMX8MN
90 select SUPPORT_SPL 99 select SUPPORT_SPL
91 select IMX8M_DDR4 100 select IMX8M_DDR4
92 101
93 config TARGET_IMX8MP_EVK 102 config TARGET_IMX8MP_EVK
94 bool "imx8mp LPDDR4 EVK board" 103 bool "imx8mp LPDDR4 EVK board"
95 select IMX8MP 104 select IMX8MP
96 select SUPPORT_SPL 105 select SUPPORT_SPL
97 select IMX8M_LPDDR4 106 select IMX8M_LPDDR4
98 107
99 config TARGET_IMX8MM_AB2 108 config TARGET_IMX8MM_AB2
100 bool "imx8mm LPDDR4 Audio board 2.0" 109 bool "imx8mm LPDDR4 Audio board 2.0"
101 select IMX8MM 110 select IMX8MM
102 select SUPPORT_SPL 111 select SUPPORT_SPL
103 select IMX8M_LPDDR4 112 select IMX8M_LPDDR4
104 113
105 config TARGET_IMX8MN_AB2 114 config TARGET_IMX8MN_AB2
106 bool "imx8mn LPDDR4 Audio board 2.0" 115 bool "imx8mn LPDDR4 Audio board 2.0"
107 select IMX8MN 116 select IMX8MN
108 select SUPPORT_SPL 117 select SUPPORT_SPL
109 select IMX8M_LPDDR4 118 select IMX8M_LPDDR4
110 119
111 config TARGET_IMX8MN_DDR4_AB2 120 config TARGET_IMX8MN_DDR4_AB2
112 bool "imx8mn DDR4 Audio board 2.0" 121 bool "imx8mn DDR4 Audio board 2.0"
113 select IMX8MN 122 select IMX8MN
114 select SUPPORT_SPL 123 select SUPPORT_SPL
115 select IMX8M_DDR4 124 select IMX8M_DDR4
116 125
117 config TARGET_VERDIN_IMX8MM 126 config TARGET_VERDIN_IMX8MM
118 bool "Support Toradex Verdin iMX8M Mini module" 127 bool "Support Toradex Verdin iMX8M Mini module"
119 select IMX8MM 128 select IMX8MM
120 select SUPPORT_SPL 129 select SUPPORT_SPL
121 select IMX8M_LPDDR4 130 select IMX8M_LPDDR4
122 131
123 endchoice 132 endchoice
124 133
125 source "board/freescale/imx8mq_evk/Kconfig" 134 source "board/freescale/imx8mq_evk/Kconfig"
126 source "board/freescale/imx8mq_val/Kconfig" 135 source "board/freescale/imx8mq_val/Kconfig"
127 source "board/freescale/imx8mm_ab2/Kconfig" 136 source "board/freescale/imx8mm_ab2/Kconfig"
128 source "board/freescale/imx8mm_evk/Kconfig" 137 source "board/freescale/imx8mm_evk/Kconfig"
129 source "board/freescale/imx8mm_val/Kconfig" 138 source "board/freescale/imx8mm_val/Kconfig"
130 source "board/freescale/imx8mn_evk/Kconfig" 139 source "board/freescale/imx8mn_evk/Kconfig"
131 source "board/freescale/imx8mp_evk/Kconfig" 140 source "board/freescale/imx8mp_evk/Kconfig"
132 source "board/toradex/verdin-imx8mm/Kconfig" 141 source "board/toradex/verdin-imx8mm/Kconfig"
133 142
134 endif 143 endif
135 144
include/configs/imx8mm_evk.h
Diff comments   View file @ 1f3aebc
1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 #ifndef __IMX8MM_EVK_H 6 #ifndef __IMX8MM_EVK_H
7 #define __IMX8MM_EVK_H 7 #define __IMX8MM_EVK_H
8 8
9 #include <linux/sizes.h> 9 #include <linux/sizes.h>
10 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/imx-regs.h>
11 #include "imx_env.h" 11 #include "imx_env.h"
12 12
13 #define CONFIG_SPL_MAX_SIZE (148 * 1024) 13 #define CONFIG_SPL_MAX_SIZE (148 * 1024)
14 #define CONFIG_SYS_MONITOR_LEN SZ_512K 14 #define CONFIG_SYS_MONITOR_LEN SZ_512K
15 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR 15 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
16 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 16 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (0x300 + CONFIG_SECONDARY_BOOT_SECTOR_OFFSET)
17 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 17 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
18 #define CONFIG_SYS_UBOOT_BASE \ 18 #define CONFIG_SYS_UBOOT_BASE \
19 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) 19 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
20 20
21 #ifdef CONFIG_SPL_BUILD 21 #ifdef CONFIG_SPL_BUILD
22 #define CONFIG_SPL_STACK 0x920000 22 #define CONFIG_SPL_STACK 0x920000
23 #define CONFIG_SPL_BSS_START_ADDR 0x910000 23 #define CONFIG_SPL_BSS_START_ADDR 0x910000
24 #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ 24 #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
25 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 25 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
26 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ 26 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
27 27
28 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ 28 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
29 #define CONFIG_MALLOC_F_ADDR 0x912000 29 #define CONFIG_MALLOC_F_ADDR 0x912000
30 /* For RAW image gives a error info not panic */ 30 /* For RAW image gives a error info not panic */
31 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE 31 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
32 32
33 #define CONFIG_POWER 33 #define CONFIG_POWER
34 #define CONFIG_POWER_I2C 34 #define CONFIG_POWER_I2C
35 #define CONFIG_POWER_BD71837 35 #define CONFIG_POWER_BD71837
36 36
37 #define CONFIG_SYS_I2C 37 #define CONFIG_SYS_I2C
38 38
39 #if defined(CONFIG_NAND_BOOT) 39 #if defined(CONFIG_NAND_BOOT)
40 #define CONFIG_SPL_NAND_SUPPORT 40 #define CONFIG_SPL_NAND_SUPPORT
41 #define CONFIG_SPL_DMA 41 #define CONFIG_SPL_DMA
42 #define CONFIG_SPL_NAND_MXS 42 #define CONFIG_SPL_NAND_MXS
43 #define CONFIG_SPL_NAND_BASE 43 #define CONFIG_SPL_NAND_BASE
44 #define CONFIG_SPL_NAND_IDENT 44 #define CONFIG_SPL_NAND_IDENT
45 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */ 45 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */
46 46
47 /* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */ 47 /* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
48 #define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \ 48 #define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
49 (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400) 49 (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
50 #endif 50 #endif
51 51
52 #endif 52 #endif
53 53
54 #define CONFIG_CMD_READ 54 #define CONFIG_CMD_READ
55 #define CONFIG_SERIAL_TAG 55 #define CONFIG_SERIAL_TAG
56 #define CONFIG_FASTBOOT_USB_DEV 0 56 #define CONFIG_FASTBOOT_USB_DEV 0
57 57
58 #define CONFIG_REMAKE_ELF 58 #define CONFIG_REMAKE_ELF
59 /* ENET Config */ 59 /* ENET Config */
60 /* ENET1 */ 60 /* ENET1 */
61 #if defined(CONFIG_FEC_MXC) 61 #if defined(CONFIG_FEC_MXC)
62 #define CONFIG_ETHPRIME "FEC" 62 #define CONFIG_ETHPRIME "FEC"
63 #define PHY_ANEG_TIMEOUT 20000 63 #define PHY_ANEG_TIMEOUT 20000
64 64
65 #define CONFIG_FEC_XCV_TYPE RGMII 65 #define CONFIG_FEC_XCV_TYPE RGMII
66 #define CONFIG_FEC_MXC_PHYADDR 0 66 #define CONFIG_FEC_MXC_PHYADDR 0
67 #define FEC_QUIRK_ENET_MAC 67 #define FEC_QUIRK_ENET_MAC
68 68
69 #define IMX_FEC_BASE 0x30BE0000 69 #define IMX_FEC_BASE 0x30BE0000
70 #endif 70 #endif
71 71
72 #ifdef CONFIG_NAND_BOOT 72 #ifdef CONFIG_NAND_BOOT
73 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)" 73 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)"
74 #endif 74 #endif
75 75
76 /* 76 /*
77 * Another approach is add the clocks for inmates into clks_init_on 77 * Another approach is add the clocks for inmates into clks_init_on
78 * in clk-imx8mm.c, then clk_ingore_unused could be removed. 78 * in clk-imx8mm.c, then clk_ingore_unused could be removed.
79 */ 79 */
80 #define JAILHOUSE_ENV \ 80 #define JAILHOUSE_ENV \
81 "jh_clk= \0 " \ 81 "jh_clk= \0 " \
82 "jh_mmcboot=mw 0x303d0518 0xff; setenv fdt_file imx8mm-evk-root.dtb;" \ 82 "jh_mmcboot=mw 0x303d0518 0xff; setenv fdt_file imx8mm-evk-root.dtb;" \
83 "setenv jh_clk clk_ignore_unused; " \ 83 "setenv jh_clk clk_ignore_unused; " \
84 "if run loadimage; then " \ 84 "if run loadimage; then " \
85 "run mmcboot; " \ 85 "run mmcboot; " \
86 "else run jh_netboot; fi; \0" \ 86 "else run jh_netboot; fi; \0" \
87 "jh_netboot=mw 0x303d0518 0xff; setenv fdt_file imx8mm-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 " 87 "jh_netboot=mw 0x303d0518 0xff; setenv fdt_file imx8mm-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 "
88 88
89 89
90 #define CONFIG_MFG_ENV_SETTINGS \ 90 #define CONFIG_MFG_ENV_SETTINGS \
91 CONFIG_MFG_ENV_SETTINGS_DEFAULT \ 91 CONFIG_MFG_ENV_SETTINGS_DEFAULT \
92 "initrd_addr=0x43800000\0" \ 92 "initrd_addr=0x43800000\0" \
93 "initrd_high=0xffffffffffffffff\0" \ 93 "initrd_high=0xffffffffffffffff\0" \
94 "emmc_dev=2\0"\ 94 "emmc_dev=2\0"\
95 "sd_dev=1\0" \ 95 "sd_dev=1\0" \
96 96
97 /* Initial environment variables */ 97 /* Initial environment variables */
98 #if defined(CONFIG_NAND_BOOT) 98 #if defined(CONFIG_NAND_BOOT)
99 #define CONFIG_EXTRA_ENV_SETTINGS \ 99 #define CONFIG_EXTRA_ENV_SETTINGS \
100 CONFIG_MFG_ENV_SETTINGS \ 100 CONFIG_MFG_ENV_SETTINGS \
101 "splashimage=0x50000000\0" \ 101 "splashimage=0x50000000\0" \
102 "fdt_addr=0x43000000\0" \ 102 "fdt_addr=0x43000000\0" \
103 "fdt_high=0xffffffffffffffff\0" \ 103 "fdt_high=0xffffffffffffffff\0" \
104 "mtdparts=" MFG_NAND_PARTITION "\0" \ 104 "mtdparts=" MFG_NAND_PARTITION "\0" \
105 "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ 105 "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
106 "bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=nandrootfs " \ 106 "bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=nandrootfs " \
107 "root=ubi0:nandrootfs rootfstype=ubifs " \ 107 "root=ubi0:nandrootfs rootfstype=ubifs " \
108 MFG_NAND_PARTITION \ 108 MFG_NAND_PARTITION \
109 "\0" \ 109 "\0" \
110 "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\ 110 "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\
111 "nand read ${fdt_addr} 0x7000000 0x100000;"\ 111 "nand read ${fdt_addr} 0x7000000 0x100000;"\
112 "booti ${loadaddr} - ${fdt_addr}" 112 "booti ${loadaddr} - ${fdt_addr}"
113 113
114 #else 114 #else
115 #define CONFIG_EXTRA_ENV_SETTINGS \ 115 #define CONFIG_EXTRA_ENV_SETTINGS \
116 CONFIG_MFG_ENV_SETTINGS \ 116 CONFIG_MFG_ENV_SETTINGS \
117 JAILHOUSE_ENV \ 117 JAILHOUSE_ENV \
118 "script=boot.scr\0" \ 118 "script=boot.scr\0" \
119 "image=Image\0" \ 119 "image=Image\0" \
120 "splashimage=0x50000000\0" \ 120 "splashimage=0x50000000\0" \
121 "console=ttymxc1,115200\0" \ 121 "console=ttymxc1,115200\0" \
122 "fdt_addr=0x43000000\0" \ 122 "fdt_addr=0x43000000\0" \
123 "fdt_high=0xffffffffffffffff\0" \ 123 "fdt_high=0xffffffffffffffff\0" \
124 "boot_fit=no\0" \ 124 "boot_fit=no\0" \
125 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ 125 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
126 "initrd_addr=0x43800000\0" \ 126 "initrd_addr=0x43800000\0" \
127 "initrd_high=0xffffffffffffffff\0" \ 127 "initrd_high=0xffffffffffffffff\0" \
128 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ 128 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
129 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ 129 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
130 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 130 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
131 "mmcautodetect=yes\0" \ 131 "mmcautodetect=yes\0" \
132 "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ 132 "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
133 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 133 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
134 "bootscript=echo Running bootscript from mmc ...; " \ 134 "bootscript=echo Running bootscript from mmc ...; " \
135 "source\0" \ 135 "source\0" \
136 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 136 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
137 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 137 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
138 "mmcboot=echo Booting from mmc ...; " \ 138 "mmcboot=echo Booting from mmc ...; " \
139 "run mmcargs; " \ 139 "run mmcargs; " \
140 "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ 140 "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
141 "bootm ${loadaddr}; " \ 141 "bootm ${loadaddr}; " \
142 "else " \ 142 "else " \
143 "if run loadfdt; then " \ 143 "if run loadfdt; then " \
144 "booti ${loadaddr} - ${fdt_addr}; " \ 144 "booti ${loadaddr} - ${fdt_addr}; " \
145 "else " \ 145 "else " \
146 "echo WARN: Cannot load the DT; " \ 146 "echo WARN: Cannot load the DT; " \
147 "fi; " \ 147 "fi; " \
148 "fi;\0" \ 148 "fi;\0" \
149 "netargs=setenv bootargs ${jh_clk} console=${console} " \ 149 "netargs=setenv bootargs ${jh_clk} console=${console} " \
150 "root=/dev/nfs " \ 150 "root=/dev/nfs " \
151 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 151 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
152 "netboot=echo Booting from net ...; " \ 152 "netboot=echo Booting from net ...; " \
153 "run netargs; " \ 153 "run netargs; " \
154 "if test ${ip_dyn} = yes; then " \ 154 "if test ${ip_dyn} = yes; then " \
155 "setenv get_cmd dhcp; " \ 155 "setenv get_cmd dhcp; " \
156 "else " \ 156 "else " \
157 "setenv get_cmd tftp; " \ 157 "setenv get_cmd tftp; " \
158 "fi; " \ 158 "fi; " \
159 "${get_cmd} ${loadaddr} ${image}; " \ 159 "${get_cmd} ${loadaddr} ${image}; " \
160 "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ 160 "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
161 "bootm ${loadaddr}; " \ 161 "bootm ${loadaddr}; " \
162 "else " \ 162 "else " \
163 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 163 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
164 "booti ${loadaddr} - ${fdt_addr}; " \ 164 "booti ${loadaddr} - ${fdt_addr}; " \
165 "else " \ 165 "else " \
166 "echo WARN: Cannot load the DT; " \ 166 "echo WARN: Cannot load the DT; " \
167 "fi; " \ 167 "fi; " \
168 "fi;\0" 168 "fi;\0"
169 169
170 #define CONFIG_BOOTCOMMAND \ 170 #define CONFIG_BOOTCOMMAND \
171 "mmc dev ${mmcdev}; if mmc rescan; then " \ 171 "mmc dev ${mmcdev}; if mmc rescan; then " \
172 "if run loadbootscript; then " \ 172 "if run loadbootscript; then " \
173 "run bootscript; " \ 173 "run bootscript; " \
174 "else " \ 174 "else " \
175 "if run loadimage; then " \ 175 "if run loadimage; then " \
176 "run mmcboot; " \ 176 "run mmcboot; " \
177 "else run netboot; " \ 177 "else run netboot; " \
178 "fi; " \ 178 "fi; " \
179 "fi; " \ 179 "fi; " \
180 "fi;" 180 "fi;"
181 #endif 181 #endif
182 182
183 /* Link Definitions */ 183 /* Link Definitions */
184 #define CONFIG_LOADADDR 0x40480000 184 #define CONFIG_LOADADDR 0x40480000
185 185
186 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 186 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
187 187
188 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 188 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
189 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 189 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000
190 #define CONFIG_SYS_INIT_SP_OFFSET \ 190 #define CONFIG_SYS_INIT_SP_OFFSET \
191 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 191 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
192 #define CONFIG_SYS_INIT_SP_ADDR \ 192 #define CONFIG_SYS_INIT_SP_ADDR \
193 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 193 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
194 194
195 #define CONFIG_ENV_OVERWRITE 195 #define CONFIG_ENV_OVERWRITE
196 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) 196 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
197 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 197 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
198 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 198 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
199 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 199 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
200 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 200 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
201 #endif 201 #endif
202 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ 202 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
203 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ 203 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
204 204
205 /* Size of malloc() pool */ 205 /* Size of malloc() pool */
206 #define CONFIG_SYS_MALLOC_LEN SZ_32M 206 #define CONFIG_SYS_MALLOC_LEN SZ_32M
207 207
208 #define CONFIG_SYS_SDRAM_BASE 0x40000000 208 #define CONFIG_SYS_SDRAM_BASE 0x40000000
209 #define PHYS_SDRAM 0x40000000 209 #define PHYS_SDRAM 0x40000000
210 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ 210 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
211 211
212 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 212 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
213 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) 213 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
214 214
215 #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR 215 #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
216 216
217 /* Monitor Command Prompt */ 217 /* Monitor Command Prompt */
218 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 218 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
219 #define CONFIG_SYS_CBSIZE 2048 219 #define CONFIG_SYS_CBSIZE 2048
220 #define CONFIG_SYS_MAXARGS 64 220 #define CONFIG_SYS_MAXARGS 64
221 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 221 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
222 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 222 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
223 sizeof(CONFIG_SYS_PROMPT) + 16) 223 sizeof(CONFIG_SYS_PROMPT) + 16)
224 224
225 #define CONFIG_IMX_BOOTAUX 225 #define CONFIG_IMX_BOOTAUX
226 226
227 /* USDHC */ 227 /* USDHC */
228 #define CONFIG_FSL_USDHC 228 #define CONFIG_FSL_USDHC
229 229
230 #ifdef CONFIG_TARGET_IMX8MM_DDR4_EVK 230 #ifdef CONFIG_TARGET_IMX8MM_DDR4_EVK
231 #define CONFIG_SYS_FSL_USDHC_NUM 1 231 #define CONFIG_SYS_FSL_USDHC_NUM 1
232 #else 232 #else
233 #define CONFIG_SYS_FSL_USDHC_NUM 2 233 #define CONFIG_SYS_FSL_USDHC_NUM 2
234 #endif 234 #endif
235 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 235 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
236 236
237 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 237 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
238 238
239 #ifdef CONFIG_FSL_FSPI 239 #ifdef CONFIG_FSL_FSPI
240 #define FSL_FSPI_FLASH_SIZE SZ_32M 240 #define FSL_FSPI_FLASH_SIZE SZ_32M
241 #define FSL_FSPI_FLASH_NUM 1 241 #define FSL_FSPI_FLASH_NUM 1
242 #define FSPI0_BASE_ADDR 0x30bb0000 242 #define FSPI0_BASE_ADDR 0x30bb0000
243 #define FSPI0_AMBA_BASE 0x0 243 #define FSPI0_AMBA_BASE 0x0
244 #define CONFIG_FSPI_QUAD_SUPPORT 244 #define CONFIG_FSPI_QUAD_SUPPORT
245 245
246 #define CONFIG_SYS_FSL_FSPI_AHB 246 #define CONFIG_SYS_FSL_FSPI_AHB
247 #endif 247 #endif
248 248
249 #ifdef CONFIG_NAND_MXS 249 #ifdef CONFIG_NAND_MXS
250 #define CONFIG_CMD_NAND_TRIMFFS 250 #define CONFIG_CMD_NAND_TRIMFFS
251 251
252 /* NAND stuff */ 252 /* NAND stuff */
253 #define CONFIG_SYS_MAX_NAND_DEVICE 1 253 #define CONFIG_SYS_MAX_NAND_DEVICE 1
254 #define CONFIG_SYS_NAND_BASE 0x20000000 254 #define CONFIG_SYS_NAND_BASE 0x20000000
255 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 255 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
256 #define CONFIG_SYS_NAND_ONFI_DETECTION 256 #define CONFIG_SYS_NAND_ONFI_DETECTION
257 #define CONFIG_SYS_NAND_USE_FLASH_BBT 257 #define CONFIG_SYS_NAND_USE_FLASH_BBT
258 #endif /* CONFIG_NAND_MXS */ 258 #endif /* CONFIG_NAND_MXS */
259 259
260 #define CONFIG_SYS_I2C_SPEED 100000 260 #define CONFIG_SYS_I2C_SPEED 100000
261 261
262 /* USB configs */ 262 /* USB configs */
263 #ifndef CONFIG_SPL_BUILD 263 #ifndef CONFIG_SPL_BUILD
264 #define CONFIG_CMD_USB 264 #define CONFIG_CMD_USB
265 #define CONFIG_USB_STORAGE 265 #define CONFIG_USB_STORAGE
266 #define CONFIG_USBD_HS 266 #define CONFIG_USBD_HS
267 267
268 #define CONFIG_CMD_USB_MASS_STORAGE 268 #define CONFIG_CMD_USB_MASS_STORAGE
269 #define CONFIG_USB_GADGET_MASS_STORAGE 269 #define CONFIG_USB_GADGET_MASS_STORAGE
270 #define CONFIG_USB_FUNCTION_MASS_STORAGE 270 #define CONFIG_USB_FUNCTION_MASS_STORAGE
271 271
272 #endif 272 #endif
273 273
274 #define CONFIG_USB_GADGET_VBUS_DRAW 2 274 #define CONFIG_USB_GADGET_VBUS_DRAW 2
275 275
276 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 276 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
277 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 277 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
278 278
279 #ifdef CONFIG_DM_VIDEO 279 #ifdef CONFIG_DM_VIDEO
280 #define CONFIG_VIDEO_MXS 280 #define CONFIG_VIDEO_MXS
281 #define CONFIG_VIDEO_LOGO 281 #define CONFIG_VIDEO_LOGO
282 #define CONFIG_SPLASH_SCREEN 282 #define CONFIG_SPLASH_SCREEN
283 #define CONFIG_SPLASH_SCREEN_ALIGN 283 #define CONFIG_SPLASH_SCREEN_ALIGN
284 #define CONFIG_CMD_BMP 284 #define CONFIG_CMD_BMP
285 #define CONFIG_BMP_16BPP 285 #define CONFIG_BMP_16BPP
286 #define CONFIG_BMP_24BPP 286 #define CONFIG_BMP_24BPP
287 #define CONFIG_BMP_32BPP 287 #define CONFIG_BMP_32BPP
288 #define CONFIG_VIDEO_BMP_RLE8 288 #define CONFIG_VIDEO_BMP_RLE8
289 #define CONFIG_VIDEO_BMP_LOGO 289 #define CONFIG_VIDEO_BMP_LOGO
290 #endif 290 #endif
291 291
292 #if defined(CONFIG_ANDROID_SUPPORT) 292 #if defined(CONFIG_ANDROID_SUPPORT)
293 #include "imx8mm_evk_android.h" 293 #include "imx8mm_evk_android.h"
294 #endif 294 #endif
295 295
296 #endif 296 #endif
297 297
include/configs/imx8mm_val.h
Diff comments   View file @ 1f3aebc
1 /* 1 /*
2 * Copyright 2018 NXP 2 * Copyright 2018 NXP
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __IMX8MM_VAL_H 7 #ifndef __IMX8MM_VAL_H
8 #define __IMX8MM_VAL_H 8 #define __IMX8MM_VAL_H
9 9
10 #include <linux/sizes.h> 10 #include <linux/sizes.h>
11 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/imx-regs.h>
12 #include "imx_env.h" 12 #include "imx_env.h"
13 13
14 #define CONFIG_SPL_MAX_SIZE (148 * 1024) 14 #define CONFIG_SPL_MAX_SIZE (148 * 1024)
15 #define CONFIG_SYS_MONITOR_LEN SZ_512K 15 #define CONFIG_SYS_MONITOR_LEN SZ_512K
16 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR 16 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
17 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 17 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (0x300 + CONFIG_SECONDARY_BOOT_SECTOR_OFFSET)
18 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 18 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
19 #define CONFIG_SYS_UBOOT_BASE \ 19 #define CONFIG_SYS_UBOOT_BASE \
20 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) 20 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
21 21
22 #ifdef CONFIG_SPL_BUILD 22 #ifdef CONFIG_SPL_BUILD
23 #define CONFIG_SPL_STACK 0x920000 23 #define CONFIG_SPL_STACK 0x920000
24 #define CONFIG_SPL_BSS_START_ADDR 0x910000 24 #define CONFIG_SPL_BSS_START_ADDR 0x910000
25 #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ 25 #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
26 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 26 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
27 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ 27 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
28 28
29 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ 29 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
30 #define CONFIG_MALLOC_F_ADDR 0x912000 30 #define CONFIG_MALLOC_F_ADDR 0x912000
31 /* For RAW image gives a error info not panic */ 31 /* For RAW image gives a error info not panic */
32 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE 32 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
33 33
34 #define CONFIG_POWER 34 #define CONFIG_POWER
35 #define CONFIG_POWER_I2C 35 #define CONFIG_POWER_I2C
36 #define CONFIG_POWER_BD71837 36 #define CONFIG_POWER_BD71837
37 37
38 #define CONFIG_SYS_I2C 38 #define CONFIG_SYS_I2C
39 #endif 39 #endif
40 40
41 41
42 #define CONFIG_CMD_READ 42 #define CONFIG_CMD_READ
43 #define CONFIG_SERIAL_TAG 43 #define CONFIG_SERIAL_TAG
44 #define CONFIG_FASTBOOT_USB_DEV 0 44 #define CONFIG_FASTBOOT_USB_DEV 0
45 45
46 #define CONFIG_REMAKE_ELF 46 #define CONFIG_REMAKE_ELF
47 /* ENET Config */ 47 /* ENET Config */
48 /* ENET1 */ 48 /* ENET1 */
49 #if defined(CONFIG_FEC_MXC) 49 #if defined(CONFIG_FEC_MXC)
50 #define CONFIG_ETHPRIME "FEC" 50 #define CONFIG_ETHPRIME "FEC"
51 #define PHY_ANEG_TIMEOUT 20000 51 #define PHY_ANEG_TIMEOUT 20000
52 52
53 #define FEC_QUIRK_ENET_MAC 53 #define FEC_QUIRK_ENET_MAC
54 54
55 #define IMX_FEC_BASE 0x30BE0000 55 #define IMX_FEC_BASE 0x30BE0000
56 56
57 #ifdef CONFIG_TARGET_IMX8MM_DDR3L_VAL 57 #ifdef CONFIG_TARGET_IMX8MM_DDR3L_VAL
58 #define CONFIG_FEC_XCV_TYPE RMII 58 #define CONFIG_FEC_XCV_TYPE RMII
59 #define CONFIG_FEC_MXC_PHYADDR 3 59 #define CONFIG_FEC_MXC_PHYADDR 3
60 #else 60 #else
61 #define CONFIG_FEC_MXC_PHYADDR 0 61 #define CONFIG_FEC_MXC_PHYADDR 0
62 #define CONFIG_FEC_XCV_TYPE RGMII 62 #define CONFIG_FEC_XCV_TYPE RGMII
63 #endif 63 #endif
64 64
65 #endif 65 #endif
66 66
67 #define CONFIG_MFG_ENV_SETTINGS \ 67 #define CONFIG_MFG_ENV_SETTINGS \
68 CONFIG_MFG_ENV_SETTINGS_DEFAULT \ 68 CONFIG_MFG_ENV_SETTINGS_DEFAULT \
69 "initrd_addr=0x43800000\0" \ 69 "initrd_addr=0x43800000\0" \
70 "initrd_high=0xffffffffffffffff\0" \ 70 "initrd_high=0xffffffffffffffff\0" \
71 "emmc_dev=2\0"\ 71 "emmc_dev=2\0"\
72 "sd_dev=1\0" \ 72 "sd_dev=1\0" \
73 73
74 /* Initial environment variables */ 74 /* Initial environment variables */
75 #define CONFIG_EXTRA_ENV_SETTINGS \ 75 #define CONFIG_EXTRA_ENV_SETTINGS \
76 CONFIG_MFG_ENV_SETTINGS \ 76 CONFIG_MFG_ENV_SETTINGS \
77 "script=boot.scr\0" \ 77 "script=boot.scr\0" \
78 "image=Image\0" \ 78 "image=Image\0" \
79 "console=ttymxc1,115200\0" \ 79 "console=ttymxc1,115200\0" \
80 "fdt_addr=0x43000000\0" \ 80 "fdt_addr=0x43000000\0" \
81 "fdt_high=0xffffffffffffffff\0" \ 81 "fdt_high=0xffffffffffffffff\0" \
82 "boot_fdt=try\0" \ 82 "boot_fdt=try\0" \
83 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ 83 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
84 "initrd_addr=0x43800000\0" \ 84 "initrd_addr=0x43800000\0" \
85 "initrd_high=0xffffffffffffffff\0" \ 85 "initrd_high=0xffffffffffffffff\0" \
86 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ 86 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
87 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ 87 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
88 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 88 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
89 "mmcautodetect=yes\0" \ 89 "mmcautodetect=yes\0" \
90 "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ 90 "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
91 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 91 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
92 "bootscript=echo Running bootscript from mmc ...; " \ 92 "bootscript=echo Running bootscript from mmc ...; " \
93 "source\0" \ 93 "source\0" \
94 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 94 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
95 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 95 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
96 "mmcboot=echo Booting from mmc ...; " \ 96 "mmcboot=echo Booting from mmc ...; " \
97 "run mmcargs; " \ 97 "run mmcargs; " \
98 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 98 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
99 "if run loadfdt; then " \ 99 "if run loadfdt; then " \
100 "booti ${loadaddr} - ${fdt_addr}; " \ 100 "booti ${loadaddr} - ${fdt_addr}; " \
101 "else " \ 101 "else " \
102 "echo WARN: Cannot load the DT; " \ 102 "echo WARN: Cannot load the DT; " \
103 "fi; " \ 103 "fi; " \
104 "else " \ 104 "else " \
105 "echo wait for boot; " \ 105 "echo wait for boot; " \
106 "fi;\0" \ 106 "fi;\0" \
107 "netargs=setenv bootargs console=${console} " \ 107 "netargs=setenv bootargs console=${console} " \
108 "root=/dev/nfs " \ 108 "root=/dev/nfs " \
109 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 109 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
110 "netboot=echo Booting from net ...; " \ 110 "netboot=echo Booting from net ...; " \
111 "run netargs; " \ 111 "run netargs; " \
112 "if test ${ip_dyn} = yes; then " \ 112 "if test ${ip_dyn} = yes; then " \
113 "setenv get_cmd dhcp; " \ 113 "setenv get_cmd dhcp; " \
114 "else " \ 114 "else " \
115 "setenv get_cmd tftp; " \ 115 "setenv get_cmd tftp; " \
116 "fi; " \ 116 "fi; " \
117 "${get_cmd} ${loadaddr} ${image}; " \ 117 "${get_cmd} ${loadaddr} ${image}; " \
118 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 118 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
119 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 119 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
120 "booti ${loadaddr} - ${fdt_addr}; " \ 120 "booti ${loadaddr} - ${fdt_addr}; " \
121 "else " \ 121 "else " \
122 "echo WARN: Cannot load the DT; " \ 122 "echo WARN: Cannot load the DT; " \
123 "fi; " \ 123 "fi; " \
124 "else " \ 124 "else " \
125 "booti; " \ 125 "booti; " \
126 "fi;\0" 126 "fi;\0"
127 127
128 #define CONFIG_BOOTCOMMAND \ 128 #define CONFIG_BOOTCOMMAND \
129 "mmc dev ${mmcdev}; if mmc rescan; then " \ 129 "mmc dev ${mmcdev}; if mmc rescan; then " \
130 "if run loadbootscript; then " \ 130 "if run loadbootscript; then " \
131 "run bootscript; " \ 131 "run bootscript; " \
132 "else " \ 132 "else " \
133 "if run loadimage; then " \ 133 "if run loadimage; then " \
134 "run mmcboot; " \ 134 "run mmcboot; " \
135 "else run netboot; " \ 135 "else run netboot; " \
136 "fi; " \ 136 "fi; " \
137 "fi; " \ 137 "fi; " \
138 "else booti ${loadaddr} - ${fdt_addr}; fi" 138 "else booti ${loadaddr} - ${fdt_addr}; fi"
139 139
140 /* Link Definitions */ 140 /* Link Definitions */
141 #define CONFIG_LOADADDR 0x40480000 141 #define CONFIG_LOADADDR 0x40480000
142 142
143 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 143 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
144 144
145 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 145 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
146 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 146 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
147 #define CONFIG_SYS_INIT_SP_OFFSET \ 147 #define CONFIG_SYS_INIT_SP_OFFSET \
148 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 148 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
149 #define CONFIG_SYS_INIT_SP_ADDR \ 149 #define CONFIG_SYS_INIT_SP_ADDR \
150 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 150 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
151 151
152 #define CONFIG_ENV_OVERWRITE 152 #define CONFIG_ENV_OVERWRITE
153 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) 153 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
154 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 154 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
155 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 155 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
156 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 156 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
157 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 157 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
158 #endif 158 #endif
159 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ 159 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
160 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ 160 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
161 161
162 /* Size of malloc() pool */ 162 /* Size of malloc() pool */
163 #define CONFIG_SYS_MALLOC_LEN SZ_32M 163 #define CONFIG_SYS_MALLOC_LEN SZ_32M
164 164
165 #define CONFIG_SYS_SDRAM_BASE 0x40000000 165 #define CONFIG_SYS_SDRAM_BASE 0x40000000
166 #define PHYS_SDRAM 0x40000000 166 #define PHYS_SDRAM 0x40000000
167 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ 167 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
168 168
169 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 169 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
170 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) 170 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
171 171
172 #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR 172 #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
173 173
174 /* Monitor Command Prompt */ 174 /* Monitor Command Prompt */
175 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 175 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
176 #define CONFIG_SYS_CBSIZE 2048 176 #define CONFIG_SYS_CBSIZE 2048
177 #define CONFIG_SYS_MAXARGS 64 177 #define CONFIG_SYS_MAXARGS 64
178 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 178 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
179 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 179 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
180 sizeof(CONFIG_SYS_PROMPT) + 16) 180 sizeof(CONFIG_SYS_PROMPT) + 16)
181 181
182 #define CONFIG_IMX_BOOTAUX 182 #define CONFIG_IMX_BOOTAUX
183 183
184 /* USDHC */ 184 /* USDHC */
185 #define CONFIG_FSL_USDHC 185 #define CONFIG_FSL_USDHC
186 186
187 #ifdef CONFIG_TARGET_IMX8MM_DDR3L_VAL 187 #ifdef CONFIG_TARGET_IMX8MM_DDR3L_VAL
188 #define CONFIG_SYS_FSL_USDHC_NUM 1 188 #define CONFIG_SYS_FSL_USDHC_NUM 1
189 #else 189 #else
190 #define CONFIG_SYS_FSL_USDHC_NUM 2 190 #define CONFIG_SYS_FSL_USDHC_NUM 2
191 #endif 191 #endif
192 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 192 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
193 193
194 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 194 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
195 195
196 #ifdef CONFIG_FSL_FSPI 196 #ifdef CONFIG_FSL_FSPI
197 #define FSL_FSPI_FLASH_SIZE SZ_32M 197 #define FSL_FSPI_FLASH_SIZE SZ_32M
198 #define FSL_FSPI_FLASH_NUM 1 198 #define FSL_FSPI_FLASH_NUM 1
199 #define FSPI0_BASE_ADDR 0x30bb0000 199 #define FSPI0_BASE_ADDR 0x30bb0000
200 #define FSPI0_AMBA_BASE 0x0 200 #define FSPI0_AMBA_BASE 0x0
201 #define CONFIG_FSPI_QUAD_SUPPORT 201 #define CONFIG_FSPI_QUAD_SUPPORT
202 202
203 #define CONFIG_SYS_FSL_FSPI_AHB 203 #define CONFIG_SYS_FSL_FSPI_AHB
204 #endif 204 #endif
205 205
206 #ifdef CONFIG_NAND_MXS 206 #ifdef CONFIG_NAND_MXS
207 #define CONFIG_CMD_NAND_TRIMFFS 207 #define CONFIG_CMD_NAND_TRIMFFS
208 208
209 /* NAND stuff */ 209 /* NAND stuff */
210 #define CONFIG_SYS_MAX_NAND_DEVICE 1 210 #define CONFIG_SYS_MAX_NAND_DEVICE 1
211 #define CONFIG_SYS_NAND_BASE 0x20000000 211 #define CONFIG_SYS_NAND_BASE 0x20000000
212 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 212 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
213 #define CONFIG_SYS_NAND_ONFI_DETECTION 213 #define CONFIG_SYS_NAND_ONFI_DETECTION
214 #define CONFIG_SYS_NAND_USE_FLASH_BBT 214 #define CONFIG_SYS_NAND_USE_FLASH_BBT
215 #endif /* CONFIG_NAND_MXS */ 215 #endif /* CONFIG_NAND_MXS */
216 216
217 #define CONFIG_SYS_I2C_SPEED 100000 217 #define CONFIG_SYS_I2C_SPEED 100000
218 218
219 /* USB configs */ 219 /* USB configs */
220 #ifndef CONFIG_SPL_BUILD 220 #ifndef CONFIG_SPL_BUILD
221 #define CONFIG_CMD_USB 221 #define CONFIG_CMD_USB
222 #define CONFIG_USB_STORAGE 222 #define CONFIG_USB_STORAGE
223 #define CONFIG_USBD_HS 223 #define CONFIG_USBD_HS
224 224
225 #define CONFIG_CMD_USB_MASS_STORAGE 225 #define CONFIG_CMD_USB_MASS_STORAGE
226 #define CONFIG_USB_GADGET_MASS_STORAGE 226 #define CONFIG_USB_GADGET_MASS_STORAGE
227 #define CONFIG_USB_FUNCTION_MASS_STORAGE 227 #define CONFIG_USB_FUNCTION_MASS_STORAGE
228 228
229 #endif 229 #endif
230 230
231 #define CONFIG_USB_GADGET_VBUS_DRAW 2 231 #define CONFIG_USB_GADGET_VBUS_DRAW 2
232 232
233 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 233 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
234 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 234 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
235 235
236 #endif 236 #endif
237 237
include/configs/imx8mq_evk.h
Diff comments   View file @ 1f3aebc
1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * Copyright 2018 NXP 3 * Copyright 2018 NXP
4 */ 4 */
5 5
6 #ifndef __IMX8M_EVK_H 6 #ifndef __IMX8M_EVK_H
7 #define __IMX8M_EVK_H 7 #define __IMX8M_EVK_H
8 8
9 #include <linux/sizes.h> 9 #include <linux/sizes.h>
10 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/imx-regs.h>
11 #include "imx_env.h" 11 #include "imx_env.h"
12 12
13 #define CONFIG_SPL_MAX_SIZE (148 * 1024) 13 #define CONFIG_SPL_MAX_SIZE (148 * 1024)
14 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 14 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
15 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR 15 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
16 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 16 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (0x300 + CONFIG_SECONDARY_BOOT_SECTOR_OFFSET)
17 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 17 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
18 18
19 #ifdef CONFIG_SPL_BUILD 19 #ifdef CONFIG_SPL_BUILD
20 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ 20 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
21 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 21 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
22 #define CONFIG_SPL_STACK 0x187FF0 22 #define CONFIG_SPL_STACK 0x187FF0
23 #define CONFIG_SPL_BSS_START_ADDR 0x00180000 23 #define CONFIG_SPL_BSS_START_ADDR 0x00180000
24 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ 24 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
25 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 25 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
26 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ 26 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
27 #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 27 #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
28 28
29 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ 29 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
30 #define CONFIG_MALLOC_F_ADDR 0x182000 30 #define CONFIG_MALLOC_F_ADDR 0x182000
31 /* For RAW image gives a error info not panic */ 31 /* For RAW image gives a error info not panic */
32 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE 32 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
33 33
34 #undef CONFIG_DM_MMC 34 #undef CONFIG_DM_MMC
35 #undef CONFIG_DM_PMIC 35 #undef CONFIG_DM_PMIC
36 #undef CONFIG_DM_PMIC_PFUZE100 36 #undef CONFIG_DM_PMIC_PFUZE100
37 37
38 #define CONFIG_SYS_I2C 38 #define CONFIG_SYS_I2C
39 39
40 #define CONFIG_POWER 40 #define CONFIG_POWER
41 #define CONFIG_POWER_I2C 41 #define CONFIG_POWER_I2C
42 #define CONFIG_POWER_PFUZE100 42 #define CONFIG_POWER_PFUZE100
43 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 43 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
44 #endif 44 #endif
45 45
46 #define CONFIG_REMAKE_ELF 46 #define CONFIG_REMAKE_ELF
47 47
48 /* ENET Config */ 48 /* ENET Config */
49 /* ENET1 */ 49 /* ENET1 */
50 #if defined(CONFIG_FEC_MXC) 50 #if defined(CONFIG_FEC_MXC)
51 #define CONFIG_ETHPRIME "FEC" 51 #define CONFIG_ETHPRIME "FEC"
52 #define PHY_ANEG_TIMEOUT 20000 52 #define PHY_ANEG_TIMEOUT 20000
53 53
54 #define CONFIG_FEC_XCV_TYPE RGMII 54 #define CONFIG_FEC_XCV_TYPE RGMII
55 #define CONFIG_FEC_MXC_PHYADDR 0 55 #define CONFIG_FEC_MXC_PHYADDR 0
56 #define FEC_QUIRK_ENET_MAC 56 #define FEC_QUIRK_ENET_MAC
57 57
58 #define IMX_FEC_BASE 0x30BE0000 58 #define IMX_FEC_BASE 0x30BE0000
59 #endif 59 #endif
60 60
61 /* 61 /*
62 * Another approach is add the clocks for inmates into clks_init_on 62 * Another approach is add the clocks for inmates into clks_init_on
63 * in clk-imx8mq.c, then clk_ingore_unused could be removed. 63 * in clk-imx8mq.c, then clk_ingore_unused could be removed.
64 */ 64 */
65 #define JAILHOUSE_ENV \ 65 #define JAILHOUSE_ENV \
66 "jh_clk= \0 " \ 66 "jh_clk= \0 " \
67 "jh_mmcboot=setenv fdt_file imx8mq-evk-root.dtb; " \ 67 "jh_mmcboot=setenv fdt_file imx8mq-evk-root.dtb; " \
68 "setenv jh_clk clk_ignore_unused; " \ 68 "setenv jh_clk clk_ignore_unused; " \
69 "if run loadimage; then " \ 69 "if run loadimage; then " \
70 "run mmcboot; " \ 70 "run mmcboot; " \
71 "else run jh_netboot; fi; \0" \ 71 "else run jh_netboot; fi; \0" \
72 "jh_netboot=setenv fdt_file imx8mq-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 " 72 "jh_netboot=setenv fdt_file imx8mq-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 "
73 73
74 #define CONFIG_MFG_ENV_SETTINGS \ 74 #define CONFIG_MFG_ENV_SETTINGS \
75 CONFIG_MFG_ENV_SETTINGS_DEFAULT \ 75 CONFIG_MFG_ENV_SETTINGS_DEFAULT \
76 "initrd_addr=0x43800000\0" \ 76 "initrd_addr=0x43800000\0" \
77 "initrd_high=0xffffffffffffffff\0" \ 77 "initrd_high=0xffffffffffffffff\0" \
78 "emmc_dev=0\0"\ 78 "emmc_dev=0\0"\
79 "sd_dev=1\0" \ 79 "sd_dev=1\0" \
80 80
81 /* Initial environment variables */ 81 /* Initial environment variables */
82 #define CONFIG_EXTRA_ENV_SETTINGS \ 82 #define CONFIG_EXTRA_ENV_SETTINGS \
83 CONFIG_MFG_ENV_SETTINGS \ 83 CONFIG_MFG_ENV_SETTINGS \
84 JAILHOUSE_ENV \ 84 JAILHOUSE_ENV \
85 "script=boot.scr\0" \ 85 "script=boot.scr\0" \
86 "image=Image\0" \ 86 "image=Image\0" \
87 "splashimage=0x50000000\0" \ 87 "splashimage=0x50000000\0" \
88 "console=ttymxc0,115200\0" \ 88 "console=ttymxc0,115200\0" \
89 "fdt_addr=0x43000000\0" \ 89 "fdt_addr=0x43000000\0" \
90 "fdt_high=0xffffffffffffffff\0" \ 90 "fdt_high=0xffffffffffffffff\0" \
91 "boot_fdt=try\0" \ 91 "boot_fdt=try\0" \
92 "fdt_file=imx8mq-evk.dtb\0" \ 92 "fdt_file=imx8mq-evk.dtb\0" \
93 "initrd_addr=0x43800000\0" \ 93 "initrd_addr=0x43800000\0" \
94 "initrd_high=0xffffffffffffffff\0" \ 94 "initrd_high=0xffffffffffffffff\0" \
95 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ 95 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
96 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ 96 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
97 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 97 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
98 "mmcautodetect=yes\0" \ 98 "mmcautodetect=yes\0" \
99 "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ 99 "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
100 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 100 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
101 "bootscript=echo Running bootscript from mmc ...; " \ 101 "bootscript=echo Running bootscript from mmc ...; " \
102 "source\0" \ 102 "source\0" \
103 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 103 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
104 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 104 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
105 "mmcboot=echo Booting from mmc ...; " \ 105 "mmcboot=echo Booting from mmc ...; " \
106 "run mmcargs; " \ 106 "run mmcargs; " \
107 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 107 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
108 "if run loadfdt; then " \ 108 "if run loadfdt; then " \
109 "booti ${loadaddr} - ${fdt_addr}; " \ 109 "booti ${loadaddr} - ${fdt_addr}; " \
110 "else " \ 110 "else " \
111 "echo WARN: Cannot load the DT; " \ 111 "echo WARN: Cannot load the DT; " \
112 "fi; " \ 112 "fi; " \
113 "else " \ 113 "else " \
114 "echo wait for boot; " \ 114 "echo wait for boot; " \
115 "fi;\0" \ 115 "fi;\0" \
116 "netargs=setenv bootargs ${jh_clk} console=${console} " \ 116 "netargs=setenv bootargs ${jh_clk} console=${console} " \
117 "root=/dev/nfs " \ 117 "root=/dev/nfs " \
118 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 118 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
119 "netboot=echo Booting from net ...; " \ 119 "netboot=echo Booting from net ...; " \
120 "run netargs; " \ 120 "run netargs; " \
121 "if test ${ip_dyn} = yes; then " \ 121 "if test ${ip_dyn} = yes; then " \
122 "setenv get_cmd dhcp; " \ 122 "setenv get_cmd dhcp; " \
123 "else " \ 123 "else " \
124 "setenv get_cmd tftp; " \ 124 "setenv get_cmd tftp; " \
125 "fi; " \ 125 "fi; " \
126 "${get_cmd} ${loadaddr} ${image}; " \ 126 "${get_cmd} ${loadaddr} ${image}; " \
127 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 127 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
128 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 128 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
129 "booti ${loadaddr} - ${fdt_addr}; " \ 129 "booti ${loadaddr} - ${fdt_addr}; " \
130 "else " \ 130 "else " \
131 "echo WARN: Cannot load the DT; " \ 131 "echo WARN: Cannot load the DT; " \
132 "fi; " \ 132 "fi; " \
133 "else " \ 133 "else " \
134 "booti; " \ 134 "booti; " \
135 "fi;\0" 135 "fi;\0"
136 136
137 #define CONFIG_BOOTCOMMAND \ 137 #define CONFIG_BOOTCOMMAND \
138 "mmc dev ${mmcdev}; if mmc rescan; then " \ 138 "mmc dev ${mmcdev}; if mmc rescan; then " \
139 "if run loadbootscript; then " \ 139 "if run loadbootscript; then " \
140 "run bootscript; " \ 140 "run bootscript; " \
141 "else " \ 141 "else " \
142 "if run loadimage; then " \ 142 "if run loadimage; then " \
143 "run mmcboot; " \ 143 "run mmcboot; " \
144 "else run netboot; " \ 144 "else run netboot; " \
145 "fi; " \ 145 "fi; " \
146 "fi; " \ 146 "fi; " \
147 "else booti ${loadaddr} - ${fdt_addr}; fi" 147 "else booti ${loadaddr} - ${fdt_addr}; fi"
148 148
149 /* Link Definitions */ 149 /* Link Definitions */
150 #define CONFIG_LOADADDR 0x40480000 150 #define CONFIG_LOADADDR 0x40480000
151 151
152 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 152 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
153 153
154 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 154 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
155 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 155 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
156 #define CONFIG_SYS_INIT_SP_OFFSET \ 156 #define CONFIG_SYS_INIT_SP_OFFSET \
157 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 157 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
158 #define CONFIG_SYS_INIT_SP_ADDR \ 158 #define CONFIG_SYS_INIT_SP_ADDR \
159 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 159 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
160 160
161 #define CONFIG_ENV_OVERWRITE 161 #define CONFIG_ENV_OVERWRITE
162 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ 162 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
163 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ 163 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
164 164
165 /* Size of malloc() pool */ 165 /* Size of malloc() pool */
166 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) 166 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
167 167
168 #define CONFIG_SYS_SDRAM_BASE 0x40000000 168 #define CONFIG_SYS_SDRAM_BASE 0x40000000
169 #define PHYS_SDRAM 0x40000000 169 #define PHYS_SDRAM 0x40000000
170 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ 170 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
171 171
172 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 172 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
173 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 173 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
174 (PHYS_SDRAM_SIZE >> 1)) 174 (PHYS_SDRAM_SIZE >> 1))
175 175
176 #define CONFIG_BAUDRATE 115200 176 #define CONFIG_BAUDRATE 115200
177 177
178 #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR 178 #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
179 179
180 /* Monitor Command Prompt */ 180 /* Monitor Command Prompt */
181 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 181 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
182 #define CONFIG_SYS_CBSIZE 1024 182 #define CONFIG_SYS_CBSIZE 1024
183 #define CONFIG_SYS_MAXARGS 64 183 #define CONFIG_SYS_MAXARGS 64
184 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 184 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
185 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 185 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
186 sizeof(CONFIG_SYS_PROMPT) + 16) 186 sizeof(CONFIG_SYS_PROMPT) + 16)
187 187
188 #define CONFIG_IMX_BOOTAUX 188 #define CONFIG_IMX_BOOTAUX
189 189
190 #define CONFIG_SYS_FSL_USDHC_NUM 2 190 #define CONFIG_SYS_FSL_USDHC_NUM 2
191 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 191 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
192 192
193 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 193 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
194 194
195 #ifdef CONFIG_FSL_QSPI 195 #ifdef CONFIG_FSL_QSPI
196 #define FSL_QSPI_FLASH_SIZE (SZ_32M) 196 #define FSL_QSPI_FLASH_SIZE (SZ_32M)
197 #define FSL_QSPI_FLASH_NUM 1 197 #define FSL_QSPI_FLASH_NUM 1
198 #endif 198 #endif
199 199
200 /* I2C Configs */ 200 /* I2C Configs */
201 #define CONFIG_SYS_I2C_SPEED 100000 201 #define CONFIG_SYS_I2C_SPEED 100000
202 202
203 /* USB configs */ 203 /* USB configs */
204 #ifndef CONFIG_SPL_BUILD 204 #ifndef CONFIG_SPL_BUILD
205 #define CONFIG_CMD_USB 205 #define CONFIG_CMD_USB
206 #define CONFIG_USB_STORAGE 206 #define CONFIG_USB_STORAGE
207 207
208 #define CONFIG_CMD_USB_MASS_STORAGE 208 #define CONFIG_CMD_USB_MASS_STORAGE
209 #define CONFIG_USB_GADGET_MASS_STORAGE 209 #define CONFIG_USB_GADGET_MASS_STORAGE
210 #define CONFIG_USB_FUNCTION_MASS_STORAGE 210 #define CONFIG_USB_FUNCTION_MASS_STORAGE
211 211
212 #define CONFIG_CMD_READ 212 #define CONFIG_CMD_READ
213 213
214 #endif 214 #endif
215 215
216 #define CONFIG_SERIAL_TAG 216 #define CONFIG_SERIAL_TAG
217 #define CONFIG_FASTBOOT_USB_DEV 0 217 #define CONFIG_FASTBOOT_USB_DEV 0
218 218
219 219
220 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 220 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
221 221
222 #define CONFIG_USBD_HS 222 #define CONFIG_USBD_HS
223 #define CONFIG_USB_GADGET_VBUS_DRAW 2 223 #define CONFIG_USB_GADGET_VBUS_DRAW 2
224 224
225 #ifndef CONFIG_SPL_BUILD 225 #ifndef CONFIG_SPL_BUILD
226 #define CONFIG_DM_PMIC 226 #define CONFIG_DM_PMIC
227 #endif 227 #endif
228 228
229 #ifdef CONFIG_DM_VIDEO 229 #ifdef CONFIG_DM_VIDEO
230 #define CONFIG_VIDEO_LOGO 230 #define CONFIG_VIDEO_LOGO
231 #define CONFIG_SPLASH_SCREEN 231 #define CONFIG_SPLASH_SCREEN
232 #define CONFIG_SPLASH_SCREEN_ALIGN 232 #define CONFIG_SPLASH_SCREEN_ALIGN
233 #define CONFIG_CMD_BMP 233 #define CONFIG_CMD_BMP
234 #define CONFIG_BMP_16BPP 234 #define CONFIG_BMP_16BPP
235 #define CONFIG_BMP_24BPP 235 #define CONFIG_BMP_24BPP
236 #define CONFIG_BMP_32BPP 236 #define CONFIG_BMP_32BPP
237 #define CONFIG_VIDEO_BMP_RLE8 237 #define CONFIG_VIDEO_BMP_RLE8
238 #define CONFIG_VIDEO_BMP_LOGO 238 #define CONFIG_VIDEO_BMP_LOGO
239 #endif 239 #endif
240 240
241 #ifdef CONFIG_ANDROID_SUPPORT 241 #ifdef CONFIG_ANDROID_SUPPORT
242 #include "imx8mq_evk_android.h" 242 #include "imx8mq_evk_android.h"
243 #endif 243 #endif
244 244
245 #endif 245 #endif
246 246
include/configs/imx8mq_val.h
Diff comments   View file @ 1f3aebc
1 /* 1 /*
2 * Copyright 2017 NXP 2 * Copyright 2017 NXP
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __IMX8M_VAL_H 7 #ifndef __IMX8M_VAL_H
8 #define __IMX8M_VAL_H 8 #define __IMX8M_VAL_H
9 9
10 #include <linux/sizes.h> 10 #include <linux/sizes.h>
11 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/imx-regs.h>
12 #include "imx_env.h" 12 #include "imx_env.h"
13 13
14 #define CONFIG_SPL_MAX_SIZE (148 * 1024) 14 #define CONFIG_SPL_MAX_SIZE (148 * 1024)
15 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 15 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
16 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR 16 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
17 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 17 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (0x300 + CONFIG_SECONDARY_BOOT_SECTOR_OFFSET)
18 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 18 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
19 19
20 #ifdef CONFIG_SPL_BUILD 20 #ifdef CONFIG_SPL_BUILD
21 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ 21 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
22 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 22 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
23 #define CONFIG_SPL_STACK 0x187FF0 23 #define CONFIG_SPL_STACK 0x187FF0
24 #define CONFIG_SPL_BSS_START_ADDR 0x00180000 24 #define CONFIG_SPL_BSS_START_ADDR 0x00180000
25 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ 25 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
26 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 26 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
27 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ 27 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
28 28
29 #define CONFIG_MALLOC_F_ADDR 0x182000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ 29 #define CONFIG_MALLOC_F_ADDR 0x182000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
30 30
31 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ 31 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
32 32
33 #undef CONFIG_DM_MMC 33 #undef CONFIG_DM_MMC
34 #undef CONFIG_DM_PMIC 34 #undef CONFIG_DM_PMIC
35 #undef CONFIG_DM_PMIC_PFUZE100 35 #undef CONFIG_DM_PMIC_PFUZE100
36 36
37 #define CONFIG_SYS_I2C 37 #define CONFIG_SYS_I2C
38 38
39 #define CONFIG_POWER 39 #define CONFIG_POWER
40 #define CONFIG_POWER_I2C 40 #define CONFIG_POWER_I2C
41 #define CONFIG_POWER_PFUZE100 41 #define CONFIG_POWER_PFUZE100
42 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 42 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
43 43
44 #if defined(CONFIG_NAND_BOOT) 44 #if defined(CONFIG_NAND_BOOT)
45 #define CONFIG_SPL_NAND_SUPPORT 45 #define CONFIG_SPL_NAND_SUPPORT
46 #define CONFIG_SPL_DMA 46 #define CONFIG_SPL_DMA
47 #define CONFIG_SPL_NAND_MXS 47 #define CONFIG_SPL_NAND_MXS
48 #define CONFIG_SPL_NAND_BASE 48 #define CONFIG_SPL_NAND_BASE
49 #define CONFIG_SPL_NAND_IDENT 49 #define CONFIG_SPL_NAND_IDENT
50 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */ 50 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */
51 51
52 /* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */ 52 /* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
53 #define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \ 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
54 (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400) 54 (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
55 #endif 55 #endif
56 56
57 #endif /* CONFIG_SPL_BUILD*/ 57 #endif /* CONFIG_SPL_BUILD*/
58 58
59 #define CONFIG_REMAKE_ELF 59 #define CONFIG_REMAKE_ELF
60 60
61 /* ENET Config */ 61 /* ENET Config */
62 /* ENET1 */ 62 /* ENET1 */
63 #if defined(CONFIG_FEC_MXC) 63 #if defined(CONFIG_FEC_MXC)
64 #define CONFIG_ETHPRIME "FEC" 64 #define CONFIG_ETHPRIME "FEC"
65 #define PHY_ANEG_TIMEOUT 20000 65 #define PHY_ANEG_TIMEOUT 20000
66 66
67 #define FEC_QUIRK_ENET_MAC 67 #define FEC_QUIRK_ENET_MAC
68 68
69 #define IMX_FEC_BASE 0x30BE0000 69 #define IMX_FEC_BASE 0x30BE0000
70 70
71 #ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL 71 #ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL
72 #define CONFIG_FEC_XCV_TYPE RMII 72 #define CONFIG_FEC_XCV_TYPE RMII
73 #define CONFIG_FEC_MXC_PHYADDR 3 73 #define CONFIG_FEC_MXC_PHYADDR 3
74 #else 74 #else
75 #define CONFIG_FEC_MXC_PHYADDR 0 75 #define CONFIG_FEC_MXC_PHYADDR 0
76 #define CONFIG_FEC_XCV_TYPE RGMII 76 #define CONFIG_FEC_XCV_TYPE RGMII
77 #endif 77 #endif
78 78
79 #endif 79 #endif
80 80
81 #ifdef CONFIG_NAND_BOOT 81 #ifdef CONFIG_NAND_BOOT
82 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)" 82 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)"
83 #endif 83 #endif
84 84
85 #define CONFIG_MFG_ENV_SETTINGS \ 85 #define CONFIG_MFG_ENV_SETTINGS \
86 CONFIG_MFG_ENV_SETTINGS_DEFAULT \ 86 CONFIG_MFG_ENV_SETTINGS_DEFAULT \
87 "initrd_addr=0x43800000\0" \ 87 "initrd_addr=0x43800000\0" \
88 "initrd_high=0xffffffffffffffff\0" \ 88 "initrd_high=0xffffffffffffffff\0" \
89 "emmc_dev=0\0"\ 89 "emmc_dev=0\0"\
90 "sd_dev=1\0" \ 90 "sd_dev=1\0" \
91 91
92 /* Initial environment variables */ 92 /* Initial environment variables */
93 #if defined(CONFIG_NAND_BOOT) 93 #if defined(CONFIG_NAND_BOOT)
94 #define CONFIG_EXTRA_ENV_SETTINGS \ 94 #define CONFIG_EXTRA_ENV_SETTINGS \
95 CONFIG_MFG_ENV_SETTINGS \ 95 CONFIG_MFG_ENV_SETTINGS \
96 "fdt_addr=0x43000000\0" \ 96 "fdt_addr=0x43000000\0" \
97 "fdt_high=0xffffffffffffffff\0" \ 97 "fdt_high=0xffffffffffffffff\0" \
98 "mtdparts=" MFG_NAND_PARTITION "\0" \ 98 "mtdparts=" MFG_NAND_PARTITION "\0" \
99 "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ 99 "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \
100 "bootargs=console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200 ubi.mtd=nandrootfs " \ 100 "bootargs=console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200 ubi.mtd=nandrootfs " \
101 "root=ubi0:nandrootfs rootfstype=ubifs " \ 101 "root=ubi0:nandrootfs rootfstype=ubifs " \
102 MFG_NAND_PARTITION \ 102 MFG_NAND_PARTITION \
103 "\0" \ 103 "\0" \
104 "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\ 104 "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\
105 "nand read ${fdt_addr} 0x7000000 0x100000;"\ 105 "nand read ${fdt_addr} 0x7000000 0x100000;"\
106 "booti ${loadaddr} - ${fdt_addr}" 106 "booti ${loadaddr} - ${fdt_addr}"
107 107
108 #else 108 #else
109 #define CONFIG_EXTRA_ENV_SETTINGS \ 109 #define CONFIG_EXTRA_ENV_SETTINGS \
110 CONFIG_MFG_ENV_SETTINGS \ 110 CONFIG_MFG_ENV_SETTINGS \
111 "script=boot.scr\0" \ 111 "script=boot.scr\0" \
112 "image=Image\0" \ 112 "image=Image\0" \
113 "console=ttymxc0,115200\0" \ 113 "console=ttymxc0,115200\0" \
114 "fdt_addr=0x43000000\0" \ 114 "fdt_addr=0x43000000\0" \
115 "fdt_high=0xffffffffffffffff\0" \ 115 "fdt_high=0xffffffffffffffff\0" \
116 "boot_fdt=try\0" \ 116 "boot_fdt=try\0" \
117 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ 117 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
118 "initrd_addr=0x43800000\0" \ 118 "initrd_addr=0x43800000\0" \
119 "initrd_high=0xffffffffffffffff\0" \ 119 "initrd_high=0xffffffffffffffff\0" \
120 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ 120 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
121 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ 121 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
122 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 122 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
123 "mmcautodetect=yes\0" \ 123 "mmcautodetect=yes\0" \
124 "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ 124 "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
125 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 125 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
126 "bootscript=echo Running bootscript from mmc ...; " \ 126 "bootscript=echo Running bootscript from mmc ...; " \
127 "source\0" \ 127 "source\0" \
128 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 128 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
129 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 129 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
130 "mmcboot=echo Booting from mmc ...; " \ 130 "mmcboot=echo Booting from mmc ...; " \
131 "run mmcargs; " \ 131 "run mmcargs; " \
132 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 132 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
133 "if run loadfdt; then " \ 133 "if run loadfdt; then " \
134 "booti ${loadaddr} - ${fdt_addr}; " \ 134 "booti ${loadaddr} - ${fdt_addr}; " \
135 "else " \ 135 "else " \
136 "echo WARN: Cannot load the DT; " \ 136 "echo WARN: Cannot load the DT; " \
137 "fi; " \ 137 "fi; " \
138 "else " \ 138 "else " \
139 "echo wait for boot; " \ 139 "echo wait for boot; " \
140 "fi;\0" \ 140 "fi;\0" \
141 "netargs=setenv bootargs console=${console} " \ 141 "netargs=setenv bootargs console=${console} " \
142 "root=/dev/nfs " \ 142 "root=/dev/nfs " \
143 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 143 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
144 "netboot=echo Booting from net ...; " \ 144 "netboot=echo Booting from net ...; " \
145 "run netargs; " \ 145 "run netargs; " \
146 "if test ${ip_dyn} = yes; then " \ 146 "if test ${ip_dyn} = yes; then " \
147 "setenv get_cmd dhcp; " \ 147 "setenv get_cmd dhcp; " \
148 "else " \ 148 "else " \
149 "setenv get_cmd tftp; " \ 149 "setenv get_cmd tftp; " \
150 "fi; " \ 150 "fi; " \
151 "${get_cmd} ${loadaddr} ${image}; " \ 151 "${get_cmd} ${loadaddr} ${image}; " \
152 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 152 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
153 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 153 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
154 "booti ${loadaddr} - ${fdt_addr}; " \ 154 "booti ${loadaddr} - ${fdt_addr}; " \
155 "else " \ 155 "else " \
156 "echo WARN: Cannot load the DT; " \ 156 "echo WARN: Cannot load the DT; " \
157 "fi; " \ 157 "fi; " \
158 "else " \ 158 "else " \
159 "booti; " \ 159 "booti; " \
160 "fi;\0" 160 "fi;\0"
161 161
162 #define CONFIG_BOOTCOMMAND \ 162 #define CONFIG_BOOTCOMMAND \
163 "mmc dev ${mmcdev}; if mmc rescan; then " \ 163 "mmc dev ${mmcdev}; if mmc rescan; then " \
164 "if run loadbootscript; then " \ 164 "if run loadbootscript; then " \
165 "run bootscript; " \ 165 "run bootscript; " \
166 "else " \ 166 "else " \
167 "if run loadimage; then " \ 167 "if run loadimage; then " \
168 "run mmcboot; " \ 168 "run mmcboot; " \
169 "else run netboot; " \ 169 "else run netboot; " \
170 "fi; " \ 170 "fi; " \
171 "fi; " \ 171 "fi; " \
172 "else booti ${loadaddr} - ${fdt_addr}; fi" 172 "else booti ${loadaddr} - ${fdt_addr}; fi"
173 #endif 173 #endif
174 174
175 /* Link Definitions */ 175 /* Link Definitions */
176 #define CONFIG_LOADADDR 0x40480000 176 #define CONFIG_LOADADDR 0x40480000
177 177
178 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 178 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
179 179
180 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 180 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
181 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 181 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
182 #define CONFIG_SYS_INIT_SP_OFFSET \ 182 #define CONFIG_SYS_INIT_SP_OFFSET \
183 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 183 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
184 #define CONFIG_SYS_INIT_SP_ADDR \ 184 #define CONFIG_SYS_INIT_SP_ADDR \
185 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 185 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
186 186
187 #define CONFIG_ENV_OVERWRITE 187 #define CONFIG_ENV_OVERWRITE
188 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ 188 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
189 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ 189 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
190 190
191 /* Size of malloc() pool */ 191 /* Size of malloc() pool */
192 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024)) * 1024) 192 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024)) * 1024)
193 193
194 #define CONFIG_SYS_SDRAM_BASE 0x40000000 194 #define CONFIG_SYS_SDRAM_BASE 0x40000000
195 #define PHYS_SDRAM 0x40000000 195 #define PHYS_SDRAM 0x40000000
196 #ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL 196 #ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL
197 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR3L for two rank */ 197 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR3L for two rank */
198 #else 198 #else
199 #define PHYS_SDRAM_SIZE 0xc0000000 /* 3GB */ 199 #define PHYS_SDRAM_SIZE 0xc0000000 /* 3GB */
200 #define PHYS_SDRAM_2 0x100000000 200 #define PHYS_SDRAM_2 0x100000000
201 #define PHYS_SDRAM_2_SIZE 0x40000000 /* 1GB */ 201 #define PHYS_SDRAM_2_SIZE 0x40000000 /* 1GB */
202 #endif 202 #endif
203 203
204 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 204 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
205 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 205 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
206 (PHYS_SDRAM_SIZE >> 1)) 206 (PHYS_SDRAM_SIZE >> 1))
207 207
208 #define CONFIG_BAUDRATE 115200 208 #define CONFIG_BAUDRATE 115200
209 209
210 #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR 210 #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
211 211
212 /* Monitor Command Prompt */ 212 /* Monitor Command Prompt */
213 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 213 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
214 #define CONFIG_SYS_CBSIZE 1024 214 #define CONFIG_SYS_CBSIZE 1024
215 #define CONFIG_SYS_MAXARGS 64 215 #define CONFIG_SYS_MAXARGS 64
216 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 216 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
217 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 217 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
218 sizeof(CONFIG_SYS_PROMPT) + 16) 218 sizeof(CONFIG_SYS_PROMPT) + 16)
219 219
220 #define CONFIG_IMX_BOOTAUX 220 #define CONFIG_IMX_BOOTAUX
221 221
222 #define CONFIG_SYS_FSL_USDHC_NUM 2 222 #define CONFIG_SYS_FSL_USDHC_NUM 2
223 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 223 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
224 224
225 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 225 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
226 226
227 #ifdef CONFIG_FSL_QSPI 227 #ifdef CONFIG_FSL_QSPI
228 #define FSL_QSPI_FLASH_SIZE (SZ_2M) 228 #define FSL_QSPI_FLASH_SIZE (SZ_2M)
229 #define FSL_QSPI_FLASH_NUM 2 229 #define FSL_QSPI_FLASH_NUM 2
230 #endif 230 #endif
231 231
232 /* I2C Configs */ 232 /* I2C Configs */
233 #define CONFIG_SYS_I2C_SPEED 100000 233 #define CONFIG_SYS_I2C_SPEED 100000
234 234
235 #ifdef CONFIG_NAND_MXS 235 #ifdef CONFIG_NAND_MXS
236 #define CONFIG_CMD_NAND_TRIMFFS 236 #define CONFIG_CMD_NAND_TRIMFFS
237 237
238 /* NAND stuff */ 238 /* NAND stuff */
239 #define CONFIG_SYS_MAX_NAND_DEVICE 1 239 #define CONFIG_SYS_MAX_NAND_DEVICE 1
240 #define CONFIG_SYS_NAND_BASE 0x20000000 240 #define CONFIG_SYS_NAND_BASE 0x20000000
241 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 241 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
242 #define CONFIG_SYS_NAND_ONFI_DETECTION 242 #define CONFIG_SYS_NAND_ONFI_DETECTION
243 #define CONFIG_SYS_NAND_USE_FLASH_BBT 243 #define CONFIG_SYS_NAND_USE_FLASH_BBT
244 #endif /* CONFIG_NAND_MXS */ 244 #endif /* CONFIG_NAND_MXS */
245 245
246 /* USB configs */ 246 /* USB configs */
247 #ifndef CONFIG_SPL_BUILD 247 #ifndef CONFIG_SPL_BUILD
248 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 248 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
249 249
250 #define CONFIG_CMD_USB 250 #define CONFIG_CMD_USB
251 #define CONFIG_USB_STORAGE 251 #define CONFIG_USB_STORAGE
252 252
253 #define CONFIG_USBD_HS 253 #define CONFIG_USBD_HS
254 254
255 #define CONFIG_CMD_USB_MASS_STORAGE 255 #define CONFIG_CMD_USB_MASS_STORAGE
256 #define CONFIG_USB_GADGET_MASS_STORAGE 256 #define CONFIG_USB_GADGET_MASS_STORAGE
257 #define CONFIG_USB_GADGET_VBUS_DRAW 2 257 #define CONFIG_USB_GADGET_VBUS_DRAW 2
258 #define CONFIG_USB_FUNCTION_MASS_STORAGE 258 #define CONFIG_USB_FUNCTION_MASS_STORAGE
259 259
260 #endif 260 #endif
261 261
262 #define CONFIG_SERIAL_TAG 262 #define CONFIG_SERIAL_TAG
263 #define CONFIG_FASTBOOT_USB_DEV 0 263 #define CONFIG_FASTBOOT_USB_DEV 0
264 264
265 #endif 265 #endif
266 266