Eric Lee / smarc-uboot

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/* SPDX-License-Identifier: GPL-2.0+ */

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/* SPDX-License-Identifier: GPL-2.0+ */

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/*

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/*

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* Andreas Heppel <aheppel@sysgo.de>

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* Andreas Heppel <aheppel@sysgo.de>

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*

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*

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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.

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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.

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*/

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*/

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#ifndef _PCI_H

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#ifndef _PCI_H

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#define _PCI_H

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#define _PCI_H

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#define PCI_CFG_SPACE_SIZE 256

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#define PCI_CFG_SPACE_SIZE 256

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#define PCI_CFG_SPACE_EXP_SIZE 4096

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#define PCI_CFG_SPACE_EXP_SIZE 4096

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/*

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/*

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* Under PCI, each device has 256 bytes of configuration address space,

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* Under PCI, each device has 256 bytes of configuration address space,

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* of which the first 64 bytes are standardized as follows:

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* of which the first 64 bytes are standardized as follows:

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*/

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*/

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#define PCI_STD_HEADER_SIZEOF 64

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#define PCI_STD_HEADER_SIZEOF 64

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#define PCI_VENDOR_ID 0x00 /* 16 bits */

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#define PCI_VENDOR_ID 0x00 /* 16 bits */

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#define PCI_DEVICE_ID 0x02 /* 16 bits */

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#define PCI_DEVICE_ID 0x02 /* 16 bits */

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#define PCI_COMMAND 0x04 /* 16 bits */

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#define PCI_COMMAND 0x04 /* 16 bits */

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#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */

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#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */

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#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */

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#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */

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#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */

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#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */

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#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */

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#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */

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#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */

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#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */

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#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */

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#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */

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#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */

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#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */

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#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */

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#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */

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#define PCI_COMMAND_SERR 0x100 /* Enable SERR */

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#define PCI_COMMAND_SERR 0x100 /* Enable SERR */

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#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */

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#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */

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#define PCI_STATUS 0x06 /* 16 bits */

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#define PCI_STATUS 0x06 /* 16 bits */

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#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */

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#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */

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#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */

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#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */

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#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */

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#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */

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#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */

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#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */

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#define PCI_STATUS_PARITY 0x100 /* Detected parity error */

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#define PCI_STATUS_PARITY 0x100 /* Detected parity error */

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#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */

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#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */

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#define PCI_STATUS_DEVSEL_FAST 0x000

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#define PCI_STATUS_DEVSEL_FAST 0x000

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#define PCI_STATUS_DEVSEL_MEDIUM 0x200

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#define PCI_STATUS_DEVSEL_MEDIUM 0x200

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#define PCI_STATUS_DEVSEL_SLOW 0x400

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#define PCI_STATUS_DEVSEL_SLOW 0x400

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#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */

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#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */

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#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */

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#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */

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#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */

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#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */

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#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */

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#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */

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#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */

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#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */

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#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8

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#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8

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revision */

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revision */

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#define PCI_REVISION_ID 0x08 /* Revision ID */

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#define PCI_REVISION_ID 0x08 /* Revision ID */

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#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */

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#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */

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#define PCI_CLASS_DEVICE 0x0a /* Device class */

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#define PCI_CLASS_DEVICE 0x0a /* Device class */

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#define PCI_CLASS_CODE 0x0b /* Device class code */

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#define PCI_CLASS_CODE 0x0b /* Device class code */

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#define PCI_CLASS_CODE_TOO_OLD 0x00

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#define PCI_CLASS_CODE_TOO_OLD 0x00

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#define PCI_CLASS_CODE_STORAGE 0x01

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#define PCI_CLASS_CODE_STORAGE 0x01

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#define PCI_CLASS_CODE_NETWORK 0x02

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#define PCI_CLASS_CODE_NETWORK 0x02

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#define PCI_CLASS_CODE_DISPLAY 0x03

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#define PCI_CLASS_CODE_DISPLAY 0x03

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#define PCI_CLASS_CODE_MULTIMEDIA 0x04

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#define PCI_CLASS_CODE_MULTIMEDIA 0x04

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#define PCI_CLASS_CODE_MEMORY 0x05

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#define PCI_CLASS_CODE_MEMORY 0x05

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#define PCI_CLASS_CODE_BRIDGE 0x06

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#define PCI_CLASS_CODE_BRIDGE 0x06

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#define PCI_CLASS_CODE_COMM 0x07

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#define PCI_CLASS_CODE_COMM 0x07

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#define PCI_CLASS_CODE_PERIPHERAL 0x08

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#define PCI_CLASS_CODE_PERIPHERAL 0x08

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#define PCI_CLASS_CODE_INPUT 0x09

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#define PCI_CLASS_CODE_INPUT 0x09

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#define PCI_CLASS_CODE_DOCKING 0x0A

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#define PCI_CLASS_CODE_DOCKING 0x0A

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#define PCI_CLASS_CODE_PROCESSOR 0x0B

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#define PCI_CLASS_CODE_PROCESSOR 0x0B

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#define PCI_CLASS_CODE_SERIAL 0x0C

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#define PCI_CLASS_CODE_SERIAL 0x0C

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#define PCI_CLASS_CODE_WIRELESS 0x0D

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#define PCI_CLASS_CODE_WIRELESS 0x0D

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#define PCI_CLASS_CODE_I2O 0x0E

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#define PCI_CLASS_CODE_I2O 0x0E

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#define PCI_CLASS_CODE_SATELLITE 0x0F

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#define PCI_CLASS_CODE_SATELLITE 0x0F

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#define PCI_CLASS_CODE_CRYPTO 0x10

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#define PCI_CLASS_CODE_CRYPTO 0x10

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#define PCI_CLASS_CODE_DATA 0x11

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#define PCI_CLASS_CODE_DATA 0x11

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/* Base Class 0x12 - 0xFE is reserved */

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/* Base Class 0x12 - 0xFE is reserved */

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#define PCI_CLASS_CODE_OTHER 0xFF

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#define PCI_CLASS_CODE_OTHER 0xFF

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#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */

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#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */

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#define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00

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#define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00

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#define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01

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#define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01

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#define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00

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#define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00

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#define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01

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#define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01

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#define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02

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#define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02

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#define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03

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#define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03

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#define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04

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#define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04

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#define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05

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#define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05

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#define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06

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#define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06

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#define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07

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#define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07

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#define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00

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#define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00

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#define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01

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#define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01

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#define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02

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#define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02

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#define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03

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#define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03

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#define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04

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#define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04

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#define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05

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#define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05

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#define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06

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#define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06

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#define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00

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#define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00

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#define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01

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#define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01

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#define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02

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#define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02

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#define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00

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#define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00

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#define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01

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#define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01

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#define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02

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#define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02

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#define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00

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#define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00

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#define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01

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#define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01

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#define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00

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#define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00

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#define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01

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#define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01

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#define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02

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#define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02

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#define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03

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#define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03

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#define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04

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#define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04

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#define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05

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#define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05

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#define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06

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#define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06

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#define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07

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#define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07

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#define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08

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#define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08

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#define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09

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#define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09

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#define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A

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#define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A

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#define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00

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#define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00

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#define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01

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#define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01

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#define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02

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#define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02

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#define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03

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#define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03

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#define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04

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#define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04

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#define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05

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#define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05

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#define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00

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#define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00

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#define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01

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#define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01

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#define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02

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#define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02

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#define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03

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#define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03

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#define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04

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#define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04

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#define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05

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#define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05

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#define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00

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#define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00

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#define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01

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#define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01

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#define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02

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#define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02

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#define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03

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#define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03

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#define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04

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#define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04

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#define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00

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#define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00

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#define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00

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#define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00

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#define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01

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#define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01

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#define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02

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#define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02

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#define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10

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#define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10

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#define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20

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#define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20

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#define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30

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#define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30

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#define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40

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#define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40

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#define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00

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#define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00

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#define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01

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#define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01

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#define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02

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#define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02

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#define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03

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#define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03

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#define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04

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#define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04

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#define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05

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#define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05

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#define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06

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#define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06

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#define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07

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#define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07

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#define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08

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#define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08

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#define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09

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#define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09

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#define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00

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#define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00

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#define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01

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#define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01

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#define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10

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#define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10

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#define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11

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#define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11

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#define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12

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#define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12

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#define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20

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#define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20

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#define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21

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#define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21

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#define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00

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#define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00

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#define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01

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#define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01

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#define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02

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#define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02

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#define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03

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#define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03

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#define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04

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#define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04

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#define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00

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#define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00

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#define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10

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#define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10

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#define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00

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#define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00

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#define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01

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#define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01

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#define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10

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#define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10

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#define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20

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#define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20

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#define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80

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#define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80

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#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */

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#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */

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#define PCI_LATENCY_TIMER 0x0d /* 8 bits */

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#define PCI_LATENCY_TIMER 0x0d /* 8 bits */

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#define PCI_HEADER_TYPE 0x0e /* 8 bits */

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#define PCI_HEADER_TYPE 0x0e /* 8 bits */

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#define PCI_HEADER_TYPE_NORMAL 0

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#define PCI_HEADER_TYPE_NORMAL 0

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#define PCI_HEADER_TYPE_BRIDGE 1

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#define PCI_HEADER_TYPE_BRIDGE 1

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#define PCI_HEADER_TYPE_CARDBUS 2

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#define PCI_HEADER_TYPE_CARDBUS 2

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#define PCI_BIST 0x0f /* 8 bits */

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#define PCI_BIST 0x0f /* 8 bits */

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#define PCI_BIST_CODE_MASK 0x0f /* Return result */

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#define PCI_BIST_CODE_MASK 0x0f /* Return result */

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#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */

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#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */

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#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */

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#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */

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/*

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/*

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* Base addresses specify locations in memory or I/O space.

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* Base addresses specify locations in memory or I/O space.

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* Decoded size can be determined by writing a value of

196

* Decoded size can be determined by writing a value of

197

* 0xffffffff to the register, and reading it back. Only

197

* 0xffffffff to the register, and reading it back. Only

198

* 1 bits are decoded.

198

* 1 bits are decoded.

199

*/

199

*/

200

#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */

200

#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */

201

#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */

201

#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */

202

#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */

202

#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */

203

#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */

203

#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */

204

#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */

204

#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */

205

#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */

205

#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */

206

#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */

206

#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */

207

#define PCI_BASE_ADDRESS_SPACE_IO 0x01

207

#define PCI_BASE_ADDRESS_SPACE_IO 0x01

208

#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00

208

#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00

209

#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06

209

#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06

210

#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */

210

#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */

211

#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */

211

#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */

212

#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */

212

#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */

213

#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */

213

#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */

214

#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)

214

#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)

215

#define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)

215

#define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)

216

/* bit 1 is reserved if address_space = 1 */

216

/* bit 1 is reserved if address_space = 1 */

217

218

/* Header type 0 (normal devices) */

218

/* Header type 0 (normal devices) */

219

#define PCI_CARDBUS_CIS 0x28

219

#define PCI_CARDBUS_CIS 0x28

220

#define PCI_SUBSYSTEM_VENDOR_ID 0x2c

220

#define PCI_SUBSYSTEM_VENDOR_ID 0x2c

221

#define PCI_SUBSYSTEM_ID 0x2e

221

#define PCI_SUBSYSTEM_ID 0x2e

222

#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */

222

#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */

223

#define PCI_ROM_ADDRESS_ENABLE 0x01

223

#define PCI_ROM_ADDRESS_ENABLE 0x01

224

#define PCI_ROM_ADDRESS_MASK (~0x7ffULL)

224

#define PCI_ROM_ADDRESS_MASK (~0x7ffULL)

225

226

#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */

226

#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */

227

228

/* 0x35-0x3b are reserved */

228

/* 0x35-0x3b are reserved */

229

#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */

229

#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */

230

#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */

230

#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */

231

#define PCI_MIN_GNT 0x3e /* 8 bits */

231

#define PCI_MIN_GNT 0x3e /* 8 bits */

232

#define PCI_MAX_LAT 0x3f /* 8 bits */

232

#define PCI_MAX_LAT 0x3f /* 8 bits */

233

234

#define PCI_INTERRUPT_LINE_DISABLE 0xff

234

#define PCI_INTERRUPT_LINE_DISABLE 0xff

235

236

/* Header type 1 (PCI-to-PCI bridges) */

236

/* Header type 1 (PCI-to-PCI bridges) */

237

#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */

237

#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */

238

#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */

238

#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */

239

#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */

239

#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */

240

#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */

240

#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */

241

#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */

241

#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */

242

#define PCI_IO_LIMIT 0x1d

242

#define PCI_IO_LIMIT 0x1d

243

#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */

243

#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */

244

#define PCI_IO_RANGE_TYPE_16 0x00

244

#define PCI_IO_RANGE_TYPE_16 0x00

245

#define PCI_IO_RANGE_TYPE_32 0x01

245

#define PCI_IO_RANGE_TYPE_32 0x01

246

#define PCI_IO_RANGE_MASK ~0x0f

246

#define PCI_IO_RANGE_MASK ~0x0f

247

#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */

247

#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */

248

#define PCI_MEMORY_BASE 0x20 /* Memory range behind */

248

#define PCI_MEMORY_BASE 0x20 /* Memory range behind */

249

#define PCI_MEMORY_LIMIT 0x22

249

#define PCI_MEMORY_LIMIT 0x22

250

#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f

250

#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f

251

#define PCI_MEMORY_RANGE_MASK ~0x0f

251

#define PCI_MEMORY_RANGE_MASK ~0x0f

252

#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */

252

#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */

253

#define PCI_PREF_MEMORY_LIMIT 0x26

253

#define PCI_PREF_MEMORY_LIMIT 0x26

254

#define PCI_PREF_RANGE_TYPE_MASK 0x0f

254

#define PCI_PREF_RANGE_TYPE_MASK 0x0f

255

#define PCI_PREF_RANGE_TYPE_32 0x00

255

#define PCI_PREF_RANGE_TYPE_32 0x00

256

#define PCI_PREF_RANGE_TYPE_64 0x01

256

#define PCI_PREF_RANGE_TYPE_64 0x01

257

#define PCI_PREF_RANGE_MASK ~0x0f

257

#define PCI_PREF_RANGE_MASK ~0x0f

258

#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */

258

#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */

259

#define PCI_PREF_LIMIT_UPPER32 0x2c

259

#define PCI_PREF_LIMIT_UPPER32 0x2c

260

#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */

260

#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */

261

#define PCI_IO_LIMIT_UPPER16 0x32

261

#define PCI_IO_LIMIT_UPPER16 0x32

262

/* 0x34 same as for htype 0 */

262

/* 0x34 same as for htype 0 */

263

/* 0x35-0x3b is reserved */

263

/* 0x35-0x3b is reserved */

264

#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */

264

#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */

265

/* 0x3c-0x3d are same as for htype 0 */

265

/* 0x3c-0x3d are same as for htype 0 */

266

#define PCI_BRIDGE_CONTROL 0x3e

266

#define PCI_BRIDGE_CONTROL 0x3e

267

#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */

267

#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */

268

#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */

268

#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */

269

#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */

269

#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */

270

#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */

270

#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */

271

#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */

271

#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */

272

#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */

272

#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */

273

#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */

273

#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */

274

275

/* Header type 2 (CardBus bridges) */

275

/* Header type 2 (CardBus bridges) */

276

#define PCI_CB_CAPABILITY_LIST 0x14

276

#define PCI_CB_CAPABILITY_LIST 0x14

277

/* 0x15 reserved */

277

/* 0x15 reserved */

278

#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */

278

#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */

279

#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */

279

#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */

280

#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */

280

#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */

281

#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */

281

#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */

282

#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */

282

#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */

283

#define PCI_CB_MEMORY_BASE_0 0x1c

283

#define PCI_CB_MEMORY_BASE_0 0x1c

284

#define PCI_CB_MEMORY_LIMIT_0 0x20

284

#define PCI_CB_MEMORY_LIMIT_0 0x20

285

#define PCI_CB_MEMORY_BASE_1 0x24

285

#define PCI_CB_MEMORY_BASE_1 0x24

286

#define PCI_CB_MEMORY_LIMIT_1 0x28

286

#define PCI_CB_MEMORY_LIMIT_1 0x28

287

#define PCI_CB_IO_BASE_0 0x2c

287

#define PCI_CB_IO_BASE_0 0x2c

288

#define PCI_CB_IO_BASE_0_HI 0x2e

288

#define PCI_CB_IO_BASE_0_HI 0x2e

289

#define PCI_CB_IO_LIMIT_0 0x30

289

#define PCI_CB_IO_LIMIT_0 0x30

290

#define PCI_CB_IO_LIMIT_0_HI 0x32

290

#define PCI_CB_IO_LIMIT_0_HI 0x32

291

#define PCI_CB_IO_BASE_1 0x34

291

#define PCI_CB_IO_BASE_1 0x34

292

#define PCI_CB_IO_BASE_1_HI 0x36

292

#define PCI_CB_IO_BASE_1_HI 0x36

293

#define PCI_CB_IO_LIMIT_1 0x38

293

#define PCI_CB_IO_LIMIT_1 0x38

294

#define PCI_CB_IO_LIMIT_1_HI 0x3a

294

#define PCI_CB_IO_LIMIT_1_HI 0x3a

295

#define PCI_CB_IO_RANGE_MASK ~0x03

295

#define PCI_CB_IO_RANGE_MASK ~0x03

296

/* 0x3c-0x3d are same as for htype 0 */

296

/* 0x3c-0x3d are same as for htype 0 */

297

#define PCI_CB_BRIDGE_CONTROL 0x3e

297

#define PCI_CB_BRIDGE_CONTROL 0x3e

298

#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */

298

#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */

299

#define PCI_CB_BRIDGE_CTL_SERR 0x02

299

#define PCI_CB_BRIDGE_CTL_SERR 0x02

300

#define PCI_CB_BRIDGE_CTL_ISA 0x04

300

#define PCI_CB_BRIDGE_CTL_ISA 0x04

301

#define PCI_CB_BRIDGE_CTL_VGA 0x08

301

#define PCI_CB_BRIDGE_CTL_VGA 0x08

302

#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20

302

#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20

303

#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */

303

#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */

304

#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */

304

#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */

305

#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */

305

#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */

306

#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200

306

#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200

307

#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400

307

#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400

308

#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40

308

#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40

309

#define PCI_CB_SUBSYSTEM_ID 0x42

309

#define PCI_CB_SUBSYSTEM_ID 0x42

310

#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */

310

#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */

311

/* 0x48-0x7f reserved */

311

/* 0x48-0x7f reserved */

312

313

/* Capability lists */

313

/* Capability lists */

314

315

#define PCI_CAP_LIST_ID 0 /* Capability ID */

315

#define PCI_CAP_LIST_ID 0 /* Capability ID */

316

#define PCI_CAP_ID_PM 0x01 /* Power Management */

316

#define PCI_CAP_ID_PM 0x01 /* Power Management */

317

#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */

317

#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */

318

#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */

318

#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */

319

#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */

319

#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */

320

#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */

320

#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */

321

#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */

321

#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */

322

#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */

322

#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */

323

#define PCI_CAP_ID_HT 0x08 /* HyperTransport */

323

#define PCI_CAP_ID_HT 0x08 /* HyperTransport */

324

#define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */

324

#define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */

325

#define PCI_CAP_ID_DBG 0x0A /* Debug port */

325

#define PCI_CAP_ID_DBG 0x0A /* Debug port */

326

#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */

326

#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */

327

#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */

327

#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */

328

#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */

328

#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */

329

#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */

329

#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */

330

#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */

330

#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */

331

#define PCI_CAP_ID_EXP 0x10 /* PCI Express */

331

#define PCI_CAP_ID_EXP 0x10 /* PCI Express */

332

#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */

332

#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */

333

#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */

333

#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */

334

#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */

334

#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */

335

#define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */

335

#define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */

336

#define PCI_CAP_ID_MAX PCI_CAP_ID_EA

336

#define PCI_CAP_ID_MAX PCI_CAP_ID_EA

337

#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */

337

#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */

338

#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */

338

#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */

339

#define PCI_CAP_SIZEOF 4

339

#define PCI_CAP_SIZEOF 4

340

341

/* Power Management Registers */

341

/* Power Management Registers */

342

343

#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */

343

#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */

344

#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */

344

#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */

345

#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */

345

#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */

346

#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */

346

#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */

347

#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */

347

#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */

348

#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */

348

#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */

349

#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */

349

#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */

350

#define PCI_PM_CTRL 4 /* PM control and status register */

350

#define PCI_PM_CTRL 4 /* PM control and status register */

351

#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */

351

#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */

352

#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */

352

#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */

353

#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */

353

#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */

354

#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */

354

#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */

355

#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */

355

#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */

356

#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */

356

#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */

357

#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */

357

#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */

358

#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */

358

#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */

359

#define PCI_PM_DATA_REGISTER 7 /* (??) */

359

#define PCI_PM_DATA_REGISTER 7 /* (??) */

360

#define PCI_PM_SIZEOF 8

360

#define PCI_PM_SIZEOF 8

361

362

/* AGP registers */

362

/* AGP registers */

363

364

#define PCI_AGP_VERSION 2 /* BCD version number */

364

#define PCI_AGP_VERSION 2 /* BCD version number */

365

#define PCI_AGP_RFU 3 /* Rest of capability flags */

365

#define PCI_AGP_RFU 3 /* Rest of capability flags */

366

#define PCI_AGP_STATUS 4 /* Status register */

366

#define PCI_AGP_STATUS 4 /* Status register */

367

#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */

367

#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */

368

#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */

368

#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */

369

#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */

369

#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */

370

#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */

370

#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */

371

#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */

371

#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */

372

#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */

372

#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */

373

#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */

373

#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */

374

#define PCI_AGP_COMMAND 8 /* Control register */

374

#define PCI_AGP_COMMAND 8 /* Control register */

375

#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */

375

#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */

376

#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */

376

#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */

377

#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */

377

#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */

378

#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */

378

#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */

379

#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */

379

#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */

380

#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */

380

#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */

381

#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */

381

#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */

382

#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */

382

#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */

383

#define PCI_AGP_SIZEOF 12

383

#define PCI_AGP_SIZEOF 12

384

385

/* PCI-X registers */

385

/* PCI-X registers */

386

387

#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */

387

#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */

388

#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */

388

#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */

389

#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */

389

#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */

390

#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */

390

#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */

391

#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */

391

#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */

392

393

394

/* Slot Identification */

394

/* Slot Identification */

395

396

#define PCI_SID_ESR 2 /* Expansion Slot Register */

396

#define PCI_SID_ESR 2 /* Expansion Slot Register */

397

#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */

397

#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */

398

#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */

398

#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */

399

#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */

399

#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */

400

401

/* Message Signalled Interrupts registers */

401

/* Message Signalled Interrupts registers */

402

403

#define PCI_MSI_FLAGS 2 /* Various flags */

403

#define PCI_MSI_FLAGS 2 /* Various flags */

404

#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */

404

#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */

405

#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */

405

#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */

406

#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */

406

#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */

407

#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */

407

#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */

408

#define PCI_MSI_RFU 3 /* Rest of capability flags */

408

#define PCI_MSI_RFU 3 /* Rest of capability flags */

409

#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */

409

#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */

410

#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */

410

#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */

411

#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */

411

#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */

412

#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */

412

#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */

413

414

#define PCI_MAX_PCI_DEVICES 32

414

#define PCI_MAX_PCI_DEVICES 32

415

#define PCI_MAX_PCI_FUNCTIONS 8

415

#define PCI_MAX_PCI_FUNCTIONS 8

416

417

#define PCI_FIND_CAP_TTL 0x48

417

#define PCI_FIND_CAP_TTL 0x48

418

#define CAP_START_POS 0x40

418

#define CAP_START_POS 0x40

419

420

/* Extended Capabilities (PCI-X 2.0 and Express) */

420

/* Extended Capabilities (PCI-X 2.0 and Express) */

421

#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)

421

#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)

422

#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)

422

#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)

423

#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)

423

#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)

424

425

#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */

425

#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */

426

#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */

426

#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */

427

#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */

427

#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */

428

#define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */

428

#define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */

429

#define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */

429

#define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */

430

#define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */

430

#define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */

431

#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */

431

#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */

432

#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */

432

#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */

433

#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */

433

#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */

434

#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */

434

#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */

435

#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */

435

#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */

436

#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */

436

#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */

437

#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */

437

#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */

438

#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */

438

#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */

439

#define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */

439

#define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */

440

#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */

440

#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */

441

#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */

441

#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */

442

#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */

442

#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */

443

#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */

443

#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */

444

#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */

444

#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */

445

#define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */

445

#define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */

446

#define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */

446

#define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */

447

#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */

447

#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */

448

#define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */

448

#define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */

449

#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */

449

#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */

450

#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */

450

#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */

451

#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */

451

#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */

452

#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */

452

#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */

453

#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */

453

#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */

454

#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */

454

#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */

455

#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM

455

#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM

456

457

/* Include the ID list */

457

/* Include the ID list */

458

459

#include <pci_ids.h>

459

#include <pci_ids.h>

460

461

#ifndef __ASSEMBLY__

461

#ifndef __ASSEMBLY__

462

463

#ifdef CONFIG_SYS_PCI_64BIT

463

#ifdef CONFIG_SYS_PCI_64BIT

464

typedef u64 pci_addr_t;

464

typedef u64 pci_addr_t;

465

typedef u64 pci_size_t;

465

typedef u64 pci_size_t;

466

#else

466

#else

467

typedef u32 pci_addr_t;

467

typedef u32 pci_addr_t;

468

typedef u32 pci_size_t;

468

typedef u32 pci_size_t;

469

#endif

469

#endif

470

471

struct pci_region {

471

struct pci_region {

472

pci_addr_t bus_start; /* Start on the bus */

472

pci_addr_t bus_start; /* Start on the bus */

473

phys_addr_t phys_start; /* Start in physical address space */

473

phys_addr_t phys_start; /* Start in physical address space */

474

pci_size_t size; /* Size */

474

pci_size_t size; /* Size */

475

unsigned long flags; /* Resource flags */

475

unsigned long flags; /* Resource flags */

476

477

pci_addr_t bus_lower;

477

pci_addr_t bus_lower;

478

};

478

};

479

480

#define PCI_REGION_MEM 0x00000000 /* PCI memory space */

480

#define PCI_REGION_MEM 0x00000000 /* PCI memory space */

481

#define PCI_REGION_IO 0x00000001 /* PCI IO space */

481

#define PCI_REGION_IO 0x00000001 /* PCI IO space */

482

#define PCI_REGION_TYPE 0x00000001

482

#define PCI_REGION_TYPE 0x00000001

483

#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */

483

#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */

484

485

#define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */

485

#define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */

486

#define PCI_REGION_RO 0x00000200 /* Read-only memory */

486

#define PCI_REGION_RO 0x00000200 /* Read-only memory */

487

488

static inline void pci_set_region(struct pci_region *reg,

488

static inline void pci_set_region(struct pci_region *reg,

489

pci_addr_t bus_start,

489

pci_addr_t bus_start,

490

phys_addr_t phys_start,

490

phys_addr_t phys_start,

491

pci_size_t size,

491

pci_size_t size,

492

unsigned long flags) {

492

unsigned long flags) {

493

reg->bus_start = bus_start;

493

reg->bus_start = bus_start;

494

reg->phys_start = phys_start;

494

reg->phys_start = phys_start;

495

reg->size = size;

495

reg->size = size;

496

reg->flags = flags;

496

reg->flags = flags;

497

}

497

}

498

499

typedef int pci_dev_t;

499

typedef int pci_dev_t;

500

501

#define PCI_BUS(d) (((d) >> 16) & 0xff)

501

#define PCI_BUS(d) (((d) >> 16) & 0xff)

502

503

/*

504

* Please note the difference in DEVFN usage in U-Boot vs Linux. U-Boot

505

* uses DEVFN in bits 15-8 but Linux instead expects DEVFN in bits 7-0.

506

* Please see the Linux header include/uapi/linux/pci.h for more details.

507

* This is relevant for the following macros:

508

* PCI_DEV, PCI_FUNC, PCI_DEVFN

509

* The U-Boot macro PCI_DEV is equivalent to the Linux PCI_SLOT version with

510

* the remark from above (input d in bits 15-8 instead of 7-0.

511

*/

502

#define PCI_DEV(d) (((d) >> 11) & 0x1f)

512

#define PCI_DEV(d) (((d) >> 11) & 0x1f)

503

#define PCI_FUNC(d) (((d) >> 8) & 0x7)

513

#define PCI_FUNC(d) (((d) >> 8) & 0x7)

504

#define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)

514

#define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)

515

505

#define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)

516

#define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)

506

#define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))

517

#define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))

507

#define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))

518

#define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))

508

#define PCI_VENDEV(v, d) (((v) << 16) | (d))

519

#define PCI_VENDEV(v, d) (((v) << 16) | (d))

509

#define PCI_ANY_ID (~0)

520

#define PCI_ANY_ID (~0)

510

521

511

struct pci_device_id {

522

struct pci_device_id {

512

unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */

523

unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */

513

unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */

524

unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */

514

unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */

525

unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */

515

unsigned long driver_data; /* Data private to the driver */

526

unsigned long driver_data; /* Data private to the driver */

516

};

527

};

517

528

518

struct pci_controller;

529

struct pci_controller;

519

530

520

struct pci_config_table {

531

struct pci_config_table {

521

unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */

532

unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */

522

unsigned int class; /* Class ID, or PCI_ANY_ID */

533

unsigned int class; /* Class ID, or PCI_ANY_ID */

523

unsigned int bus; /* Bus number, or PCI_ANY_ID */

534

unsigned int bus; /* Bus number, or PCI_ANY_ID */

524

unsigned int dev; /* Device number, or PCI_ANY_ID */

535

unsigned int dev; /* Device number, or PCI_ANY_ID */

525

unsigned int func; /* Function number, or PCI_ANY_ID */

536

unsigned int func; /* Function number, or PCI_ANY_ID */

526

537

527

void (*config_device)(struct pci_controller* hose, pci_dev_t dev,

538

void (*config_device)(struct pci_controller* hose, pci_dev_t dev,

528

struct pci_config_table *);

539

struct pci_config_table *);

529

unsigned long priv[3];

540

unsigned long priv[3];

530

};

541

};

531

542

532

extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,

543

extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,

533

struct pci_config_table *);

544

struct pci_config_table *);

534

extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,

545

extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,

535

struct pci_config_table *);

546

struct pci_config_table *);

536

547

537

#define MAX_PCI_REGIONS 7

548

#define MAX_PCI_REGIONS 7

538

549

539

#define INDIRECT_TYPE_NO_PCIE_LINK 1

550

#define INDIRECT_TYPE_NO_PCIE_LINK 1

540

551

541

/*

552

/*

542

* Structure of a PCI controller (host bridge)

553

* Structure of a PCI controller (host bridge)

543

*

554

*

544

* With driver model this is dev_get_uclass_priv(bus)

555

* With driver model this is dev_get_uclass_priv(bus)

545

*/

556

*/

546

struct pci_controller {

557

struct pci_controller {

547

#ifdef CONFIG_DM_PCI

558

#ifdef CONFIG_DM_PCI

548

struct udevice *bus;

559

struct udevice *bus;

549

struct udevice *ctlr;

560

struct udevice *ctlr;

550

#else

561

#else

551

struct pci_controller *next;

562

struct pci_controller *next;

552

#endif

563

#endif

553

564

554

int first_busno;

565

int first_busno;

555

int last_busno;

566

int last_busno;

556

567

557

volatile unsigned int *cfg_addr;

568

volatile unsigned int *cfg_addr;

558

volatile unsigned char *cfg_data;

569

volatile unsigned char *cfg_data;

559

570

560

int indirect_type;

571

int indirect_type;

561

572

562

/*

573

/*

563

* TODO(sjg@chromium.org): With driver model we use struct

574

* TODO(sjg@chromium.org): With driver model we use struct

564

* pci_controller for both the controller and any bridge devices

575

* pci_controller for both the controller and any bridge devices

565

* attached to it. But there is only one region list and it is in the

576

* attached to it. But there is only one region list and it is in the

566

* top-level controller.

577

* top-level controller.

567

*

578

*

568

* This could be changed so that struct pci_controller is only used

579

* This could be changed so that struct pci_controller is only used

569

* for PCI controllers and a separate UCLASS (or perhaps

580

* for PCI controllers and a separate UCLASS (or perhaps

570

* UCLASS_PCI_GENERIC) is used for bridges.

581

* UCLASS_PCI_GENERIC) is used for bridges.

571

*/

582

*/

572

struct pci_region regions[MAX_PCI_REGIONS];

583

struct pci_region regions[MAX_PCI_REGIONS];

573

int region_count;

584

int region_count;

574

585

575

struct pci_config_table *config_table;

586

struct pci_config_table *config_table;

576

587

577

void (*fixup_irq)(struct pci_controller *, pci_dev_t);

588

void (*fixup_irq)(struct pci_controller *, pci_dev_t);

578

#ifndef CONFIG_DM_PCI

589

#ifndef CONFIG_DM_PCI

579

/* Low-level architecture-dependent routines */

590

/* Low-level architecture-dependent routines */

580

int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);

591

int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);

581

int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);

592

int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);

582

int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);

593

int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);

583

int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);

594

int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);

584

int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);

595

int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);

585

int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);

596

int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);

586

#endif

597

#endif

587

598

588

/* Used by auto config */

599

/* Used by auto config */

589

struct pci_region *pci_mem, *pci_io, *pci_prefetch;

600

struct pci_region *pci_mem, *pci_io, *pci_prefetch;

590

601

591

#ifndef CONFIG_DM_PCI

602

#ifndef CONFIG_DM_PCI

592

int current_busno;

603

int current_busno;

593

604

594

void *priv_data;

605

void *priv_data;

595

#endif

606

#endif

596

};

607

};

597

608

598

#ifndef CONFIG_DM_PCI

609

#ifndef CONFIG_DM_PCI

599

static inline void pci_set_ops(struct pci_controller *hose,

610

static inline void pci_set_ops(struct pci_controller *hose,

600

int (*read_byte)(struct pci_controller*,

611

int (*read_byte)(struct pci_controller*,

601

pci_dev_t, int where, u8 *),

612

pci_dev_t, int where, u8 *),

602

int (*read_word)(struct pci_controller*,

613

int (*read_word)(struct pci_controller*,

603

pci_dev_t, int where, u16 *),

614

pci_dev_t, int where, u16 *),

604

int (*read_dword)(struct pci_controller*,

615

int (*read_dword)(struct pci_controller*,

605

pci_dev_t, int where, u32 *),

616

pci_dev_t, int where, u32 *),

606

int (*write_byte)(struct pci_controller*,

617

int (*write_byte)(struct pci_controller*,

607

pci_dev_t, int where, u8),

618

pci_dev_t, int where, u8),

608

int (*write_word)(struct pci_controller*,

619

int (*write_word)(struct pci_controller*,

609

pci_dev_t, int where, u16),

620

pci_dev_t, int where, u16),

610

int (*write_dword)(struct pci_controller*,

621

int (*write_dword)(struct pci_controller*,

611

pci_dev_t, int where, u32)) {

622

pci_dev_t, int where, u32)) {

612

hose->read_byte = read_byte;

623

hose->read_byte = read_byte;

613

hose->read_word = read_word;

624

hose->read_word = read_word;

614

hose->read_dword = read_dword;

625

hose->read_dword = read_dword;

615

hose->write_byte = write_byte;

626

hose->write_byte = write_byte;

616

hose->write_word = write_word;

627

hose->write_word = write_word;

617

hose->write_dword = write_dword;

628

hose->write_dword = write_dword;

618

}

629

}

619

#endif

630

#endif

620

631

621

#ifdef CONFIG_PCI_INDIRECT_BRIDGE

632

#ifdef CONFIG_PCI_INDIRECT_BRIDGE

622

extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);

633

extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);

623

#endif

634

#endif

624

635

625

#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)

636

#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)

626

extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,

637

extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,

627

pci_addr_t addr, unsigned long flags);

638

pci_addr_t addr, unsigned long flags);

628

extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,

639

extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,

629

phys_addr_t addr, unsigned long flags);

640

phys_addr_t addr, unsigned long flags);

630

641

631

#define pci_phys_to_bus(dev, addr, flags) \

642

#define pci_phys_to_bus(dev, addr, flags) \

632

pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))

643

pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))

633

#define pci_bus_to_phys(dev, addr, flags) \

644

#define pci_bus_to_phys(dev, addr, flags) \

634

pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))

645

pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))

635

646

636

#define pci_virt_to_bus(dev, addr, flags) \

647

#define pci_virt_to_bus(dev, addr, flags) \

637

pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \

648

pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \

638

(virt_to_phys(addr)), (flags))

649

(virt_to_phys(addr)), (flags))

639

#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \

650

#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \

640

map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \

651

map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \

641

(addr), (flags)), \

652

(addr), (flags)), \

642

(len), (map_flags))

653

(len), (map_flags))

643

654

644

#define pci_phys_to_mem(dev, addr) \

655

#define pci_phys_to_mem(dev, addr) \

645

pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)

656

pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)

646

#define pci_mem_to_phys(dev, addr) \

657

#define pci_mem_to_phys(dev, addr) \

647

pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)

658

pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)

648

#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)

659

#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)

649

#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)

660

#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)

650

661

651

#define pci_virt_to_mem(dev, addr) \

662

#define pci_virt_to_mem(dev, addr) \

652

pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)

663

pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)

653

#define pci_mem_to_virt(dev, addr, len, map_flags) \

664

#define pci_mem_to_virt(dev, addr, len, map_flags) \

654

pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))

665

pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))

655

#define pci_virt_to_io(dev, addr) \

666

#define pci_virt_to_io(dev, addr) \

656

pci_virt_to_bus((dev), (addr), PCI_REGION_IO)

667

pci_virt_to_bus((dev), (addr), PCI_REGION_IO)

657

#define pci_io_to_virt(dev, addr, len, map_flags) \

668

#define pci_io_to_virt(dev, addr, len, map_flags) \

658

pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))

669

pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))

659

670

660

/* For driver model these are defined in macros in pci_compat.c */

671

/* For driver model these are defined in macros in pci_compat.c */

661

extern int pci_hose_read_config_byte(struct pci_controller *hose,

672

extern int pci_hose_read_config_byte(struct pci_controller *hose,

662

pci_dev_t dev, int where, u8 *val);

673

pci_dev_t dev, int where, u8 *val);

663

extern int pci_hose_read_config_word(struct pci_controller *hose,

674

extern int pci_hose_read_config_word(struct pci_controller *hose,

664

pci_dev_t dev, int where, u16 *val);

675

pci_dev_t dev, int where, u16 *val);

665

extern int pci_hose_read_config_dword(struct pci_controller *hose,

676

extern int pci_hose_read_config_dword(struct pci_controller *hose,

666

pci_dev_t dev, int where, u32 *val);

677

pci_dev_t dev, int where, u32 *val);

667

extern int pci_hose_write_config_byte(struct pci_controller *hose,

678

extern int pci_hose_write_config_byte(struct pci_controller *hose,

668

pci_dev_t dev, int where, u8 val);

679

pci_dev_t dev, int where, u8 val);

669

extern int pci_hose_write_config_word(struct pci_controller *hose,

680

extern int pci_hose_write_config_word(struct pci_controller *hose,

670

pci_dev_t dev, int where, u16 val);

681

pci_dev_t dev, int where, u16 val);

671

extern int pci_hose_write_config_dword(struct pci_controller *hose,

682

extern int pci_hose_write_config_dword(struct pci_controller *hose,

672

pci_dev_t dev, int where, u32 val);

683

pci_dev_t dev, int where, u32 val);

673

#endif

684

#endif

674

685

675

#ifndef CONFIG_DM_PCI

686

#ifndef CONFIG_DM_PCI

676

extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);

687

extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);

677

extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);

688

extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);

678

extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);

689

extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);

679

extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);

690

extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);

680

extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);

691

extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);

681

extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);

692

extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);

682

#endif

693

#endif

683

694

684

void pciauto_region_init(struct pci_region *res);

695

void pciauto_region_init(struct pci_region *res);

685

void pciauto_region_align(struct pci_region *res, pci_size_t size);

696

void pciauto_region_align(struct pci_region *res, pci_size_t size);

686

void pciauto_config_init(struct pci_controller *hose);

697

void pciauto_config_init(struct pci_controller *hose);

687

698

688

/**

699

/**

689

* pciauto_region_allocate() - Allocate resources from a PCI resource region

700

* pciauto_region_allocate() - Allocate resources from a PCI resource region

690

*

701

*

691

* Allocates @size bytes from the PCI resource @res. If @supports_64bit is

702

* Allocates @size bytes from the PCI resource @res. If @supports_64bit is

692

* false, the result will be guaranteed to fit in 32 bits.

703

* false, the result will be guaranteed to fit in 32 bits.

693

*

704

*

694

* @res: PCI region to allocate from

705

* @res: PCI region to allocate from

695

* @size: Amount of bytes to allocate

706

* @size: Amount of bytes to allocate

696

* @bar: Returns the PCI bus address of the allocated resource

707

* @bar: Returns the PCI bus address of the allocated resource

697

* @supports_64bit: Whether to allow allocations above the 32-bit boundary

708

* @supports_64bit: Whether to allow allocations above the 32-bit boundary

698

* @return 0 if successful, -1 on failure

709

* @return 0 if successful, -1 on failure

699

*/

710

*/

700

int pciauto_region_allocate(struct pci_region *res, pci_size_t size,

711

int pciauto_region_allocate(struct pci_region *res, pci_size_t size,

701

pci_addr_t *bar, bool supports_64bit);

712

pci_addr_t *bar, bool supports_64bit);

702

713

703

#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)

714

#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)

704

extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,

715

extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,

705

pci_dev_t dev, int where, u8 *val);

716

pci_dev_t dev, int where, u8 *val);

706

extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,

717

extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,

707

pci_dev_t dev, int where, u16 *val);

718

pci_dev_t dev, int where, u16 *val);

708

extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,

719

extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,

709

pci_dev_t dev, int where, u8 val);

720

pci_dev_t dev, int where, u8 val);

710

extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,

721

extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,

711

pci_dev_t dev, int where, u16 val);

722

pci_dev_t dev, int where, u16 val);

712

723

713

extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);

724

extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);

714

extern void pci_register_hose(struct pci_controller* hose);

725

extern void pci_register_hose(struct pci_controller* hose);

715

extern struct pci_controller* pci_bus_to_hose(int bus);

726

extern struct pci_controller* pci_bus_to_hose(int bus);

716

extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);

727

extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);

717

extern struct pci_controller *pci_get_hose_head(void);

728

extern struct pci_controller *pci_get_hose_head(void);

718

729

719

extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);

730

extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);

720

extern int pci_hose_scan(struct pci_controller *hose);

731

extern int pci_hose_scan(struct pci_controller *hose);

721

extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);

732

extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);

722

733

723

extern void pciauto_setup_device(struct pci_controller *hose,

734

extern void pciauto_setup_device(struct pci_controller *hose,

724

pci_dev_t dev, int bars_num,

735

pci_dev_t dev, int bars_num,

725

struct pci_region *mem,

736

struct pci_region *mem,

726

struct pci_region *prefetch,

737

struct pci_region *prefetch,

727

struct pci_region *io);

738

struct pci_region *io);

728

extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,

739

extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,

729

pci_dev_t dev, int sub_bus);

740

pci_dev_t dev, int sub_bus);

730

extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,

741

extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,

731

pci_dev_t dev, int sub_bus);

742

pci_dev_t dev, int sub_bus);

732

extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);

743

extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);

733

744

734

extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);

745

extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);

735

extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);

746

extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);

736

pci_dev_t pci_find_class(unsigned int find_class, int index);

747

pci_dev_t pci_find_class(unsigned int find_class, int index);

737

748

738

extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,

749

extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,

739

int cap);

750

int cap);

740

extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,

751

extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,

741

u8 hdr_type);

752

u8 hdr_type);

742

extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,

753

extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,

743

int cap);

754

int cap);

744

755

745

int pci_find_next_ext_capability(struct pci_controller *hose,

756

int pci_find_next_ext_capability(struct pci_controller *hose,

746

pci_dev_t dev, int start, int cap);

757

pci_dev_t dev, int start, int cap);

747

int pci_hose_find_ext_capability(struct pci_controller *hose,

758

int pci_hose_find_ext_capability(struct pci_controller *hose,

748

pci_dev_t dev, int cap);

759

pci_dev_t dev, int cap);

749

760

750

#ifdef CONFIG_PCI_FIXUP_DEV

761

#ifdef CONFIG_PCI_FIXUP_DEV

751

extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,

762

extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,

752

unsigned short vendor,

763

unsigned short vendor,

753

unsigned short device,

764

unsigned short device,

754

unsigned short class);

765

unsigned short class);

755

#endif

766

#endif

756

#endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */

767

#endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */

757

768

758

const char * pci_class_str(u8 class);

769

const char * pci_class_str(u8 class);

759

int pci_last_busno(void);

770

int pci_last_busno(void);

760

771

761

#ifdef CONFIG_MPC85xx

772

#ifdef CONFIG_MPC85xx

762

extern void pci_mpc85xx_init (struct pci_controller *hose);

773

extern void pci_mpc85xx_init (struct pci_controller *hose);

763

#endif

774

#endif

764

775

765

#ifdef CONFIG_PCIE_IMX

776

#ifdef CONFIG_PCIE_IMX

766

extern void imx_pcie_remove(void);

777

extern void imx_pcie_remove(void);

767

#endif

778

#endif

768

779

769

#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)

780

#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)

770

/**

781

/**

771

* pci_write_bar32() - Write the address of a BAR including control bits

782

* pci_write_bar32() - Write the address of a BAR including control bits

772

*

783

*

773

* This writes a raw address (with control bits) to a bar. This can be used

784

* This writes a raw address (with control bits) to a bar. This can be used

774

* with devices which require hard-coded addresses, not part of the normal

785

* with devices which require hard-coded addresses, not part of the normal

775

* PCI enumeration process.

786

* PCI enumeration process.

776

*

787

*

777

* @hose: PCI hose to use

788

* @hose: PCI hose to use

778

* @dev: PCI device to update

789

* @dev: PCI device to update

779

* @barnum: BAR number (0-5)

790

* @barnum: BAR number (0-5)

780

* @addr: BAR address with control bits

791

* @addr: BAR address with control bits

781

*/

792

*/

782

void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,

793

void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,

783

u32 addr);

794

u32 addr);

784

795

785

/**

796

/**

786

* pci_read_bar32() - read the address of a bar

797

* pci_read_bar32() - read the address of a bar

787

*

798

*

788

* @hose: PCI hose to use

799

* @hose: PCI hose to use

789

* @dev: PCI device to inspect

800

* @dev: PCI device to inspect

790

* @barnum: BAR number (0-5)

801

* @barnum: BAR number (0-5)

791

* @return address of the bar, masking out any control bits

802

* @return address of the bar, masking out any control bits

792

* */

803

* */

793

u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);

804

u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);

794

805

795

/**

806

/**

796

* pci_hose_find_devices() - Find devices by vendor/device ID

807

* pci_hose_find_devices() - Find devices by vendor/device ID

797

*

808

*

798

* @hose: PCI hose to search

809

* @hose: PCI hose to search

799

* @busnum: Bus number to search

810

* @busnum: Bus number to search

800

* @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record

811

* @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record

801

* @indexp: Pointer to device index to find. To find the first matching

812

* @indexp: Pointer to device index to find. To find the first matching

802

* device, pass 0; to find the second, pass 1, etc. This

813

* device, pass 0; to find the second, pass 1, etc. This

803

* parameter is decremented for each non-matching device so

814

* parameter is decremented for each non-matching device so

804

* can be called repeatedly.

815

* can be called repeatedly.

805

*/

816

*/

806

pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,

817

pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,

807

struct pci_device_id *ids, int *indexp);

818

struct pci_device_id *ids, int *indexp);

808

#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */

819

#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */

809

820

810

/* Access sizes for PCI reads and writes */

821

/* Access sizes for PCI reads and writes */

811

enum pci_size_t {

822

enum pci_size_t {

812

PCI_SIZE_8,

823

PCI_SIZE_8,

813

PCI_SIZE_16,

824

PCI_SIZE_16,

814

PCI_SIZE_32,

825

PCI_SIZE_32,

815

};

826

};

816

827

817

struct udevice;

828

struct udevice;

818

829

819

#ifdef CONFIG_DM_PCI

830

#ifdef CONFIG_DM_PCI

820

/**

831

/**

821

* struct pci_child_platdata - information stored about each PCI device

832

* struct pci_child_platdata - information stored about each PCI device

822

*

833

*

823

* Every device on a PCI bus has this per-child data.

834

* Every device on a PCI bus has this per-child data.

824

*

835

*

825

* It can be accessed using dev_get_parent_platdata(dev) if dev->parent is a

836

* It can be accessed using dev_get_parent_platdata(dev) if dev->parent is a

826

* PCI bus (i.e. UCLASS_PCI)

837

* PCI bus (i.e. UCLASS_PCI)

827

*

838

*

828

* @devfn: Encoded device and function index - see PCI_DEVFN()

839

* @devfn: Encoded device and function index - see PCI_DEVFN()

829

* @vendor: PCI vendor ID (see pci_ids.h)

840

* @vendor: PCI vendor ID (see pci_ids.h)

830

* @device: PCI device ID (see pci_ids.h)

841

* @device: PCI device ID (see pci_ids.h)

831

* @class: PCI class, 3 bytes: (base, sub, prog-if)

842

* @class: PCI class, 3 bytes: (base, sub, prog-if)

832

*/

843

*/

833

struct pci_child_platdata {

844

struct pci_child_platdata {

834

int devfn;

845

int devfn;

835

unsigned short vendor;

846

unsigned short vendor;

836

unsigned short device;

847

unsigned short device;

837

unsigned int class;

848

unsigned int class;

838

};

849

};

839

850

840

/* PCI bus operations */

851

/* PCI bus operations */

841

struct dm_pci_ops {

852

struct dm_pci_ops {

842

/**

853

/**

843

* read_config() - Read a PCI configuration value

854

* read_config() - Read a PCI configuration value

844

*

855

*

845

* PCI buses must support reading and writing configuration values

856

* PCI buses must support reading and writing configuration values

846

* so that the bus can be scanned and its devices configured.

857

* so that the bus can be scanned and its devices configured.

847

*

858

*

848

* Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always.

859

* Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always.

849

* If bridges exist it is possible to use the top-level bus to

860

* If bridges exist it is possible to use the top-level bus to

850

* access a sub-bus. In that case @bus will be the top-level bus

861

* access a sub-bus. In that case @bus will be the top-level bus

851

* and PCI_BUS(bdf) will be a different (higher) value

862

* and PCI_BUS(bdf) will be a different (higher) value

852

*

863

*

853

* @bus: Bus to read from

864

* @bus: Bus to read from

854

* @bdf: Bus, device and function to read

865

* @bdf: Bus, device and function to read

855

* @offset: Byte offset within the device's configuration space

866

* @offset: Byte offset within the device's configuration space

856

* @valuep: Place to put the returned value

867

* @valuep: Place to put the returned value

857

* @size: Access size

868

* @size: Access size

858

* @return 0 if OK, -ve on error

869

* @return 0 if OK, -ve on error

859

*/

870

*/

860

int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset,

871

int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset,

861

ulong *valuep, enum pci_size_t size);

872

ulong *valuep, enum pci_size_t size);

862

/**

873

/**

863

* write_config() - Write a PCI configuration value

874

* write_config() - Write a PCI configuration value

864

*

875

*

865

* @bus: Bus to write to

876

* @bus: Bus to write to

866

* @bdf: Bus, device and function to write

877

* @bdf: Bus, device and function to write

867

* @offset: Byte offset within the device's configuration space

878

* @offset: Byte offset within the device's configuration space

868

* @value: Value to write

879

* @value: Value to write

869

* @size: Access size

880

* @size: Access size

870

* @return 0 if OK, -ve on error

881

* @return 0 if OK, -ve on error

871

*/

882

*/

872

int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,

883

int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,

873

ulong value, enum pci_size_t size);

884

ulong value, enum pci_size_t size);

874

};

885

};

875

886

876

/* Get access to a PCI bus' operations */

887

/* Get access to a PCI bus' operations */

877

#define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)

888

#define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)

878

889

879

/**

890

/**

880

* dm_pci_get_bdf() - Get the BDF value for a device

891

* dm_pci_get_bdf() - Get the BDF value for a device

881

*

892

*

882

* @dev: Device to check

893

* @dev: Device to check

883

* @return bus/device/function value (see PCI_BDF())

894

* @return bus/device/function value (see PCI_BDF())

884

*/

895

*/

885

pci_dev_t dm_pci_get_bdf(struct udevice *dev);

896

pci_dev_t dm_pci_get_bdf(struct udevice *dev);

886

897

887

/**

898

/**

888

* pci_bind_bus_devices() - scan a PCI bus and bind devices

899

* pci_bind_bus_devices() - scan a PCI bus and bind devices

889

*

900

*

890

* Scan a PCI bus looking for devices. Bind each one that is found. If

901

* Scan a PCI bus looking for devices. Bind each one that is found. If

891

* devices are already bound that match the scanned devices, just update the

902

* devices are already bound that match the scanned devices, just update the

892

* child data so that the device can be used correctly (this happens when

903

* child data so that the device can be used correctly (this happens when

893

* the device tree describes devices we expect to see on the bus).

904

* the device tree describes devices we expect to see on the bus).

894

*

905

*

895

* Devices that are bound in this way will use a generic PCI driver which

906

* Devices that are bound in this way will use a generic PCI driver which

896

* does nothing. The device can still be accessed but will not provide any

907

* does nothing. The device can still be accessed but will not provide any

897

* driver interface.

908

* driver interface.

898

*

909

*

899

* @bus: Bus containing devices to bind

910

* @bus: Bus containing devices to bind

900

* @return 0 if OK, -ve on error

911

* @return 0 if OK, -ve on error

901

*/

912

*/

902

int pci_bind_bus_devices(struct udevice *bus);

913

int pci_bind_bus_devices(struct udevice *bus);

903

914

904

/**

915

/**

905

* pci_auto_config_devices() - configure bus devices ready for use

916

* pci_auto_config_devices() - configure bus devices ready for use

906

*

917

*

907

* This works through all devices on a bus by scanning the driver model

918

* This works through all devices on a bus by scanning the driver model

908

* data structures (normally these have been set up by pci_bind_bus_devices()

919

* data structures (normally these have been set up by pci_bind_bus_devices()

909

* earlier).

920

* earlier).

910

*

921

*

911

* Space is allocated for each PCI base address register (BAR) so that the

922

* Space is allocated for each PCI base address register (BAR) so that the

912

* devices are mapped into memory and I/O space ready for use.

923

* devices are mapped into memory and I/O space ready for use.

913

*

924

*

914

* @bus: Bus containing devices to bind

925

* @bus: Bus containing devices to bind

915

* @return 0 if OK, -ve on error

926

* @return 0 if OK, -ve on error

916

*/

927

*/

917

int pci_auto_config_devices(struct udevice *bus);

928

int pci_auto_config_devices(struct udevice *bus);

918

929

919

/**

930

/**

920

* dm_pci_bus_find_bdf() - Find a device given its PCI bus address

931

* dm_pci_bus_find_bdf() - Find a device given its PCI bus address

921

*

932

*

922

* @bdf: PCI device address: bus, device and function -see PCI_BDF()

933

* @bdf: PCI device address: bus, device and function -see PCI_BDF()

923

* @devp: Returns the device for this address, if found

934

* @devp: Returns the device for this address, if found

924

* @return 0 if OK, -ENODEV if not found

935

* @return 0 if OK, -ENODEV if not found

925

*/

936

*/

926

int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);

937

int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);

927

938

928

/**

939

/**

929

* pci_bus_find_devfn() - Find a device on a bus

940

* pci_bus_find_devfn() - Find a device on a bus

930

*

941

*

931

* @find_devfn: PCI device address (device and function only)

942

* @find_devfn: PCI device address (device and function only)

932

* @devp: Returns the device for this address, if found

943

* @devp: Returns the device for this address, if found

933

* @return 0 if OK, -ENODEV if not found

944

* @return 0 if OK, -ENODEV if not found

934

*/

945

*/

935

int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,

946

int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,

936

struct udevice **devp);

947

struct udevice **devp);

937

948

938

/**

949

/**

939

* pci_find_first_device() - return the first available PCI device

950

* pci_find_first_device() - return the first available PCI device

940

*

951

*

941

* This function and pci_find_first_device() allow iteration through all

952

* This function and pci_find_first_device() allow iteration through all

942

* available PCI devices on all buses. Assuming there are any, this will

953

* available PCI devices on all buses. Assuming there are any, this will

943

* return the first one.

954

* return the first one.

944

*

955

*

945

* @devp: Set to the first available device, or NULL if no more are left

956

* @devp: Set to the first available device, or NULL if no more are left

946

* or we got an error

957

* or we got an error

947

* @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)

958

* @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)

948

*/

959

*/

949

int pci_find_first_device(struct udevice **devp);

960

int pci_find_first_device(struct udevice **devp);

950

961

951

/**

962

/**

952

* pci_find_next_device() - return the next available PCI device

963

* pci_find_next_device() - return the next available PCI device

953

*

964

*

954

* Finds the next available PCI device after the one supplied, or sets @devp

965

* Finds the next available PCI device after the one supplied, or sets @devp

955

* to NULL if there are no more.

966

* to NULL if there are no more.

956

*

967

*

957

* @devp: On entry, the last device returned. Set to the next available

968

* @devp: On entry, the last device returned. Set to the next available

958

* device, or NULL if no more are left or we got an error

969

* device, or NULL if no more are left or we got an error

959

* @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)

970

* @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)

960

*/

971

*/

961

int pci_find_next_device(struct udevice **devp);

972

int pci_find_next_device(struct udevice **devp);

962

973

963

/**

974

/**

964

* pci_get_ff() - Returns a mask for the given access size

975

* pci_get_ff() - Returns a mask for the given access size

965

*

976

*

966

* @size: Access size

977

* @size: Access size

967

* @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for

978

* @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for

968

* PCI_SIZE_32

979

* PCI_SIZE_32

969

*/

980

*/

970

int pci_get_ff(enum pci_size_t size);

981

int pci_get_ff(enum pci_size_t size);

971

982

972

/**

983

/**

973

* pci_bus_find_devices () - Find devices on a bus

984

* pci_bus_find_devices () - Find devices on a bus

974

*

985

*

975

* @bus: Bus to search

986

* @bus: Bus to search

976

* @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record

987

* @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record

977

* @indexp: Pointer to device index to find. To find the first matching

988

* @indexp: Pointer to device index to find. To find the first matching

978

* device, pass 0; to find the second, pass 1, etc. This

989

* device, pass 0; to find the second, pass 1, etc. This

979

* parameter is decremented for each non-matching device so

990

* parameter is decremented for each non-matching device so

980

* can be called repeatedly.

991

* can be called repeatedly.

981

* @devp: Returns matching device if found

992

* @devp: Returns matching device if found

982

* @return 0 if found, -ENODEV if not

993

* @return 0 if found, -ENODEV if not

983

*/

994

*/

984

int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,

995

int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,

985

int *indexp, struct udevice **devp);

996

int *indexp, struct udevice **devp);

986

997

987

/**

998

/**

988

* pci_find_device_id() - Find a device on any bus

999

* pci_find_device_id() - Find a device on any bus

989

*

1000

*

990

* @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record

1001

* @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record

991

* @index: Index number of device to find, 0 for the first match, 1 for

1002

* @index: Index number of device to find, 0 for the first match, 1 for

992

* the second, etc.

1003

* the second, etc.

993

* @devp: Returns matching device if found

1004

* @devp: Returns matching device if found

994

* @return 0 if found, -ENODEV if not

1005

* @return 0 if found, -ENODEV if not

995

*/

1006

*/

996

int pci_find_device_id(struct pci_device_id *ids, int index,

1007

int pci_find_device_id(struct pci_device_id *ids, int index,

997

struct udevice **devp);

1008

struct udevice **devp);

998

1009

999

/**

1010

/**

1000

* dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices

1011

* dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices

1001

*

1012

*

1002

* This probes the given bus which causes it to be scanned for devices. The

1013

* This probes the given bus which causes it to be scanned for devices. The

1003

* devices will be bound but not probed.

1014

* devices will be bound but not probed.

1004

*

1015

*

1005

* @hose specifies the PCI hose that will be used for the scan. This is

1016

* @hose specifies the PCI hose that will be used for the scan. This is

1006

* always a top-level bus with uclass UCLASS_PCI. The bus to scan is

1017

* always a top-level bus with uclass UCLASS_PCI. The bus to scan is

1007

* in @bdf, and is a subordinate bus reachable from @hose.

1018

* in @bdf, and is a subordinate bus reachable from @hose.

1008

*

1019

*

1009

* @hose: PCI hose to scan

1020

* @hose: PCI hose to scan

1010

* @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)

1021

* @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)

1011

* @return 0 if OK, -ve on error

1022

* @return 0 if OK, -ve on error

1012

*/

1023

*/

1013

int dm_pci_hose_probe_bus(struct udevice *bus);

1024

int dm_pci_hose_probe_bus(struct udevice *bus);

1014

1025

1015

/**

1026

/**

1016

* pci_bus_read_config() - Read a configuration value from a device

1027

* pci_bus_read_config() - Read a configuration value from a device

1017

*

1028

*

1018

* TODO(sjg@chromium.org): We should be able to pass just a device and have

1029

* TODO(sjg@chromium.org): We should be able to pass just a device and have

1019

* it do the right thing. It would be good to have that function also.

1030

* it do the right thing. It would be good to have that function also.

1020

*

1031

*

1021

* @bus: Bus to read from

1032

* @bus: Bus to read from

1022

* @bdf: PCI device address: bus, device and function -see PCI_BDF()

1033

* @bdf: PCI device address: bus, device and function -see PCI_BDF()

1023

* @offset: Register offset to read

1034

* @offset: Register offset to read

1024

* @valuep: Place to put the returned value

1035

* @valuep: Place to put the returned value

1025

* @size: Access size

1036

* @size: Access size

1026

* @return 0 if OK, -ve on error

1037

* @return 0 if OK, -ve on error

1027

*/

1038

*/

1028

int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,

1039

int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,

1029

unsigned long *valuep, enum pci_size_t size);

1040

unsigned long *valuep, enum pci_size_t size);

1030

1041

1031

/**

1042

/**

1032

* pci_bus_write_config() - Write a configuration value to a device

1043

* pci_bus_write_config() - Write a configuration value to a device

1033

*

1044

*

1034

* @bus: Bus to write from

1045

* @bus: Bus to write from

1035

* @bdf: PCI device address: bus, device and function -see PCI_BDF()

1046

* @bdf: PCI device address: bus, device and function -see PCI_BDF()

1036

* @offset: Register offset to write

1047

* @offset: Register offset to write

1037

* @value: Value to write

1048

* @value: Value to write

1038

* @size: Access size

1049

* @size: Access size

1039

* @return 0 if OK, -ve on error

1050

* @return 0 if OK, -ve on error

1040

*/

1051

*/

1041

int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,

1052

int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,

1042

unsigned long value, enum pci_size_t size);

1053

unsigned long value, enum pci_size_t size);

1043

1054

1044

/**

1055

/**

1045

* pci_bus_clrset_config32() - Update a configuration value for a device

1056

* pci_bus_clrset_config32() - Update a configuration value for a device

1046

*

1057

*

1047

* The register at @offset is updated to (oldvalue & ~clr) | set.

1058

* The register at @offset is updated to (oldvalue & ~clr) | set.

1048

*

1059

*

1049

* @bus: Bus to access

1060

* @bus: Bus to access

1050

* @bdf: PCI device address: bus, device and function -see PCI_BDF()

1061

* @bdf: PCI device address: bus, device and function -see PCI_BDF()

1051

* @offset: Register offset to update

1062

* @offset: Register offset to update

1052

* @clr: Bits to clear

1063

* @clr: Bits to clear

1053

* @set: Bits to set

1064

* @set: Bits to set

1054

* @return 0 if OK, -ve on error

1065

* @return 0 if OK, -ve on error

1055

*/

1066

*/

1056

int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,

1067

int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,

1057

u32 clr, u32 set);

1068

u32 clr, u32 set);

1058

1069

1059

/**

1070

/**

1060

* Driver model PCI config access functions. Use these in preference to others

1071

* Driver model PCI config access functions. Use these in preference to others

1061

* when you have a valid device

1072

* when you have a valid device

1062

*/

1073

*/

1063

int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,

1074

int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,

1064

enum pci_size_t size);

1075

enum pci_size_t size);

1065

1076

1066

int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep);

1077

int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep);

1067

int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep);

1078

int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep);

1068

int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep);

1079

int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep);

1069

1080

1070

int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,

1081

int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,

1071

enum pci_size_t size);

1082

enum pci_size_t size);

1072

1083

1073

int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);

1084

int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);

1074

int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);

1085

int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);

1075

int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);

1086

int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);

1076

1087

1077

/**

1088

/**

1078

* These permit convenient read/modify/write on PCI configuration. The

1089

* These permit convenient read/modify/write on PCI configuration. The

1079

* register is updated to (oldvalue & ~clr) | set.

1090

* register is updated to (oldvalue & ~clr) | set.

1080

*/

1091

*/

1081

int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);

1092

int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);

1082

int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);

1093

int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);

1083

int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);

1094

int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);

1084

1095

1085

/*

1096

/*

1086

* The following functions provide access to the above without needing the

1097

* The following functions provide access to the above without needing the

1087

* size parameter. We are trying to encourage the use of the 8/16/32-style

1098

* size parameter. We are trying to encourage the use of the 8/16/32-style

1088

* functions, rather than byte/word/dword. But both are supported.

1099

* functions, rather than byte/word/dword. But both are supported.

1089

*/

1100

*/

1090

int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);

1101

int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);

1091

int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);

1102

int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);

1092

int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);

1103

int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);

1093

int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);

1104

int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);

1094

int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);

1105

int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);

1095

int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);

1106

int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);

1096

1107

1097

/**

1108

/**

1098

* pci_generic_mmap_write_config() - Generic helper for writing to

1109

* pci_generic_mmap_write_config() - Generic helper for writing to

1099

* memory-mapped PCI configuration space.

1110

* memory-mapped PCI configuration space.

1100

* @bus: Pointer to the PCI bus

1111

* @bus: Pointer to the PCI bus

1101

* @addr_f: Callback for calculating the config space address

1112

* @addr_f: Callback for calculating the config space address

1102

* @bdf: Identifies the PCI device to access

1113

* @bdf: Identifies the PCI device to access

1103

* @offset: The offset into the device's configuration space

1114

* @offset: The offset into the device's configuration space

1104

* @value: The value to write

1115

* @value: The value to write

1105

* @size: Indicates the size of access to perform

1116

* @size: Indicates the size of access to perform

1106

*

1117

*

1107

* Write the value @value of size @size from offset @offset within the

1118

* Write the value @value of size @size from offset @offset within the

1108

* configuration space of the device identified by the bus, device & function

1119

* configuration space of the device identified by the bus, device & function

1109

* numbers in @bdf on the PCI bus @bus. The callback function @addr_f is

1120

* numbers in @bdf on the PCI bus @bus. The callback function @addr_f is

1110

* responsible for calculating the CPU address of the respective configuration

1121

* responsible for calculating the CPU address of the respective configuration

1111

* space offset.

1122

* space offset.

1112

*

1123

*

1113

* Return: 0 on success, else -EINVAL

1124

* Return: 0 on success, else -EINVAL

1114

*/

1125

*/

1115

int pci_generic_mmap_write_config(

1126

int pci_generic_mmap_write_config(

1116

struct udevice *bus,

1127

struct udevice *bus,

1117

int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),

1128

int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),

1118

pci_dev_t bdf,

1129

pci_dev_t bdf,

1119

uint offset,

1130

uint offset,

1120

ulong value,

1131

ulong value,

1121

enum pci_size_t size);

1132

enum pci_size_t size);

1122

1133

1123

/**

1134

/**

1124

* pci_generic_mmap_read_config() - Generic helper for reading from

1135

* pci_generic_mmap_read_config() - Generic helper for reading from

1125

* memory-mapped PCI configuration space.

1136

* memory-mapped PCI configuration space.

1126

* @bus: Pointer to the PCI bus

1137

* @bus: Pointer to the PCI bus

1127

* @addr_f: Callback for calculating the config space address

1138

* @addr_f: Callback for calculating the config space address

1128

* @bdf: Identifies the PCI device to access

1139

* @bdf: Identifies the PCI device to access

1129

* @offset: The offset into the device's configuration space

1140

* @offset: The offset into the device's configuration space

1130

* @valuep: A pointer at which to store the read value

1141

* @valuep: A pointer at which to store the read value

1131

* @size: Indicates the size of access to perform

1142

* @size: Indicates the size of access to perform

1132

*

1143

*

1133

* Read a value of size @size from offset @offset within the configuration

1144

* Read a value of size @size from offset @offset within the configuration

1134

* space of the device identified by the bus, device & function numbers in @bdf

1145

* space of the device identified by the bus, device & function numbers in @bdf

1135

* on the PCI bus @bus. The callback function @addr_f is responsible for

1146

* on the PCI bus @bus. The callback function @addr_f is responsible for

1136

* calculating the CPU address of the respective configuration space offset.

1147

* calculating the CPU address of the respective configuration space offset.

1137

*

1148

*

1138

* Return: 0 on success, else -EINVAL

1149

* Return: 0 on success, else -EINVAL

1139

*/

1150

*/

1140

int pci_generic_mmap_read_config(

1151

int pci_generic_mmap_read_config(

1141

struct udevice *bus,

1152

struct udevice *bus,

1142

int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),

1153

int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),

1143

pci_dev_t bdf,

1154

pci_dev_t bdf,

1144

uint offset,

1155

uint offset,

1145

ulong *valuep,

1156

ulong *valuep,

1146

enum pci_size_t size);

1157

enum pci_size_t size);

1147

1158

1148

#ifdef CONFIG_DM_PCI_COMPAT

1159

#ifdef CONFIG_DM_PCI_COMPAT

1149

/* Compatibility with old naming */

1160

/* Compatibility with old naming */

1150

static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,

1161

static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,

1151

u32 value)

1162

u32 value)

1152

{

1163

{

1153

return pci_write_config32(pcidev, offset, value);

1164

return pci_write_config32(pcidev, offset, value);

1154

}

1165

}

1155

1166

1156

/* Compatibility with old naming */

1167

/* Compatibility with old naming */

1157

static inline int pci_write_config_word(pci_dev_t pcidev, int offset,

1168

static inline int pci_write_config_word(pci_dev_t pcidev, int offset,

1158

u16 value)

1169

u16 value)

1159

{

1170

{

1160

return pci_write_config16(pcidev, offset, value);

1171

return pci_write_config16(pcidev, offset, value);

1161

}

1172

}

1162

1173

1163

/* Compatibility with old naming */

1174

/* Compatibility with old naming */

1164

static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,

1175

static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,

1165

u8 value)

1176

u8 value)

1166

{

1177

{

1167

return pci_write_config8(pcidev, offset, value);

1178

return pci_write_config8(pcidev, offset, value);

1168

}

1179

}

1169

1180

1170

/* Compatibility with old naming */

1181

/* Compatibility with old naming */

1171

static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,

1182

static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,

1172

u32 *valuep)

1183

u32 *valuep)

1173

{

1184

{

1174

return pci_read_config32(pcidev, offset, valuep);

1185

return pci_read_config32(pcidev, offset, valuep);

1175

}

1186

}

1176

1187

1177

/* Compatibility with old naming */

1188

/* Compatibility with old naming */

1178

static inline int pci_read_config_word(pci_dev_t pcidev, int offset,

1189

static inline int pci_read_config_word(pci_dev_t pcidev, int offset,

1179

u16 *valuep)

1190

u16 *valuep)

1180

{

1191

{

1181

return pci_read_config16(pcidev, offset, valuep);

1192

return pci_read_config16(pcidev, offset, valuep);

1182

}

1193

}

1183

1194

1184

/* Compatibility with old naming */

1195

/* Compatibility with old naming */

1185

static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,

1196

static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,

1186

u8 *valuep)

1197

u8 *valuep)

1187

{

1198

{

1188

return pci_read_config8(pcidev, offset, valuep);

1199

return pci_read_config8(pcidev, offset, valuep);

1189

}

1200

}

1190

#endif /* CONFIG_DM_PCI_COMPAT */

1201

#endif /* CONFIG_DM_PCI_COMPAT */

1191

1202

1192

/**

1203

/**

1193

* dm_pciauto_config_device() - configure a device ready for use

1204

* dm_pciauto_config_device() - configure a device ready for use

1194

*

1205

*

1195

* Space is allocated for each PCI base address register (BAR) so that the

1206

* Space is allocated for each PCI base address register (BAR) so that the

1196

* devices are mapped into memory and I/O space ready for use.

1207

* devices are mapped into memory and I/O space ready for use.

1197

*

1208

*

1198

* @dev: Device to configure

1209

* @dev: Device to configure

1199

* @return 0 if OK, -ve on error

1210

* @return 0 if OK, -ve on error

1200

*/

1211

*/

1201

int dm_pciauto_config_device(struct udevice *dev);

1212

int dm_pciauto_config_device(struct udevice *dev);

1202

1213

1203

/**

1214

/**

1204

* pci_conv_32_to_size() - convert a 32-bit read value to the given size

1215

* pci_conv_32_to_size() - convert a 32-bit read value to the given size

1205

*

1216

*

1206

* Some PCI buses must always perform 32-bit reads. The data must then be

1217

* Some PCI buses must always perform 32-bit reads. The data must then be

1207

* shifted and masked to reflect the required access size and offset. This

1218

* shifted and masked to reflect the required access size and offset. This

1208

* function performs this transformation.

1219

* function performs this transformation.

1209

*

1220

*

1210

* @value: Value to transform (32-bit value read from @offset & ~3)

1221

* @value: Value to transform (32-bit value read from @offset & ~3)

1211

* @offset: Register offset that was read

1222

* @offset: Register offset that was read

1212

* @size: Required size of the result

1223

* @size: Required size of the result

1213

* @return the value that would have been obtained if the read had been

1224

* @return the value that would have been obtained if the read had been

1214

* performed at the given offset with the correct size

1225

* performed at the given offset with the correct size

1215

*/

1226

*/

1216

ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);

1227

ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);

1217

1228

1218

/**

1229

/**

1219

* pci_conv_size_to_32() - update a 32-bit value to prepare for a write

1230

* pci_conv_size_to_32() - update a 32-bit value to prepare for a write

1220

*

1231

*

1221

* Some PCI buses must always perform 32-bit writes. To emulate a smaller

1232

* Some PCI buses must always perform 32-bit writes. To emulate a smaller

1222

* write the old 32-bit data must be read, updated with the required new data

1233

* write the old 32-bit data must be read, updated with the required new data

1223

* and written back as a 32-bit value. This function performs the

1234

* and written back as a 32-bit value. This function performs the

1224

* transformation from the old value to the new value.

1235

* transformation from the old value to the new value.

1225

*

1236

*

1226

* @value: Value to transform (32-bit value read from @offset & ~3)

1237

* @value: Value to transform (32-bit value read from @offset & ~3)

1227

* @offset: Register offset that should be written

1238

* @offset: Register offset that should be written

1228

* @size: Required size of the write

1239

* @size: Required size of the write

1229

* @return the value that should be written as a 32-bit access to @offset & ~3.

1240

* @return the value that should be written as a 32-bit access to @offset & ~3.

1230

*/

1241

*/

1231

ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,

1242

ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,

1232

enum pci_size_t size);

1243

enum pci_size_t size);

1233

1244

1234

/**

1245

/**

1235

* pci_get_controller() - obtain the controller to use for a bus

1246

* pci_get_controller() - obtain the controller to use for a bus

1236

*

1247

*

1237

* @dev: Device to check

1248

* @dev: Device to check

1238

* @return pointer to the controller device for this bus

1249

* @return pointer to the controller device for this bus

1239

*/

1250

*/

1240

struct udevice *pci_get_controller(struct udevice *dev);

1251

struct udevice *pci_get_controller(struct udevice *dev);

1241

1252

1242

/**

1253

/**

1243

* pci_get_regions() - obtain pointers to all the region types

1254

* pci_get_regions() - obtain pointers to all the region types

1244

*

1255

*

1245

* @dev: Device to check

1256

* @dev: Device to check

1246

* @iop: Returns a pointer to the I/O region, or NULL if none

1257

* @iop: Returns a pointer to the I/O region, or NULL if none

1247

* @memp: Returns a pointer to the memory region, or NULL if none

1258

* @memp: Returns a pointer to the memory region, or NULL if none

1248

* @prefp: Returns a pointer to the pre-fetch region, or NULL if none

1259

* @prefp: Returns a pointer to the pre-fetch region, or NULL if none

1249

* @return the number of non-NULL regions returned, normally 3

1260

* @return the number of non-NULL regions returned, normally 3

1250

*/

1261

*/

1251

int pci_get_regions(struct udevice *dev, struct pci_region **iop,

1262

int pci_get_regions(struct udevice *dev, struct pci_region **iop,

1252

struct pci_region **memp, struct pci_region **prefp);

1263

struct pci_region **memp, struct pci_region **prefp);

1253

1264

1254

/**

1265

/**

1255

* dm_pci_write_bar32() - Write the address of a BAR

1266

* dm_pci_write_bar32() - Write the address of a BAR

1256

*

1267

*

1257

* This writes a raw address to a bar

1268

* This writes a raw address to a bar

1258

*

1269

*

1259

* @dev: PCI device to update

1270

* @dev: PCI device to update

1260

* @barnum: BAR number (0-5)

1271

* @barnum: BAR number (0-5)

1261

* @addr: BAR address

1272

* @addr: BAR address

1262

*/

1273

*/

1263

void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);

1274

void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);

1264

1275

1265

/**

1276

/**

1266

* dm_pci_read_bar32() - read a base address register from a device

1277

* dm_pci_read_bar32() - read a base address register from a device

1267

*

1278

*

1268

* @dev: Device to check

1279

* @dev: Device to check

1269

* @barnum: Bar number to read (numbered from 0)

1280

* @barnum: Bar number to read (numbered from 0)

1270

* @return: value of BAR

1281

* @return: value of BAR

1271

*/

1282

*/

1272

u32 dm_pci_read_bar32(struct udevice *dev, int barnum);

1283

u32 dm_pci_read_bar32(struct udevice *dev, int barnum);

1273

1284

1274

/**

1285

/**

1275

* dm_pci_bus_to_phys() - convert a PCI bus address to a physical address

1286

* dm_pci_bus_to_phys() - convert a PCI bus address to a physical address

1276

*

1287

*

1277

* @dev: Device containing the PCI address

1288

* @dev: Device containing the PCI address

1278

* @addr: PCI address to convert

1289

* @addr: PCI address to convert

1279

* @flags: Flags for the region type (PCI_REGION_...)

1290

* @flags: Flags for the region type (PCI_REGION_...)

1280

* @return physical address corresponding to that PCI bus address

1291

* @return physical address corresponding to that PCI bus address

1281

*/

1292

*/

1282

phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,

1293

phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,

1283

unsigned long flags);

1294

unsigned long flags);

1284

1295

1285

/**

1296

/**

1286

* dm_pci_phys_to_bus() - convert a physical address to a PCI bus address

1297

* dm_pci_phys_to_bus() - convert a physical address to a PCI bus address

1287

*

1298

*

1288

* @dev: Device containing the bus address

1299

* @dev: Device containing the bus address

1289

* @addr: Physical address to convert

1300

* @addr: Physical address to convert

1290

* @flags: Flags for the region type (PCI_REGION_...)

1301

* @flags: Flags for the region type (PCI_REGION_...)

1291

* @return PCI bus address corresponding to that physical address

1302

* @return PCI bus address corresponding to that physical address

1292

*/

1303

*/

1293

pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,

1304

pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,

1294

unsigned long flags);

1305

unsigned long flags);

1295

1306

1296

/**

1307

/**

1297

* dm_pci_map_bar() - get a virtual address associated with a BAR region

1308

* dm_pci_map_bar() - get a virtual address associated with a BAR region

1298

*

1309

*

1299

* Looks up a base address register and finds the physical memory address

1310

* Looks up a base address register and finds the physical memory address

1300

* that corresponds to it

1311

* that corresponds to it

1301

*

1312

*

1302

* @dev: Device to check

1313

* @dev: Device to check

1303

* @bar: Bar number to read (numbered from 0)

1314

* @bar: Bar number to read (numbered from 0)

1304

* @flags: Flags for the region type (PCI_REGION_...)

1315

* @flags: Flags for the region type (PCI_REGION_...)

1305

* @return: pointer to the virtual address to use

1316

* @return: pointer to the virtual address to use

1306

*/

1317

*/

1307

void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);

1318

void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);

1308

1319

1309

/**

1320

/**

1310

* dm_pci_find_next_capability() - find a capability starting from an offset

1321

* dm_pci_find_next_capability() - find a capability starting from an offset

1311

*

1322

*

1312

* Tell if a device supports a given PCI capability. Returns the

1323

* Tell if a device supports a given PCI capability. Returns the

1313

* address of the requested capability structure within the device's

1324

* address of the requested capability structure within the device's

1314

* PCI configuration space or 0 in case the device does not support it.

1325

* PCI configuration space or 0 in case the device does not support it.

1315

*

1326

*

1316

* Possible values for @cap:

1327

* Possible values for @cap:

1317

*

1328

*

1318

* %PCI_CAP_ID_MSI Message Signalled Interrupts

1329

* %PCI_CAP_ID_MSI Message Signalled Interrupts

1319

* %PCI_CAP_ID_PCIX PCI-X

1330

* %PCI_CAP_ID_PCIX PCI-X

1320

* %PCI_CAP_ID_EXP PCI Express

1331

* %PCI_CAP_ID_EXP PCI Express

1321

* %PCI_CAP_ID_MSIX MSI-X

1332

* %PCI_CAP_ID_MSIX MSI-X

1322

*

1333

*

1323

* See PCI_CAP_ID_xxx for the complete capability ID codes.

1334

* See PCI_CAP_ID_xxx for the complete capability ID codes.

1324

*

1335

*

1325

* @dev: PCI device to query

1336

* @dev: PCI device to query

1326

* @start: offset to start from

1337

* @start: offset to start from

1327

* @cap: capability code

1338

* @cap: capability code

1328

* @return: capability address or 0 if not supported

1339

* @return: capability address or 0 if not supported

1329

*/

1340

*/

1330

int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap);

1341

int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap);

1331

1342

1332

/**

1343

/**

1333

* dm_pci_find_capability() - find a capability

1344

* dm_pci_find_capability() - find a capability

1334

*

1345

*

1335

* Tell if a device supports a given PCI capability. Returns the

1346

* Tell if a device supports a given PCI capability. Returns the

1336

* address of the requested capability structure within the device's

1347

* address of the requested capability structure within the device's

1337

* PCI configuration space or 0 in case the device does not support it.

1348

* PCI configuration space or 0 in case the device does not support it.

1338

*

1349

*

1339

* Possible values for @cap:

1350

* Possible values for @cap:

1340

*

1351

*

1341

* %PCI_CAP_ID_MSI Message Signalled Interrupts

1352

* %PCI_CAP_ID_MSI Message Signalled Interrupts

1342

* %PCI_CAP_ID_PCIX PCI-X

1353

* %PCI_CAP_ID_PCIX PCI-X

1343

* %PCI_CAP_ID_EXP PCI Express

1354

* %PCI_CAP_ID_EXP PCI Express

1344

* %PCI_CAP_ID_MSIX MSI-X

1355

* %PCI_CAP_ID_MSIX MSI-X

1345

*

1356

*

1346

* See PCI_CAP_ID_xxx for the complete capability ID codes.

1357

* See PCI_CAP_ID_xxx for the complete capability ID codes.

1347

*

1358

*

1348

* @dev: PCI device to query

1359

* @dev: PCI device to query

1349

* @cap: capability code

1360

* @cap: capability code

1350

* @return: capability address or 0 if not supported

1361

* @return: capability address or 0 if not supported

1351

*/

1362

*/

1352

int dm_pci_find_capability(struct udevice *dev, int cap);

1363

int dm_pci_find_capability(struct udevice *dev, int cap);

1353

1364

1354

/**

1365

/**

1355

* dm_pci_find_next_ext_capability() - find an extended capability

1366

* dm_pci_find_next_ext_capability() - find an extended capability

1356

* starting from an offset

1367

* starting from an offset

1357

*

1368

*

1358

* Tell if a device supports a given PCI express extended capability.

1369

* Tell if a device supports a given PCI express extended capability.

1359

* Returns the address of the requested extended capability structure

1370

* Returns the address of the requested extended capability structure

1360

* within the device's PCI configuration space or 0 in case the device

1371

* within the device's PCI configuration space or 0 in case the device

1361

* does not support it.

1372

* does not support it.

1362

*

1373

*

1363

* Possible values for @cap:

1374

* Possible values for @cap:

1364

*

1375

*

1365

* %PCI_EXT_CAP_ID_ERR Advanced Error Reporting

1376

* %PCI_EXT_CAP_ID_ERR Advanced Error Reporting

1366

* %PCI_EXT_CAP_ID_VC Virtual Channel

1377

* %PCI_EXT_CAP_ID_VC Virtual Channel

1367

* %PCI_EXT_CAP_ID_DSN Device Serial Number

1378

* %PCI_EXT_CAP_ID_DSN Device Serial Number

1368

* %PCI_EXT_CAP_ID_PWR Power Budgeting

1379

* %PCI_EXT_CAP_ID_PWR Power Budgeting

1369

*

1380

*

1370

* See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.

1381

* See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.

1371

*

1382

*

1372

* @dev: PCI device to query

1383

* @dev: PCI device to query

1373

* @start: offset to start from

1384

* @start: offset to start from

1374

* @cap: extended capability code

1385

* @cap: extended capability code

1375

* @return: extended capability address or 0 if not supported

1386

* @return: extended capability address or 0 if not supported

1376

*/

1387

*/

1377

int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap);

1388

int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap);

1378

1389

1379

/**

1390

/**

1380

* dm_pci_find_ext_capability() - find an extended capability

1391

* dm_pci_find_ext_capability() - find an extended capability

1381

*

1392

*

1382

* Tell if a device supports a given PCI express extended capability.

1393

* Tell if a device supports a given PCI express extended capability.

1383

* Returns the address of the requested extended capability structure

1394

* Returns the address of the requested extended capability structure

1384

* within the device's PCI configuration space or 0 in case the device

1395

* within the device's PCI configuration space or 0 in case the device

1385

* does not support it.

1396

* does not support it.

1386

*

1397

*

1387

* Possible values for @cap:

1398

* Possible values for @cap:

1388

*

1399

*

1389

* %PCI_EXT_CAP_ID_ERR Advanced Error Reporting

1400

* %PCI_EXT_CAP_ID_ERR Advanced Error Reporting

1390

* %PCI_EXT_CAP_ID_VC Virtual Channel

1401

* %PCI_EXT_CAP_ID_VC Virtual Channel

1391

* %PCI_EXT_CAP_ID_DSN Device Serial Number

1402

* %PCI_EXT_CAP_ID_DSN Device Serial Number

1392

* %PCI_EXT_CAP_ID_PWR Power Budgeting

1403

* %PCI_EXT_CAP_ID_PWR Power Budgeting

1393

*

1404

*

1394

* See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.

1405

* See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.

1395

*

1406

*

1396

* @dev: PCI device to query

1407

* @dev: PCI device to query

1397

* @cap: extended capability code

1408

* @cap: extended capability code

1398

* @return: extended capability address or 0 if not supported

1409

* @return: extended capability address or 0 if not supported

1399

*/

1410

*/

1400

int dm_pci_find_ext_capability(struct udevice *dev, int cap);

1411

int dm_pci_find_ext_capability(struct udevice *dev, int cap);

1401

1412

1402

#define dm_pci_virt_to_bus(dev, addr, flags) \

1413

#define dm_pci_virt_to_bus(dev, addr, flags) \

1403

dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))

1414

dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))

1404

#define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \

1415

#define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \

1405

map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \

1416

map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \

1406

(len), (map_flags))

1417

(len), (map_flags))

1407

1418

1408

#define dm_pci_phys_to_mem(dev, addr) \

1419

#define dm_pci_phys_to_mem(dev, addr) \

1409

dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)

1420

dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)

1410

#define dm_pci_mem_to_phys(dev, addr) \

1421

#define dm_pci_mem_to_phys(dev, addr) \

1411

dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)

1422

dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)

1412

#define dm_pci_phys_to_io(dev, addr) \

1423

#define dm_pci_phys_to_io(dev, addr) \

1413

dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)

1424

dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)

1414

#define dm_pci_io_to_phys(dev, addr) \

1425

#define dm_pci_io_to_phys(dev, addr) \

1415

dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)

1426

dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)

1416

1427

1417

#define dm_pci_virt_to_mem(dev, addr) \

1428

#define dm_pci_virt_to_mem(dev, addr) \

1418

dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)

1429

dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)

1419

#define dm_pci_mem_to_virt(dev, addr, len, map_flags) \

1430

#define dm_pci_mem_to_virt(dev, addr, len, map_flags) \

1420

dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))

1431

dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))

1421

#define dm_pci_virt_to_io(dev, addr) \

1432

#define dm_pci_virt_to_io(dev, addr) \

1422

dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)

1433

dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)

1423

#define dm_pci_io_to_virt(dev, addr, len, map_flags) \

1434

#define dm_pci_io_to_virt(dev, addr, len, map_flags) \

1424

dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))

1435

dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))

1425

1436

1426

/**

1437

/**

1427

* dm_pci_find_device() - find a device by vendor/device ID

1438

* dm_pci_find_device() - find a device by vendor/device ID

1428

*

1439

*

1429

* @vendor: Vendor ID

1440

* @vendor: Vendor ID

1430

* @device: Device ID

1441

* @device: Device ID

1431

* @index: 0 to find the first match, 1 for second, etc.

1442

* @index: 0 to find the first match, 1 for second, etc.

1432

* @devp: Returns pointer to the device, if found

1443

* @devp: Returns pointer to the device, if found

1433

* @return 0 if found, -ve on error

1444

* @return 0 if found, -ve on error

1434

*/

1445

*/

1435

int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,

1446

int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,

1436

struct udevice **devp);

1447

struct udevice **devp);

1437

1448

1438

/**

1449

/**

1439

* dm_pci_find_class() - find a device by class

1450

* dm_pci_find_class() - find a device by class

1440

*

1451

*

1441

* @find_class: 3-byte (24-bit) class value to find

1452

* @find_class: 3-byte (24-bit) class value to find

1442

* @index: 0 to find the first match, 1 for second, etc.

1453

* @index: 0 to find the first match, 1 for second, etc.

1443

* @devp: Returns pointer to the device, if found

1454

* @devp: Returns pointer to the device, if found

1444

* @return 0 if found, -ve on error

1455

* @return 0 if found, -ve on error

1445

*/

1456

*/

1446

int dm_pci_find_class(uint find_class, int index, struct udevice **devp);

1457

int dm_pci_find_class(uint find_class, int index, struct udevice **devp);

1447

1458

1448

/**

1459

/**

1449

* struct dm_pci_emul_ops - PCI device emulator operations

1460

* struct dm_pci_emul_ops - PCI device emulator operations

1450

*/

1461

*/

1451

struct dm_pci_emul_ops {

1462

struct dm_pci_emul_ops {

1452

/**

1463

/**

1453

* get_devfn(): Check which device and function this emulators

1464

* get_devfn(): Check which device and function this emulators

1454

*

1465

*

1455

* @dev: device to check

1466

* @dev: device to check

1456

* @return the device and function this emulates, or -ve on error

1467

* @return the device and function this emulates, or -ve on error

1457

*/

1468

*/

1458

int (*get_devfn)(struct udevice *dev);

1469

int (*get_devfn)(struct udevice *dev);

1459

/**

1470

/**

1460

* read_config() - Read a PCI configuration value

1471

* read_config() - Read a PCI configuration value

1461

*

1472

*

1462

* @dev: Emulated device to read from

1473

* @dev: Emulated device to read from

1463

* @offset: Byte offset within the device's configuration space

1474

* @offset: Byte offset within the device's configuration space

1464

* @valuep: Place to put the returned value

1475

* @valuep: Place to put the returned value

1465

* @size: Access size

1476

* @size: Access size

1466

* @return 0 if OK, -ve on error

1477

* @return 0 if OK, -ve on error

1467

*/

1478

*/

1468

int (*read_config)(struct udevice *dev, uint offset, ulong *valuep,

1479

int (*read_config)(struct udevice *dev, uint offset, ulong *valuep,

1469

enum pci_size_t size);

1480

enum pci_size_t size);

1470

/**

1481

/**

1471

* write_config() - Write a PCI configuration value

1482

* write_config() - Write a PCI configuration value

1472

*

1483

*

1473

* @dev: Emulated device to write to

1484

* @dev: Emulated device to write to

1474

* @offset: Byte offset within the device's configuration space

1485

* @offset: Byte offset within the device's configuration space

1475

* @value: Value to write

1486

* @value: Value to write

1476

* @size: Access size

1487

* @size: Access size

1477

* @return 0 if OK, -ve on error

1488

* @return 0 if OK, -ve on error

1478

*/

1489

*/

1479

int (*write_config)(struct udevice *dev, uint offset, ulong value,

1490

int (*write_config)(struct udevice *dev, uint offset, ulong value,

1480

enum pci_size_t size);

1491

enum pci_size_t size);

1481

/**

1492

/**

1482

* read_io() - Read a PCI I/O value

1493

* read_io() - Read a PCI I/O value

1483

*

1494

*

1484

* @dev: Emulated device to read from

1495

* @dev: Emulated device to read from

1485

* @addr: I/O address to read

1496

* @addr: I/O address to read

1486

* @valuep: Place to put the returned value

1497

* @valuep: Place to put the returned value

1487

* @size: Access size

1498

* @size: Access size

1488

* @return 0 if OK, -ENOENT if @addr is not mapped by this device,

1499

* @return 0 if OK, -ENOENT if @addr is not mapped by this device,

1489

* other -ve value on error

1500

* other -ve value on error

1490

*/

1501

*/

1491

int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,

1502

int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,

1492

enum pci_size_t size);

1503

enum pci_size_t size);

1493

/**

1504

/**

1494

* write_io() - Write a PCI I/O value

1505

* write_io() - Write a PCI I/O value

1495

*

1506

*

1496

* @dev: Emulated device to write from

1507

* @dev: Emulated device to write from

1497

* @addr: I/O address to write

1508

* @addr: I/O address to write

1498

* @value: Value to write

1509

* @value: Value to write

1499

* @size: Access size

1510

* @size: Access size

1500

* @return 0 if OK, -ENOENT if @addr is not mapped by this device,

1511

* @return 0 if OK, -ENOENT if @addr is not mapped by this device,

1501

* other -ve value on error

1512

* other -ve value on error

1502

*/

1513

*/

1503

int (*write_io)(struct udevice *dev, unsigned int addr,

1514

int (*write_io)(struct udevice *dev, unsigned int addr,

1504

ulong value, enum pci_size_t size);

1515

ulong value, enum pci_size_t size);

1505

/**

1516

/**

1506

* map_physmem() - Map a device into sandbox memory

1517

* map_physmem() - Map a device into sandbox memory

1507

*

1518

*

1508

* @dev: Emulated device to map

1519

* @dev: Emulated device to map

1509

* @addr: Memory address, normally corresponding to a PCI BAR.

1520

* @addr: Memory address, normally corresponding to a PCI BAR.

1510

* The device should have been configured to have a BAR

1521

* The device should have been configured to have a BAR

1511

* at this address.

1522

* at this address.

1512

* @lenp: On entry, the size of the area to map, On exit it is

1523

* @lenp: On entry, the size of the area to map, On exit it is

1513

* updated to the size actually mapped, which may be less

1524

* updated to the size actually mapped, which may be less

1514

* if the device has less space

1525

* if the device has less space

1515

* @ptrp: Returns a pointer to the mapped address. The device's

1526

* @ptrp: Returns a pointer to the mapped address. The device's

1516

* space can be accessed as @lenp bytes starting here

1527

* space can be accessed as @lenp bytes starting here

1517

* @return 0 if OK, -ENOENT if @addr is not mapped by this device,

1528

* @return 0 if OK, -ENOENT if @addr is not mapped by this device,

1518

* other -ve value on error

1529

* other -ve value on error

1519

*/

1530

*/

1520

int (*map_physmem)(struct udevice *dev, phys_addr_t addr,

1531

int (*map_physmem)(struct udevice *dev, phys_addr_t addr,

1521

unsigned long *lenp, void **ptrp);

1532

unsigned long *lenp, void **ptrp);

1522

/**

1533

/**

1523

* unmap_physmem() - undo a memory mapping

1534

* unmap_physmem() - undo a memory mapping

1524

*

1535

*

1525

* This must be called after map_physmem() to undo the mapping.

1536

* This must be called after map_physmem() to undo the mapping.

1526

* Some devices can use this to check what has been written into

1537

* Some devices can use this to check what has been written into

1527

* their mapped memory and perform an operations they require on it.

1538

* their mapped memory and perform an operations they require on it.

1528

* In this way, map/unmap can be used as a sort of handshake between

1539

* In this way, map/unmap can be used as a sort of handshake between

1529

* the emulated device and its users.

1540

* the emulated device and its users.

1530

*

1541

*

1531

* @dev: Emuated device to unmap

1542

* @dev: Emuated device to unmap

1532

* @vaddr: Mapped memory address, as passed to map_physmem()

1543

* @vaddr: Mapped memory address, as passed to map_physmem()

1533

* @len: Size of area mapped, as returned by map_physmem()

1544

* @len: Size of area mapped, as returned by map_physmem()

1534

* @return 0 if OK, -ve on error

1545

* @return 0 if OK, -ve on error

1535

*/

1546

*/

1536

int (*unmap_physmem)(struct udevice *dev, const void *vaddr,

1547

int (*unmap_physmem)(struct udevice *dev, const void *vaddr,

1537

unsigned long len);

1548

unsigned long len);

1538

};

1549

};

1539

1550

1540

/* Get access to a PCI device emulator's operations */

1551

/* Get access to a PCI device emulator's operations */

1541

#define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)

1552

#define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)

1542

1553

1543

/**

1554

/**

1544

* sandbox_pci_get_emul() - Get the emulation device for a PCI device

1555

* sandbox_pci_get_emul() - Get the emulation device for a PCI device

1545

*

1556

*

1546

* Searches for a suitable emulator for the given PCI bus device

1557

* Searches for a suitable emulator for the given PCI bus device

1547

*

1558

*

1548

* @bus: PCI bus to search

1559

* @bus: PCI bus to search

1549

* @find_devfn: PCI device and function address (PCI_DEVFN())

1560

* @find_devfn: PCI device and function address (PCI_DEVFN())

1550

* @containerp: Returns container device if found

1561

* @containerp: Returns container device if found

1551

* @emulp: Returns emulated device if found

1562

* @emulp: Returns emulated device if found

1552

* @return 0 if found, -ENODEV if not found

1563

* @return 0 if found, -ENODEV if not found

1553

*/

1564

*/

1554

int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,

1565

int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,

1555

struct udevice **containerp, struct udevice **emulp);

1566

struct udevice **containerp, struct udevice **emulp);

1556

1567

1557

/**

1568

/**

1558

* pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device

1569

* pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device

1559

*

1570

*

1560

* Get devfn from fdt_pci_addr of the specifified device

1571

* Get devfn from fdt_pci_addr of the specifified device

1561

*

1572

*

1562

* @dev: PCI device

1573

* @dev: PCI device

1563

* @return devfn in bits 15...8 if found, -ENODEV if not found

1574

* @return devfn in bits 15...8 if found, -ENODEV if not found

1564

*/

1575

*/

1565

int pci_get_devfn(struct udevice *dev);

1576

int pci_get_devfn(struct udevice *dev);

1566

1577

1567

#endif /* CONFIG_DM_PCI */

1578

#endif /* CONFIG_DM_PCI */

1568

1579

1569

/**

1580

/**

1570

* PCI_DEVICE - macro used to describe a specific pci device

1581

* PCI_DEVICE - macro used to describe a specific pci device

1571

* @vend: the 16 bit PCI Vendor ID

1582

* @vend: the 16 bit PCI Vendor ID

1572

* @dev: the 16 bit PCI Device ID

1583

* @dev: the 16 bit PCI Device ID

1573

*

1584

*

1574

* This macro is used to create a struct pci_device_id that matches a

1585

* This macro is used to create a struct pci_device_id that matches a

1575

* specific device. The subvendor and subdevice fields will be set to

1586

* specific device. The subvendor and subdevice fields will be set to

1576

* PCI_ANY_ID.

1587

* PCI_ANY_ID.

1577

*/

1588

*/

1578

#define PCI_DEVICE(vend, dev) \

1589

#define PCI_DEVICE(vend, dev) \

1579

.vendor = (vend), .device = (dev), \

1590

.vendor = (vend), .device = (dev), \

1580

.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID

1591

.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID

1581

1592

1582

/**

1593

/**

1583

* PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem

1594

* PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem

1584

* @vend: the 16 bit PCI Vendor ID

1595

* @vend: the 16 bit PCI Vendor ID

1585

* @dev: the 16 bit PCI Device ID

1596

* @dev: the 16 bit PCI Device ID

1586

* @subvend: the 16 bit PCI Subvendor ID

1597

* @subvend: the 16 bit PCI Subvendor ID

1587

* @subdev: the 16 bit PCI Subdevice ID

1598

* @subdev: the 16 bit PCI Subdevice ID

1588

*

1599

*

1589

* This macro is used to create a struct pci_device_id that matches a

1600

* This macro is used to create a struct pci_device_id that matches a

1590

* specific device with subsystem information.

1601

* specific device with subsystem information.

1591

*/

1602

*/

1592

#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \

1603

#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \

1593

.vendor = (vend), .device = (dev), \

1604

.vendor = (vend), .device = (dev), \

1594

.subvendor = (subvend), .subdevice = (subdev)

1605

.subvendor = (subvend), .subdevice = (subdev)

1595

1606

1596

/**

1607

/**

1597

* PCI_DEVICE_CLASS - macro used to describe a specific pci device class

1608

* PCI_DEVICE_CLASS - macro used to describe a specific pci device class

1598

* @dev_class: the class, subclass, prog-if triple for this device

1609

* @dev_class: the class, subclass, prog-if triple for this device

1599

* @dev_class_mask: the class mask for this device

1610

* @dev_class_mask: the class mask for this device

1600

*

1611

*

1601

* This macro is used to create a struct pci_device_id that matches a

1612

* This macro is used to create a struct pci_device_id that matches a

1602

* specific PCI class. The vendor, device, subvendor, and subdevice

1613

* specific PCI class. The vendor, device, subvendor, and subdevice

1603

* fields will be set to PCI_ANY_ID.

1614

* fields will be set to PCI_ANY_ID.

1604

*/

1615

*/

1605

#define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \

1616

#define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \

1606

.class = (dev_class), .class_mask = (dev_class_mask), \

1617

.class = (dev_class), .class_mask = (dev_class_mask), \

1607

.vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \

1618

.vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \

1608

.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID

1619

.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID

1609

1620

1610

/**

1621

/**

1611

* PCI_VDEVICE - macro used to describe a specific pci device in short form

1622

* PCI_VDEVICE - macro used to describe a specific pci device in short form

1612

* @vend: the vendor name

1623

* @vend: the vendor name

1613

* @dev: the 16 bit PCI Device ID

1624

* @dev: the 16 bit PCI Device ID

1614

*

1625

*

1615

* This macro is used to create a struct pci_device_id that matches a

1626

* This macro is used to create a struct pci_device_id that matches a

1616

* specific PCI device. The subvendor, and subdevice fields will be set

1627

* specific PCI device. The subvendor, and subdevice fields will be set

1617

* to PCI_ANY_ID. The macro allows the next field to follow as the device

1628

* to PCI_ANY_ID. The macro allows the next field to follow as the device

1618

* private data.

1629

* private data.

1619

*/

1630

*/

1620

1631

1621

#define PCI_VDEVICE(vend, dev) \

1632

#define PCI_VDEVICE(vend, dev) \

1622

.vendor = PCI_VENDOR_ID_##vend, .device = (dev), \

1633

.vendor = PCI_VENDOR_ID_##vend, .device = (dev), \

1623

.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0

1634

.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0

1624

1635

1625

/**

1636

/**

1626

* struct pci_driver_entry - Matches a driver to its pci_device_id list

1637

* struct pci_driver_entry - Matches a driver to its pci_device_id list

1627

* @driver: Driver to use

1638

* @driver: Driver to use

1628

* @match: List of match records for this driver, terminated by {}

1639

* @match: List of match records for this driver, terminated by {}

1629

*/

1640

*/

1630

struct pci_driver_entry {

1641

struct pci_driver_entry {

1631

struct driver *driver;

1642

struct driver *driver;

1632

const struct pci_device_id *match;

1643

const struct pci_device_id *match;

1633

};

1644

};

1634

1645

1635

#define U_BOOT_PCI_DEVICE(__name, __match) \

1646

#define U_BOOT_PCI_DEVICE(__name, __match) \

1636

ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\

1647

ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\

1637

.driver = llsym(struct driver, __name, driver), \

1648

.driver = llsym(struct driver, __name, driver), \

1638

.match = __match, \

1649

.match = __match, \

1639

}

1650

}

1640

1651

1641

#endif /* __ASSEMBLY__ */

1652

#endif /* __ASSEMBLY__ */

1642

#endif /* _PCI_H */

1653

#endif /* _PCI_H */

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1654

GITLAB

pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux

 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Andreas Heppel <aheppel@sysgo.de>
  *
  * (C) Copyright 2002
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  */
 #ifndef _PCI_H
 #define _PCI_H
 #define PCI_CFG_SPACE_SIZE	256
 #define PCI_CFG_SPACE_EXP_SIZE	4096
 /*
  * Under PCI, each device has 256 bytes of configuration address space,
  * of which the first 64 bytes are standardized as follows:
  */
 #define PCI_STD_HEADER_SIZEOF	64
 #define PCI_VENDOR_ID		0x00	/* 16 bits */
 #define PCI_DEVICE_ID		0x02	/* 16 bits */
 #define PCI_COMMAND		0x04	/* 16 bits */
 #define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
 #define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
 #define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
 #define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
 #define  PCI_COMMAND_INVALIDATE 0x10	/* Use memory write and invalidate */
 #define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
 #define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
 #define  PCI_COMMAND_WAIT	0x80	/* Enable address/data stepping */
 #define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
 #define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
 #define PCI_STATUS		0x06	/* 16 bits */
 #define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
 #define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
 #define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
 #define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
 #define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
 #define  PCI_STATUS_DEVSEL_MASK 0x600	/* DEVSEL timing */
 #define  PCI_STATUS_DEVSEL_FAST 0x000
 #define  PCI_STATUS_DEVSEL_MEDIUM 0x200
 #define  PCI_STATUS_DEVSEL_SLOW 0x400
 #define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
 #define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
 #define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
 #define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
 #define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
 #define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8
 					   revision */
 #define PCI_REVISION_ID		0x08	/* Revision ID */
 #define PCI_CLASS_PROG		0x09	/* Reg. Level Programming Interface */
 #define PCI_CLASS_DEVICE	0x0a	/* Device class */
 #define PCI_CLASS_CODE		0x0b	/* Device class code */
 #define  PCI_CLASS_CODE_TOO_OLD	0x00
 #define  PCI_CLASS_CODE_STORAGE 0x01
 #define  PCI_CLASS_CODE_NETWORK 0x02
 #define  PCI_CLASS_CODE_DISPLAY	0x03
 #define  PCI_CLASS_CODE_MULTIMEDIA 0x04
 #define  PCI_CLASS_CODE_MEMORY	0x05
 #define  PCI_CLASS_CODE_BRIDGE	0x06
 #define  PCI_CLASS_CODE_COMM	0x07
 #define  PCI_CLASS_CODE_PERIPHERAL 0x08
 #define  PCI_CLASS_CODE_INPUT	0x09
 #define  PCI_CLASS_CODE_DOCKING	0x0A
 #define  PCI_CLASS_CODE_PROCESSOR 0x0B
 #define  PCI_CLASS_CODE_SERIAL	0x0C
 #define  PCI_CLASS_CODE_WIRELESS 0x0D
 #define  PCI_CLASS_CODE_I2O	0x0E
 #define  PCI_CLASS_CODE_SATELLITE 0x0F
 #define  PCI_CLASS_CODE_CRYPTO	0x10
 #define  PCI_CLASS_CODE_DATA	0x11
 /* Base Class 0x12 - 0xFE is reserved */
 #define  PCI_CLASS_CODE_OTHER	0xFF
 #define PCI_CLASS_SUB_CODE	0x0a	/* Device sub-class code */
 #define  PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA	0x00
 #define  PCI_CLASS_SUB_CODE_TOO_OLD_VGA		0x01
 #define  PCI_CLASS_SUB_CODE_STORAGE_SCSI	0x00
 #define  PCI_CLASS_SUB_CODE_STORAGE_IDE		0x01
 #define  PCI_CLASS_SUB_CODE_STORAGE_FLOPPY	0x02
 #define  PCI_CLASS_SUB_CODE_STORAGE_IPIBUS	0x03
 #define  PCI_CLASS_SUB_CODE_STORAGE_RAID	0x04
 #define  PCI_CLASS_SUB_CODE_STORAGE_ATA		0x05
 #define  PCI_CLASS_SUB_CODE_STORAGE_SATA	0x06
 #define  PCI_CLASS_SUB_CODE_STORAGE_SAS		0x07
 #define  PCI_CLASS_SUB_CODE_STORAGE_OTHER	0x80
 #define  PCI_CLASS_SUB_CODE_NETWORK_ETHERNET	0x00
 #define  PCI_CLASS_SUB_CODE_NETWORK_TOKENRING	0x01
 #define  PCI_CLASS_SUB_CODE_NETWORK_FDDI	0x02
 #define  PCI_CLASS_SUB_CODE_NETWORK_ATM		0x03
 #define  PCI_CLASS_SUB_CODE_NETWORK_ISDN	0x04
 #define  PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP	0x05
 #define  PCI_CLASS_SUB_CODE_NETWORK_PICMG	0x06
 #define  PCI_CLASS_SUB_CODE_NETWORK_OTHER	0x80
 #define  PCI_CLASS_SUB_CODE_DISPLAY_VGA		0x00
 #define  PCI_CLASS_SUB_CODE_DISPLAY_XGA		0x01
 #define  PCI_CLASS_SUB_CODE_DISPLAY_3D		0x02
 #define  PCI_CLASS_SUB_CODE_DISPLAY_OTHER	0x80
 #define  PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO	0x00
 #define  PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO	0x01
 #define  PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE	0x02
 #define  PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER	0x80
 #define  PCI_CLASS_SUB_CODE_MEMORY_RAM		0x00
 #define  PCI_CLASS_SUB_CODE_MEMORY_FLASH	0x01
 #define  PCI_CLASS_SUB_CODE_MEMORY_OTHER	0x80
 #define  PCI_CLASS_SUB_CODE_BRIDGE_HOST		0x00
 #define  PCI_CLASS_SUB_CODE_BRIDGE_ISA		0x01
 #define  PCI_CLASS_SUB_CODE_BRIDGE_EISA		0x02
 #define  PCI_CLASS_SUB_CODE_BRIDGE_MCA		0x03
 #define  PCI_CLASS_SUB_CODE_BRIDGE_PCI		0x04
 #define  PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA	0x05
 #define  PCI_CLASS_SUB_CODE_BRIDGE_NUBUS	0x06
 #define  PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS	0x07
 #define  PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY	0x08
 #define  PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI	0x09
 #define  PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND	0x0A
 #define  PCI_CLASS_SUB_CODE_BRIDGE_OTHER	0x80
 #define  PCI_CLASS_SUB_CODE_COMM_SERIAL		0x00
 #define  PCI_CLASS_SUB_CODE_COMM_PARALLEL	0x01
 #define  PCI_CLASS_SUB_CODE_COMM_MULTIPORT	0x02
 #define  PCI_CLASS_SUB_CODE_COMM_MODEM		0x03
 #define  PCI_CLASS_SUB_CODE_COMM_GPIB		0x04
 #define  PCI_CLASS_SUB_CODE_COMM_SMARTCARD	0x05
 #define  PCI_CLASS_SUB_CODE_COMM_OTHER		0x80
 #define  PCI_CLASS_SUB_CODE_PERIPHERAL_PIC	0x00
 #define  PCI_CLASS_SUB_CODE_PERIPHERAL_DMA	0x01
 #define  PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER	0x02
 #define  PCI_CLASS_SUB_CODE_PERIPHERAL_RTC	0x03
 #define  PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG	0x04
 #define  PCI_CLASS_SUB_CODE_PERIPHERAL_SD	0x05
 #define  PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER	0x80
 #define  PCI_CLASS_SUB_CODE_INPUT_KEYBOARD	0x00
 #define  PCI_CLASS_SUB_CODE_INPUT_DIGITIZER	0x01
 #define  PCI_CLASS_SUB_CODE_INPUT_MOUSE		0x02
 #define  PCI_CLASS_SUB_CODE_INPUT_SCANNER	0x03
 #define  PCI_CLASS_SUB_CODE_INPUT_GAMEPORT	0x04
 #define  PCI_CLASS_SUB_CODE_INPUT_OTHER		0x80
 #define  PCI_CLASS_SUB_CODE_DOCKING_GENERIC	0x00
 #define  PCI_CLASS_SUB_CODE_DOCKING_OTHER	0x80
 #define  PCI_CLASS_SUB_CODE_PROCESSOR_386	0x00
 #define  PCI_CLASS_SUB_CODE_PROCESSOR_486	0x01
 #define  PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM	0x02
 #define  PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA	0x10
 #define  PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC	0x20
 #define  PCI_CLASS_SUB_CODE_PROCESSOR_MIPS	0x30
 #define  PCI_CLASS_SUB_CODE_PROCESSOR_COPROC	0x40
 #define  PCI_CLASS_SUB_CODE_SERIAL_1394		0x00
 #define  PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS	0x01
 #define  PCI_CLASS_SUB_CODE_SERIAL_SSA		0x02
 #define  PCI_CLASS_SUB_CODE_SERIAL_USB		0x03
 #define  PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN	0x04
 #define  PCI_CLASS_SUB_CODE_SERIAL_SMBUS	0x05
 #define  PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND	0x06
 #define  PCI_CLASS_SUB_CODE_SERIAL_IPMI		0x07
 #define  PCI_CLASS_SUB_CODE_SERIAL_SERCOS	0x08
 #define  PCI_CLASS_SUB_CODE_SERIAL_CANBUS	0x09
 #define  PCI_CLASS_SUB_CODE_WIRELESS_IRDA	0x00
 #define  PCI_CLASS_SUB_CODE_WIRELESS_IR		0x01
 #define  PCI_CLASS_SUB_CODE_WIRELESS_RF		0x10
 #define  PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH	0x11
 #define  PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND	0x12
 #define  PCI_CLASS_SUB_CODE_WIRELESS_80211A	0x20
 #define  PCI_CLASS_SUB_CODE_WIRELESS_80211B	0x21
 #define  PCI_CLASS_SUB_CODE_WIRELESS_OTHER	0x80
 #define  PCI_CLASS_SUB_CODE_I2O_V1_0		0x00
 #define  PCI_CLASS_SUB_CODE_SATELLITE_TV	0x01
 #define  PCI_CLASS_SUB_CODE_SATELLITE_AUDIO	0x02
 #define  PCI_CLASS_SUB_CODE_SATELLITE_VOICE	0x03
 #define  PCI_CLASS_SUB_CODE_SATELLITE_DATA	0x04
 #define  PCI_CLASS_SUB_CODE_CRYPTO_NETWORK	0x00
 #define  PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
 #define  PCI_CLASS_SUB_CODE_CRYPTO_OTHER	0x80
 #define  PCI_CLASS_SUB_CODE_DATA_DPIO		0x00
 #define  PCI_CLASS_SUB_CODE_DATA_PERFCNTR	0x01
 #define  PCI_CLASS_SUB_CODE_DATA_COMMSYNC	0x10
 #define  PCI_CLASS_SUB_CODE_DATA_MGMT		0x20
 #define  PCI_CLASS_SUB_CODE_DATA_OTHER		0x80
 #define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
 #define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
 #define PCI_HEADER_TYPE		0x0e	/* 8 bits */
 #define  PCI_HEADER_TYPE_NORMAL 0
 #define  PCI_HEADER_TYPE_BRIDGE 1
 #define  PCI_HEADER_TYPE_CARDBUS 2
 #define PCI_BIST		0x0f	/* 8 bits */
 #define PCI_BIST_CODE_MASK	0x0f	/* Return result */
 #define PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
 #define PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
 /*
  * Base addresses specify locations in memory or I/O space.
  * Decoded size can be determined by writing a value of
  * 0xffffffff to the register, and reading it back.  Only
  * 1 bits are decoded.
  */
 #define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
 #define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */
 #define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */
 #define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
 #define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
 #define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */
 #define  PCI_BASE_ADDRESS_SPACE 0x01	/* 0 = memory, 1 = I/O */
 #define  PCI_BASE_ADDRESS_SPACE_IO 0x01
 #define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
 #define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
 #define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
 #define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
 #define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
 #define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
 #define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fULL)
 #define  PCI_BASE_ADDRESS_IO_MASK	(~0x03ULL)
 /* bit 1 is reserved if address_space = 1 */
 /* Header type 0 (normal devices) */
 #define PCI_CARDBUS_CIS		0x28
 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
 #define PCI_SUBSYSTEM_ID	0x2e
 #define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
 #define  PCI_ROM_ADDRESS_ENABLE 0x01
 #define PCI_ROM_ADDRESS_MASK	(~0x7ffULL)
 #define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
 /* 0x35-0x3b are reserved */
 #define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
 #define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
 #define PCI_MIN_GNT		0x3e	/* 8 bits */
 #define PCI_MAX_LAT		0x3f	/* 8 bits */
 #define PCI_INTERRUPT_LINE_DISABLE	0xff
 /* Header type 1 (PCI-to-PCI bridges) */
 #define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
 #define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
 #define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
 #define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */
 #define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */
 #define PCI_IO_LIMIT		0x1d
 #define  PCI_IO_RANGE_TYPE_MASK 0x0f	/* I/O bridging type */
 #define  PCI_IO_RANGE_TYPE_16	0x00
 #define  PCI_IO_RANGE_TYPE_32	0x01
 #define  PCI_IO_RANGE_MASK	~0x0f
 #define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
 #define PCI_MEMORY_BASE		0x20	/* Memory range behind */
 #define PCI_MEMORY_LIMIT	0x22
 #define  PCI_MEMORY_RANGE_TYPE_MASK 0x0f
 #define  PCI_MEMORY_RANGE_MASK	~0x0f
 #define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */
 #define PCI_PREF_MEMORY_LIMIT	0x26
 #define  PCI_PREF_RANGE_TYPE_MASK 0x0f
 #define  PCI_PREF_RANGE_TYPE_32 0x00
 #define  PCI_PREF_RANGE_TYPE_64 0x01
 #define  PCI_PREF_RANGE_MASK	~0x0f
 #define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */
 #define PCI_PREF_LIMIT_UPPER32	0x2c
 #define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
 #define PCI_IO_LIMIT_UPPER16	0x32
 /* 0x34 same as for htype 0 */
 /* 0x35-0x3b is reserved */
 #define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
 /* 0x3c-0x3d are same as for htype 0 */
 #define PCI_BRIDGE_CONTROL	0x3e
 #define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */
 #define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */
 #define  PCI_BRIDGE_CTL_NO_ISA	0x04	/* Disable bridging of ISA ports */
 #define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */
 #define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
 #define  PCI_BRIDGE_CTL_BUS_RESET 0x40	/* Secondary bus reset */
 #define  PCI_BRIDGE_CTL_FAST_BACK 0x80	/* Fast Back2Back enabled on secondary interface */
 /* Header type 2 (CardBus bridges) */
 #define PCI_CB_CAPABILITY_LIST	0x14
 /* 0x15 reserved */
 #define PCI_CB_SEC_STATUS	0x16	/* Secondary status */
 #define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */
 #define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */
 #define PCI_CB_SUBORDINATE_BUS	0x1a	/* Subordinate bus number */
 #define PCI_CB_LATENCY_TIMER	0x1b	/* CardBus latency timer */
 #define PCI_CB_MEMORY_BASE_0	0x1c
 #define PCI_CB_MEMORY_LIMIT_0	0x20
 #define PCI_CB_MEMORY_BASE_1	0x24
 #define PCI_CB_MEMORY_LIMIT_1	0x28
 #define PCI_CB_IO_BASE_0	0x2c
 #define PCI_CB_IO_BASE_0_HI	0x2e
 #define PCI_CB_IO_LIMIT_0	0x30
 #define PCI_CB_IO_LIMIT_0_HI	0x32
 #define PCI_CB_IO_BASE_1	0x34
 #define PCI_CB_IO_BASE_1_HI	0x36
 #define PCI_CB_IO_LIMIT_1	0x38
 #define PCI_CB_IO_LIMIT_1_HI	0x3a
 #define  PCI_CB_IO_RANGE_MASK	~0x03
 /* 0x3c-0x3d are same as for htype 0 */
 #define PCI_CB_BRIDGE_CONTROL	0x3e
 #define  PCI_CB_BRIDGE_CTL_PARITY	0x01	/* Similar to standard bridge control register */
 #define  PCI_CB_BRIDGE_CTL_SERR		0x02
 #define  PCI_CB_BRIDGE_CTL_ISA		0x04
 #define  PCI_CB_BRIDGE_CTL_VGA		0x08
 #define  PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
 #define  PCI_CB_BRIDGE_CTL_CB_RESET	0x40	/* CardBus reset */
 #define  PCI_CB_BRIDGE_CTL_16BIT_INT	0x80	/* Enable interrupt for 16-bit cards */
 #define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100	/* Prefetch enable for both memory regions */
 #define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
 #define  PCI_CB_BRIDGE_CTL_POST_WRITES	0x400
 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
 #define PCI_CB_SUBSYSTEM_ID	0x42
 #define PCI_CB_LEGACY_MODE_BASE 0x44	/* 16-bit PC Card legacy mode base address (ExCa) */
 /* 0x48-0x7f reserved */
 /* Capability lists */
 #define PCI_CAP_LIST_ID		0	/* Capability ID */
 #define  PCI_CAP_ID_PM		0x01	/* Power Management */
 #define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
 #define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
 #define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
 #define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
 #define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
 #define  PCI_CAP_ID_PCIX	0x07	/* PCI-X */
 #define  PCI_CAP_ID_HT		0x08	/* HyperTransport */
 #define  PCI_CAP_ID_VNDR	0x09	/* Vendor-Specific */
 #define  PCI_CAP_ID_DBG		0x0A	/* Debug port */
 #define  PCI_CAP_ID_CCRC	0x0B	/* CompactPCI Central Resource Control */
 #define  PCI_CAP_ID_SHPC	0x0C	/* PCI Standard Hot-Plug Controller */
 #define  PCI_CAP_ID_SSVID	0x0D	/* Bridge subsystem vendor/device ID */
 #define  PCI_CAP_ID_AGP3	0x0E	/* AGP Target PCI-PCI bridge */
 #define  PCI_CAP_ID_SECDEV	0x0F	/* Secure Device */
 #define  PCI_CAP_ID_EXP		0x10	/* PCI Express */
 #define  PCI_CAP_ID_MSIX	0x11	/* MSI-X */
 #define  PCI_CAP_ID_SATA	0x12	/* SATA Data/Index Conf. */
 #define  PCI_CAP_ID_AF		0x13	/* PCI Advanced Features */
 #define  PCI_CAP_ID_EA		0x14	/* PCI Enhanced Allocation */
 #define  PCI_CAP_ID_MAX		PCI_CAP_ID_EA
 #define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
 #define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
 #define PCI_CAP_SIZEOF		4
 /* Power Management Registers */
 #define  PCI_PM_CAP_VER_MASK	0x0007	/* Version */
 #define  PCI_PM_CAP_PME_CLOCK	0x0008	/* PME clock required */
 #define  PCI_PM_CAP_AUX_POWER	0x0010	/* Auxilliary power support */
 #define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization */
 #define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
 #define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
 #define  PCI_PM_CAP_PME		0x0800	/* PME pin supported */
 #define PCI_PM_CTRL		4	/* PM control and status register */
 #define  PCI_PM_CTRL_STATE_MASK 0x0003	/* Current power state (D0 to D3) */
 #define  PCI_PM_CTRL_PME_ENABLE 0x0100	/* PME pin enable */
 #define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
 #define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */
 #define  PCI_PM_CTRL_PME_STATUS 0x8000	/* PME pin status */
 #define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions (??) */
 #define  PCI_PM_PPB_B2_B3	0x40	/* Stop clock when in D3hot (??) */
 #define  PCI_PM_BPCC_ENABLE	0x80	/* Bus power/clock control enable (??) */
 #define PCI_PM_DATA_REGISTER	7	/* (??) */
 #define PCI_PM_SIZEOF		8
 /* AGP registers */
 #define PCI_AGP_VERSION		2	/* BCD version number */
 #define PCI_AGP_RFU		3	/* Rest of capability flags */
 #define PCI_AGP_STATUS		4	/* Status register */
 #define  PCI_AGP_STATUS_RQ_MASK 0xff000000	/* Maximum number of requests - 1 */
 #define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
 #define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing supported */
 #define  PCI_AGP_STATUS_FW	0x0010	/* FW transfers supported */
 #define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported */
 #define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported */
 #define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported */
 #define PCI_AGP_COMMAND		8	/* Control register */
 #define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
 #define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
 #define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
 #define  PCI_AGP_COMMAND_64BIT	0x0020	/* Allow processing of 64-bit addresses */
 #define  PCI_AGP_COMMAND_FW	0x0010	/* Force FW transfers */
 #define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
 #define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 4x rate */
 #define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 4x rate */
 #define PCI_AGP_SIZEOF		12
 /* PCI-X registers */
 #define  PCI_X_CMD_DPERR_E      0x0001  /* Data Parity Error Recovery Enable */
 #define  PCI_X_CMD_ERO          0x0002  /* Enable Relaxed Ordering */
 #define  PCI_X_CMD_MAX_READ     0x0000  /* Max Memory Read Byte Count */
 #define  PCI_X_CMD_MAX_SPLIT    0x0030  /* Max Outstanding Split Transactions */
 #define  PCI_X_CMD_VERSION(x)   (((x) >> 12) & 3) /* Version */
 /* Slot Identification */
 #define PCI_SID_ESR		2	/* Expansion Slot Register */
 #define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
 #define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
 #define PCI_SID_CHASSIS_NR	3	/* Chassis Number */
 /* Message Signalled Interrupts registers */
 #define PCI_MSI_FLAGS		2	/* Various flags */
 #define  PCI_MSI_FLAGS_64BIT	0x80	/* 64-bit addresses allowed */
 #define  PCI_MSI_FLAGS_QSIZE	0x70	/* Message queue size configured */
 #define  PCI_MSI_FLAGS_QMASK	0x0e	/* Maximum queue size available */
 #define  PCI_MSI_FLAGS_ENABLE	0x01	/* MSI feature enabled */
 #define PCI_MSI_RFU		3	/* Rest of capability flags */
 #define PCI_MSI_ADDRESS_LO	4	/* Lower 32 bits */
 #define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
 #define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
 #define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */
 #define PCI_MAX_PCI_DEVICES	32
 #define PCI_MAX_PCI_FUNCTIONS	8
 #define PCI_FIND_CAP_TTL 0x48
 #define CAP_START_POS 0x40
 /* Extended Capabilities (PCI-X 2.0 and Express) */
 #define PCI_EXT_CAP_ID(header)		(header & 0x0000ffff)
 #define PCI_EXT_CAP_VER(header)		((header >> 16) & 0xf)
 #define PCI_EXT_CAP_NEXT(header)	((header >> 20) & 0xffc)
 #define PCI_EXT_CAP_ID_ERR	0x01	/* Advanced Error Reporting */
 #define PCI_EXT_CAP_ID_VC	0x02	/* Virtual Channel Capability */
 #define PCI_EXT_CAP_ID_DSN	0x03	/* Device Serial Number */
 #define PCI_EXT_CAP_ID_PWR	0x04	/* Power Budgeting */
 #define PCI_EXT_CAP_ID_RCLD	0x05	/* Root Complex Link Declaration */
 #define PCI_EXT_CAP_ID_RCILC	0x06	/* Root Complex Internal Link Control */
 #define PCI_EXT_CAP_ID_RCEC	0x07	/* Root Complex Event Collector */
 #define PCI_EXT_CAP_ID_MFVC	0x08	/* Multi-Function VC Capability */
 #define PCI_EXT_CAP_ID_VC9	0x09	/* same as _VC */
 #define PCI_EXT_CAP_ID_RCRB	0x0A	/* Root Complex RB? */
 #define PCI_EXT_CAP_ID_VNDR	0x0B	/* Vendor-Specific */
 #define PCI_EXT_CAP_ID_CAC	0x0C	/* Config Access - obsolete */
 #define PCI_EXT_CAP_ID_ACS	0x0D	/* Access Control Services */
 #define PCI_EXT_CAP_ID_ARI	0x0E	/* Alternate Routing ID */
 #define PCI_EXT_CAP_ID_ATS	0x0F	/* Address Translation Services */
 #define PCI_EXT_CAP_ID_SRIOV	0x10	/* Single Root I/O Virtualization */
 #define PCI_EXT_CAP_ID_MRIOV	0x11	/* Multi Root I/O Virtualization */
 #define PCI_EXT_CAP_ID_MCAST	0x12	/* Multicast */
 #define PCI_EXT_CAP_ID_PRI	0x13	/* Page Request Interface */
 #define PCI_EXT_CAP_ID_AMD_XXX	0x14	/* Reserved for AMD */
 #define PCI_EXT_CAP_ID_REBAR	0x15	/* Resizable BAR */
 #define PCI_EXT_CAP_ID_DPA	0x16	/* Dynamic Power Allocation */
 #define PCI_EXT_CAP_ID_TPH	0x17	/* TPH Requester */
 #define PCI_EXT_CAP_ID_LTR	0x18	/* Latency Tolerance Reporting */
 #define PCI_EXT_CAP_ID_SECPCI	0x19	/* Secondary PCIe Capability */
 #define PCI_EXT_CAP_ID_PMUX	0x1A	/* Protocol Multiplexing */
 #define PCI_EXT_CAP_ID_PASID	0x1B	/* Process Address Space ID */
 #define PCI_EXT_CAP_ID_DPC	0x1D	/* Downstream Port Containment */
 #define PCI_EXT_CAP_ID_L1SS	0x1E	/* L1 PM Substates */
 #define PCI_EXT_CAP_ID_PTM	0x1F	/* Precision Time Measurement */
 #define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_PTM
 /* Include the ID list */
 #include <pci_ids.h>
 #ifndef __ASSEMBLY__
 #ifdef CONFIG_SYS_PCI_64BIT
 typedef u64 pci_addr_t;
 typedef u64 pci_size_t;
 #else
 typedef u32 pci_addr_t;
 typedef u32 pci_size_t;
 #endif
 struct pci_region {
 	pci_addr_t bus_start;	/* Start on the bus */
 	phys_addr_t phys_start;	/* Start in physical address space */
 	pci_size_t size;	/* Size */
 	unsigned long flags;	/* Resource flags */
 	pci_addr_t bus_lower;
 };
 #define PCI_REGION_MEM		0x00000000	/* PCI memory space */
 #define PCI_REGION_IO		0x00000001	/* PCI IO space */
 #define PCI_REGION_TYPE		0x00000001
 #define PCI_REGION_PREFETCH	0x00000008	/* prefetchable PCI memory */
 #define PCI_REGION_SYS_MEMORY	0x00000100	/* System memory */
 #define PCI_REGION_RO		0x00000200	/* Read-only memory */
 static inline void pci_set_region(struct pci_region *reg,
 				      pci_addr_t bus_start,
 				      phys_addr_t phys_start,
 				      pci_size_t size,
 				      unsigned long flags) {
 	reg->bus_start	= bus_start;
 	reg->phys_start = phys_start;
 	reg->size	= size;
 	reg->flags	= flags;
 }
 typedef int pci_dev_t;
 #define PCI_BUS(d)		(((d) >> 16) & 0xff)
+/*
+ * Please note the difference in DEVFN usage in U-Boot vs Linux. U-Boot
+ * uses DEVFN in bits 15-8 but Linux instead expects DEVFN in bits 7-0.
+ * Please see the Linux header include/uapi/linux/pci.h for more details.
+ * This is relevant for the following macros:
+ * PCI_DEV, PCI_FUNC, PCI_DEVFN
+ * The U-Boot macro PCI_DEV is equivalent to the Linux PCI_SLOT version with
+ * the remark from above (input d in bits 15-8 instead of 7-0.
+ */
 #define PCI_DEV(d)		(((d) >> 11) & 0x1f)
 #define PCI_FUNC(d)		(((d) >> 8) & 0x7)
 #define PCI_DEVFN(d, f)		((d) << 11 | (f) << 8)
 #define PCI_MASK_BUS(bdf)	((bdf) & 0xffff)
 #define PCI_ADD_BUS(bus, devfn)	(((bus) << 16) | (devfn))
 #define PCI_BDF(b, d, f)	((b) << 16 | PCI_DEVFN(d, f))
 #define PCI_VENDEV(v, d)	(((v) << 16) | (d))
 #define PCI_ANY_ID		(~0)
 struct pci_device_id {
 	unsigned int vendor, device;	/* Vendor and device ID or PCI_ANY_ID */
 	unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
 	unsigned int class, class_mask;	/* (class,subclass,prog-if) triplet */
 	unsigned long driver_data;	/* Data private to the driver */
 };
 struct pci_controller;
 struct pci_config_table {
 	unsigned int vendor, device;		/* Vendor and device ID or PCI_ANY_ID */
 	unsigned int class;			/* Class ID, or  PCI_ANY_ID */
 	unsigned int bus;			/* Bus number, or PCI_ANY_ID */
 	unsigned int dev;			/* Device number, or PCI_ANY_ID */
 	unsigned int func;			/* Function number, or PCI_ANY_ID */
 	void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
 			      struct pci_config_table *);
 	unsigned long priv[3];
 };
 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
 				   struct pci_config_table *);
 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
 				      struct pci_config_table *);
 #define MAX_PCI_REGIONS		7
 #define INDIRECT_TYPE_NO_PCIE_LINK	1
 /*
  * Structure of a PCI controller (host bridge)
  *
  * With driver model this is dev_get_uclass_priv(bus)
  */
 struct pci_controller {
 #ifdef CONFIG_DM_PCI
 	struct udevice *bus;
 	struct udevice *ctlr;
 #else
 	struct pci_controller *next;
 #endif
 	int first_busno;
 	int last_busno;
 	volatile unsigned int *cfg_addr;
 	volatile unsigned char *cfg_data;
 	int indirect_type;
 	/*
 	 * TODO(sjg@chromium.org): With driver model we use struct
 	 * pci_controller for both the controller and any bridge devices
 	 * attached to it. But there is only one region list and it is in the
 	 * top-level controller.
 	 *
 	 * This could be changed so that struct pci_controller is only used
 	 * for PCI controllers and a separate UCLASS (or perhaps
 	 * UCLASS_PCI_GENERIC) is used for bridges.
 	 */
 	struct pci_region regions[MAX_PCI_REGIONS];
 	int region_count;
 	struct pci_config_table *config_table;
 	void (*fixup_irq)(struct pci_controller *, pci_dev_t);
 #ifndef CONFIG_DM_PCI
 	/* Low-level architecture-dependent routines */
 	int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
 	int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
 	int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
 	int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
 	int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
 	int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
 #endif
 	/* Used by auto config */
 	struct pci_region *pci_mem, *pci_io, *pci_prefetch;
 #ifndef CONFIG_DM_PCI
 	int current_busno;
 	void *priv_data;
 #endif
 };
 #ifndef CONFIG_DM_PCI
 static inline void pci_set_ops(struct pci_controller *hose,
 				   int (*read_byte)(struct pci_controller*,
 						    pci_dev_t, int where, u8 *),
 				   int (*read_word)(struct pci_controller*,
 						    pci_dev_t, int where, u16 *),
 				   int (*read_dword)(struct pci_controller*,
 						     pci_dev_t, int where, u32 *),
 				   int (*write_byte)(struct pci_controller*,
 						     pci_dev_t, int where, u8),
 				   int (*write_word)(struct pci_controller*,
 						     pci_dev_t, int where, u16),
 				   int (*write_dword)(struct pci_controller*,
 						      pci_dev_t, int where, u32)) {
 	hose->read_byte   = read_byte;
 	hose->read_word   = read_word;
 	hose->read_dword  = read_dword;
 	hose->write_byte  = write_byte;
 	hose->write_word  = write_word;
 	hose->write_dword = write_dword;
 }
 #endif
 #ifdef CONFIG_PCI_INDIRECT_BRIDGE
 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
 #endif
 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
 					pci_addr_t addr, unsigned long flags);
 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
 					phys_addr_t addr, unsigned long flags);
 #define pci_phys_to_bus(dev, addr, flags) \
 	pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
 #define pci_bus_to_phys(dev, addr, flags) \
 	pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
 #define pci_virt_to_bus(dev, addr, flags) \
 	pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
 			     (virt_to_phys(addr)), (flags))
 #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
 	map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
 					 (addr), (flags)), \
 		    (len), (map_flags))
 #define pci_phys_to_mem(dev, addr) \
 	pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
 #define pci_mem_to_phys(dev, addr) \
 	pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
 #define pci_phys_to_io(dev, addr)  pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
 #define pci_io_to_phys(dev, addr)  pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
 #define pci_virt_to_mem(dev, addr) \
 	pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
 #define pci_mem_to_virt(dev, addr, len, map_flags) \
 	pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
 #define pci_virt_to_io(dev, addr) \
 	pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
 #define pci_io_to_virt(dev, addr, len, map_flags) \
 	pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
 /* For driver model these are defined in macros in pci_compat.c */
 extern int pci_hose_read_config_byte(struct pci_controller *hose,
 				     pci_dev_t dev, int where, u8 *val);
 extern int pci_hose_read_config_word(struct pci_controller *hose,
 				     pci_dev_t dev, int where, u16 *val);
 extern int pci_hose_read_config_dword(struct pci_controller *hose,
 				      pci_dev_t dev, int where, u32 *val);
 extern int pci_hose_write_config_byte(struct pci_controller *hose,
 				      pci_dev_t dev, int where, u8 val);
 extern int pci_hose_write_config_word(struct pci_controller *hose,
 				      pci_dev_t dev, int where, u16 val);
 extern int pci_hose_write_config_dword(struct pci_controller *hose,
 				       pci_dev_t dev, int where, u32 val);
 #endif
 #ifndef CONFIG_DM_PCI
 extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
 extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
 extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
 extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
 extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
 extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
 #endif
 void pciauto_region_init(struct pci_region *res);
 void pciauto_region_align(struct pci_region *res, pci_size_t size);
 void pciauto_config_init(struct pci_controller *hose);
 /**
  * pciauto_region_allocate() - Allocate resources from a PCI resource region
  *
  * Allocates @size bytes from the PCI resource @res. If @supports_64bit is
  * false, the result will be guaranteed to fit in 32 bits.
  *
  * @res:		PCI region to allocate from
  * @size:		Amount of bytes to allocate
  * @bar:		Returns the PCI bus address of the allocated resource
  * @supports_64bit:	Whether to allow allocations above the 32-bit boundary
  * @return 0 if successful, -1 on failure
  */
 int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
 			    pci_addr_t *bar, bool supports_64bit);
 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
 extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
 					       pci_dev_t dev, int where, u8 *val);
 extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
 					       pci_dev_t dev, int where, u16 *val);
 extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
 						pci_dev_t dev, int where, u8 val);
 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
 						pci_dev_t dev, int where, u16 val);
 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
 extern void pci_register_hose(struct pci_controller* hose);
 extern struct pci_controller* pci_bus_to_hose(int bus);
 extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
 extern struct pci_controller *pci_get_hose_head(void);
 extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
 extern int pci_hose_scan(struct pci_controller *hose);
 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
 extern void pciauto_setup_device(struct pci_controller *hose,
 				 pci_dev_t dev, int bars_num,
 				 struct pci_region *mem,
 				 struct pci_region *prefetch,
 				 struct pci_region *io);
 extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 				 pci_dev_t dev, int sub_bus);
 extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
 				 pci_dev_t dev, int sub_bus);
 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
 pci_dev_t pci_find_class(unsigned int find_class, int index);
 extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
 				    int cap);
 extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
 				   u8 hdr_type);
 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
 			int cap);
 int pci_find_next_ext_capability(struct pci_controller *hose,
 				 pci_dev_t dev, int start, int cap);
 int pci_hose_find_ext_capability(struct pci_controller *hose,
 				 pci_dev_t dev, int cap);
 #ifdef CONFIG_PCI_FIXUP_DEV
 extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
 				unsigned short vendor,
 				unsigned short device,
 				unsigned short class);
 #endif
 #endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */
 const char * pci_class_str(u8 class);
 int pci_last_busno(void);
 #ifdef CONFIG_MPC85xx
 extern void pci_mpc85xx_init (struct pci_controller *hose);
 #endif
 #ifdef CONFIG_PCIE_IMX
 extern void imx_pcie_remove(void);
 #endif
 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
 /**
  * pci_write_bar32() - Write the address of a BAR including control bits
  *
  * This writes a raw address (with control bits) to a bar. This can be used
  * with devices which require hard-coded addresses, not part of the normal
  * PCI enumeration process.
  *
  * @hose:	PCI hose to use
  * @dev:	PCI device to update
  * @barnum:	BAR number (0-5)
  * @addr:	BAR address with control bits
  */
 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
 		     u32 addr);
 /**
  * pci_read_bar32() - read the address of a bar
  *
  * @hose:	PCI hose to use
  * @dev:	PCI device to inspect
  * @barnum:	BAR number (0-5)
  * @return address of the bar, masking out any control bits
  * */
 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
 /**
  * pci_hose_find_devices() - Find devices by vendor/device ID
  *
  * @hose:	PCI hose to search
  * @busnum:	Bus number to search
  * @ids:	PCI vendor/device IDs to look for, terminated by 0, 0 record
  * @indexp:	Pointer to device index to find. To find the first matching
  *		device, pass 0; to find the second, pass 1, etc. This
  *		parameter is decremented for each non-matching device so
  *		can be called repeatedly.
  */
 pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
 				struct pci_device_id *ids, int *indexp);
 #endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
 /* Access sizes for PCI reads and writes */
 enum pci_size_t {
 	PCI_SIZE_8,
 	PCI_SIZE_16,
 	PCI_SIZE_32,
 };
 struct udevice;
 #ifdef CONFIG_DM_PCI
 /**
  * struct pci_child_platdata - information stored about each PCI device
  *
  * Every device on a PCI bus has this per-child data.
  *
  * It can be accessed using dev_get_parent_platdata(dev) if dev->parent is a
  * PCI bus (i.e. UCLASS_PCI)
  *
  * @devfn:	Encoded device and function index - see PCI_DEVFN()
  * @vendor:	PCI vendor ID (see pci_ids.h)
  * @device:	PCI device ID (see pci_ids.h)
  * @class:	PCI class, 3 bytes: (base, sub, prog-if)
  */
 struct pci_child_platdata {
 	int devfn;
 	unsigned short vendor;
 	unsigned short device;
 	unsigned int class;
 };
 /* PCI bus operations */
 struct dm_pci_ops {
 	/**
 	 * read_config() - Read a PCI configuration value
 	 *
 	 * PCI buses must support reading and writing configuration values
 	 * so that the bus can be scanned and its devices configured.
 	 *
 	 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always.
 	 * If bridges exist it is possible to use the top-level bus to
 	 * access a sub-bus. In that case @bus will be the top-level bus
 	 * and PCI_BUS(bdf) will be a different (higher) value
 	 *
 	 * @bus:	Bus to read from
 	 * @bdf:	Bus, device and function to read
 	 * @offset:	Byte offset within the device's configuration space
 	 * @valuep:	Place to put the returned value
 	 * @size:	Access size
 	 * @return 0 if OK, -ve on error
 	 */
 	int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
 			   ulong *valuep, enum pci_size_t size);
 	/**
 	 * write_config() - Write a PCI configuration value
 	 *
 	 * @bus:	Bus to write to
 	 * @bdf:	Bus, device and function to write
 	 * @offset:	Byte offset within the device's configuration space
 	 * @value:	Value to write
 	 * @size:	Access size
 	 * @return 0 if OK, -ve on error
 	 */
 	int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
 			    ulong value, enum pci_size_t size);
 };
 /* Get access to a PCI bus' operations */
 #define pci_get_ops(dev)	((struct dm_pci_ops *)(dev)->driver->ops)
 /**
  * dm_pci_get_bdf() - Get the BDF value for a device
  *
  * @dev:	Device to check
  * @return bus/device/function value (see PCI_BDF())
  */
 pci_dev_t dm_pci_get_bdf(struct udevice *dev);
 /**
  * pci_bind_bus_devices() - scan a PCI bus and bind devices
  *
  * Scan a PCI bus looking for devices. Bind each one that is found. If
  * devices are already bound that match the scanned devices, just update the
  * child data so that the device can be used correctly (this happens when
  * the device tree describes devices we expect to see on the bus).
  *
  * Devices that are bound in this way will use a generic PCI driver which
  * does nothing. The device can still be accessed but will not provide any
  * driver interface.
  *
  * @bus:	Bus containing devices to bind
  * @return 0 if OK, -ve on error
  */
 int pci_bind_bus_devices(struct udevice *bus);
 /**
  * pci_auto_config_devices() - configure bus devices ready for use
  *
  * This works through all devices on a bus by scanning the driver model
  * data structures (normally these have been set up by pci_bind_bus_devices()
  * earlier).
  *
  * Space is allocated for each PCI base address register (BAR) so that the
  * devices are mapped into memory and I/O space ready for use.
  *
  * @bus:	Bus containing devices to bind
  * @return 0 if OK, -ve on error
  */
 int pci_auto_config_devices(struct udevice *bus);
 /**
  * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
  *
  * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
  * @devp:	Returns the device for this address, if found
  * @return 0 if OK, -ENODEV if not found
  */
 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
 /**
  * pci_bus_find_devfn() - Find a device on a bus
  *
  * @find_devfn:		PCI device address (device and function only)
  * @devp:	Returns the device for this address, if found
  * @return 0 if OK, -ENODEV if not found
  */
 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
 		       struct udevice **devp);
 /**
  * pci_find_first_device() - return the first available PCI device
  *
  * This function and pci_find_first_device() allow iteration through all
  * available PCI devices on all buses. Assuming there are any, this will
  * return the first one.
  *
  * @devp:	Set to the first available device, or NULL if no more are left
  *		or we got an error
  * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
  */
 int pci_find_first_device(struct udevice **devp);
 /**
  * pci_find_next_device() - return the next available PCI device
  *
  * Finds the next available PCI device after the one supplied, or sets @devp
  * to NULL if there are no more.
  *
  * @devp:	On entry, the last device returned. Set to the next available
  *		device, or NULL if no more are left or we got an error
  * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
  */
 int pci_find_next_device(struct udevice **devp);
 /**
  * pci_get_ff() - Returns a mask for the given access size
  *
  * @size:	Access size
  * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
  * PCI_SIZE_32
  */
 int pci_get_ff(enum pci_size_t size);
 /**
  * pci_bus_find_devices () - Find devices on a bus
  *
  * @bus:	Bus to search
  * @ids:	PCI vendor/device IDs to look for, terminated by 0, 0 record
  * @indexp:	Pointer to device index to find. To find the first matching
  *		device, pass 0; to find the second, pass 1, etc. This
  *		parameter is decremented for each non-matching device so
  *		can be called repeatedly.
  * @devp:	Returns matching device if found
  * @return 0 if found, -ENODEV if not
  */
 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
 			 int *indexp, struct udevice **devp);
 /**
  * pci_find_device_id() - Find a device on any bus
  *
  * @ids:	PCI vendor/device IDs to look for, terminated by 0, 0 record
  * @index:	Index number of device to find, 0 for the first match, 1 for
  *		the second, etc.
  * @devp:	Returns matching device if found
  * @return 0 if found, -ENODEV if not
  */
 int pci_find_device_id(struct pci_device_id *ids, int index,
 		       struct udevice **devp);
 /**
  * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices
  *
  * This probes the given bus which causes it to be scanned for devices. The
  * devices will be bound but not probed.
  *
  * @hose specifies the PCI hose that will be used for the scan. This is
  * always a top-level bus with uclass UCLASS_PCI. The bus to scan is
  * in @bdf, and is a subordinate bus reachable from @hose.
  *
  * @hose:	PCI hose to scan
  * @bdf:	PCI bus address to scan (PCI_BUS(bdf) is the bus number)
  * @return 0 if OK, -ve on error
  */
 int dm_pci_hose_probe_bus(struct udevice *bus);
 /**
  * pci_bus_read_config() - Read a configuration value from a device
  *
  * TODO(sjg@chromium.org): We should be able to pass just a device and have
  * it do the right thing. It would be good to have that function also.
  *
  * @bus:	Bus to read from
  * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
  * @offset:	Register offset to read
  * @valuep:	Place to put the returned value
  * @size:	Access size
  * @return 0 if OK, -ve on error
  */
 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
 			unsigned long *valuep, enum pci_size_t size);
 /**
  * pci_bus_write_config() - Write a configuration value to a device
  *
  * @bus:	Bus to write from
  * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
  * @offset:	Register offset to write
  * @value:	Value to write
  * @size:	Access size
  * @return 0 if OK, -ve on error
  */
 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
 			 unsigned long value, enum pci_size_t size);
 /**
  * pci_bus_clrset_config32() - Update a configuration value for a device
  *
  * The register at @offset is updated to (oldvalue & ~clr) | set.
  *
  * @bus:	Bus to access
  * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
  * @offset:	Register offset to update
  * @clr:	Bits to clear
  * @set:	Bits to set
  * @return 0 if OK, -ve on error
  */
 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
 			    u32 clr, u32 set);
 /**
  * Driver model PCI config access functions. Use these in preference to others
  * when you have a valid device
  */
 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
 		       enum pci_size_t size);
 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep);
 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep);
 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep);
 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
 			enum pci_size_t size);
 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
 /**
  * These permit convenient read/modify/write on PCI configuration. The
  * register is updated to (oldvalue & ~clr) | set.
  */
 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
 /*
  * The following functions provide access to the above without needing the
  * size parameter. We are trying to encourage the use of the 8/16/32-style
  * functions, rather than byte/word/dword. But both are supported.
  */
 int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
 int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
 int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
 int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
 int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
 int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
 /**
  * pci_generic_mmap_write_config() - Generic helper for writing to
  * memory-mapped PCI configuration space.
  * @bus: Pointer to the PCI bus
  * @addr_f: Callback for calculating the config space address
  * @bdf: Identifies the PCI device to access
  * @offset: The offset into the device's configuration space
  * @value: The value to write
  * @size: Indicates the size of access to perform
  *
  * Write the value @value of size @size from offset @offset within the
  * configuration space of the device identified by the bus, device & function
  * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is
  * responsible for calculating the CPU address of the respective configuration
  * space offset.
  *
  * Return: 0 on success, else -EINVAL
  */
 int pci_generic_mmap_write_config(
 	struct udevice *bus,
 	int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
 	pci_dev_t bdf,
 	uint offset,
 	ulong value,
 	enum pci_size_t size);
 /**
  * pci_generic_mmap_read_config() - Generic helper for reading from
  * memory-mapped PCI configuration space.
  * @bus: Pointer to the PCI bus
  * @addr_f: Callback for calculating the config space address
  * @bdf: Identifies the PCI device to access
  * @offset: The offset into the device's configuration space
  * @valuep: A pointer at which to store the read value
  * @size: Indicates the size of access to perform
  *
  * Read a value of size @size from offset @offset within the configuration
  * space of the device identified by the bus, device & function numbers in @bdf
  * on the PCI bus @bus. The callback function @addr_f is responsible for
  * calculating the CPU address of the respective configuration space offset.
  *
  * Return: 0 on success, else -EINVAL
  */
 int pci_generic_mmap_read_config(
 	struct udevice *bus,
 	int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
 	pci_dev_t bdf,
 	uint offset,
 	ulong *valuep,
 	enum pci_size_t size);
 #ifdef CONFIG_DM_PCI_COMPAT
 /* Compatibility with old naming */
 static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
 					 u32 value)
 {
 	return pci_write_config32(pcidev, offset, value);
 }
 /* Compatibility with old naming */
 static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
 					u16 value)
 {
 	return pci_write_config16(pcidev, offset, value);
 }
 /* Compatibility with old naming */
 static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
 					u8 value)
 {
 	return pci_write_config8(pcidev, offset, value);
 }
 /* Compatibility with old naming */
 static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
 					u32 *valuep)
 {
 	return pci_read_config32(pcidev, offset, valuep);
 }
 /* Compatibility with old naming */
 static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
 				       u16 *valuep)
 {
 	return pci_read_config16(pcidev, offset, valuep);
 }
 /* Compatibility with old naming */
 static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
 				       u8 *valuep)
 {
 	return pci_read_config8(pcidev, offset, valuep);
 }
 #endif /* CONFIG_DM_PCI_COMPAT */
 /**
  * dm_pciauto_config_device() - configure a device ready for use
  *
  * Space is allocated for each PCI base address register (BAR) so that the
  * devices are mapped into memory and I/O space ready for use.
  *
  * @dev:	Device to configure
  * @return 0 if OK, -ve on error
  */
 int dm_pciauto_config_device(struct udevice *dev);
 /**
  * pci_conv_32_to_size() - convert a 32-bit read value to the given size
  *
  * Some PCI buses must always perform 32-bit reads. The data must then be
  * shifted and masked to reflect the required access size and offset. This
  * function performs this transformation.
  *
  * @value:	Value to transform (32-bit value read from @offset & ~3)
  * @offset:	Register offset that was read
  * @size:	Required size of the result
  * @return the value that would have been obtained if the read had been
  * performed at the given offset with the correct size
  */
 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
 /**
  * pci_conv_size_to_32() - update a 32-bit value to prepare for a write
  *
  * Some PCI buses must always perform 32-bit writes. To emulate a smaller
  * write the old 32-bit data must be read, updated with the required new data
  * and written back as a 32-bit value. This function performs the
  * transformation from the old value to the new value.
  *
  * @value:	Value to transform (32-bit value read from @offset & ~3)
  * @offset:	Register offset that should be written
  * @size:	Required size of the write
  * @return the value that should be written as a 32-bit access to @offset & ~3.
  */
 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
 			  enum pci_size_t size);
 /**
  * pci_get_controller() - obtain the controller to use for a bus
  *
  * @dev:	Device to check
  * @return pointer to the controller device for this bus
  */
 struct udevice *pci_get_controller(struct udevice *dev);
 /**
  * pci_get_regions() - obtain pointers to all the region types
  *
  * @dev:	Device to check
  * @iop:	Returns a pointer to the I/O region, or NULL if none
  * @memp:	Returns a pointer to the memory region, or NULL if none
  * @prefp:	Returns a pointer to the pre-fetch region, or NULL if none
  * @return the number of non-NULL regions returned, normally 3
  */
 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
 		    struct pci_region **memp, struct pci_region **prefp);
 /**
  * dm_pci_write_bar32() - Write the address of a BAR
  *
  * This writes a raw address to a bar
  *
  * @dev:	PCI device to update
  * @barnum:	BAR number (0-5)
  * @addr:	BAR address
  */
 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
 /**
  * dm_pci_read_bar32() - read a base address register from a device
  *
  * @dev:	Device to check
  * @barnum:	Bar number to read (numbered from 0)
  * @return: value of BAR
  */
 u32 dm_pci_read_bar32(struct udevice *dev, int barnum);
 /**
  * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address
  *
  * @dev:	Device containing the PCI address
  * @addr:	PCI address to convert
  * @flags:	Flags for the region type (PCI_REGION_...)
  * @return physical address corresponding to that PCI bus address
  */
 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
 			       unsigned long flags);
 /**
  * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
  *
  * @dev:	Device containing the bus address
  * @addr:	Physical address to convert
  * @flags:	Flags for the region type (PCI_REGION_...)
  * @return PCI bus address corresponding to that physical address
  */
 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
 			      unsigned long flags);
 /**
  * dm_pci_map_bar() - get a virtual address associated with a BAR region
  *
  * Looks up a base address register and finds the physical memory address
  * that corresponds to it
  *
  * @dev:	Device to check
  * @bar:	Bar number to read (numbered from 0)
  * @flags:	Flags for the region type (PCI_REGION_...)
  * @return: pointer to the virtual address to use
  */
 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
 /**
  * dm_pci_find_next_capability() - find a capability starting from an offset
  *
  * Tell if a device supports a given PCI capability. Returns the
  * address of the requested capability structure within the device's
  * PCI configuration space or 0 in case the device does not support it.
  *
  * Possible values for @cap:
  *
  *  %PCI_CAP_ID_MSI	Message Signalled Interrupts
  *  %PCI_CAP_ID_PCIX	PCI-X
  *  %PCI_CAP_ID_EXP	PCI Express
  *  %PCI_CAP_ID_MSIX	MSI-X
  *
  * See PCI_CAP_ID_xxx for the complete capability ID codes.
  *
  * @dev:	PCI device to query
  * @start:	offset to start from
  * @cap:	capability code
  * @return:	capability address or 0 if not supported
  */
 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap);
 /**
  * dm_pci_find_capability() - find a capability
  *
  * Tell if a device supports a given PCI capability. Returns the
  * address of the requested capability structure within the device's
  * PCI configuration space or 0 in case the device does not support it.
  *
  * Possible values for @cap:
  *
  *  %PCI_CAP_ID_MSI	Message Signalled Interrupts
  *  %PCI_CAP_ID_PCIX	PCI-X
  *  %PCI_CAP_ID_EXP	PCI Express
  *  %PCI_CAP_ID_MSIX	MSI-X
  *
  * See PCI_CAP_ID_xxx for the complete capability ID codes.
  *
  * @dev:	PCI device to query
  * @cap:	capability code
  * @return:	capability address or 0 if not supported
  */
 int dm_pci_find_capability(struct udevice *dev, int cap);
 /**
  * dm_pci_find_next_ext_capability() - find an extended capability
  *				       starting from an offset
  *
  * Tell if a device supports a given PCI express extended capability.
  * Returns the address of the requested extended capability structure
  * within the device's PCI configuration space or 0 in case the device
  * does not support it.
  *
  * Possible values for @cap:
  *
  *  %PCI_EXT_CAP_ID_ERR	Advanced Error Reporting
  *  %PCI_EXT_CAP_ID_VC	Virtual Channel
  *  %PCI_EXT_CAP_ID_DSN	Device Serial Number
  *  %PCI_EXT_CAP_ID_PWR	Power Budgeting
  *
  * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
  *
  * @dev:	PCI device to query
  * @start:	offset to start from
  * @cap:	extended capability code
  * @return:	extended capability address or 0 if not supported
  */
 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap);
 /**
  * dm_pci_find_ext_capability() - find an extended capability
  *
  * Tell if a device supports a given PCI express extended capability.
  * Returns the address of the requested extended capability structure
  * within the device's PCI configuration space or 0 in case the device
  * does not support it.
  *
  * Possible values for @cap:
  *
  *  %PCI_EXT_CAP_ID_ERR	Advanced Error Reporting
  *  %PCI_EXT_CAP_ID_VC	Virtual Channel
  *  %PCI_EXT_CAP_ID_DSN	Device Serial Number
  *  %PCI_EXT_CAP_ID_PWR	Power Budgeting
  *
  * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
  *
  * @dev:	PCI device to query
  * @cap:	extended capability code
  * @return:	extended capability address or 0 if not supported
  */
 int dm_pci_find_ext_capability(struct udevice *dev, int cap);
 #define dm_pci_virt_to_bus(dev, addr, flags) \
 	dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
 #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
 	map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
 		    (len), (map_flags))
 #define dm_pci_phys_to_mem(dev, addr) \
 	dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
 #define dm_pci_mem_to_phys(dev, addr) \
 	dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
 #define dm_pci_phys_to_io(dev, addr) \
 	dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
 #define dm_pci_io_to_phys(dev, addr) \
 	dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
 #define dm_pci_virt_to_mem(dev, addr) \
 	dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
 #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
 	dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
 #define dm_pci_virt_to_io(dev, addr) \
 	dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
 #define dm_pci_io_to_virt(dev, addr, len, map_flags) \
 	dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
 /**
  * dm_pci_find_device() - find a device by vendor/device ID
  *
  * @vendor:	Vendor ID
  * @device:	Device ID
  * @index:	0 to find the first match, 1 for second, etc.
  * @devp:	Returns pointer to the device, if found
  * @return 0 if found, -ve on error
  */
 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
 		       struct udevice **devp);
 /**
  * dm_pci_find_class() - find a device by class
  *
  * @find_class: 3-byte (24-bit) class value to find
  * @index:	0 to find the first match, 1 for second, etc.
  * @devp:	Returns pointer to the device, if found
  * @return 0 if found, -ve on error
  */
 int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
 /**
  * struct dm_pci_emul_ops - PCI device emulator operations
  */
 struct dm_pci_emul_ops {
 	/**
 	 * get_devfn(): Check which device and function this emulators
 	 *
 	 * @dev:	device to check
 	 * @return the device and function this emulates, or -ve on error
 	 */
 	int (*get_devfn)(struct udevice *dev);
 	/**
 	 * read_config() - Read a PCI configuration value
 	 *
 	 * @dev:	Emulated device to read from
 	 * @offset:	Byte offset within the device's configuration space
 	 * @valuep:	Place to put the returned value
 	 * @size:	Access size
 	 * @return 0 if OK, -ve on error
 	 */
 	int (*read_config)(struct udevice *dev, uint offset, ulong *valuep,
 			   enum pci_size_t size);
 	/**
 	 * write_config() - Write a PCI configuration value
 	 *
 	 * @dev:	Emulated device to write to
 	 * @offset:	Byte offset within the device's configuration space
 	 * @value:	Value to write
 	 * @size:	Access size
 	 * @return 0 if OK, -ve on error
 	 */
 	int (*write_config)(struct udevice *dev, uint offset, ulong value,
 			    enum pci_size_t size);
 	/**
 	 * read_io() - Read a PCI I/O value
 	 *
 	 * @dev:	Emulated device to read from
 	 * @addr:	I/O address to read
 	 * @valuep:	Place to put the returned value
 	 * @size:	Access size
 	 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
 	 *		other -ve value on error
 	 */
 	int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
 		       enum pci_size_t size);
 	/**
 	 * write_io() - Write a PCI I/O value
 	 *
 	 * @dev:	Emulated device to write from
 	 * @addr:	I/O address to write
 	 * @value:	Value to write
 	 * @size:	Access size
 	 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
 	 *		other -ve value on error
 	 */
 	int (*write_io)(struct udevice *dev, unsigned int addr,
 			ulong value, enum pci_size_t size);
 	/**
 	 * map_physmem() - Map a device into sandbox memory
 	 *
 	 * @dev:	Emulated device to map
 	 * @addr:	Memory address, normally corresponding to a PCI BAR.
 	 *		The device should have been configured to have a BAR
 	 *		at this address.
 	 * @lenp:	On entry, the size of the area to map, On exit it is
 	 *		updated to the size actually mapped, which may be less
 	 *		if the device has less space
 	 * @ptrp:	Returns a pointer to the mapped address. The device's
 	 *		space can be accessed as @lenp bytes starting here
 	 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
 	 *		other -ve value on error
 	 */
 	int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
 			   unsigned long *lenp, void **ptrp);
 	/**
 	 * unmap_physmem() - undo a memory mapping
 	 *
 	 * This must be called after map_physmem() to undo the mapping.
 	 * Some devices can use this to check what has been written into
 	 * their mapped memory and perform an operations they require on it.
 	 * In this way, map/unmap can be used as a sort of handshake between
 	 * the emulated device and its users.
 	 *
 	 * @dev:	Emuated device to unmap
 	 * @vaddr:	Mapped memory address, as passed to map_physmem()
 	 * @len:	Size of area mapped, as returned by map_physmem()
 	 * @return 0 if OK, -ve on error
 	 */
 	int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
 			     unsigned long len);
 };
 /* Get access to a PCI device emulator's operations */
 #define pci_get_emul_ops(dev)	((struct dm_pci_emul_ops *)(dev)->driver->ops)
 /**
  * sandbox_pci_get_emul() - Get the emulation device for a PCI device
  *
  * Searches for a suitable emulator for the given PCI bus device
  *
  * @bus:	PCI bus to search
  * @find_devfn:	PCI device and function address (PCI_DEVFN())
  * @containerp:	Returns container device if found
  * @emulp:	Returns emulated device if found
  * @return 0 if found, -ENODEV if not found
  */
 int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
 			 struct udevice **containerp, struct udevice **emulp);
 /**
  * pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device
  *
  * Get devfn from fdt_pci_addr of the specifified device
  *
  * @dev:	PCI device
  * @return devfn in bits 15...8 if found, -ENODEV if not found
  */
 int pci_get_devfn(struct udevice *dev);
 #endif /* CONFIG_DM_PCI */
 /**
  * PCI_DEVICE - macro used to describe a specific pci device
  * @vend: the 16 bit PCI Vendor ID
  * @dev: the 16 bit PCI Device ID
  *
  * This macro is used to create a struct pci_device_id that matches a
  * specific device.  The subvendor and subdevice fields will be set to
  * PCI_ANY_ID.
  */
 #define PCI_DEVICE(vend, dev) \
 	.vendor = (vend), .device = (dev), \
 	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
 /**
  * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
  * @vend: the 16 bit PCI Vendor ID
  * @dev: the 16 bit PCI Device ID
  * @subvend: the 16 bit PCI Subvendor ID
  * @subdev: the 16 bit PCI Subdevice ID
  *
  * This macro is used to create a struct pci_device_id that matches a
  * specific device with subsystem information.
  */
 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
 	.vendor = (vend), .device = (dev), \
 	.subvendor = (subvend), .subdevice = (subdev)
 /**
  * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
  * @dev_class: the class, subclass, prog-if triple for this device
  * @dev_class_mask: the class mask for this device
  *
  * This macro is used to create a struct pci_device_id that matches a
  * specific PCI class.  The vendor, device, subvendor, and subdevice
  * fields will be set to PCI_ANY_ID.
  */
 #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
 	.class = (dev_class), .class_mask = (dev_class_mask), \
 	.vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
 	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
 /**
  * PCI_VDEVICE - macro used to describe a specific pci device in short form
  * @vend: the vendor name
  * @dev: the 16 bit PCI Device ID
  *
  * This macro is used to create a struct pci_device_id that matches a
  * specific PCI device.  The subvendor, and subdevice fields will be set
  * to PCI_ANY_ID. The macro allows the next field to follow as the device
  * private data.
  */
 #define PCI_VDEVICE(vend, dev) \
 	.vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
 	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
 /**
  * struct pci_driver_entry - Matches a driver to its pci_device_id list
  * @driver: Driver to use
  * @match: List of match records for this driver, terminated by {}
  */
 struct pci_driver_entry {
 	struct driver *driver;
 	const struct pci_device_id *match;
 };
 #define U_BOOT_PCI_DEVICE(__name, __match)				\
 	ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
 		.driver = llsym(struct driver, __name, driver), \
 		.match = __match, \
 		}
 #endif /* __ASSEMBLY__ */
 #endif /* _PCI_H */