Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 2330001afc27b3150e961be6b0775f174c0900ce

Authored by Utkarsh Gupta
Committed by Ye Li
1 parent 15ecd669ac
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 4 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-20893: imx: in_le32 out_le32 preprocessor casting issue with addresses involving math 

The sec_in32 preprocessor is defined as follows in include/fsl_sec.h file:
When address "a" is calculated using math for ex: addition of base address and an offset, then casting is applied only to the first address which in this example is base address.

caam_ccbvid_reg = sec_in32(CONFIG_SYS_FSL_SEC_ADDR + CAAM_CCBVID_OFFSET)
resolves to:
caam_ccbvid_reg = in_le32((ulong *)(ulong)CONFIG_SYS_FSL_SEC_ADDR + CAAM_CCBVID_OFFSET)
instead it should resolve to:
caam_ccbvid_reg = in_le32((ulong *)(ulong)(CONFIG_SYS_FSL_SEC_ADDR + CAAM_CCBVID_OFFSET))

Thus add parenthesis around the address "a" so that however the address is calculated, the casting is applied to the final calculated address.

Bug introduced by commit 79e90af14af3 ("MLK-18044-2: crypto: caam: Fix build warnings pointer casting").

Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 5d10d1cab052f8af4fd00640e09642aa0a596922)

Showing 1 changed file with 2 additions and 2 deletions Inline Diff

1 /* 1 /*
2 * Common internal memory map for some Freescale SoCs 2 * Common internal memory map for some Freescale SoCs
3 * 3 *
4 * Copyright 2014 Freescale Semiconductor, Inc. 4 * Copyright 2014 Freescale Semiconductor, Inc.
5 * Copyright 2018 NXP 5 * Copyright 2018 NXP
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 #ifndef __FSL_SEC_H 10 #ifndef __FSL_SEC_H
11 #define __FSL_SEC_H 11 #define __FSL_SEC_H
12 12
13 #include <common.h> 13 #include <common.h>
14 #include <asm/io.h> 14 #include <asm/io.h>
15 15
16 #ifdef CONFIG_SYS_FSL_SEC_LE 16 #ifdef CONFIG_SYS_FSL_SEC_LE
17 #define sec_in32(a) in_le32((ulong *)(ulong)a) 17 #define sec_in32(a) in_le32((ulong *)(ulong)(a))
18 #define sec_out32(a, v) out_le32((ulong *)(ulong)a, v) 18 #define sec_out32(a, v) out_le32((ulong *)(ulong)(a), v)
19 #define sec_in16(a) in_le16(a) 19 #define sec_in16(a) in_le16(a)
20 #define sec_clrbits32 clrbits_le32 20 #define sec_clrbits32 clrbits_le32
21 #define sec_setbits32 setbits_le32 21 #define sec_setbits32 setbits_le32
22 #elif defined(CONFIG_SYS_FSL_SEC_BE) 22 #elif defined(CONFIG_SYS_FSL_SEC_BE)
23 #define sec_in32(a) in_be32(a) 23 #define sec_in32(a) in_be32(a)
24 #define sec_out32(a, v) out_be32(a, v) 24 #define sec_out32(a, v) out_be32(a, v)
25 #define sec_in16(a) in_be16(a) 25 #define sec_in16(a) in_be16(a)
26 #define sec_clrbits32 clrbits_be32 26 #define sec_clrbits32 clrbits_be32
27 #define sec_setbits32 setbits_be32 27 #define sec_setbits32 setbits_be32
28 #elif defined(CONFIG_SYS_FSL_HAS_SEC) 28 #elif defined(CONFIG_SYS_FSL_HAS_SEC)
29 #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined 29 #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
30 #endif 30 #endif
31 31
32 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ 32 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
33 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 33 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
34 /* RNG4 TRNG test registers */ 34 /* RNG4 TRNG test registers */
35 struct rng4tst { 35 struct rng4tst {
36 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ 36 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
37 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in 37 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
38 both entropy shifter and 38 both entropy shifter and
39 statistical checker */ 39 statistical checker */
40 #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both 40 #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both
41 entropy shifter and 41 entropy shifter and
42 statistical checker */ 42 statistical checker */
43 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in 43 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
44 entropy shifter, raw data 44 entropy shifter, raw data
45 in statistical checker */ 45 in statistical checker */
46 #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */ 46 #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */
47 u32 rtmctl; /* misc. control register */ 47 u32 rtmctl; /* misc. control register */
48 u32 rtscmisc; /* statistical check misc. register */ 48 u32 rtscmisc; /* statistical check misc. register */
49 u32 rtpkrrng; /* poker range register */ 49 u32 rtpkrrng; /* poker range register */
50 #define RTSDCTL_ENT_DLY_MIN 3200 50 #define RTSDCTL_ENT_DLY_MIN 3200
51 #define RTSDCTL_ENT_DLY_MAX 12800 51 #define RTSDCTL_ENT_DLY_MAX 12800
52 union { 52 union {
53 u32 rtpkrmax; /* PRGM=1: poker max. limit register */ 53 u32 rtpkrmax; /* PRGM=1: poker max. limit register */
54 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ 54 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
55 }; 55 };
56 #define RTSDCTL_ENT_DLY_SHIFT 16 56 #define RTSDCTL_ENT_DLY_SHIFT 16
57 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) 57 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
58 u32 rtsdctl; /* seed control register */ 58 u32 rtsdctl; /* seed control register */
59 union { 59 union {
60 u32 rtsblim; /* PRGM=1: sparse bit limit register */ 60 u32 rtsblim; /* PRGM=1: sparse bit limit register */
61 u32 rttotsam; /* PRGM=0: total samples register */ 61 u32 rttotsam; /* PRGM=0: total samples register */
62 }; 62 };
63 u32 rtfreqmin; /* frequency count min. limit register */ 63 u32 rtfreqmin; /* frequency count min. limit register */
64 #define RTFRQMAX_DISABLE (1 << 20) 64 #define RTFRQMAX_DISABLE (1 << 20)
65 union { 65 union {
66 u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */ 66 u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
67 u32 rtfreqcnt; /* PRGM=0: freq. count register */ 67 u32 rtfreqcnt; /* PRGM=0: freq. count register */
68 }; 68 };
69 u32 rsvd1[40]; 69 u32 rsvd1[40];
70 #define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001 70 #define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
71 #define RNG_STATE1_HANDLE_INSTANTIATED 0x00000002 71 #define RNG_STATE1_HANDLE_INSTANTIATED 0x00000002
72 #define RNG_STATE_HANDLE_MASK \ 72 #define RNG_STATE_HANDLE_MASK \
73 (RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED) 73 (RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED)
74 u32 rdsta; /*RNG DRNG Status Register*/ 74 u32 rdsta; /*RNG DRNG Status Register*/
75 u32 rsvd2[15]; 75 u32 rsvd2[15];
76 }; 76 };
77 77
78 typedef struct ccsr_sec { 78 typedef struct ccsr_sec {
79 u32 res0; 79 u32 res0;
80 u32 mcfgr; /* Master CFG Register */ 80 u32 mcfgr; /* Master CFG Register */
81 u8 res1[0x4]; 81 u8 res1[0x4];
82 u32 scfgr; 82 u32 scfgr;
83 struct { 83 struct {
84 u32 ms; /* Job Ring LIODN Register, MS */ 84 u32 ms; /* Job Ring LIODN Register, MS */
85 u32 ls; /* Job Ring LIODN Register, LS */ 85 u32 ls; /* Job Ring LIODN Register, LS */
86 } jrliodnr[4]; 86 } jrliodnr[4];
87 u8 res2[0x2c]; 87 u8 res2[0x2c];
88 u32 jrstartr; /* Job Ring Start Register */ 88 u32 jrstartr; /* Job Ring Start Register */
89 struct { 89 struct {
90 u32 ms; /* RTIC LIODN Register, MS */ 90 u32 ms; /* RTIC LIODN Register, MS */
91 u32 ls; /* RTIC LIODN Register, LS */ 91 u32 ls; /* RTIC LIODN Register, LS */
92 } rticliodnr[4]; 92 } rticliodnr[4];
93 u8 res3[0x1c]; 93 u8 res3[0x1c];
94 u32 decorr; /* DECO Request Register */ 94 u32 decorr; /* DECO Request Register */
95 struct { 95 struct {
96 u32 ms; /* DECO LIODN Register, MS */ 96 u32 ms; /* DECO LIODN Register, MS */
97 u32 ls; /* DECO LIODN Register, LS */ 97 u32 ls; /* DECO LIODN Register, LS */
98 } decoliodnr[8]; 98 } decoliodnr[8];
99 u8 res4[0x40]; 99 u8 res4[0x40];
100 u32 dar; /* DECO Avail Register */ 100 u32 dar; /* DECO Avail Register */
101 u32 drr; /* DECO Reset Register */ 101 u32 drr; /* DECO Reset Register */
102 u8 res5[0x4d8]; 102 u8 res5[0x4d8];
103 struct rng4tst rng; /* RNG Registers */ 103 struct rng4tst rng; /* RNG Registers */
104 u8 res6[0x8a0]; 104 u8 res6[0x8a0];
105 u32 crnr_ms; /* CHA Revision Number Register, MS */ 105 u32 crnr_ms; /* CHA Revision Number Register, MS */
106 u32 crnr_ls; /* CHA Revision Number Register, LS */ 106 u32 crnr_ls; /* CHA Revision Number Register, LS */
107 u32 ctpr_ms; /* Compile Time Parameters Register, MS */ 107 u32 ctpr_ms; /* Compile Time Parameters Register, MS */
108 u32 ctpr_ls; /* Compile Time Parameters Register, LS */ 108 u32 ctpr_ls; /* Compile Time Parameters Register, LS */
109 u8 res7[0x10]; 109 u8 res7[0x10];
110 u32 far_ms; /* Fault Address Register, MS */ 110 u32 far_ms; /* Fault Address Register, MS */
111 u32 far_ls; /* Fault Address Register, LS */ 111 u32 far_ls; /* Fault Address Register, LS */
112 u32 falr; /* Fault Address LIODN Register */ 112 u32 falr; /* Fault Address LIODN Register */
113 u32 fadr; /* Fault Address Detail Register */ 113 u32 fadr; /* Fault Address Detail Register */
114 u8 res8[0x4]; 114 u8 res8[0x4];
115 u32 csta; /* CAAM Status Register */ 115 u32 csta; /* CAAM Status Register */
116 u32 smpart; /* Secure Memory Partition Parameters */ 116 u32 smpart; /* Secure Memory Partition Parameters */
117 u32 smvid; /* Secure Memory Version ID */ 117 u32 smvid; /* Secure Memory Version ID */
118 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ 118 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
119 u32 ccbvid; /* CHA Cluster Block Version ID Register */ 119 u32 ccbvid; /* CHA Cluster Block Version ID Register */
120 u32 chavid_ms; /* CHA Version ID Register, MS */ 120 u32 chavid_ms; /* CHA Version ID Register, MS */
121 u32 chavid_ls; /* CHA Version ID Register, LS */ 121 u32 chavid_ls; /* CHA Version ID Register, LS */
122 u32 chanum_ms; /* CHA Number Register, MS */ 122 u32 chanum_ms; /* CHA Number Register, MS */
123 u32 chanum_ls; /* CHA Number Register, LS */ 123 u32 chanum_ls; /* CHA Number Register, LS */
124 u32 secvid_ms; /* SEC Version ID Register, MS */ 124 u32 secvid_ms; /* SEC Version ID Register, MS */
125 u32 secvid_ls; /* SEC Version ID Register, LS */ 125 u32 secvid_ls; /* SEC Version ID Register, LS */
126 u8 res9[0x6020]; 126 u8 res9[0x6020];
127 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ 127 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
128 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ 128 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
129 u8 res10[0x8fd8]; 129 u8 res10[0x8fd8];
130 } ccsr_sec_t; 130 } ccsr_sec_t;
131 131
132 #define SEC_CTPR_MS_AXI_LIODN 0x08000000 132 #define SEC_CTPR_MS_AXI_LIODN 0x08000000
133 #define SEC_CTPR_MS_QI 0x02000000 133 #define SEC_CTPR_MS_QI 0x02000000
134 #define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001 134 #define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
135 #define SEC_CTPR_MS_VIRT_EN_POR 0x00000002 135 #define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
136 #define SEC_RVID_MA 0x0f000000 136 #define SEC_RVID_MA 0x0f000000
137 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000 137 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
138 #define SEC_CHANUM_MS_JRNUM_SHIFT 28 138 #define SEC_CHANUM_MS_JRNUM_SHIFT 28
139 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 139 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
140 #define SEC_CHANUM_MS_DECONUM_SHIFT 24 140 #define SEC_CHANUM_MS_DECONUM_SHIFT 24
141 #define SEC_SECVID_MS_IPID_MASK 0xffff0000 141 #define SEC_SECVID_MS_IPID_MASK 0xffff0000
142 #define SEC_SECVID_MS_IPID_SHIFT 16 142 #define SEC_SECVID_MS_IPID_SHIFT 16
143 #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00 143 #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
144 #define SEC_SECVID_MS_MAJ_REV_SHIFT 8 144 #define SEC_SECVID_MS_MAJ_REV_SHIFT 8
145 #define SEC_CCBVID_ERA_MASK 0xff000000 145 #define SEC_CCBVID_ERA_MASK 0xff000000
146 #define SEC_CCBVID_ERA_SHIFT 24 146 #define SEC_CCBVID_ERA_SHIFT 24
147 #define SEC_SCFGR_RDBENABLE 0x00000400 147 #define SEC_SCFGR_RDBENABLE 0x00000400
148 #define SEC_SCFGR_VIRT_EN 0x00008000 148 #define SEC_SCFGR_VIRT_EN 0x00008000
149 #define SEC_CHAVID_LS_RNG_SHIFT 16 149 #define SEC_CHAVID_LS_RNG_SHIFT 16
150 #define SEC_CHAVID_RNG_LS_MASK 0x000f0000 150 #define SEC_CHAVID_RNG_LS_MASK 0x000f0000
151 151
152 #define CONFIG_JRSTARTR_JR0 0x00000001 152 #define CONFIG_JRSTARTR_JR0 0x00000001
153 153
154 struct jr_regs { 154 struct jr_regs {
155 #if defined(CONFIG_SYS_FSL_SEC_LE) && \ 155 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
156 !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ 156 !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
157 defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) 157 defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
158 u32 irba_l; 158 u32 irba_l;
159 u32 irba_h; 159 u32 irba_h;
160 #else 160 #else
161 u32 irba_h; 161 u32 irba_h;
162 u32 irba_l; 162 u32 irba_l;
163 #endif 163 #endif
164 u32 rsvd1; 164 u32 rsvd1;
165 u32 irs; 165 u32 irs;
166 u32 rsvd2; 166 u32 rsvd2;
167 u32 irsa; 167 u32 irsa;
168 u32 rsvd3; 168 u32 rsvd3;
169 u32 irja; 169 u32 irja;
170 #if defined(CONFIG_SYS_FSL_SEC_LE) && \ 170 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
171 !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ 171 !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
172 defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) 172 defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
173 u32 orba_l; 173 u32 orba_l;
174 u32 orba_h; 174 u32 orba_h;
175 #else 175 #else
176 u32 orba_h; 176 u32 orba_h;
177 u32 orba_l; 177 u32 orba_l;
178 #endif 178 #endif
179 u32 rsvd4; 179 u32 rsvd4;
180 u32 ors; 180 u32 ors;
181 u32 rsvd5; 181 u32 rsvd5;
182 u32 orjr; 182 u32 orjr;
183 u32 rsvd6; 183 u32 rsvd6;
184 u32 orsf; 184 u32 orsf;
185 u32 rsvd7; 185 u32 rsvd7;
186 u32 jrsta; 186 u32 jrsta;
187 u32 rsvd8; 187 u32 rsvd8;
188 u32 jrint; 188 u32 jrint;
189 u32 jrcfg0; 189 u32 jrcfg0;
190 u32 jrcfg1; 190 u32 jrcfg1;
191 u32 rsvd9; 191 u32 rsvd9;
192 u32 irri; 192 u32 irri;
193 u32 rsvd10; 193 u32 rsvd10;
194 u32 orwi; 194 u32 orwi;
195 u32 rsvd11; 195 u32 rsvd11;
196 u32 jrcr; 196 u32 jrcr;
197 }; 197 };
198 198
199 /* 199 /*
200 * Scatter Gather Entry - Specifies the the Scatter Gather Format 200 * Scatter Gather Entry - Specifies the the Scatter Gather Format
201 * related information 201 * related information
202 */ 202 */
203 struct sg_entry { 203 struct sg_entry {
204 #if defined(CONFIG_SYS_FSL_SEC_LE) && \ 204 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
205 !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ 205 !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
206 defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) 206 defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
207 uint32_t addr_lo; /* Memory Address - lo */ 207 uint32_t addr_lo; /* Memory Address - lo */
208 uint32_t addr_hi; /* Memory Address of start of buffer - hi */ 208 uint32_t addr_hi; /* Memory Address of start of buffer - hi */
209 #else 209 #else
210 uint32_t addr_hi; /* Memory Address of start of buffer - hi */ 210 uint32_t addr_hi; /* Memory Address of start of buffer - hi */
211 uint32_t addr_lo; /* Memory Address - lo */ 211 uint32_t addr_lo; /* Memory Address - lo */
212 #endif 212 #endif
213 213
214 uint32_t len_flag; /* Length of the data in the frame */ 214 uint32_t len_flag; /* Length of the data in the frame */
215 #define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF 215 #define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
216 #define SG_ENTRY_EXTENSION_BIT 0x80000000 216 #define SG_ENTRY_EXTENSION_BIT 0x80000000
217 #define SG_ENTRY_FINAL_BIT 0x40000000 217 #define SG_ENTRY_FINAL_BIT 0x40000000
218 uint32_t bpid_offset; 218 uint32_t bpid_offset;
219 #define SG_ENTRY_BPID_MASK 0x00FF0000 219 #define SG_ENTRY_BPID_MASK 0x00FF0000
220 #define SG_ENTRY_BPID_SHIFT 16 220 #define SG_ENTRY_BPID_SHIFT 16
221 #define SG_ENTRY_OFFSET_MASK 0x00001FFF 221 #define SG_ENTRY_OFFSET_MASK 0x00001FFF
222 #define SG_ENTRY_OFFSET_SHIFT 0 222 #define SG_ENTRY_OFFSET_SHIFT 0
223 }; 223 };
224 224
225 #define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */ 225 #define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */
226 226
227 #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ 227 #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
228 defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) 228 defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)
229 /* Job Ring Base Address */ 229 /* Job Ring Base Address */
230 #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1)) 230 #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
231 /* Secure Memory Offset varies accross versions */ 231 /* Secure Memory Offset varies accross versions */
232 #define SM_V1_OFFSET 0x0f4 232 #define SM_V1_OFFSET 0x0f4
233 #define SM_V2_OFFSET 0xa00 233 #define SM_V2_OFFSET 0xa00
234 /*Secure Memory Versioning */ 234 /*Secure Memory Versioning */
235 #define SMVID_V2 0x20105 235 #define SMVID_V2 0x20105
236 #define SM_VERSION(x) ({typeof(x) _x = x; \ 236 #define SM_VERSION(x) ({typeof(x) _x = x; \
237 _x < SMVID_V2 ? 1 : (_x < 0x20300 ? 2 : 3); }) 237 _x < SMVID_V2 ? 1 : (_x < 0x20300 ? 2 : 3); })
238 #define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET) 238 #define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET)
239 /* CAAM Job Ring 0 Registers */ 239 /* CAAM Job Ring 0 Registers */
240 /* Secure Memory Partition Owner register */ 240 /* Secure Memory Partition Owner register */
241 #define SMCSJR_PO (3 << 6) 241 #define SMCSJR_PO (3 << 6)
242 /* JR Allocation Error */ 242 /* JR Allocation Error */
243 #define SMCSJR_AERR (3 << 12) 243 #define SMCSJR_AERR (3 << 12)
244 /* Secure memory partition 0 page 0 owner register */ 244 /* Secure memory partition 0 page 0 owner register */
245 #define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC) 245 #define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
246 /* Secure memory command register */ 246 /* Secure memory command register */
247 #define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v)) 247 #define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
248 /* Secure memory command status register */ 248 /* Secure memory command status register */
249 #define CAAM_SMCSJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v)) 249 #define CAAM_SMCSJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v))
250 /* Secure memory access permissions register */ 250 /* Secure memory access permissions register */
251 #define CAAM_SMAPJR(v, jr, y) \ 251 #define CAAM_SMAPJR(v, jr, y) \
252 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16) 252 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16)
253 /* Secure memory access group 2 register */ 253 /* Secure memory access group 2 register */
254 #define CAAM_SMAG2JR(v, jr, y) \ 254 #define CAAM_SMAG2JR(v, jr, y) \
255 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16) 255 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16)
256 /* Secure memory access group 1 register */ 256 /* Secure memory access group 1 register */
257 #define CAAM_SMAG1JR(v, jr, y) \ 257 #define CAAM_SMAG1JR(v, jr, y) \
258 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16) 258 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16)
259 259
260 /* Commands and macros for secure memory */ 260 /* Commands and macros for secure memory */
261 #define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4) 261 #define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4)
262 #define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC) 262 #define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC)
263 #define SM_PERM(v) (v == 1 ? 0x10 : 0x4) 263 #define SM_PERM(v) (v == 1 ? 0x10 : 0x4)
264 #define SM_GROUP2(v) ({typeof(v) _v = v; \ 264 #define SM_GROUP2(v) ({typeof(v) _v = v; \
265 _v == 1 ? 0x14 : (_v == 2 ? 0x8 : 0xC); }) 265 _v == 1 ? 0x14 : (_v == 2 ? 0x8 : 0xC); })
266 #define SM_GROUP1(v) ({typeof(v) _v = v; \ 266 #define SM_GROUP1(v) ({typeof(v) _v = v; \
267 _v == 1 ? 0x18 : (_v == 2 ? 0xC : 0x8); }) 267 _v == 1 ? 0x18 : (_v == 2 ? 0xC : 0x8); })
268 #define CMD_PAGE_ALLOC 0x1 268 #define CMD_PAGE_ALLOC 0x1
269 #define CMD_PAGE_DEALLOC 0x2 269 #define CMD_PAGE_DEALLOC 0x2
270 #define CMD_PART_DEALLOC 0x3 270 #define CMD_PART_DEALLOC 0x3
271 #define CMD_INQUIRY 0x5 271 #define CMD_INQUIRY 0x5
272 #define CMD_COMPLETE (3 << 14) 272 #define CMD_COMPLETE (3 << 14)
273 #define PAGE_AVAILABLE 0 273 #define PAGE_AVAILABLE 0
274 #define PAGE_OWNED (3 << 6) 274 #define PAGE_OWNED (3 << 6)
275 #define PAGE(x) (x << 16) 275 #define PAGE(x) (x << 16)
276 #define PARTITION(x) (x << 8) 276 #define PARTITION(x) (x << 8)
277 #define PARTITION_OWNER(x) (0x3 << (x*2)) 277 #define PARTITION_OWNER(x) (0x3 << (x*2))
278 278
279 /* Address of secure 4kbyte pages */ 279 /* Address of secure 4kbyte pages */
280 #define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR 280 #define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR
281 #define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000) 281 #define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000)
282 #define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000) 282 #define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000)
283 #define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000) 283 #define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000)
284 284
285 #ifdef CONFIG_IMX8M 285 #ifdef CONFIG_IMX8M
286 #define JR_MID (1) /* Matches ATF configuration */ 286 #define JR_MID (1) /* Matches ATF configuration */
287 #define KS_G1 (0x10000 << JR_MID) /* CAAM only */ 287 #define KS_G1 (0x10000 << JR_MID) /* CAAM only */
288 #define PERM (0xB080) /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */ 288 #define PERM (0xB080) /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */
289 #else 289 #else
290 #define JR_MID (2) /* Matches ROM configuration */ 290 #define JR_MID (2) /* Matches ROM configuration */
291 #define KS_G1 BIT(JR_MID) /* CAAM only */ 291 #define KS_G1 BIT(JR_MID) /* CAAM only */
292 #define PERM (0xB008) /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */ 292 #define PERM (0xB008) /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */
293 #endif /* CONFIG_IMX8M */ 293 #endif /* CONFIG_IMX8M */
294 294
295 /* HAB WRAPPED KEY header */ 295 /* HAB WRAPPED KEY header */
296 #define WRP_HDR_SIZE 0x08 296 #define WRP_HDR_SIZE 0x08
297 #define HDR_TAG 0x81 297 #define HDR_TAG 0x81
298 #define HDR_PAR 0x41 298 #define HDR_PAR 0x41
299 /* HAB WRAPPED KEY Data */ 299 /* HAB WRAPPED KEY Data */
300 #define HAB_MOD 0x66 300 #define HAB_MOD 0x66
301 #define HAB_ALG 0x55 301 #define HAB_ALG 0x55
302 #define HAB_FLG 0x00 302 #define HAB_FLG 0x00
303 303
304 /* Partition and Page IDs */ 304 /* Partition and Page IDs */
305 #define PARTITION_1 1 305 #define PARTITION_1 1
306 #define PAGE_1 1 306 #define PAGE_1 1
307 307
308 #define ERROR_IN_PAGE_ALLOC 1 308 #define ERROR_IN_PAGE_ALLOC 1
309 #define ECONSTRJDESC -1 309 #define ECONSTRJDESC -1
310 310
311 #endif 311 #endif
312 312
313 #define FSL_CAAM_MP_PUBK_BYTES 64 313 #define FSL_CAAM_MP_PUBK_BYTES 64
314 #define FSL_CAAM_MP_PRVK_BYTES 32 314 #define FSL_CAAM_MP_PRVK_BYTES 32
315 #define FSL_CAAM_MP_MES_DGST_BYTES 32 315 #define FSL_CAAM_MP_MES_DGST_BYTES 32
316 316
317 #define FSL_CAAM_ORSR_JRa_OFFSET 0x102c 317 #define FSL_CAAM_ORSR_JRa_OFFSET 0x102c
318 #define FSL_CAAM_MAX_JR_SIZE 4 318 #define FSL_CAAM_MAX_JR_SIZE 4
319 319
320 /* blob_dek: 320 /* blob_dek:
321 * Encapsulates the src in a secure blob and stores it dst 321 * Encapsulates the src in a secure blob and stores it dst
322 * @src: reference to the plaintext 322 * @src: reference to the plaintext
323 * @dst: reference to the output adrress 323 * @dst: reference to the output adrress
324 * @len: size in bytes of src 324 * @len: size in bytes of src
325 * @return: 0 on success, error otherwise 325 * @return: 0 on success, error otherwise
326 */ 326 */
327 int blob_dek(const u8 *src, u8 *dst, u8 len); 327 int blob_dek(const u8 *src, u8 *dst, u8 len);
328 328
329 int gen_mppubk(u8 *dst); 329 int gen_mppubk(u8 *dst);
330 330
331 int sign_mppubk(const u8 *m, int data_size, u8 *dgst, u8 *c, u8 *d); 331 int sign_mppubk(const u8 *m, int data_size, u8 *dgst, u8 *c, u8 *d);
332 332
333 #if defined(CONFIG_ARCH_C29X) 333 #if defined(CONFIG_ARCH_C29X)
334 int sec_init_idx(uint8_t); 334 int sec_init_idx(uint8_t);
335 #endif 335 #endif
336 int sec_init(void); 336 int sec_init(void);
337 #endif 337 #endif
338 338
339 #endif /* __FSL_SEC_H */ 339 #endif /* __FSL_SEC_H */
340 340