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Commit 2434131a7be41b19c2b6ddaa10369274ba9ffcc6

Authored by Peng Fan
Committed by Stefano Babic
1 parent 66ec590c49
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

imx8mn: support get_cpu_rev 

Add a dummy cpu type and support get_cpu_rev for i.MX8MN

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Showing 4 changed files with 8 additions and 1 deletions Inline Diff

arch/arm/include/asm/arch-imx/cpu.h
Diff comments   View file @ 2434131
1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * (C) Copyright 2014 Freescale Semiconductor, Inc. 3 * (C) Copyright 2014 Freescale Semiconductor, Inc.
4 */ 4 */
5 5
6 #define MXC_CPU_MX23 0x23 6 #define MXC_CPU_MX23 0x23
7 #define MXC_CPU_MX25 0x25 7 #define MXC_CPU_MX25 0x25
8 #define MXC_CPU_MX27 0x27 8 #define MXC_CPU_MX27 0x27
9 #define MXC_CPU_MX28 0x28 9 #define MXC_CPU_MX28 0x28
10 #define MXC_CPU_MX31 0x31 10 #define MXC_CPU_MX31 0x31
11 #define MXC_CPU_MX35 0x35 11 #define MXC_CPU_MX35 0x35
12 #define MXC_CPU_MX51 0x51 12 #define MXC_CPU_MX51 0x51
13 #define MXC_CPU_MX53 0x53 13 #define MXC_CPU_MX53 0x53
14 #define MXC_CPU_MX6SL 0x60 14 #define MXC_CPU_MX6SL 0x60
15 #define MXC_CPU_MX6DL 0x61 15 #define MXC_CPU_MX6DL 0x61
16 #define MXC_CPU_MX6SX 0x62 16 #define MXC_CPU_MX6SX 0x62
17 #define MXC_CPU_MX6Q 0x63 17 #define MXC_CPU_MX6Q 0x63
18 #define MXC_CPU_MX6UL 0x64 18 #define MXC_CPU_MX6UL 0x64
19 #define MXC_CPU_MX6ULL 0x65 19 #define MXC_CPU_MX6ULL 0x65
20 #define MXC_CPU_MX6ULZ 0x6B 20 #define MXC_CPU_MX6ULZ 0x6B
21 #define MXC_CPU_MX6SOLO 0x66 /* dummy */ 21 #define MXC_CPU_MX6SOLO 0x66 /* dummy */
22 #define MXC_CPU_MX6SLL 0x67 22 #define MXC_CPU_MX6SLL 0x67
23 #define MXC_CPU_MX6D 0x6A 23 #define MXC_CPU_MX6D 0x6A
24 #define MXC_CPU_MX6DP 0x68 24 #define MXC_CPU_MX6DP 0x68
25 #define MXC_CPU_MX6QP 0x69 25 #define MXC_CPU_MX6QP 0x69
26 #define MXC_CPU_MX7S 0x71 /* dummy ID */ 26 #define MXC_CPU_MX7S 0x71 /* dummy ID */
27 #define MXC_CPU_MX7D 0x72 27 #define MXC_CPU_MX7D 0x72
28 #define MXC_CPU_IMX8MQ 0x82 28 #define MXC_CPU_IMX8MQ 0x82
29 #define MXC_CPU_IMX8MM 0x85 /* dummy ID */ 29 #define MXC_CPU_IMX8MM 0x85 /* dummy ID */
30 #define MXC_CPU_IMX8MML 0x86 /* dummy ID */ 30 #define MXC_CPU_IMX8MML 0x86 /* dummy ID */
31 #define MXC_CPU_IMX8MMD 0x87 /* dummy ID */ 31 #define MXC_CPU_IMX8MMD 0x87 /* dummy ID */
32 #define MXC_CPU_IMX8MMDL 0x88 /* dummy ID */ 32 #define MXC_CPU_IMX8MMDL 0x88 /* dummy ID */
33 #define MXC_CPU_IMX8MMS 0x89 /* dummy ID */ 33 #define MXC_CPU_IMX8MMS 0x89 /* dummy ID */
34 #define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */ 34 #define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */
35 #define MXC_CPU_IMX8MN 0x8b /* dummy ID */
35 #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ 36 #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
36 #define MXC_CPU_IMX8QM 0x91 /* dummy ID */ 37 #define MXC_CPU_IMX8QM 0x91 /* dummy ID */
37 #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ 38 #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
38 #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ 39 #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
39 #define MXC_CPU_VF610 0xF6 /* dummy ID */ 40 #define MXC_CPU_VF610 0xF6 /* dummy ID */
40 41
41 #define MXC_SOC_MX6 0x60 42 #define MXC_SOC_MX6 0x60
42 #define MXC_SOC_MX7 0x70 43 #define MXC_SOC_MX7 0x70
43 #define MXC_SOC_IMX8M 0x80 44 #define MXC_SOC_IMX8M 0x80
44 #define MXC_SOC_IMX8 0x90 /* dummy */ 45 #define MXC_SOC_IMX8 0x90 /* dummy */
45 #define MXC_SOC_MX7ULP 0xE0 /* dummy */ 46 #define MXC_SOC_MX7ULP 0xE0 /* dummy */
46 47
47 #define CHIP_REV_1_0 0x10 48 #define CHIP_REV_1_0 0x10
48 #define CHIP_REV_1_1 0x11 49 #define CHIP_REV_1_1 0x11
49 #define CHIP_REV_1_2 0x12 50 #define CHIP_REV_1_2 0x12
50 #define CHIP_REV_1_5 0x15 51 #define CHIP_REV_1_5 0x15
51 #define CHIP_REV_2_0 0x20 52 #define CHIP_REV_2_0 0x20
52 #define CHIP_REV_2_1 0x21 53 #define CHIP_REV_2_1 0x21
53 #define CHIP_REV_2_5 0x25 54 #define CHIP_REV_2_5 0x25
54 #define CHIP_REV_3_0 0x30 55 #define CHIP_REV_3_0 0x30
55 56
56 #define CHIP_REV_A 0x0 57 #define CHIP_REV_A 0x0
57 #define CHIP_REV_B 0x1 58 #define CHIP_REV_B 0x1
58 59
59 #define BOARD_REV_1_0 0x0 60 #define BOARD_REV_1_0 0x0
60 #define BOARD_REV_2_0 0x1 61 #define BOARD_REV_2_0 0x1
61 #define BOARD_VER_OFFSET 0x8 62 #define BOARD_VER_OFFSET 0x8
62 63
63 #define CS0_128 0 64 #define CS0_128 0
64 #define CS0_64M_CS1_64M 1 65 #define CS0_64M_CS1_64M 1
65 #define CS0_64M_CS1_32M_CS2_32M 2 66 #define CS0_64M_CS1_32M_CS2_32M 2
66 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 67 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
67 68
68 u32 get_imx_reset_cause(void); 69 u32 get_imx_reset_cause(void);
69 ulong get_systemPLLCLK(void); 70 ulong get_systemPLLCLK(void);
70 ulong get_FCLK(void); 71 ulong get_FCLK(void);
71 ulong get_HCLK(void); 72 ulong get_HCLK(void);
72 ulong get_BCLK(void); 73 ulong get_BCLK(void);
73 ulong get_PERCLK1(void); 74 ulong get_PERCLK1(void);
74 ulong get_PERCLK2(void); 75 ulong get_PERCLK2(void);
75 ulong get_PERCLK3(void); 76 ulong get_PERCLK3(void);
76 77
arch/arm/include/asm/mach-imx/sys_proto.h
Diff comments   View file @ 2434131
1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * (C) Copyright 2009 3 * (C) Copyright 2009
4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 */ 5 */
6 6
7 #ifndef _SYS_PROTO_H_ 7 #ifndef _SYS_PROTO_H_
8 #define _SYS_PROTO_H_ 8 #define _SYS_PROTO_H_
9 9
10 #include <asm/io.h> 10 #include <asm/io.h>
11 #include <asm/mach-imx/regs-common.h> 11 #include <asm/mach-imx/regs-common.h>
12 #include <common.h> 12 #include <common.h>
13 #include "../arch-imx/cpu.h" 13 #include "../arch-imx/cpu.h"
14 14
15 #define soc_rev() (get_cpu_rev() & 0xFF) 15 #define soc_rev() (get_cpu_rev() & 0xFF)
16 #define is_soc_rev(rev) (soc_rev() == rev) 16 #define is_soc_rev(rev) (soc_rev() == rev)
17 17
18 /* returns MXC_CPU_ value */ 18 /* returns MXC_CPU_ value */
19 #define cpu_type(rev) (((rev) >> 12) & 0xff) 19 #define cpu_type(rev) (((rev) >> 12) & 0xff)
20 #define soc_type(rev) (((rev) >> 12) & 0xf0) 20 #define soc_type(rev) (((rev) >> 12) & 0xf0)
21 /* both macros return/take MXC_CPU_ constants */ 21 /* both macros return/take MXC_CPU_ constants */
22 #define get_cpu_type() (cpu_type(get_cpu_rev())) 22 #define get_cpu_type() (cpu_type(get_cpu_rev()))
23 #define get_soc_type() (soc_type(get_cpu_rev())) 23 #define get_soc_type() (soc_type(get_cpu_rev()))
24 #define is_cpu_type(cpu) (get_cpu_type() == cpu) 24 #define is_cpu_type(cpu) (get_cpu_type() == cpu)
25 #define is_soc_type(soc) (get_soc_type() == soc) 25 #define is_soc_type(soc) (get_soc_type() == soc)
26 26
27 #define is_mx6() (is_soc_type(MXC_SOC_MX6)) 27 #define is_mx6() (is_soc_type(MXC_SOC_MX6))
28 #define is_mx7() (is_soc_type(MXC_SOC_MX7)) 28 #define is_mx7() (is_soc_type(MXC_SOC_MX7))
29 #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) 29 #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
30 #define is_imx8() (is_soc_type(MXC_SOC_IMX8)) 30 #define is_imx8() (is_soc_type(MXC_SOC_IMX8))
31 31
32 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) 32 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
33 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) 33 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
34 #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL)) 34 #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
35 #define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL)) 35 #define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
36 #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX)) 36 #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
37 #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL)) 37 #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
38 #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO)) 38 #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
39 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL)) 39 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
40 #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL)) 40 #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
41 #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ)) 41 #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ))
42 #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) 42 #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
43 43
44 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) 44 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
45 45
46 #define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ)) 46 #define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ))
47 #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM)) 47 #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM))
48 #define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\ 48 #define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\
49 is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \ 49 is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \
50 is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL)) 50 is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL))
51 #define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML)) 51 #define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML))
52 #define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD)) 52 #define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD))
53 #define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL)) 53 #define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL))
54 #define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS)) 54 #define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS))
55 #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL)) 55 #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
56 #define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN))
57
56 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) 58 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
57 59
58 #ifdef CONFIG_MX6 60 #ifdef CONFIG_MX6
59 #define IMX6_SRC_GPR10_BMODE BIT(28) 61 #define IMX6_SRC_GPR10_BMODE BIT(28)
60 62
61 #define IMX6_BMODE_MASK GENMASK(7, 0) 63 #define IMX6_BMODE_MASK GENMASK(7, 0)
62 #define IMX6_BMODE_SHIFT 4 64 #define IMX6_BMODE_SHIFT 4
63 #define IMX6_BMODE_EMI_MASK BIT(3) 65 #define IMX6_BMODE_EMI_MASK BIT(3)
64 #define IMX6_BMODE_EMI_SHIFT 3 66 #define IMX6_BMODE_EMI_SHIFT 3
65 #define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24) 67 #define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24)
66 #define IMX6_BMODE_SERIAL_ROM_SHIFT 24 68 #define IMX6_BMODE_SERIAL_ROM_SHIFT 24
67 69
68 enum imx6_bmode_serial_rom { 70 enum imx6_bmode_serial_rom {
69 IMX6_BMODE_ECSPI1, 71 IMX6_BMODE_ECSPI1,
70 IMX6_BMODE_ECSPI2, 72 IMX6_BMODE_ECSPI2,
71 IMX6_BMODE_ECSPI3, 73 IMX6_BMODE_ECSPI3,
72 IMX6_BMODE_ECSPI4, 74 IMX6_BMODE_ECSPI4,
73 IMX6_BMODE_ECSPI5, 75 IMX6_BMODE_ECSPI5,
74 IMX6_BMODE_I2C1, 76 IMX6_BMODE_I2C1,
75 IMX6_BMODE_I2C2, 77 IMX6_BMODE_I2C2,
76 IMX6_BMODE_I2C3, 78 IMX6_BMODE_I2C3,
77 }; 79 };
78 80
79 enum imx6_bmode_emi { 81 enum imx6_bmode_emi {
80 IMX6_BMODE_NOR, 82 IMX6_BMODE_NOR,
81 IMX6_BMODE_ONENAND, 83 IMX6_BMODE_ONENAND,
82 }; 84 };
83 85
84 enum imx6_bmode { 86 enum imx6_bmode {
85 IMX6_BMODE_EMI, 87 IMX6_BMODE_EMI,
86 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) 88 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
87 IMX6_BMODE_QSPI, 89 IMX6_BMODE_QSPI,
88 IMX6_BMODE_RESERVED, 90 IMX6_BMODE_RESERVED,
89 #else 91 #else
90 IMX6_BMODE_RESERVED, 92 IMX6_BMODE_RESERVED,
91 IMX6_BMODE_SATA, 93 IMX6_BMODE_SATA,
92 #endif 94 #endif
93 IMX6_BMODE_SERIAL_ROM, 95 IMX6_BMODE_SERIAL_ROM,
94 IMX6_BMODE_SD, 96 IMX6_BMODE_SD,
95 IMX6_BMODE_ESD, 97 IMX6_BMODE_ESD,
96 IMX6_BMODE_MMC, 98 IMX6_BMODE_MMC,
97 IMX6_BMODE_EMMC, 99 IMX6_BMODE_EMMC,
98 IMX6_BMODE_NAND_MIN, 100 IMX6_BMODE_NAND_MIN,
99 IMX6_BMODE_NAND_MAX = 0xf, 101 IMX6_BMODE_NAND_MAX = 0xf,
100 }; 102 };
101 103
102 u32 imx6_src_get_boot_mode(void); 104 u32 imx6_src_get_boot_mode(void);
103 void gpr_init(void); 105 void gpr_init(void);
104 106
105 #endif /* CONFIG_MX6 */ 107 #endif /* CONFIG_MX6 */
106 108
107 u32 get_nr_cpus(void); 109 u32 get_nr_cpus(void);
108 u32 get_cpu_rev(void); 110 u32 get_cpu_rev(void);
109 u32 get_cpu_speed_grade_hz(void); 111 u32 get_cpu_speed_grade_hz(void);
110 u32 get_cpu_temp_grade(int *minc, int *maxc); 112 u32 get_cpu_temp_grade(int *minc, int *maxc);
111 const char *get_imx_type(u32 imxtype); 113 const char *get_imx_type(u32 imxtype);
112 u32 imx_ddr_size(void); 114 u32 imx_ddr_size(void);
113 void sdelay(unsigned long); 115 void sdelay(unsigned long);
114 void set_chipselect_size(int const); 116 void set_chipselect_size(int const);
115 117
116 void init_aips(void); 118 void init_aips(void);
117 void init_src(void); 119 void init_src(void);
118 void init_snvs(void); 120 void init_snvs(void);
119 void imx_wdog_disable_powerdown(void); 121 void imx_wdog_disable_powerdown(void);
120 122
121 int board_mmc_get_env_dev(int devno); 123 int board_mmc_get_env_dev(int devno);
122 124
123 int nxp_board_rev(void); 125 int nxp_board_rev(void);
124 char nxp_board_rev_string(void); 126 char nxp_board_rev_string(void);
125 127
126 /* 128 /*
127 * Initializes on-chip ethernet controllers. 129 * Initializes on-chip ethernet controllers.
128 * to override, implement board_eth_init() 130 * to override, implement board_eth_init()
129 */ 131 */
130 int fecmxc_initialize(bd_t *bis); 132 int fecmxc_initialize(bd_t *bis);
131 u32 get_ahb_clk(void); 133 u32 get_ahb_clk(void);
132 u32 get_periph_clk(void); 134 u32 get_periph_clk(void);
133 135
134 void lcdif_power_down(void); 136 void lcdif_power_down(void);
135 137
136 int mxs_reset_block(struct mxs_register_32 *reg); 138 int mxs_reset_block(struct mxs_register_32 *reg);
137 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout); 139 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
138 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout); 140 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
139 141
140 unsigned long call_imx_sip(unsigned long id, unsigned long reg0, 142 unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
141 unsigned long reg1, unsigned long reg2, 143 unsigned long reg1, unsigned long reg2,
142 unsigned long reg3); 144 unsigned long reg3);
143 unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0, 145 unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
144 unsigned long *reg1, unsigned long reg2, 146 unsigned long *reg1, unsigned long reg2,
145 unsigned long reg3); 147 unsigned long reg3);
146 #endif 148 #endif
147 149
arch/arm/mach-imx/cpu.c
Diff comments   View file @ 2434131
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * (C) Copyright 2007 3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix 4 * Sascha Hauer, Pengutronix
5 * 5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc. 6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 */ 7 */
8 8
9 #include <bootm.h> 9 #include <bootm.h>
10 #include <common.h> 10 #include <common.h>
11 #include <netdev.h> 11 #include <netdev.h>
12 #include <linux/errno.h> 12 #include <linux/errno.h>
13 #include <asm/io.h> 13 #include <asm/io.h>
14 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h> 15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h> 16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/crm_regs.h> 17 #include <asm/arch/crm_regs.h>
18 #include <asm/mach-imx/boot_mode.h> 18 #include <asm/mach-imx/boot_mode.h>
19 #include <imx_thermal.h> 19 #include <imx_thermal.h>
20 #include <ipu_pixfmt.h> 20 #include <ipu_pixfmt.h>
21 #include <thermal.h> 21 #include <thermal.h>
22 #include <sata.h> 22 #include <sata.h>
23 23
24 #ifdef CONFIG_FSL_ESDHC_IMX 24 #ifdef CONFIG_FSL_ESDHC_IMX
25 #include <fsl_esdhc_imx.h> 25 #include <fsl_esdhc_imx.h>
26 #endif 26 #endif
27 27
28 static u32 reset_cause = -1; 28 static u32 reset_cause = -1;
29 29
30 u32 get_imx_reset_cause(void) 30 u32 get_imx_reset_cause(void)
31 { 31 {
32 struct src *src_regs = (struct src *)SRC_BASE_ADDR; 32 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
33 33
34 if (reset_cause == -1) { 34 if (reset_cause == -1) {
35 reset_cause = readl(&src_regs->srsr); 35 reset_cause = readl(&src_regs->srsr);
36 /* preserve the value for U-Boot proper */ 36 /* preserve the value for U-Boot proper */
37 #if !defined(CONFIG_SPL_BUILD) 37 #if !defined(CONFIG_SPL_BUILD)
38 writel(reset_cause, &src_regs->srsr); 38 writel(reset_cause, &src_regs->srsr);
39 #endif 39 #endif
40 } 40 }
41 41
42 return reset_cause; 42 return reset_cause;
43 } 43 }
44 44
45 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) 45 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
46 static char *get_reset_cause(void) 46 static char *get_reset_cause(void)
47 { 47 {
48 switch (get_imx_reset_cause()) { 48 switch (get_imx_reset_cause()) {
49 case 0x00001: 49 case 0x00001:
50 case 0x00011: 50 case 0x00011:
51 return "POR"; 51 return "POR";
52 case 0x00004: 52 case 0x00004:
53 return "CSU"; 53 return "CSU";
54 case 0x00008: 54 case 0x00008:
55 return "IPP USER"; 55 return "IPP USER";
56 case 0x00010: 56 case 0x00010:
57 #ifdef CONFIG_MX7 57 #ifdef CONFIG_MX7
58 return "WDOG1"; 58 return "WDOG1";
59 #else 59 #else
60 return "WDOG"; 60 return "WDOG";
61 #endif 61 #endif
62 case 0x00020: 62 case 0x00020:
63 return "JTAG HIGH-Z"; 63 return "JTAG HIGH-Z";
64 case 0x00040: 64 case 0x00040:
65 return "JTAG SW"; 65 return "JTAG SW";
66 case 0x00080: 66 case 0x00080:
67 return "WDOG3"; 67 return "WDOG3";
68 #ifdef CONFIG_MX7 68 #ifdef CONFIG_MX7
69 case 0x00100: 69 case 0x00100:
70 return "WDOG4"; 70 return "WDOG4";
71 case 0x00200: 71 case 0x00200:
72 return "TEMPSENSE"; 72 return "TEMPSENSE";
73 #elif defined(CONFIG_IMX8M) 73 #elif defined(CONFIG_IMX8M)
74 case 0x00100: 74 case 0x00100:
75 return "WDOG2"; 75 return "WDOG2";
76 case 0x00200: 76 case 0x00200:
77 return "TEMPSENSE"; 77 return "TEMPSENSE";
78 #else 78 #else
79 case 0x00100: 79 case 0x00100:
80 return "TEMPSENSE"; 80 return "TEMPSENSE";
81 case 0x10000: 81 case 0x10000:
82 return "WARM BOOT"; 82 return "WARM BOOT";
83 #endif 83 #endif
84 default: 84 default:
85 return "unknown reset"; 85 return "unknown reset";
86 } 86 }
87 } 87 }
88 #endif 88 #endif
89 89
90 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) 90 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
91 91
92 const char *get_imx_type(u32 imxtype) 92 const char *get_imx_type(u32 imxtype)
93 { 93 {
94 switch (imxtype) { 94 switch (imxtype) {
95 case MXC_CPU_IMX8MN:
96 return "8MNano";/* Quad-core version of the imx8mn */
95 case MXC_CPU_IMX8MM: 97 case MXC_CPU_IMX8MM:
96 return "8MMQ"; /* Quad-core version of the imx8mm */ 98 return "8MMQ"; /* Quad-core version of the imx8mm */
97 case MXC_CPU_IMX8MML: 99 case MXC_CPU_IMX8MML:
98 return "8MMQL"; /* Quad-core Lite version of the imx8mm */ 100 return "8MMQL"; /* Quad-core Lite version of the imx8mm */
99 case MXC_CPU_IMX8MMD: 101 case MXC_CPU_IMX8MMD:
100 return "8MMD"; /* Dual-core version of the imx8mm */ 102 return "8MMD"; /* Dual-core version of the imx8mm */
101 case MXC_CPU_IMX8MMDL: 103 case MXC_CPU_IMX8MMDL:
102 return "8MMDL"; /* Dual-core Lite version of the imx8mm */ 104 return "8MMDL"; /* Dual-core Lite version of the imx8mm */
103 case MXC_CPU_IMX8MMS: 105 case MXC_CPU_IMX8MMS:
104 return "8MMS"; /* Single-core version of the imx8mm */ 106 return "8MMS"; /* Single-core version of the imx8mm */
105 case MXC_CPU_IMX8MMSL: 107 case MXC_CPU_IMX8MMSL:
106 return "8MMSL"; /* Single-core Lite version of the imx8mm */ 108 return "8MMSL"; /* Single-core Lite version of the imx8mm */
107 case MXC_CPU_IMX8MQ: 109 case MXC_CPU_IMX8MQ:
108 return "8MQ"; /* Quad-core version of the imx8m */ 110 return "8MQ"; /* Quad-core version of the imx8m */
109 case MXC_CPU_MX7S: 111 case MXC_CPU_MX7S:
110 return "7S"; /* Single-core version of the mx7 */ 112 return "7S"; /* Single-core version of the mx7 */
111 case MXC_CPU_MX7D: 113 case MXC_CPU_MX7D:
112 return "7D"; /* Dual-core version of the mx7 */ 114 return "7D"; /* Dual-core version of the mx7 */
113 case MXC_CPU_MX6QP: 115 case MXC_CPU_MX6QP:
114 return "6QP"; /* Quad-Plus version of the mx6 */ 116 return "6QP"; /* Quad-Plus version of the mx6 */
115 case MXC_CPU_MX6DP: 117 case MXC_CPU_MX6DP:
116 return "6DP"; /* Dual-Plus version of the mx6 */ 118 return "6DP"; /* Dual-Plus version of the mx6 */
117 case MXC_CPU_MX6Q: 119 case MXC_CPU_MX6Q:
118 return "6Q"; /* Quad-core version of the mx6 */ 120 return "6Q"; /* Quad-core version of the mx6 */
119 case MXC_CPU_MX6D: 121 case MXC_CPU_MX6D:
120 return "6D"; /* Dual-core version of the mx6 */ 122 return "6D"; /* Dual-core version of the mx6 */
121 case MXC_CPU_MX6DL: 123 case MXC_CPU_MX6DL:
122 return "6DL"; /* Dual Lite version of the mx6 */ 124 return "6DL"; /* Dual Lite version of the mx6 */
123 case MXC_CPU_MX6SOLO: 125 case MXC_CPU_MX6SOLO:
124 return "6SOLO"; /* Solo version of the mx6 */ 126 return "6SOLO"; /* Solo version of the mx6 */
125 case MXC_CPU_MX6SL: 127 case MXC_CPU_MX6SL:
126 return "6SL"; /* Solo-Lite version of the mx6 */ 128 return "6SL"; /* Solo-Lite version of the mx6 */
127 case MXC_CPU_MX6SLL: 129 case MXC_CPU_MX6SLL:
128 return "6SLL"; /* SLL version of the mx6 */ 130 return "6SLL"; /* SLL version of the mx6 */
129 case MXC_CPU_MX6SX: 131 case MXC_CPU_MX6SX:
130 return "6SX"; /* SoloX version of the mx6 */ 132 return "6SX"; /* SoloX version of the mx6 */
131 case MXC_CPU_MX6UL: 133 case MXC_CPU_MX6UL:
132 return "6UL"; /* Ultra-Lite version of the mx6 */ 134 return "6UL"; /* Ultra-Lite version of the mx6 */
133 case MXC_CPU_MX6ULL: 135 case MXC_CPU_MX6ULL:
134 return "6ULL"; /* ULL version of the mx6 */ 136 return "6ULL"; /* ULL version of the mx6 */
135 case MXC_CPU_MX6ULZ: 137 case MXC_CPU_MX6ULZ:
136 return "6ULZ"; /* ULZ version of the mx6 */ 138 return "6ULZ"; /* ULZ version of the mx6 */
137 case MXC_CPU_MX51: 139 case MXC_CPU_MX51:
138 return "51"; 140 return "51";
139 case MXC_CPU_MX53: 141 case MXC_CPU_MX53:
140 return "53"; 142 return "53";
141 default: 143 default:
142 return "??"; 144 return "??";
143 } 145 }
144 } 146 }
145 147
146 int print_cpuinfo(void) 148 int print_cpuinfo(void)
147 { 149 {
148 u32 cpurev; 150 u32 cpurev;
149 __maybe_unused u32 max_freq; 151 __maybe_unused u32 max_freq;
150 152
151 cpurev = get_cpu_rev(); 153 cpurev = get_cpu_rev();
152 154
153 #if defined(CONFIG_IMX_THERMAL) 155 #if defined(CONFIG_IMX_THERMAL)
154 struct udevice *thermal_dev; 156 struct udevice *thermal_dev;
155 int cpu_tmp, minc, maxc, ret; 157 int cpu_tmp, minc, maxc, ret;
156 158
157 printf("CPU: Freescale i.MX%s rev%d.%d", 159 printf("CPU: Freescale i.MX%s rev%d.%d",
158 get_imx_type((cpurev & 0xFF000) >> 12), 160 get_imx_type((cpurev & 0xFF000) >> 12),
159 (cpurev & 0x000F0) >> 4, 161 (cpurev & 0x000F0) >> 4,
160 (cpurev & 0x0000F) >> 0); 162 (cpurev & 0x0000F) >> 0);
161 max_freq = get_cpu_speed_grade_hz(); 163 max_freq = get_cpu_speed_grade_hz();
162 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) { 164 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
163 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); 165 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
164 } else { 166 } else {
165 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000, 167 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
166 mxc_get_clock(MXC_ARM_CLK) / 1000000); 168 mxc_get_clock(MXC_ARM_CLK) / 1000000);
167 } 169 }
168 #else 170 #else
169 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", 171 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
170 get_imx_type((cpurev & 0xFF000) >> 12), 172 get_imx_type((cpurev & 0xFF000) >> 12),
171 (cpurev & 0x000F0) >> 4, 173 (cpurev & 0x000F0) >> 4,
172 (cpurev & 0x0000F) >> 0, 174 (cpurev & 0x0000F) >> 0,
173 mxc_get_clock(MXC_ARM_CLK) / 1000000); 175 mxc_get_clock(MXC_ARM_CLK) / 1000000);
174 #endif 176 #endif
175 177
176 #if defined(CONFIG_IMX_THERMAL) 178 #if defined(CONFIG_IMX_THERMAL)
177 puts("CPU: "); 179 puts("CPU: ");
178 switch (get_cpu_temp_grade(&minc, &maxc)) { 180 switch (get_cpu_temp_grade(&minc, &maxc)) {
179 case TEMP_AUTOMOTIVE: 181 case TEMP_AUTOMOTIVE:
180 puts("Automotive temperature grade "); 182 puts("Automotive temperature grade ");
181 break; 183 break;
182 case TEMP_INDUSTRIAL: 184 case TEMP_INDUSTRIAL:
183 puts("Industrial temperature grade "); 185 puts("Industrial temperature grade ");
184 break; 186 break;
185 case TEMP_EXTCOMMERCIAL: 187 case TEMP_EXTCOMMERCIAL:
186 puts("Extended Commercial temperature grade "); 188 puts("Extended Commercial temperature grade ");
187 break; 189 break;
188 default: 190 default:
189 puts("Commercial temperature grade "); 191 puts("Commercial temperature grade ");
190 break; 192 break;
191 } 193 }
192 printf("(%dC to %dC)", minc, maxc); 194 printf("(%dC to %dC)", minc, maxc);
193 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev); 195 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
194 if (!ret) { 196 if (!ret) {
195 ret = thermal_get_temp(thermal_dev, &cpu_tmp); 197 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
196 198
197 if (!ret) 199 if (!ret)
198 printf(" at %dC\n", cpu_tmp); 200 printf(" at %dC\n", cpu_tmp);
199 else 201 else
200 debug(" - invalid sensor data\n"); 202 debug(" - invalid sensor data\n");
201 } else { 203 } else {
202 debug(" - invalid sensor device\n"); 204 debug(" - invalid sensor device\n");
203 } 205 }
204 #endif 206 #endif
205 207
206 printf("Reset cause: %s\n", get_reset_cause()); 208 printf("Reset cause: %s\n", get_reset_cause());
207 return 0; 209 return 0;
208 } 210 }
209 #endif 211 #endif
210 212
211 int cpu_eth_init(bd_t *bis) 213 int cpu_eth_init(bd_t *bis)
212 { 214 {
213 int rc = -ENODEV; 215 int rc = -ENODEV;
214 216
215 #if defined(CONFIG_FEC_MXC) 217 #if defined(CONFIG_FEC_MXC)
216 rc = fecmxc_initialize(bis); 218 rc = fecmxc_initialize(bis);
217 #endif 219 #endif
218 220
219 return rc; 221 return rc;
220 } 222 }
221 223
222 #ifdef CONFIG_FSL_ESDHC_IMX 224 #ifdef CONFIG_FSL_ESDHC_IMX
223 /* 225 /*
224 * Initializes on-chip MMC controllers. 226 * Initializes on-chip MMC controllers.
225 * to override, implement board_mmc_init() 227 * to override, implement board_mmc_init()
226 */ 228 */
227 int cpu_mmc_init(bd_t *bis) 229 int cpu_mmc_init(bd_t *bis)
228 { 230 {
229 return fsl_esdhc_mmc_init(bis); 231 return fsl_esdhc_mmc_init(bis);
230 } 232 }
231 #endif 233 #endif
232 234
233 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) 235 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
234 u32 get_ahb_clk(void) 236 u32 get_ahb_clk(void)
235 { 237 {
236 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 238 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
237 u32 reg, ahb_podf; 239 u32 reg, ahb_podf;
238 240
239 reg = __raw_readl(&imx_ccm->cbcdr); 241 reg = __raw_readl(&imx_ccm->cbcdr);
240 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK; 242 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
241 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET; 243 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
242 244
243 return get_periph_clk() / (ahb_podf + 1); 245 return get_periph_clk() / (ahb_podf + 1);
244 } 246 }
245 #endif 247 #endif
246 248
247 void arch_preboot_os(void) 249 void arch_preboot_os(void)
248 { 250 {
249 #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI) 251 #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
250 imx_pcie_remove(); 252 imx_pcie_remove();
251 #endif 253 #endif
252 #if defined(CONFIG_SATA) 254 #if defined(CONFIG_SATA)
253 if (!is_mx6sdl()) { 255 if (!is_mx6sdl()) {
254 sata_remove(0); 256 sata_remove(0);
255 #if defined(CONFIG_MX6) 257 #if defined(CONFIG_MX6)
256 disable_sata_clock(); 258 disable_sata_clock();
257 #endif 259 #endif
258 } 260 }
259 #endif 261 #endif
260 #if defined(CONFIG_VIDEO_IPUV3) 262 #if defined(CONFIG_VIDEO_IPUV3)
261 /* disable video before launching O/S */ 263 /* disable video before launching O/S */
262 ipuv3_fb_shutdown(); 264 ipuv3_fb_shutdown();
263 #endif 265 #endif
264 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO) 266 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
265 lcdif_power_down(); 267 lcdif_power_down();
266 #endif 268 #endif
267 } 269 }
268 270
269 #ifndef CONFIG_IMX8M 271 #ifndef CONFIG_IMX8M
270 void set_chipselect_size(int const cs_size) 272 void set_chipselect_size(int const cs_size)
271 { 273 {
272 unsigned int reg; 274 unsigned int reg;
273 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 275 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
274 reg = readl(&iomuxc_regs->gpr[1]); 276 reg = readl(&iomuxc_regs->gpr[1]);
275 277
276 switch (cs_size) { 278 switch (cs_size) {
277 case CS0_128: 279 case CS0_128:
278 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */ 280 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
279 reg |= 0x5; 281 reg |= 0x5;
280 break; 282 break;
281 case CS0_64M_CS1_64M: 283 case CS0_64M_CS1_64M:
282 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */ 284 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
283 reg |= 0x1B; 285 reg |= 0x1B;
284 break; 286 break;
285 case CS0_64M_CS1_32M_CS2_32M: 287 case CS0_64M_CS1_32M_CS2_32M:
286 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */ 288 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
287 reg |= 0x4B; 289 reg |= 0x4B;
288 break; 290 break;
289 case CS0_32M_CS1_32M_CS2_32M_CS3_32M: 291 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
290 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */ 292 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
291 reg |= 0x249; 293 reg |= 0x249;
292 break; 294 break;
293 default: 295 default:
294 printf("Unknown chip select size: %d\n", cs_size); 296 printf("Unknown chip select size: %d\n", cs_size);
295 break; 297 break;
296 } 298 }
297 299
298 writel(reg, &iomuxc_regs->gpr[1]); 300 writel(reg, &iomuxc_regs->gpr[1]);
299 } 301 }
300 #endif 302 #endif
301 303
302 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) 304 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
303 /* 305 /*
304 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440) 306 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
305 * defines a 2-bit SPEED_GRADING 307 * defines a 2-bit SPEED_GRADING
306 */ 308 */
307 #define OCOTP_TESTER3_SPEED_SHIFT 8 309 #define OCOTP_TESTER3_SPEED_SHIFT 8
308 enum cpu_speed { 310 enum cpu_speed {
309 OCOTP_TESTER3_SPEED_GRADE0, 311 OCOTP_TESTER3_SPEED_GRADE0,
310 OCOTP_TESTER3_SPEED_GRADE1, 312 OCOTP_TESTER3_SPEED_GRADE1,
311 OCOTP_TESTER3_SPEED_GRADE2, 313 OCOTP_TESTER3_SPEED_GRADE2,
312 OCOTP_TESTER3_SPEED_GRADE3, 314 OCOTP_TESTER3_SPEED_GRADE3,
313 }; 315 };
314 316
315 u32 get_cpu_speed_grade_hz(void) 317 u32 get_cpu_speed_grade_hz(void)
316 { 318 {
317 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 319 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
318 struct fuse_bank *bank = &ocotp->bank[1]; 320 struct fuse_bank *bank = &ocotp->bank[1];
319 struct fuse_bank1_regs *fuse = 321 struct fuse_bank1_regs *fuse =
320 (struct fuse_bank1_regs *)bank->fuse_regs; 322 (struct fuse_bank1_regs *)bank->fuse_regs;
321 uint32_t val; 323 uint32_t val;
322 324
323 val = readl(&fuse->tester3); 325 val = readl(&fuse->tester3);
324 val >>= OCOTP_TESTER3_SPEED_SHIFT; 326 val >>= OCOTP_TESTER3_SPEED_SHIFT;
325 val &= 0x3; 327 val &= 0x3;
326 328
327 switch(val) { 329 switch(val) {
328 case OCOTP_TESTER3_SPEED_GRADE0: 330 case OCOTP_TESTER3_SPEED_GRADE0:
329 return 800000000; 331 return 800000000;
330 case OCOTP_TESTER3_SPEED_GRADE1: 332 case OCOTP_TESTER3_SPEED_GRADE1:
331 return is_mx7() ? 500000000 : 1000000000; 333 return is_mx7() ? 500000000 : 1000000000;
332 case OCOTP_TESTER3_SPEED_GRADE2: 334 case OCOTP_TESTER3_SPEED_GRADE2:
333 return is_mx7() ? 1000000000 : 1300000000; 335 return is_mx7() ? 1000000000 : 1300000000;
334 case OCOTP_TESTER3_SPEED_GRADE3: 336 case OCOTP_TESTER3_SPEED_GRADE3:
335 return is_mx7() ? 1200000000 : 1500000000; 337 return is_mx7() ? 1200000000 : 1500000000;
336 } 338 }
337 339
338 return 0; 340 return 0;
339 } 341 }
340 342
341 /* 343 /*
342 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440) 344 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
343 * defines a 2-bit SPEED_GRADING 345 * defines a 2-bit SPEED_GRADING
344 */ 346 */
345 #define OCOTP_TESTER3_TEMP_SHIFT 6 347 #define OCOTP_TESTER3_TEMP_SHIFT 6
346 348
347 u32 get_cpu_temp_grade(int *minc, int *maxc) 349 u32 get_cpu_temp_grade(int *minc, int *maxc)
348 { 350 {
349 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 351 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
350 struct fuse_bank *bank = &ocotp->bank[1]; 352 struct fuse_bank *bank = &ocotp->bank[1];
351 struct fuse_bank1_regs *fuse = 353 struct fuse_bank1_regs *fuse =
352 (struct fuse_bank1_regs *)bank->fuse_regs; 354 (struct fuse_bank1_regs *)bank->fuse_regs;
353 uint32_t val; 355 uint32_t val;
354 356
355 val = readl(&fuse->tester3); 357 val = readl(&fuse->tester3);
356 val >>= OCOTP_TESTER3_TEMP_SHIFT; 358 val >>= OCOTP_TESTER3_TEMP_SHIFT;
357 val &= 0x3; 359 val &= 0x3;
358 360
359 if (minc && maxc) { 361 if (minc && maxc) {
360 if (val == TEMP_AUTOMOTIVE) { 362 if (val == TEMP_AUTOMOTIVE) {
361 *minc = -40; 363 *minc = -40;
362 *maxc = 125; 364 *maxc = 125;
363 } else if (val == TEMP_INDUSTRIAL) { 365 } else if (val == TEMP_INDUSTRIAL) {
364 *minc = -40; 366 *minc = -40;
365 *maxc = 105; 367 *maxc = 105;
366 } else if (val == TEMP_EXTCOMMERCIAL) { 368 } else if (val == TEMP_EXTCOMMERCIAL) {
367 *minc = -20; 369 *minc = -20;
368 *maxc = 105; 370 *maxc = 105;
369 } else { 371 } else {
370 *minc = 0; 372 *minc = 0;
371 *maxc = 95; 373 *maxc = 95;
372 } 374 }
373 } 375 }
374 return val; 376 return val;
375 } 377 }
376 #endif 378 #endif
377 379
378 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) 380 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
379 enum boot_device get_boot_device(void) 381 enum boot_device get_boot_device(void)
380 { 382 {
381 struct bootrom_sw_info **p = 383 struct bootrom_sw_info **p =
382 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR; 384 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
383 385
384 enum boot_device boot_dev = SD1_BOOT; 386 enum boot_device boot_dev = SD1_BOOT;
385 u8 boot_type = (*p)->boot_dev_type; 387 u8 boot_type = (*p)->boot_dev_type;
386 u8 boot_instance = (*p)->boot_dev_instance; 388 u8 boot_instance = (*p)->boot_dev_instance;
387 389
388 switch (boot_type) { 390 switch (boot_type) {
389 case BOOT_TYPE_SD: 391 case BOOT_TYPE_SD:
390 boot_dev = boot_instance + SD1_BOOT; 392 boot_dev = boot_instance + SD1_BOOT;
391 break; 393 break;
392 case BOOT_TYPE_MMC: 394 case BOOT_TYPE_MMC:
393 boot_dev = boot_instance + MMC1_BOOT; 395 boot_dev = boot_instance + MMC1_BOOT;
394 break; 396 break;
395 case BOOT_TYPE_NAND: 397 case BOOT_TYPE_NAND:
396 boot_dev = NAND_BOOT; 398 boot_dev = NAND_BOOT;
397 break; 399 break;
398 case BOOT_TYPE_QSPI: 400 case BOOT_TYPE_QSPI:
399 boot_dev = QSPI_BOOT; 401 boot_dev = QSPI_BOOT;
400 break; 402 break;
401 case BOOT_TYPE_WEIM: 403 case BOOT_TYPE_WEIM:
402 boot_dev = WEIM_NOR_BOOT; 404 boot_dev = WEIM_NOR_BOOT;
403 break; 405 break;
404 case BOOT_TYPE_SPINOR: 406 case BOOT_TYPE_SPINOR:
405 boot_dev = SPI_NOR_BOOT; 407 boot_dev = SPI_NOR_BOOT;
406 break; 408 break;
407 #ifdef CONFIG_IMX8M 409 #ifdef CONFIG_IMX8M
408 case BOOT_TYPE_USB: 410 case BOOT_TYPE_USB:
409 boot_dev = USB_BOOT; 411 boot_dev = USB_BOOT;
410 break; 412 break;
411 #endif 413 #endif
412 default: 414 default:
413 break; 415 break;
414 } 416 }
415 417
416 return boot_dev; 418 return boot_dev;
417 } 419 }
418 #endif 420 #endif
419 421
420 #ifdef CONFIG_NXP_BOARD_REVISION 422 #ifdef CONFIG_NXP_BOARD_REVISION
421 int nxp_board_rev(void) 423 int nxp_board_rev(void)
422 { 424 {
423 /* 425 /*
424 * Get Board ID information from OCOTP_GP1[15:8] 426 * Get Board ID information from OCOTP_GP1[15:8]
425 * RevA: 0x1 427 * RevA: 0x1
426 * RevB: 0x2 428 * RevB: 0x2
427 * RevC: 0x3 429 * RevC: 0x3
428 */ 430 */
429 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 431 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
430 struct fuse_bank *bank = &ocotp->bank[4]; 432 struct fuse_bank *bank = &ocotp->bank[4];
431 struct fuse_bank4_regs *fuse = 433 struct fuse_bank4_regs *fuse =
432 (struct fuse_bank4_regs *)bank->fuse_regs; 434 (struct fuse_bank4_regs *)bank->fuse_regs;
433 435
434 return (readl(&fuse->gp1) >> 8 & 0x0F); 436 return (readl(&fuse->gp1) >> 8 & 0x0F);
435 } 437 }
436 438
437 char nxp_board_rev_string(void) 439 char nxp_board_rev_string(void)
438 { 440 {
439 const char *rev = "A"; 441 const char *rev = "A";
440 442
441 return (*rev + nxp_board_rev() - 1); 443 return (*rev + nxp_board_rev() - 1);
442 } 444 }
443 #endif 445 #endif
444 446
arch/arm/mach-imx/imx8m/soc.c
Diff comments   View file @ 2434131
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 * 4 *
5 * Peng Fan <peng.fan@nxp.com> 5 * Peng Fan <peng.fan@nxp.com>
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/imx-regs.h>
10 #include <asm/io.h> 10 #include <asm/io.h>
11 #include <asm/arch/clock.h> 11 #include <asm/arch/clock.h>
12 #include <asm/arch/sys_proto.h> 12 #include <asm/arch/sys_proto.h>
13 #include <asm/mach-imx/hab.h> 13 #include <asm/mach-imx/hab.h>
14 #include <asm/mach-imx/boot_mode.h> 14 #include <asm/mach-imx/boot_mode.h>
15 #include <asm/mach-imx/syscounter.h> 15 #include <asm/mach-imx/syscounter.h>
16 #include <asm/armv8/mmu.h> 16 #include <asm/armv8/mmu.h>
17 #include <dm/uclass.h> 17 #include <dm/uclass.h>
18 #include <errno.h> 18 #include <errno.h>
19 #include <fdt_support.h> 19 #include <fdt_support.h>
20 #include <fsl_wdog.h> 20 #include <fsl_wdog.h>
21 #include <imx_sip.h> 21 #include <imx_sip.h>
22 22
23 DECLARE_GLOBAL_DATA_PTR; 23 DECLARE_GLOBAL_DATA_PTR;
24 24
25 #if defined(CONFIG_IMX_HAB) 25 #if defined(CONFIG_IMX_HAB)
26 struct imx_sec_config_fuse_t const imx_sec_config_fuse = { 26 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
27 .bank = 1, 27 .bank = 1,
28 .word = 3, 28 .word = 3,
29 }; 29 };
30 #endif 30 #endif
31 31
32 int timer_init(void) 32 int timer_init(void)
33 { 33 {
34 #ifdef CONFIG_SPL_BUILD 34 #ifdef CONFIG_SPL_BUILD
35 struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; 35 struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
36 unsigned long freq = readl(&sctr->cntfid0); 36 unsigned long freq = readl(&sctr->cntfid0);
37 37
38 /* Update with accurate clock frequency */ 38 /* Update with accurate clock frequency */
39 asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory"); 39 asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
40 40
41 clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1, 41 clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
42 SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG); 42 SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
43 #endif 43 #endif
44 44
45 gd->arch.tbl = 0; 45 gd->arch.tbl = 0;
46 gd->arch.tbu = 0; 46 gd->arch.tbu = 0;
47 47
48 return 0; 48 return 0;
49 } 49 }
50 50
51 void enable_tzc380(void) 51 void enable_tzc380(void)
52 { 52 {
53 struct iomuxc_gpr_base_regs *gpr = 53 struct iomuxc_gpr_base_regs *gpr =
54 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; 54 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
55 55
56 /* Enable TZASC and lock setting */ 56 /* Enable TZASC and lock setting */
57 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN); 57 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
58 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK); 58 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
59 if (IS_ENABLED(CONFIG_IMX8MM)) 59 if (IS_ENABLED(CONFIG_IMX8MM))
60 setbits_le32(&gpr->gpr[10], BIT(1)); 60 setbits_le32(&gpr->gpr[10], BIT(1));
61 /* 61 /*
62 * set Region 0 attribute to allow secure and non-secure 62 * set Region 0 attribute to allow secure and non-secure
63 * read/write permission. Found some masters like usb dwc3 63 * read/write permission. Found some masters like usb dwc3
64 * controllers can't work with secure memory. 64 * controllers can't work with secure memory.
65 */ 65 */
66 writel(0xf0000000, TZASC_BASE_ADDR + 0x108); 66 writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
67 } 67 }
68 68
69 void set_wdog_reset(struct wdog_regs *wdog) 69 void set_wdog_reset(struct wdog_regs *wdog)
70 { 70 {
71 /* 71 /*
72 * Output WDOG_B signal to reset external pmic or POR_B decided by 72 * Output WDOG_B signal to reset external pmic or POR_B decided by
73 * the board design. Without external reset, the peripherals/DDR/ 73 * the board design. Without external reset, the peripherals/DDR/
74 * PMIC are not reset, that may cause system working abnormal. 74 * PMIC are not reset, that may cause system working abnormal.
75 * WDZST bit is write-once only bit. Align this bit in kernel, 75 * WDZST bit is write-once only bit. Align this bit in kernel,
76 * otherwise kernel code will have no chance to set this bit. 76 * otherwise kernel code will have no chance to set this bit.
77 */ 77 */
78 setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK); 78 setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
79 } 79 }
80 80
81 static struct mm_region imx8m_mem_map[] = { 81 static struct mm_region imx8m_mem_map[] = {
82 { 82 {
83 /* ROM */ 83 /* ROM */
84 .virt = 0x0UL, 84 .virt = 0x0UL,
85 .phys = 0x0UL, 85 .phys = 0x0UL,
86 .size = 0x100000UL, 86 .size = 0x100000UL,
87 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 87 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
88 PTE_BLOCK_OUTER_SHARE 88 PTE_BLOCK_OUTER_SHARE
89 }, { 89 }, {
90 /* CAAM */ 90 /* CAAM */
91 .virt = 0x100000UL, 91 .virt = 0x100000UL,
92 .phys = 0x100000UL, 92 .phys = 0x100000UL,
93 .size = 0x8000UL, 93 .size = 0x8000UL,
94 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 94 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
95 PTE_BLOCK_NON_SHARE | 95 PTE_BLOCK_NON_SHARE |
96 PTE_BLOCK_PXN | PTE_BLOCK_UXN 96 PTE_BLOCK_PXN | PTE_BLOCK_UXN
97 }, { 97 }, {
98 /* TCM */ 98 /* TCM */
99 .virt = 0x7C0000UL, 99 .virt = 0x7C0000UL,
100 .phys = 0x7C0000UL, 100 .phys = 0x7C0000UL,
101 .size = 0x80000UL, 101 .size = 0x80000UL,
102 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 102 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
103 PTE_BLOCK_NON_SHARE | 103 PTE_BLOCK_NON_SHARE |
104 PTE_BLOCK_PXN | PTE_BLOCK_UXN 104 PTE_BLOCK_PXN | PTE_BLOCK_UXN
105 }, { 105 }, {
106 /* OCRAM */ 106 /* OCRAM */
107 .virt = 0x900000UL, 107 .virt = 0x900000UL,
108 .phys = 0x900000UL, 108 .phys = 0x900000UL,
109 .size = 0x200000UL, 109 .size = 0x200000UL,
110 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 110 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
111 PTE_BLOCK_OUTER_SHARE 111 PTE_BLOCK_OUTER_SHARE
112 }, { 112 }, {
113 /* AIPS */ 113 /* AIPS */
114 .virt = 0xB00000UL, 114 .virt = 0xB00000UL,
115 .phys = 0xB00000UL, 115 .phys = 0xB00000UL,
116 .size = 0x3f500000UL, 116 .size = 0x3f500000UL,
117 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 117 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
118 PTE_BLOCK_NON_SHARE | 118 PTE_BLOCK_NON_SHARE |
119 PTE_BLOCK_PXN | PTE_BLOCK_UXN 119 PTE_BLOCK_PXN | PTE_BLOCK_UXN
120 }, { 120 }, {
121 /* DRAM1 */ 121 /* DRAM1 */
122 .virt = 0x40000000UL, 122 .virt = 0x40000000UL,
123 .phys = 0x40000000UL, 123 .phys = 0x40000000UL,
124 .size = PHYS_SDRAM_SIZE, 124 .size = PHYS_SDRAM_SIZE,
125 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 125 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
126 PTE_BLOCK_OUTER_SHARE 126 PTE_BLOCK_OUTER_SHARE
127 #ifdef PHYS_SDRAM_2_SIZE 127 #ifdef PHYS_SDRAM_2_SIZE
128 }, { 128 }, {
129 /* DRAM2 */ 129 /* DRAM2 */
130 .virt = 0x100000000UL, 130 .virt = 0x100000000UL,
131 .phys = 0x100000000UL, 131 .phys = 0x100000000UL,
132 .size = PHYS_SDRAM_2_SIZE, 132 .size = PHYS_SDRAM_2_SIZE,
133 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 133 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
134 PTE_BLOCK_OUTER_SHARE 134 PTE_BLOCK_OUTER_SHARE
135 #endif 135 #endif
136 }, { 136 }, {
137 /* List terminator */ 137 /* List terminator */
138 0, 138 0,
139 } 139 }
140 }; 140 };
141 141
142 struct mm_region *mem_map = imx8m_mem_map; 142 struct mm_region *mem_map = imx8m_mem_map;
143 143
144 void enable_caches(void) 144 void enable_caches(void)
145 { 145 {
146 /* 146 /*
147 * If OPTEE runs, remove OPTEE memory from MMU table to 147 * If OPTEE runs, remove OPTEE memory from MMU table to
148 * avoid speculative prefetch. OPTEE runs at the top of 148 * avoid speculative prefetch. OPTEE runs at the top of
149 * the first memory bank 149 * the first memory bank
150 */ 150 */
151 if (rom_pointer[1]) 151 if (rom_pointer[1])
152 imx8m_mem_map[5].size -= rom_pointer[1]; 152 imx8m_mem_map[5].size -= rom_pointer[1];
153 153
154 icache_enable(); 154 icache_enable();
155 dcache_enable(); 155 dcache_enable();
156 } 156 }
157 157
158 static u32 get_cpu_variant_type(u32 type) 158 static u32 get_cpu_variant_type(u32 type)
159 { 159 {
160 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 160 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
161 struct fuse_bank *bank = &ocotp->bank[1]; 161 struct fuse_bank *bank = &ocotp->bank[1];
162 struct fuse_bank1_regs *fuse = 162 struct fuse_bank1_regs *fuse =
163 (struct fuse_bank1_regs *)bank->fuse_regs; 163 (struct fuse_bank1_regs *)bank->fuse_regs;
164 164
165 u32 value = readl(&fuse->tester4); 165 u32 value = readl(&fuse->tester4);
166 166
167 if (type == MXC_CPU_IMX8MM) { 167 if (type == MXC_CPU_IMX8MM) {
168 switch (value & 0x3) { 168 switch (value & 0x3) {
169 case 2: 169 case 2:
170 if (value & 0x1c0000) 170 if (value & 0x1c0000)
171 return MXC_CPU_IMX8MMDL; 171 return MXC_CPU_IMX8MMDL;
172 else 172 else
173 return MXC_CPU_IMX8MMD; 173 return MXC_CPU_IMX8MMD;
174 case 3: 174 case 3:
175 if (value & 0x1c0000) 175 if (value & 0x1c0000)
176 return MXC_CPU_IMX8MMSL; 176 return MXC_CPU_IMX8MMSL;
177 else 177 else
178 return MXC_CPU_IMX8MMS; 178 return MXC_CPU_IMX8MMS;
179 default: 179 default:
180 if (value & 0x1c0000) 180 if (value & 0x1c0000)
181 return MXC_CPU_IMX8MML; 181 return MXC_CPU_IMX8MML;
182 break; 182 break;
183 } 183 }
184 } 184 }
185 185
186 return type; 186 return type;
187 } 187 }
188 188
189 u32 get_cpu_rev(void) 189 u32 get_cpu_rev(void)
190 { 190 {
191 struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; 191 struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
192 u32 reg = readl(&ana_pll->digprog); 192 u32 reg = readl(&ana_pll->digprog);
193 u32 type = (reg >> 16) & 0xff; 193 u32 type = (reg >> 16) & 0xff;
194 u32 major_low = (reg >> 8) & 0xff; 194 u32 major_low = (reg >> 8) & 0xff;
195 u32 rom_version; 195 u32 rom_version;
196 196
197 reg &= 0xff; 197 reg &= 0xff;
198 198
199 /* i.MX8MM */ 199 /* i.MX8MM */
200 if (major_low == 0x41) { 200 if (major_low == 0x42) {
201 return (MXC_CPU_IMX8MN << 12) | reg;
202 } else if (major_low == 0x41) {
201 type = get_cpu_variant_type(MXC_CPU_IMX8MM); 203 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
202 } else { 204 } else {
203 if (reg == CHIP_REV_1_0) { 205 if (reg == CHIP_REV_1_0) {
204 /* 206 /*
205 * For B0 chip, the DIGPROG is not updated, 207 * For B0 chip, the DIGPROG is not updated,
206 * it is still TO1.0. we have to check ROM 208 * it is still TO1.0. we have to check ROM
207 * version or OCOTP_READ_FUSE_DATA. 209 * version or OCOTP_READ_FUSE_DATA.
208 * 0xff0055aa is magic number for B1. 210 * 0xff0055aa is magic number for B1.
209 */ 211 */
210 if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) { 212 if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
211 reg = CHIP_REV_2_1; 213 reg = CHIP_REV_2_1;
212 } else { 214 } else {
213 rom_version = 215 rom_version =
214 readl((void __iomem *)ROM_VERSION_A0); 216 readl((void __iomem *)ROM_VERSION_A0);
215 if (rom_version != CHIP_REV_1_0) { 217 if (rom_version != CHIP_REV_1_0) {
216 rom_version = readl((void __iomem *)ROM_VERSION_B0); 218 rom_version = readl((void __iomem *)ROM_VERSION_B0);
217 if (rom_version == CHIP_REV_2_0) 219 if (rom_version == CHIP_REV_2_0)
218 reg = CHIP_REV_2_0; 220 reg = CHIP_REV_2_0;
219 } 221 }
220 } 222 }
221 } 223 }
222 } 224 }
223 225
224 return (type << 12) | reg; 226 return (type << 12) | reg;
225 } 227 }
226 228
227 static void imx_set_wdog_powerdown(bool enable) 229 static void imx_set_wdog_powerdown(bool enable)
228 { 230 {
229 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; 231 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
230 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; 232 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
231 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; 233 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
232 234
233 /* Write to the PDE (Power Down Enable) bit */ 235 /* Write to the PDE (Power Down Enable) bit */
234 writew(enable, &wdog1->wmcr); 236 writew(enable, &wdog1->wmcr);
235 writew(enable, &wdog2->wmcr); 237 writew(enable, &wdog2->wmcr);
236 writew(enable, &wdog3->wmcr); 238 writew(enable, &wdog3->wmcr);
237 } 239 }
238 240
239 int arch_cpu_init_dm(void) 241 int arch_cpu_init_dm(void)
240 { 242 {
241 struct udevice *dev; 243 struct udevice *dev;
242 int ret; 244 int ret;
243 245
244 ret = uclass_get_device_by_name(UCLASS_CLK, 246 ret = uclass_get_device_by_name(UCLASS_CLK,
245 "clock-controller@30380000", 247 "clock-controller@30380000",
246 &dev); 248 &dev);
247 if (ret < 0) { 249 if (ret < 0) {
248 printf("Failed to find clock node. Check device tree\n"); 250 printf("Failed to find clock node. Check device tree\n");
249 return ret; 251 return ret;
250 } 252 }
251 253
252 return 0; 254 return 0;
253 } 255 }
254 256
255 int arch_cpu_init(void) 257 int arch_cpu_init(void)
256 { 258 {
257 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 259 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
258 /* 260 /*
259 * ROM might disable clock for SCTR, 261 * ROM might disable clock for SCTR,
260 * enable the clock before timer_init. 262 * enable the clock before timer_init.
261 */ 263 */
262 if (IS_ENABLED(CONFIG_SPL_BUILD)) 264 if (IS_ENABLED(CONFIG_SPL_BUILD))
263 clock_enable(CCGR_SCTR, 1); 265 clock_enable(CCGR_SCTR, 1);
264 /* 266 /*
265 * Init timer at very early state, because sscg pll setting 267 * Init timer at very early state, because sscg pll setting
266 * will use it 268 * will use it
267 */ 269 */
268 timer_init(); 270 timer_init();
269 271
270 if (IS_ENABLED(CONFIG_SPL_BUILD)) { 272 if (IS_ENABLED(CONFIG_SPL_BUILD)) {
271 clock_init(); 273 clock_init();
272 imx_set_wdog_powerdown(false); 274 imx_set_wdog_powerdown(false);
273 } 275 }
274 276
275 if (is_imx8mq()) { 277 if (is_imx8mq()) {
276 clock_enable(CCGR_OCOTP, 1); 278 clock_enable(CCGR_OCOTP, 1);
277 if (readl(&ocotp->ctrl) & 0x200) 279 if (readl(&ocotp->ctrl) & 0x200)
278 writel(0x200, &ocotp->ctrl_clr); 280 writel(0x200, &ocotp->ctrl_clr);
279 } 281 }
280 282
281 return 0; 283 return 0;
282 } 284 }
283 285
284 bool is_usb_boot(void) 286 bool is_usb_boot(void)
285 { 287 {
286 return get_boot_device() == USB_BOOT; 288 return get_boot_device() == USB_BOOT;
287 } 289 }
288 290
289 #ifdef CONFIG_OF_SYSTEM_SETUP 291 #ifdef CONFIG_OF_SYSTEM_SETUP
290 int ft_system_setup(void *blob, bd_t *bd) 292 int ft_system_setup(void *blob, bd_t *bd)
291 { 293 {
292 int i = 0; 294 int i = 0;
293 int rc; 295 int rc;
294 int nodeoff; 296 int nodeoff;
295 297
296 /* Disable the CPU idle for A0 chip since the HW does not support it */ 298 /* Disable the CPU idle for A0 chip since the HW does not support it */
297 if (is_soc_rev(CHIP_REV_1_0)) { 299 if (is_soc_rev(CHIP_REV_1_0)) {
298 static const char * const nodes_path[] = { 300 static const char * const nodes_path[] = {
299 "/cpus/cpu@0", 301 "/cpus/cpu@0",
300 "/cpus/cpu@1", 302 "/cpus/cpu@1",
301 "/cpus/cpu@2", 303 "/cpus/cpu@2",
302 "/cpus/cpu@3", 304 "/cpus/cpu@3",
303 }; 305 };
304 306
305 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) { 307 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
306 nodeoff = fdt_path_offset(blob, nodes_path[i]); 308 nodeoff = fdt_path_offset(blob, nodes_path[i]);
307 if (nodeoff < 0) 309 if (nodeoff < 0)
308 continue; /* Not found, skip it */ 310 continue; /* Not found, skip it */
309 311
310 printf("Found %s node\n", nodes_path[i]); 312 printf("Found %s node\n", nodes_path[i]);
311 313
312 rc = fdt_delprop(blob, nodeoff, "cpu-idle-states"); 314 rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
313 if (rc) { 315 if (rc) {
314 printf("Unable to update property %s:%s, err=%s\n", 316 printf("Unable to update property %s:%s, err=%s\n",
315 nodes_path[i], "status", fdt_strerror(rc)); 317 nodes_path[i], "status", fdt_strerror(rc));
316 return rc; 318 return rc;
317 } 319 }
318 320
319 printf("Remove %s:%s\n", nodes_path[i], 321 printf("Remove %s:%s\n", nodes_path[i],
320 "cpu-idle-states"); 322 "cpu-idle-states");
321 } 323 }
322 } 324 }
323 325
324 return 0; 326 return 0;
325 } 327 }
326 #endif 328 #endif
327 329
328 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET) 330 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET)
329 void reset_cpu(ulong addr) 331 void reset_cpu(ulong addr)
330 { 332 {
331 struct watchdog_regs *wdog = (struct watchdog_regs *)addr; 333 struct watchdog_regs *wdog = (struct watchdog_regs *)addr;
332 334
333 if (!addr) 335 if (!addr)
334 wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; 336 wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
335 337
336 /* Clear WDA to trigger WDOG_B immediately */ 338 /* Clear WDA to trigger WDOG_B immediately */
337 writew((WCR_WDE | WCR_SRS), &wdog->wcr); 339 writew((WCR_WDE | WCR_SRS), &wdog->wcr);
338 340
339 while (1) { 341 while (1) {
340 /* 342 /*
341 * spin for .5 seconds before reset 343 * spin for .5 seconds before reset
342 */ 344 */
343 } 345 }
344 } 346 }
345 #endif 347 #endif
346 348