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Commit 29138c6ff80d6e736640050f5e9643637c44abad

Authored by Soeren Moch
Committed by Stefano Babic
1 parent 3b30eece27
Exists in v2017.01-smarct4x and in 28 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

board: tbs2910: Fix BOOTMAPSZ 

The linux kernel imx_v6_v7_defconfig sets the user/kernel memory split
to 3G/1G now (was 2G/2G before). We have to adapt the BOOTMAPSZ so that
the decompressor finds zImage and dtb in lowmem.

Signed-off-by: Soeren Moch <smoch@web.de>

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

include/configs/tbs2910.h
Diff comments   View file @ 29138c6
1 /* 1 /*
2 * Copyright (C) 2014 Soeren Moch <smoch@web.de> 2 * Copyright (C) 2014 Soeren Moch <smoch@web.de>
3 * 3 *
4 * Configuration settings for the TBS2910 MatrixARM board. 4 * Configuration settings for the TBS2910 MatrixARM board.
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #ifndef __TBS2910_CONFIG_H 9 #ifndef __TBS2910_CONFIG_H
10 #define __TBS2910_CONFIG_H 10 #define __TBS2910_CONFIG_H
11 11
12 #include "mx6_common.h" 12 #include "mx6_common.h"
13 13
14 /* General configuration */ 14 /* General configuration */
15 #define CONFIG_SYS_THUMB_BUILD 15 #define CONFIG_SYS_THUMB_BUILD
16 16
17 #define CONFIG_MACH_TYPE 3980 17 #define CONFIG_MACH_TYPE 3980
18 18
19 #define CONFIG_BOARD_EARLY_INIT_F 19 #define CONFIG_BOARD_EARLY_INIT_F
20 20
21 #define CONFIG_SYS_HZ 1000 21 #define CONFIG_SYS_HZ 1000
22 22
23 #define CONFIG_IMX_THERMAL 23 #define CONFIG_IMX_THERMAL
24 24
25 /* Physical Memory Map */ 25 /* Physical Memory Map */
26 #define CONFIG_NR_DRAM_BANKS 1 26 #define CONFIG_NR_DRAM_BANKS 1
27 #define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR 27 #define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
28 28
29 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 29 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
30 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 30 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
31 #define CONFIG_SYS_INIT_SP_OFFSET \ 31 #define CONFIG_SYS_INIT_SP_OFFSET \
32 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 32 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
33 #define CONFIG_SYS_INIT_SP_ADDR \ 33 #define CONFIG_SYS_INIT_SP_ADDR \
34 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 34 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
35 35
36 #define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) 36 #define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024)
37 37
38 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 38 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
39 #define CONFIG_SYS_MEMTEST_END \ 39 #define CONFIG_SYS_MEMTEST_END \
40 (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024) 40 (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
41 41
42 #define CONFIG_SYS_BOOTMAPSZ 0x6C000000 42 #define CONFIG_SYS_BOOTMAPSZ 0x10000000
43 43
44 /* Serial console */ 44 /* Serial console */
45 #define CONFIG_MXC_UART 45 #define CONFIG_MXC_UART
46 #define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */ 46 #define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */
47 #define CONFIG_BAUDRATE 115200 47 #define CONFIG_BAUDRATE 115200
48 48
49 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 49 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
50 #define CONFIG_CONSOLE_MUX 50 #define CONFIG_CONSOLE_MUX
51 #define CONFIG_CONS_INDEX 1 51 #define CONFIG_CONS_INDEX 1
52 52
53 #define CONFIG_PRE_CONSOLE_BUFFER 53 #define CONFIG_PRE_CONSOLE_BUFFER
54 #define CONFIG_PRE_CON_BUF_SZ 4096 54 #define CONFIG_PRE_CON_BUF_SZ 4096
55 #define CONFIG_PRE_CON_BUF_ADDR 0x7C000000 55 #define CONFIG_PRE_CON_BUF_ADDR 0x7C000000
56 56
57 /* *** Command definition *** */ 57 /* *** Command definition *** */
58 #define CONFIG_CMD_BMODE 58 #define CONFIG_CMD_BMODE
59 59
60 /* Filesystems / image support */ 60 /* Filesystems / image support */
61 #define CONFIG_EFI_PARTITION 61 #define CONFIG_EFI_PARTITION
62 62
63 /* MMC */ 63 /* MMC */
64 #define CONFIG_SYS_FSL_USDHC_NUM 3 64 #define CONFIG_SYS_FSL_USDHC_NUM 3
65 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR 65 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
66 #define CONFIG_SUPPORT_EMMC_BOOT 66 #define CONFIG_SUPPORT_EMMC_BOOT
67 67
68 /* Ethernet */ 68 /* Ethernet */
69 #define CONFIG_FEC_MXC 69 #define CONFIG_FEC_MXC
70 #define CONFIG_FEC_MXC 70 #define CONFIG_FEC_MXC
71 #define CONFIG_MII 71 #define CONFIG_MII
72 #define IMX_FEC_BASE ENET_BASE_ADDR 72 #define IMX_FEC_BASE ENET_BASE_ADDR
73 #define CONFIG_FEC_XCV_TYPE RGMII 73 #define CONFIG_FEC_XCV_TYPE RGMII
74 #define CONFIG_ETHPRIME "FEC" 74 #define CONFIG_ETHPRIME "FEC"
75 #define CONFIG_FEC_MXC_PHYADDR 4 75 #define CONFIG_FEC_MXC_PHYADDR 4
76 #define CONFIG_PHYLIB 76 #define CONFIG_PHYLIB
77 #define CONFIG_PHY_ATHEROS 77 #define CONFIG_PHY_ATHEROS
78 78
79 /* Framebuffer */ 79 /* Framebuffer */
80 #define CONFIG_VIDEO 80 #define CONFIG_VIDEO
81 #ifdef CONFIG_VIDEO 81 #ifdef CONFIG_VIDEO
82 #define CONFIG_VIDEO_IPUV3 82 #define CONFIG_VIDEO_IPUV3
83 #define CONFIG_IPUV3_CLK 260000000 83 #define CONFIG_IPUV3_CLK 260000000
84 #define CONFIG_CFB_CONSOLE 84 #define CONFIG_CFB_CONSOLE
85 #define CONFIG_CFB_CONSOLE_ANSI 85 #define CONFIG_CFB_CONSOLE_ANSI
86 #define CONFIG_VIDEO_SW_CURSOR 86 #define CONFIG_VIDEO_SW_CURSOR
87 #define CONFIG_VGA_AS_SINGLE_DEVICE 87 #define CONFIG_VGA_AS_SINGLE_DEVICE
88 #define CONFIG_VIDEO_BMP_RLE8 88 #define CONFIG_VIDEO_BMP_RLE8
89 #define CONFIG_IMX_HDMI 89 #define CONFIG_IMX_HDMI
90 #define CONFIG_IMX_VIDEO_SKIP 90 #define CONFIG_IMX_VIDEO_SKIP
91 #define CONFIG_CMD_HDMIDETECT 91 #define CONFIG_CMD_HDMIDETECT
92 #endif 92 #endif
93 93
94 /* PCI */ 94 /* PCI */
95 #define CONFIG_CMD_PCI 95 #define CONFIG_CMD_PCI
96 #ifdef CONFIG_CMD_PCI 96 #ifdef CONFIG_CMD_PCI
97 #define CONFIG_PCI 97 #define CONFIG_PCI
98 #define CONFIG_PCI_PNP 98 #define CONFIG_PCI_PNP
99 #define CONFIG_PCI_SCAN_SHOW 99 #define CONFIG_PCI_SCAN_SHOW
100 #define CONFIG_PCIE_IMX 100 #define CONFIG_PCIE_IMX
101 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) 101 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
102 #endif 102 #endif
103 103
104 /* SATA */ 104 /* SATA */
105 #define CONFIG_CMD_SATA 105 #define CONFIG_CMD_SATA
106 #ifdef CONFIG_CMD_SATA 106 #ifdef CONFIG_CMD_SATA
107 #define CONFIG_DWC_AHSATA 107 #define CONFIG_DWC_AHSATA
108 #define CONFIG_SYS_SATA_MAX_DEVICE 1 108 #define CONFIG_SYS_SATA_MAX_DEVICE 1
109 #define CONFIG_DWC_AHSATA_PORT_ID 0 109 #define CONFIG_DWC_AHSATA_PORT_ID 0
110 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 110 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
111 #define CONFIG_LBA48 111 #define CONFIG_LBA48
112 #define CONFIG_LIBATA 112 #define CONFIG_LIBATA
113 #endif 113 #endif
114 114
115 /* USB */ 115 /* USB */
116 #ifdef CONFIG_CMD_USB 116 #ifdef CONFIG_CMD_USB
117 #define CONFIG_USB_EHCI 117 #define CONFIG_USB_EHCI
118 #define CONFIG_USB_EHCI_MX6 118 #define CONFIG_USB_EHCI_MX6
119 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 119 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
120 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 120 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
121 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 121 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
122 #ifdef CONFIG_CMD_USB_MASS_STORAGE 122 #ifdef CONFIG_CMD_USB_MASS_STORAGE
123 #define CONFIG_USBD_HS 123 #define CONFIG_USBD_HS
124 #define CONFIG_USB_FUNCTION_MASS_STORAGE 124 #define CONFIG_USB_FUNCTION_MASS_STORAGE
125 #endif /* CONFIG_CMD_USB_MASS_STORAGE */ 125 #endif /* CONFIG_CMD_USB_MASS_STORAGE */
126 #define CONFIG_USB_KEYBOARD 126 #define CONFIG_USB_KEYBOARD
127 #ifdef CONFIG_USB_KEYBOARD 127 #ifdef CONFIG_USB_KEYBOARD
128 #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE 128 #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
129 #define CONFIG_SYS_STDIO_DEREGISTER 129 #define CONFIG_SYS_STDIO_DEREGISTER
130 #define CONFIG_PREBOOT \ 130 #define CONFIG_PREBOOT \
131 "usb start; " \ 131 "usb start; " \
132 "if hdmidet; then " \ 132 "if hdmidet; then " \
133 "run set_con_hdmi; " \ 133 "run set_con_hdmi; " \
134 "else " \ 134 "else " \
135 "run set_con_serial; " \ 135 "run set_con_serial; " \
136 "fi;" 136 "fi;"
137 #endif /* CONFIG_USB_KEYBOARD */ 137 #endif /* CONFIG_USB_KEYBOARD */
138 #endif /* CONFIG_CMD_USB */ 138 #endif /* CONFIG_CMD_USB */
139 139
140 /* RTC */ 140 /* RTC */
141 #define CONFIG_CMD_DATE 141 #define CONFIG_CMD_DATE
142 #ifdef CONFIG_CMD_DATE 142 #ifdef CONFIG_CMD_DATE
143 #define CONFIG_RTC_DS1307 143 #define CONFIG_RTC_DS1307
144 #define CONFIG_SYS_RTC_BUS_NUM 2 144 #define CONFIG_SYS_RTC_BUS_NUM 2
145 #endif 145 #endif
146 146
147 /* I2C */ 147 /* I2C */
148 #ifdef CONFIG_CMD_I2C 148 #ifdef CONFIG_CMD_I2C
149 #define CONFIG_SYS_I2C 149 #define CONFIG_SYS_I2C
150 #define CONFIG_SYS_I2C_MXC 150 #define CONFIG_SYS_I2C_MXC
151 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 151 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
152 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 152 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
153 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 153 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
154 #define CONFIG_SYS_I2C_SPEED 100000 154 #define CONFIG_SYS_I2C_SPEED 100000
155 #define CONFIG_I2C_EDID 155 #define CONFIG_I2C_EDID
156 #endif 156 #endif
157 157
158 /* Environment organization */ 158 /* Environment organization */
159 #define CONFIG_ENV_IS_IN_MMC 159 #define CONFIG_ENV_IS_IN_MMC
160 #define CONFIG_SYS_MMC_ENV_DEV 2 /* overwritten on SD boot */ 160 #define CONFIG_SYS_MMC_ENV_DEV 2 /* overwritten on SD boot */
161 #define CONFIG_SYS_MMC_ENV_PART 1 /* overwritten on SD boot */ 161 #define CONFIG_SYS_MMC_ENV_PART 1 /* overwritten on SD boot */
162 #define CONFIG_ENV_SIZE (8 * 1024) 162 #define CONFIG_ENV_SIZE (8 * 1024)
163 #define CONFIG_ENV_OFFSET (384 * 1024) 163 #define CONFIG_ENV_OFFSET (384 * 1024)
164 #define CONFIG_ENV_OVERWRITE 164 #define CONFIG_ENV_OVERWRITE
165 165
166 #define CONFIG_EXTRA_ENV_SETTINGS \ 166 #define CONFIG_EXTRA_ENV_SETTINGS \
167 "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \ 167 "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
168 "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \ 168 "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
169 "video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \ 169 "video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \
170 "bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \ 170 "bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \
171 "bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \ 171 "bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \
172 "${bootargs_mmc3}\0" \ 172 "${bootargs_mmc3}\0" \
173 "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \ 173 "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \
174 "rdinit=/sbin/init enable_wait_mode=off\0" \ 174 "rdinit=/sbin/init enable_wait_mode=off\0" \
175 "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \ 175 "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \
176 "mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \ 176 "mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \
177 "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \ 177 "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \
178 "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \ 178 "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \
179 "run bootargs_upd; " \ 179 "run bootargs_upd; " \
180 "bootm 0x10800000 0x10d00000\0" \ 180 "bootm 0x10800000 0x10d00000\0" \
181 "console=ttymxc0\0" \ 181 "console=ttymxc0\0" \
182 "fan=gpio set 92\0" \ 182 "fan=gpio set 92\0" \
183 "set_con_serial=setenv stdout serial; " \ 183 "set_con_serial=setenv stdout serial; " \
184 "setenv stderr serial;\0" \ 184 "setenv stderr serial;\0" \
185 "set_con_hdmi=setenv stdout serial,vga; " \ 185 "set_con_hdmi=setenv stdout serial,vga; " \
186 "setenv stderr serial,vga;\0" \ 186 "setenv stderr serial,vga;\0" \
187 "stderr=serial,vga;\0" \ 187 "stderr=serial,vga;\0" \
188 "stdin=serial,usbkbd;\0" \ 188 "stdin=serial,usbkbd;\0" \
189 "stdout=serial,vga;\0" 189 "stdout=serial,vga;\0"
190 190
191 #define CONFIG_BOOTCOMMAND \ 191 #define CONFIG_BOOTCOMMAND \
192 "mmc rescan; " \ 192 "mmc rescan; " \
193 "if run bootcmd_up1; then " \ 193 "if run bootcmd_up1; then " \
194 "run bootcmd_up2; " \ 194 "run bootcmd_up2; " \
195 "else " \ 195 "else " \
196 "run bootcmd_mmc; " \ 196 "run bootcmd_mmc; " \
197 "fi" 197 "fi"
198 198
199 #endif /* __TBS2910_CONFIG_H * */ 199 #endif /* __TBS2910_CONFIG_H * */
200 200