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Commit 2ade7bee153d801db8246a3e3f06805f8231b677

Authored by Dirk Eibach
Committed by Stefan Roese
1 parent b19bf8344f

powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20 

In hardware revision 1.20 one more fan controller is added to dlvision-10g.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

Showing 2 changed files with 13 additions and 3 deletions Inline Diff

board/gdsys/405ep/dlvision-10g.c
Diff comments   View file @ 2ade7be
1 /* 1 /*
2 * (C) Copyright 2010 2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 #include <common.h> 24 #include <common.h>
25 #include <command.h> 25 #include <command.h>
26 #include <asm/processor.h> 26 #include <asm/processor.h>
27 #include <asm/io.h> 27 #include <asm/io.h>
28 #include <asm/ppc4xx-gpio.h> 28 #include <asm/ppc4xx-gpio.h>
29 #include <dtt.h> 29 #include <dtt.h>
30 30
31 #include "405ep.h" 31 #include "405ep.h"
32 #include <gdsys_fpga.h> 32 #include <gdsys_fpga.h>
33 33
34 #include "../common/osd.h" 34 #include "../common/osd.h"
35 35
36 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) 36 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
37 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) 37 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
38 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) 38 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
39 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300) 39 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
40 40
41 #define LATCH2_MC2_PRESENT_N 0x0080 41 #define LATCH2_MC2_PRESENT_N 0x0080
42 42
43 enum { 43 enum {
44 UNITTYPE_VIDEO_USER = 0, 44 UNITTYPE_VIDEO_USER = 0,
45 UNITTYPE_MAIN_USER = 1, 45 UNITTYPE_MAIN_USER = 1,
46 UNITTYPE_VIDEO_SERVER = 2, 46 UNITTYPE_VIDEO_SERVER = 2,
47 UNITTYPE_MAIN_SERVER = 3, 47 UNITTYPE_MAIN_SERVER = 3,
48 }; 48 };
49 49
50 enum { 50 enum {
51 HWVER_101 = 0, 51 HWVER_101 = 0,
52 HWVER_110 = 1, 52 HWVER_110 = 1,
53 HWVER_120 = 2,
54 HWVER_130 = 3,
53 }; 55 };
54 56
55 enum { 57 enum {
56 AUDIO_NONE = 0, 58 AUDIO_NONE = 0,
57 AUDIO_TX = 1, 59 AUDIO_TX = 1,
58 AUDIO_RX = 2, 60 AUDIO_RX = 2,
59 AUDIO_RXTX = 3, 61 AUDIO_RXTX = 3,
60 }; 62 };
61 63
62 enum { 64 enum {
63 SYSCLK_156250 = 2, 65 SYSCLK_156250 = 2,
64 }; 66 };
65 67
66 enum { 68 enum {
67 RAM_NONE = 0, 69 RAM_NONE = 0,
68 RAM_DDR2_32 = 1, 70 RAM_DDR2_32 = 1,
69 RAM_DDR2_64 = 2, 71 RAM_DDR2_64 = 2,
70 }; 72 };
71 73
72 int misc_init_r(void) 74 int misc_init_r(void)
73 { 75 {
74 /* startup fans */ 76 /* startup fans */
75 dtt_init(); 77 dtt_init();
76 78
77 return 0; 79 return 0;
78 } 80 }
79 81
80 static unsigned int get_hwver(void) 82 static unsigned int get_hwver(void)
81 { 83 {
82 u16 latch3 = in_le16((void *)LATCH3_BASE); 84 u16 latch3 = in_le16((void *)LATCH3_BASE);
83 85
84 return latch3 & 0x0003; 86 return latch3 & 0x0003;
85 } 87 }
86 88
87 static unsigned int get_mc2_present(void) 89 static unsigned int get_mc2_present(void)
88 { 90 {
89 u16 latch2 = in_le16((void *)LATCH2_BASE); 91 u16 latch2 = in_le16((void *)LATCH2_BASE);
90 92
91 return !(latch2 & LATCH2_MC2_PRESENT_N); 93 return !(latch2 & LATCH2_MC2_PRESENT_N);
92 } 94 }
93 95
94 static void print_fpga_info(unsigned dev) 96 static void print_fpga_info(unsigned dev)
95 { 97 {
96 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev); 98 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
97 u16 versions = in_le16(&fpga->versions); 99 u16 versions = in_le16(&fpga->versions);
98 u16 fpga_version = in_le16(&fpga->fpga_version); 100 u16 fpga_version = in_le16(&fpga->fpga_version);
99 u16 fpga_features = in_le16(&fpga->fpga_features); 101 u16 fpga_features = in_le16(&fpga->fpga_features);
100 unsigned unit_type; 102 unsigned unit_type;
101 unsigned hardware_version; 103 unsigned hardware_version;
102 unsigned feature_rs232; 104 unsigned feature_rs232;
103 unsigned feature_audio; 105 unsigned feature_audio;
104 unsigned feature_sysclock; 106 unsigned feature_sysclock;
105 unsigned feature_ramconfig; 107 unsigned feature_ramconfig;
106 unsigned feature_carrier_speed; 108 unsigned feature_carrier_speed;
107 unsigned feature_carriers; 109 unsigned feature_carriers;
108 unsigned feature_video_channels; 110 unsigned feature_video_channels;
109 int fpga_state = get_fpga_state(dev); 111 int fpga_state = get_fpga_state(dev);
110 112
111 printf("FPGA%d: ", dev); 113 printf("FPGA%d: ", dev);
112 114
113 hardware_version = versions & 0x000f; 115 hardware_version = versions & 0x000f;
114 116
115 if (fpga_state 117 if (fpga_state
116 && !((hardware_version == HWVER_101) 118 && !((hardware_version == HWVER_101)
117 && (fpga_state == FPGA_STATE_DONE_FAILED))) { 119 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
118 puts("not available\n"); 120 puts("not available\n");
119 print_fpga_state(dev); 121 print_fpga_state(dev);
120 return; 122 return;
121 } 123 }
122 124
123 unit_type = (versions >> 4) & 0x000f; 125 unit_type = (versions >> 4) & 0x000f;
124 hardware_version = versions & 0x000f; 126 hardware_version = versions & 0x000f;
125 feature_rs232 = fpga_features & (1<<11); 127 feature_rs232 = fpga_features & (1<<11);
126 feature_audio = (fpga_features >> 9) & 0x0003; 128 feature_audio = (fpga_features >> 9) & 0x0003;
127 feature_sysclock = (fpga_features >> 7) & 0x0003; 129 feature_sysclock = (fpga_features >> 7) & 0x0003;
128 feature_ramconfig = (fpga_features >> 5) & 0x0003; 130 feature_ramconfig = (fpga_features >> 5) & 0x0003;
129 feature_carrier_speed = fpga_features & (1<<4); 131 feature_carrier_speed = fpga_features & (1<<4);
130 feature_carriers = (fpga_features >> 2) & 0x0003; 132 feature_carriers = (fpga_features >> 2) & 0x0003;
131 feature_video_channels = fpga_features & 0x0003; 133 feature_video_channels = fpga_features & 0x0003;
132 134
133 switch (unit_type) { 135 switch (unit_type) {
134 case UNITTYPE_VIDEO_USER: 136 case UNITTYPE_VIDEO_USER:
135 printf("Videochannel Userside"); 137 printf("Videochannel Userside");
136 break; 138 break;
137 139
138 case UNITTYPE_MAIN_USER: 140 case UNITTYPE_MAIN_USER:
139 printf("Mainchannel Userside"); 141 printf("Mainchannel Userside");
140 break; 142 break;
141 143
142 case UNITTYPE_VIDEO_SERVER: 144 case UNITTYPE_VIDEO_SERVER:
143 printf("Videochannel Serverside"); 145 printf("Videochannel Serverside");
144 break; 146 break;
145 147
146 case UNITTYPE_MAIN_SERVER: 148 case UNITTYPE_MAIN_SERVER:
147 printf("Mainchannel Serverside"); 149 printf("Mainchannel Serverside");
148 break; 150 break;
149 151
150 default: 152 default:
151 printf("UnitType %d(not supported)", unit_type); 153 printf("UnitType %d(not supported)", unit_type);
152 break; 154 break;
153 } 155 }
154 156
155 switch (hardware_version) { 157 switch (hardware_version) {
156 case HWVER_101: 158 case HWVER_101:
157 printf(" HW-Ver 1.01\n"); 159 printf(" HW-Ver 1.01\n");
158 break; 160 break;
159 161
160 case HWVER_110: 162 case HWVER_110:
161 printf(" HW-Ver 1.10\n"); 163 printf(" HW-Ver 1.10-1.12\n");
164 break;
165
166 case HWVER_120:
167 printf(" HW-Ver 1.20\n");
168 break;
169
170 case HWVER_130:
171 printf(" HW-Ver 1.30\n");
162 break; 172 break;
163 173
164 default: 174 default:
165 printf(" HW-Ver %d(not supported)\n", 175 printf(" HW-Ver %d(not supported)\n",
166 hardware_version); 176 hardware_version);
167 break; 177 break;
168 } 178 }
169 179
170 printf(" FPGA V %d.%02d, features:", 180 printf(" FPGA V %d.%02d, features:",
171 fpga_version / 100, fpga_version % 100); 181 fpga_version / 100, fpga_version % 100);
172 182
173 printf(" %sRS232", feature_rs232 ? "" : "no "); 183 printf(" %sRS232", feature_rs232 ? "" : "no ");
174 184
175 switch (feature_audio) { 185 switch (feature_audio) {
176 case AUDIO_NONE: 186 case AUDIO_NONE:
177 printf(", no audio"); 187 printf(", no audio");
178 break; 188 break;
179 189
180 case AUDIO_TX: 190 case AUDIO_TX:
181 printf(", audio tx"); 191 printf(", audio tx");
182 break; 192 break;
183 193
184 case AUDIO_RX: 194 case AUDIO_RX:
185 printf(", audio rx"); 195 printf(", audio rx");
186 break; 196 break;
187 197
188 case AUDIO_RXTX: 198 case AUDIO_RXTX:
189 printf(", audio rx+tx"); 199 printf(", audio rx+tx");
190 break; 200 break;
191 201
192 default: 202 default:
193 printf(", audio %d(not supported)", feature_audio); 203 printf(", audio %d(not supported)", feature_audio);
194 break; 204 break;
195 } 205 }
196 206
197 switch (feature_sysclock) { 207 switch (feature_sysclock) {
198 case SYSCLK_156250: 208 case SYSCLK_156250:
199 printf(", clock 156.25 MHz"); 209 printf(", clock 156.25 MHz");
200 break; 210 break;
201 211
202 default: 212 default:
203 printf(", clock %d(not supported)", feature_sysclock); 213 printf(", clock %d(not supported)", feature_sysclock);
204 break; 214 break;
205 } 215 }
206 216
207 puts(",\n "); 217 puts(",\n ");
208 218
209 switch (feature_ramconfig) { 219 switch (feature_ramconfig) {
210 case RAM_NONE: 220 case RAM_NONE:
211 printf("no RAM"); 221 printf("no RAM");
212 break; 222 break;
213 223
214 case RAM_DDR2_32: 224 case RAM_DDR2_32:
215 printf("RAM 32 bit DDR2"); 225 printf("RAM 32 bit DDR2");
216 break; 226 break;
217 227
218 case RAM_DDR2_64: 228 case RAM_DDR2_64:
219 printf("RAM 64 bit DDR2"); 229 printf("RAM 64 bit DDR2");
220 break; 230 break;
221 231
222 default: 232 default:
223 printf("RAM %d(not supported)", feature_ramconfig); 233 printf("RAM %d(not supported)", feature_ramconfig);
224 break; 234 break;
225 } 235 }
226 236
227 printf(", %d carrier(s) %s", feature_carriers, 237 printf(", %d carrier(s) %s", feature_carriers,
228 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed"); 238 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
229 239
230 printf(", %d video channel(s)\n", feature_video_channels); 240 printf(", %d video channel(s)\n", feature_video_channels);
231 } 241 }
232 242
233 /* 243 /*
234 * Check Board Identity: 244 * Check Board Identity:
235 */ 245 */
236 int checkboard(void) 246 int checkboard(void)
237 { 247 {
238 char *s = getenv("serial#"); 248 char *s = getenv("serial#");
239 249
240 puts("Board: "); 250 puts("Board: ");
241 251
242 puts("DLVision 10G"); 252 puts("DLVision 10G");
243 253
244 if (s != NULL) { 254 if (s != NULL) {
245 puts(", serial# "); 255 puts(", serial# ");
246 puts(s); 256 puts(s);
247 } 257 }
248 258
249 puts("\n"); 259 puts("\n");
250 260
251 return 0; 261 return 0;
252 } 262 }
253 263
254 int last_stage_init(void) 264 int last_stage_init(void)
255 { 265 {
256 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); 266 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
257 u16 versions = in_le16(&fpga->versions); 267 u16 versions = in_le16(&fpga->versions);
258 268
259 print_fpga_info(0); 269 print_fpga_info(0);
260 if (get_mc2_present()) 270 if (get_mc2_present())
261 print_fpga_info(1); 271 print_fpga_info(1);
262 272
263 if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER) 273 if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
264 return 0; 274 return 0;
265 275
266 if (!get_fpga_state(0) || (get_hwver() == HWVER_101)) 276 if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
267 osd_probe(0); 277 osd_probe(0);
268 278
269 if (get_mc2_present() && 279 if (get_mc2_present() &&
270 (!get_fpga_state(1) || (get_hwver() == HWVER_101))) 280 (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
271 osd_probe(1); 281 osd_probe(1);
272 282
273 return 0; 283 return 0;
274 } 284 }
275 285
276 void gd405ep_init(void) 286 void gd405ep_init(void)
277 { 287 {
278 } 288 }
279 289
280 void gd405ep_set_fpga_reset(unsigned state) 290 void gd405ep_set_fpga_reset(unsigned state)
281 { 291 {
282 if (state) { 292 if (state) {
283 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); 293 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
284 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); 294 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
285 } else { 295 } else {
286 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); 296 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
287 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); 297 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
288 } 298 }
289 } 299 }
290 300
291 void gd405ep_setup_hw(void) 301 void gd405ep_setup_hw(void)
292 { 302 {
293 /* 303 /*
294 * set "startup-finished"-gpios 304 * set "startup-finished"-gpios
295 */ 305 */
296 gpio_write_bit(21, 0); 306 gpio_write_bit(21, 0);
297 gpio_write_bit(22, 1); 307 gpio_write_bit(22, 1);
298 } 308 }
299 309
300 int gd405ep_get_fpga_done(unsigned fpga) 310 int gd405ep_get_fpga_done(unsigned fpga)
301 { 311 {
302 return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga); 312 return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
303 } 313 }
304 314
include/configs/dlvision-10g.h
Diff comments   View file @ 2ade7be
1 /* 1 /*
2 * (C) Copyright 2010 2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 #ifndef __CONFIG_H 24 #ifndef __CONFIG_H
25 #define __CONFIG_H 25 #define __CONFIG_H
26 26
27 #define CONFIG_405EP 1 /* this is a PPC405 CPU */ 27 #define CONFIG_405EP 1 /* this is a PPC405 CPU */
28 #define CONFIG_4xx 1 /* member of PPC4xx family */ 28 #define CONFIG_4xx 1 /* member of PPC4xx family */
29 #define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */ 29 #define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */
30 30
31 #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 31 #define CONFIG_SYS_TEXT_BASE 0xFFFC0000
32 32
33 /* 33 /*
34 * Include common defines/options for all AMCC eval boards 34 * Include common defines/options for all AMCC eval boards
35 */ 35 */
36 #define CONFIG_HOSTNAME dlvsion-10g 36 #define CONFIG_HOSTNAME dlvsion-10g
37 #define CONFIG_IDENT_STRING " dlvision-10g 0.02" 37 #define CONFIG_IDENT_STRING " dlvision-10g 0.03"
38 #include "amcc-common.h" 38 #include "amcc-common.h"
39 39
40 #define CONFIG_BOARD_EARLY_INIT_F 40 #define CONFIG_BOARD_EARLY_INIT_F
41 #define CONFIG_BOARD_EARLY_INIT_R 41 #define CONFIG_BOARD_EARLY_INIT_R
42 #define CONFIG_MISC_INIT_R 42 #define CONFIG_MISC_INIT_R
43 #define CONFIG_LAST_STAGE_INIT 43 #define CONFIG_LAST_STAGE_INIT
44 44
45 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ 45 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
46 46
47 #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ 47 #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
48 #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ 48 #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
49 #define CONFIG_AUTOBOOT_STOP_STR " " 49 #define CONFIG_AUTOBOOT_STOP_STR " "
50 50
51 /* 51 /*
52 * Configure PLL 52 * Configure PLL
53 */ 53 */
54 #define PLLMR0_DEFAULT PLLMR0_266_133_66 54 #define PLLMR0_DEFAULT PLLMR0_266_133_66
55 #define PLLMR1_DEFAULT PLLMR1_266_133_66 55 #define PLLMR1_DEFAULT PLLMR1_266_133_66
56 56
57 /* new uImage format support */ 57 /* new uImage format support */
58 #define CONFIG_FIT 58 #define CONFIG_FIT
59 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 59 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
60 60
61 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ 61 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
62 62
63 /* 63 /*
64 * Default environment variables 64 * Default environment variables
65 */ 65 */
66 #define CONFIG_EXTRA_ENV_SETTINGS \ 66 #define CONFIG_EXTRA_ENV_SETTINGS \
67 CONFIG_AMCC_DEF_ENV \ 67 CONFIG_AMCC_DEF_ENV \
68 CONFIG_AMCC_DEF_ENV_POWERPC \ 68 CONFIG_AMCC_DEF_ENV_POWERPC \
69 CONFIG_AMCC_DEF_ENV_NOR_UPD \ 69 CONFIG_AMCC_DEF_ENV_NOR_UPD \
70 "kernel_addr=fc000000\0" \ 70 "kernel_addr=fc000000\0" \
71 "fdt_addr=fc1e0000\0" \ 71 "fdt_addr=fc1e0000\0" \
72 "ramdisk_addr=fc200000\0" \ 72 "ramdisk_addr=fc200000\0" \
73 "" 73 ""
74 74
75 #define CONFIG_PHY_ADDR 4 /* PHY address */ 75 #define CONFIG_PHY_ADDR 4 /* PHY address */
76 #define CONFIG_HAS_ETH0 76 #define CONFIG_HAS_ETH0
77 #define CONFIG_HAS_ETH1 77 #define CONFIG_HAS_ETH1
78 #define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */ 78 #define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
79 #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ 79 #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
80 80
81 /* 81 /*
82 * Commands additional to the ones defined in amcc-common.h 82 * Commands additional to the ones defined in amcc-common.h
83 */ 83 */
84 #define CONFIG_CMD_CACHE 84 #define CONFIG_CMD_CACHE
85 #define CONFIG_CMD_DTT 85 #define CONFIG_CMD_DTT
86 #undef CONFIG_CMD_EEPROM 86 #undef CONFIG_CMD_EEPROM
87 87
88 /* 88 /*
89 * SDRAM configuration (please see cpu/ppc/sdram.[ch]) 89 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
90 */ 90 */
91 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ 91 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
92 92
93 /* SDRAM timings used in datasheet */ 93 /* SDRAM timings used in datasheet */
94 #define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ 94 #define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
95 #define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ 95 #define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
96 #define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */ 96 #define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
97 #define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ 97 #define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
98 #define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ 98 #define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
99 99
100 /* 100 /*
101 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. 101 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
102 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. 102 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
103 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD. 103 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
104 * The Linux BASE_BAUD define should match this configuration. 104 * The Linux BASE_BAUD define should match this configuration.
105 * baseBaud = cpuClock/(uartDivisor*16) 105 * baseBaud = cpuClock/(uartDivisor*16)
106 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, 106 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
107 * set Linux BASE_BAUD to 403200. 107 * set Linux BASE_BAUD to 403200.
108 */ 108 */
109 #define CONFIG_CONS_INDEX 1 /* Use UART0 */ 109 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
110 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ 110 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
111 #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ 111 #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
112 #define CONFIG_SYS_BASE_BAUD 691200 112 #define CONFIG_SYS_BASE_BAUD 691200
113 113
114 /* 114 /*
115 * I2C stuff 115 * I2C stuff
116 */ 116 */
117 #define CONFIG_SYS_I2C_SPEED 100000 117 #define CONFIG_SYS_I2C_SPEED 100000
118 118
119 /* Temp sensor/hwmon/dtt */ 119 /* Temp sensor/hwmon/dtt */
120 #define CONFIG_DTT_LM63 1 /* National LM63 */ 120 #define CONFIG_DTT_LM63 1 /* National LM63 */
121 #define CONFIG_DTT_SENSORS { 0x4c, 0x4e } /* Sensor addresses */ 121 #define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
122 #define CONFIG_DTT_PWM_LOOKUPTABLE \ 122 #define CONFIG_DTT_PWM_LOOKUPTABLE \
123 { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\ 123 { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
124 { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } } 124 { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
125 #define CONFIG_DTT_TACH_LIMIT 0xa10 125 #define CONFIG_DTT_TACH_LIMIT 0xa10
126 126
127 /* EBC peripherals */ 127 /* EBC peripherals */
128 128
129 #define CONFIG_SYS_FLASH_BASE 0xFC000000 129 #define CONFIG_SYS_FLASH_BASE 0xFC000000
130 #define CONFIG_SYS_FPGA0_BASE 0x7f100000 130 #define CONFIG_SYS_FPGA0_BASE 0x7f100000
131 #define CONFIG_SYS_FPGA1_BASE 0x7f200000 131 #define CONFIG_SYS_FPGA1_BASE 0x7f200000
132 #define CONFIG_SYS_LATCH_BASE 0x7f300000 132 #define CONFIG_SYS_LATCH_BASE 0x7f300000
133 133
134 #define CONFIG_SYS_FPGA_BASE(k) \ 134 #define CONFIG_SYS_FPGA_BASE(k) \
135 (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE) 135 (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
136 136
137 #define CONFIG_SYS_FPGA_DONE(k) \ 137 #define CONFIG_SYS_FPGA_DONE(k) \
138 (k ? 0x2000 : 0x1000) 138 (k ? 0x2000 : 0x1000)
139 139
140 #define CONFIG_SYS_FPGA_COUNT 2 140 #define CONFIG_SYS_FPGA_COUNT 2
141 141
142 #define CONFIG_SYS_LATCH0_RESET 0xffff 142 #define CONFIG_SYS_LATCH0_RESET 0xffff
143 #define CONFIG_SYS_LATCH0_BOOT 0xffff 143 #define CONFIG_SYS_LATCH0_BOOT 0xffff
144 #define CONFIG_SYS_LATCH1_RESET 0xffcf 144 #define CONFIG_SYS_LATCH1_RESET 0xffcf
145 #define CONFIG_SYS_LATCH1_BOOT 0xffff 145 #define CONFIG_SYS_LATCH1_BOOT 0xffff
146 146
147 #define CONFIG_SYS_FPGA_NO_RFL_HI 147 #define CONFIG_SYS_FPGA_NO_RFL_HI
148 148
149 /* 149 /*
150 * FLASH organization 150 * FLASH organization
151 */ 151 */
152 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 152 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
153 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 153 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
154 154
155 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 155 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
156 156
157 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 157 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
158 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/ 158 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
159 159
160 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */ 160 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
161 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ 161 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
162 162
163 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */ 163 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
164 #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */ 164 #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
165 165
166 #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ 166 #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
167 #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */ 167 #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
168 168
169 #ifdef CONFIG_ENV_IS_IN_FLASH 169 #ifdef CONFIG_ENV_IS_IN_FLASH
170 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ 170 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
171 #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) 171 #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
172 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ 172 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
173 173
174 /* Address and size of Redundant Environment Sector */ 174 /* Address and size of Redundant Environment Sector */
175 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) 175 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
176 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 176 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
177 #endif 177 #endif
178 178
179 /* 179 /*
180 * PPC405 GPIO Configuration 180 * PPC405 GPIO Configuration
181 */ 181 */
182 #define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ 182 #define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
183 { \ 183 { \
184 /* GPIO Core 0 */ \ 184 /* GPIO Core 0 */ \
185 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \ 185 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
186 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ 186 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
187 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ 187 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
188 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ 188 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
189 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ 189 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
190 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \ 190 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
191 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \ 191 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
192 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \ 192 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
193 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ 193 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
194 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \ 194 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
195 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ 195 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
196 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ 196 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
197 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ 197 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
198 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ 198 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
199 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \ 199 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
200 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \ 200 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
201 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \ 201 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
202 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \ 202 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
203 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \ 203 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
204 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \ 204 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
205 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \ 205 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
206 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \ 206 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
207 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \ 207 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
208 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \ 208 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
209 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \ 209 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
210 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ 210 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
211 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ 211 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
212 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ 212 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
213 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \ 213 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
214 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ 214 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
215 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \ 215 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
216 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \ 216 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
217 } \ 217 } \
218 } 218 }
219 219
220 /* 220 /*
221 * Definitions for initial stack pointer and data area (in data cache) 221 * Definitions for initial stack pointer and data area (in data cache)
222 */ 222 */
223 /* use on chip memory (OCM) for temperary stack until sdram is tested */ 223 /* use on chip memory (OCM) for temperary stack until sdram is tested */
224 #define CONFIG_SYS_TEMP_STACK_OCM 1 224 #define CONFIG_SYS_TEMP_STACK_OCM 1
225 225
226 /* On Chip Memory location */ 226 /* On Chip Memory location */
227 #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 227 #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
228 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 228 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
229 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ 229 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
230 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */ 230 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
231 231
232 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/ 232 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
233 #define CONFIG_SYS_GBL_DATA_OFFSET \ 233 #define CONFIG_SYS_GBL_DATA_OFFSET \
234 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 234 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
235 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 235 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
236 236
237 /* 237 /*
238 * External Bus Controller (EBC) Setup 238 * External Bus Controller (EBC) Setup
239 */ 239 */
240 240
241 /* Memory Bank 0 (NOR-flash) */ 241 /* Memory Bank 0 (NOR-flash) */
242 #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED | \ 242 #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED | \
243 EBC_BXAP_FWT_ENCODE(8) | \ 243 EBC_BXAP_FWT_ENCODE(8) | \
244 EBC_BXAP_BWT_ENCODE(7) | \ 244 EBC_BXAP_BWT_ENCODE(7) | \
245 EBC_BXAP_BCE_DISABLE | \ 245 EBC_BXAP_BCE_DISABLE | \
246 EBC_BXAP_BCT_2TRANS | \ 246 EBC_BXAP_BCT_2TRANS | \
247 EBC_BXAP_CSN_ENCODE(0) | \ 247 EBC_BXAP_CSN_ENCODE(0) | \
248 EBC_BXAP_OEN_ENCODE(2) | \ 248 EBC_BXAP_OEN_ENCODE(2) | \
249 EBC_BXAP_WBN_ENCODE(2) | \ 249 EBC_BXAP_WBN_ENCODE(2) | \
250 EBC_BXAP_WBF_ENCODE(2) | \ 250 EBC_BXAP_WBF_ENCODE(2) | \
251 EBC_BXAP_TH_ENCODE(4) | \ 251 EBC_BXAP_TH_ENCODE(4) | \
252 EBC_BXAP_RE_DISABLED | \ 252 EBC_BXAP_RE_DISABLED | \
253 EBC_BXAP_SOR_NONDELAYED | \ 253 EBC_BXAP_SOR_NONDELAYED | \
254 EBC_BXAP_BEM_WRITEONLY | \ 254 EBC_BXAP_BEM_WRITEONLY | \
255 EBC_BXAP_PEN_DISABLED) 255 EBC_BXAP_PEN_DISABLED)
256 #define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ 256 #define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
257 EBC_BXCR_BS_64MB | \ 257 EBC_BXCR_BS_64MB | \
258 EBC_BXCR_BU_RW | \ 258 EBC_BXCR_BU_RW | \
259 EBC_BXCR_BW_16BIT) 259 EBC_BXCR_BW_16BIT)
260 260
261 /* Memory Bank 1 (FPGA0) */ 261 /* Memory Bank 1 (FPGA0) */
262 #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ 262 #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
263 EBC_BXAP_TWT_ENCODE(5) | \ 263 EBC_BXAP_TWT_ENCODE(5) | \
264 EBC_BXAP_BCE_DISABLE | \ 264 EBC_BXAP_BCE_DISABLE | \
265 EBC_BXAP_BCT_2TRANS | \ 265 EBC_BXAP_BCT_2TRANS | \
266 EBC_BXAP_CSN_ENCODE(0) | \ 266 EBC_BXAP_CSN_ENCODE(0) | \
267 EBC_BXAP_OEN_ENCODE(2) | \ 267 EBC_BXAP_OEN_ENCODE(2) | \
268 EBC_BXAP_WBN_ENCODE(1) | \ 268 EBC_BXAP_WBN_ENCODE(1) | \
269 EBC_BXAP_WBF_ENCODE(1) | \ 269 EBC_BXAP_WBF_ENCODE(1) | \
270 EBC_BXAP_TH_ENCODE(0) | \ 270 EBC_BXAP_TH_ENCODE(0) | \
271 EBC_BXAP_RE_DISABLED | \ 271 EBC_BXAP_RE_DISABLED | \
272 EBC_BXAP_SOR_NONDELAYED | \ 272 EBC_BXAP_SOR_NONDELAYED | \
273 EBC_BXAP_BEM_WRITEONLY | \ 273 EBC_BXAP_BEM_WRITEONLY | \
274 EBC_BXAP_PEN_DISABLED) 274 EBC_BXAP_PEN_DISABLED)
275 #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \ 275 #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
276 EBC_BXCR_BS_1MB | \ 276 EBC_BXCR_BS_1MB | \
277 EBC_BXCR_BU_RW | \ 277 EBC_BXCR_BU_RW | \
278 EBC_BXCR_BW_16BIT) 278 EBC_BXCR_BW_16BIT)
279 279
280 /* Memory Bank 2 (FPGA1) */ 280 /* Memory Bank 2 (FPGA1) */
281 #define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \ 281 #define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
282 EBC_BXAP_TWT_ENCODE(6) | \ 282 EBC_BXAP_TWT_ENCODE(6) | \
283 EBC_BXAP_BCE_DISABLE | \ 283 EBC_BXAP_BCE_DISABLE | \
284 EBC_BXAP_BCT_2TRANS | \ 284 EBC_BXAP_BCT_2TRANS | \
285 EBC_BXAP_CSN_ENCODE(0) | \ 285 EBC_BXAP_CSN_ENCODE(0) | \
286 EBC_BXAP_OEN_ENCODE(2) | \ 286 EBC_BXAP_OEN_ENCODE(2) | \
287 EBC_BXAP_WBN_ENCODE(1) | \ 287 EBC_BXAP_WBN_ENCODE(1) | \
288 EBC_BXAP_WBF_ENCODE(1) | \ 288 EBC_BXAP_WBF_ENCODE(1) | \
289 EBC_BXAP_TH_ENCODE(0) | \ 289 EBC_BXAP_TH_ENCODE(0) | \
290 EBC_BXAP_RE_DISABLED | \ 290 EBC_BXAP_RE_DISABLED | \
291 EBC_BXAP_SOR_NONDELAYED | \ 291 EBC_BXAP_SOR_NONDELAYED | \
292 EBC_BXAP_BEM_WRITEONLY | \ 292 EBC_BXAP_BEM_WRITEONLY | \
293 EBC_BXAP_PEN_DISABLED) 293 EBC_BXAP_PEN_DISABLED)
294 #define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \ 294 #define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
295 EBC_BXCR_BS_1MB | \ 295 EBC_BXCR_BS_1MB | \
296 EBC_BXCR_BU_RW | \ 296 EBC_BXCR_BU_RW | \
297 EBC_BXCR_BW_16BIT) 297 EBC_BXCR_BW_16BIT)
298 298
299 /* Memory Bank 3 (Latches) */ 299 /* Memory Bank 3 (Latches) */
300 #define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \ 300 #define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
301 EBC_BXAP_FWT_ENCODE(8) | \ 301 EBC_BXAP_FWT_ENCODE(8) | \
302 EBC_BXAP_BWT_ENCODE(4) | \ 302 EBC_BXAP_BWT_ENCODE(4) | \
303 EBC_BXAP_BCE_DISABLE | \ 303 EBC_BXAP_BCE_DISABLE | \
304 EBC_BXAP_BCT_2TRANS | \ 304 EBC_BXAP_BCT_2TRANS | \
305 EBC_BXAP_CSN_ENCODE(0) | \ 305 EBC_BXAP_CSN_ENCODE(0) | \
306 EBC_BXAP_OEN_ENCODE(1) | \ 306 EBC_BXAP_OEN_ENCODE(1) | \
307 EBC_BXAP_WBN_ENCODE(1) | \ 307 EBC_BXAP_WBN_ENCODE(1) | \
308 EBC_BXAP_WBF_ENCODE(1) | \ 308 EBC_BXAP_WBF_ENCODE(1) | \
309 EBC_BXAP_TH_ENCODE(2) | \ 309 EBC_BXAP_TH_ENCODE(2) | \
310 EBC_BXAP_RE_DISABLED | \ 310 EBC_BXAP_RE_DISABLED | \
311 EBC_BXAP_SOR_NONDELAYED | \ 311 EBC_BXAP_SOR_NONDELAYED | \
312 EBC_BXAP_BEM_WRITEONLY | \ 312 EBC_BXAP_BEM_WRITEONLY | \
313 EBC_BXAP_PEN_DISABLED) 313 EBC_BXAP_PEN_DISABLED)
314 #define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \ 314 #define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
315 EBC_BXCR_BS_1MB | \ 315 EBC_BXCR_BS_1MB | \
316 EBC_BXCR_BU_RW | \ 316 EBC_BXCR_BU_RW | \
317 EBC_BXCR_BW_16BIT) 317 EBC_BXCR_BW_16BIT)
318 318
319 /* 319 /*
320 * OSD Setup 320 * OSD Setup
321 */ 321 */
322 #define CONFIG_SYS_ICS8N3QV01 322 #define CONFIG_SYS_ICS8N3QV01
323 #define CONFIG_SYS_MPC92469AC 323 #define CONFIG_SYS_MPC92469AC
324 #define CONFIG_SYS_SIL1178 324 #define CONFIG_SYS_SIL1178
325 #define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT 325 #define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
326 326
327 #endif /* __CONFIG_H */ 327 #endif /* __CONFIG_H */
328 328