Commit 2b445e4d31940d512b3257f7398b794be710b8a9

Authored by Alexander Graf
Committed by Bin Meng
1 parent d5a815327d

x86: Move table csum into separate header

We need the checksum function without all the other table functionality
soon, so let's split it out into its own header file.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Showing 3 changed files with 24 additions and 12 deletions Inline Diff

arch/x86/include/asm/tables.h
1 /* 1 /*
2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef _X86_TABLES_H_ 7 #ifndef _X86_TABLES_H_
8 #define _X86_TABLES_H_ 8 #define _X86_TABLES_H_
9 9
10 #include <tables_csum.h>
11
10 /* 12 /*
11 * All x86 tables happen to like the address range from 0xf0000 to 0x100000. 13 * All x86 tables happen to like the address range from 0xf0000 to 0x100000.
12 * We use 0xf0000 as the starting address to store those tables, including 14 * We use 0xf0000 as the starting address to store those tables, including
13 * PIRQ routing table, Multi-Processor table and ACPI table. 15 * PIRQ routing table, Multi-Processor table and ACPI table.
14 */ 16 */
15 #define ROM_TABLE_ADDR 0xf0000 17 #define ROM_TABLE_ADDR 0xf0000
16 18
17 #define ROM_TABLE_ALIGN 1024 19 #define ROM_TABLE_ALIGN 1024
18 20
19 /* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */ 21 /* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */
20 #define CB_TABLE_ADDR 0x800 22 #define CB_TABLE_ADDR 0x800
21 23
22 /** 24 /**
23 * table_compute_checksum() - Compute a table checksum 25 * table_compute_checksum() - Compute a table checksum
24 * 26 *
25 * This computes an 8-bit checksum for the configuration table. 27 * This computes an 8-bit checksum for the configuration table.
26 * All bytes in the configuration table, including checksum itself and 28 * All bytes in the configuration table, including checksum itself and
27 * reserved bytes must add up to zero. 29 * reserved bytes must add up to zero.
28 * 30 *
29 * @v: configuration table base address 31 * @v: configuration table base address
30 * @len: configuration table size 32 * @len: configuration table size
31 * @return: the 8-bit checksum 33 * @return: the 8-bit checksum
32 */ 34 */
33 u8 table_compute_checksum(void *v, int len); 35 u8 table_compute_checksum(void *v, int len);
34 36
35 /** 37 /**
36 * table_fill_string() - Fill a string with pad in the configuration table 38 * table_fill_string() - Fill a string with pad in the configuration table
37 * 39 *
38 * This fills a string in the configuration table. It copies number of bytes 40 * This fills a string in the configuration table. It copies number of bytes
39 * from the source string, and if source string length is shorter than the 41 * from the source string, and if source string length is shorter than the
40 * required size to copy, pad the table string with the given pad character. 42 * required size to copy, pad the table string with the given pad character.
41 * 43 *
42 * @dest: where to fill a string 44 * @dest: where to fill a string
43 * @src: where to copy from 45 * @src: where to copy from
44 * @n: number of bytes to copy 46 * @n: number of bytes to copy
45 * @pad: character to pad the remaining bytes 47 * @pad: character to pad the remaining bytes
46 */ 48 */
47 void table_fill_string(char *dest, const char *src, size_t n, char pad); 49 void table_fill_string(char *dest, const char *src, size_t n, char pad);
48 50
49 /** 51 /**
50 * write_tables() - Write x86 configuration tables 52 * write_tables() - Write x86 configuration tables
51 * 53 *
52 * This writes x86 configuration tables, including PIRQ routing table, 54 * This writes x86 configuration tables, including PIRQ routing table,
53 * Multi-Processor table and ACPI table. Whether a specific type of 55 * Multi-Processor table and ACPI table. Whether a specific type of
54 * configuration table is written is controlled by a Kconfig option. 56 * configuration table is written is controlled by a Kconfig option.
55 */ 57 */
56 void write_tables(void); 58 void write_tables(void);
57 59
58 /** 60 /**
59 * write_pirq_routing_table() - Write PIRQ routing table 61 * write_pirq_routing_table() - Write PIRQ routing table
60 * 62 *
61 * This writes PIRQ routing table at a given address. 63 * This writes PIRQ routing table at a given address.
62 * 64 *
63 * @start: start address to write PIRQ routing table 65 * @start: start address to write PIRQ routing table
64 * @return: end address of PIRQ routing table 66 * @return: end address of PIRQ routing table
65 */ 67 */
66 u32 write_pirq_routing_table(u32 start); 68 u32 write_pirq_routing_table(u32 start);
67 69
68 #endif /* _X86_TABLES_H_ */ 70 #endif /* _X86_TABLES_H_ */
69 71
arch/x86/lib/tables.c
1 /* 1 /*
2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <asm/sfi.h> 8 #include <asm/sfi.h>
9 #include <asm/mpspec.h> 9 #include <asm/mpspec.h>
10 #include <asm/smbios.h> 10 #include <asm/smbios.h>
11 #include <asm/tables.h> 11 #include <asm/tables.h>
12 #include <asm/acpi_table.h> 12 #include <asm/acpi_table.h>
13 #include <asm/coreboot_tables.h> 13 #include <asm/coreboot_tables.h>
14 14
15 /** 15 /**
16 * Function prototype to write a specific configuration table 16 * Function prototype to write a specific configuration table
17 * 17 *
18 * @addr: start address to write the table 18 * @addr: start address to write the table
19 * @return: end address of the table 19 * @return: end address of the table
20 */ 20 */
21 typedef u32 (*table_write)(u32 addr); 21 typedef u32 (*table_write)(u32 addr);
22 22
23 static table_write table_write_funcs[] = { 23 static table_write table_write_funcs[] = {
24 #ifdef CONFIG_GENERATE_PIRQ_TABLE 24 #ifdef CONFIG_GENERATE_PIRQ_TABLE
25 write_pirq_routing_table, 25 write_pirq_routing_table,
26 #endif 26 #endif
27 #ifdef CONFIG_GENERATE_SFI_TABLE 27 #ifdef CONFIG_GENERATE_SFI_TABLE
28 write_sfi_table, 28 write_sfi_table,
29 #endif 29 #endif
30 #ifdef CONFIG_GENERATE_MP_TABLE 30 #ifdef CONFIG_GENERATE_MP_TABLE
31 write_mp_table, 31 write_mp_table,
32 #endif 32 #endif
33 #ifdef CONFIG_GENERATE_ACPI_TABLE 33 #ifdef CONFIG_GENERATE_ACPI_TABLE
34 write_acpi_tables, 34 write_acpi_tables,
35 #endif 35 #endif
36 #ifdef CONFIG_GENERATE_SMBIOS_TABLE 36 #ifdef CONFIG_GENERATE_SMBIOS_TABLE
37 write_smbios_table, 37 write_smbios_table,
38 #endif 38 #endif
39 }; 39 };
40 40
41 u8 table_compute_checksum(void *v, int len)
42 {
43 u8 *bytes = v;
44 u8 checksum = 0;
45 int i;
46
47 for (i = 0; i < len; i++)
48 checksum -= bytes[i];
49
50 return checksum;
51 }
52
53 void table_fill_string(char *dest, const char *src, size_t n, char pad) 41 void table_fill_string(char *dest, const char *src, size_t n, char pad)
54 { 42 {
55 int start, len; 43 int start, len;
56 int i; 44 int i;
57 45
58 strncpy(dest, src, n); 46 strncpy(dest, src, n);
59 47
60 /* Fill the remaining bytes with pad */ 48 /* Fill the remaining bytes with pad */
61 len = strlen(src); 49 len = strlen(src);
62 start = len < n ? len : n; 50 start = len < n ? len : n;
63 for (i = start; i < n; i++) 51 for (i = start; i < n; i++)
64 dest[i] = pad; 52 dest[i] = pad;
65 } 53 }
66 54
67 void write_tables(void) 55 void write_tables(void)
68 { 56 {
69 u32 rom_table_start = ROM_TABLE_ADDR; 57 u32 rom_table_start = ROM_TABLE_ADDR;
70 u32 rom_table_end; 58 u32 rom_table_end;
71 #ifdef CONFIG_SEABIOS 59 #ifdef CONFIG_SEABIOS
72 u32 high_table, table_size; 60 u32 high_table, table_size;
73 struct memory_area cfg_tables[ARRAY_SIZE(table_write_funcs) + 1]; 61 struct memory_area cfg_tables[ARRAY_SIZE(table_write_funcs) + 1];
74 #endif 62 #endif
75 int i; 63 int i;
76 64
77 for (i = 0; i < ARRAY_SIZE(table_write_funcs); i++) { 65 for (i = 0; i < ARRAY_SIZE(table_write_funcs); i++) {
78 rom_table_end = table_write_funcs[i](rom_table_start); 66 rom_table_end = table_write_funcs[i](rom_table_start);
79 rom_table_end = ALIGN(rom_table_end, ROM_TABLE_ALIGN); 67 rom_table_end = ALIGN(rom_table_end, ROM_TABLE_ALIGN);
80 68
81 #ifdef CONFIG_SEABIOS 69 #ifdef CONFIG_SEABIOS
82 table_size = rom_table_end - rom_table_start; 70 table_size = rom_table_end - rom_table_start;
83 high_table = (u32)high_table_malloc(table_size); 71 high_table = (u32)high_table_malloc(table_size);
84 if (high_table) { 72 if (high_table) {
85 table_write_funcs[i](high_table); 73 table_write_funcs[i](high_table);
86 74
87 cfg_tables[i].start = high_table; 75 cfg_tables[i].start = high_table;
88 cfg_tables[i].size = table_size; 76 cfg_tables[i].size = table_size;
89 } else { 77 } else {
90 printf("%d: no memory for configuration tables\n", i); 78 printf("%d: no memory for configuration tables\n", i);
91 } 79 }
92 #endif 80 #endif
93 81
94 rom_table_start = rom_table_end; 82 rom_table_start = rom_table_end;
95 } 83 }
96 84
97 #ifdef CONFIG_SEABIOS 85 #ifdef CONFIG_SEABIOS
98 /* make sure the last item is zero */ 86 /* make sure the last item is zero */
99 cfg_tables[i].size = 0; 87 cfg_tables[i].size = 0;
100 write_coreboot_table(CB_TABLE_ADDR, cfg_tables); 88 write_coreboot_table(CB_TABLE_ADDR, cfg_tables);
101 #endif 89 #endif
102 } 90 }
103 91
include/tables_csum.h
File was created 1 /*
2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #ifndef _TABLES_CSUM_H_
8 #define _TABLES_CSUM_H_
9
10 static inline u8 table_compute_checksum(void *v, int len)
11 {
12 u8 *bytes = v;
13 u8 checksum = 0;
14 int i;
15
16 for (i = 0; i < len; i++)
17 checksum -= bytes[i];
18
19 return checksum;
20 }
21
22 #endif
23