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Commit 2f665945b39a9972260cbcf60d5e7f2a60587f5e

Authored by Rostislav Lisovy
Committed by Scott Wood
1 parent e3a4facdfc
Exists in v2017.01-smarct4x and in 39 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

mtd: nand: am335x: Fix 'bit-flip' errors in SPL 

OMAP GPMC driver used with some NAND Flash devices
(e.g. Spansion S34ML08G1) causes that U-boot shows
hundreds of 'nand: bit-flip corrected' error messages.
Possible cause was discussed in the mailinglist thread:
http://lists.denx.de/pipermail/u-boot/2014-April/177508.html

The issue was partially fixed with the cc81a5291910d7a.git
however this has to be done to fix the SPL.

The original author of the code is Belisko Marek
<marek.belisko@gmail.com>

Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>

Showing 1 changed file with 8 additions and 4 deletions Inline Diff

drivers/mtd/nand/am335x_spl_bch.c
Diff comments   View file @ 2f66594
1 /* 1 /*
2 * (C) Copyright 2012 2 * (C) Copyright 2012
3 * Konstantin Kozhevnikov, Cogent Embedded 3 * Konstantin Kozhevnikov, Cogent Embedded
4 * 4 *
5 * based on nand_spl_simple code 5 * based on nand_spl_simple code
6 * 6 *
7 * (C) Copyright 2006-2008 7 * (C) Copyright 2006-2008
8 * Stefan Roese, DENX Software Engineering, sr@denx.de. 8 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * 9 *
10 * SPDX-License-Identifier: GPL-2.0+ 10 * SPDX-License-Identifier: GPL-2.0+
11 */ 11 */
12 12
13 #include <common.h> 13 #include <common.h>
14 #include <nand.h> 14 #include <nand.h>
15 #include <asm/io.h> 15 #include <asm/io.h>
16 #include <linux/mtd/nand_ecc.h> 16 #include <linux/mtd/nand_ecc.h>
17 17
18 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; 18 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
19 nand_info_t nand_info[1]; 19 nand_info_t nand_info[1];
20 static struct nand_chip nand_chip; 20 static struct nand_chip nand_chip;
21 21
22 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ 22 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
23 CONFIG_SYS_NAND_ECCSIZE) 23 CONFIG_SYS_NAND_ECCSIZE)
24 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES) 24 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
25 25
26 26
27 /* 27 /*
28 * NAND command for large page NAND devices (2k) 28 * NAND command for large page NAND devices (2k)
29 */ 29 */
30 static int nand_command(int block, int page, uint32_t offs, 30 static int nand_command(int block, int page, uint32_t offs,
31 u8 cmd) 31 u8 cmd)
32 { 32 {
33 struct nand_chip *this = nand_info[0].priv; 33 struct nand_chip *this = nand_info[0].priv;
34 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; 34 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
35 void (*hwctrl)(struct mtd_info *mtd, int cmd, 35 void (*hwctrl)(struct mtd_info *mtd, int cmd,
36 unsigned int ctrl) = this->cmd_ctrl; 36 unsigned int ctrl) = this->cmd_ctrl;
37 37
38 while (!this->dev_ready(&nand_info[0])) 38 while (!this->dev_ready(&nand_info[0]))
39 ; 39 ;
40 40
41 /* Emulate NAND_CMD_READOOB */ 41 /* Emulate NAND_CMD_READOOB */
42 if (cmd == NAND_CMD_READOOB) { 42 if (cmd == NAND_CMD_READOOB) {
43 offs += CONFIG_SYS_NAND_PAGE_SIZE; 43 offs += CONFIG_SYS_NAND_PAGE_SIZE;
44 cmd = NAND_CMD_READ0; 44 cmd = NAND_CMD_READ0;
45 } 45 }
46 46
47 /* Begin command latch cycle */ 47 /* Begin command latch cycle */
48 hwctrl(&nand_info[0], cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); 48 hwctrl(&nand_info[0], cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
49 49
50 if (cmd == NAND_CMD_RESET) { 50 if (cmd == NAND_CMD_RESET) {
51 hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 51 hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
52 while (!this->dev_ready(&nand_info[0])) 52 while (!this->dev_ready(&nand_info[0]))
53 ; 53 ;
54 return 0; 54 return 0;
55 } 55 }
56 56
57 /* Shift the offset from byte addressing to word addressing. */ 57 /* Shift the offset from byte addressing to word addressing. */
58 if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd)) 58 if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
59 offs >>= 1; 59 offs >>= 1;
60 60
61 /* Set ALE and clear CLE to start address cycle */ 61 /* Set ALE and clear CLE to start address cycle */
62 /* Column address */ 62 /* Column address */
63 hwctrl(&nand_info[0], offs & 0xff, 63 hwctrl(&nand_info[0], offs & 0xff,
64 NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */ 64 NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
65 hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ 65 hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
66 /* Row address */ 66 /* Row address */
67 hwctrl(&nand_info[0], (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */ 67 if (cmd != NAND_CMD_RNDOUT) {
68 hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff), 68 hwctrl(&nand_info[0], (page_addr & 0xff),
69 NAND_CTRL_ALE); /* A[19:12] */
70 hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
69 NAND_CTRL_ALE); /* A[27:20] */ 71 NAND_CTRL_ALE); /* A[27:20] */
70 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE 72 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
71 /* One more address cycle for devices > 128MiB */ 73 /* One more address cycle for devices > 128MiB */
72 hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f, 74 hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
73 NAND_CTRL_ALE); /* A[31:28] */ 75 NAND_CTRL_ALE); /* A[31:28] */
74 #endif 76 #endif
77 }
78
75 hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 79 hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
76 80
77 if (cmd == NAND_CMD_READ0) { 81 if (cmd == NAND_CMD_READ0) {
78 /* Latch in address */ 82 /* Latch in address */
79 hwctrl(&nand_info[0], NAND_CMD_READSTART, 83 hwctrl(&nand_info[0], NAND_CMD_READSTART,
80 NAND_CTRL_CLE | NAND_CTRL_CHANGE); 84 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
81 hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 85 hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
82 86
83 /* 87 /*
84 * Wait a while for the data to be ready 88 * Wait a while for the data to be ready
85 */ 89 */
86 while (!this->dev_ready(&nand_info[0])) 90 while (!this->dev_ready(&nand_info[0]))
87 ; 91 ;
88 } else if (cmd == NAND_CMD_RNDOUT) { 92 } else if (cmd == NAND_CMD_RNDOUT) {
89 hwctrl(&nand_info[0], NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE | 93 hwctrl(&nand_info[0], NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
90 NAND_CTRL_CHANGE); 94 NAND_CTRL_CHANGE);
91 hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 95 hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
92 } 96 }
93 97
94 return 0; 98 return 0;
95 } 99 }
96 100
97 static int nand_is_bad_block(int block) 101 static int nand_is_bad_block(int block)
98 { 102 {
99 struct nand_chip *this = nand_info[0].priv; 103 struct nand_chip *this = nand_info[0].priv;
100 104
101 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, 105 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
102 NAND_CMD_READOOB); 106 NAND_CMD_READOOB);
103 107
104 /* 108 /*
105 * Read one byte (or two if it's a 16 bit chip). 109 * Read one byte (or two if it's a 16 bit chip).
106 */ 110 */
107 if (this->options & NAND_BUSWIDTH_16) { 111 if (this->options & NAND_BUSWIDTH_16) {
108 if (readw(this->IO_ADDR_R) != 0xffff) 112 if (readw(this->IO_ADDR_R) != 0xffff)
109 return 1; 113 return 1;
110 } else { 114 } else {
111 if (readb(this->IO_ADDR_R) != 0xff) 115 if (readb(this->IO_ADDR_R) != 0xff)
112 return 1; 116 return 1;
113 } 117 }
114 118
115 return 0; 119 return 0;
116 } 120 }
117 121
118 static int nand_read_page(int block, int page, void *dst) 122 static int nand_read_page(int block, int page, void *dst)
119 { 123 {
120 struct nand_chip *this = nand_info[0].priv; 124 struct nand_chip *this = nand_info[0].priv;
121 u_char ecc_calc[ECCTOTAL]; 125 u_char ecc_calc[ECCTOTAL];
122 u_char ecc_code[ECCTOTAL]; 126 u_char ecc_code[ECCTOTAL];
123 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; 127 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
124 int i; 128 int i;
125 int eccsize = CONFIG_SYS_NAND_ECCSIZE; 129 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
126 int eccbytes = CONFIG_SYS_NAND_ECCBYTES; 130 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
127 int eccsteps = ECCSTEPS; 131 int eccsteps = ECCSTEPS;
128 uint8_t *p = dst; 132 uint8_t *p = dst;
129 uint32_t data_pos = 0; 133 uint32_t data_pos = 0;
130 uint8_t *oob = &oob_data[0] + nand_ecc_pos[0]; 134 uint8_t *oob = &oob_data[0] + nand_ecc_pos[0];
131 uint32_t oob_pos = eccsize * eccsteps + nand_ecc_pos[0]; 135 uint32_t oob_pos = eccsize * eccsteps + nand_ecc_pos[0];
132 136
133 nand_command(block, page, 0, NAND_CMD_READ0); 137 nand_command(block, page, 0, NAND_CMD_READ0);
134 138
135 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 139 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
136 this->ecc.hwctl(&nand_info[0], NAND_ECC_READ); 140 this->ecc.hwctl(&nand_info[0], NAND_ECC_READ);
137 nand_command(block, page, data_pos, NAND_CMD_RNDOUT); 141 nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
138 142
139 this->read_buf(&nand_info[0], p, eccsize); 143 this->read_buf(&nand_info[0], p, eccsize);
140 144
141 nand_command(block, page, oob_pos, NAND_CMD_RNDOUT); 145 nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
142 146
143 this->read_buf(&nand_info[0], oob, eccbytes); 147 this->read_buf(&nand_info[0], oob, eccbytes);
144 this->ecc.calculate(&nand_info[0], p, &ecc_calc[i]); 148 this->ecc.calculate(&nand_info[0], p, &ecc_calc[i]);
145 149
146 data_pos += eccsize; 150 data_pos += eccsize;
147 oob_pos += eccbytes; 151 oob_pos += eccbytes;
148 oob += eccbytes; 152 oob += eccbytes;
149 } 153 }
150 154
151 /* Pick the ECC bytes out of the oob data */ 155 /* Pick the ECC bytes out of the oob data */
152 for (i = 0; i < ECCTOTAL; i++) 156 for (i = 0; i < ECCTOTAL; i++)
153 ecc_code[i] = oob_data[nand_ecc_pos[i]]; 157 ecc_code[i] = oob_data[nand_ecc_pos[i]];
154 158
155 eccsteps = ECCSTEPS; 159 eccsteps = ECCSTEPS;
156 p = dst; 160 p = dst;
157 161
158 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 162 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
159 /* No chance to do something with the possible error message 163 /* No chance to do something with the possible error message
160 * from correct_data(). We just hope that all possible errors 164 * from correct_data(). We just hope that all possible errors
161 * are corrected by this routine. 165 * are corrected by this routine.
162 */ 166 */
163 this->ecc.correct(&nand_info[0], p, &ecc_code[i], &ecc_calc[i]); 167 this->ecc.correct(&nand_info[0], p, &ecc_code[i], &ecc_calc[i]);
164 } 168 }
165 169
166 return 0; 170 return 0;
167 } 171 }
168 172
169 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) 173 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
170 { 174 {
171 unsigned int block, lastblock; 175 unsigned int block, lastblock;
172 unsigned int page; 176 unsigned int page;
173 177
174 /* 178 /*
175 * offs has to be aligned to a page address! 179 * offs has to be aligned to a page address!
176 */ 180 */
177 block = offs / CONFIG_SYS_NAND_BLOCK_SIZE; 181 block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
178 lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE; 182 lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
179 page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE; 183 page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
180 184
181 while (block <= lastblock) { 185 while (block <= lastblock) {
182 if (!nand_is_bad_block(block)) { 186 if (!nand_is_bad_block(block)) {
183 /* 187 /*
184 * Skip bad blocks 188 * Skip bad blocks
185 */ 189 */
186 while (page < CONFIG_SYS_NAND_PAGE_COUNT) { 190 while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
187 nand_read_page(block, page, dst); 191 nand_read_page(block, page, dst);
188 dst += CONFIG_SYS_NAND_PAGE_SIZE; 192 dst += CONFIG_SYS_NAND_PAGE_SIZE;
189 page++; 193 page++;
190 } 194 }
191 195
192 page = 0; 196 page = 0;
193 } else { 197 } else {
194 lastblock++; 198 lastblock++;
195 } 199 }
196 200
197 block++; 201 block++;
198 } 202 }
199 203
200 return 0; 204 return 0;
201 } 205 }
202 206
203 /* nand_init() - initialize data to make nand usable by SPL */ 207 /* nand_init() - initialize data to make nand usable by SPL */
204 void nand_init(void) 208 void nand_init(void)
205 { 209 {
206 /* 210 /*
207 * Init board specific nand support 211 * Init board specific nand support
208 */ 212 */
209 nand_info[0].priv = &nand_chip; 213 nand_info[0].priv = &nand_chip;
210 nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = 214 nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
211 (void __iomem *)CONFIG_SYS_NAND_BASE; 215 (void __iomem *)CONFIG_SYS_NAND_BASE;
212 board_nand_init(&nand_chip); 216 board_nand_init(&nand_chip);
213 217
214 if (nand_chip.select_chip) 218 if (nand_chip.select_chip)
215 nand_chip.select_chip(&nand_info[0], 0); 219 nand_chip.select_chip(&nand_info[0], 0);
216 220
217 /* NAND chip may require reset after power-on */ 221 /* NAND chip may require reset after power-on */
218 nand_command(0, 0, 0, NAND_CMD_RESET); 222 nand_command(0, 0, 0, NAND_CMD_RESET);
219 } 223 }
220 224
221 /* Unselect after operation */ 225 /* Unselect after operation */
222 void nand_deselect(void) 226 void nand_deselect(void)
223 { 227 {
224 if (nand_chip.select_chip) 228 if (nand_chip.select_chip)
225 nand_chip.select_chip(&nand_info[0], -1); 229 nand_chip.select_chip(&nand_info[0], -1);
226 } 230 }
227 231