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Commit 3160b1b98603cba3c480f70e153b259171d3e4a6

Authored by Roger Quadros
Committed by Tom Rini
1 parent 02590aa31c
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

OMAP5+: sata/scsi: Implement scsi_init() 

On OMAP platforms, SATA controller provides the SCSI subsystem
so implement scsi_init().

Get rid of the unnecessary sata_init() call from dra7xx-evm
and omap5-uevm board files.

Signed-off-by: Roger Quadros <rogerq@ti.com>

Showing 4 changed files with 6 additions and 8 deletions Inline Diff

arch/arm/cpu/armv7/omap-common/sata.c
Diff comments   View file @ 3160b1b
1 /* 1 /*
2 * TI SATA platform driver 2 * TI SATA platform driver
3 * 3 *
4 * (C) Copyright 2013 4 * (C) Copyright 2013
5 * Texas Instruments, <www.ti.com> 5 * Texas Instruments, <www.ti.com>
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 #include <common.h> 10 #include <common.h>
11 #include <ahci.h> 11 #include <ahci.h>
12 #include <scsi.h> 12 #include <scsi.h>
13 #include <asm/arch/clock.h> 13 #include <asm/arch/clock.h>
14 #include <asm/arch/sata.h> 14 #include <asm/arch/sata.h>
15 #include <sata.h> 15 #include <sata.h>
16 #include <asm/io.h> 16 #include <asm/io.h>
17 #include "pipe3-phy.h" 17 #include "pipe3-phy.h"
18 18
19 static struct pipe3_dpll_map dpll_map_sata[] = { 19 static struct pipe3_dpll_map dpll_map_sata[] = {
20 {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */ 20 {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
21 {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */ 21 {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
22 {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ 22 {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
23 {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */ 23 {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
24 {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */ 24 {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
25 {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */ 25 {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
26 { }, /* Terminator */ 26 { }, /* Terminator */
27 }; 27 };
28 28
29 struct omap_pipe3 sata_phy = { 29 struct omap_pipe3 sata_phy = {
30 .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE, 30 .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
31 /* .power_reg is updated at runtime */ 31 /* .power_reg is updated at runtime */
32 .dpll_map = dpll_map_sata, 32 .dpll_map = dpll_map_sata,
33 }; 33 };
34 34
35 int init_sata(int dev) 35 int init_sata(int dev)
36 { 36 {
37 int ret; 37 int ret;
38 u32 val; 38 u32 val;
39 39
40 u32 const clk_domains_sata[] = { 40 u32 const clk_domains_sata[] = {
41 0 41 0
42 }; 42 };
43 43
44 u32 const clk_modules_hw_auto_sata[] = { 44 u32 const clk_modules_hw_auto_sata[] = {
45 (*prcm)->cm_l3init_ocp2scp3_clkctrl, 45 (*prcm)->cm_l3init_ocp2scp3_clkctrl,
46 0 46 0
47 }; 47 };
48 48
49 u32 const clk_modules_explicit_en_sata[] = { 49 u32 const clk_modules_explicit_en_sata[] = {
50 (*prcm)->cm_l3init_sata_clkctrl, 50 (*prcm)->cm_l3init_sata_clkctrl,
51 0 51 0
52 }; 52 };
53 53
54 do_enable_clocks(clk_domains_sata, 54 do_enable_clocks(clk_domains_sata,
55 clk_modules_hw_auto_sata, 55 clk_modules_hw_auto_sata,
56 clk_modules_explicit_en_sata, 56 clk_modules_explicit_en_sata,
57 0); 57 0);
58 58
59 /* Enable optional functional clock for SATA */ 59 /* Enable optional functional clock for SATA */
60 setbits_le32((*prcm)->cm_l3init_sata_clkctrl, 60 setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
61 SATA_CLKCTRL_OPTFCLKEN_MASK); 61 SATA_CLKCTRL_OPTFCLKEN_MASK);
62 62
63 sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata; 63 sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
64 64
65 /* Power up the PHY */ 65 /* Power up the PHY */
66 phy_pipe3_power_on(&sata_phy); 66 phy_pipe3_power_on(&sata_phy);
67 67
68 /* Enable SATA module, No Idle, No Standby */ 68 /* Enable SATA module, No Idle, No Standby */
69 val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO; 69 val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
70 writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG); 70 writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
71 71
72 ret = ahci_init(DWC_AHSATA_BASE); 72 ret = ahci_init(DWC_AHSATA_BASE);
73 scsi_scan(1); 73 scsi_scan(1);
74 74
75 return ret; 75 return ret;
76 } 76 }
77
78 /* On OMAP platforms SATA provides the SCSI subsystem */
79 void scsi_init(void)
80 {
81 init_sata(0);
82 }
77 83
board/ti/dra7xx/evm.c
Diff comments   View file @ 3160b1b
1 /* 1 /*
2 * (C) Copyright 2013 2 * (C) Copyright 2013
3 * Texas Instruments Incorporated, <www.ti.com> 3 * Texas Instruments Incorporated, <www.ti.com>
4 * 4 *
5 * Lokesh Vutla <lokeshvutla@ti.com> 5 * Lokesh Vutla <lokeshvutla@ti.com>
6 * 6 *
7 * Based on previous work by: 7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com> 8 * Aneesh V <aneesh@ti.com>
9 * Steve Sakoman <steve@sakoman.com> 9 * Steve Sakoman <steve@sakoman.com>
10 * 10 *
11 * SPDX-License-Identifier: GPL-2.0+ 11 * SPDX-License-Identifier: GPL-2.0+
12 */ 12 */
13 #include <common.h> 13 #include <common.h>
14 #include <palmas.h> 14 #include <palmas.h>
15 #include <sata.h> 15 #include <sata.h>
16 #include <asm/gpio.h> 16 #include <asm/gpio.h>
17 #include <asm/arch/gpio.h> 17 #include <asm/arch/gpio.h>
18 #include <asm/arch/sys_proto.h> 18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/mmc_host_def.h> 19 #include <asm/arch/mmc_host_def.h>
20 #include <asm/arch/sata.h> 20 #include <asm/arch/sata.h>
21 #include <environment.h> 21 #include <environment.h>
22 22
23 #include "mux_data.h" 23 #include "mux_data.h"
24 24
25 #ifdef CONFIG_DRIVER_TI_CPSW 25 #ifdef CONFIG_DRIVER_TI_CPSW
26 #include <cpsw.h> 26 #include <cpsw.h>
27 #endif 27 #endif
28 28
29 DECLARE_GLOBAL_DATA_PTR; 29 DECLARE_GLOBAL_DATA_PTR;
30 30
31 /* GPIO 7_11 */ 31 /* GPIO 7_11 */
32 #define GPIO_DDR_VTT_EN 203 32 #define GPIO_DDR_VTT_EN 203
33 33
34 const struct omap_sysinfo sysinfo = { 34 const struct omap_sysinfo sysinfo = {
35 "Board: DRA7xx\n" 35 "Board: DRA7xx\n"
36 }; 36 };
37 37
38 /* 38 /*
39 * Adjust I/O delays on the Tx control and data lines of each MAC port. This 39 * Adjust I/O delays on the Tx control and data lines of each MAC port. This
40 * is a workaround in order to work properly with the DP83865 PHYs on the EVM. 40 * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
41 * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we 41 * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
42 * essentially need to counteract the DRA7xx internal delay, and we do this 42 * essentially need to counteract the DRA7xx internal delay, and we do this
43 * by delaying the control and data lines. If not using this PHY, you probably 43 * by delaying the control and data lines. If not using this PHY, you probably
44 * don't need to do this stuff! 44 * don't need to do this stuff!
45 */ 45 */
46 static void dra7xx_adj_io_delay(const struct io_delay *io_dly) 46 static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
47 { 47 {
48 int i = 0; 48 int i = 0;
49 u32 reg_val; 49 u32 reg_val;
50 u32 delta; 50 u32 delta;
51 u32 coarse; 51 u32 coarse;
52 u32 fine; 52 u32 fine;
53 53
54 writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK); 54 writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
55 55
56 while(io_dly[i].addr) { 56 while(io_dly[i].addr) {
57 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK, 57 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
58 io_dly[i].addr); 58 io_dly[i].addr);
59 delta = io_dly[i].dly; 59 delta = io_dly[i].dly;
60 reg_val = readl(io_dly[i].addr) & 0x3ff; 60 reg_val = readl(io_dly[i].addr) & 0x3ff;
61 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F); 61 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
62 coarse = (coarse > 0x1F) ? (0x1F) : (coarse); 62 coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
63 fine = (reg_val & 0x1F) + (delta & 0x1F); 63 fine = (reg_val & 0x1F) + (delta & 0x1F);
64 fine = (fine > 0x1F) ? (0x1F) : (fine); 64 fine = (fine > 0x1F) ? (0x1F) : (fine);
65 reg_val = CFG_IO_DELAY_ACCESS_PATTERN | 65 reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
66 CFG_IO_DELAY_LOCK_MASK | 66 CFG_IO_DELAY_LOCK_MASK |
67 ((coarse << 5) | (fine)); 67 ((coarse << 5) | (fine));
68 writel(reg_val, io_dly[i].addr); 68 writel(reg_val, io_dly[i].addr);
69 i++; 69 i++;
70 } 70 }
71 71
72 writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK); 72 writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
73 } 73 }
74 74
75 /** 75 /**
76 * @brief board_init 76 * @brief board_init
77 * 77 *
78 * @return 0 78 * @return 0
79 */ 79 */
80 int board_init(void) 80 int board_init(void)
81 { 81 {
82 gpmc_init(); 82 gpmc_init();
83 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 83 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
84 84
85 return 0; 85 return 0;
86 } 86 }
87 87
88 int board_late_init(void) 88 int board_late_init(void)
89 { 89 {
90 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 90 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
91 if (omap_revision() == DRA722_ES1_0) 91 if (omap_revision() == DRA722_ES1_0)
92 setenv("board_name", "dra72x"); 92 setenv("board_name", "dra72x");
93 else 93 else
94 setenv("board_name", "dra7xx"); 94 setenv("board_name", "dra7xx");
95 #endif 95 #endif
96 init_sata(0);
97 return 0; 96 return 0;
98 } 97 }
99 98
100 /** 99 /**
101 * @brief misc_init_r - Configure EVM board specific configurations 100 * @brief misc_init_r - Configure EVM board specific configurations
102 * such as power configurations, ethernet initialization as phase2 of 101 * such as power configurations, ethernet initialization as phase2 of
103 * boot sequence 102 * boot sequence
104 * 103 *
105 * @return 0 104 * @return 0
106 */ 105 */
107 int misc_init_r(void) 106 int misc_init_r(void)
108 { 107 {
109 return 0; 108 return 0;
110 } 109 }
111 110
112 static void do_set_mux32(u32 base, 111 static void do_set_mux32(u32 base,
113 struct pad_conf_entry const *array, int size) 112 struct pad_conf_entry const *array, int size)
114 { 113 {
115 int i; 114 int i;
116 struct pad_conf_entry *pad = (struct pad_conf_entry *)array; 115 struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
117 116
118 for (i = 0; i < size; i++, pad++) 117 for (i = 0; i < size; i++, pad++)
119 writel(pad->val, base + pad->offset); 118 writel(pad->val, base + pad->offset);
120 } 119 }
121 120
122 void set_muxconf_regs_essential(void) 121 void set_muxconf_regs_essential(void)
123 { 122 {
124 do_set_mux32((*ctrl)->control_padconf_core_base, 123 do_set_mux32((*ctrl)->control_padconf_core_base,
125 core_padconf_array_essential, 124 core_padconf_array_essential,
126 sizeof(core_padconf_array_essential) / 125 sizeof(core_padconf_array_essential) /
127 sizeof(struct pad_conf_entry)); 126 sizeof(struct pad_conf_entry));
128 } 127 }
129 128
130 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 129 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
131 int board_mmc_init(bd_t *bis) 130 int board_mmc_init(bd_t *bis)
132 { 131 {
133 omap_mmc_init(0, 0, 0, -1, -1); 132 omap_mmc_init(0, 0, 0, -1, -1);
134 omap_mmc_init(1, 0, 0, -1, -1); 133 omap_mmc_init(1, 0, 0, -1, -1);
135 return 0; 134 return 0;
136 } 135 }
137 #endif 136 #endif
138 137
139 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) 138 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
140 int spl_start_uboot(void) 139 int spl_start_uboot(void)
141 { 140 {
142 /* break into full u-boot on 'c' */ 141 /* break into full u-boot on 'c' */
143 if (serial_tstc() && serial_getc() == 'c') 142 if (serial_tstc() && serial_getc() == 'c')
144 return 1; 143 return 1;
145 144
146 #ifdef CONFIG_SPL_ENV_SUPPORT 145 #ifdef CONFIG_SPL_ENV_SUPPORT
147 env_init(); 146 env_init();
148 env_relocate_spec(); 147 env_relocate_spec();
149 if (getenv_yesno("boot_os") != 1) 148 if (getenv_yesno("boot_os") != 1)
150 return 1; 149 return 1;
151 #endif 150 #endif
152 151
153 return 0; 152 return 0;
154 } 153 }
155 #endif 154 #endif
156 155
157 #ifdef CONFIG_DRIVER_TI_CPSW 156 #ifdef CONFIG_DRIVER_TI_CPSW
158 157
159 /* Delay value to add to calibrated value */ 158 /* Delay value to add to calibrated value */
160 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) 159 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
161 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) 160 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
162 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) 161 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
163 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) 162 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
164 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) 163 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
165 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) 164 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
166 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) 165 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
167 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) 166 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
168 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) 167 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
169 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) 168 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
170 169
171 extern u32 *const omap_si_rev; 170 extern u32 *const omap_si_rev;
172 171
173 static void cpsw_control(int enabled) 172 static void cpsw_control(int enabled)
174 { 173 {
175 /* VTP can be added here */ 174 /* VTP can be added here */
176 175
177 return; 176 return;
178 } 177 }
179 178
180 static struct cpsw_slave_data cpsw_slaves[] = { 179 static struct cpsw_slave_data cpsw_slaves[] = {
181 { 180 {
182 .slave_reg_ofs = 0x208, 181 .slave_reg_ofs = 0x208,
183 .sliver_reg_ofs = 0xd80, 182 .sliver_reg_ofs = 0xd80,
184 .phy_addr = 2, 183 .phy_addr = 2,
185 }, 184 },
186 { 185 {
187 .slave_reg_ofs = 0x308, 186 .slave_reg_ofs = 0x308,
188 .sliver_reg_ofs = 0xdc0, 187 .sliver_reg_ofs = 0xdc0,
189 .phy_addr = 3, 188 .phy_addr = 3,
190 }, 189 },
191 }; 190 };
192 191
193 static struct cpsw_platform_data cpsw_data = { 192 static struct cpsw_platform_data cpsw_data = {
194 .mdio_base = CPSW_MDIO_BASE, 193 .mdio_base = CPSW_MDIO_BASE,
195 .cpsw_base = CPSW_BASE, 194 .cpsw_base = CPSW_BASE,
196 .mdio_div = 0xff, 195 .mdio_div = 0xff,
197 .channels = 8, 196 .channels = 8,
198 .cpdma_reg_ofs = 0x800, 197 .cpdma_reg_ofs = 0x800,
199 .slaves = 2, 198 .slaves = 2,
200 .slave_data = cpsw_slaves, 199 .slave_data = cpsw_slaves,
201 .ale_reg_ofs = 0xd00, 200 .ale_reg_ofs = 0xd00,
202 .ale_entries = 1024, 201 .ale_entries = 1024,
203 .host_port_reg_ofs = 0x108, 202 .host_port_reg_ofs = 0x108,
204 .hw_stats_reg_ofs = 0x900, 203 .hw_stats_reg_ofs = 0x900,
205 .bd_ram_ofs = 0x2000, 204 .bd_ram_ofs = 0x2000,
206 .mac_control = (1 << 5), 205 .mac_control = (1 << 5),
207 .control = cpsw_control, 206 .control = cpsw_control,
208 .host_port_num = 0, 207 .host_port_num = 0,
209 .version = CPSW_CTRL_VERSION_2, 208 .version = CPSW_CTRL_VERSION_2,
210 }; 209 };
211 210
212 int board_eth_init(bd_t *bis) 211 int board_eth_init(bd_t *bis)
213 { 212 {
214 int ret; 213 int ret;
215 uint8_t mac_addr[6]; 214 uint8_t mac_addr[6];
216 uint32_t mac_hi, mac_lo; 215 uint32_t mac_hi, mac_lo;
217 uint32_t ctrl_val; 216 uint32_t ctrl_val;
218 const struct io_delay io_dly[] = { 217 const struct io_delay io_dly[] = {
219 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL}, 218 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
220 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL}, 219 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
221 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL}, 220 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
222 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL}, 221 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
223 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL}, 222 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
224 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL}, 223 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
225 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL}, 224 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
226 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL}, 225 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
227 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL}, 226 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
228 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL}, 227 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
229 {0} 228 {0}
230 }; 229 };
231 230
232 /* Adjust IO delay for RGMII tx path */ 231 /* Adjust IO delay for RGMII tx path */
233 dra7xx_adj_io_delay(io_dly); 232 dra7xx_adj_io_delay(io_dly);
234 233
235 /* try reading mac address from efuse */ 234 /* try reading mac address from efuse */
236 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 235 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
237 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 236 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
238 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 237 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
239 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 238 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
240 mac_addr[2] = mac_hi & 0xFF; 239 mac_addr[2] = mac_hi & 0xFF;
241 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 240 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
242 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 241 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
243 mac_addr[5] = mac_lo & 0xFF; 242 mac_addr[5] = mac_lo & 0xFF;
244 243
245 if (!getenv("ethaddr")) { 244 if (!getenv("ethaddr")) {
246 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 245 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
247 246
248 if (is_valid_ether_addr(mac_addr)) 247 if (is_valid_ether_addr(mac_addr))
249 eth_setenv_enetaddr("ethaddr", mac_addr); 248 eth_setenv_enetaddr("ethaddr", mac_addr);
250 } 249 }
251 250
252 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 251 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
253 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 252 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
254 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 253 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
255 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 254 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
256 mac_addr[2] = mac_hi & 0xFF; 255 mac_addr[2] = mac_hi & 0xFF;
257 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 256 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
258 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 257 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
259 mac_addr[5] = mac_lo & 0xFF; 258 mac_addr[5] = mac_lo & 0xFF;
260 259
261 if (!getenv("eth1addr")) { 260 if (!getenv("eth1addr")) {
262 if (is_valid_ether_addr(mac_addr)) 261 if (is_valid_ether_addr(mac_addr))
263 eth_setenv_enetaddr("eth1addr", mac_addr); 262 eth_setenv_enetaddr("eth1addr", mac_addr);
264 } 263 }
265 264
266 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 265 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
267 ctrl_val |= 0x22; 266 ctrl_val |= 0x22;
268 writel(ctrl_val, (*ctrl)->control_core_control_io1); 267 writel(ctrl_val, (*ctrl)->control_core_control_io1);
269 268
270 if (*omap_si_rev == DRA722_ES1_0) 269 if (*omap_si_rev == DRA722_ES1_0)
271 cpsw_data.active_slave = 1; 270 cpsw_data.active_slave = 1;
272 271
273 ret = cpsw_register(&cpsw_data); 272 ret = cpsw_register(&cpsw_data);
274 if (ret < 0) 273 if (ret < 0)
275 printf("Error %d registering CPSW switch\n", ret); 274 printf("Error %d registering CPSW switch\n", ret);
276 275
277 return ret; 276 return ret;
278 } 277 }
279 #endif 278 #endif
280 279
281 #ifdef CONFIG_BOARD_EARLY_INIT_F 280 #ifdef CONFIG_BOARD_EARLY_INIT_F
282 /* VTT regulator enable */ 281 /* VTT regulator enable */
283 static inline void vtt_regulator_enable(void) 282 static inline void vtt_regulator_enable(void)
284 { 283 {
285 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 284 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
286 return; 285 return;
287 286
288 /* Do not enable VTT for DRA722 */ 287 /* Do not enable VTT for DRA722 */
289 if (omap_revision() == DRA722_ES1_0) 288 if (omap_revision() == DRA722_ES1_0)
290 return; 289 return;
291 290
292 /* 291 /*
293 * EVM Rev G and later use gpio7_11 for DDR3 termination. 292 * EVM Rev G and later use gpio7_11 for DDR3 termination.
294 * This is safe enough to do on older revs. 293 * This is safe enough to do on older revs.
295 */ 294 */
296 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 295 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
297 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 296 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
298 } 297 }
299 298
300 int board_early_init_f(void) 299 int board_early_init_f(void)
301 { 300 {
302 vtt_regulator_enable(); 301 vtt_regulator_enable();
303 return 0; 302 return 0;
304 } 303 }
305 #endif 304 #endif
306 305
board/ti/omap5_uevm/evm.c
Diff comments   View file @ 3160b1b
1 /* 1 /*
2 * (C) Copyright 2010 2 * (C) Copyright 2010
3 * Texas Instruments Incorporated, <www.ti.com> 3 * Texas Instruments Incorporated, <www.ti.com>
4 * Aneesh V <aneesh@ti.com> 4 * Aneesh V <aneesh@ti.com>
5 * Steve Sakoman <steve@sakoman.com> 5 * Steve Sakoman <steve@sakoman.com>
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 #include <common.h> 9 #include <common.h>
10 #include <palmas.h> 10 #include <palmas.h>
11 #include <asm/arch/sys_proto.h> 11 #include <asm/arch/sys_proto.h>
12 #include <asm/arch/mmc_host_def.h> 12 #include <asm/arch/mmc_host_def.h>
13 #include <tca642x.h> 13 #include <tca642x.h>
14 14
15 #include "mux_data.h" 15 #include "mux_data.h"
16 16
17 #if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP) 17 #if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
18 #include <sata.h> 18 #include <sata.h>
19 #include <usb.h> 19 #include <usb.h>
20 #include <asm/gpio.h> 20 #include <asm/gpio.h>
21 #include <asm/arch/clock.h> 21 #include <asm/arch/clock.h>
22 #include <asm/arch/ehci.h> 22 #include <asm/arch/ehci.h>
23 #include <asm/ehci-omap.h> 23 #include <asm/ehci-omap.h>
24 #include <asm/arch/sata.h> 24 #include <asm/arch/sata.h>
25 25
26 #define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000) 26 #define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
27 #define DIE_ID_REG_OFFSET 0x200 27 #define DIE_ID_REG_OFFSET 0x200
28 28
29 #endif 29 #endif
30 30
31 DECLARE_GLOBAL_DATA_PTR; 31 DECLARE_GLOBAL_DATA_PTR;
32 32
33 const struct omap_sysinfo sysinfo = { 33 const struct omap_sysinfo sysinfo = {
34 "Board: OMAP5432 uEVM\n" 34 "Board: OMAP5432 uEVM\n"
35 }; 35 };
36 36
37 /** 37 /**
38 * @brief tca642x_init - uEVM default values for the GPIO expander 38 * @brief tca642x_init - uEVM default values for the GPIO expander
39 * input reg, output reg, polarity reg, configuration reg 39 * input reg, output reg, polarity reg, configuration reg
40 */ 40 */
41 struct tca642x_bank_info tca642x_init[] = { 41 struct tca642x_bank_info tca642x_init[] = {
42 { .input_reg = 0x00, 42 { .input_reg = 0x00,
43 .output_reg = 0x04, 43 .output_reg = 0x04,
44 .polarity_reg = 0x00, 44 .polarity_reg = 0x00,
45 .configuration_reg = 0x80 }, 45 .configuration_reg = 0x80 },
46 { .input_reg = 0x00, 46 { .input_reg = 0x00,
47 .output_reg = 0x00, 47 .output_reg = 0x00,
48 .polarity_reg = 0x00, 48 .polarity_reg = 0x00,
49 .configuration_reg = 0xff }, 49 .configuration_reg = 0xff },
50 { .input_reg = 0x00, 50 { .input_reg = 0x00,
51 .output_reg = 0x00, 51 .output_reg = 0x00,
52 .polarity_reg = 0x00, 52 .polarity_reg = 0x00,
53 .configuration_reg = 0x40 }, 53 .configuration_reg = 0x40 },
54 }; 54 };
55 55
56 /** 56 /**
57 * @brief board_init 57 * @brief board_init
58 * 58 *
59 * @return 0 59 * @return 0
60 */ 60 */
61 int board_init(void) 61 int board_init(void)
62 { 62 {
63 gpmc_init(); 63 gpmc_init();
64 gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM; 64 gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
65 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 65 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
66 66
67 tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init); 67 tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);
68 68
69 return 0; 69 return 0;
70 } 70 }
71 71
72 int board_late_init(void)
73 {
74 init_sata(0);
75 return 0;
76 }
77
78 int board_eth_init(bd_t *bis) 72 int board_eth_init(bd_t *bis)
79 { 73 {
80 return 0; 74 return 0;
81 } 75 }
82 76
83 #if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP) 77 #if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
84 static void enable_host_clocks(void) 78 static void enable_host_clocks(void)
85 { 79 {
86 int auxclk; 80 int auxclk;
87 int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK | 81 int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
88 OPTFCLKEN_HSIC480M_P3_CLK | 82 OPTFCLKEN_HSIC480M_P3_CLK |
89 OPTFCLKEN_HSIC60M_P2_CLK | 83 OPTFCLKEN_HSIC60M_P2_CLK |
90 OPTFCLKEN_HSIC480M_P2_CLK | 84 OPTFCLKEN_HSIC480M_P2_CLK |
91 OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK); 85 OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
92 86
93 /* Enable port 2 and 3 clocks*/ 87 /* Enable port 2 and 3 clocks*/
94 setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val); 88 setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
95 89
96 /* Enable port 2 and 3 usb host ports tll clocks*/ 90 /* Enable port 2 and 3 usb host ports tll clocks*/
97 setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, 91 setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
98 (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE)); 92 (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
99 #ifdef CONFIG_USB_XHCI_OMAP 93 #ifdef CONFIG_USB_XHCI_OMAP
100 /* Enable the USB OTG Super speed clocks */ 94 /* Enable the USB OTG Super speed clocks */
101 setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, 95 setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
102 (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW)); 96 (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW));
103 #endif 97 #endif
104 98
105 auxclk = readl((*prcm)->scrm_auxclk1); 99 auxclk = readl((*prcm)->scrm_auxclk1);
106 /* Request auxilary clock */ 100 /* Request auxilary clock */
107 auxclk |= AUXCLK_ENABLE_MASK; 101 auxclk |= AUXCLK_ENABLE_MASK;
108 writel(auxclk, (*prcm)->scrm_auxclk1); 102 writel(auxclk, (*prcm)->scrm_auxclk1);
109 } 103 }
110 #endif 104 #endif
111 105
112 /** 106 /**
113 * @brief misc_init_r - Configure EVM board specific configurations 107 * @brief misc_init_r - Configure EVM board specific configurations
114 * such as power configurations, ethernet initialization as phase2 of 108 * such as power configurations, ethernet initialization as phase2 of
115 * boot sequence 109 * boot sequence
116 * 110 *
117 * @return 0 111 * @return 0
118 */ 112 */
119 int misc_init_r(void) 113 int misc_init_r(void)
120 { 114 {
121 int reg; 115 int reg;
122 u32 id[4]; 116 u32 id[4];
123 117
124 #ifdef CONFIG_PALMAS_POWER 118 #ifdef CONFIG_PALMAS_POWER
125 palmas_init_settings(); 119 palmas_init_settings();
126 #endif 120 #endif
127 121
128 reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET; 122 reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
129 123
130 id[0] = readl(reg); 124 id[0] = readl(reg);
131 id[1] = readl(reg + 0x8); 125 id[1] = readl(reg + 0x8);
132 id[2] = readl(reg + 0xC); 126 id[2] = readl(reg + 0xC);
133 id[3] = readl(reg + 0x10); 127 id[3] = readl(reg + 0x10);
134 usb_fake_mac_from_die_id(id); 128 usb_fake_mac_from_die_id(id);
135 129
136 return 0; 130 return 0;
137 } 131 }
138 132
139 void set_muxconf_regs_essential(void) 133 void set_muxconf_regs_essential(void)
140 { 134 {
141 do_set_mux((*ctrl)->control_padconf_core_base, 135 do_set_mux((*ctrl)->control_padconf_core_base,
142 core_padconf_array_essential, 136 core_padconf_array_essential,
143 sizeof(core_padconf_array_essential) / 137 sizeof(core_padconf_array_essential) /
144 sizeof(struct pad_conf_entry)); 138 sizeof(struct pad_conf_entry));
145 139
146 do_set_mux((*ctrl)->control_padconf_wkup_base, 140 do_set_mux((*ctrl)->control_padconf_wkup_base,
147 wkup_padconf_array_essential, 141 wkup_padconf_array_essential,
148 sizeof(wkup_padconf_array_essential) / 142 sizeof(wkup_padconf_array_essential) /
149 sizeof(struct pad_conf_entry)); 143 sizeof(struct pad_conf_entry));
150 } 144 }
151 145
152 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 146 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
153 int board_mmc_init(bd_t *bis) 147 int board_mmc_init(bd_t *bis)
154 { 148 {
155 omap_mmc_init(0, 0, 0, -1, -1); 149 omap_mmc_init(0, 0, 0, -1, -1);
156 omap_mmc_init(1, 0, 0, -1, -1); 150 omap_mmc_init(1, 0, 0, -1, -1);
157 return 0; 151 return 0;
158 } 152 }
159 #endif 153 #endif
160 154
161 #ifdef CONFIG_USB_EHCI 155 #ifdef CONFIG_USB_EHCI
162 static struct omap_usbhs_board_data usbhs_bdata = { 156 static struct omap_usbhs_board_data usbhs_bdata = {
163 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, 157 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
164 .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC, 158 .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
165 .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC, 159 .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
166 }; 160 };
167 161
168 int ehci_hcd_init(int index, enum usb_init_type init, 162 int ehci_hcd_init(int index, enum usb_init_type init,
169 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 163 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
170 { 164 {
171 int ret; 165 int ret;
172 166
173 enable_host_clocks(); 167 enable_host_clocks();
174 168
175 ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 169 ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
176 if (ret < 0) { 170 if (ret < 0) {
177 puts("Failed to initialize ehci\n"); 171 puts("Failed to initialize ehci\n");
178 return ret; 172 return ret;
179 } 173 }
180 174
181 return 0; 175 return 0;
182 } 176 }
183 177
184 int ehci_hcd_stop(void) 178 int ehci_hcd_stop(void)
185 { 179 {
186 int ret; 180 int ret;
187 181
188 ret = omap_ehci_hcd_stop(); 182 ret = omap_ehci_hcd_stop();
189 return ret; 183 return ret;
190 } 184 }
191 185
192 void usb_hub_reset_devices(int port) 186 void usb_hub_reset_devices(int port)
193 { 187 {
194 /* The LAN9730 needs to be reset after the port power has been set. */ 188 /* The LAN9730 needs to be reset after the port power has been set. */
195 if (port == 3) { 189 if (port == 3) {
196 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0); 190 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
197 udelay(10); 191 udelay(10);
198 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1); 192 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
199 } 193 }
200 } 194 }
201 #endif 195 #endif
202 196
203 #ifdef CONFIG_USB_XHCI_OMAP 197 #ifdef CONFIG_USB_XHCI_OMAP
204 /** 198 /**
205 * @brief board_usb_init - Configure EVM board specific configurations 199 * @brief board_usb_init - Configure EVM board specific configurations
206 * for the LDO's and clocks for the USB blocks. 200 * for the LDO's and clocks for the USB blocks.
207 * 201 *
208 * @return 0 202 * @return 0
209 */ 203 */
210 int board_usb_init(int index, enum usb_init_type init) 204 int board_usb_init(int index, enum usb_init_type init)
211 { 205 {
212 int ret; 206 int ret;
213 #ifdef CONFIG_PALMAS_USB_SS_PWR 207 #ifdef CONFIG_PALMAS_USB_SS_PWR
214 ret = palmas_enable_ss_ldo(); 208 ret = palmas_enable_ss_ldo();
215 #endif 209 #endif
216 210
217 enable_host_clocks(); 211 enable_host_clocks();
218 212
219 return 0; 213 return 0;
220 } 214 }
221 #endif 215 #endif
222 216
include/configs/omap5_uevm.h
Diff comments   View file @ 3160b1b
1 /* 1 /*
2 * (C) Copyright 2013 2 * (C) Copyright 2013
3 * Texas Instruments Incorporated. 3 * Texas Instruments Incorporated.
4 * Sricharan R <r.sricharan@ti.com> 4 * Sricharan R <r.sricharan@ti.com>
5 * 5 *
6 * Configuration settings for the TI EVM5430 board. 6 * Configuration settings for the TI EVM5430 board.
7 * See ti_omap5_common.h for omap5 common settings. 7 * See ti_omap5_common.h for omap5 common settings.
8 * 8 *
9 * SPDX-License-Identifier: GPL-2.0+ 9 * SPDX-License-Identifier: GPL-2.0+
10 */ 10 */
11 11
12 #ifndef __CONFIG_OMAP5_EVM_H 12 #ifndef __CONFIG_OMAP5_EVM_H
13 #define __CONFIG_OMAP5_EVM_H 13 #define __CONFIG_OMAP5_EVM_H
14 14
15 /* Define the default GPT table for eMMC */ 15 /* Define the default GPT table for eMMC */
16 #define PARTS_DEFAULT \ 16 #define PARTS_DEFAULT \
17 "uuid_disk=${uuid_gpt_disk};" \ 17 "uuid_disk=${uuid_gpt_disk};" \
18 "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" 18 "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
19 19
20 #include <configs/ti_omap5_common.h> 20 #include <configs/ti_omap5_common.h>
21 21
22 #define CONFIG_CONS_INDEX 3 22 #define CONFIG_CONS_INDEX 3
23 #define CONFIG_SYS_NS16550_COM3 UART3_BASE 23 #define CONFIG_SYS_NS16550_COM3 UART3_BASE
24 #define CONFIG_BAUDRATE 115200 24 #define CONFIG_BAUDRATE 115200
25 25
26 /* MMC ENV related defines */ 26 /* MMC ENV related defines */
27 #define CONFIG_ENV_IS_IN_MMC 27 #define CONFIG_ENV_IS_IN_MMC
28 #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ 28 #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
29 #define CONFIG_ENV_SIZE (128 << 10) 29 #define CONFIG_ENV_SIZE (128 << 10)
30 #define CONFIG_ENV_OFFSET 0xE0000 30 #define CONFIG_ENV_OFFSET 0xE0000
31 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 31 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
32 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 32 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
33 #define CONFIG_CMD_SAVEENV 33 #define CONFIG_CMD_SAVEENV
34 34
35 /* Enhance our eMMC support / experience. */ 35 /* Enhance our eMMC support / experience. */
36 #define CONFIG_CMD_GPT 36 #define CONFIG_CMD_GPT
37 #define CONFIG_EFI_PARTITION 37 #define CONFIG_EFI_PARTITION
38 #define CONFIG_PARTITION_UUIDS 38 #define CONFIG_PARTITION_UUIDS
39 #define CONFIG_CMD_PART 39 #define CONFIG_CMD_PART
40 #define CONFIG_HSMMC2_8BIT 40 #define CONFIG_HSMMC2_8BIT
41 #define CONFIG_SUPPORT_EMMC_BOOT 41 #define CONFIG_SUPPORT_EMMC_BOOT
42 42
43 /* Required support for the TCA642X GPIO we have on the uEVM */ 43 /* Required support for the TCA642X GPIO we have on the uEVM */
44 #define CONFIG_TCA642X 44 #define CONFIG_TCA642X
45 #define CONFIG_CMD_TCA642X 45 #define CONFIG_CMD_TCA642X
46 #define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4 46 #define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4
47 #define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 47 #define CONFIG_SYS_I2C_TCA642X_ADDR 0x22
48 48
49 /* USB UHH support options */ 49 /* USB UHH support options */
50 #define CONFIG_CMD_USB 50 #define CONFIG_CMD_USB
51 #define CONFIG_USB_HOST 51 #define CONFIG_USB_HOST
52 #define CONFIG_USB_EHCI 52 #define CONFIG_USB_EHCI
53 #define CONFIG_USB_EHCI_OMAP 53 #define CONFIG_USB_EHCI_OMAP
54 #define CONFIG_USB_STORAGE 54 #define CONFIG_USB_STORAGE
55 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 55 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
56 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 56 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
57 57
58 #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80 58 #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80
59 #define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79 59 #define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79
60 60
61 /* Enabled commands */ 61 /* Enabled commands */
62 #define CONFIG_CMD_DHCP /* DHCP Support */ 62 #define CONFIG_CMD_DHCP /* DHCP Support */
63 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 63 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
64 #define CONFIG_CMD_NFS /* NFS support */ 64 #define CONFIG_CMD_NFS /* NFS support */
65 65
66 /* USB Networking options */ 66 /* USB Networking options */
67 #define CONFIG_USB_HOST_ETHER 67 #define CONFIG_USB_HOST_ETHER
68 #define CONFIG_USB_ETHER_SMSC95XX 68 #define CONFIG_USB_ETHER_SMSC95XX
69 69
70 #define CONSOLEDEV "ttyO2" 70 #define CONSOLEDEV "ttyO2"
71 71
72 /* Max time to hold reset on this board, see doc/README.omap-reset-time */ 72 /* Max time to hold reset on this board, see doc/README.omap-reset-time */
73 #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 73 #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296
74 74
75 #define CONFIG_BOARD_LATE_INIT
76 #define CONFIG_CMD_SCSI 75 #define CONFIG_CMD_SCSI
77 #define CONFIG_LIBATA 76 #define CONFIG_LIBATA
78 #define CONFIG_SCSI_AHCI 77 #define CONFIG_SCSI_AHCI
79 #define CONFIG_SCSI_AHCI_PLAT 78 #define CONFIG_SCSI_AHCI_PLAT
80 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 79 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
81 #define CONFIG_SYS_SCSI_MAX_LUN 1 80 #define CONFIG_SYS_SCSI_MAX_LUN 1
82 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 81 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
83 CONFIG_SYS_SCSI_MAX_LUN) 82 CONFIG_SYS_SCSI_MAX_LUN)
84 83
85 #endif /* __CONFIG_OMAP5_EVM_H */ 84 #endif /* __CONFIG_OMAP5_EVM_H */
86 85