Commit 31eadc4bbd3a46d7509369b14bc9add9f8f3a810
1 parent
c9f0f0e174
Exists in
smarc-imx_v2014.04_3.14.28_1.0.0_ga
Add uenvcmd parameters
Showing 1 changed file with 4 additions and 4 deletions Inline Diff
board/embedian/smarcfimx6/smarcfimx6.c
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2012-2014 Freescale Semiconductor, Inc. | 2 | * Copyright (C) 2012-2014 Freescale Semiconductor, Inc. |
| 3 | * | 3 | * |
| 4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> | 4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> |
| 5 | * | 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | #include <common.h> | 9 | #include <common.h> |
| 10 | #include <asm/io.h> | 10 | #include <asm/io.h> |
| 11 | #include <asm/arch/clock.h> | 11 | #include <asm/arch/clock.h> |
| 12 | #include <asm/arch/imx-regs.h> | 12 | #include <asm/arch/imx-regs.h> |
| 13 | #include <asm/arch/crm_regs.h> | 13 | #include <asm/arch/crm_regs.h> |
| 14 | #include <asm/arch/iomux.h> | 14 | #include <asm/arch/iomux.h> |
| 15 | #include <asm/arch/mx6-pins.h> | 15 | #include <asm/arch/mx6-pins.h> |
| 16 | #include <asm/errno.h> | 16 | #include <asm/errno.h> |
| 17 | #include <asm/gpio.h> | 17 | #include <asm/gpio.h> |
| 18 | #include <asm/imx-common/iomux-v3.h> | 18 | #include <asm/imx-common/iomux-v3.h> |
| 19 | #include <asm/imx-common/boot_mode.h> | 19 | #include <asm/imx-common/boot_mode.h> |
| 20 | #include <mmc.h> | 20 | #include <mmc.h> |
| 21 | #include <fsl_esdhc.h> | 21 | #include <fsl_esdhc.h> |
| 22 | #include <miiphy.h> | 22 | #include <miiphy.h> |
| 23 | #include <netdev.h> | 23 | #include <netdev.h> |
| 24 | #include <phy.h> | 24 | #include <phy.h> |
| 25 | 25 | ||
| 26 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) | 26 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) |
| 27 | #include <lcd.h> | 27 | #include <lcd.h> |
| 28 | #include <mxc_epdc_fb.h> | 28 | #include <mxc_epdc_fb.h> |
| 29 | #endif | 29 | #endif |
| 30 | #include <asm/arch/mxc_hdmi.h> | 30 | #include <asm/arch/mxc_hdmi.h> |
| 31 | #include <linux/fb.h> | 31 | #include <linux/fb.h> |
| 32 | #include <ipu_pixfmt.h> | 32 | #include <ipu_pixfmt.h> |
| 33 | #include <asm/io.h> | 33 | #include <asm/io.h> |
| 34 | #include <asm/arch/sys_proto.h> | 34 | #include <asm/arch/sys_proto.h> |
| 35 | #include <pwm.h> | 35 | #include <pwm.h> |
| 36 | #ifdef CONFIG_SYS_I2C_MXC | 36 | #ifdef CONFIG_SYS_I2C_MXC |
| 37 | #include <i2c.h> | 37 | #include <i2c.h> |
| 38 | #include <asm/imx-common/mxc_i2c.h> | 38 | #include <asm/imx-common/mxc_i2c.h> |
| 39 | #endif | 39 | #endif |
| 40 | #include "smarcfimx6.h" | 40 | #include "smarcfimx6.h" |
| 41 | #ifdef CONFIG_CMD_SATA | 41 | #ifdef CONFIG_CMD_SATA |
| 42 | #include <asm/imx-common/sata.h> | 42 | #include <asm/imx-common/sata.h> |
| 43 | #endif | 43 | #endif |
| 44 | #ifdef CONFIG_FASTBOOT | 44 | #ifdef CONFIG_FASTBOOT |
| 45 | #include <fastboot.h> | 45 | #include <fastboot.h> |
| 46 | #ifdef CONFIG_ANDROID_RECOVERY | 46 | #ifdef CONFIG_ANDROID_RECOVERY |
| 47 | #include <recovery.h> | 47 | #include <recovery.h> |
| 48 | #endif | 48 | #endif |
| 49 | #endif /*CONFIG_FASTBOOT*/ | 49 | #endif /*CONFIG_FASTBOOT*/ |
| 50 | 50 | ||
| 51 | DECLARE_GLOBAL_DATA_PTR; | 51 | DECLARE_GLOBAL_DATA_PTR; |
| 52 | 52 | ||
| 53 | #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ | 53 | #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| 54 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ | 54 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ |
| 55 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | 55 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| 56 | 56 | ||
| 57 | #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ | 57 | #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ |
| 58 | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ | 58 | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ |
| 59 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | 59 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| 60 | 60 | ||
| 61 | #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ | 61 | #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| 62 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) | 62 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
| 63 | 63 | ||
| 64 | #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ | 64 | #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ |
| 65 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) | 65 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
| 66 | 66 | ||
| 67 | #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_HIGH | \ | 67 | #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_HIGH | \ |
| 68 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) | 68 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
| 69 | 69 | ||
| 70 | #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | 70 | #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| 71 | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ | 71 | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| 72 | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ | 72 | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ |
| 73 | PAD_CTL_ODE | PAD_CTL_SRE_FAST) | 73 | PAD_CTL_ODE | PAD_CTL_SRE_FAST) |
| 74 | 74 | ||
| 75 | #define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ | 75 | #define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ |
| 76 | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) | 76 | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
| 77 | 77 | ||
| 78 | #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ | 78 | #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ |
| 79 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ | 79 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ |
| 80 | PAD_CTL_SRE_SLOW) | 80 | PAD_CTL_SRE_SLOW) |
| 81 | 81 | ||
| 82 | #ifdef CONFIG_SYS_I2C_MXC | 82 | #ifdef CONFIG_SYS_I2C_MXC |
| 83 | #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) | 83 | #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
| 84 | 84 | ||
| 85 | #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) | 85 | #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) |
| 86 | 86 | ||
| 87 | /* | 87 | /* |
| 88 | * Read header information from EEPROM into global structure. | 88 | * Read header information from EEPROM into global structure. |
| 89 | */ | 89 | */ |
| 90 | static int read_eeprom(struct smarcfimx6_id *header) | 90 | static int read_eeprom(struct smarcfimx6_id *header) |
| 91 | { | 91 | { |
| 92 | /* Check if baseboard eeprom is available */ | 92 | /* Check if baseboard eeprom is available */ |
| 93 | if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { | 93 | if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { |
| 94 | puts("Could not probe the EEPROM; something fundamentally " | 94 | puts("Could not probe the EEPROM; something fundamentally " |
| 95 | "wrong on the I2C bus.\n"); | 95 | "wrong on the I2C bus.\n"); |
| 96 | return -ENODEV; | 96 | return -ENODEV; |
| 97 | } | 97 | } |
| 98 | 98 | ||
| 99 | /* read the eeprom using i2c */ | 99 | /* read the eeprom using i2c */ |
| 100 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, | 100 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, |
| 101 | sizeof(struct smarcfimx6_id))) { | 101 | sizeof(struct smarcfimx6_id))) { |
| 102 | puts("Could not read the EEPROM; something fundamentally" | 102 | puts("Could not read the EEPROM; something fundamentally" |
| 103 | " wrong on the I2C bus.\n"); | 103 | " wrong on the I2C bus.\n"); |
| 104 | return -EIO; | 104 | return -EIO; |
| 105 | } | 105 | } |
| 106 | 106 | ||
| 107 | if (header->magic != 0xEE3355AA) { | 107 | if (header->magic != 0xEE3355AA) { |
| 108 | /* | 108 | /* |
| 109 | * read the eeprom using i2c again, | 109 | * read the eeprom using i2c again, |
| 110 | * but use only a 1 byte address | 110 | * but use only a 1 byte address |
| 111 | */ | 111 | */ |
| 112 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, | 112 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, |
| 113 | sizeof(struct smarcfimx6_id))) { | 113 | sizeof(struct smarcfimx6_id))) { |
| 114 | puts("Could not read the EEPROM; something " | 114 | puts("Could not read the EEPROM; something " |
| 115 | "fundamentally wrong on the I2C bus.\n"); | 115 | "fundamentally wrong on the I2C bus.\n"); |
| 116 | return -EIO; | 116 | return -EIO; |
| 117 | } | 117 | } |
| 118 | 118 | ||
| 119 | if (header->magic != 0xEE3355AA) { | 119 | if (header->magic != 0xEE3355AA) { |
| 120 | printf("Incorrect magic number (0x%x) in EEPROM\n", | 120 | printf("Incorrect magic number (0x%x) in EEPROM\n", |
| 121 | header->magic); | 121 | header->magic); |
| 122 | return -EINVAL; | 122 | return -EINVAL; |
| 123 | } | 123 | } |
| 124 | } | 124 | } |
| 125 | 125 | ||
| 126 | return 0; | 126 | return 0; |
| 127 | } | 127 | } |
| 128 | 128 | ||
| 129 | /*I2C1 I2C_PM*/ | 129 | /*I2C1 I2C_PM*/ |
| 130 | struct i2c_pads_info i2c_pad_info1 = { | 130 | struct i2c_pads_info i2c_pad_info1 = { |
| 131 | .scl = { | 131 | .scl = { |
| 132 | .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, | 132 | .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, |
| 133 | .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, | 133 | .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, |
| 134 | .gp = IMX_GPIO_NR(3, 21) | 134 | .gp = IMX_GPIO_NR(3, 21) |
| 135 | }, | 135 | }, |
| 136 | .sda = { | 136 | .sda = { |
| 137 | .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, | 137 | .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, |
| 138 | .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, | 138 | .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, |
| 139 | .gp = IMX_GPIO_NR(3, 28) | 139 | .gp = IMX_GPIO_NR(3, 28) |
| 140 | } | 140 | } |
| 141 | }; | 141 | }; |
| 142 | 142 | ||
| 143 | /* I2C2 HDMI */ | 143 | /* I2C2 HDMI */ |
| 144 | struct i2c_pads_info i2c_pad_info2 = { | 144 | struct i2c_pads_info i2c_pad_info2 = { |
| 145 | .scl = { | 145 | .scl = { |
| 146 | .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, | 146 | .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, |
| 147 | .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, | 147 | .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, |
| 148 | .gp = IMX_GPIO_NR(4, 12) | 148 | .gp = IMX_GPIO_NR(4, 12) |
| 149 | }, | 149 | }, |
| 150 | .sda = { | 150 | .sda = { |
| 151 | .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, | 151 | .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, |
| 152 | .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, | 152 | .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, |
| 153 | .gp = IMX_GPIO_NR(4, 13) | 153 | .gp = IMX_GPIO_NR(4, 13) |
| 154 | } | 154 | } |
| 155 | }; | 155 | }; |
| 156 | 156 | ||
| 157 | /* I2C3 TCA9546APWR */ | 157 | /* I2C3 TCA9546APWR */ |
| 158 | struct i2c_pads_info i2c_pad_info3 = { | 158 | struct i2c_pads_info i2c_pad_info3 = { |
| 159 | .scl = { | 159 | .scl = { |
| 160 | .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, | 160 | .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, |
| 161 | .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, | 161 | .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, |
| 162 | .gp = IMX_GPIO_NR(3, 17) | 162 | .gp = IMX_GPIO_NR(3, 17) |
| 163 | }, | 163 | }, |
| 164 | .sda = { | 164 | .sda = { |
| 165 | .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, | 165 | .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, |
| 166 | .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, | 166 | .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, |
| 167 | .gp = IMX_GPIO_NR(3, 18) | 167 | .gp = IMX_GPIO_NR(3, 18) |
| 168 | } | 168 | } |
| 169 | }; | 169 | }; |
| 170 | #endif | 170 | #endif |
| 171 | 171 | ||
| 172 | int dram_init(void) | 172 | int dram_init(void) |
| 173 | { | 173 | { |
| 174 | 174 | ||
| 175 | gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); | 175 | gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); |
| 176 | 176 | ||
| 177 | return 0; | 177 | return 0; |
| 178 | } | 178 | } |
| 179 | 179 | ||
| 180 | /* SER0/UART1 */ | 180 | /* SER0/UART1 */ |
| 181 | iomux_v3_cfg_t const uart1_pads[] = { | 181 | iomux_v3_cfg_t const uart1_pads[] = { |
| 182 | MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | 182 | MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 183 | MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | 183 | MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 184 | MX6_PAD_EIM_D20__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | 184 | MX6_PAD_EIM_D20__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 185 | MX6_PAD_EIM_D19__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | 185 | MX6_PAD_EIM_D19__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 186 | }; | 186 | }; |
| 187 | 187 | ||
| 188 | /* SER1/UART2 */ | 188 | /* SER1/UART2 */ |
| 189 | iomux_v3_cfg_t const uart2_pads[] = { | 189 | iomux_v3_cfg_t const uart2_pads[] = { |
| 190 | MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | 190 | MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 191 | MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | 191 | MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 192 | }; | 192 | }; |
| 193 | 193 | ||
| 194 | /* SER2/UART4 */ | 194 | /* SER2/UART4 */ |
| 195 | iomux_v3_cfg_t const uart4_pads[] = { | 195 | iomux_v3_cfg_t const uart4_pads[] = { |
| 196 | MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | 196 | MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 197 | MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | 197 | MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 198 | MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | 198 | MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 199 | MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | 199 | MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 200 | }; | 200 | }; |
| 201 | 201 | ||
| 202 | /* SER3/UART5 Debug Port */ | 202 | /* SER3/UART5 Debug Port */ |
| 203 | iomux_v3_cfg_t const uart5_pads[] = { | 203 | iomux_v3_cfg_t const uart5_pads[] = { |
| 204 | MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | 204 | MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 205 | MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | 205 | MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 206 | }; | 206 | }; |
| 207 | 207 | ||
| 208 | iomux_v3_cfg_t const wdt_pads[] = { | 208 | iomux_v3_cfg_t const wdt_pads[] = { |
| 209 | MX6_PAD_EIM_D16__GPIO3_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), | 209 | MX6_PAD_EIM_D16__GPIO3_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 210 | }; | 210 | }; |
| 211 | 211 | ||
| 212 | iomux_v3_cfg_t const reset_out_pads[] = { | 212 | iomux_v3_cfg_t const reset_out_pads[] = { |
| 213 | MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), | 213 | MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 214 | }; | 214 | }; |
| 215 | 215 | ||
| 216 | iomux_v3_cfg_t const enet_pads[] = { | 216 | iomux_v3_cfg_t const enet_pads[] = { |
| 217 | MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), | 217 | MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 218 | MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), | 218 | MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 219 | MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), | 219 | MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 220 | MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), | 220 | MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 221 | MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), | 221 | MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 222 | MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), | 222 | MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 223 | MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), | 223 | MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 224 | MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), | 224 | MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 225 | MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), | 225 | MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 226 | MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), | 226 | MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 227 | MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), | 227 | MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 228 | MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), | 228 | MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 229 | MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), | 229 | MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 230 | MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), | 230 | MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 231 | MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), | 231 | MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 232 | }; | 232 | }; |
| 233 | 233 | ||
| 234 | static void setup_iomux_enet(void) | 234 | static void setup_iomux_enet(void) |
| 235 | { | 235 | { |
| 236 | imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); | 236 | imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); |
| 237 | gpio_direction_input(IMX_GPIO_NR(4, 11)); | 237 | gpio_direction_input(IMX_GPIO_NR(4, 11)); |
| 238 | } | 238 | } |
| 239 | 239 | ||
| 240 | /* SDIO */ | 240 | /* SDIO */ |
| 241 | iomux_v3_cfg_t const usdhc2_pads[] = { | 241 | iomux_v3_cfg_t const usdhc2_pads[] = { |
| 242 | MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 242 | MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 243 | MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 243 | MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 244 | MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 244 | MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 245 | MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 245 | MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 246 | MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 246 | MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 247 | MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 247 | MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 248 | MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ | 248 | MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
| 249 | MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ | 249 | MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ |
| 250 | MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), /* SDIO_PWR_EN */ | 250 | MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), /* SDIO_PWR_EN */ |
| 251 | }; | 251 | }; |
| 252 | 252 | ||
| 253 | /* SDMMC */ | 253 | /* SDMMC */ |
| 254 | iomux_v3_cfg_t const usdhc3_pads[] = { | 254 | iomux_v3_cfg_t const usdhc3_pads[] = { |
| 255 | MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 255 | MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 256 | MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 256 | MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 257 | MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 257 | MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 258 | MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 258 | MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 259 | MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 259 | MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 260 | MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 260 | MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 261 | MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 261 | MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 262 | }; | 262 | }; |
| 263 | 263 | ||
| 264 | /* eMMC */ | 264 | /* eMMC */ |
| 265 | iomux_v3_cfg_t const usdhc4_pads[] = { | 265 | iomux_v3_cfg_t const usdhc4_pads[] = { |
| 266 | MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 266 | MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 267 | MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 267 | MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 268 | MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 268 | MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 269 | MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 269 | MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 270 | MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 270 | MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 271 | MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 271 | MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 272 | MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 272 | MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 273 | MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 273 | MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 274 | MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 274 | MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 275 | MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 275 | MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 276 | }; | 276 | }; |
| 277 | 277 | ||
| 278 | #ifdef CONFIG_SYS_USE_SPINOR | 278 | #ifdef CONFIG_SYS_USE_SPINOR |
| 279 | /* SPI0 */ | 279 | /* SPI0 */ |
| 280 | iomux_v3_cfg_t const ecspi2_pads[] = { | 280 | iomux_v3_cfg_t const ecspi2_pads[] = { |
| 281 | MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), | 281 | MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 282 | MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), | 282 | MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 283 | MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), | 283 | MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 284 | MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/ | 284 | MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/ |
| 285 | MX6_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/ | 285 | MX6_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/ |
| 286 | MX6_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS3#*/ | 286 | MX6_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS3#*/ |
| 287 | }; | 287 | }; |
| 288 | 288 | ||
| 289 | static void setup_spinor(void) | 289 | static void setup_spinor(void) |
| 290 | { | 290 | { |
| 291 | imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); | 291 | imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); |
| 292 | } | 292 | } |
| 293 | #endif | 293 | #endif |
| 294 | 294 | ||
| 295 | /* SPI1 */ | 295 | /* SPI1 */ |
| 296 | iomux_v3_cfg_t const ecspi1_pads[] = { | 296 | iomux_v3_cfg_t const ecspi1_pads[] = { |
| 297 | MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), | 297 | MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 298 | MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), | 298 | MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 299 | MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), | 299 | MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 300 | MX6_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/ | 300 | MX6_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/ |
| 301 | MX6_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/ | 301 | MX6_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/ |
| 302 | }; | 302 | }; |
| 303 | 303 | ||
| 304 | iomux_v3_cfg_t const pcie_pads[] = { | 304 | iomux_v3_cfg_t const pcie_pads[] = { |
| 305 | MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe Present */ | 305 | MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe Present */ |
| 306 | MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ | 306 | MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ |
| 307 | MX6_PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe Clock Request */ | 307 | MX6_PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe Clock Request */ |
| 308 | }; | 308 | }; |
| 309 | 309 | ||
| 310 | static void setup_pcie(void) | 310 | static void setup_pcie(void) |
| 311 | { | 311 | { |
| 312 | imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); | 312 | imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); |
| 313 | gpio_direction_input(IMX_GPIO_NR(1, 16)); | 313 | gpio_direction_input(IMX_GPIO_NR(1, 16)); |
| 314 | gpio_direction_input(IMX_GPIO_NR(1, 17)); | 314 | gpio_direction_input(IMX_GPIO_NR(1, 17)); |
| 315 | gpio_direction_input(IMX_GPIO_NR(1, 19)); | 315 | gpio_direction_input(IMX_GPIO_NR(1, 19)); |
| 316 | gpio_direction_output(IMX_GPIO_NR(1,20), 0); | 316 | gpio_direction_output(IMX_GPIO_NR(1,20), 0); |
| 317 | } | 317 | } |
| 318 | 318 | ||
| 319 | iomux_v3_cfg_t const di0_pads[] = { | 319 | iomux_v3_cfg_t const di0_pads[] = { |
| 320 | MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ | 320 | MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ |
| 321 | MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */ | 321 | MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */ |
| 322 | MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */ | 322 | MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */ |
| 323 | }; | 323 | }; |
| 324 | 324 | ||
| 325 | /* CAN0/FLEXCAN1 */ | 325 | /* CAN0/FLEXCAN1 */ |
| 326 | iomux_v3_cfg_t const flexcan1_pads[] = { | 326 | iomux_v3_cfg_t const flexcan1_pads[] = { |
| 327 | 327 | ||
| 328 | MX6_PAD_GPIO_7__FLEXCAN1_TX | MUX_PAD_CTRL(WEAK_PULLUP), | 328 | MX6_PAD_GPIO_7__FLEXCAN1_TX | MUX_PAD_CTRL(WEAK_PULLUP), |
| 329 | MX6_PAD_GPIO_8__FLEXCAN1_RX | MUX_PAD_CTRL(WEAK_PULLUP), | 329 | MX6_PAD_GPIO_8__FLEXCAN1_RX | MUX_PAD_CTRL(WEAK_PULLUP), |
| 330 | }; | 330 | }; |
| 331 | 331 | ||
| 332 | /* CAN1/FLEXCAN2 */ | 332 | /* CAN1/FLEXCAN2 */ |
| 333 | iomux_v3_cfg_t const flexcan2_pads[] = { | 333 | iomux_v3_cfg_t const flexcan2_pads[] = { |
| 334 | MX6_PAD_KEY_COL4__FLEXCAN2_TX | MUX_PAD_CTRL(WEAK_PULLUP), | 334 | MX6_PAD_KEY_COL4__FLEXCAN2_TX | MUX_PAD_CTRL(WEAK_PULLUP), |
| 335 | MX6_PAD_KEY_ROW4__FLEXCAN2_RX | MUX_PAD_CTRL(WEAK_PULLUP), | 335 | MX6_PAD_KEY_ROW4__FLEXCAN2_RX | MUX_PAD_CTRL(WEAK_PULLUP), |
| 336 | }; | 336 | }; |
| 337 | 337 | ||
| 338 | /* GPIOs */ | 338 | /* GPIOs */ |
| 339 | iomux_v3_cfg_t const gpios_pads[] = { | 339 | iomux_v3_cfg_t const gpios_pads[] = { |
| 340 | MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO0 */ | 340 | MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO0 */ |
| 341 | MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO1 */ | 341 | MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO1 */ |
| 342 | MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO2 */ | 342 | MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO2 */ |
| 343 | MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO3 */ | 343 | MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO3 */ |
| 344 | MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO4 */ | 344 | MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO4 */ |
| 345 | MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO6 */ | 345 | MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO6 */ |
| 346 | MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO7 */ | 346 | MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO7 */ |
| 347 | MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO8 */ | 347 | MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO8 */ |
| 348 | MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO9 */ | 348 | MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO9 */ |
| 349 | MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO10 */ | 349 | MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO10 */ |
| 350 | MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO11 */ | 350 | MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO11 */ |
| 351 | }; | 351 | }; |
| 352 | 352 | ||
| 353 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) | 353 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) |
| 354 | static iomux_v3_cfg_t const epdc_enable_pads[] = { | 354 | static iomux_v3_cfg_t const epdc_enable_pads[] = { |
| 355 | MX6_PAD_EIM_A16__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 355 | MX6_PAD_EIM_A16__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 356 | MX6_PAD_EIM_DA10__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 356 | MX6_PAD_EIM_DA10__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 357 | MX6_PAD_EIM_DA12__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 357 | MX6_PAD_EIM_DA12__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 358 | MX6_PAD_EIM_DA11__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 358 | MX6_PAD_EIM_DA11__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 359 | MX6_PAD_EIM_LBA__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 359 | MX6_PAD_EIM_LBA__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 360 | MX6_PAD_EIM_EB2__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 360 | MX6_PAD_EIM_EB2__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 361 | MX6_PAD_EIM_CS0__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 361 | MX6_PAD_EIM_CS0__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 362 | MX6_PAD_EIM_RW__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 362 | MX6_PAD_EIM_RW__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 363 | MX6_PAD_EIM_A21__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 363 | MX6_PAD_EIM_A21__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 364 | MX6_PAD_EIM_A22__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 364 | MX6_PAD_EIM_A22__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 365 | MX6_PAD_EIM_A23__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 365 | MX6_PAD_EIM_A23__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 366 | MX6_PAD_EIM_A24__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 366 | MX6_PAD_EIM_A24__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 367 | MX6_PAD_EIM_D31__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 367 | MX6_PAD_EIM_D31__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 368 | MX6_PAD_EIM_D27__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 368 | MX6_PAD_EIM_D27__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 369 | MX6_PAD_EIM_DA1__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 369 | MX6_PAD_EIM_DA1__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 370 | MX6_PAD_EIM_EB1__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 370 | MX6_PAD_EIM_EB1__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 371 | MX6_PAD_EIM_DA2__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 371 | MX6_PAD_EIM_DA2__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 372 | MX6_PAD_EIM_DA4__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 372 | MX6_PAD_EIM_DA4__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 373 | MX6_PAD_EIM_DA5__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 373 | MX6_PAD_EIM_DA5__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 374 | MX6_PAD_EIM_DA6__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 374 | MX6_PAD_EIM_DA6__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 375 | }; | 375 | }; |
| 376 | 376 | ||
| 377 | static iomux_v3_cfg_t const epdc_disable_pads[] = { | 377 | static iomux_v3_cfg_t const epdc_disable_pads[] = { |
| 378 | MX6_PAD_EIM_A16__GPIO2_IO22, | 378 | MX6_PAD_EIM_A16__GPIO2_IO22, |
| 379 | MX6_PAD_EIM_DA10__GPIO3_IO10, | 379 | MX6_PAD_EIM_DA10__GPIO3_IO10, |
| 380 | MX6_PAD_EIM_DA12__GPIO3_IO12, | 380 | MX6_PAD_EIM_DA12__GPIO3_IO12, |
| 381 | MX6_PAD_EIM_DA11__GPIO3_IO11, | 381 | MX6_PAD_EIM_DA11__GPIO3_IO11, |
| 382 | MX6_PAD_EIM_LBA__GPIO2_IO27, | 382 | MX6_PAD_EIM_LBA__GPIO2_IO27, |
| 383 | MX6_PAD_EIM_EB2__GPIO2_IO30, | 383 | MX6_PAD_EIM_EB2__GPIO2_IO30, |
| 384 | MX6_PAD_EIM_CS0__GPIO2_IO23, | 384 | MX6_PAD_EIM_CS0__GPIO2_IO23, |
| 385 | MX6_PAD_EIM_RW__GPIO2_IO26, | 385 | MX6_PAD_EIM_RW__GPIO2_IO26, |
| 386 | MX6_PAD_EIM_A21__GPIO2_IO17, | 386 | MX6_PAD_EIM_A21__GPIO2_IO17, |
| 387 | MX6_PAD_EIM_A22__GPIO2_IO16, | 387 | MX6_PAD_EIM_A22__GPIO2_IO16, |
| 388 | MX6_PAD_EIM_A23__GPIO6_IO06, | 388 | MX6_PAD_EIM_A23__GPIO6_IO06, |
| 389 | MX6_PAD_EIM_A24__GPIO5_IO04, | 389 | MX6_PAD_EIM_A24__GPIO5_IO04, |
| 390 | MX6_PAD_EIM_D31__GPIO3_IO31, | 390 | MX6_PAD_EIM_D31__GPIO3_IO31, |
| 391 | MX6_PAD_EIM_D27__GPIO3_IO27, | 391 | MX6_PAD_EIM_D27__GPIO3_IO27, |
| 392 | MX6_PAD_EIM_DA1__GPIO3_IO01, | 392 | MX6_PAD_EIM_DA1__GPIO3_IO01, |
| 393 | MX6_PAD_EIM_EB1__GPIO2_IO29, | 393 | MX6_PAD_EIM_EB1__GPIO2_IO29, |
| 394 | MX6_PAD_EIM_DA2__GPIO3_IO02, | 394 | MX6_PAD_EIM_DA2__GPIO3_IO02, |
| 395 | MX6_PAD_EIM_DA4__GPIO3_IO04, | 395 | MX6_PAD_EIM_DA4__GPIO3_IO04, |
| 396 | MX6_PAD_EIM_DA5__GPIO3_IO05, | 396 | MX6_PAD_EIM_DA5__GPIO3_IO05, |
| 397 | MX6_PAD_EIM_DA6__GPIO3_IO06, | 397 | MX6_PAD_EIM_DA6__GPIO3_IO06, |
| 398 | }; | 398 | }; |
| 399 | #endif | 399 | #endif |
| 400 | 400 | ||
| 401 | static void setup_iomux_uart1(void) | 401 | static void setup_iomux_uart1(void) |
| 402 | { | 402 | { |
| 403 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); | 403 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| 404 | } | 404 | } |
| 405 | 405 | ||
| 406 | static void setup_iomux_uart2(void) | 406 | static void setup_iomux_uart2(void) |
| 407 | { | 407 | { |
| 408 | imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); | 408 | imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); |
| 409 | } | 409 | } |
| 410 | 410 | ||
| 411 | static void setup_iomux_uart4(void) | 411 | static void setup_iomux_uart4(void) |
| 412 | { | 412 | { |
| 413 | imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); | 413 | imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); |
| 414 | } | 414 | } |
| 415 | 415 | ||
| 416 | static void setup_iomux_uart5(void) | 416 | static void setup_iomux_uart5(void) |
| 417 | { | 417 | { |
| 418 | imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); | 418 | imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); |
| 419 | } | 419 | } |
| 420 | 420 | ||
| 421 | static void setup_iomux_wdt(void) | 421 | static void setup_iomux_wdt(void) |
| 422 | { | 422 | { |
| 423 | imx_iomux_v3_setup_multiple_pads(wdt_pads, ARRAY_SIZE(wdt_pads)); | 423 | imx_iomux_v3_setup_multiple_pads(wdt_pads, ARRAY_SIZE(wdt_pads)); |
| 424 | 424 | ||
| 425 | /* Set HW_WDT as Output High */ | 425 | /* Set HW_WDT as Output High */ |
| 426 | gpio_direction_output(IMX_GPIO_NR(3, 16) , 1); | 426 | gpio_direction_output(IMX_GPIO_NR(3, 16) , 1); |
| 427 | } | 427 | } |
| 428 | 428 | ||
| 429 | static void setup_iomux_reset_out(void) | 429 | static void setup_iomux_reset_out(void) |
| 430 | { | 430 | { |
| 431 | imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads)); | 431 | imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads)); |
| 432 | 432 | ||
| 433 | /* Set CPU RESET_OUT as Output */ | 433 | /* Set CPU RESET_OUT as Output */ |
| 434 | gpio_direction_output(IMX_GPIO_NR(6, 16) , 0); | 434 | gpio_direction_output(IMX_GPIO_NR(6, 16) , 0); |
| 435 | } | 435 | } |
| 436 | 436 | ||
| 437 | static void setup_spi1(void) | 437 | static void setup_spi1(void) |
| 438 | { | 438 | { |
| 439 | imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); | 439 | imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); |
| 440 | gpio_direction_output(IMX_GPIO_NR(4, 9), 0); | 440 | gpio_direction_output(IMX_GPIO_NR(4, 9), 0); |
| 441 | gpio_direction_output(IMX_GPIO_NR(4, 10), 0); | 441 | gpio_direction_output(IMX_GPIO_NR(4, 10), 0); |
| 442 | } | 442 | } |
| 443 | 443 | ||
| 444 | static void setup_flexcan1(void) | 444 | static void setup_flexcan1(void) |
| 445 | { | 445 | { |
| 446 | imx_iomux_v3_setup_multiple_pads(flexcan1_pads, ARRAY_SIZE(flexcan1_pads)); | 446 | imx_iomux_v3_setup_multiple_pads(flexcan1_pads, ARRAY_SIZE(flexcan1_pads)); |
| 447 | } | 447 | } |
| 448 | 448 | ||
| 449 | static void setup_flexcan2(void) | 449 | static void setup_flexcan2(void) |
| 450 | { | 450 | { |
| 451 | imx_iomux_v3_setup_multiple_pads(flexcan2_pads, ARRAY_SIZE(flexcan2_pads)); | 451 | imx_iomux_v3_setup_multiple_pads(flexcan2_pads, ARRAY_SIZE(flexcan2_pads)); |
| 452 | } | 452 | } |
| 453 | 453 | ||
| 454 | static void setup_gpios(void) | 454 | static void setup_gpios(void) |
| 455 | { | 455 | { |
| 456 | imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads)); | 456 | imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads)); |
| 457 | gpio_direction_output(IMX_GPIO_NR(6, 11), 0); | 457 | gpio_direction_output(IMX_GPIO_NR(6, 11), 0); |
| 458 | gpio_direction_output(IMX_GPIO_NR(2, 02), 0); | 458 | gpio_direction_output(IMX_GPIO_NR(2, 02), 0); |
| 459 | gpio_direction_output(IMX_GPIO_NR(2, 06), 0); | 459 | gpio_direction_output(IMX_GPIO_NR(2, 06), 0); |
| 460 | gpio_direction_output(IMX_GPIO_NR(2, 03), 0); | 460 | gpio_direction_output(IMX_GPIO_NR(2, 03), 0); |
| 461 | gpio_direction_output(IMX_GPIO_NR(2, 07), 0); | 461 | gpio_direction_output(IMX_GPIO_NR(2, 07), 0); |
| 462 | gpio_direction_input(IMX_GPIO_NR(6, 14)); | 462 | gpio_direction_input(IMX_GPIO_NR(6, 14)); |
| 463 | gpio_direction_input(IMX_GPIO_NR(6, 07)); | 463 | gpio_direction_input(IMX_GPIO_NR(6, 07)); |
| 464 | gpio_direction_input(IMX_GPIO_NR(2, 04)); | 464 | gpio_direction_input(IMX_GPIO_NR(2, 04)); |
| 465 | gpio_direction_input(IMX_GPIO_NR(2, 00)); | 465 | gpio_direction_input(IMX_GPIO_NR(2, 00)); |
| 466 | gpio_direction_input(IMX_GPIO_NR(2, 05)); | 466 | gpio_direction_input(IMX_GPIO_NR(2, 05)); |
| 467 | gpio_direction_input(IMX_GPIO_NR(6, 8)); | 467 | gpio_direction_input(IMX_GPIO_NR(6, 8)); |
| 468 | } | 468 | } |
| 469 | 469 | ||
| 470 | #ifdef CONFIG_FSL_ESDHC | 470 | #ifdef CONFIG_FSL_ESDHC |
| 471 | struct fsl_esdhc_cfg usdhc_cfg[3] = { | 471 | struct fsl_esdhc_cfg usdhc_cfg[3] = { |
| 472 | {USDHC2_BASE_ADDR}, | 472 | {USDHC2_BASE_ADDR}, |
| 473 | {USDHC3_BASE_ADDR}, | 473 | {USDHC3_BASE_ADDR}, |
| 474 | {USDHC4_BASE_ADDR}, | 474 | {USDHC4_BASE_ADDR}, |
| 475 | }; | 475 | }; |
| 476 | 476 | ||
| 477 | int mmc_get_env_devno(void) | 477 | int mmc_get_env_devno(void) |
| 478 | { | 478 | { |
| 479 | u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); | 479 | u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); |
| 480 | u32 dev_no; | 480 | u32 dev_no; |
| 481 | u32 bootsel; | 481 | u32 bootsel; |
| 482 | 482 | ||
| 483 | bootsel = (soc_sbmr & 0x000000FF) >> 6 ; | 483 | bootsel = (soc_sbmr & 0x000000FF) >> 6 ; |
| 484 | 484 | ||
| 485 | /* If not boot from sd/mmc, use default value */ | 485 | /* If not boot from sd/mmc, use default value */ |
| 486 | if (bootsel != 1) | 486 | if (bootsel != 1) |
| 487 | return CONFIG_SYS_MMC_ENV_DEV; | 487 | return CONFIG_SYS_MMC_ENV_DEV; |
| 488 | 488 | ||
| 489 | /* BOOT_CFG2[3] and BOOT_CFG2[4] */ | 489 | /* BOOT_CFG2[3] and BOOT_CFG2[4] */ |
| 490 | dev_no = (soc_sbmr & 0x00001800) >> 11; | 490 | dev_no = (soc_sbmr & 0x00001800) >> 11; |
| 491 | 491 | ||
| 492 | /* need ubstract 1 to map to the mmc device id | 492 | /* need ubstract 1 to map to the mmc device id |
| 493 | * see the comments in board_mmc_init function | 493 | * see the comments in board_mmc_init function |
| 494 | */ | 494 | */ |
| 495 | 495 | ||
| 496 | dev_no--; | 496 | dev_no--; |
| 497 | 497 | ||
| 498 | return dev_no; | 498 | return dev_no; |
| 499 | } | 499 | } |
| 500 | 500 | ||
| 501 | int mmc_map_to_kernel_blk(int dev_no) | 501 | int mmc_map_to_kernel_blk(int dev_no) |
| 502 | { | 502 | { |
| 503 | return dev_no + 1; | 503 | return dev_no + 1; |
| 504 | } | 504 | } |
| 505 | 505 | ||
| 506 | #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 28) | 506 | #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 28) |
| 507 | /*#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)*/ | 507 | /*#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)*/ |
| 508 | 508 | ||
| 509 | int board_mmc_getcd(struct mmc *mmc) | 509 | int board_mmc_getcd(struct mmc *mmc) |
| 510 | { | 510 | { |
| 511 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; | 511 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| 512 | int ret = 0; | 512 | int ret = 0; |
| 513 | 513 | ||
| 514 | switch (cfg->esdhc_base) { | 514 | switch (cfg->esdhc_base) { |
| 515 | case USDHC2_BASE_ADDR: | 515 | case USDHC2_BASE_ADDR: |
| 516 | ret = !gpio_get_value(USDHC2_CD_GPIO); | 516 | ret = !gpio_get_value(USDHC2_CD_GPIO); |
| 517 | break; | 517 | break; |
| 518 | case USDHC3_BASE_ADDR: | 518 | case USDHC3_BASE_ADDR: |
| 519 | /*ret = !gpio_get_value(USDHC3_CD_GPIO);*/ | 519 | /*ret = !gpio_get_value(USDHC3_CD_GPIO);*/ |
| 520 | break; | 520 | break; |
| 521 | case USDHC4_BASE_ADDR: | 521 | case USDHC4_BASE_ADDR: |
| 522 | ret = 1; /* eMMC/uSDHC4 is always present */ | 522 | ret = 1; /* eMMC/uSDHC4 is always present */ |
| 523 | break; | 523 | break; |
| 524 | } | 524 | } |
| 525 | 525 | ||
| 526 | return ret; | 526 | return ret; |
| 527 | } | 527 | } |
| 528 | 528 | ||
| 529 | int board_mmc_init(bd_t *bis) | 529 | int board_mmc_init(bd_t *bis) |
| 530 | { | 530 | { |
| 531 | s32 status = 0; | 531 | s32 status = 0; |
| 532 | int i; | 532 | int i; |
| 533 | 533 | ||
| 534 | /* | 534 | /* |
| 535 | * According to the board_mmc_init() the following map is done: | 535 | * According to the board_mmc_init() the following map is done: |
| 536 | * (U-boot device node) (Physical Port) | 536 | * (U-boot device node) (Physical Port) |
| 537 | * mmc0 SDIO | 537 | * mmc0 SDIO |
| 538 | * mmc1 SDMMC | 538 | * mmc1 SDMMC |
| 539 | * mmc2 eMMC | 539 | * mmc2 eMMC |
| 540 | */ | 540 | */ |
| 541 | for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { | 541 | for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
| 542 | switch (i) { | 542 | switch (i) { |
| 543 | case 0: | 543 | case 0: |
| 544 | imx_iomux_v3_setup_multiple_pads( | 544 | imx_iomux_v3_setup_multiple_pads( |
| 545 | usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); | 545 | usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
| 546 | gpio_direction_input(USDHC2_CD_GPIO); | 546 | gpio_direction_input(USDHC2_CD_GPIO); |
| 547 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); | 547 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| 548 | break; | 548 | break; |
| 549 | case 1: | 549 | case 1: |
| 550 | imx_iomux_v3_setup_multiple_pads( | 550 | imx_iomux_v3_setup_multiple_pads( |
| 551 | usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); | 551 | usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
| 552 | /*gpio_direction_input(USDHC3_CD_GPIO);*/ | 552 | /*gpio_direction_input(USDHC3_CD_GPIO);*/ |
| 553 | usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); | 553 | usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
| 554 | break; | 554 | break; |
| 555 | case 2: | 555 | case 2: |
| 556 | imx_iomux_v3_setup_multiple_pads( | 556 | imx_iomux_v3_setup_multiple_pads( |
| 557 | usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); | 557 | usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
| 558 | usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); | 558 | usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
| 559 | break; | 559 | break; |
| 560 | default: | 560 | default: |
| 561 | printf("Warning: you configured more USDHC controllers" | 561 | printf("Warning: you configured more USDHC controllers" |
| 562 | "(%d) then supported by the board (%d)\n", | 562 | "(%d) then supported by the board (%d)\n", |
| 563 | i + 1, CONFIG_SYS_FSL_USDHC_NUM); | 563 | i + 1, CONFIG_SYS_FSL_USDHC_NUM); |
| 564 | return status; | 564 | return status; |
| 565 | } | 565 | } |
| 566 | 566 | ||
| 567 | status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]); | 567 | status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
| 568 | } | 568 | } |
| 569 | 569 | ||
| 570 | return status; | 570 | return status; |
| 571 | } | 571 | } |
| 572 | 572 | ||
| 573 | int check_mmc_autodetect(void) | 573 | int check_mmc_autodetect(void) |
| 574 | { | 574 | { |
| 575 | char *autodetect_str = getenv("mmcautodetect"); | 575 | char *autodetect_str = getenv("mmcautodetect"); |
| 576 | 576 | ||
| 577 | if ((autodetect_str != NULL) && | 577 | if ((autodetect_str != NULL) && |
| 578 | (strcmp(autodetect_str, "yes") == 0)) { | 578 | (strcmp(autodetect_str, "yes") == 0)) { |
| 579 | return 1; | 579 | return 1; |
| 580 | } | 580 | } |
| 581 | 581 | ||
| 582 | return 0; | 582 | return 0; |
| 583 | } | 583 | } |
| 584 | 584 | ||
| 585 | void board_late_mmc_env_init(void) | 585 | void board_late_mmc_env_init(void) |
| 586 | { | 586 | { |
| 587 | char cmd[32]; | 587 | char cmd[32]; |
| 588 | char mmcblk[32]; | 588 | char mmcblk[32]; |
| 589 | u32 dev_no = mmc_get_env_devno(); | 589 | u32 dev_no = mmc_get_env_devno(); |
| 590 | 590 | ||
| 591 | if (!check_mmc_autodetect()) | 591 | if (!check_mmc_autodetect()) |
| 592 | return; | 592 | return; |
| 593 | 593 | ||
| 594 | setenv_ulong("mmcdev", dev_no); | 594 | setenv_ulong("mmcdev", dev_no); |
| 595 | 595 | ||
| 596 | /* Set mmcblk env */ | 596 | /* Set mmcblk env */ |
| 597 | sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", | 597 | sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", |
| 598 | mmc_map_to_kernel_blk(dev_no)); | 598 | mmc_map_to_kernel_blk(dev_no)); |
| 599 | setenv("mmcroot", mmcblk); | 599 | setenv("mmcroot", mmcblk); |
| 600 | 600 | ||
| 601 | sprintf(cmd, "mmc dev %d", dev_no); | 601 | sprintf(cmd, "mmc dev %d", dev_no); |
| 602 | run_command(cmd, 0); | 602 | run_command(cmd, 0); |
| 603 | } | 603 | } |
| 604 | #endif | 604 | #endif |
| 605 | 605 | ||
| 606 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) | 606 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) |
| 607 | #ifdef CONFIG_SPLASH_SCREEN | 607 | #ifdef CONFIG_SPLASH_SCREEN |
| 608 | extern int mmc_get_env_devno(void); | 608 | extern int mmc_get_env_devno(void); |
| 609 | int setup_splash_img(void) | 609 | int setup_splash_img(void) |
| 610 | { | 610 | { |
| 611 | #ifdef CONFIG_SPLASH_IS_IN_MMC | 611 | #ifdef CONFIG_SPLASH_IS_IN_MMC |
| 612 | int mmc_dev = mmc_get_env_devno(); | 612 | int mmc_dev = mmc_get_env_devno(); |
| 613 | ulong offset = CONFIG_SPLASH_IMG_OFFSET; | 613 | ulong offset = CONFIG_SPLASH_IMG_OFFSET; |
| 614 | ulong size = CONFIG_SPLASH_IMG_SIZE; | 614 | ulong size = CONFIG_SPLASH_IMG_SIZE; |
| 615 | ulong addr = 0; | 615 | ulong addr = 0; |
| 616 | char *s = NULL; | 616 | char *s = NULL; |
| 617 | struct mmc *mmc = find_mmc_device(mmc_dev); | 617 | struct mmc *mmc = find_mmc_device(mmc_dev); |
| 618 | uint blk_start, blk_cnt, n; | 618 | uint blk_start, blk_cnt, n; |
| 619 | 619 | ||
| 620 | s = getenv("splashimage"); | 620 | s = getenv("splashimage"); |
| 621 | 621 | ||
| 622 | if (NULL == s) { | 622 | if (NULL == s) { |
| 623 | puts("env splashimage not found!\n"); | 623 | puts("env splashimage not found!\n"); |
| 624 | return -1; | 624 | return -1; |
| 625 | } | 625 | } |
| 626 | addr = simple_strtoul(s, NULL, 16); | 626 | addr = simple_strtoul(s, NULL, 16); |
| 627 | 627 | ||
| 628 | if (!mmc) { | 628 | if (!mmc) { |
| 629 | printf("MMC Device %d not found\n", mmc_dev); | 629 | printf("MMC Device %d not found\n", mmc_dev); |
| 630 | return -1; | 630 | return -1; |
| 631 | } | 631 | } |
| 632 | 632 | ||
| 633 | if (mmc_init(mmc)) { | 633 | if (mmc_init(mmc)) { |
| 634 | puts("MMC init failed\n"); | 634 | puts("MMC init failed\n"); |
| 635 | return -1; | 635 | return -1; |
| 636 | } | 636 | } |
| 637 | 637 | ||
| 638 | blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; | 638 | blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; |
| 639 | blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; | 639 | blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; |
| 640 | n = mmc->block_dev.block_read(mmc_dev, blk_start, | 640 | n = mmc->block_dev.block_read(mmc_dev, blk_start, |
| 641 | blk_cnt, (u_char *)addr); | 641 | blk_cnt, (u_char *)addr); |
| 642 | flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len); | 642 | flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len); |
| 643 | 643 | ||
| 644 | return (n == blk_cnt) ? 0 : -1; | 644 | return (n == blk_cnt) ? 0 : -1; |
| 645 | #endif | 645 | #endif |
| 646 | 646 | ||
| 647 | return 0; | 647 | return 0; |
| 648 | } | 648 | } |
| 649 | #endif | 649 | #endif |
| 650 | 650 | ||
| 651 | vidinfo_t panel_info = { | 651 | vidinfo_t panel_info = { |
| 652 | .vl_refresh = 85, | 652 | .vl_refresh = 85, |
| 653 | .vl_col = 800, | 653 | .vl_col = 800, |
| 654 | .vl_row = 600, | 654 | .vl_row = 600, |
| 655 | .vl_pixclock = 26666667, | 655 | .vl_pixclock = 26666667, |
| 656 | .vl_left_margin = 8, | 656 | .vl_left_margin = 8, |
| 657 | .vl_right_margin = 100, | 657 | .vl_right_margin = 100, |
| 658 | .vl_upper_margin = 4, | 658 | .vl_upper_margin = 4, |
| 659 | .vl_lower_margin = 8, | 659 | .vl_lower_margin = 8, |
| 660 | .vl_hsync = 4, | 660 | .vl_hsync = 4, |
| 661 | .vl_vsync = 1, | 661 | .vl_vsync = 1, |
| 662 | .vl_sync = 0, | 662 | .vl_sync = 0, |
| 663 | .vl_mode = 0, | 663 | .vl_mode = 0, |
| 664 | .vl_flag = 0, | 664 | .vl_flag = 0, |
| 665 | .vl_bpix = 3, | 665 | .vl_bpix = 3, |
| 666 | .cmap = 0, | 666 | .cmap = 0, |
| 667 | }; | 667 | }; |
| 668 | 668 | ||
| 669 | struct epdc_timing_params panel_timings = { | 669 | struct epdc_timing_params panel_timings = { |
| 670 | .vscan_holdoff = 4, | 670 | .vscan_holdoff = 4, |
| 671 | .sdoed_width = 10, | 671 | .sdoed_width = 10, |
| 672 | .sdoed_delay = 20, | 672 | .sdoed_delay = 20, |
| 673 | .sdoez_width = 10, | 673 | .sdoez_width = 10, |
| 674 | .sdoez_delay = 20, | 674 | .sdoez_delay = 20, |
| 675 | .gdclk_hp_offs = 419, | 675 | .gdclk_hp_offs = 419, |
| 676 | .gdsp_offs = 20, | 676 | .gdsp_offs = 20, |
| 677 | .gdoe_offs = 0, | 677 | .gdoe_offs = 0, |
| 678 | .gdclk_offs = 5, | 678 | .gdclk_offs = 5, |
| 679 | .num_ce = 1, | 679 | .num_ce = 1, |
| 680 | }; | 680 | }; |
| 681 | 681 | ||
| 682 | static void setup_epdc_power(void) | 682 | static void setup_epdc_power(void) |
| 683 | { | 683 | { |
| 684 | /* Setup epdc voltage */ | 684 | /* Setup epdc voltage */ |
| 685 | 685 | ||
| 686 | /* EIM_A17 - GPIO2[21] for PWR_GOOD status */ | 686 | /* EIM_A17 - GPIO2[21] for PWR_GOOD status */ |
| 687 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 | | 687 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 | |
| 688 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); | 688 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); |
| 689 | /* Set as input */ | 689 | /* Set as input */ |
| 690 | gpio_direction_input(IMX_GPIO_NR(2, 21)); | 690 | gpio_direction_input(IMX_GPIO_NR(2, 21)); |
| 691 | 691 | ||
| 692 | /* EIM_D17 - GPIO3[17] for VCOM control */ | 692 | /* EIM_D17 - GPIO3[17] for VCOM control */ |
| 693 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 | | 693 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 | |
| 694 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); | 694 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); |
| 695 | 695 | ||
| 696 | /* Set as output */ | 696 | /* Set as output */ |
| 697 | gpio_direction_output(IMX_GPIO_NR(3, 17), 1); | 697 | gpio_direction_output(IMX_GPIO_NR(3, 17), 1); |
| 698 | 698 | ||
| 699 | /* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */ | 699 | /* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */ |
| 700 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 | | 700 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 | |
| 701 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); | 701 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); |
| 702 | /* Set as output */ | 702 | /* Set as output */ |
| 703 | gpio_direction_output(IMX_GPIO_NR(3, 20), 1); | 703 | gpio_direction_output(IMX_GPIO_NR(3, 20), 1); |
| 704 | 704 | ||
| 705 | /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ | 705 | /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ |
| 706 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 | | 706 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 | |
| 707 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); | 707 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); |
| 708 | /* Set as output */ | 708 | /* Set as output */ |
| 709 | gpio_direction_output(IMX_GPIO_NR(2, 20), 1); | 709 | gpio_direction_output(IMX_GPIO_NR(2, 20), 1); |
| 710 | } | 710 | } |
| 711 | 711 | ||
| 712 | int setup_waveform_file(void) | 712 | int setup_waveform_file(void) |
| 713 | { | 713 | { |
| 714 | #ifdef CONFIG_WAVEFORM_FILE_IN_MMC | 714 | #ifdef CONFIG_WAVEFORM_FILE_IN_MMC |
| 715 | int mmc_dev = mmc_get_env_devno(); | 715 | int mmc_dev = mmc_get_env_devno(); |
| 716 | ulong offset = CONFIG_WAVEFORM_FILE_OFFSET; | 716 | ulong offset = CONFIG_WAVEFORM_FILE_OFFSET; |
| 717 | ulong size = CONFIG_WAVEFORM_FILE_SIZE; | 717 | ulong size = CONFIG_WAVEFORM_FILE_SIZE; |
| 718 | ulong addr = CONFIG_WAVEFORM_BUF_ADDR; | 718 | ulong addr = CONFIG_WAVEFORM_BUF_ADDR; |
| 719 | struct mmc *mmc = find_mmc_device(mmc_dev); | 719 | struct mmc *mmc = find_mmc_device(mmc_dev); |
| 720 | uint blk_start, blk_cnt, n; | 720 | uint blk_start, blk_cnt, n; |
| 721 | 721 | ||
| 722 | if (!mmc) { | 722 | if (!mmc) { |
| 723 | printf("MMC Device %d not found\n", mmc_dev); | 723 | printf("MMC Device %d not found\n", mmc_dev); |
| 724 | return -1; | 724 | return -1; |
| 725 | } | 725 | } |
| 726 | 726 | ||
| 727 | if (mmc_init(mmc)) { | 727 | if (mmc_init(mmc)) { |
| 728 | puts("MMC init failed\n"); | 728 | puts("MMC init failed\n"); |
| 729 | return -1; | 729 | return -1; |
| 730 | } | 730 | } |
| 731 | 731 | ||
| 732 | blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; | 732 | blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; |
| 733 | blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; | 733 | blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; |
| 734 | n = mmc->block_dev.block_read(mmc_dev, blk_start, | 734 | n = mmc->block_dev.block_read(mmc_dev, blk_start, |
| 735 | blk_cnt, (u_char *)addr); | 735 | blk_cnt, (u_char *)addr); |
| 736 | flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len); | 736 | flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len); |
| 737 | 737 | ||
| 738 | return (n == blk_cnt) ? 0 : -1; | 738 | return (n == blk_cnt) ? 0 : -1; |
| 739 | #else | 739 | #else |
| 740 | return -1; | 740 | return -1; |
| 741 | #endif | 741 | #endif |
| 742 | } | 742 | } |
| 743 | 743 | ||
| 744 | static void epdc_enable_pins(void) | 744 | static void epdc_enable_pins(void) |
| 745 | { | 745 | { |
| 746 | /* epdc iomux settings */ | 746 | /* epdc iomux settings */ |
| 747 | imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, | 747 | imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, |
| 748 | ARRAY_SIZE(epdc_enable_pads)); | 748 | ARRAY_SIZE(epdc_enable_pads)); |
| 749 | } | 749 | } |
| 750 | 750 | ||
| 751 | static void epdc_disable_pins(void) | 751 | static void epdc_disable_pins(void) |
| 752 | { | 752 | { |
| 753 | /* Configure MUX settings for EPDC pins to GPIO */ | 753 | /* Configure MUX settings for EPDC pins to GPIO */ |
| 754 | imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, | 754 | imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, |
| 755 | ARRAY_SIZE(epdc_disable_pads)); | 755 | ARRAY_SIZE(epdc_disable_pads)); |
| 756 | } | 756 | } |
| 757 | 757 | ||
| 758 | static void setup_epdc(void) | 758 | static void setup_epdc(void) |
| 759 | { | 759 | { |
| 760 | unsigned int reg; | 760 | unsigned int reg; |
| 761 | struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | 761 | struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 762 | 762 | ||
| 763 | /*** epdc Maxim PMIC settings ***/ | 763 | /*** epdc Maxim PMIC settings ***/ |
| 764 | 764 | ||
| 765 | /* EPDC PWRSTAT - GPIO2[21] for PWR_GOOD status */ | 765 | /* EPDC PWRSTAT - GPIO2[21] for PWR_GOOD status */ |
| 766 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 | | 766 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 | |
| 767 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); | 767 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); |
| 768 | 768 | ||
| 769 | /* EPDC VCOM0 - GPIO3[17] for VCOM control */ | 769 | /* EPDC VCOM0 - GPIO3[17] for VCOM control */ |
| 770 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 | | 770 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 | |
| 771 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); | 771 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); |
| 772 | 772 | ||
| 773 | /* UART4 TXD - GPIO3[20] for EPD PMIC WAKEUP */ | 773 | /* UART4 TXD - GPIO3[20] for EPD PMIC WAKEUP */ |
| 774 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 | | 774 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 | |
| 775 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); | 775 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); |
| 776 | 776 | ||
| 777 | /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ | 777 | /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ |
| 778 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 | | 778 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 | |
| 779 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); | 779 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); |
| 780 | 780 | ||
| 781 | /*** Set pixel clock rates for EPDC ***/ | 781 | /*** Set pixel clock rates for EPDC ***/ |
| 782 | 782 | ||
| 783 | /* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */ | 783 | /* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */ |
| 784 | reg = readl(&ccm_regs->cscdr3); | 784 | reg = readl(&ccm_regs->cscdr3); |
| 785 | reg &= ~0x7C000; | 785 | reg &= ~0x7C000; |
| 786 | reg |= (1 << 16) | (1 << 14); | 786 | reg |= (1 << 16) | (1 << 14); |
| 787 | writel(reg, &ccm_regs->cscdr3); | 787 | writel(reg, &ccm_regs->cscdr3); |
| 788 | 788 | ||
| 789 | /* EPDC AXI clk enable */ | 789 | /* EPDC AXI clk enable */ |
| 790 | reg = readl(&ccm_regs->CCGR3); | 790 | reg = readl(&ccm_regs->CCGR3); |
| 791 | reg |= 0x00C0; | 791 | reg |= 0x00C0; |
| 792 | writel(reg, &ccm_regs->CCGR3); | 792 | writel(reg, &ccm_regs->CCGR3); |
| 793 | 793 | ||
| 794 | /* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */ | 794 | /* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */ |
| 795 | reg = readl(&ccm_regs->cscdr2); | 795 | reg = readl(&ccm_regs->cscdr2); |
| 796 | reg &= ~0x3FE00; | 796 | reg &= ~0x3FE00; |
| 797 | reg |= (2 << 15) | (5 << 12); | 797 | reg |= (2 << 15) | (5 << 12); |
| 798 | writel(reg, &ccm_regs->cscdr2); | 798 | writel(reg, &ccm_regs->cscdr2); |
| 799 | 799 | ||
| 800 | /* PLL5 enable (defaults to 650) */ | 800 | /* PLL5 enable (defaults to 650) */ |
| 801 | reg = readl(&ccm_regs->analog_pll_video); | 801 | reg = readl(&ccm_regs->analog_pll_video); |
| 802 | reg &= ~((1 << 16) | (1 << 12)); | 802 | reg &= ~((1 << 16) | (1 << 12)); |
| 803 | reg |= (1 << 13); | 803 | reg |= (1 << 13); |
| 804 | writel(reg, &ccm_regs->analog_pll_video); | 804 | writel(reg, &ccm_regs->analog_pll_video); |
| 805 | 805 | ||
| 806 | /* EPDC PIX clk enable */ | 806 | /* EPDC PIX clk enable */ |
| 807 | reg = readl(&ccm_regs->CCGR3); | 807 | reg = readl(&ccm_regs->CCGR3); |
| 808 | reg |= 0x0C00; | 808 | reg |= 0x0C00; |
| 809 | writel(reg, &ccm_regs->CCGR3); | 809 | writel(reg, &ccm_regs->CCGR3); |
| 810 | 810 | ||
| 811 | panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR; | 811 | panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR; |
| 812 | panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR; | 812 | panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR; |
| 813 | 813 | ||
| 814 | panel_info.epdc_data.wv_modes.mode_init = 0; | 814 | panel_info.epdc_data.wv_modes.mode_init = 0; |
| 815 | panel_info.epdc_data.wv_modes.mode_du = 1; | 815 | panel_info.epdc_data.wv_modes.mode_du = 1; |
| 816 | panel_info.epdc_data.wv_modes.mode_gc4 = 3; | 816 | panel_info.epdc_data.wv_modes.mode_gc4 = 3; |
| 817 | panel_info.epdc_data.wv_modes.mode_gc8 = 2; | 817 | panel_info.epdc_data.wv_modes.mode_gc8 = 2; |
| 818 | panel_info.epdc_data.wv_modes.mode_gc16 = 2; | 818 | panel_info.epdc_data.wv_modes.mode_gc16 = 2; |
| 819 | panel_info.epdc_data.wv_modes.mode_gc32 = 2; | 819 | panel_info.epdc_data.wv_modes.mode_gc32 = 2; |
| 820 | 820 | ||
| 821 | panel_info.epdc_data.epdc_timings = panel_timings; | 821 | panel_info.epdc_data.epdc_timings = panel_timings; |
| 822 | 822 | ||
| 823 | setup_epdc_power(); | 823 | setup_epdc_power(); |
| 824 | 824 | ||
| 825 | /* Assign fb_base */ | 825 | /* Assign fb_base */ |
| 826 | gd->fb_base = CONFIG_FB_BASE; | 826 | gd->fb_base = CONFIG_FB_BASE; |
| 827 | } | 827 | } |
| 828 | 828 | ||
| 829 | void epdc_power_on(void) | 829 | void epdc_power_on(void) |
| 830 | { | 830 | { |
| 831 | unsigned int reg; | 831 | unsigned int reg; |
| 832 | struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; | 832 | struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; |
| 833 | 833 | ||
| 834 | /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ | 834 | /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ |
| 835 | gpio_set_value(IMX_GPIO_NR(2, 20), 1); | 835 | gpio_set_value(IMX_GPIO_NR(2, 20), 1); |
| 836 | udelay(1000); | 836 | udelay(1000); |
| 837 | 837 | ||
| 838 | /* Enable epdc signal pin */ | 838 | /* Enable epdc signal pin */ |
| 839 | epdc_enable_pins(); | 839 | epdc_enable_pins(); |
| 840 | 840 | ||
| 841 | /* Set PMIC Wakeup to high - enable Display power */ | 841 | /* Set PMIC Wakeup to high - enable Display power */ |
| 842 | gpio_set_value(IMX_GPIO_NR(3, 20), 1); | 842 | gpio_set_value(IMX_GPIO_NR(3, 20), 1); |
| 843 | 843 | ||
| 844 | /* Wait for PWRGOOD == 1 */ | 844 | /* Wait for PWRGOOD == 1 */ |
| 845 | while (1) { | 845 | while (1) { |
| 846 | reg = readl(&gpio_regs->gpio_psr); | 846 | reg = readl(&gpio_regs->gpio_psr); |
| 847 | if (!(reg & (1 << 21))) | 847 | if (!(reg & (1 << 21))) |
| 848 | break; | 848 | break; |
| 849 | 849 | ||
| 850 | udelay(100); | 850 | udelay(100); |
| 851 | } | 851 | } |
| 852 | 852 | ||
| 853 | /* Enable VCOM */ | 853 | /* Enable VCOM */ |
| 854 | gpio_set_value(IMX_GPIO_NR(3, 17), 1); | 854 | gpio_set_value(IMX_GPIO_NR(3, 17), 1); |
| 855 | 855 | ||
| 856 | udelay(500); | 856 | udelay(500); |
| 857 | } | 857 | } |
| 858 | 858 | ||
| 859 | void epdc_power_off(void) | 859 | void epdc_power_off(void) |
| 860 | { | 860 | { |
| 861 | /* Set PMIC Wakeup to low - disable Display power */ | 861 | /* Set PMIC Wakeup to low - disable Display power */ |
| 862 | gpio_set_value(IMX_GPIO_NR(3, 20), 0); | 862 | gpio_set_value(IMX_GPIO_NR(3, 20), 0); |
| 863 | 863 | ||
| 864 | /* Disable VCOM */ | 864 | /* Disable VCOM */ |
| 865 | gpio_set_value(IMX_GPIO_NR(3, 17), 0); | 865 | gpio_set_value(IMX_GPIO_NR(3, 17), 0); |
| 866 | 866 | ||
| 867 | epdc_disable_pins(); | 867 | epdc_disable_pins(); |
| 868 | 868 | ||
| 869 | /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ | 869 | /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ |
| 870 | gpio_set_value(IMX_GPIO_NR(2, 20), 0); | 870 | gpio_set_value(IMX_GPIO_NR(2, 20), 0); |
| 871 | } | 871 | } |
| 872 | #endif | 872 | #endif |
| 873 | 873 | ||
| 874 | #if defined(CONFIG_VIDEO_IPUV3) | 874 | #if defined(CONFIG_VIDEO_IPUV3) |
| 875 | 875 | ||
| 876 | static iomux_v3_cfg_t const backlight_pads[] = { | 876 | static iomux_v3_cfg_t const backlight_pads[] = { |
| 877 | /* Backlight Enable for RGB: S127 */ | 877 | /* Backlight Enable for RGB: S127 */ |
| 878 | MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), | 878 | MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 879 | #define BACKLIGHT_EN IMX_GPIO_NR(1, 00) | 879 | #define BACKLIGHT_EN IMX_GPIO_NR(1, 00) |
| 880 | /* PWM Backlight Control: S141 */ | 880 | /* PWM Backlight Control: S141 */ |
| 881 | 881 | ||
| 882 | /* Backlight Enable for LVDS: S127 */ | 882 | /* Backlight Enable for LVDS: S127 */ |
| 883 | MX6_PAD_GPIO_1__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), | 883 | MX6_PAD_GPIO_1__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 884 | /* LCD VDD Enable(for parallel LCD): S133 */ | 884 | /* LCD VDD Enable(for parallel LCD): S133 */ |
| 885 | MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), | 885 | MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 886 | #define LCD_VDD_EN IMX_GPIO_NR(1, 02) | 886 | #define LCD_VDD_EN IMX_GPIO_NR(1, 02) |
| 887 | }; | 887 | }; |
| 888 | 888 | ||
| 889 | static iomux_v3_cfg_t const rgb_pads[] = { | 889 | static iomux_v3_cfg_t const rgb_pads[] = { |
| 890 | MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), | 890 | MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 891 | MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 891 | MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 892 | MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 892 | MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 893 | MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 893 | MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 894 | MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(LCD_PAD_CTRL), /* DISP0_DRDY */ | 894 | MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(LCD_PAD_CTRL), /* DISP0_DRDY */ |
| 895 | MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 895 | MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 896 | MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 896 | MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 897 | MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 897 | MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 898 | MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 898 | MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 899 | MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 899 | MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 900 | MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 900 | MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 901 | MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 901 | MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 902 | MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 902 | MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 903 | MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 903 | MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 904 | MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 904 | MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 905 | MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 905 | MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 906 | MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 906 | MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 907 | MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 907 | MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 908 | MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 908 | MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 909 | MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 909 | MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 910 | MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 910 | MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 911 | MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 911 | MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 912 | MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 912 | MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 913 | MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 913 | MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 914 | MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 914 | MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 915 | MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 915 | MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 916 | MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 916 | MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 917 | MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 917 | MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 918 | MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 918 | MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 919 | }; | 919 | }; |
| 920 | 920 | ||
| 921 | struct display_info_t { | 921 | struct display_info_t { |
| 922 | int bus; | 922 | int bus; |
| 923 | int addr; | 923 | int addr; |
| 924 | int pixfmt; | 924 | int pixfmt; |
| 925 | int (*detect)(struct display_info_t const *dev); | 925 | int (*detect)(struct display_info_t const *dev); |
| 926 | void (*enable)(struct display_info_t const *dev); | 926 | void (*enable)(struct display_info_t const *dev); |
| 927 | struct fb_videomode mode; | 927 | struct fb_videomode mode; |
| 928 | }; | 928 | }; |
| 929 | 929 | ||
| 930 | /*static void disable_lvds(struct display_info_t const *dev) | 930 | /*static void disable_lvds(struct display_info_t const *dev) |
| 931 | { | 931 | { |
| 932 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | 932 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| 933 | 933 | ||
| 934 | int reg = readl(&iomux->gpr[2]); | 934 | int reg = readl(&iomux->gpr[2]); |
| 935 | 935 | ||
| 936 | reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | | 936 | reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | |
| 937 | IOMUXC_GPR2_LVDS_CH1_MODE_MASK); | 937 | IOMUXC_GPR2_LVDS_CH1_MODE_MASK); |
| 938 | 938 | ||
| 939 | writel(reg, &iomux->gpr[2]); | 939 | writel(reg, &iomux->gpr[2]); |
| 940 | }*/ | 940 | }*/ |
| 941 | 941 | ||
| 942 | /*static void do_enable_hdmi(struct display_info_t const *dev) | 942 | /*static void do_enable_hdmi(struct display_info_t const *dev) |
| 943 | { | 943 | { |
| 944 | disable_lvds(dev); | 944 | disable_lvds(dev); |
| 945 | imx_enable_hdmi_phy(); | 945 | imx_enable_hdmi_phy(); |
| 946 | } | 946 | } |
| 947 | 947 | ||
| 948 | static void enable_rgb(struct display_info_t const *dev) | 948 | static void enable_rgb(struct display_info_t const *dev) |
| 949 | { | 949 | { |
| 950 | imx_iomux_v3_setup_multiple_pads( | 950 | imx_iomux_v3_setup_multiple_pads( |
| 951 | rgb_pads, | 951 | rgb_pads, |
| 952 | ARRAY_SIZE(rgb_pads)); | 952 | ARRAY_SIZE(rgb_pads)); |
| 953 | }*/ | 953 | }*/ |
| 954 | 954 | ||
| 955 | static struct display_info_t const displays[] = {{ | 955 | static struct display_info_t const displays[] = {{ |
| 956 | .bus = -1, | 956 | .bus = -1, |
| 957 | .addr = 0, | 957 | .addr = 0, |
| 958 | .pixfmt = IPU_PIX_FMT_RGB24, | 958 | .pixfmt = IPU_PIX_FMT_RGB24, |
| 959 | .detect = NULL, | 959 | .detect = NULL, |
| 960 | /*.enable = do_enable_hdmi,*/ | 960 | /*.enable = do_enable_hdmi,*/ |
| 961 | .enable = NULL, | 961 | .enable = NULL, |
| 962 | .mode = { | 962 | .mode = { |
| 963 | .name = "HDMI", | 963 | .name = "HDMI", |
| 964 | .refresh = 60, | 964 | .refresh = 60, |
| 965 | .xres = 640, | 965 | .xres = 640, |
| 966 | .yres = 480, | 966 | .yres = 480, |
| 967 | .pixclock = 39721, | 967 | .pixclock = 39721, |
| 968 | .left_margin = 48, | 968 | .left_margin = 48, |
| 969 | .right_margin = 16, | 969 | .right_margin = 16, |
| 970 | .upper_margin = 33, | 970 | .upper_margin = 33, |
| 971 | .lower_margin = 10, | 971 | .lower_margin = 10, |
| 972 | .hsync_len = 96, | 972 | .hsync_len = 96, |
| 973 | .vsync_len = 2, | 973 | .vsync_len = 2, |
| 974 | .sync = 0, | 974 | .sync = 0, |
| 975 | .vmode = FB_VMODE_NONINTERLACED | 975 | .vmode = FB_VMODE_NONINTERLACED |
| 976 | } }, { | 976 | } }, { |
| 977 | .bus = -1, | 977 | .bus = -1, |
| 978 | .addr = 0, | 978 | .addr = 0, |
| 979 | .pixfmt = IPU_PIX_FMT_LVDS666, | 979 | .pixfmt = IPU_PIX_FMT_LVDS666, |
| 980 | .detect = NULL, | 980 | .detect = NULL, |
| 981 | .enable = NULL, | 981 | .enable = NULL, |
| 982 | .mode = { | 982 | .mode = { |
| 983 | .name = "Hannstar-XGA", | 983 | .name = "Hannstar-XGA", |
| 984 | .refresh = 60, | 984 | .refresh = 60, |
| 985 | .xres = 1024, | 985 | .xres = 1024, |
| 986 | .yres = 768, | 986 | .yres = 768, |
| 987 | .pixclock = 15385, | 987 | .pixclock = 15385, |
| 988 | .left_margin = 220, | 988 | .left_margin = 220, |
| 989 | .right_margin = 40, | 989 | .right_margin = 40, |
| 990 | .upper_margin = 21, | 990 | .upper_margin = 21, |
| 991 | .lower_margin = 7, | 991 | .lower_margin = 7, |
| 992 | .hsync_len = 60, | 992 | .hsync_len = 60, |
| 993 | .vsync_len = 10, | 993 | .vsync_len = 10, |
| 994 | .sync = FB_SYNC_EXT, | 994 | .sync = FB_SYNC_EXT, |
| 995 | .vmode = FB_VMODE_NONINTERLACED | 995 | .vmode = FB_VMODE_NONINTERLACED |
| 996 | } }, { | 996 | } }, { |
| 997 | .bus = -1, | 997 | .bus = -1, |
| 998 | .addr = 0, | 998 | .addr = 0, |
| 999 | .pixfmt = IPU_PIX_FMT_RGB24, | 999 | .pixfmt = IPU_PIX_FMT_RGB24, |
| 1000 | .detect = NULL, | 1000 | .detect = NULL, |
| 1001 | .enable = NULL, | 1001 | .enable = NULL, |
| 1002 | .mode = { | 1002 | .mode = { |
| 1003 | .name = "wvga-rgb", | 1003 | .name = "wvga-rgb", |
| 1004 | .refresh = 57, | 1004 | .refresh = 57, |
| 1005 | .xres = 800, | 1005 | .xres = 800, |
| 1006 | .yres = 480, | 1006 | .yres = 480, |
| 1007 | .pixclock = 37037, | 1007 | .pixclock = 37037, |
| 1008 | .left_margin = 40, | 1008 | .left_margin = 40, |
| 1009 | .right_margin = 60, | 1009 | .right_margin = 60, |
| 1010 | .upper_margin = 10, | 1010 | .upper_margin = 10, |
| 1011 | .lower_margin = 10, | 1011 | .lower_margin = 10, |
| 1012 | .hsync_len = 20, | 1012 | .hsync_len = 20, |
| 1013 | .vsync_len = 10, | 1013 | .vsync_len = 10, |
| 1014 | .sync = 0, | 1014 | .sync = 0, |
| 1015 | .vmode = FB_VMODE_NONINTERLACED | 1015 | .vmode = FB_VMODE_NONINTERLACED |
| 1016 | } } }; | 1016 | } } }; |
| 1017 | 1017 | ||
| 1018 | int board_video_skip(void) | 1018 | int board_video_skip(void) |
| 1019 | { | 1019 | { |
| 1020 | int i; | 1020 | int i; |
| 1021 | int ret; | 1021 | int ret; |
| 1022 | char const *panel = getenv("panel"); | 1022 | char const *panel = getenv("panel"); |
| 1023 | if (!panel) { | 1023 | if (!panel) { |
| 1024 | for (i = 0; i < ARRAY_SIZE(displays); i++) { | 1024 | for (i = 0; i < ARRAY_SIZE(displays); i++) { |
| 1025 | struct display_info_t const *dev = displays+i; | 1025 | struct display_info_t const *dev = displays+i; |
| 1026 | if (dev->detect && dev->detect(dev)) { | 1026 | if (dev->detect && dev->detect(dev)) { |
| 1027 | panel = dev->mode.name; | 1027 | panel = dev->mode.name; |
| 1028 | printf("auto-detected panel %s\n", panel); | 1028 | printf("auto-detected panel %s\n", panel); |
| 1029 | break; | 1029 | break; |
| 1030 | } | 1030 | } |
| 1031 | } | 1031 | } |
| 1032 | if (!panel) { | 1032 | if (!panel) { |
| 1033 | panel = displays[0].mode.name; | 1033 | panel = displays[0].mode.name; |
| 1034 | printf("No panel detected: default to %s\n", panel); | 1034 | printf("No panel detected: default to %s\n", panel); |
| 1035 | i = 0; | 1035 | i = 0; |
| 1036 | } | 1036 | } |
| 1037 | } else { | 1037 | } else { |
| 1038 | for (i = 0; i < ARRAY_SIZE(displays); i++) { | 1038 | for (i = 0; i < ARRAY_SIZE(displays); i++) { |
| 1039 | if (!strcmp(panel, displays[i].mode.name)) | 1039 | if (!strcmp(panel, displays[i].mode.name)) |
| 1040 | break; | 1040 | break; |
| 1041 | } | 1041 | } |
| 1042 | } | 1042 | } |
| 1043 | if (i < ARRAY_SIZE(displays)) { | 1043 | if (i < ARRAY_SIZE(displays)) { |
| 1044 | ret = ipuv3_fb_init(&displays[i].mode, 0, | 1044 | ret = ipuv3_fb_init(&displays[i].mode, 0, |
| 1045 | displays[i].pixfmt); | 1045 | displays[i].pixfmt); |
| 1046 | if (!ret) { | 1046 | if (!ret) { |
| 1047 | if (displays[i].enable) | 1047 | if (displays[i].enable) |
| 1048 | displays[i].enable(displays+i); | 1048 | displays[i].enable(displays+i); |
| 1049 | printf("Display: %s (%ux%u)\n", | 1049 | printf("Display: %s (%ux%u)\n", |
| 1050 | displays[i].mode.name, | 1050 | displays[i].mode.name, |
| 1051 | displays[i].mode.xres, | 1051 | displays[i].mode.xres, |
| 1052 | displays[i].mode.yres); | 1052 | displays[i].mode.yres); |
| 1053 | } else | 1053 | } else |
| 1054 | printf("LCD %s cannot be configured: %d\n", | 1054 | printf("LCD %s cannot be configured: %d\n", |
| 1055 | displays[i].mode.name, ret); | 1055 | displays[i].mode.name, ret); |
| 1056 | } else { | 1056 | } else { |
| 1057 | printf("unsupported panel %s\n", panel); | 1057 | printf("unsupported panel %s\n", panel); |
| 1058 | return -EINVAL; | 1058 | return -EINVAL; |
| 1059 | } | 1059 | } |
| 1060 | 1060 | ||
| 1061 | return 0; | 1061 | return 0; |
| 1062 | } | 1062 | } |
| 1063 | 1063 | ||
| 1064 | static void setup_display(void) | 1064 | static void setup_display(void) |
| 1065 | { | 1065 | { |
| 1066 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | 1066 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 1067 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | 1067 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| 1068 | int reg; | 1068 | int reg; |
| 1069 | 1069 | ||
| 1070 | /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ | 1070 | /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ |
| 1071 | imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads)); | 1071 | imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads)); |
| 1072 | 1072 | ||
| 1073 | enable_ipu_clock(); | 1073 | enable_ipu_clock(); |
| 1074 | imx_setup_hdmi(); | 1074 | imx_setup_hdmi(); |
| 1075 | 1075 | ||
| 1076 | /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ | 1076 | /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ |
| 1077 | reg = readl(&mxc_ccm->CCGR3); | 1077 | reg = readl(&mxc_ccm->CCGR3); |
| 1078 | reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; | 1078 | reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; |
| 1079 | writel(reg, &mxc_ccm->CCGR3); | 1079 | writel(reg, &mxc_ccm->CCGR3); |
| 1080 | 1080 | ||
| 1081 | /* set LDB0, LDB1 clk select to 011/011 */ | 1081 | /* set LDB0, LDB1 clk select to 011/011 */ |
| 1082 | reg = readl(&mxc_ccm->cs2cdr); | 1082 | reg = readl(&mxc_ccm->cs2cdr); |
| 1083 | reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | 1083 | reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
| 1084 | | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); | 1084 | | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); |
| 1085 | reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | 1085 | reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
| 1086 | | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); | 1086 | | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); |
| 1087 | writel(reg, &mxc_ccm->cs2cdr); | 1087 | writel(reg, &mxc_ccm->cs2cdr); |
| 1088 | 1088 | ||
| 1089 | reg = readl(&mxc_ccm->cscmr2); | 1089 | reg = readl(&mxc_ccm->cscmr2); |
| 1090 | reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; | 1090 | reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; |
| 1091 | writel(reg, &mxc_ccm->cscmr2); | 1091 | writel(reg, &mxc_ccm->cscmr2); |
| 1092 | 1092 | ||
| 1093 | reg = readl(&mxc_ccm->chsccdr); | 1093 | reg = readl(&mxc_ccm->chsccdr); |
| 1094 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 | 1094 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 |
| 1095 | << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); | 1095 | << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); |
| 1096 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 | 1096 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 |
| 1097 | << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); | 1097 | << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); |
| 1098 | writel(reg, &mxc_ccm->chsccdr); | 1098 | writel(reg, &mxc_ccm->chsccdr); |
| 1099 | 1099 | ||
| 1100 | reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | 1100 | reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
| 1101 | | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW | 1101 | | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
| 1102 | | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | 1102 | | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
| 1103 | | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | 1103 | | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
| 1104 | | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | 1104 | | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
| 1105 | | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | 1105 | | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
| 1106 | | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | 1106 | | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
| 1107 | | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED | 1107 | | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED |
| 1108 | | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; | 1108 | | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; |
| 1109 | writel(reg, &iomux->gpr[2]); | 1109 | writel(reg, &iomux->gpr[2]); |
| 1110 | 1110 | ||
| 1111 | reg = readl(&iomux->gpr[3]); | 1111 | reg = readl(&iomux->gpr[3]); |
| 1112 | reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | 1112 | reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
| 1113 | | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) | 1113 | | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |
| 1114 | | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 | 1114 | | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 |
| 1115 | << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); | 1115 | << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); |
| 1116 | writel(reg, &iomux->gpr[3]); | 1116 | writel(reg, &iomux->gpr[3]); |
| 1117 | /* backlights off until needed */ | 1117 | /* backlights off until needed */ |
| 1118 | 1118 | ||
| 1119 | imx_iomux_v3_setup_multiple_pads(backlight_pads, | 1119 | imx_iomux_v3_setup_multiple_pads(backlight_pads, |
| 1120 | ARRAY_SIZE(backlight_pads)); | 1120 | ARRAY_SIZE(backlight_pads)); |
| 1121 | /*gpio_direction_input(BACKLIGHT_EN);*/ | 1121 | /*gpio_direction_input(BACKLIGHT_EN);*/ |
| 1122 | /* turn on backlight */ | 1122 | /* turn on backlight */ |
| 1123 | gpio_direction_output(BACKLIGHT_EN, 1); | 1123 | gpio_direction_output(BACKLIGHT_EN, 1); |
| 1124 | gpio_direction_output(LCD_VDD_EN, 1); | 1124 | gpio_direction_output(LCD_VDD_EN, 1); |
| 1125 | /* enable backlight PWM 2 */ | 1125 | /* enable backlight PWM 2 */ |
| 1126 | if (pwm_init(1, 0, 0)) | 1126 | if (pwm_init(1, 0, 0)) |
| 1127 | goto error; | 1127 | goto error; |
| 1128 | /* duty cycle 500ns, period: 3000ns */ | 1128 | /* duty cycle 500ns, period: 3000ns */ |
| 1129 | if (pwm_config(1, 1000, 3000)) | 1129 | if (pwm_config(1, 1000, 3000)) |
| 1130 | goto error; | 1130 | goto error; |
| 1131 | if (pwm_enable(1)) | 1131 | if (pwm_enable(1)) |
| 1132 | goto error; | 1132 | goto error; |
| 1133 | return; | 1133 | return; |
| 1134 | 1134 | ||
| 1135 | error: | 1135 | error: |
| 1136 | puts("error init pwm for backlight\n"); | 1136 | puts("error init pwm for backlight\n"); |
| 1137 | return; | 1137 | return; |
| 1138 | } | 1138 | } |
| 1139 | #endif /* CONFIG_VIDEO_IPUV3 */ | 1139 | #endif /* CONFIG_VIDEO_IPUV3 */ |
| 1140 | 1140 | ||
| 1141 | /* | 1141 | /* |
| 1142 | * Do not overwrite the console | 1142 | * Do not overwrite the console |
| 1143 | * Use always serial for U-Boot console | 1143 | * Use always serial for U-Boot console |
| 1144 | */ | 1144 | */ |
| 1145 | int overwrite_console(void) | 1145 | int overwrite_console(void) |
| 1146 | { | 1146 | { |
| 1147 | return 1; | 1147 | return 1; |
| 1148 | } | 1148 | } |
| 1149 | 1149 | ||
| 1150 | int board_eth_init(bd_t *bis) | 1150 | int board_eth_init(bd_t *bis) |
| 1151 | { | 1151 | { |
| 1152 | #if defined(CONFIG_MAC_ADDR_IN_EEPROM) | 1152 | #if defined(CONFIG_MAC_ADDR_IN_EEPROM) |
| 1153 | 1153 | ||
| 1154 | uchar env_enetaddr[6]; | 1154 | uchar env_enetaddr[6]; |
| 1155 | int enetaddr_found; | 1155 | int enetaddr_found; |
| 1156 | 1156 | ||
| 1157 | enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr); | 1157 | enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr); |
| 1158 | 1158 | ||
| 1159 | uint8_t enetaddr[8]; | 1159 | uint8_t enetaddr[8]; |
| 1160 | int eeprom_mac_read; | 1160 | int eeprom_mac_read; |
| 1161 | 1161 | ||
| 1162 | /* Read Ethernet MAC address from EEPROM */ | 1162 | /* Read Ethernet MAC address from EEPROM */ |
| 1163 | eeprom_mac_read = smarcfimx6_read_mac_address(enetaddr); | 1163 | eeprom_mac_read = smarcfimx6_read_mac_address(enetaddr); |
| 1164 | 1164 | ||
| 1165 | /* | 1165 | /* |
| 1166 | * MAC address not present in the environment | 1166 | * MAC address not present in the environment |
| 1167 | * try and read the MAC address from EEPROM flash | 1167 | * try and read the MAC address from EEPROM flash |
| 1168 | * and set it. | 1168 | * and set it. |
| 1169 | */ | 1169 | */ |
| 1170 | if (!enetaddr_found) { | 1170 | if (!enetaddr_found) { |
| 1171 | if (eeprom_mac_read) | 1171 | if (eeprom_mac_read) |
| 1172 | /* Set Ethernet MAC address from EEPROM */ | 1172 | /* Set Ethernet MAC address from EEPROM */ |
| 1173 | smarcfimx6_sync_env_enetaddr(enetaddr); | 1173 | smarcfimx6_sync_env_enetaddr(enetaddr); |
| 1174 | } else { | 1174 | } else { |
| 1175 | /* | 1175 | /* |
| 1176 | * MAC address present in environment compare it with | 1176 | * MAC address present in environment compare it with |
| 1177 | * the MAC address in EEPROM and warn on mismatch | 1177 | * the MAC address in EEPROM and warn on mismatch |
| 1178 | */ | 1178 | */ |
| 1179 | if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6)) | 1179 | if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6)) |
| 1180 | printf("Warning: MAC address in EEPROM don't match " | 1180 | printf("Warning: MAC address in EEPROM don't match " |
| 1181 | "with the MAC address in the environment\n"); | 1181 | "with the MAC address in the environment\n"); |
| 1182 | printf("Default using MAC address from environment\n"); | 1182 | printf("Default using MAC address from environment\n"); |
| 1183 | } | 1183 | } |
| 1184 | 1184 | ||
| 1185 | #endif | 1185 | #endif |
| 1186 | 1186 | ||
| 1187 | setup_iomux_enet(); | 1187 | setup_iomux_enet(); |
| 1188 | setup_pcie(); | 1188 | setup_pcie(); |
| 1189 | 1189 | ||
| 1190 | return cpu_eth_init(bis); | 1190 | return cpu_eth_init(bis); |
| 1191 | } | 1191 | } |
| 1192 | 1192 | ||
| 1193 | int board_early_init_f(void) | 1193 | int board_early_init_f(void) |
| 1194 | { | 1194 | { |
| 1195 | setup_iomux_wdt(); | 1195 | setup_iomux_wdt(); |
| 1196 | setup_iomux_reset_out(); | 1196 | setup_iomux_reset_out(); |
| 1197 | setup_iomux_uart1(); | 1197 | setup_iomux_uart1(); |
| 1198 | setup_iomux_uart2(); | 1198 | setup_iomux_uart2(); |
| 1199 | setup_iomux_uart4(); | 1199 | setup_iomux_uart4(); |
| 1200 | setup_iomux_uart5(); | 1200 | setup_iomux_uart5(); |
| 1201 | #if defined(CONFIG_VIDEO_IPUV3) | 1201 | #if defined(CONFIG_VIDEO_IPUV3) |
| 1202 | setup_display(); | 1202 | setup_display(); |
| 1203 | #endif | 1203 | #endif |
| 1204 | 1204 | ||
| 1205 | #ifdef CONFIG_SYS_USE_SPINOR | 1205 | #ifdef CONFIG_SYS_USE_SPINOR |
| 1206 | /*Unlock SPI Flash*/ | 1206 | /*Unlock SPI Flash*/ |
| 1207 | gpio_direction_output(IMX_GPIO_NR(4,20), 1); | 1207 | gpio_direction_output(IMX_GPIO_NR(4,20), 1); |
| 1208 | setup_spinor(); | 1208 | setup_spinor(); |
| 1209 | /*Lock SPI Flash and Free SPI0*/ | 1209 | /*Lock SPI Flash and Free SPI0*/ |
| 1210 | gpio_direction_output(IMX_GPIO_NR(4,20), 0); | 1210 | gpio_direction_output(IMX_GPIO_NR(4,20), 0); |
| 1211 | #endif | 1211 | #endif |
| 1212 | 1212 | ||
| 1213 | setup_spi1(); | 1213 | setup_spi1(); |
| 1214 | setup_flexcan1(); | 1214 | setup_flexcan1(); |
| 1215 | setup_flexcan2(); | 1215 | setup_flexcan2(); |
| 1216 | setup_gpios(); | 1216 | setup_gpios(); |
| 1217 | 1217 | ||
| 1218 | #ifdef CONFIG_CMD_SATA | 1218 | #ifdef CONFIG_CMD_SATA |
| 1219 | setup_sata(); | 1219 | setup_sata(); |
| 1220 | #endif | 1220 | #endif |
| 1221 | 1221 | ||
| 1222 | return 0; | 1222 | return 0; |
| 1223 | } | 1223 | } |
| 1224 | 1224 | ||
| 1225 | int board_init(void) | 1225 | int board_init(void) |
| 1226 | { | 1226 | { |
| 1227 | /* address of boot parameters */ | 1227 | /* address of boot parameters */ |
| 1228 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; | 1228 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| 1229 | 1229 | ||
| 1230 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) | 1230 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) |
| 1231 | setup_epdc(); | 1231 | setup_epdc(); |
| 1232 | #endif | 1232 | #endif |
| 1233 | 1233 | ||
| 1234 | #ifdef CONFIG_SYS_I2C_MXC | 1234 | #ifdef CONFIG_SYS_I2C_MXC |
| 1235 | setup_i2c(2, CONFIG_SYS_I2C_SPEED, | 1235 | setup_i2c(2, CONFIG_SYS_I2C_SPEED, |
| 1236 | 0x70, &i2c_pad_info3); | 1236 | 0x70, &i2c_pad_info3); |
| 1237 | 1237 | ||
| 1238 | /* Configure I2C switch (PCA9546) to enable channel 0. */ | 1238 | /* Configure I2C switch (PCA9546) to enable channel 0. */ |
| 1239 | i2c_set_bus_num(2); | 1239 | i2c_set_bus_num(2); |
| 1240 | uint8_t i2cbuf; | 1240 | uint8_t i2cbuf; |
| 1241 | i2cbuf = CONFIG_SYS_I2C_PCA9546_ENABLE; | 1241 | i2cbuf = CONFIG_SYS_I2C_PCA9546_ENABLE; |
| 1242 | if (i2c_write(CONFIG_SYS_I2C_PCA9546_ADDR, 0, | 1242 | if (i2c_write(CONFIG_SYS_I2C_PCA9546_ADDR, 0, |
| 1243 | CONFIG_SYS_I2C_PCA9546_ADDR_LEN, &i2cbuf, 1)) { | 1243 | CONFIG_SYS_I2C_PCA9546_ADDR_LEN, &i2cbuf, 1)) { |
| 1244 | printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9546_ADDR); | 1244 | printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9546_ADDR); |
| 1245 | return 1; | 1245 | return 1; |
| 1246 | } | 1246 | } |
| 1247 | 1247 | ||
| 1248 | #endif | 1248 | #endif |
| 1249 | return 0; | 1249 | return 0; |
| 1250 | } | 1250 | } |
| 1251 | 1251 | ||
| 1252 | #ifdef CONFIG_CMD_BMODE | 1252 | #ifdef CONFIG_CMD_BMODE |
| 1253 | static const struct boot_mode board_boot_modes[] = { | 1253 | static const struct boot_mode board_boot_modes[] = { |
| 1254 | /* 4 bit bus width */ | 1254 | /* 4 bit bus width */ |
| 1255 | {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, | 1255 | {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, |
| 1256 | {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, | 1256 | {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, |
| 1257 | /* 8 bit bus width */ | 1257 | /* 8 bit bus width */ |
| 1258 | {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, | 1258 | {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, |
| 1259 | {NULL, 0}, | 1259 | {NULL, 0}, |
| 1260 | }; | 1260 | }; |
| 1261 | #endif | 1261 | #endif |
| 1262 | 1262 | ||
| 1263 | int board_late_init(void) | 1263 | int board_late_init(void) |
| 1264 | { | 1264 | { |
| 1265 | // Make sure we enable ECSPI2 clock | 1265 | // Make sure we enable ECSPI2 clock |
| 1266 | int reg; | 1266 | int reg; |
| 1267 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | 1267 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 1268 | reg = readl(&mxc_ccm->CCGR1); | 1268 | reg = readl(&mxc_ccm->CCGR1); |
| 1269 | reg |= MXC_CCM_CCGR1_ECSPI2S_MASK; | 1269 | reg |= MXC_CCM_CCGR1_ECSPI2S_MASK; |
| 1270 | writel(reg, &mxc_ccm->CCGR1); | 1270 | writel(reg, &mxc_ccm->CCGR1); |
| 1271 | #ifdef CONFIG_CMD_BMODE | 1271 | #ifdef CONFIG_CMD_BMODE |
| 1272 | add_board_boot_modes(board_boot_modes); | 1272 | add_board_boot_modes(board_boot_modes); |
| 1273 | #endif | 1273 | #endif |
| 1274 | 1274 | ||
| 1275 | #ifdef CONFIG_ENV_IS_IN_MMC | 1275 | #ifdef CONFIG_ENV_IS_IN_MMC |
| 1276 | board_late_mmc_env_init(); | 1276 | board_late_mmc_env_init(); |
| 1277 | #endif | 1277 | #endif |
| 1278 | 1278 | ||
| 1279 | /* Check Board Revision */ | 1279 | /* Check Board Revision */ |
| 1280 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, | 1280 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, |
| 1281 | 0x50, &i2c_pad_info1); | 1281 | 0x50, &i2c_pad_info1); |
| 1282 | 1282 | ||
| 1283 | struct smarcfimx6_id header; | 1283 | struct smarcfimx6_id header; |
| 1284 | 1284 | ||
| 1285 | if (read_eeprom(&header) < 0) | 1285 | if (read_eeprom(&header) < 0) |
| 1286 | puts("Could not get board ID.\n"); | 1286 | puts("Could not get board ID.\n"); |
| 1287 | 1287 | ||
| 1288 | if (revision_is_00a0(&header)) { | 1288 | if (revision_is_00a0(&header)) { |
| 1289 | puts("Board: SMARC-FiMX6 Rev.00A0\n"); | 1289 | puts("Board: SMARC-FiMX6 Rev.00A0\n"); |
| 1290 | 1290 | ||
| 1291 | } else if (revision_is_00b0(&header)) { | 1291 | } else if (revision_is_00b0(&header)) { |
| 1292 | puts("Board: SMARC-FiMX6 Rev.00B0\n"); | 1292 | puts("Board: SMARC-FiMX6 Rev.00B0\n"); |
| 1293 | 1293 | ||
| 1294 | } else if (revision_is_00c0(&header)) { | 1294 | } else if (revision_is_00c0(&header)) { |
| 1295 | puts("Board: SMARC-FiMX6 Rev.00C0\n"); | 1295 | puts("Board: SMARC-FiMX6 Rev.00C0\n"); |
| 1296 | 1296 | ||
| 1297 | } else { | 1297 | } else { |
| 1298 | puts("Board: SMARC-FiMX6, Cannot find Revision number from EEPROM\n"); | 1298 | puts("Board: SMARC-FiMX6, Cannot find Revision number from EEPROM\n"); |
| 1299 | 1299 | ||
| 1300 | return 0; | 1300 | return 0; |
| 1301 | } | 1301 | } |
| 1302 | 1302 | ||
| 1303 | /* SMARC BOOT_SEL*/ | 1303 | /* SMARC BOOT_SEL*/ |
| 1304 | if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | 1304 | if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { |
| 1305 | puts("BOOT_SEL Detected: OFF OFF OFF, Load zImage from Carrier SATA...\n"); | 1305 | puts("BOOT_SEL Detected: OFF OFF OFF, Load zImage from Carrier SATA...\n"); |
| 1306 | setenv("root", "/dev/sda1 rootwait rw "); | 1306 | setenv("root", "/dev/sda1 rootwait rw "); |
| 1307 | setenv("bootcmd", "sata init; sata read 0x12000000 0x800 0x4000; sata read 0x18000000 0x8000 0x800; bootz 0x12000000 - 0x18000000;"); | 1307 | setenv("bootcmd", "sata init; sata read 0x12000000 0x800 0x4000; sata read 0x18000000 0x8000 0x800; bootz 0x12000000 - 0x18000000;"); |
| 1308 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | 1308 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { |
| 1309 | puts("BOOT_SEL Detected: OFF OFF ON, USB Boot Up Not Defined...Carrier SPI Boot Not Supported...\n"); | 1309 | puts("BOOT_SEL Detected: OFF OFF ON, USB Boot Up Not Defined...Carrier SPI Boot Not Supported...\n"); |
| 1310 | hang(); | 1310 | hang(); |
| 1311 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | 1311 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { |
| 1312 | puts("BOOT_SEL Detected: OFF ON OFF, Load zImage from Carrier SDMMC...\n"); | 1312 | puts("BOOT_SEL Detected: OFF ON OFF, Load zImage from Carrier SDMMC...\n"); |
| 1313 | setenv_ulong("mmcdev", 1); | 1313 | setenv_ulong("mmcdev", 1); |
| 1314 | setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run loadzimage; run loadfdt; run mmcboot;"); | 1314 | setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;"); |
| 1315 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | 1315 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { |
| 1316 | puts("BOOT_SEL Detected: ON OFF OFF, Load zImage from Carrier SD Card...\n"); | 1316 | puts("BOOT_SEL Detected: ON OFF OFF, Load zImage from Carrier SD Card...\n"); |
| 1317 | setenv_ulong("mmcdev", 0); | 1317 | setenv_ulong("mmcdev", 0); |
| 1318 | setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run loadzimage; run loadfdt; run mmcboot;"); | 1318 | setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;"); |
| 1319 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | 1319 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { |
| 1320 | puts("BOOT_SEL Detected: OFF ON ON, Load zImage from Module eMMC Flash...\n"); | 1320 | puts("BOOT_SEL Detected: OFF ON ON, Load zImage from Module eMMC Flash...\n"); |
| 1321 | setenv_ulong("mmcdev", 2); | 1321 | setenv_ulong("mmcdev", 2); |
| 1322 | setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run loadzimage; run loadfdt; run mmcboot;"); | 1322 | setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;"); |
| 1323 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | 1323 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { |
| 1324 | puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n"); | 1324 | puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n"); |
| 1325 | setenv("bootcmd", "run netboot;"); | 1325 | setenv("bootcmd", "run netboot;"); |
| 1326 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | 1326 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { |
| 1327 | puts("Carrier SPI Boot 110\n"); | 1327 | puts("Carrier SPI Boot 110\n"); |
| 1328 | hang(); | 1328 | hang(); |
| 1329 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | 1329 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { |
| 1330 | puts("BOOT_SEL Detected: ON ON ON, MOdule SPI Boot up is Default, Load zImage from Module eMMC...\n"); | 1330 | puts("BOOT_SEL Detected: ON ON ON, MOdule SPI Boot up is Default, Load zImage from Module eMMC...\n"); |
| 1331 | setenv_ulong("mmcdev", 2); | 1331 | setenv_ulong("mmcdev", 2); |
| 1332 | setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run loadzimage; run loadfdt; run mmcboot;"); | 1332 | setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;"); |
| 1333 | } else { | 1333 | } else { |
| 1334 | puts("unsupported boot devices\n"); | 1334 | puts("unsupported boot devices\n"); |
| 1335 | hang(); | 1335 | hang(); |
| 1336 | } | 1336 | } |
| 1337 | 1337 | ||
| 1338 | return 0; | 1338 | return 0; |
| 1339 | } | 1339 | } |
| 1340 | 1340 | ||
| 1341 | #ifdef CONFIG_FASTBOOT | 1341 | #ifdef CONFIG_FASTBOOT |
| 1342 | 1342 | ||
| 1343 | void board_fastboot_setup(void) | 1343 | void board_fastboot_setup(void) |
| 1344 | { | 1344 | { |
| 1345 | switch (get_boot_device()) { | 1345 | switch (get_boot_device()) { |
| 1346 | #if defined(CONFIG_FASTBOOT_STORAGE_SATA) | 1346 | #if defined(CONFIG_FASTBOOT_STORAGE_SATA) |
| 1347 | case SATA_BOOT: | 1347 | case SATA_BOOT: |
| 1348 | if (!getenv("fastboot_dev")) | 1348 | if (!getenv("fastboot_dev")) |
| 1349 | setenv("fastboot_dev", "sata"); | 1349 | setenv("fastboot_dev", "sata"); |
| 1350 | if (!getenv("bootcmd")) | 1350 | if (!getenv("bootcmd")) |
| 1351 | setenv("bootcmd", "booti sata"); | 1351 | setenv("bootcmd", "booti sata"); |
| 1352 | break; | 1352 | break; |
| 1353 | #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/ | 1353 | #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/ |
| 1354 | #if defined(CONFIG_FASTBOOT_STORAGE_MMC) | 1354 | #if defined(CONFIG_FASTBOOT_STORAGE_MMC) |
| 1355 | case SD2_BOOT: | 1355 | case SD2_BOOT: |
| 1356 | case MMC2_BOOT: | 1356 | case MMC2_BOOT: |
| 1357 | if (!getenv("fastboot_dev")) | 1357 | if (!getenv("fastboot_dev")) |
| 1358 | setenv("fastboot_dev", "mmc0"); | 1358 | setenv("fastboot_dev", "mmc0"); |
| 1359 | if (!getenv("bootcmd")) | 1359 | if (!getenv("bootcmd")) |
| 1360 | setenv("bootcmd", "booti mmc0"); | 1360 | setenv("bootcmd", "booti mmc0"); |
| 1361 | break; | 1361 | break; |
| 1362 | case SD3_BOOT: | 1362 | case SD3_BOOT: |
| 1363 | case MMC3_BOOT: | 1363 | case MMC3_BOOT: |
| 1364 | if (!getenv("fastboot_dev")) | 1364 | if (!getenv("fastboot_dev")) |
| 1365 | setenv("fastboot_dev", "mmc1"); | 1365 | setenv("fastboot_dev", "mmc1"); |
| 1366 | if (!getenv("bootcmd")) | 1366 | if (!getenv("bootcmd")) |
| 1367 | setenv("bootcmd", "booti mmc1"); | 1367 | setenv("bootcmd", "booti mmc1"); |
| 1368 | break; | 1368 | break; |
| 1369 | case MMC4_BOOT: | 1369 | case MMC4_BOOT: |
| 1370 | if (!getenv("fastboot_dev")) | 1370 | if (!getenv("fastboot_dev")) |
| 1371 | setenv("fastboot_dev", "mmc2"); | 1371 | setenv("fastboot_dev", "mmc2"); |
| 1372 | if (!getenv("bootcmd")) | 1372 | if (!getenv("bootcmd")) |
| 1373 | setenv("bootcmd", "booti mmc2"); | 1373 | setenv("bootcmd", "booti mmc2"); |
| 1374 | break; | 1374 | break; |
| 1375 | #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ | 1375 | #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ |
| 1376 | default: | 1376 | default: |
| 1377 | printf("unsupported boot devices\n"); | 1377 | printf("unsupported boot devices\n"); |
| 1378 | break; | 1378 | break; |
| 1379 | } | 1379 | } |
| 1380 | 1380 | ||
| 1381 | } | 1381 | } |
| 1382 | 1382 | ||
| 1383 | #ifdef CONFIG_ANDROID_RECOVERY | 1383 | #ifdef CONFIG_ANDROID_RECOVERY |
| 1384 | 1384 | ||
| 1385 | #define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5) | 1385 | #define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5) |
| 1386 | iomux_v3_cfg_t const recovery_key_pads[] = { | 1386 | iomux_v3_cfg_t const recovery_key_pads[] = { |
| 1387 | (MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)), | 1387 | (MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
| 1388 | }; | 1388 | }; |
| 1389 | 1389 | ||
| 1390 | int check_recovery_cmd_file(void) | 1390 | int check_recovery_cmd_file(void) |
| 1391 | { | 1391 | { |
| 1392 | int button_pressed = 0; | 1392 | int button_pressed = 0; |
| 1393 | int recovery_mode = 0; | 1393 | int recovery_mode = 0; |
| 1394 | 1394 | ||
| 1395 | recovery_mode = recovery_check_and_clean_flag(); | 1395 | recovery_mode = recovery_check_and_clean_flag(); |
| 1396 | 1396 | ||
| 1397 | /* Check Recovery Combo Button press or not. */ | 1397 | /* Check Recovery Combo Button press or not. */ |
| 1398 | imx_iomux_v3_setup_multiple_pads(recovery_key_pads, | 1398 | imx_iomux_v3_setup_multiple_pads(recovery_key_pads, |
| 1399 | ARRAY_SIZE(recovery_key_pads)); | 1399 | ARRAY_SIZE(recovery_key_pads)); |
| 1400 | 1400 | ||
| 1401 | gpio_direction_input(GPIO_VOL_DN_KEY); | 1401 | gpio_direction_input(GPIO_VOL_DN_KEY); |
| 1402 | 1402 | ||
| 1403 | if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ | 1403 | if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ |
| 1404 | button_pressed = 1; | 1404 | button_pressed = 1; |
| 1405 | printf("Recovery key pressed\n"); | 1405 | printf("Recovery key pressed\n"); |
| 1406 | } | 1406 | } |
| 1407 | 1407 | ||
| 1408 | return recovery_mode || button_pressed; | 1408 | return recovery_mode || button_pressed; |
| 1409 | } | 1409 | } |
| 1410 | 1410 | ||
| 1411 | void board_recovery_setup(void) | 1411 | void board_recovery_setup(void) |
| 1412 | { | 1412 | { |
| 1413 | int bootdev = get_boot_device(); | 1413 | int bootdev = get_boot_device(); |
| 1414 | 1414 | ||
| 1415 | switch (bootdev) { | 1415 | switch (bootdev) { |
| 1416 | #if defined(CONFIG_FASTBOOT_STORAGE_SATA) | 1416 | #if defined(CONFIG_FASTBOOT_STORAGE_SATA) |
| 1417 | case SATA_BOOT: | 1417 | case SATA_BOOT: |
| 1418 | if (!getenv("bootcmd_android_recovery")) | 1418 | if (!getenv("bootcmd_android_recovery")) |
| 1419 | setenv("bootcmd_android_recovery", | 1419 | setenv("bootcmd_android_recovery", |
| 1420 | "booti sata recovery"); | 1420 | "booti sata recovery"); |
| 1421 | break; | 1421 | break; |
| 1422 | #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/ | 1422 | #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/ |
| 1423 | #if defined(CONFIG_FASTBOOT_STORAGE_MMC) | 1423 | #if defined(CONFIG_FASTBOOT_STORAGE_MMC) |
| 1424 | case SD2_BOOT: | 1424 | case SD2_BOOT: |
| 1425 | case MMC2_BOOT: | 1425 | case MMC2_BOOT: |
| 1426 | if (!getenv("bootcmd_android_recovery")) | 1426 | if (!getenv("bootcmd_android_recovery")) |
| 1427 | setenv("bootcmd_android_recovery", | 1427 | setenv("bootcmd_android_recovery", |
| 1428 | "booti mmc0 recovery"); | 1428 | "booti mmc0 recovery"); |
| 1429 | break; | 1429 | break; |
| 1430 | case SD3_BOOT: | 1430 | case SD3_BOOT: |
| 1431 | case MMC3_BOOT: | 1431 | case MMC3_BOOT: |
| 1432 | if (!getenv("bootcmd_android_recovery")) | 1432 | if (!getenv("bootcmd_android_recovery")) |
| 1433 | setenv("bootcmd_android_recovery", | 1433 | setenv("bootcmd_android_recovery", |
| 1434 | "booti mmc1 recovery"); | 1434 | "booti mmc1 recovery"); |
| 1435 | break; | 1435 | break; |
| 1436 | case MMC4_BOOT: | 1436 | case MMC4_BOOT: |
| 1437 | if (!getenv("bootcmd_android_recovery")) | 1437 | if (!getenv("bootcmd_android_recovery")) |
| 1438 | setenv("bootcmd_android_recovery", | 1438 | setenv("bootcmd_android_recovery", |
| 1439 | "booti mmc2 recovery"); | 1439 | "booti mmc2 recovery"); |
| 1440 | break; | 1440 | break; |
| 1441 | #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ | 1441 | #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ |
| 1442 | default: | 1442 | default: |
| 1443 | printf("Unsupported bootup device for recovery: dev: %d\n", | 1443 | printf("Unsupported bootup device for recovery: dev: %d\n", |
| 1444 | bootdev); | 1444 | bootdev); |
| 1445 | return; | 1445 | return; |
| 1446 | } | 1446 | } |
| 1447 | 1447 | ||
| 1448 | printf("setup env for recovery..\n"); | 1448 | printf("setup env for recovery..\n"); |
| 1449 | setenv("bootcmd", "run bootcmd_android_recovery"); | 1449 | setenv("bootcmd", "run bootcmd_android_recovery"); |
| 1450 | } | 1450 | } |
| 1451 | 1451 | ||
| 1452 | #endif /*CONFIG_ANDROID_RECOVERY*/ | 1452 | #endif /*CONFIG_ANDROID_RECOVERY*/ |
| 1453 | 1453 | ||
| 1454 | #endif /*CONFIG_FASTBOOT*/ | 1454 | #endif /*CONFIG_FASTBOOT*/ |
| 1455 | 1455 | ||
| 1456 | #ifdef CONFIG_IMX_UDC | 1456 | #ifdef CONFIG_IMX_UDC |
| 1457 | iomux_v3_cfg_t const otg_udc_pads[] = { | 1457 | iomux_v3_cfg_t const otg_udc_pads[] = { |
| 1458 | (MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP)), | 1458 | (MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP)), |
| 1459 | }; | 1459 | }; |
| 1460 | void udc_pins_setting(void) | 1460 | void udc_pins_setting(void) |
| 1461 | { | 1461 | { |
| 1462 | imx_iomux_v3_setup_multiple_pads(otg_udc_pads, | 1462 | imx_iomux_v3_setup_multiple_pads(otg_udc_pads, |
| 1463 | ARRAY_SIZE(otg_udc_pads)); | 1463 | ARRAY_SIZE(otg_udc_pads)); |
| 1464 | 1464 | ||
| 1465 | /*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/ | 1465 | /*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/ |
| 1466 | mxc_iomux_set_gpr_register(1, 13, 1, 0); | 1466 | mxc_iomux_set_gpr_register(1, 13, 1, 0); |
| 1467 | } | 1467 | } |
| 1468 | #endif /*CONFIG_IMX_UDC*/ | 1468 | #endif /*CONFIG_IMX_UDC*/ |
| 1469 | 1469 | ||
| 1470 | #ifdef CONFIG_USB_EHCI_MX6 | 1470 | #ifdef CONFIG_USB_EHCI_MX6 |
| 1471 | iomux_v3_cfg_t const usb_otg_pads[] = { | 1471 | iomux_v3_cfg_t const usb_otg_pads[] = { |
| 1472 | MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(WEAK_PULLUP), | 1472 | MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(WEAK_PULLUP), |
| 1473 | MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP), | 1473 | MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP), |
| 1474 | /* OTG Power enable */ | 1474 | /* OTG Power enable */ |
| 1475 | MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(OUTPUT_40OHM), | 1475 | MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(OUTPUT_40OHM), |
| 1476 | }; | 1476 | }; |
| 1477 | 1477 | ||
| 1478 | iomux_v3_cfg_t const usb_hc1_pads[] = { | 1478 | iomux_v3_cfg_t const usb_hc1_pads[] = { |
| 1479 | MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(WEAK_PULLUP), | 1479 | MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(WEAK_PULLUP), |
| 1480 | /* USB1 Power enable */ | 1480 | /* USB1 Power enable */ |
| 1481 | MX6_PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(OUTPUT_40OHM), | 1481 | MX6_PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(OUTPUT_40OHM), |
| 1482 | }; | 1482 | }; |
| 1483 | 1483 | ||
| 1484 | int board_ehci_hcd_init(int port) | 1484 | int board_ehci_hcd_init(int port) |
| 1485 | { | 1485 | { |
| 1486 | switch (port) { | 1486 | switch (port) { |
| 1487 | case 0: | 1487 | case 0: |
| 1488 | imx_iomux_v3_setup_multiple_pads(usb_otg_pads, | 1488 | imx_iomux_v3_setup_multiple_pads(usb_otg_pads, |
| 1489 | ARRAY_SIZE(usb_otg_pads)); | 1489 | ARRAY_SIZE(usb_otg_pads)); |
| 1490 | 1490 | ||
| 1491 | /*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/ | 1491 | /*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/ |
| 1492 | mxc_iomux_set_gpr_register(1, 13, 1, 0); | 1492 | mxc_iomux_set_gpr_register(1, 13, 1, 0); |
| 1493 | break; | 1493 | break; |
| 1494 | case 1: | 1494 | case 1: |
| 1495 | imx_iomux_v3_setup_multiple_pads(usb_hc1_pads, | 1495 | imx_iomux_v3_setup_multiple_pads(usb_hc1_pads, |
| 1496 | ARRAY_SIZE(usb_hc1_pads)); | 1496 | ARRAY_SIZE(usb_hc1_pads)); |
| 1497 | break; | 1497 | break; |
| 1498 | default: | 1498 | default: |
| 1499 | printf("MXC USB port %d not yet supported\n", port); | 1499 | printf("MXC USB port %d not yet supported\n", port); |
| 1500 | return 1; | 1500 | return 1; |
| 1501 | } | 1501 | } |
| 1502 | return 0; | 1502 | return 0; |
| 1503 | } | 1503 | } |
| 1504 | 1504 | ||
| 1505 | int board_ehci_power(int port, int on) | 1505 | int board_ehci_power(int port, int on) |
| 1506 | { | 1506 | { |
| 1507 | switch (port) { | 1507 | switch (port) { |
| 1508 | case 0: | 1508 | case 0: |
| 1509 | /* Set USB OTG Over Current */ | 1509 | /* Set USB OTG Over Current */ |
| 1510 | gpio_direction_input(IMX_GPIO_NR(1, 30)); | 1510 | gpio_direction_input(IMX_GPIO_NR(1, 30)); |
| 1511 | /* Trun On USB OTG Power */ | 1511 | /* Trun On USB OTG Power */ |
| 1512 | gpio_direction_output(IMX_GPIO_NR(1, 29),1); | 1512 | gpio_direction_output(IMX_GPIO_NR(1, 29),1); |
| 1513 | break; | 1513 | break; |
| 1514 | case 1: | 1514 | case 1: |
| 1515 | if (on){ | 1515 | if (on){ |
| 1516 | /* Set USB1 Over Current */ | 1516 | /* Set USB1 Over Current */ |
| 1517 | gpio_direction_input(IMX_GPIO_NR(1, 27)); | 1517 | gpio_direction_input(IMX_GPIO_NR(1, 27)); |
| 1518 | /* Trun On USB1 Power */ | 1518 | /* Trun On USB1 Power */ |
| 1519 | gpio_direction_output(IMX_GPIO_NR(1, 26),1); | 1519 | gpio_direction_output(IMX_GPIO_NR(1, 26),1); |
| 1520 | } | 1520 | } |
| 1521 | else | 1521 | else |
| 1522 | gpio_direction_output(IMX_GPIO_NR(1, 26), 0); | 1522 | gpio_direction_output(IMX_GPIO_NR(1, 26), 0); |
| 1523 | break; | 1523 | break; |
| 1524 | default: | 1524 | default: |
| 1525 | printf("MXC USB port %d not yet supported\n", port); | 1525 | printf("MXC USB port %d not yet supported\n", port); |
| 1526 | return 1; | 1526 | return 1; |
| 1527 | } | 1527 | } |
| 1528 | return 0; | 1528 | return 0; |
| 1529 | } | 1529 | } |
| 1530 | #endif | 1530 | #endif |
| 1531 | 1531 |