Eric Lee / smarc-uboot

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Commit 32e9ec1f8812ffe5874a2e3a0a1b8fe85c489ab8

Authored by Simon Glass
1 parent 7337fcd8c0
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

x86: Move link to use driver model for SCSI 

As a demonstration of how to use SCSI with driver model, move link over
to use this. This patch needs more work, but illustrates the concept.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Showing 4 changed files with 27 additions and 1 deletions Inline Diff

arch/x86/cpu/ivybridge/sata.c
Diff comments   View file @ 32e9ec1
1 /* 1 /*
2 * From Coreboot 2 * From Coreboot
3 * Copyright (C) 2008-2009 coresystems GmbH 3 * Copyright (C) 2008-2009 coresystems GmbH
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0 5 * SPDX-License-Identifier: GPL-2.0
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <ahci.h>
9 #include <dm.h> 10 #include <dm.h>
10 #include <fdtdec.h> 11 #include <fdtdec.h>
11 #include <asm/io.h> 12 #include <asm/io.h>
12 #include <asm/pch_common.h> 13 #include <asm/pch_common.h>
13 #include <asm/pci.h> 14 #include <asm/pci.h>
14 #include <asm/arch/pch.h> 15 #include <asm/arch/pch.h>
15 16
16 DECLARE_GLOBAL_DATA_PTR; 17 DECLARE_GLOBAL_DATA_PTR;
17 18
18 static void common_sata_init(struct udevice *dev, unsigned int port_map) 19 static void common_sata_init(struct udevice *dev, unsigned int port_map)
19 { 20 {
20 u32 reg32; 21 u32 reg32;
21 u16 reg16; 22 u16 reg16;
22 23
23 /* Set IDE I/O Configuration */ 24 /* Set IDE I/O Configuration */
24 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; 25 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
25 dm_pci_write_config32(dev, IDE_CONFIG, reg32); 26 dm_pci_write_config32(dev, IDE_CONFIG, reg32);
26 27
27 /* Port enable */ 28 /* Port enable */
28 dm_pci_read_config16(dev, 0x92, &reg16); 29 dm_pci_read_config16(dev, 0x92, &reg16);
29 reg16 &= ~0x3f; 30 reg16 &= ~0x3f;
30 reg16 |= port_map; 31 reg16 |= port_map;
31 dm_pci_write_config16(dev, 0x92, reg16); 32 dm_pci_write_config16(dev, 0x92, reg16);
32 33
33 /* SATA Initialization register */ 34 /* SATA Initialization register */
34 port_map &= 0xff; 35 port_map &= 0xff;
35 dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183); 36 dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
36 } 37 }
37 38
38 static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch) 39 static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)
39 { 40 {
40 unsigned int port_map, speed_support, port_tx; 41 unsigned int port_map, speed_support, port_tx;
41 const void *blob = gd->fdt_blob; 42 const void *blob = gd->fdt_blob;
42 int node = dev_of_offset(dev); 43 int node = dev_of_offset(dev);
43 const char *mode; 44 const char *mode;
44 u32 reg32; 45 u32 reg32;
45 u16 reg16; 46 u16 reg16;
46 47
47 debug("SATA: Initializing...\n"); 48 debug("SATA: Initializing...\n");
48 49
49 /* SATA configuration */ 50 /* SATA configuration */
50 port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); 51 port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
51 speed_support = fdtdec_get_int(blob, node, 52 speed_support = fdtdec_get_int(blob, node,
52 "sata_interface_speed_support", 0); 53 "sata_interface_speed_support", 0);
53 54
54 mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); 55 mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
55 if (!mode || !strcmp(mode, "ahci")) { 56 if (!mode || !strcmp(mode, "ahci")) {
56 ulong abar; 57 ulong abar;
57 58
58 debug("SATA: Controller in AHCI mode\n"); 59 debug("SATA: Controller in AHCI mode\n");
59 60
60 /* Set timings */ 61 /* Set timings */
61 dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | 62 dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
62 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | 63 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
63 IDE_PPE0 | IDE_IE0 | IDE_TIME0); 64 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
64 dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | 65 dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
65 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); 66 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
66 67
67 /* Sync DMA */ 68 /* Sync DMA */
68 dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); 69 dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
69 dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); 70 dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
70 71
71 common_sata_init(dev, 0x8000 | port_map); 72 common_sata_init(dev, 0x8000 | port_map);
72 73
73 /* Initialize AHCI memory-mapped space */ 74 /* Initialize AHCI memory-mapped space */
74 abar = dm_pci_read_bar32(dev, 5); 75 abar = dm_pci_read_bar32(dev, 5);
75 debug("ABAR: %08lx\n", abar); 76 debug("ABAR: %08lx\n", abar);
76 /* CAP (HBA Capabilities) : enable power management */ 77 /* CAP (HBA Capabilities) : enable power management */
77 reg32 = readl(abar + 0x00); 78 reg32 = readl(abar + 0x00);
78 reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ 79 reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */
79 reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ 80 reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
80 /* Set ISS, if available */ 81 /* Set ISS, if available */
81 if (speed_support) { 82 if (speed_support) {
82 reg32 &= ~0x00f00000; 83 reg32 &= ~0x00f00000;
83 reg32 |= (speed_support & 0x03) << 20; 84 reg32 |= (speed_support & 0x03) << 20;
84 } 85 }
85 writel(reg32, abar + 0x00); 86 writel(reg32, abar + 0x00);
86 /* PI (Ports implemented) */ 87 /* PI (Ports implemented) */
87 writel(port_map, abar + 0x0c); 88 writel(port_map, abar + 0x0c);
88 (void) readl(abar + 0x0c); /* Read back 1 */ 89 (void) readl(abar + 0x0c); /* Read back 1 */
89 (void) readl(abar + 0x0c); /* Read back 2 */ 90 (void) readl(abar + 0x0c); /* Read back 2 */
90 /* CAP2 (HBA Capabilities Extended)*/ 91 /* CAP2 (HBA Capabilities Extended)*/
91 reg32 = readl(abar + 0x24); 92 reg32 = readl(abar + 0x24);
92 reg32 &= ~0x00000002; 93 reg32 &= ~0x00000002;
93 writel(reg32, abar + 0x24); 94 writel(reg32, abar + 0x24);
94 /* VSP (Vendor Specific Register */ 95 /* VSP (Vendor Specific Register */
95 reg32 = readl(abar + 0xa0); 96 reg32 = readl(abar + 0xa0);
96 reg32 &= ~0x00000005; 97 reg32 &= ~0x00000005;
97 writel(reg32, abar + 0xa0); 98 writel(reg32, abar + 0xa0);
98 } else if (!strcmp(mode, "combined")) { 99 } else if (!strcmp(mode, "combined")) {
99 debug("SATA: Controller in combined mode\n"); 100 debug("SATA: Controller in combined mode\n");
100 101
101 /* No AHCI: clear AHCI base */ 102 /* No AHCI: clear AHCI base */
102 dm_pci_write_bar32(dev, 5, 0x00000000); 103 dm_pci_write_bar32(dev, 5, 0x00000000);
103 /* And without AHCI BAR no memory decoding */ 104 /* And without AHCI BAR no memory decoding */
104 dm_pci_read_config16(dev, PCI_COMMAND, &reg16); 105 dm_pci_read_config16(dev, PCI_COMMAND, &reg16);
105 reg16 &= ~PCI_COMMAND_MEMORY; 106 reg16 &= ~PCI_COMMAND_MEMORY;
106 dm_pci_write_config16(dev, PCI_COMMAND, reg16); 107 dm_pci_write_config16(dev, PCI_COMMAND, reg16);
107 108
108 dm_pci_write_config8(dev, 0x09, 0x80); 109 dm_pci_write_config8(dev, 0x09, 0x80);
109 110
110 /* Set timings */ 111 /* Set timings */
111 dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | 112 dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
112 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); 113 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
113 dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | 114 dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
114 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | 115 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
115 IDE_PPE0 | IDE_IE0 | IDE_TIME0); 116 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
116 117
117 /* Sync DMA */ 118 /* Sync DMA */
118 dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); 119 dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
119 dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); 120 dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
120 121
121 common_sata_init(dev, port_map); 122 common_sata_init(dev, port_map);
122 } else { 123 } else {
123 debug("SATA: Controller in plain-ide mode\n"); 124 debug("SATA: Controller in plain-ide mode\n");
124 125
125 /* No AHCI: clear AHCI base */ 126 /* No AHCI: clear AHCI base */
126 dm_pci_write_bar32(dev, 5, 0x00000000); 127 dm_pci_write_bar32(dev, 5, 0x00000000);
127 128
128 /* And without AHCI BAR no memory decoding */ 129 /* And without AHCI BAR no memory decoding */
129 dm_pci_read_config16(dev, PCI_COMMAND, &reg16); 130 dm_pci_read_config16(dev, PCI_COMMAND, &reg16);
130 reg16 &= ~PCI_COMMAND_MEMORY; 131 reg16 &= ~PCI_COMMAND_MEMORY;
131 dm_pci_write_config16(dev, PCI_COMMAND, reg16); 132 dm_pci_write_config16(dev, PCI_COMMAND, reg16);
132 133
133 /* 134 /*
134 * Native mode capable on both primary and secondary (0xa) 135 * Native mode capable on both primary and secondary (0xa)
135 * OR'ed with enabled (0x50) = 0xf 136 * OR'ed with enabled (0x50) = 0xf
136 */ 137 */
137 dm_pci_write_config8(dev, 0x09, 0x8f); 138 dm_pci_write_config8(dev, 0x09, 0x8f);
138 139
139 /* Set timings */ 140 /* Set timings */
140 dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | 141 dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
141 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | 142 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
142 IDE_PPE0 | IDE_IE0 | IDE_TIME0); 143 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
143 dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | 144 dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
144 IDE_SITRE | IDE_ISP_3_CLOCKS | 145 IDE_SITRE | IDE_ISP_3_CLOCKS |
145 IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); 146 IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
146 147
147 /* Sync DMA */ 148 /* Sync DMA */
148 dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); 149 dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
149 dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); 150 dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
150 151
151 common_sata_init(dev, port_map); 152 common_sata_init(dev, port_map);
152 } 153 }
153 154
154 /* Set Gen3 Transmitter settings if needed */ 155 /* Set Gen3 Transmitter settings if needed */
155 port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0); 156 port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
156 if (port_tx) 157 if (port_tx)
157 pch_iobp_update(pch, SATA_IOBP_SP0G3IR, 0, port_tx); 158 pch_iobp_update(pch, SATA_IOBP_SP0G3IR, 0, port_tx);
158 159
159 port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0); 160 port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
160 if (port_tx) 161 if (port_tx)
161 pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx); 162 pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);
162 163
163 /* Additional Programming Requirements */ 164 /* Additional Programming Requirements */
164 pch_common_sir_write(dev, 0x04, 0x00001600); 165 pch_common_sir_write(dev, 0x04, 0x00001600);
165 pch_common_sir_write(dev, 0x28, 0xa0000033); 166 pch_common_sir_write(dev, 0x28, 0xa0000033);
166 reg32 = pch_common_sir_read(dev, 0x54); 167 reg32 = pch_common_sir_read(dev, 0x54);
167 reg32 &= 0xff000000; 168 reg32 &= 0xff000000;
168 reg32 |= 0x5555aa; 169 reg32 |= 0x5555aa;
169 pch_common_sir_write(dev, 0x54, reg32); 170 pch_common_sir_write(dev, 0x54, reg32);
170 pch_common_sir_write(dev, 0x64, 0xcccc8484); 171 pch_common_sir_write(dev, 0x64, 0xcccc8484);
171 reg32 = pch_common_sir_read(dev, 0x68); 172 reg32 = pch_common_sir_read(dev, 0x68);
172 reg32 &= 0xffff0000; 173 reg32 &= 0xffff0000;
173 reg32 |= 0xcccc; 174 reg32 |= 0xcccc;
174 pch_common_sir_write(dev, 0x68, reg32); 175 pch_common_sir_write(dev, 0x68, reg32);
175 reg32 = pch_common_sir_read(dev, 0x78); 176 reg32 = pch_common_sir_read(dev, 0x78);
176 reg32 &= 0x0000ffff; 177 reg32 &= 0x0000ffff;
177 reg32 |= 0x88880000; 178 reg32 |= 0x88880000;
178 pch_common_sir_write(dev, 0x78, reg32); 179 pch_common_sir_write(dev, 0x78, reg32);
179 pch_common_sir_write(dev, 0x84, 0x001c7000); 180 pch_common_sir_write(dev, 0x84, 0x001c7000);
180 pch_common_sir_write(dev, 0x88, 0x88338822); 181 pch_common_sir_write(dev, 0x88, 0x88338822);
181 pch_common_sir_write(dev, 0xa0, 0x001c7000); 182 pch_common_sir_write(dev, 0xa0, 0x001c7000);
182 pch_common_sir_write(dev, 0xc4, 0x0c0c0c0c); 183 pch_common_sir_write(dev, 0xc4, 0x0c0c0c0c);
183 pch_common_sir_write(dev, 0xc8, 0x0c0c0c0c); 184 pch_common_sir_write(dev, 0xc8, 0x0c0c0c0c);
184 pch_common_sir_write(dev, 0xd4, 0x10000000); 185 pch_common_sir_write(dev, 0xd4, 0x10000000);
185 186
186 pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000); 187 pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000);
187 pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100); 188 pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100);
188 } 189 }
189 190
190 static void bd82x6x_sata_enable(struct udevice *dev) 191 static void bd82x6x_sata_enable(struct udevice *dev)
191 { 192 {
192 const void *blob = gd->fdt_blob; 193 const void *blob = gd->fdt_blob;
193 int node = dev_of_offset(dev); 194 int node = dev_of_offset(dev);
194 unsigned port_map; 195 unsigned port_map;
195 const char *mode; 196 const char *mode;
196 u16 map = 0; 197 u16 map = 0;
197 198
198 /* 199 /*
199 * Set SATA controller mode early so the resource allocator can 200 * Set SATA controller mode early so the resource allocator can
200 * properly assign IO/Memory resources for the controller. 201 * properly assign IO/Memory resources for the controller.
201 */ 202 */
202 mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); 203 mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
203 if (mode && !strcmp(mode, "ahci")) 204 if (mode && !strcmp(mode, "ahci"))
204 map = 0x0060; 205 map = 0x0060;
205 port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); 206 port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
206 207
207 map |= (port_map ^ 0x3f) << 8; 208 map |= (port_map ^ 0x3f) << 8;
208 dm_pci_write_config16(dev, 0x90, map); 209 dm_pci_write_config16(dev, 0x90, map);
209 } 210 }
210 211
212 static int bd82x6x_sata_bind(struct udevice *dev)
213 {
214 struct udevice *scsi_dev;
215 int ret;
216
217 if (gd->flags & GD_FLG_RELOC) {
218 ret = ahci_bind_scsi(dev, &scsi_dev);
219 if (ret)
220 return ret;
221 }
222
223 return 0;
224 }
225
211 static int bd82x6x_sata_probe(struct udevice *dev) 226 static int bd82x6x_sata_probe(struct udevice *dev)
212 { 227 {
213 struct udevice *pch; 228 struct udevice *pch;
214 int ret; 229 int ret;
215 230
216 ret = uclass_first_device_err(UCLASS_PCH, &pch); 231 ret = uclass_first_device_err(UCLASS_PCH, &pch);
217 if (ret) 232 if (ret)
218 return ret; 233 return ret;
219 234
220 if (!(gd->flags & GD_FLG_RELOC)) 235 if (!(gd->flags & GD_FLG_RELOC))
221 bd82x6x_sata_enable(dev); 236 bd82x6x_sata_enable(dev);
222 else 237 else {
223 bd82x6x_sata_init(dev, pch); 238 bd82x6x_sata_init(dev, pch);
239 ret = ahci_probe_scsi(dev);
240 if (ret)
241 return ret;
242 }
224 243
225 return 0; 244 return 0;
226 } 245 }
227 246
228 static const struct udevice_id bd82x6x_ahci_ids[] = { 247 static const struct udevice_id bd82x6x_ahci_ids[] = {
229 { .compatible = "intel,pantherpoint-ahci" }, 248 { .compatible = "intel,pantherpoint-ahci" },
230 { } 249 { }
231 }; 250 };
232 251
233 U_BOOT_DRIVER(ahci_ivybridge_drv) = { 252 U_BOOT_DRIVER(ahci_ivybridge_drv) = {
234 .name = "ahci_ivybridge", 253 .name = "ahci_ivybridge",
235 .id = UCLASS_AHCI, 254 .id = UCLASS_AHCI,
236 .of_match = bd82x6x_ahci_ids, 255 .of_match = bd82x6x_ahci_ids,
256 .bind = bd82x6x_sata_bind,
237 .probe = bd82x6x_sata_probe, 257 .probe = bd82x6x_sata_probe,
238 }; 258 };
239 259
configs/chromebook_link64_defconfig
Diff comments   View file @ 32e9ec1
1 CONFIG_X86=y 1 CONFIG_X86=y
2 CONFIG_SPL_GPIO_SUPPORT=y 2 CONFIG_SPL_GPIO_SUPPORT=y
3 CONFIG_SPL_LIBCOMMON_SUPPORT=y 3 CONFIG_SPL_LIBCOMMON_SUPPORT=y
4 CONFIG_SPL_LIBGENERIC_SUPPORT=y 4 CONFIG_SPL_LIBGENERIC_SUPPORT=y
5 CONFIG_SYS_MALLOC_F_LEN=0x2000 5 CONFIG_SYS_MALLOC_F_LEN=0x2000
6 CONFIG_SPL_SERIAL_SUPPORT=y 6 CONFIG_SPL_SERIAL_SUPPORT=y
7 CONFIG_SPL_SPI_FLASH_SUPPORT=y 7 CONFIG_SPL_SPI_FLASH_SUPPORT=y
8 CONFIG_SPL_SPI_SUPPORT=y 8 CONFIG_SPL_SPI_SUPPORT=y
9 CONFIG_X86_RUN_64BIT=y 9 CONFIG_X86_RUN_64BIT=y
10 CONFIG_VENDOR_GOOGLE=y 10 CONFIG_VENDOR_GOOGLE=y
11 CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" 11 CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
12 CONFIG_TARGET_CHROMEBOOK_LINK64=y 12 CONFIG_TARGET_CHROMEBOOK_LINK64=y
13 CONFIG_DEBUG_UART=y 13 CONFIG_DEBUG_UART=y
14 CONFIG_ENABLE_MRC_CACHE=y 14 CONFIG_ENABLE_MRC_CACHE=y
15 CONFIG_HAVE_MRC=y 15 CONFIG_HAVE_MRC=y
16 CONFIG_SMP=y 16 CONFIG_SMP=y
17 CONFIG_HAVE_VGA_BIOS=y 17 CONFIG_HAVE_VGA_BIOS=y
18 CONFIG_FIT=y 18 CONFIG_FIT=y
19 CONFIG_SPL_LOAD_FIT=y 19 CONFIG_SPL_LOAD_FIT=y
20 CONFIG_BOOTSTAGE=y 20 CONFIG_BOOTSTAGE=y
21 CONFIG_BOOTSTAGE_REPORT=y 21 CONFIG_BOOTSTAGE_REPORT=y
22 CONFIG_SYS_CONSOLE_INFO_QUIET=y 22 CONFIG_SYS_CONSOLE_INFO_QUIET=y
23 CONFIG_SPL_SYS_MALLOC_SIMPLE=y 23 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
24 CONFIG_SPL_CPU_SUPPORT=y 24 CONFIG_SPL_CPU_SUPPORT=y
25 CONFIG_SPL_I2C_SUPPORT=y 25 CONFIG_SPL_I2C_SUPPORT=y
26 CONFIG_SPL_NET_SUPPORT=y 26 CONFIG_SPL_NET_SUPPORT=y
27 CONFIG_SPL_PCI_SUPPORT=y 27 CONFIG_SPL_PCI_SUPPORT=y
28 CONFIG_SPL_PCH_SUPPORT=y 28 CONFIG_SPL_PCH_SUPPORT=y
29 CONFIG_SPL_RTC_SUPPORT=y 29 CONFIG_SPL_RTC_SUPPORT=y
30 CONFIG_SPL_TIMER_SUPPORT=y 30 CONFIG_SPL_TIMER_SUPPORT=y
31 CONFIG_HUSH_PARSER=y 31 CONFIG_HUSH_PARSER=y
32 CONFIG_CMD_CPU=y 32 CONFIG_CMD_CPU=y
33 # CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set 33 # CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
34 # CONFIG_CMD_IMLS is not set 34 # CONFIG_CMD_IMLS is not set
35 # CONFIG_CMD_FLASH is not set 35 # CONFIG_CMD_FLASH is not set
36 CONFIG_CMD_SF=y 36 CONFIG_CMD_SF=y
37 CONFIG_CMD_SPI=y 37 CONFIG_CMD_SPI=y
38 CONFIG_CMD_USB=y 38 CONFIG_CMD_USB=y
39 CONFIG_CMD_GPIO=y 39 CONFIG_CMD_GPIO=y
40 # CONFIG_CMD_SETEXPR is not set 40 # CONFIG_CMD_SETEXPR is not set
41 CONFIG_CMD_DHCP=y 41 CONFIG_CMD_DHCP=y
42 # CONFIG_CMD_NFS is not set 42 # CONFIG_CMD_NFS is not set
43 CONFIG_CMD_PING=y 43 CONFIG_CMD_PING=y
44 CONFIG_CMD_TIME=y 44 CONFIG_CMD_TIME=y
45 CONFIG_CMD_BOOTSTAGE=y 45 CONFIG_CMD_BOOTSTAGE=y
46 CONFIG_CMD_TPM=y 46 CONFIG_CMD_TPM=y
47 CONFIG_CMD_TPM_TEST=y 47 CONFIG_CMD_TPM_TEST=y
48 CONFIG_CMD_EXT2=y 48 CONFIG_CMD_EXT2=y
49 CONFIG_CMD_EXT4=y 49 CONFIG_CMD_EXT4=y
50 CONFIG_CMD_EXT4_WRITE=y 50 CONFIG_CMD_EXT4_WRITE=y
51 CONFIG_CMD_FAT=y 51 CONFIG_CMD_FAT=y
52 CONFIG_CMD_FS_GENERIC=y 52 CONFIG_CMD_FS_GENERIC=y
53 CONFIG_OF_CONTROL=y 53 CONFIG_OF_CONTROL=y
54 CONFIG_SPL_OF_CONTROL=y 54 CONFIG_SPL_OF_CONTROL=y
55 CONFIG_SPL_DM=y 55 CONFIG_SPL_DM=y
56 CONFIG_REGMAP=y 56 CONFIG_REGMAP=y
57 CONFIG_SPL_REGMAP=y 57 CONFIG_SPL_REGMAP=y
58 CONFIG_SYSCON=y 58 CONFIG_SYSCON=y
59 CONFIG_SPL_SYSCON=y 59 CONFIG_SPL_SYSCON=y
60 CONFIG_SCSI=y 60 CONFIG_SCSI=y
61 CONFIG_DM_SCSI=y
62 CONFIG_BLK=y
61 CONFIG_CPU=y 63 CONFIG_CPU=y
62 CONFIG_DM_I2C=y 64 CONFIG_DM_I2C=y
63 CONFIG_SYS_I2C_INTEL=y 65 CONFIG_SYS_I2C_INTEL=y
64 CONFIG_CROS_EC=y 66 CONFIG_CROS_EC=y
65 CONFIG_CROS_EC_LPC=y 67 CONFIG_CROS_EC_LPC=y
66 CONFIG_SPI_FLASH=y 68 CONFIG_SPI_FLASH=y
67 CONFIG_SPI_FLASH_GIGADEVICE=y 69 CONFIG_SPI_FLASH_GIGADEVICE=y
68 CONFIG_SPI_FLASH_MACRONIX=y 70 CONFIG_SPI_FLASH_MACRONIX=y
69 CONFIG_SPI_FLASH_WINBOND=y 71 CONFIG_SPI_FLASH_WINBOND=y
70 CONFIG_DM_PCI=y 72 CONFIG_DM_PCI=y
71 CONFIG_DM_RTC=y 73 CONFIG_DM_RTC=y
72 CONFIG_DEBUG_UART_BASE=0x3f8 74 CONFIG_DEBUG_UART_BASE=0x3f8
73 CONFIG_DEBUG_UART_CLOCK=1843200 75 CONFIG_DEBUG_UART_CLOCK=1843200
74 CONFIG_DEBUG_UART_BOARD_INIT=y 76 CONFIG_DEBUG_UART_BOARD_INIT=y
75 CONFIG_SYS_NS16550=y 77 CONFIG_SYS_NS16550=y
76 CONFIG_ICH_SPI=y 78 CONFIG_ICH_SPI=y
77 CONFIG_TIMER=y 79 CONFIG_TIMER=y
78 CONFIG_TPM_TIS_LPC=y 80 CONFIG_TPM_TIS_LPC=y
79 CONFIG_USB=y 81 CONFIG_USB=y
80 CONFIG_DM_USB=y 82 CONFIG_DM_USB=y
81 CONFIG_USB_STORAGE=y 83 CONFIG_USB_STORAGE=y
82 CONFIG_USB_KEYBOARD=y 84 CONFIG_USB_KEYBOARD=y
83 CONFIG_DM_VIDEO=y 85 CONFIG_DM_VIDEO=y
84 CONFIG_VIDEO_VESA=y 86 CONFIG_VIDEO_VESA=y
85 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y 87 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
86 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y 88 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
87 CONFIG_VIDEO_IVYBRIDGE_IGD=y 89 CONFIG_VIDEO_IVYBRIDGE_IGD=y
88 CONFIG_CONSOLE_SCROLL_LINES=5 90 CONFIG_CONSOLE_SCROLL_LINES=5
89 CONFIG_USE_PRIVATE_LIBGCC=y 91 CONFIG_USE_PRIVATE_LIBGCC=y
90 CONFIG_CMD_DHRYSTONE=y 92 CONFIG_CMD_DHRYSTONE=y
91 CONFIG_TPM=y 93 CONFIG_TPM=y
92 94
configs/chromebook_link_defconfig
Diff comments   View file @ 32e9ec1
1 CONFIG_X86=y 1 CONFIG_X86=y
2 CONFIG_SYS_MALLOC_F_LEN=0x2000 2 CONFIG_SYS_MALLOC_F_LEN=0x2000
3 CONFIG_VENDOR_GOOGLE=y 3 CONFIG_VENDOR_GOOGLE=y
4 CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" 4 CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
5 CONFIG_TARGET_CHROMEBOOK_LINK=y 5 CONFIG_TARGET_CHROMEBOOK_LINK=y
6 CONFIG_DEBUG_UART=y 6 CONFIG_DEBUG_UART=y
7 CONFIG_ENABLE_MRC_CACHE=y 7 CONFIG_ENABLE_MRC_CACHE=y
8 CONFIG_HAVE_MRC=y 8 CONFIG_HAVE_MRC=y
9 CONFIG_SMP=y 9 CONFIG_SMP=y
10 CONFIG_HAVE_VGA_BIOS=y 10 CONFIG_HAVE_VGA_BIOS=y
11 CONFIG_FIT=y 11 CONFIG_FIT=y
12 CONFIG_BOOTSTAGE=y 12 CONFIG_BOOTSTAGE=y
13 CONFIG_BOOTSTAGE_REPORT=y 13 CONFIG_BOOTSTAGE_REPORT=y
14 CONFIG_SYS_CONSOLE_INFO_QUIET=y 14 CONFIG_SYS_CONSOLE_INFO_QUIET=y
15 CONFIG_HUSH_PARSER=y 15 CONFIG_HUSH_PARSER=y
16 CONFIG_CMD_CPU=y 16 CONFIG_CMD_CPU=y
17 # CONFIG_CMD_IMLS is not set 17 # CONFIG_CMD_IMLS is not set
18 # CONFIG_CMD_FLASH is not set 18 # CONFIG_CMD_FLASH is not set
19 CONFIG_CMD_PART=y 19 CONFIG_CMD_PART=y
20 CONFIG_CMD_SF=y 20 CONFIG_CMD_SF=y
21 CONFIG_CMD_SPI=y 21 CONFIG_CMD_SPI=y
22 CONFIG_CMD_USB=y 22 CONFIG_CMD_USB=y
23 CONFIG_CMD_GPIO=y 23 CONFIG_CMD_GPIO=y
24 # CONFIG_CMD_SETEXPR is not set 24 # CONFIG_CMD_SETEXPR is not set
25 CONFIG_CMD_DHCP=y 25 CONFIG_CMD_DHCP=y
26 # CONFIG_CMD_NFS is not set 26 # CONFIG_CMD_NFS is not set
27 CONFIG_CMD_PING=y 27 CONFIG_CMD_PING=y
28 CONFIG_CMD_TIME=y 28 CONFIG_CMD_TIME=y
29 CONFIG_CMD_BOOTSTAGE=y 29 CONFIG_CMD_BOOTSTAGE=y
30 CONFIG_CMD_TPM=y 30 CONFIG_CMD_TPM=y
31 CONFIG_CMD_TPM_TEST=y 31 CONFIG_CMD_TPM_TEST=y
32 CONFIG_CMD_EXT2=y 32 CONFIG_CMD_EXT2=y
33 CONFIG_CMD_EXT4=y 33 CONFIG_CMD_EXT4=y
34 CONFIG_CMD_EXT4_WRITE=y 34 CONFIG_CMD_EXT4_WRITE=y
35 CONFIG_CMD_FAT=y 35 CONFIG_CMD_FAT=y
36 CONFIG_CMD_FS_GENERIC=y 36 CONFIG_CMD_FS_GENERIC=y
37 CONFIG_MAC_PARTITION=y 37 CONFIG_MAC_PARTITION=y
38 CONFIG_ISO_PARTITION=y 38 CONFIG_ISO_PARTITION=y
39 CONFIG_EFI_PARTITION=y 39 CONFIG_EFI_PARTITION=y
40 CONFIG_OF_CONTROL=y 40 CONFIG_OF_CONTROL=y
41 CONFIG_REGMAP=y 41 CONFIG_REGMAP=y
42 CONFIG_SYSCON=y 42 CONFIG_SYSCON=y
43 CONFIG_SCSI=y 43 CONFIG_SCSI=y
44 CONFIG_DM_SCSI=y
45 CONFIG_BLK=y
44 CONFIG_CPU=y 46 CONFIG_CPU=y
45 CONFIG_DM_I2C=y 47 CONFIG_DM_I2C=y
46 CONFIG_SYS_I2C_INTEL=y 48 CONFIG_SYS_I2C_INTEL=y
47 CONFIG_CROS_EC=y 49 CONFIG_CROS_EC=y
48 CONFIG_CROS_EC_LPC=y 50 CONFIG_CROS_EC_LPC=y
49 CONFIG_SPI_FLASH=y 51 CONFIG_SPI_FLASH=y
50 CONFIG_SPI_FLASH_GIGADEVICE=y 52 CONFIG_SPI_FLASH_GIGADEVICE=y
51 CONFIG_SPI_FLASH_MACRONIX=y 53 CONFIG_SPI_FLASH_MACRONIX=y
52 CONFIG_SPI_FLASH_WINBOND=y 54 CONFIG_SPI_FLASH_WINBOND=y
53 CONFIG_DM_PCI=y 55 CONFIG_DM_PCI=y
54 CONFIG_DM_RTC=y 56 CONFIG_DM_RTC=y
55 CONFIG_DEBUG_UART_BASE=0x3f8 57 CONFIG_DEBUG_UART_BASE=0x3f8
56 CONFIG_DEBUG_UART_CLOCK=1843200 58 CONFIG_DEBUG_UART_CLOCK=1843200
57 CONFIG_DEBUG_UART_BOARD_INIT=y 59 CONFIG_DEBUG_UART_BOARD_INIT=y
58 CONFIG_SYS_NS16550=y 60 CONFIG_SYS_NS16550=y
59 CONFIG_ICH_SPI=y 61 CONFIG_ICH_SPI=y
60 CONFIG_TIMER=y 62 CONFIG_TIMER=y
61 CONFIG_TPM_TIS_LPC=y 63 CONFIG_TPM_TIS_LPC=y
62 CONFIG_USB=y 64 CONFIG_USB=y
63 CONFIG_DM_USB=y 65 CONFIG_DM_USB=y
64 CONFIG_USB_STORAGE=y 66 CONFIG_USB_STORAGE=y
65 CONFIG_USB_KEYBOARD=y 67 CONFIG_USB_KEYBOARD=y
66 CONFIG_DM_VIDEO=y 68 CONFIG_DM_VIDEO=y
67 CONFIG_VIDEO_VESA=y 69 CONFIG_VIDEO_VESA=y
68 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y 70 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
69 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y 71 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
70 CONFIG_VIDEO_IVYBRIDGE_IGD=y 72 CONFIG_VIDEO_IVYBRIDGE_IGD=y
71 CONFIG_CONSOLE_SCROLL_LINES=5 73 CONFIG_CONSOLE_SCROLL_LINES=5
72 CONFIG_USE_PRIVATE_LIBGCC=y 74 CONFIG_USE_PRIVATE_LIBGCC=y
73 CONFIG_CMD_DHRYSTONE=y 75 CONFIG_CMD_DHRYSTONE=y
74 CONFIG_TPM=y 76 CONFIG_TPM=y
75 77
configs/chromebox_panther_defconfig
Diff comments   View file @ 32e9ec1
1 CONFIG_X86=y 1 CONFIG_X86=y
2 CONFIG_VENDOR_GOOGLE=y 2 CONFIG_VENDOR_GOOGLE=y
3 CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther" 3 CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther"
4 CONFIG_TARGET_CHROMEBOX_PANTHER=y 4 CONFIG_TARGET_CHROMEBOX_PANTHER=y
5 CONFIG_ENABLE_MRC_CACHE=y 5 CONFIG_ENABLE_MRC_CACHE=y
6 CONFIG_HAVE_MRC=y 6 CONFIG_HAVE_MRC=y
7 CONFIG_HAVE_VGA_BIOS=y 7 CONFIG_HAVE_VGA_BIOS=y
8 CONFIG_FIT=y 8 CONFIG_FIT=y
9 CONFIG_BOOTSTAGE=y 9 CONFIG_BOOTSTAGE=y
10 CONFIG_BOOTSTAGE_REPORT=y 10 CONFIG_BOOTSTAGE_REPORT=y
11 CONFIG_SYS_CONSOLE_INFO_QUIET=y 11 CONFIG_SYS_CONSOLE_INFO_QUIET=y
12 CONFIG_HUSH_PARSER=y 12 CONFIG_HUSH_PARSER=y
13 # CONFIG_CMD_IMLS is not set 13 # CONFIG_CMD_IMLS is not set
14 # CONFIG_CMD_FLASH is not set 14 # CONFIG_CMD_FLASH is not set
15 CONFIG_CMD_PART=y 15 CONFIG_CMD_PART=y
16 CONFIG_CMD_SF=y 16 CONFIG_CMD_SF=y
17 CONFIG_CMD_SPI=y 17 CONFIG_CMD_SPI=y
18 CONFIG_CMD_USB=y 18 CONFIG_CMD_USB=y
19 CONFIG_CMD_GPIO=y 19 CONFIG_CMD_GPIO=y
20 # CONFIG_CMD_SETEXPR is not set 20 # CONFIG_CMD_SETEXPR is not set
21 CONFIG_CMD_DHCP=y 21 CONFIG_CMD_DHCP=y
22 # CONFIG_CMD_NFS is not set 22 # CONFIG_CMD_NFS is not set
23 CONFIG_CMD_PING=y 23 CONFIG_CMD_PING=y
24 CONFIG_CMD_TIME=y 24 CONFIG_CMD_TIME=y
25 CONFIG_CMD_BOOTSTAGE=y 25 CONFIG_CMD_BOOTSTAGE=y
26 CONFIG_CMD_TPM=y 26 CONFIG_CMD_TPM=y
27 CONFIG_CMD_TPM_TEST=y 27 CONFIG_CMD_TPM_TEST=y
28 CONFIG_CMD_EXT2=y 28 CONFIG_CMD_EXT2=y
29 CONFIG_CMD_EXT4=y 29 CONFIG_CMD_EXT4=y
30 CONFIG_CMD_EXT4_WRITE=y 30 CONFIG_CMD_EXT4_WRITE=y
31 CONFIG_CMD_FAT=y 31 CONFIG_CMD_FAT=y
32 CONFIG_CMD_FS_GENERIC=y 32 CONFIG_CMD_FS_GENERIC=y
33 CONFIG_MAC_PARTITION=y 33 CONFIG_MAC_PARTITION=y
34 CONFIG_ISO_PARTITION=y 34 CONFIG_ISO_PARTITION=y
35 CONFIG_EFI_PARTITION=y 35 CONFIG_EFI_PARTITION=y
36 CONFIG_OF_CONTROL=y 36 CONFIG_OF_CONTROL=y
37 CONFIG_REGMAP=y 37 CONFIG_REGMAP=y
38 CONFIG_SYSCON=y 38 CONFIG_SYSCON=y
39 CONFIG_SCSI=y 39 CONFIG_SCSI=y
40 CONFIG_DM_SCSI=y
41 CONFIG_BLK=y
40 CONFIG_CROS_EC=y 42 CONFIG_CROS_EC=y
41 CONFIG_CROS_EC_LPC=y 43 CONFIG_CROS_EC_LPC=y
42 CONFIG_SPI_FLASH=y 44 CONFIG_SPI_FLASH=y
43 CONFIG_SPI_FLASH_GIGADEVICE=y 45 CONFIG_SPI_FLASH_GIGADEVICE=y
44 CONFIG_SPI_FLASH_MACRONIX=y 46 CONFIG_SPI_FLASH_MACRONIX=y
45 CONFIG_SPI_FLASH_WINBOND=y 47 CONFIG_SPI_FLASH_WINBOND=y
46 CONFIG_DM_ETH=y 48 CONFIG_DM_ETH=y
47 CONFIG_RTL8169=y 49 CONFIG_RTL8169=y
48 CONFIG_DM_PCI=y 50 CONFIG_DM_PCI=y
49 CONFIG_DM_RTC=y 51 CONFIG_DM_RTC=y
50 CONFIG_SYS_NS16550=y 52 CONFIG_SYS_NS16550=y
51 CONFIG_ICH_SPI=y 53 CONFIG_ICH_SPI=y
52 CONFIG_TIMER=y 54 CONFIG_TIMER=y
53 CONFIG_TPM_TIS_LPC=y 55 CONFIG_TPM_TIS_LPC=y
54 CONFIG_USB=y 56 CONFIG_USB=y
55 CONFIG_DM_USB=y 57 CONFIG_DM_USB=y
56 CONFIG_USB_STORAGE=y 58 CONFIG_USB_STORAGE=y
57 CONFIG_USB_KEYBOARD=y 59 CONFIG_USB_KEYBOARD=y
58 CONFIG_DM_VIDEO=y 60 CONFIG_DM_VIDEO=y
59 CONFIG_VIDEO_VESA=y 61 CONFIG_VIDEO_VESA=y
60 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y 62 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
61 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y 63 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
62 CONFIG_CONSOLE_SCROLL_LINES=5 64 CONFIG_CONSOLE_SCROLL_LINES=5
63 CONFIG_USE_PRIVATE_LIBGCC=y 65 CONFIG_USE_PRIVATE_LIBGCC=y
64 CONFIG_TPM=y 66 CONFIG_TPM=y
65 67