Eric Lee / smarc-uboot

43
Download as
Browse Code ยป

Commit 337b0c52b3296f371d04aef71a833e09110e0e6b

Authored by Priyanka Jain
Committed by York Sun
1 parent bf4699db85
Exists in v2017.01-smarct4x and in 48 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc/t1040qds: Add Video - HDMI support 

T1040 has internal display interface unit (DIU) for driving video.
T1040QDS supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoder

Chrontel, CH7301C encoder which is I2C programmable is used as
HDMI connector on T1040QDS.
This patch add support to
-enable Video interface for T1040QDS
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1040
-program HDMI encoder via I2C on board

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Showing 5 changed files with 255 additions and 1 deletions Inline Diff

board/freescale/t1040qds/Makefile
Diff comments   View file @ 337b0c5
1 # 1 #
2 # Copyright 2013 Freescale Semiconductor, Inc. 2 # Copyright 2013 Freescale Semiconductor, Inc.
3 # 3 #
4 # SPDX-License-Identifier: GPL-2.0+ 4 # SPDX-License-Identifier: GPL-2.0+
5 # 5 #
6 6
7 obj-y += t1040qds.o 7 obj-y += t1040qds.o
8 obj-y += ddr.o 8 obj-y += ddr.o
9 obj-$(CONFIG_PCI) += pci.o 9 obj-$(CONFIG_PCI) += pci.o
10 obj-y += law.o 10 obj-y += law.o
11 obj-y += tlb.o 11 obj-y += tlb.o
12 obj-y += eth.o 12 obj-y += eth.o
13 obj-y += diu.o
13 14
board/freescale/t1040qds/diu.c
Diff comments   View file @ 337b0c5
File was created 1 /*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <command.h>
10 #include <linux/ctype.h>
11 #include <asm/io.h>
12 #include <stdio_dev.h>
13 #include <video_fb.h>
14 #include <fsl_diu_fb.h>
15 #include "../common/qixis.h"
16 #include "t1040qds.h"
17 #include "t1040qds_qixis.h"
18 #include <i2c.h>
19
20
21 #define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F
22 #define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33
23 #define I2C_DVI_PLL_DIVIDER_REG 0x34
24 #define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35
25 #define I2C_DVI_PLL_FILTER_REG 0x36
26 #define I2C_DVI_TEST_PATTERN_REG 0x48
27 #define I2C_DVI_POWER_MGMT_REG 0x49
28 #define I2C_DVI_LOCK_STATE_REG 0x4D
29 #define I2C_DVI_SYNC_POLARITY_REG 0x56
30
31 /*
32 * Set VSYNC/HSYNC to active high. This is polarity of sync signals
33 * from DIU->DVI. The DIU default is active igh, so DVI is set to
34 * active high.
35 */
36 #define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98
37
38 #define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06
39 #define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26
40 #define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0
41 #define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08
42 #define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16
43 #define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60
44
45 /* Clear test pattern */
46 #define I2C_DVI_TEST_PATTERN_VAL 0x18
47 /* Exit Power-down mode */
48 #define I2C_DVI_POWER_MGMT_VAL 0xC0
49
50 /* Monitor polarity is handled via DVI Sync Polarity Register */
51 #define I2C_DVI_SYNC_POLARITY_VAL 0x00
52
53 /*
54 * DIU Area Descriptor
55 *
56 * Note that we need to byte-swap the value before it's written to the AD
57 * register. So even though the registers don't look like they're in the same
58 * bit positions as they are on the MPC8610, the same value is written to the
59 * AD register on the MPC8610 and on the P1022.
60 */
61 #define AD_BYTE_F 0x10000000
62 #define AD_ALPHA_C_SHIFT 25
63 #define AD_BLUE_C_SHIFT 23
64 #define AD_GREEN_C_SHIFT 21
65 #define AD_RED_C_SHIFT 19
66 #define AD_PIXEL_S_SHIFT 16
67 #define AD_COMP_3_SHIFT 12
68 #define AD_COMP_2_SHIFT 8
69 #define AD_COMP_1_SHIFT 4
70 #define AD_COMP_0_SHIFT 0
71
72 /* Programming of HDMI Chrontel CH7301 connector */
73 int diu_set_dvi_encoder(unsigned int pixclock)
74 {
75 int ret;
76 u8 temp;
77 select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
78
79 temp = I2C_DVI_TEST_PATTERN_VAL;
80 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
81 &temp, 1);
82 if (ret) {
83 puts("I2C: failed to select proper dvi test pattern\n");
84 return ret;
85 }
86 temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
87 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
88 1, &temp, 1);
89 if (ret) {
90 puts("I2C: failed to select dvi input data format\n");
91 return ret;
92 }
93
94 /* Set Sync polarity register */
95 temp = I2C_DVI_SYNC_POLARITY_VAL;
96 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
97 &temp, 1);
98 if (ret) {
99 puts("I2C: failed to select dvi syc polarity\n");
100 return ret;
101 }
102
103 /* Set PLL registers based on pixel clock rate*/
104 if (pixclock > 65000000) {
105 temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
106 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
107 I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
108 if (ret) {
109 puts("I2C: failed to select dvi pll charge_cntl\n");
110 return ret;
111 }
112 temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
113 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
114 I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
115 if (ret) {
116 puts("I2C: failed to select dvi pll divider\n");
117 return ret;
118 }
119 temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
120 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
121 I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
122 if (ret) {
123 puts("I2C: failed to select dvi pll filter\n");
124 return ret;
125 }
126 } else {
127 temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
128 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
129 I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
130 if (ret) {
131 puts("I2C: failed to select dvi pll charge_cntl\n");
132 return ret;
133 }
134 temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
135 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
136 I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
137 if (ret) {
138 puts("I2C: failed to select dvi pll divider\n");
139 return ret;
140 }
141 temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
142 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
143 I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
144 if (ret) {
145 puts("I2C: failed to select dvi pll filter\n");
146 return ret;
147 }
148 }
149
150 temp = I2C_DVI_POWER_MGMT_VAL;
151 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
152 &temp, 1);
153 if (ret) {
154 puts("I2C: failed to select dvi power mgmt\n");
155 return ret;
156 }
157
158 udelay(500);
159
160 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
161 return 0;
162 }
163
164 void diu_set_pixel_clock(unsigned int pixclock)
165 {
166 unsigned long speed_ccb, temp;
167 u32 pixval;
168 int ret = 0;
169 speed_ccb = get_bus_freq(0);
170 temp = 1000000000 / pixclock;
171 temp *= 1000;
172 pixval = speed_ccb / temp;
173
174 /* Program HDMI encoder */
175 ret = diu_set_dvi_encoder(temp);
176 if (ret) {
177 puts("Failed to set DVI encoder\n");
178 return;
179 }
180
181 /* Program pixel clock */
182 out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
183 ((pixval << PXCK_BITS_START) & PXCK_MASK));
184 /* enable clock*/
185 out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
186 ((pixval << PXCK_BITS_START) & PXCK_MASK));
187 }
188
189 int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
190 {
191 u32 pixel_format;
192 u8 sw;
193
194 /*Route I2C4 to DIU system as HSYNC/VSYNC*/
195 sw = QIXIS_READ(brdcfg[5]);
196 QIXIS_WRITE(brdcfg[5],
197 ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU)));
198
199 /*Configure Display ouput port as HDMI*/
200 sw = QIXIS_READ(brdcfg[15]);
201 QIXIS_WRITE(brdcfg[15],
202 ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK))
203 | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI)));
204
205 pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
206 (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
207 (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
208 (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
209 (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
210
211 printf("DIU: Switching to monitor @ %ux%u\n", xres, yres);
212
213
214 return fsl_diu_init(xres, yres, pixel_format, 0);
215 }
216
board/freescale/t1040qds/t1040qds.h
Diff comments   View file @ 337b0c5
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __T1040_QDS_H__ 7 #ifndef __T1040_QDS_H__
8 #define __T1040_QDS_H__ 8 #define __T1040_QDS_H__
9 9
10 void fdt_fixup_board_enet(void *blob); 10 void fdt_fixup_board_enet(void *blob);
11 void pci_of_setup(void *blob, bd_t *bd); 11 void pci_of_setup(void *blob, bd_t *bd);
12 int select_i2c_ch_pca9547(u8 ch);
12 13
13 #endif 14 #endif
14 15
board/freescale/t1040qds/t1040qds_qixis.h
Diff comments   View file @ 337b0c5
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __T1040QDS_QIXIS_H__ 7 #ifndef __T1040QDS_QIXIS_H__
8 #define __T1040QDS_QIXIS_H__ 8 #define __T1040QDS_QIXIS_H__
9 9
10 /* Definitions of QIXIS Registers for T1040QDS */ 10 /* Definitions of QIXIS Registers for T1040QDS */
11 11
12 /* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ 12 /* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
13 #define BRDCFG4_EMISEL_MASK 0xE0 13 #define BRDCFG4_EMISEL_MASK 0xE0
14 #define BRDCFG4_EMISEL_SHIFT 5 14 #define BRDCFG4_EMISEL_SHIFT 5
15 15
16 /* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
17 #define BRDCFG5_IMX_MASK 0xC0
18 #define BRDCFG5_IMX_DIU 0x80
19
20 /* BRDCFG15[3] controls LCD Panel Powerdown*/
21 #define BRDCFG15_LCDPD_MASK 0x10
22 #define BRDCFG15_LCDPD_ENABLED 0x00
23
24 /* BRDCFG15[6:7] controls DIU MUX selction*/
25 #define BRDCFG15_DIUSEL_MASK 0x03
26 #define BRDCFG15_DIUSEL_HDMI 0x00
27
16 /* SYSCLK */ 28 /* SYSCLK */
17 #define QIXIS_SYSCLK_66 0x0 29 #define QIXIS_SYSCLK_66 0x0
18 #define QIXIS_SYSCLK_83 0x1 30 #define QIXIS_SYSCLK_83 0x1
19 #define QIXIS_SYSCLK_100 0x2 31 #define QIXIS_SYSCLK_100 0x2
20 #define QIXIS_SYSCLK_125 0x3 32 #define QIXIS_SYSCLK_125 0x3
21 #define QIXIS_SYSCLK_133 0x4 33 #define QIXIS_SYSCLK_133 0x4
22 #define QIXIS_SYSCLK_150 0x5 34 #define QIXIS_SYSCLK_150 0x5
23 #define QIXIS_SYSCLK_160 0x6 35 #define QIXIS_SYSCLK_160 0x6
24 #define QIXIS_SYSCLK_166 0x7 36 #define QIXIS_SYSCLK_166 0x7
25 #define QIXIS_SYSCLK_64 0x8 37 #define QIXIS_SYSCLK_64 0x8
26 38
27 /* DDRCLK */ 39 /* DDRCLK */
28 #define QIXIS_DDRCLK_66 0x0 40 #define QIXIS_DDRCLK_66 0x0
29 #define QIXIS_DDRCLK_100 0x1 41 #define QIXIS_DDRCLK_100 0x1
30 #define QIXIS_DDRCLK_125 0x2 42 #define QIXIS_DDRCLK_125 0x2
31 #define QIXIS_DDRCLK_133 0x3 43 #define QIXIS_DDRCLK_133 0x3
32 44
33 45
34 #define QIXIS_SRDS1CLK_122 0x5a 46 #define QIXIS_SRDS1CLK_122 0x5a
35 #define QIXIS_SRDS1CLK_125 0x5e 47 #define QIXIS_SRDS1CLK_125 0x5e
36 #endif 48 #endif
37 49
include/configs/T1040QDS.h
Diff comments   View file @ 337b0c5
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * See file CREDITS for list of people who contributed to this 4 * See file CREDITS for list of people who contributed to this
5 * project. 5 * project.
6 * 6 *
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as 8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of 9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version. 10 * the License, or (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 * 16 *
17 * You should have received a copy of the GNU General Public License 17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA 20 * MA 02111-1307 USA
21 */ 21 */
22 22
23 #ifndef __CONFIG_H 23 #ifndef __CONFIG_H
24 #define __CONFIG_H 24 #define __CONFIG_H
25 25
26 /* 26 /*
27 * T1040 QDS board configuration file 27 * T1040 QDS board configuration file
28 */ 28 */
29 #define CONFIG_T1040QDS 29 #define CONFIG_T1040QDS
30 #define CONFIG_PHYS_64BIT 30 #define CONFIG_PHYS_64BIT
31 31
32 #ifdef CONFIG_RAMBOOT_PBL 32 #ifdef CONFIG_RAMBOOT_PBL
33 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 33 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
34 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
35 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg 35 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg
36 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg 36 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
37 #endif 37 #endif
38 38
39 /* High Level Configuration Options */ 39 /* High Level Configuration Options */
40 #define CONFIG_BOOKE 40 #define CONFIG_BOOKE
41 #define CONFIG_E500 /* BOOKE e500 family */ 41 #define CONFIG_E500 /* BOOKE e500 family */
42 #define CONFIG_E500MC /* BOOKE e500mc family */ 42 #define CONFIG_E500MC /* BOOKE e500mc family */
43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
44 #define CONFIG_MP /* support multiple processors */ 44 #define CONFIG_MP /* support multiple processors */
45 45
46 #ifndef CONFIG_SYS_TEXT_BASE 46 #ifndef CONFIG_SYS_TEXT_BASE
47 #define CONFIG_SYS_TEXT_BASE 0xeff40000 47 #define CONFIG_SYS_TEXT_BASE 0xeff40000
48 #endif 48 #endif
49 49
50 #ifndef CONFIG_RESET_VECTOR_ADDRESS 50 #ifndef CONFIG_RESET_VECTOR_ADDRESS
51 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 51 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
52 #endif 52 #endif
53 53
54 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 54 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
55 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 55 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
56 #define CONFIG_FSL_IFC /* Enable IFC Support */ 56 #define CONFIG_FSL_IFC /* Enable IFC Support */
57 #define CONFIG_PCI /* Enable PCI/PCIE */ 57 #define CONFIG_PCI /* Enable PCI/PCIE */
58 #define CONFIG_PCI_INDIRECT_BRIDGE 58 #define CONFIG_PCI_INDIRECT_BRIDGE
59 #define CONFIG_PCIE1 /* PCIE controler 1 */ 59 #define CONFIG_PCIE1 /* PCIE controler 1 */
60 #define CONFIG_PCIE2 /* PCIE controler 2 */ 60 #define CONFIG_PCIE2 /* PCIE controler 2 */
61 #define CONFIG_PCIE3 /* PCIE controler 3 */ 61 #define CONFIG_PCIE3 /* PCIE controler 3 */
62 #define CONFIG_PCIE4 /* PCIE controler 4 */ 62 #define CONFIG_PCIE4 /* PCIE controler 4 */
63 63
64 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 64 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
65 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 65 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
66 66
67 #define CONFIG_FSL_LAW /* Use common FSL init code */ 67 #define CONFIG_FSL_LAW /* Use common FSL init code */
68 68
69 #define CONFIG_ENV_OVERWRITE 69 #define CONFIG_ENV_OVERWRITE
70 70
71 #ifdef CONFIG_SYS_NO_FLASH 71 #ifdef CONFIG_SYS_NO_FLASH
72 #define CONFIG_ENV_IS_NOWHERE 72 #define CONFIG_ENV_IS_NOWHERE
73 #else 73 #else
74 #define CONFIG_FLASH_CFI_DRIVER 74 #define CONFIG_FLASH_CFI_DRIVER
75 #define CONFIG_SYS_FLASH_CFI 75 #define CONFIG_SYS_FLASH_CFI
76 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 76 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
77 #endif 77 #endif
78 78
79 #ifndef CONFIG_SYS_NO_FLASH 79 #ifndef CONFIG_SYS_NO_FLASH
80 #if defined(CONFIG_SPIFLASH) 80 #if defined(CONFIG_SPIFLASH)
81 #define CONFIG_SYS_EXTRA_ENV_RELOC 81 #define CONFIG_SYS_EXTRA_ENV_RELOC
82 #define CONFIG_ENV_IS_IN_SPI_FLASH 82 #define CONFIG_ENV_IS_IN_SPI_FLASH
83 #define CONFIG_ENV_SPI_BUS 0 83 #define CONFIG_ENV_SPI_BUS 0
84 #define CONFIG_ENV_SPI_CS 0 84 #define CONFIG_ENV_SPI_CS 0
85 #define CONFIG_ENV_SPI_MAX_HZ 10000000 85 #define CONFIG_ENV_SPI_MAX_HZ 10000000
86 #define CONFIG_ENV_SPI_MODE 0 86 #define CONFIG_ENV_SPI_MODE 0
87 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 87 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
88 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 88 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
89 #define CONFIG_ENV_SECT_SIZE 0x10000 89 #define CONFIG_ENV_SECT_SIZE 0x10000
90 #elif defined(CONFIG_SDCARD) 90 #elif defined(CONFIG_SDCARD)
91 #define CONFIG_SYS_EXTRA_ENV_RELOC 91 #define CONFIG_SYS_EXTRA_ENV_RELOC
92 #define CONFIG_ENV_IS_IN_MMC 92 #define CONFIG_ENV_IS_IN_MMC
93 #define CONFIG_SYS_MMC_ENV_DEV 0 93 #define CONFIG_SYS_MMC_ENV_DEV 0
94 #define CONFIG_ENV_SIZE 0x2000 94 #define CONFIG_ENV_SIZE 0x2000
95 #define CONFIG_ENV_OFFSET (512 * 1658) 95 #define CONFIG_ENV_OFFSET (512 * 1658)
96 #elif defined(CONFIG_NAND) 96 #elif defined(CONFIG_NAND)
97 #define CONFIG_SYS_EXTRA_ENV_RELOC 97 #define CONFIG_SYS_EXTRA_ENV_RELOC
98 #define CONFIG_ENV_IS_IN_NAND 98 #define CONFIG_ENV_IS_IN_NAND
99 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 99 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
100 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 100 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
101 #else 101 #else
102 #define CONFIG_ENV_IS_IN_FLASH 102 #define CONFIG_ENV_IS_IN_FLASH
103 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 103 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
104 #define CONFIG_ENV_SIZE 0x2000 104 #define CONFIG_ENV_SIZE 0x2000
105 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 105 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
106 #endif 106 #endif
107 #else /* CONFIG_SYS_NO_FLASH */ 107 #else /* CONFIG_SYS_NO_FLASH */
108 #define CONFIG_ENV_SIZE 0x2000 108 #define CONFIG_ENV_SIZE 0x2000
109 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 109 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
110 #endif 110 #endif
111 111
112 #ifndef __ASSEMBLY__ 112 #ifndef __ASSEMBLY__
113 unsigned long get_board_sys_clk(void); 113 unsigned long get_board_sys_clk(void);
114 unsigned long get_board_ddr_clk(void); 114 unsigned long get_board_ddr_clk(void);
115 #endif 115 #endif
116 116
117 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 117 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
118 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 118 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
119 119
120 /* 120 /*
121 * These can be toggled for performance analysis, otherwise use default. 121 * These can be toggled for performance analysis, otherwise use default.
122 */ 122 */
123 #define CONFIG_SYS_CACHE_STASHING 123 #define CONFIG_SYS_CACHE_STASHING
124 #define CONFIG_BACKSIDE_L2_CACHE 124 #define CONFIG_BACKSIDE_L2_CACHE
125 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 125 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
126 #define CONFIG_BTB /* toggle branch predition */ 126 #define CONFIG_BTB /* toggle branch predition */
127 #define CONFIG_DDR_ECC 127 #define CONFIG_DDR_ECC
128 #ifdef CONFIG_DDR_ECC 128 #ifdef CONFIG_DDR_ECC
129 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 129 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
130 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 130 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
131 #endif 131 #endif
132 132
133 #define CONFIG_ENABLE_36BIT_PHYS 133 #define CONFIG_ENABLE_36BIT_PHYS
134 134
135 #define CONFIG_ADDR_MAP 135 #define CONFIG_ADDR_MAP
136 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 136 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
137 137
138 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 138 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
139 #define CONFIG_SYS_MEMTEST_END 0x00400000 139 #define CONFIG_SYS_MEMTEST_END 0x00400000
140 #define CONFIG_SYS_ALT_MEMTEST 140 #define CONFIG_SYS_ALT_MEMTEST
141 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 141 #define CONFIG_PANIC_HANG /* do not reset board on panic */
142 142
143 /* 143 /*
144 * Config the L3 Cache as L3 SRAM 144 * Config the L3 Cache as L3 SRAM
145 */ 145 */
146 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 146 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
147 147
148 #define CONFIG_SYS_DCSRBAR 0xf0000000 148 #define CONFIG_SYS_DCSRBAR 0xf0000000
149 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 149 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
150 150
151 /* EEPROM */ 151 /* EEPROM */
152 #define CONFIG_ID_EEPROM 152 #define CONFIG_ID_EEPROM
153 #define CONFIG_SYS_I2C_EEPROM_NXID 153 #define CONFIG_SYS_I2C_EEPROM_NXID
154 #define CONFIG_SYS_EEPROM_BUS_NUM 0 154 #define CONFIG_SYS_EEPROM_BUS_NUM 0
155 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 155 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
156 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 156 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
157 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 157 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
158 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 158 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
159 159
160 /* 160 /*
161 * DDR Setup 161 * DDR Setup
162 */ 162 */
163 #define CONFIG_VERY_BIG_RAM 163 #define CONFIG_VERY_BIG_RAM
164 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 164 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
165 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 165 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
166 166
167 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 167 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
168 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 168 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
169 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 169 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
170 170
171 #define CONFIG_DDR_SPD 171 #define CONFIG_DDR_SPD
172 #define CONFIG_SYS_FSL_DDR3 172 #define CONFIG_SYS_FSL_DDR3
173 #define CONFIG_FSL_DDR_INTERACTIVE 173 #define CONFIG_FSL_DDR_INTERACTIVE
174 174
175 #define CONFIG_SYS_SPD_BUS_NUM 0 175 #define CONFIG_SYS_SPD_BUS_NUM 0
176 #define SPD_EEPROM_ADDRESS 0x51 176 #define SPD_EEPROM_ADDRESS 0x51
177 177
178 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 178 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
179 179
180 /* 180 /*
181 * IFC Definitions 181 * IFC Definitions
182 */ 182 */
183 #define CONFIG_SYS_FLASH_BASE 0xe0000000 183 #define CONFIG_SYS_FLASH_BASE 0xe0000000
184 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 184 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
185 185
186 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 186 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
187 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 187 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
188 + 0x8000000) | \ 188 + 0x8000000) | \
189 CSPR_PORT_SIZE_16 | \ 189 CSPR_PORT_SIZE_16 | \
190 CSPR_MSEL_NOR | \ 190 CSPR_MSEL_NOR | \
191 CSPR_V) 191 CSPR_V)
192 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 192 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
193 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 193 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
194 CSPR_PORT_SIZE_16 | \ 194 CSPR_PORT_SIZE_16 | \
195 CSPR_MSEL_NOR | \ 195 CSPR_MSEL_NOR | \
196 CSPR_V) 196 CSPR_V)
197 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 197 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
198 /* NOR Flash Timing Params */ 198 /* NOR Flash Timing Params */
199 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 199 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
200 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 200 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
201 FTIM0_NOR_TEADC(0x5) | \ 201 FTIM0_NOR_TEADC(0x5) | \
202 FTIM0_NOR_TEAHC(0x5)) 202 FTIM0_NOR_TEAHC(0x5))
203 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 203 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
204 FTIM1_NOR_TRAD_NOR(0x1A) |\ 204 FTIM1_NOR_TRAD_NOR(0x1A) |\
205 FTIM1_NOR_TSEQRAD_NOR(0x13)) 205 FTIM1_NOR_TSEQRAD_NOR(0x13))
206 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 206 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
207 FTIM2_NOR_TCH(0x4) | \ 207 FTIM2_NOR_TCH(0x4) | \
208 FTIM2_NOR_TWPH(0x0E) | \ 208 FTIM2_NOR_TWPH(0x0E) | \
209 FTIM2_NOR_TWP(0x1c)) 209 FTIM2_NOR_TWP(0x1c))
210 #define CONFIG_SYS_NOR_FTIM3 0x0 210 #define CONFIG_SYS_NOR_FTIM3 0x0
211 211
212 #define CONFIG_SYS_FLASH_QUIET_TEST 212 #define CONFIG_SYS_FLASH_QUIET_TEST
213 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 213 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
214 214
215 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 215 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
216 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 216 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
217 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 217 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
218 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 218 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
219 219
220 #define CONFIG_SYS_FLASH_EMPTY_INFO 220 #define CONFIG_SYS_FLASH_EMPTY_INFO
221 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 221 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
222 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 222 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
223 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 223 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
224 #define QIXIS_BASE 0xffdf0000 224 #define QIXIS_BASE 0xffdf0000
225 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 225 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
226 #define QIXIS_LBMAP_SWITCH 0x06 226 #define QIXIS_LBMAP_SWITCH 0x06
227 #define QIXIS_LBMAP_MASK 0x0f 227 #define QIXIS_LBMAP_MASK 0x0f
228 #define QIXIS_LBMAP_SHIFT 0 228 #define QIXIS_LBMAP_SHIFT 0
229 #define QIXIS_LBMAP_DFLTBANK 0x00 229 #define QIXIS_LBMAP_DFLTBANK 0x00
230 #define QIXIS_LBMAP_ALTBANK 0x04 230 #define QIXIS_LBMAP_ALTBANK 0x04
231 #define QIXIS_RST_CTL_RESET 0x31 231 #define QIXIS_RST_CTL_RESET 0x31
232 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 232 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
233 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 233 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
234 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 234 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
235 #define QIXIS_RST_FORCE_MEM 0x01 235 #define QIXIS_RST_FORCE_MEM 0x01
236 236
237 #define CONFIG_SYS_CSPR3_EXT (0xf) 237 #define CONFIG_SYS_CSPR3_EXT (0xf)
238 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 238 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
239 | CSPR_PORT_SIZE_8 \ 239 | CSPR_PORT_SIZE_8 \
240 | CSPR_MSEL_GPCM \ 240 | CSPR_MSEL_GPCM \
241 | CSPR_V) 241 | CSPR_V)
242 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 242 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
243 #define CONFIG_SYS_CSOR3 0x0 243 #define CONFIG_SYS_CSOR3 0x0
244 /* QIXIS Timing parameters for IFC CS3 */ 244 /* QIXIS Timing parameters for IFC CS3 */
245 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 245 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
246 FTIM0_GPCM_TEADC(0x0e) | \ 246 FTIM0_GPCM_TEADC(0x0e) | \
247 FTIM0_GPCM_TEAHC(0x0e)) 247 FTIM0_GPCM_TEAHC(0x0e))
248 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 248 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
249 FTIM1_GPCM_TRAD(0x3f)) 249 FTIM1_GPCM_TRAD(0x3f))
250 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 250 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
251 FTIM2_GPCM_TCH(0x8) | \ 251 FTIM2_GPCM_TCH(0x8) | \
252 FTIM2_GPCM_TWP(0x1f)) 252 FTIM2_GPCM_TWP(0x1f))
253 #define CONFIG_SYS_CS3_FTIM3 0x0 253 #define CONFIG_SYS_CS3_FTIM3 0x0
254 254
255 #define CONFIG_NAND_FSL_IFC 255 #define CONFIG_NAND_FSL_IFC
256 #define CONFIG_SYS_NAND_BASE 0xff800000 256 #define CONFIG_SYS_NAND_BASE 0xff800000
257 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 257 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
258 258
259 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 259 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
260 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 260 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
261 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 261 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
262 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 262 | CSPR_MSEL_NAND /* MSEL = NAND */ \
263 | CSPR_V) 263 | CSPR_V)
264 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 264 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
265 265
266 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 266 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
267 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 267 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
268 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 268 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
269 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 269 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
270 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 270 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
271 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 271 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
272 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 272 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
273 273
274 #define CONFIG_SYS_NAND_ONFI_DETECTION 274 #define CONFIG_SYS_NAND_ONFI_DETECTION
275 275
276 /* ONFI NAND Flash mode0 Timing Params */ 276 /* ONFI NAND Flash mode0 Timing Params */
277 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 277 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
278 FTIM0_NAND_TWP(0x18) | \ 278 FTIM0_NAND_TWP(0x18) | \
279 FTIM0_NAND_TWCHT(0x07) | \ 279 FTIM0_NAND_TWCHT(0x07) | \
280 FTIM0_NAND_TWH(0x0a)) 280 FTIM0_NAND_TWH(0x0a))
281 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 281 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
282 FTIM1_NAND_TWBE(0x39) | \ 282 FTIM1_NAND_TWBE(0x39) | \
283 FTIM1_NAND_TRR(0x0e) | \ 283 FTIM1_NAND_TRR(0x0e) | \
284 FTIM1_NAND_TRP(0x18)) 284 FTIM1_NAND_TRP(0x18))
285 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 285 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
286 FTIM2_NAND_TREH(0x0a) | \ 286 FTIM2_NAND_TREH(0x0a) | \
287 FTIM2_NAND_TWHRE(0x1e)) 287 FTIM2_NAND_TWHRE(0x1e))
288 #define CONFIG_SYS_NAND_FTIM3 0x0 288 #define CONFIG_SYS_NAND_FTIM3 0x0
289 289
290 #define CONFIG_SYS_NAND_DDR_LAW 11 290 #define CONFIG_SYS_NAND_DDR_LAW 11
291 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 291 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
292 #define CONFIG_SYS_MAX_NAND_DEVICE 1 292 #define CONFIG_SYS_MAX_NAND_DEVICE 1
293 #define CONFIG_MTD_NAND_VERIFY_WRITE 293 #define CONFIG_MTD_NAND_VERIFY_WRITE
294 #define CONFIG_CMD_NAND 294 #define CONFIG_CMD_NAND
295 295
296 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 296 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
297 297
298 #if defined(CONFIG_NAND) 298 #if defined(CONFIG_NAND)
299 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 299 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
300 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 300 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
301 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 301 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
302 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 302 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
303 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 303 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
304 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 304 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
305 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 305 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
306 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 306 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
307 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 307 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
308 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 308 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
309 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 309 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
310 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 310 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
311 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 311 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
312 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 312 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
313 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 313 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
314 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 314 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
315 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 315 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
316 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 316 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
317 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 317 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
318 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 318 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
319 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 319 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
320 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 320 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
321 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 321 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
322 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 322 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
323 #else 323 #else
324 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 324 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
325 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 325 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
326 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 326 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
327 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 327 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
328 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 328 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
329 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 329 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
330 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 330 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
331 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 331 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
332 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 332 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
333 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 333 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
334 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 334 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
335 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 335 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
336 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 336 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
337 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 337 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
338 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 338 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
339 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 339 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
340 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 340 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
341 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 341 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
342 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 342 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
343 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 343 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
344 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 344 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
345 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 345 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
346 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 346 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
347 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 347 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
348 #endif 348 #endif
349 349
350 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 350 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
351 351
352 #if defined(CONFIG_RAMBOOT_PBL) 352 #if defined(CONFIG_RAMBOOT_PBL)
353 #define CONFIG_SYS_RAMBOOT 353 #define CONFIG_SYS_RAMBOOT
354 #endif 354 #endif
355 355
356 #define CONFIG_BOARD_EARLY_INIT_R 356 #define CONFIG_BOARD_EARLY_INIT_R
357 #define CONFIG_MISC_INIT_R 357 #define CONFIG_MISC_INIT_R
358 358
359 #define CONFIG_HWCONFIG 359 #define CONFIG_HWCONFIG
360 360
361 /* define to use L1 as initial stack */ 361 /* define to use L1 as initial stack */
362 #define CONFIG_L1_INIT_RAM 362 #define CONFIG_L1_INIT_RAM
363 #define CONFIG_SYS_INIT_RAM_LOCK 363 #define CONFIG_SYS_INIT_RAM_LOCK
364 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 364 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
365 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 365 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
366 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 366 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
367 /* The assembler doesn't like typecast */ 367 /* The assembler doesn't like typecast */
368 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 368 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
369 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 369 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
370 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 370 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
371 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 371 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
372 372
373 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 373 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
374 GENERATED_GBL_DATA_SIZE) 374 GENERATED_GBL_DATA_SIZE)
375 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 375 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
376 376
377 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 377 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
378 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 378 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
379 379
380 /* Serial Port - controlled on board with jumper J8 380 /* Serial Port - controlled on board with jumper J8
381 * open - index 2 381 * open - index 2
382 * shorted - index 1 382 * shorted - index 1
383 */ 383 */
384 #define CONFIG_CONS_INDEX 1 384 #define CONFIG_CONS_INDEX 1
385 #define CONFIG_SYS_NS16550 385 #define CONFIG_SYS_NS16550
386 #define CONFIG_SYS_NS16550_SERIAL 386 #define CONFIG_SYS_NS16550_SERIAL
387 #define CONFIG_SYS_NS16550_REG_SIZE 1 387 #define CONFIG_SYS_NS16550_REG_SIZE 1
388 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 388 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
389 389
390 #define CONFIG_SYS_BAUDRATE_TABLE \ 390 #define CONFIG_SYS_BAUDRATE_TABLE \
391 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 391 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
392 392
393 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 393 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
394 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 394 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
395 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 395 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
396 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 396 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
397 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 397 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
398 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 398 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
399 399
400 /* Use the HUSH parser */ 400 /* Use the HUSH parser */
401 #define CONFIG_SYS_HUSH_PARSER 401 #define CONFIG_SYS_HUSH_PARSER
402 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 402 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
403 403
404 /* Video */
405 #define CONFIG_FSL_DIU_FB
406 #ifdef CONFIG_FSL_DIU_FB
407 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
408 #define CONFIG_VIDEO
409 #define CONFIG_CMD_BMP
410 #define CONFIG_CFB_CONSOLE
411 #define CONFIG_VIDEO_SW_CURSOR
412 #define CONFIG_VGA_AS_SINGLE_DEVICE
413 #define CONFIG_VIDEO_LOGO
414 #define CONFIG_VIDEO_BMP_LOGO
415 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
416 /*
417 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
418 * disable empty flash sector detection, which is I/O-intensive.
419 */
420 #undef CONFIG_SYS_FLASH_EMPTY_INFO
421 #endif
422
404 /* pass open firmware flat tree */ 423 /* pass open firmware flat tree */
405 #define CONFIG_OF_LIBFDT 424 #define CONFIG_OF_LIBFDT
406 #define CONFIG_OF_BOARD_SETUP 425 #define CONFIG_OF_BOARD_SETUP
407 #define CONFIG_OF_STDOUT_VIA_ALIAS 426 #define CONFIG_OF_STDOUT_VIA_ALIAS
408 427
409 /* new uImage format support */ 428 /* new uImage format support */
410 #define CONFIG_FIT 429 #define CONFIG_FIT
411 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 430 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
412 431
413 /* I2C */ 432 /* I2C */
414 #define CONFIG_SYS_I2C 433 #define CONFIG_SYS_I2C
415 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 434 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
416 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 435 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
417 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 436 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
418 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 437 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
419 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 438 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
420 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 439 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
421 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 440 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
422 441
423 #define I2C_MUX_PCA_ADDR 0x77 442 #define I2C_MUX_PCA_ADDR 0x77
424 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 443 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
425 444
426 445
427 /* I2C bus multiplexer */ 446 /* I2C bus multiplexer */
428 #define I2C_MUX_CH_DEFAULT 0x8 447 #define I2C_MUX_CH_DEFAULT 0x8
448 #define I2C_MUX_CH_DIU 0xC
429 449
450 /* LDI/DVI Encoder for display */
451 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
452 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
453
430 /* 454 /*
431 * RTC configuration 455 * RTC configuration
432 */ 456 */
433 #define RTC 457 #define RTC
434 #define CONFIG_RTC_DS3231 1 458 #define CONFIG_RTC_DS3231 1
435 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 459 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
436 460
437 /* 461 /*
438 * eSPI - Enhanced SPI 462 * eSPI - Enhanced SPI
439 */ 463 */
440 #define CONFIG_FSL_ESPI 464 #define CONFIG_FSL_ESPI
441 #define CONFIG_SPI_FLASH 465 #define CONFIG_SPI_FLASH
442 #define CONFIG_SPI_FLASH_STMICRO 466 #define CONFIG_SPI_FLASH_STMICRO
443 #define CONFIG_SPI_FLASH_SST 467 #define CONFIG_SPI_FLASH_SST
444 #define CONFIG_SPI_FLASH_EON 468 #define CONFIG_SPI_FLASH_EON
445 #define CONFIG_CMD_SF 469 #define CONFIG_CMD_SF
446 #define CONFIG_SF_DEFAULT_SPEED 10000000 470 #define CONFIG_SF_DEFAULT_SPEED 10000000
447 #define CONFIG_SF_DEFAULT_MODE 0 471 #define CONFIG_SF_DEFAULT_MODE 0
448 472
449 /* 473 /*
450 * General PCI 474 * General PCI
451 * Memory space is mapped 1-1, but I/O space must start from 0. 475 * Memory space is mapped 1-1, but I/O space must start from 0.
452 */ 476 */
453 477
454 #ifdef CONFIG_PCI 478 #ifdef CONFIG_PCI
455 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 479 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
456 #ifdef CONFIG_PCIE1 480 #ifdef CONFIG_PCIE1
457 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 481 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
458 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 482 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
459 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 483 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
460 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 484 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
461 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 485 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
462 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 486 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
463 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 487 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
464 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 488 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
465 #endif 489 #endif
466 490
467 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 491 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
468 #ifdef CONFIG_PCIE2 492 #ifdef CONFIG_PCIE2
469 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 493 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
470 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 494 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
471 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 495 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
472 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 496 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
473 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 497 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
474 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 498 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
475 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 499 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
476 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 500 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
477 #endif 501 #endif
478 502
479 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 503 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
480 #ifdef CONFIG_PCIE3 504 #ifdef CONFIG_PCIE3
481 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 505 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
482 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 506 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
483 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 507 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
484 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 508 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
485 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 509 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
486 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 510 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
487 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 511 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
488 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 512 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
489 #endif 513 #endif
490 514
491 /* controller 4, Base address 203000 */ 515 /* controller 4, Base address 203000 */
492 #ifdef CONFIG_PCIE4 516 #ifdef CONFIG_PCIE4
493 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 517 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
494 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 518 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
495 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 519 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
496 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 520 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
497 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 521 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
498 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 522 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
499 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 523 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
500 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 524 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
501 #endif 525 #endif
502 526
503 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 527 #define CONFIG_PCI_PNP /* do pci plug-and-play */
504 #define CONFIG_E1000 528 #define CONFIG_E1000
505 529
506 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 530 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
507 #define CONFIG_DOS_PARTITION 531 #define CONFIG_DOS_PARTITION
508 #endif /* CONFIG_PCI */ 532 #endif /* CONFIG_PCI */
509 533
510 /* SATA */ 534 /* SATA */
511 #define CONFIG_FSL_SATA_V2 535 #define CONFIG_FSL_SATA_V2
512 #ifdef CONFIG_FSL_SATA_V2 536 #ifdef CONFIG_FSL_SATA_V2
513 #define CONFIG_LIBATA 537 #define CONFIG_LIBATA
514 #define CONFIG_FSL_SATA 538 #define CONFIG_FSL_SATA
515 539
516 #define CONFIG_SYS_SATA_MAX_DEVICE 2 540 #define CONFIG_SYS_SATA_MAX_DEVICE 2
517 #define CONFIG_SATA1 541 #define CONFIG_SATA1
518 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 542 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
519 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 543 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
520 #define CONFIG_SATA2 544 #define CONFIG_SATA2
521 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 545 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
522 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 546 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
523 547
524 #define CONFIG_LBA48 548 #define CONFIG_LBA48
525 #define CONFIG_CMD_SATA 549 #define CONFIG_CMD_SATA
526 #define CONFIG_DOS_PARTITION 550 #define CONFIG_DOS_PARTITION
527 #define CONFIG_CMD_EXT2 551 #define CONFIG_CMD_EXT2
528 #endif 552 #endif
529 553
530 /* 554 /*
531 * USB 555 * USB
532 */ 556 */
533 #define CONFIG_HAS_FSL_DR_USB 557 #define CONFIG_HAS_FSL_DR_USB
534 558
535 #ifdef CONFIG_HAS_FSL_DR_USB 559 #ifdef CONFIG_HAS_FSL_DR_USB
536 #define CONFIG_USB_EHCI 560 #define CONFIG_USB_EHCI
537 561
538 #ifdef CONFIG_USB_EHCI 562 #ifdef CONFIG_USB_EHCI
539 #define CONFIG_CMD_USB 563 #define CONFIG_CMD_USB
540 #define CONFIG_USB_STORAGE 564 #define CONFIG_USB_STORAGE
541 #define CONFIG_USB_EHCI_FSL 565 #define CONFIG_USB_EHCI_FSL
542 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 566 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
543 #define CONFIG_CMD_EXT2 567 #define CONFIG_CMD_EXT2
544 #endif 568 #endif
545 #endif 569 #endif
546 570
547 #define CONFIG_MMC 571 #define CONFIG_MMC
548 572
549 #ifdef CONFIG_MMC 573 #ifdef CONFIG_MMC
550 #define CONFIG_FSL_ESDHC 574 #define CONFIG_FSL_ESDHC
551 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 575 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
552 #define CONFIG_CMD_MMC 576 #define CONFIG_CMD_MMC
553 #define CONFIG_GENERIC_MMC 577 #define CONFIG_GENERIC_MMC
554 #define CONFIG_CMD_EXT2 578 #define CONFIG_CMD_EXT2
555 #define CONFIG_CMD_FAT 579 #define CONFIG_CMD_FAT
556 #define CONFIG_DOS_PARTITION 580 #define CONFIG_DOS_PARTITION
557 #endif 581 #endif
558 582
559 /* Qman/Bman */ 583 /* Qman/Bman */
560 #ifndef CONFIG_NOBQFMAN 584 #ifndef CONFIG_NOBQFMAN
561 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 585 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
562 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 586 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
563 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 587 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
564 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 588 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
565 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 589 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
566 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 590 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
567 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 591 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
568 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 592 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
569 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 593 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
570 594
571 #define CONFIG_SYS_DPAA_FMAN 595 #define CONFIG_SYS_DPAA_FMAN
572 #define CONFIG_SYS_DPAA_PME 596 #define CONFIG_SYS_DPAA_PME
573 597
574 /* Default address of microcode for the Linux Fman driver */ 598 /* Default address of microcode for the Linux Fman driver */
575 #if defined(CONFIG_SPIFLASH) 599 #if defined(CONFIG_SPIFLASH)
576 /* 600 /*
577 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 601 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
578 * env, so we got 0x110000. 602 * env, so we got 0x110000.
579 */ 603 */
580 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 604 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
581 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 605 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
582 #elif defined(CONFIG_SDCARD) 606 #elif defined(CONFIG_SDCARD)
583 /* 607 /*
584 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 608 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
585 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 609 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
586 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 610 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
587 */ 611 */
588 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 612 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
589 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) 613 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
590 #elif defined(CONFIG_NAND) 614 #elif defined(CONFIG_NAND)
591 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 615 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
592 #define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 616 #define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
593 #else 617 #else
594 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 618 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
595 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 619 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
596 #endif 620 #endif
597 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 621 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
598 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 622 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
599 #endif /* CONFIG_NOBQFMAN */ 623 #endif /* CONFIG_NOBQFMAN */
600 624
601 #ifdef CONFIG_SYS_DPAA_FMAN 625 #ifdef CONFIG_SYS_DPAA_FMAN
602 #define CONFIG_FMAN_ENET 626 #define CONFIG_FMAN_ENET
603 #define CONFIG_PHYLIB_10G 627 #define CONFIG_PHYLIB_10G
604 #define CONFIG_PHY_VITESSE 628 #define CONFIG_PHY_VITESSE
605 #define CONFIG_PHY_REALTEK 629 #define CONFIG_PHY_REALTEK
606 #define CONFIG_PHY_TERANETICS 630 #define CONFIG_PHY_TERANETICS
607 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 631 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
608 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 632 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
609 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 633 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
610 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 634 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
611 #endif 635 #endif
612 636
613 #ifdef CONFIG_FMAN_ENET 637 #ifdef CONFIG_FMAN_ENET
614 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 638 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
615 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 639 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
616 640
617 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 641 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
618 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 642 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
619 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 643 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
620 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 644 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
621 645
622 #define CONFIG_MII /* MII PHY management */ 646 #define CONFIG_MII /* MII PHY management */
623 #define CONFIG_ETHPRIME "FM1@DTSEC1" 647 #define CONFIG_ETHPRIME "FM1@DTSEC1"
624 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 648 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
625 #endif 649 #endif
626 650
627 /* 651 /*
628 * Environment 652 * Environment
629 */ 653 */
630 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 654 #define CONFIG_LOADS_ECHO /* echo on for serial download */
631 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 655 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
632 656
633 /* 657 /*
634 * Command line configuration. 658 * Command line configuration.
635 */ 659 */
636 #include <config_cmd_default.h> 660 #include <config_cmd_default.h>
637 661
638 #define CONFIG_CMD_DATE 662 #define CONFIG_CMD_DATE
639 #define CONFIG_CMD_DHCP 663 #define CONFIG_CMD_DHCP
640 #define CONFIG_CMD_EEPROM 664 #define CONFIG_CMD_EEPROM
641 #define CONFIG_CMD_ELF 665 #define CONFIG_CMD_ELF
642 #define CONFIG_CMD_ERRATA 666 #define CONFIG_CMD_ERRATA
643 #define CONFIG_CMD_GREPENV 667 #define CONFIG_CMD_GREPENV
644 #define CONFIG_CMD_IRQ 668 #define CONFIG_CMD_IRQ
645 #define CONFIG_CMD_I2C 669 #define CONFIG_CMD_I2C
646 #define CONFIG_CMD_MII 670 #define CONFIG_CMD_MII
647 #define CONFIG_CMD_PING 671 #define CONFIG_CMD_PING
648 #define CONFIG_CMD_REGINFO 672 #define CONFIG_CMD_REGINFO
649 #define CONFIG_CMD_SETEXPR 673 #define CONFIG_CMD_SETEXPR
650 674
651 #ifdef CONFIG_PCI 675 #ifdef CONFIG_PCI
652 #define CONFIG_CMD_PCI 676 #define CONFIG_CMD_PCI
653 #define CONFIG_CMD_NET 677 #define CONFIG_CMD_NET
654 #endif 678 #endif
655 679
656 /* 680 /*
657 * Miscellaneous configurable options 681 * Miscellaneous configurable options
658 */ 682 */
659 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 683 #define CONFIG_SYS_LONGHELP /* undef to save memory */
660 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 684 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
661 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 685 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
662 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 686 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
663 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 687 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
664 #ifdef CONFIG_CMD_KGDB 688 #ifdef CONFIG_CMD_KGDB
665 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 689 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
666 #else 690 #else
667 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 691 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
668 #endif 692 #endif
669 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 693 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
670 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 694 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
671 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 695 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
672 696
673 /* 697 /*
674 * For booting Linux, the board info and command line data 698 * For booting Linux, the board info and command line data
675 * have to be in the first 64 MB of memory, since this is 699 * have to be in the first 64 MB of memory, since this is
676 * the maximum mapped by the Linux kernel during initialization. 700 * the maximum mapped by the Linux kernel during initialization.
677 */ 701 */
678 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 702 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
679 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 703 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
680 704
681 #ifdef CONFIG_CMD_KGDB 705 #ifdef CONFIG_CMD_KGDB
682 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 706 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
683 #endif 707 #endif
684 708
685 /* 709 /*
686 * Environment Configuration 710 * Environment Configuration
687 */ 711 */
688 #define CONFIG_ROOTPATH "/opt/nfsroot" 712 #define CONFIG_ROOTPATH "/opt/nfsroot"
689 #define CONFIG_BOOTFILE "uImage" 713 #define CONFIG_BOOTFILE "uImage"
690 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 714 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
691 715
692 /* default location for tftp and bootm */ 716 /* default location for tftp and bootm */
693 #define CONFIG_LOADADDR 1000000 717 #define CONFIG_LOADADDR 1000000
694 718
695 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 719 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
696 720
697 #define CONFIG_BAUDRATE 115200 721 #define CONFIG_BAUDRATE 115200
698 722
699 #define __USB_PHY_TYPE utmi 723 #define __USB_PHY_TYPE utmi
700 724
701 #define CONFIG_EXTRA_ENV_SETTINGS \ 725 #define CONFIG_EXTRA_ENV_SETTINGS \
702 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 726 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
703 "bank_intlv=cs0_cs1;" \ 727 "bank_intlv=cs0_cs1;" \
704 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 728 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
705 "netdev=eth0\0" \ 729 "netdev=eth0\0" \
730 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
706 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 731 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
707 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 732 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
708 "tftpflash=tftpboot $loadaddr $uboot && " \ 733 "tftpflash=tftpboot $loadaddr $uboot && " \
709 "protect off $ubootaddr +$filesize && " \ 734 "protect off $ubootaddr +$filesize && " \
710 "erase $ubootaddr +$filesize && " \ 735 "erase $ubootaddr +$filesize && " \
711 "cp.b $loadaddr $ubootaddr $filesize && " \ 736 "cp.b $loadaddr $ubootaddr $filesize && " \
712 "protect on $ubootaddr +$filesize && " \ 737 "protect on $ubootaddr +$filesize && " \
713 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 738 "cmp.b $loadaddr $ubootaddr $filesize\0" \
714 "consoledev=ttyS0\0" \ 739 "consoledev=ttyS0\0" \
715 "ramdiskaddr=2000000\0" \ 740 "ramdiskaddr=2000000\0" \
716 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 741 "ramdiskfile=t1040qds/ramdisk.uboot\0" \
717 "fdtaddr=c00000\0" \ 742 "fdtaddr=c00000\0" \
718 "fdtfile=t1040qds/t1040qds.dtb\0" \ 743 "fdtfile=t1040qds/t1040qds.dtb\0" \
719 "bdev=sda3\0" \ 744 "bdev=sda3\0" \
720 "c=ffe\0" 745 "c=ffe\0"
721 746
722 #define CONFIG_LINUX \ 747 #define CONFIG_LINUX \
723 "setenv bootargs root=/dev/ram rw " \ 748 "setenv bootargs root=/dev/ram rw " \
724 "console=$consoledev,$baudrate $othbootargs;" \ 749 "console=$consoledev,$baudrate $othbootargs;" \
725 "setenv ramdiskaddr 0x02000000;" \ 750 "setenv ramdiskaddr 0x02000000;" \
726 "setenv fdtaddr 0x00c00000;" \ 751 "setenv fdtaddr 0x00c00000;" \
727 "setenv loadaddr 0x1000000;" \ 752 "setenv loadaddr 0x1000000;" \
728 "bootm $loadaddr $ramdiskaddr $fdtaddr" 753 "bootm $loadaddr $ramdiskaddr $fdtaddr"
729 754
730 #define CONFIG_HDBOOT \ 755 #define CONFIG_HDBOOT \
731 "setenv bootargs root=/dev/$bdev rw " \ 756 "setenv bootargs root=/dev/$bdev rw " \
732 "console=$consoledev,$baudrate $othbootargs;" \ 757 "console=$consoledev,$baudrate $othbootargs;" \
733 "tftp $loadaddr $bootfile;" \ 758 "tftp $loadaddr $bootfile;" \
734 "tftp $fdtaddr $fdtfile;" \ 759 "tftp $fdtaddr $fdtfile;" \
735 "bootm $loadaddr - $fdtaddr" 760 "bootm $loadaddr - $fdtaddr"
736 761
737 #define CONFIG_NFSBOOTCOMMAND \ 762 #define CONFIG_NFSBOOTCOMMAND \
738 "setenv bootargs root=/dev/nfs rw " \ 763 "setenv bootargs root=/dev/nfs rw " \
739 "nfsroot=$serverip:$rootpath " \ 764 "nfsroot=$serverip:$rootpath " \
740 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 765 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
741 "console=$consoledev,$baudrate $othbootargs;" \ 766 "console=$consoledev,$baudrate $othbootargs;" \
742 "tftp $loadaddr $bootfile;" \ 767 "tftp $loadaddr $bootfile;" \
743 "tftp $fdtaddr $fdtfile;" \ 768 "tftp $fdtaddr $fdtfile;" \
744 "bootm $loadaddr - $fdtaddr" 769 "bootm $loadaddr - $fdtaddr"
745 770
746 #define CONFIG_RAMBOOTCOMMAND \ 771 #define CONFIG_RAMBOOTCOMMAND \
747 "setenv bootargs root=/dev/ram rw " \ 772 "setenv bootargs root=/dev/ram rw " \
748 "console=$consoledev,$baudrate $othbootargs;" \ 773 "console=$consoledev,$baudrate $othbootargs;" \
749 "tftp $ramdiskaddr $ramdiskfile;" \ 774 "tftp $ramdiskaddr $ramdiskfile;" \
750 "tftp $loadaddr $bootfile;" \ 775 "tftp $loadaddr $bootfile;" \
751 "tftp $fdtaddr $fdtfile;" \ 776 "tftp $fdtaddr $fdtfile;" \
752 "bootm $loadaddr $ramdiskaddr $fdtaddr" 777 "bootm $loadaddr $ramdiskaddr $fdtaddr"
753 778
754 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 779 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
755 780
756 #ifdef CONFIG_SECURE_BOOT 781 #ifdef CONFIG_SECURE_BOOT
757 #include <asm/fsl_secure_boot.h> 782 #include <asm/fsl_secure_boot.h>
758 #endif 783 #endif
759 784
760 #endif /* __CONFIG_H */ 785 #endif /* __CONFIG_H */
761 786