Eric Lee / smarc-uboot

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Commit 3433a693a9cf143b6e5f0d7190b4df4d1c82418e

Authored by Simon Glass
Committed by Tom Rini
1 parent f73329ee82
Exists in v2017.01-smarct4x and in 25 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Move existing use of CONFIG_SPL_DM to Kconfig 

A few boards define this in a header file which is incorrect. It means that
Kconfig options that rely on this cannot be used. Move it.

Note that quite a few boards defined this options but do not appear to
actually use SPL:

	BSC9132QDS_NOR_DDRCLK100_SECURE
	BSC9132QDS_NOR_DDRCLK133_SECURE
	BSC9132QDS_SDCARD_DDRCLK100_SECURE
	BSC9132QDS_SDCARD_DDRCLK133_SECURE
	BSC9132QDS_SPIFLASH_DDRCLK100_SECURE
	BSC9132QDS_SPIFLASH_DDRCLK133_SECURE
	C29XPCIE_NOR_SECBOOT
	P1010RDB-PA_36BIT_NAND_SECBOOT
	P1010RDB-PA_36BIT_SPIFLASH_SECBOOT
	P1010RDB-PA_NAND_SECBOOT
	P1010RDB-PA_NOR_SECBOOT
	P1010RDB-PB_36BIT_NOR_SECBOOT
	P1010RDB-PB_36BIT_SPIFLASH_SECBOOT
	P1010RDB-PB_NAND_SECBOOT
	P1010RDB-PB_NOR_SECBOOT
	P3041DS_SECURE_BOOT
	P4080DS_SECURE_BOOT
	P5020DS_NAND_SECURE_BOOT
	P5040DS_SECURE_BOOT
	T1023RDB_SECURE_BOOT
	T1024QDS_DDR4_SECURE_BOOT
	T1024QDS_SECURE_BOOT
	T1024RDB_SECURE_BOOT
	T1040RDB_SECURE_BOOT
	T1042D4RDB_SECURE_BOOT
	T1042RDB_SECURE_BOOT
	T2080QDS_SECURE_BOOT
	T2080RDB_SECURE_BOOT
	T4160QDS_SECURE_BOOT
	T4240QDS_SECURE_BOOT
	ls1021aqds_nor_SECURE_BOOT
	ls1021atwr_nor_SECURE_BOOT
	ls1043ardb_SECURE_BOOT

For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since
they apparently don't have an SPL, this should not matter.

Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 4 changed files with 2 additions and 2 deletions Inline Diff

arch/arm/include/asm/fsl_secure_boot.h
Diff comments   View file @ 3433a69
1 /* 1 /*
2 * Copyright 2015 Freescale Semiconductor, Inc. 2 * Copyright 2015 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __FSL_SECURE_BOOT_H 7 #ifndef __FSL_SECURE_BOOT_H
8 #define __FSL_SECURE_BOOT_H 8 #define __FSL_SECURE_BOOT_H
9 9
10 #ifdef CONFIG_SECURE_BOOT 10 #ifdef CONFIG_SECURE_BOOT
11 11
12 #ifndef CONFIG_FIT_SIGNATURE 12 #ifndef CONFIG_FIT_SIGNATURE
13 #define CONFIG_CHAIN_OF_TRUST 13 #define CONFIG_CHAIN_OF_TRUST
14 #endif 14 #endif
15 15
16 #endif 16 #endif
17 17
18 #ifdef CONFIG_CHAIN_OF_TRUST 18 #ifdef CONFIG_CHAIN_OF_TRUST
19 #define CONFIG_CMD_ESBC_VALIDATE 19 #define CONFIG_CMD_ESBC_VALIDATE
20 #define CONFIG_FSL_SEC_MON 20 #define CONFIG_FSL_SEC_MON
21 #define CONFIG_SHA_HW_ACCEL 21 #define CONFIG_SHA_HW_ACCEL
22 #define CONFIG_SHA_PROG_HW_ACCEL 22 #define CONFIG_SHA_PROG_HW_ACCEL
23 #define CONFIG_RSA_FREESCALE_EXP 23 #define CONFIG_RSA_FREESCALE_EXP
24 24
25 #ifndef CONFIG_FSL_CAAM 25 #ifndef CONFIG_FSL_CAAM
26 #define CONFIG_FSL_CAAM 26 #define CONFIG_FSL_CAAM
27 #endif 27 #endif
28 28
29 #define CONFIG_SPL_BOARD_INIT 29 #define CONFIG_SPL_BOARD_INIT
30 #define CONFIG_SPL_DM 1
31 #define CONFIG_SPL_CRYPTO_SUPPORT 30 #define CONFIG_SPL_CRYPTO_SUPPORT
32 #define CONFIG_SPL_HASH_SUPPORT 31 #define CONFIG_SPL_HASH_SUPPORT
33 #define CONFIG_SPL_RSA 32 #define CONFIG_SPL_RSA
34 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 33 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
35 #ifdef CONFIG_SPL_BUILD 34 #ifdef CONFIG_SPL_BUILD
36 /* 35 /*
37 * Define the key hash for U-Boot here if public/private key pair used to 36 * Define the key hash for U-Boot here if public/private key pair used to
38 * sign U-boot are different from the SRK hash put in the fuse 37 * sign U-boot are different from the SRK hash put in the fuse
39 * Example of defining KEY_HASH is 38 * Example of defining KEY_HASH is
40 * #define CONFIG_SPL_UBOOT_KEY_HASH \ 39 * #define CONFIG_SPL_UBOOT_KEY_HASH \
41 * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" 40 * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
42 * else leave it defined as NULL 41 * else leave it defined as NULL
43 */ 42 */
44 43
45 #define CONFIG_SPL_UBOOT_KEY_HASH NULL 44 #define CONFIG_SPL_UBOOT_KEY_HASH NULL
46 #endif /* ifdef CONFIG_SPL_BUILD */ 45 #endif /* ifdef CONFIG_SPL_BUILD */
47 46
48 #ifndef CONFIG_SPL_BUILD 47 #ifndef CONFIG_SPL_BUILD
49 #define CONFIG_CMD_BLOB 48 #define CONFIG_CMD_BLOB
50 #define CONFIG_CMD_HASH 49 #define CONFIG_CMD_HASH
51 #define CONFIG_KEY_REVOCATION 50 #define CONFIG_KEY_REVOCATION
52 #ifndef CONFIG_SYS_RAMBOOT 51 #ifndef CONFIG_SYS_RAMBOOT
53 /* The key used for verification of next level images 52 /* The key used for verification of next level images
54 * is picked up from an Extension Table which has 53 * is picked up from an Extension Table which has
55 * been verified by the ISBC (Internal Secure boot Code) 54 * been verified by the ISBC (Internal Secure boot Code)
56 * in boot ROM of the SoC. 55 * in boot ROM of the SoC.
57 * The feature is only applicable in case of NOR boot and is 56 * The feature is only applicable in case of NOR boot and is
58 * not applicable in case of RAMBOOT (NAND, SD, SPI). 57 * not applicable in case of RAMBOOT (NAND, SD, SPI).
59 */ 58 */
60 #ifndef CONFIG_ESBC_HDR_LS 59 #ifndef CONFIG_ESBC_HDR_LS
61 /* Current Key EXT feature not available in LS ESBC Header */ 60 /* Current Key EXT feature not available in LS ESBC Header */
62 #define CONFIG_FSL_ISBC_KEY_EXT 61 #define CONFIG_FSL_ISBC_KEY_EXT
63 #endif 62 #endif
64 63
65 #endif 64 #endif
66 65
67 #if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) 66 #if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A)
68 /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit 67 /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
69 * Similiarly for LS2080 68 * Similiarly for LS2080
70 */ 69 */
71 #define CONFIG_ESBC_ADDR_64BIT 70 #define CONFIG_ESBC_ADDR_64BIT
72 #endif 71 #endif
73 72
74 #ifdef CONFIG_LS2080A 73 #ifdef CONFIG_LS2080A
75 #define CONFIG_EXTRA_ENV \ 74 #define CONFIG_EXTRA_ENV \
76 "setenv fdt_high 0xa0000000;" \ 75 "setenv fdt_high 0xa0000000;" \
77 "setenv initrd_high 0xcfffffff;" \ 76 "setenv initrd_high 0xcfffffff;" \
78 "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" 77 "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
79 #else 78 #else
80 #define CONFIG_EXTRA_ENV \ 79 #define CONFIG_EXTRA_ENV \
81 "setenv fdt_high 0xffffffff;" \ 80 "setenv fdt_high 0xffffffff;" \
82 "setenv initrd_high 0xffffffff;" \ 81 "setenv initrd_high 0xffffffff;" \
83 "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" 82 "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
84 #endif 83 #endif
85 84
86 /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from 85 /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
87 * Non-XIP Memory (Nand/SD)*/ 86 * Non-XIP Memory (Nand/SD)*/
88 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) || \ 87 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) || \
89 defined(CONFIG_SD_BOOT) 88 defined(CONFIG_SD_BOOT)
90 #define CONFIG_BOOTSCRIPT_COPY_RAM 89 #define CONFIG_BOOTSCRIPT_COPY_RAM
91 #endif 90 #endif
92 /* The address needs to be modified according to NOR, NAND, SD and 91 /* The address needs to be modified according to NOR, NAND, SD and
93 * DDR memory map 92 * DDR memory map
94 */ 93 */
95 #ifdef CONFIG_LS2080A 94 #ifdef CONFIG_LS2080A
96 #define CONFIG_BS_HDR_ADDR_DEVICE 0x583920000 95 #define CONFIG_BS_HDR_ADDR_DEVICE 0x583920000
97 #define CONFIG_BS_ADDR_DEVICE 0x583900000 96 #define CONFIG_BS_ADDR_DEVICE 0x583900000
98 #define CONFIG_BS_HDR_ADDR_RAM 0xa3920000 97 #define CONFIG_BS_HDR_ADDR_RAM 0xa3920000
99 #define CONFIG_BS_ADDR_RAM 0xa3900000 98 #define CONFIG_BS_ADDR_RAM 0xa3900000
100 #define CONFIG_BS_HDR_SIZE 0x00002000 99 #define CONFIG_BS_HDR_SIZE 0x00002000
101 #define CONFIG_BS_SIZE 0x00001000 100 #define CONFIG_BS_SIZE 0x00001000
102 #else 101 #else
103 #ifdef CONFIG_SD_BOOT 102 #ifdef CONFIG_SD_BOOT
104 /* For SD boot address and size are assigned in terms of sector 103 /* For SD boot address and size are assigned in terms of sector
105 * offset and no. of sectors respectively. 104 * offset and no. of sectors respectively.
106 */ 105 */
107 #define CONFIG_BS_HDR_ADDR_DEVICE 0x00000800 106 #define CONFIG_BS_HDR_ADDR_DEVICE 0x00000800
108 #define CONFIG_BS_ADDR_DEVICE 0x00000840 107 #define CONFIG_BS_ADDR_DEVICE 0x00000840
109 #define CONFIG_BS_HDR_SIZE 0x00000010 108 #define CONFIG_BS_HDR_SIZE 0x00000010
110 #define CONFIG_BS_SIZE 0x00000008 109 #define CONFIG_BS_SIZE 0x00000008
111 #else 110 #else
112 #define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000 111 #define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000
113 #define CONFIG_BS_ADDR_DEVICE 0x60060000 112 #define CONFIG_BS_ADDR_DEVICE 0x60060000
114 #define CONFIG_BS_HDR_SIZE 0x00002000 113 #define CONFIG_BS_HDR_SIZE 0x00002000
115 #define CONFIG_BS_SIZE 0x00001000 114 #define CONFIG_BS_SIZE 0x00001000
116 #endif /* #ifdef CONFIG_SD_BOOT */ 115 #endif /* #ifdef CONFIG_SD_BOOT */
117 #define CONFIG_BS_HDR_ADDR_RAM 0x81000000 116 #define CONFIG_BS_HDR_ADDR_RAM 0x81000000
118 #define CONFIG_BS_ADDR_RAM 0x81020000 117 #define CONFIG_BS_ADDR_RAM 0x81020000
119 #endif 118 #endif
120 119
121 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM 120 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
122 #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM 121 #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
123 #define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM 122 #define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM
124 #else 123 #else
125 #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE 124 #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE
126 /* BOOTSCRIPT_ADDR is not required */ 125 /* BOOTSCRIPT_ADDR is not required */
127 #endif 126 #endif
128 127
129 #include <config_fsl_chain_trust.h> 128 #include <config_fsl_chain_trust.h>
130 #endif /* #ifndef CONFIG_SPL_BUILD */ 129 #endif /* #ifndef CONFIG_SPL_BUILD */
131 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ 130 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
132 #endif 131 #endif
133 132
arch/powerpc/include/asm/fsl_secure_boot.h
Diff comments   View file @ 3433a69
1 /* 1 /*
2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __FSL_SECURE_BOOT_H 7 #ifndef __FSL_SECURE_BOOT_H
8 #define __FSL_SECURE_BOOT_H 8 #define __FSL_SECURE_BOOT_H
9 #include <asm/config_mpc85xx.h> 9 #include <asm/config_mpc85xx.h>
10 10
11 #ifdef CONFIG_SECURE_BOOT 11 #ifdef CONFIG_SECURE_BOOT
12 12
13 #ifndef CONFIG_FIT_SIGNATURE 13 #ifndef CONFIG_FIT_SIGNATURE
14 #define CONFIG_CHAIN_OF_TRUST 14 #define CONFIG_CHAIN_OF_TRUST
15 #endif 15 #endif
16 16
17 #if defined(CONFIG_FSL_CORENET) 17 #if defined(CONFIG_FSL_CORENET)
18 #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 18 #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
19 #elif defined(CONFIG_BSC9132QDS) 19 #elif defined(CONFIG_BSC9132QDS)
20 #define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 20 #define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
21 #elif defined(CONFIG_C29XPCIE) 21 #elif defined(CONFIG_C29XPCIE)
22 #define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000 22 #define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
23 #else 23 #else
24 #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 24 #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
25 #endif 25 #endif
26 #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 26 #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
27 27
28 #if defined(CONFIG_B4860QDS) || \ 28 #if defined(CONFIG_B4860QDS) || \
29 defined(CONFIG_T4240QDS) || \ 29 defined(CONFIG_T4240QDS) || \
30 defined(CONFIG_T2080QDS) || \ 30 defined(CONFIG_T2080QDS) || \
31 defined(CONFIG_T2080RDB) || \ 31 defined(CONFIG_T2080RDB) || \
32 defined(CONFIG_T1040QDS) || \ 32 defined(CONFIG_T1040QDS) || \
33 defined(CONFIG_T104xD4QDS) || \ 33 defined(CONFIG_T104xD4QDS) || \
34 defined(CONFIG_T104xRDB) || \ 34 defined(CONFIG_T104xRDB) || \
35 defined(CONFIG_T104xD4RDB) || \ 35 defined(CONFIG_T104xD4RDB) || \
36 defined(CONFIG_PPC_T1023) || \ 36 defined(CONFIG_PPC_T1023) || \
37 defined(CONFIG_PPC_T1024) 37 defined(CONFIG_PPC_T1024)
38 #ifndef CONFIG_SYS_RAMBOOT 38 #ifndef CONFIG_SYS_RAMBOOT
39 #define CONFIG_SYS_CPC_REINIT_F 39 #define CONFIG_SYS_CPC_REINIT_F
40 #endif 40 #endif
41 #define CONFIG_KEY_REVOCATION 41 #define CONFIG_KEY_REVOCATION
42 #undef CONFIG_SYS_INIT_L3_ADDR 42 #undef CONFIG_SYS_INIT_L3_ADDR
43 #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 43 #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
44 #endif 44 #endif
45 45
46 #if defined(CONFIG_RAMBOOT_PBL) 46 #if defined(CONFIG_RAMBOOT_PBL)
47 #undef CONFIG_SYS_INIT_L3_ADDR 47 #undef CONFIG_SYS_INIT_L3_ADDR
48 #ifdef CONFIG_SYS_INIT_L3_VADDR 48 #ifdef CONFIG_SYS_INIT_L3_VADDR
49 #define CONFIG_SYS_INIT_L3_ADDR \ 49 #define CONFIG_SYS_INIT_L3_ADDR \
50 (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ 50 (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
51 0xbff00000 51 0xbff00000
52 #else 52 #else
53 #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 53 #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
54 #endif 54 #endif
55 #endif 55 #endif
56 56
57 #if defined(CONFIG_C29XPCIE) 57 #if defined(CONFIG_C29XPCIE)
58 #define CONFIG_KEY_REVOCATION 58 #define CONFIG_KEY_REVOCATION
59 #endif 59 #endif
60 60
61 #if defined(CONFIG_PPC_P3041) || \ 61 #if defined(CONFIG_PPC_P3041) || \
62 defined(CONFIG_PPC_P4080) || \ 62 defined(CONFIG_PPC_P4080) || \
63 defined(CONFIG_PPC_P5020) || \ 63 defined(CONFIG_PPC_P5020) || \
64 defined(CONFIG_PPC_P5040) || \ 64 defined(CONFIG_PPC_P5040) || \
65 defined(CONFIG_PPC_P2041) 65 defined(CONFIG_PPC_P2041)
66 #define CONFIG_FSL_TRUST_ARCH_v1 66 #define CONFIG_FSL_TRUST_ARCH_v1
67 #endif 67 #endif
68 68
69 #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT) 69 #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
70 /* The key used for verification of next level images 70 /* The key used for verification of next level images
71 * is picked up from an Extension Table which has 71 * is picked up from an Extension Table which has
72 * been verified by the ISBC (Internal Secure boot Code) 72 * been verified by the ISBC (Internal Secure boot Code)
73 * in boot ROM of the SoC. 73 * in boot ROM of the SoC.
74 * The feature is only applicable in case of NOR boot and is 74 * The feature is only applicable in case of NOR boot and is
75 * not applicable in case of RAMBOOT (NAND, SD, SPI). 75 * not applicable in case of RAMBOOT (NAND, SD, SPI).
76 */ 76 */
77 #define CONFIG_FSL_ISBC_KEY_EXT 77 #define CONFIG_FSL_ISBC_KEY_EXT
78 #endif 78 #endif
79 #endif /* #ifdef CONFIG_SECURE_BOOT */ 79 #endif /* #ifdef CONFIG_SECURE_BOOT */
80 80
81 #ifdef CONFIG_CHAIN_OF_TRUST 81 #ifdef CONFIG_CHAIN_OF_TRUST
82 82
83 #define CONFIG_SPL_DM 1
84 #define CONFIG_SPL_CRYPTO_SUPPORT 83 #define CONFIG_SPL_CRYPTO_SUPPORT
85 #define CONFIG_SPL_HASH_SUPPORT 84 #define CONFIG_SPL_HASH_SUPPORT
86 #define CONFIG_SPL_RSA 85 #define CONFIG_SPL_RSA
87 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 86 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
88 87
89 #ifdef CONFIG_SPL_BUILD 88 #ifdef CONFIG_SPL_BUILD
90 /* 89 /*
91 * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init 90 * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
92 * due to space crunch on CPC and thus malloc will not work. 91 * due to space crunch on CPC and thus malloc will not work.
93 */ 92 */
94 #define CONFIG_SPL_PPAACT_ADDR 0x2e000000 93 #define CONFIG_SPL_PPAACT_ADDR 0x2e000000
95 #define CONFIG_SPL_SPAACT_ADDR 0x2f000000 94 #define CONFIG_SPL_SPAACT_ADDR 0x2f000000
96 #define CONFIG_SPL_JR0_LIODN_S 454 95 #define CONFIG_SPL_JR0_LIODN_S 454
97 #define CONFIG_SPL_JR0_LIODN_NS 458 96 #define CONFIG_SPL_JR0_LIODN_NS 458
98 /* 97 /*
99 * Define the key hash for U-Boot here if public/private key pair used to 98 * Define the key hash for U-Boot here if public/private key pair used to
100 * sign U-boot are different from the SRK hash put in the fuse 99 * sign U-boot are different from the SRK hash put in the fuse
101 * Example of defining KEY_HASH is 100 * Example of defining KEY_HASH is
102 * #define CONFIG_SPL_UBOOT_KEY_HASH \ 101 * #define CONFIG_SPL_UBOOT_KEY_HASH \
103 * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" 102 * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
104 * else leave it defined as NULL 103 * else leave it defined as NULL
105 */ 104 */
106 105
107 #define CONFIG_SPL_UBOOT_KEY_HASH NULL 106 #define CONFIG_SPL_UBOOT_KEY_HASH NULL
108 #endif /* ifdef CONFIG_SPL_BUILD */ 107 #endif /* ifdef CONFIG_SPL_BUILD */
109 108
110 #define CONFIG_CMD_ESBC_VALIDATE 109 #define CONFIG_CMD_ESBC_VALIDATE
111 #define CONFIG_CMD_BLOB 110 #define CONFIG_CMD_BLOB
112 #define CONFIG_FSL_SEC_MON 111 #define CONFIG_FSL_SEC_MON
113 #define CONFIG_SHA_PROG_HW_ACCEL 112 #define CONFIG_SHA_PROG_HW_ACCEL
114 #define CONFIG_RSA_FREESCALE_EXP 113 #define CONFIG_RSA_FREESCALE_EXP
115 114
116 #ifndef CONFIG_FSL_CAAM 115 #ifndef CONFIG_FSL_CAAM
117 #define CONFIG_FSL_CAAM 116 #define CONFIG_FSL_CAAM
118 #endif 117 #endif
119 118
120 #ifndef CONFIG_SPL_BUILD 119 #ifndef CONFIG_SPL_BUILD
121 /* 120 /*
122 * fsl_setenv_chain_of_trust() must be called from 121 * fsl_setenv_chain_of_trust() must be called from
123 * board_late_init() 122 * board_late_init()
124 */ 123 */
125 #ifndef CONFIG_BOARD_LATE_INIT 124 #ifndef CONFIG_BOARD_LATE_INIT
126 #define CONFIG_BOARD_LATE_INIT 125 #define CONFIG_BOARD_LATE_INIT
127 #endif 126 #endif
128 127
129 /* If Boot Script is not on NOR and is required to be copied on RAM */ 128 /* If Boot Script is not on NOR and is required to be copied on RAM */
130 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM 129 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
131 #define CONFIG_BS_HDR_ADDR_RAM 0x00010000 130 #define CONFIG_BS_HDR_ADDR_RAM 0x00010000
132 #define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000 131 #define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000
133 #define CONFIG_BS_HDR_SIZE 0x00002000 132 #define CONFIG_BS_HDR_SIZE 0x00002000
134 #define CONFIG_BS_ADDR_RAM 0x00012000 133 #define CONFIG_BS_ADDR_RAM 0x00012000
135 #define CONFIG_BS_ADDR_DEVICE 0x00802000 134 #define CONFIG_BS_ADDR_DEVICE 0x00802000
136 #define CONFIG_BS_SIZE 0x00001000 135 #define CONFIG_BS_SIZE 0x00001000
137 136
138 #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM 137 #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
139 #else 138 #else
140 139
141 /* The bootscript header address is different for B4860 because the NOR 140 /* The bootscript header address is different for B4860 because the NOR
142 * mapping is different on B4 due to reduced NOR size. 141 * mapping is different on B4 due to reduced NOR size.
143 */ 142 */
144 #if defined(CONFIG_B4860QDS) 143 #if defined(CONFIG_B4860QDS)
145 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000 144 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000
146 #elif defined(CONFIG_FSL_CORENET) 145 #elif defined(CONFIG_FSL_CORENET)
147 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000 146 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000
148 #elif defined(CONFIG_BSC9132QDS) 147 #elif defined(CONFIG_BSC9132QDS)
149 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000 148 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000
150 #elif defined(CONFIG_C29XPCIE) 149 #elif defined(CONFIG_C29XPCIE)
151 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000 150 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000
152 #else 151 #else
153 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000 152 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
154 #endif 153 #endif
155 154
156 #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */ 155 #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
157 156
158 #include <config_fsl_chain_trust.h> 157 #include <config_fsl_chain_trust.h>
159 #endif /* #ifndef CONFIG_SPL_BUILD */ 158 #endif /* #ifndef CONFIG_SPL_BUILD */
160 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ 159 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
161 #endif 160 #endif
162 161
configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
Diff comments   View file @ 3433a69
1 CONFIG_PPC=y 1 CONFIG_PPC=y
2 CONFIG_MPC85xx=y 2 CONFIG_MPC85xx=y
3 CONFIG_TARGET_T104XRDB=y 3 CONFIG_TARGET_T104XRDB=y
4 CONFIG_FIT=y 4 CONFIG_FIT=y
5 CONFIG_FIT_VERBOSE=y 5 CONFIG_FIT_VERBOSE=y
6 CONFIG_OF_BOARD_SETUP=y 6 CONFIG_OF_BOARD_SETUP=y
7 CONFIG_OF_STDOUT_VIA_ALIAS=y 7 CONFIG_OF_STDOUT_VIA_ALIAS=y
8 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND,SECURE_BOOT" 8 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND,SECURE_BOOT"
9 CONFIG_BOOTDELAY=0 9 CONFIG_BOOTDELAY=0
10 CONFIG_SPL=y 10 CONFIG_SPL=y
11 CONFIG_HUSH_PARSER=y 11 CONFIG_HUSH_PARSER=y
12 CONFIG_CMD_GREPENV=y 12 CONFIG_CMD_GREPENV=y
13 CONFIG_CMD_MMC=y 13 CONFIG_CMD_MMC=y
14 CONFIG_CMD_SF=y 14 CONFIG_CMD_SF=y
15 CONFIG_CMD_I2C=y 15 CONFIG_CMD_I2C=y
16 CONFIG_CMD_USB=y 16 CONFIG_CMD_USB=y
17 CONFIG_CMD_DHCP=y 17 CONFIG_CMD_DHCP=y
18 CONFIG_CMD_MII=y 18 CONFIG_CMD_MII=y
19 CONFIG_CMD_PING=y 19 CONFIG_CMD_PING=y
20 CONFIG_CMD_EXT2=y 20 CONFIG_CMD_EXT2=y
21 CONFIG_CMD_FAT=y 21 CONFIG_CMD_FAT=y
22 CONFIG_DM=y 22 CONFIG_DM=y
23 CONFIG_SPL_DM=y
23 CONFIG_SPI_FLASH=y 24 CONFIG_SPI_FLASH=y
24 CONFIG_SPI_FLASH_STMICRO=y 25 CONFIG_SPI_FLASH_STMICRO=y
25 CONFIG_NETDEVICES=y 26 CONFIG_NETDEVICES=y
26 CONFIG_E1000=y 27 CONFIG_E1000=y
27 CONFIG_SYS_NS16550=y 28 CONFIG_SYS_NS16550=y
28 CONFIG_FSL_ESPI=y 29 CONFIG_FSL_ESPI=y
29 CONFIG_USB=y 30 CONFIG_USB=y
30 CONFIG_USB_STORAGE=y 31 CONFIG_USB_STORAGE=y
31 CONFIG_RSA=y 32 CONFIG_RSA=y
32 CONFIG_OF_LIBFDT=y 33 CONFIG_OF_LIBFDT=y
33 34
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
Diff comments   View file @ 3433a69
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_TARGET_LS1021ATWR=y 2 CONFIG_TARGET_LS1021ATWR=y
3 CONFIG_FIT=y 3 CONFIG_FIT=y
4 CONFIG_FIT_VERBOSE=y 4 CONFIG_FIT_VERBOSE=y
5 CONFIG_OF_BOARD_SETUP=y 5 CONFIG_OF_BOARD_SETUP=y
6 CONFIG_OF_STDOUT_VIA_ALIAS=y 6 CONFIG_OF_STDOUT_VIA_ALIAS=y
7 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SECURE_BOOT" 7 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SECURE_BOOT"
8 CONFIG_BOOTDELAY=0 8 CONFIG_BOOTDELAY=0
9 CONFIG_SPL=y 9 CONFIG_SPL=y
10 CONFIG_HUSH_PARSER=y 10 CONFIG_HUSH_PARSER=y
11 CONFIG_CMD_BOOTZ=y 11 CONFIG_CMD_BOOTZ=y
12 CONFIG_CMD_GREPENV=y 12 CONFIG_CMD_GREPENV=y
13 CONFIG_CMD_MEMTEST=y 13 CONFIG_CMD_MEMTEST=y
14 CONFIG_CMD_MEMINFO=y 14 CONFIG_CMD_MEMINFO=y
15 CONFIG_CMD_MMC=y 15 CONFIG_CMD_MMC=y
16 CONFIG_CMD_I2C=y 16 CONFIG_CMD_I2C=y
17 CONFIG_CMD_USB=y 17 CONFIG_CMD_USB=y
18 CONFIG_CMD_DHCP=y 18 CONFIG_CMD_DHCP=y
19 CONFIG_CMD_MII=y 19 CONFIG_CMD_MII=y
20 CONFIG_CMD_PING=y 20 CONFIG_CMD_PING=y
21 CONFIG_CMD_EXT2=y 21 CONFIG_CMD_EXT2=y
22 CONFIG_CMD_FAT=y 22 CONFIG_CMD_FAT=y
23 CONFIG_DM=y 23 CONFIG_DM=y
24 CONFIG_SPL_DM=y
24 CONFIG_NETDEVICES=y 25 CONFIG_NETDEVICES=y
25 CONFIG_E1000=y 26 CONFIG_E1000=y
26 CONFIG_SYS_NS16550=y 27 CONFIG_SYS_NS16550=y
27 CONFIG_USB=y 28 CONFIG_USB=y
28 CONFIG_USB_XHCI_HCD=y 29 CONFIG_USB_XHCI_HCD=y
29 CONFIG_USB_XHCI_DWC3=y 30 CONFIG_USB_XHCI_DWC3=y
30 CONFIG_USB_STORAGE=y 31 CONFIG_USB_STORAGE=y
31 CONFIG_RSA=y 32 CONFIG_RSA=y
32 CONFIG_OF_LIBFDT=y 33 CONFIG_OF_LIBFDT=y
33 34