Eric Lee / smarc-uboot

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Commit 350592a8275dee800ccd4fbbfe52c5c31296c4dd

Authored by Eric Lee
1 parent b3e03ee2ec
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga

Fix u-boot wrong SD card detect pin

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

arch/arm/dts/fsl-smarcimx8mm.dts
Diff comments   View file @ 350592a
1 /* 1 /*
2 * Copyright 2018 NXP 2 * Copyright 2018 NXP
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2 6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version. 7 * of the License, or (at your option) any later version.
8 * 8 *
9 * This program is distributed in the hope that it will be useful, 9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 */ 13 */
14 14
15 /dts-v1/; 15 /dts-v1/;
16 16
17 #include "fsl-imx8mm.dtsi" 17 #include "fsl-imx8mm.dtsi"
18 18
19 / { 19 / {
20 model = "Embedian SMARC-iMX8MM Computer on Module"; 20 model = "Embedian SMARC-iMX8MM Computer on Module";
21 compatible = "embedian,smarcimx8mm", "fsl,imx8mm"; 21 compatible = "embedian,smarcimx8mm", "fsl,imx8mm";
22 22
23 reg_usdhc2_vmmc: regulator-usdhc2 { 23 reg_usdhc2_vmmc: regulator-usdhc2 {
24 compatible = "regulator-fixed"; 24 compatible = "regulator-fixed";
25 regulator-name = "VSD_3V3"; 25 regulator-name = "VSD_3V3";
26 regulator-min-microvolt = <3300000>; 26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>; 27 regulator-max-microvolt = <3300000>;
28 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 28 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
29 enable-active-high; 29 enable-active-high;
30 startup-delay-us = <100>; 30 startup-delay-us = <100>;
31 off-on-delay-us = <12000>; 31 off-on-delay-us = <12000>;
32 }; 32 };
33 33
34 backlight: backlight { 34 backlight: backlight {
35 compatible = "pwm-backlight"; 35 compatible = "pwm-backlight";
36 pwms = <&pwm1 0 1000000 0>; 36 pwms = <&pwm1 0 1000000 0>;
37 brightness-levels = < 0 1 2 3 4 5 6 7 8 9 37 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
38 10 11 12 13 14 15 16 17 18 19 38 10 11 12 13 14 15 16 17 18 19
39 20 21 22 23 24 25 26 27 28 29 39 20 21 22 23 24 25 26 27 28 29
40 30 31 32 33 34 35 36 37 38 39 40 30 31 32 33 34 35 36 37 38 39
41 40 41 42 43 44 45 46 47 48 49 41 40 41 42 43 44 45 46 47 48 49
42 50 51 52 53 54 55 56 57 58 59 42 50 51 52 53 54 55 56 57 58 59
43 60 61 62 63 64 65 66 67 68 69 43 60 61 62 63 64 65 66 67 68 69
44 70 71 72 73 74 75 76 77 78 79 44 70 71 72 73 74 75 76 77 78 79
45 80 81 82 83 84 85 86 87 88 89 45 80 81 82 83 84 85 86 87 88 89
46 90 91 92 93 94 95 96 97 98 99 46 90 91 92 93 94 95 96 97 98 99
47 100>; 47 100>;
48 default-brightness-level = <80>; 48 default-brightness-level = <80>;
49 status = "disabled"; 49 status = "disabled";
50 }; 50 };
51 }; 51 };
52 52
53 &iomuxc { 53 &iomuxc {
54 pinctrl-names = "default"; 54 pinctrl-names = "default";
55 55
56 smarc-imx8mm { 56 smarc-imx8mm {
57 pinctrl_fec1: fec1grp { 57 pinctrl_fec1: fec1grp {
58 fsl,pins = < 58 fsl,pins = <
59 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 59 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
60 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 60 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
61 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 61 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
62 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 62 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
63 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 63 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
64 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 64 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
65 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 65 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
66 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 66 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
67 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 67 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
68 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 68 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
69 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 69 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
70 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 70 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
71 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 71 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
72 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 72 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
73 MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x41 73 MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x41
74 >; 74 >;
75 }; 75 };
76 76
77 pinctrl_flexspi0: flexspi0grp { 77 pinctrl_flexspi0: flexspi0grp {
78 fsl,pins = < 78 fsl,pins = <
79 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 79 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
80 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 80 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
81 81
82 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 82 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
83 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 83 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
84 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 84 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
85 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 85 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
86 >; 86 >;
87 }; 87 };
88 88
89 pinctrl_pwm1: pwm1grp { 89 pinctrl_pwm1: pwm1grp {
90 fsl,pins = < 90 fsl,pins = <
91 MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x06 91 MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x06
92 >; 92 >;
93 }; 93 };
94 94
95 pinctrl_i2c1: i2c1grp { 95 pinctrl_i2c1: i2c1grp {
96 fsl,pins = < 96 fsl,pins = <
97 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 97 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
98 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 98 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
99 >; 99 >;
100 }; 100 };
101 101
102 pinctrl_i2c2: i2c2grp { 102 pinctrl_i2c2: i2c2grp {
103 fsl,pins = < 103 fsl,pins = <
104 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 104 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
105 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 105 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
106 >; 106 >;
107 }; 107 };
108 108
109 pinctrl_i2c3: i2c3grp { 109 pinctrl_i2c3: i2c3grp {
110 fsl,pins = < 110 fsl,pins = <
111 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 111 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
112 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 112 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
113 >; 113 >;
114 }; 114 };
115 115
116 pinctrl_i2c4: i2c4grp { 116 pinctrl_i2c4: i2c4grp {
117 fsl,pins = < 117 fsl,pins = <
118 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 118 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
119 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 119 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
120 >; 120 >;
121 }; 121 };
122 122
123 pinctrl_i2c1_gpio: i2c1grp-gpio { 123 pinctrl_i2c1_gpio: i2c1grp-gpio {
124 fsl,pins = < 124 fsl,pins = <
125 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 125 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3
126 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 126 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3
127 >; 127 >;
128 }; 128 };
129 129
130 pinctrl_i2c2_gpio: i2c2grp-gpio { 130 pinctrl_i2c2_gpio: i2c2grp-gpio {
131 fsl,pins = < 131 fsl,pins = <
132 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 132 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
133 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 133 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
134 >; 134 >;
135 }; 135 };
136 136
137 pinctrl_i2c3_gpio: i2c3grp-gpio { 137 pinctrl_i2c3_gpio: i2c3grp-gpio {
138 fsl,pins = < 138 fsl,pins = <
139 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 139 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
140 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 140 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
141 >; 141 >;
142 }; 142 };
143 143
144 pinctrl_i2c4_gpio: i2c4grp-gpio { 144 pinctrl_i2c4_gpio: i2c4grp-gpio {
145 fsl,pins = < 145 fsl,pins = <
146 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1c3 146 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1c3
147 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1c3 147 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1c3
148 >; 148 >;
149 }; 149 };
150 150
151 pinctrl_pmic: pmicirq { 151 pinctrl_pmic: pmicirq {
152 fsl,pins = < 152 fsl,pins = <
153 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 153 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
154 >; 154 >;
155 }; 155 };
156 156
157 pinctrl_uart1: uart1grp { 157 pinctrl_uart1: uart1grp {
158 fsl,pins = < 158 fsl,pins = <
159 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x49 159 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x49
160 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x49 160 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x49
161 MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x49 161 MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x49
162 MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x49 162 MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x49
163 >; 163 >;
164 }; 164 };
165 165
166 pinctrl_uart2: uart2grp { 166 pinctrl_uart2: uart2grp {
167 fsl,pins = < 167 fsl,pins = <
168 MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x49 168 MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x49
169 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x49 169 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x49
170 >; 170 >;
171 }; 171 };
172 172
173 pinctrl_uart3: uart3grp { 173 pinctrl_uart3: uart3grp {
174 fsl,pins = < 174 fsl,pins = <
175 MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x49 175 MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x49
176 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x49 176 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x49
177 MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 177 MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
178 MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 178 MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49
179 >; 179 >;
180 }; 180 };
181 181
182 pinctrl_uart4: uart4grp { 182 pinctrl_uart4: uart4grp {
183 fsl,pins = < 183 fsl,pins = <
184 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49 184 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49
185 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49 185 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49
186 >; 186 >;
187 }; 187 };
188 188
189 pinctrl_usdhc1: usdhc1grp { 189 pinctrl_usdhc1: usdhc1grp {
190 fsl,pins = < 190 fsl,pins = <
191 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000190 191 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000190
192 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 192 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
193 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 193 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
194 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 194 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
195 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 195 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
196 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 196 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
197 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 197 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
198 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 198 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
199 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 199 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
200 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 200 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
201 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 201 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
202 >; 202 >;
203 }; 203 };
204 204
205 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 205 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
206 fsl,pins = < 206 fsl,pins = <
207 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000194 207 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000194
208 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 208 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
209 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 209 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
210 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 210 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
211 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 211 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
212 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 212 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
213 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 213 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
214 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 214 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
215 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 215 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
216 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 216 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
217 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 217 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
218 >; 218 >;
219 }; 219 };
220 220
221 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 221 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
222 fsl,pins = < 222 fsl,pins = <
223 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000196 223 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000196
224 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 224 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
225 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 225 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
226 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 226 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
227 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 227 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
228 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 228 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
229 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 229 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
230 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 230 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
231 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 231 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
232 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 232 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
233 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 233 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
234 >; 234 >;
235 }; 235 };
236 236
237 pinctrl_usdhc2_gpio: usdhc2grpgpio { 237 pinctrl_usdhc2_gpio: usdhc2grpgpio {
238 fsl,pins = < 238 fsl,pins = <
239 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 239 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
240 >; 240 >;
241 }; 241 };
242 242
243 pinctrl_usdhc2: usdhc2grp { 243 pinctrl_usdhc2: usdhc2grp {
244 fsl,pins = < 244 fsl,pins = <
245 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 245 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
246 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 246 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
247 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 247 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
248 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 248 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
249 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 249 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
250 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 250 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
251 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 251 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
252 >; 252 >;
253 }; 253 };
254 254
255 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 255 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
256 fsl,pins = < 256 fsl,pins = <
257 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 257 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
258 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 258 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
259 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 259 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
260 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 260 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
261 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 261 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
262 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 262 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
263 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 263 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
264 >; 264 >;
265 }; 265 };
266 266
267 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 267 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
268 fsl,pins = < 268 fsl,pins = <
269 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 269 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
270 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 270 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
271 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 271 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
272 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 272 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
273 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 273 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
274 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 274 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
275 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 275 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
276 >; 276 >;
277 }; 277 };
278 278
279 pinctrl_wdog: wdoggrp { 279 pinctrl_wdog: wdoggrp {
280 fsl,pins = < 280 fsl,pins = <
281 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 281 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
282 >; 282 >;
283 }; 283 };
284 }; 284 };
285 }; 285 };
286 286
287 &i2c1 { 287 &i2c1 {
288 clock-frequency = <400000>; 288 clock-frequency = <400000>;
289 pinctrl-names = "default", "gpio"; 289 pinctrl-names = "default", "gpio";
290 pinctrl-0 = <&pinctrl_i2c1>; 290 pinctrl-0 = <&pinctrl_i2c1>;
291 pinctrl-1 = <&pinctrl_i2c1_gpio>; 291 pinctrl-1 = <&pinctrl_i2c1_gpio>;
292 scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; 292 scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
293 sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; 293 sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
294 status = "okay"; 294 status = "okay";
295 295
296 pmic: bd71837@4b { 296 pmic: bd71837@4b {
297 reg = <0x4b>; 297 reg = <0x4b>;
298 compatible = "rohm,bd71837"; 298 compatible = "rohm,bd71837";
299 /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ 299 /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */
300 pinctrl-0 = <&pinctrl_pmic>; 300 pinctrl-0 = <&pinctrl_pmic>;
301 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; 301 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
302 302
303 gpo { 303 gpo {
304 rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ 304 rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
305 }; 305 };
306 306
307 regulators { 307 regulators {
308 #address-cells = <1>; 308 #address-cells = <1>;
309 #size-cells = <0>; 309 #size-cells = <0>;
310 310
311 bd71837,pmic-buck2-uses-i2c-dvs; 311 bd71837,pmic-buck2-uses-i2c-dvs;
312 bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ 312 bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
313 313
314 buck1_reg: regulator@0 { 314 buck1_reg: regulator@0 {
315 reg = <0>; 315 reg = <0>;
316 regulator-compatible = "buck1"; 316 regulator-compatible = "buck1";
317 regulator-min-microvolt = <700000>; 317 regulator-min-microvolt = <700000>;
318 regulator-max-microvolt = <1300000>; 318 regulator-max-microvolt = <1300000>;
319 regulator-boot-on; 319 regulator-boot-on;
320 regulator-always-on; 320 regulator-always-on;
321 regulator-ramp-delay = <1250>; 321 regulator-ramp-delay = <1250>;
322 }; 322 };
323 323
324 buck2_reg: regulator@1 { 324 buck2_reg: regulator@1 {
325 reg = <1>; 325 reg = <1>;
326 regulator-compatible = "buck2"; 326 regulator-compatible = "buck2";
327 regulator-min-microvolt = <700000>; 327 regulator-min-microvolt = <700000>;
328 regulator-max-microvolt = <1300000>; 328 regulator-max-microvolt = <1300000>;
329 regulator-boot-on; 329 regulator-boot-on;
330 regulator-always-on; 330 regulator-always-on;
331 regulator-ramp-delay = <1250>; 331 regulator-ramp-delay = <1250>;
332 }; 332 };
333 333
334 buck3_reg: regulator@2 { 334 buck3_reg: regulator@2 {
335 reg = <2>; 335 reg = <2>;
336 regulator-compatible = "buck3"; 336 regulator-compatible = "buck3";
337 regulator-min-microvolt = <700000>; 337 regulator-min-microvolt = <700000>;
338 regulator-max-microvolt = <1300000>; 338 regulator-max-microvolt = <1300000>;
339 }; 339 };
340 340
341 buck4_reg: regulator@3 { 341 buck4_reg: regulator@3 {
342 reg = <3>; 342 reg = <3>;
343 regulator-compatible = "buck4"; 343 regulator-compatible = "buck4";
344 regulator-min-microvolt = <700000>; 344 regulator-min-microvolt = <700000>;
345 regulator-max-microvolt = <1300000>; 345 regulator-max-microvolt = <1300000>;
346 }; 346 };
347 347
348 buck5_reg: regulator@4 { 348 buck5_reg: regulator@4 {
349 reg = <4>; 349 reg = <4>;
350 regulator-compatible = "buck5"; 350 regulator-compatible = "buck5";
351 regulator-min-microvolt = <700000>; 351 regulator-min-microvolt = <700000>;
352 regulator-max-microvolt = <1350000>; 352 regulator-max-microvolt = <1350000>;
353 regulator-boot-on; 353 regulator-boot-on;
354 regulator-always-on; 354 regulator-always-on;
355 }; 355 };
356 356
357 buck6_reg: regulator@5 { 357 buck6_reg: regulator@5 {
358 reg = <5>; 358 reg = <5>;
359 regulator-compatible = "buck6"; 359 regulator-compatible = "buck6";
360 regulator-min-microvolt = <3000000>; 360 regulator-min-microvolt = <3000000>;
361 regulator-max-microvolt = <3300000>; 361 regulator-max-microvolt = <3300000>;
362 regulator-boot-on; 362 regulator-boot-on;
363 regulator-always-on; 363 regulator-always-on;
364 }; 364 };
365 365
366 buck7_reg: regulator@6 { 366 buck7_reg: regulator@6 {
367 reg = <6>; 367 reg = <6>;
368 regulator-compatible = "buck7"; 368 regulator-compatible = "buck7";
369 regulator-min-microvolt = <1605000>; 369 regulator-min-microvolt = <1605000>;
370 regulator-max-microvolt = <1995000>; 370 regulator-max-microvolt = <1995000>;
371 regulator-boot-on; 371 regulator-boot-on;
372 regulator-always-on; 372 regulator-always-on;
373 }; 373 };
374 374
375 buck8_reg: regulator@7 { 375 buck8_reg: regulator@7 {
376 reg = <7>; 376 reg = <7>;
377 regulator-compatible = "buck8"; 377 regulator-compatible = "buck8";
378 regulator-min-microvolt = <800000>; 378 regulator-min-microvolt = <800000>;
379 regulator-max-microvolt = <1400000>; 379 regulator-max-microvolt = <1400000>;
380 regulator-boot-on; 380 regulator-boot-on;
381 regulator-always-on; 381 regulator-always-on;
382 }; 382 };
383 383
384 ldo1_reg: regulator@8 { 384 ldo1_reg: regulator@8 {
385 reg = <8>; 385 reg = <8>;
386 regulator-compatible = "ldo1"; 386 regulator-compatible = "ldo1";
387 regulator-min-microvolt = <1600000>; 387 regulator-min-microvolt = <1600000>;
388 regulator-max-microvolt = <1900000>; 388 regulator-max-microvolt = <1900000>;
389 regulator-boot-on; 389 regulator-boot-on;
390 regulator-always-on; 390 regulator-always-on;
391 }; 391 };
392 392
393 ldo2_reg: regulator@9 { 393 ldo2_reg: regulator@9 {
394 reg = <9>; 394 reg = <9>;
395 regulator-compatible = "ldo2"; 395 regulator-compatible = "ldo2";
396 regulator-min-microvolt = <800000>; 396 regulator-min-microvolt = <800000>;
397 regulator-max-microvolt = <900000>; 397 regulator-max-microvolt = <900000>;
398 regulator-boot-on; 398 regulator-boot-on;
399 regulator-always-on; 399 regulator-always-on;
400 }; 400 };
401 401
402 ldo3_reg: regulator@10 { 402 ldo3_reg: regulator@10 {
403 reg = <10>; 403 reg = <10>;
404 regulator-compatible = "ldo3"; 404 regulator-compatible = "ldo3";
405 regulator-min-microvolt = <1800000>; 405 regulator-min-microvolt = <1800000>;
406 regulator-max-microvolt = <3300000>; 406 regulator-max-microvolt = <3300000>;
407 regulator-boot-on; 407 regulator-boot-on;
408 regulator-always-on; 408 regulator-always-on;
409 }; 409 };
410 410
411 ldo4_reg: regulator@11 { 411 ldo4_reg: regulator@11 {
412 reg = <11>; 412 reg = <11>;
413 regulator-compatible = "ldo4"; 413 regulator-compatible = "ldo4";
414 regulator-min-microvolt = <900000>; 414 regulator-min-microvolt = <900000>;
415 regulator-max-microvolt = <1800000>; 415 regulator-max-microvolt = <1800000>;
416 regulator-boot-on; 416 regulator-boot-on;
417 regulator-always-on; 417 regulator-always-on;
418 }; 418 };
419 419
420 ldo5_reg: regulator@12 { 420 ldo5_reg: regulator@12 {
421 reg = <12>; 421 reg = <12>;
422 regulator-compatible = "ldo5"; 422 regulator-compatible = "ldo5";
423 regulator-min-microvolt = <1800000>; 423 regulator-min-microvolt = <1800000>;
424 regulator-max-microvolt = <3300000>; 424 regulator-max-microvolt = <3300000>;
425 }; 425 };
426 426
427 ldo6_reg: regulator@13 { 427 ldo6_reg: regulator@13 {
428 reg = <13>; 428 reg = <13>;
429 regulator-compatible = "ldo6"; 429 regulator-compatible = "ldo6";
430 regulator-min-microvolt = <900000>; 430 regulator-min-microvolt = <900000>;
431 regulator-max-microvolt = <1800000>; 431 regulator-max-microvolt = <1800000>;
432 regulator-boot-on; 432 regulator-boot-on;
433 regulator-always-on; 433 regulator-always-on;
434 }; 434 };
435 435
436 ldo7_reg: regulator@14 { 436 ldo7_reg: regulator@14 {
437 reg = <14>; 437 reg = <14>;
438 regulator-compatible = "ldo7"; 438 regulator-compatible = "ldo7";
439 regulator-min-microvolt = <1800000>; 439 regulator-min-microvolt = <1800000>;
440 regulator-max-microvolt = <3300000>; 440 regulator-max-microvolt = <3300000>;
441 }; 441 };
442 }; 442 };
443 }; 443 };
444 }; 444 };
445 445
446 &i2c2 { 446 &i2c2 {
447 clock-frequency = <400000>; 447 clock-frequency = <400000>;
448 pinctrl-names = "default", "gpio"; 448 pinctrl-names = "default", "gpio";
449 pinctrl-0 = <&pinctrl_i2c2>; 449 pinctrl-0 = <&pinctrl_i2c2>;
450 pinctrl-1 = <&pinctrl_i2c2_gpio>; 450 pinctrl-1 = <&pinctrl_i2c2_gpio>;
451 scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; 451 scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
452 sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; 452 sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
453 status = "okay"; 453 status = "okay";
454 454
455 typec_ptn5110_1: ptn5110@50 { 455 typec_ptn5110_1: ptn5110@50 {
456 compatible = "usb,tcpci"; 456 compatible = "usb,tcpci";
457 reg = <0x50>; 457 reg = <0x50>;
458 src-pdos = <0x380190c8>; 458 src-pdos = <0x380190c8>;
459 snk-pdos = <0x380190c8 0x3802d0c8>; 459 snk-pdos = <0x380190c8 0x3802d0c8>;
460 max-snk-mv = <9000>; 460 max-snk-mv = <9000>;
461 max-snk-ma = <2000>; 461 max-snk-ma = <2000>;
462 op-snk-mw = <9000>; 462 op-snk-mw = <9000>;
463 max-snk-mw = <18000>; 463 max-snk-mw = <18000>;
464 port-type = "drp"; 464 port-type = "drp";
465 default-role = "sink"; 465 default-role = "sink";
466 }; 466 };
467 467
468 typec_ptn5110_2: ptn5110@52 { 468 typec_ptn5110_2: ptn5110@52 {
469 compatible = "usb,tcpci"; 469 compatible = "usb,tcpci";
470 reg = <0x52>; 470 reg = <0x52>;
471 src-pdos = <0x380190c8>; 471 src-pdos = <0x380190c8>;
472 snk-pdos = <0x380190c8 0x3802d0c8>; 472 snk-pdos = <0x380190c8 0x3802d0c8>;
473 max-snk-mv = <9000>; 473 max-snk-mv = <9000>;
474 max-snk-ma = <2000>; 474 max-snk-ma = <2000>;
475 op-snk-mw = <9000>; 475 op-snk-mw = <9000>;
476 max-snk-mw = <18000>; 476 max-snk-mw = <18000>;
477 port-type = "drp"; 477 port-type = "drp";
478 default-role = "sink"; 478 default-role = "sink";
479 }; 479 };
480 }; 480 };
481 481
482 &i2c3 { 482 &i2c3 {
483 clock-frequency = <100000>; 483 clock-frequency = <100000>;
484 pinctrl-names = "default", "gpio"; 484 pinctrl-names = "default", "gpio";
485 pinctrl-0 = <&pinctrl_i2c3>; 485 pinctrl-0 = <&pinctrl_i2c3>;
486 pinctrl-1 = <&pinctrl_i2c3_gpio>; 486 pinctrl-1 = <&pinctrl_i2c3_gpio>;
487 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; 487 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
488 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; 488 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
489 status = "okay"; 489 status = "okay";
490 }; 490 };
491 491
492 &i2c4 { 492 &i2c4 {
493 clock-frequency = <100000>; 493 clock-frequency = <100000>;
494 pinctrl-names = "default", "gpio"; 494 pinctrl-names = "default", "gpio";
495 pinctrl-0 = <&pinctrl_i2c4>; 495 pinctrl-0 = <&pinctrl_i2c4>;
496 pinctrl-1 = <&pinctrl_i2c4_gpio>; 496 pinctrl-1 = <&pinctrl_i2c4_gpio>;
497 scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; 497 scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
498 sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; 498 sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
499 status = "okay"; 499 status = "okay";
500 }; 500 };
501 501
502 &fec1 { 502 &fec1 {
503 pinctrl-names = "default"; 503 pinctrl-names = "default";
504 pinctrl-0 = <&pinctrl_fec1>; 504 pinctrl-0 = <&pinctrl_fec1>;
505 phy-mode = "rgmii-id"; 505 phy-mode = "rgmii-id";
506 phy-handle = <&ethphy0>; 506 phy-handle = <&ethphy0>;
507 fsl,magic-packet; 507 fsl,magic-packet;
508 status = "okay"; 508 status = "okay";
509 509
510 mdio { 510 mdio {
511 #address-cells = <1>; 511 #address-cells = <1>;
512 #size-cells = <0>; 512 #size-cells = <0>;
513 513
514 ethphy0: ethernet-phy@0 { 514 ethphy0: ethernet-phy@0 {
515 compatible = "ethernet-phy-ieee802.3-c22"; 515 compatible = "ethernet-phy-ieee802.3-c22";
516 reg = <6>; 516 reg = <6>;
517 at803x,led-act-blind-workaround; 517 at803x,led-act-blind-workaround;
518 at803x,eee-okay; 518 at803x,eee-okay;
519 at803x,vddio-1p8v; 519 at803x,vddio-1p8v;
520 }; 520 };
521 }; 521 };
522 }; 522 };
523 523
524 /* SER0 */ 524 /* SER0 */
525 &uart1 { 525 &uart1 {
526 pinctrl-names = "default"; 526 pinctrl-names = "default";
527 pinctrl-0 = <&pinctrl_uart1>; 527 pinctrl-0 = <&pinctrl_uart1>;
528 assigned-clocks = <&clk IMX8MM_CLK_UART1_SRC>; 528 assigned-clocks = <&clk IMX8MM_CLK_UART1_SRC>;
529 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 529 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
530 uart-has-rtscts; 530 uart-has-rtscts;
531 status = "okay"; 531 status = "okay";
532 }; 532 };
533 533
534 /* SER1 */ 534 /* SER1 */
535 &uart4 { 535 &uart4 {
536 pinctrl-names = "default"; 536 pinctrl-names = "default";
537 pinctrl-0 = <&pinctrl_uart4>; 537 pinctrl-0 = <&pinctrl_uart4>;
538 status = "okay"; 538 status = "okay";
539 }; 539 };
540 540
541 /* SER2 */ 541 /* SER2 */
542 &uart3 { 542 &uart3 {
543 pinctrl-names = "default"; 543 pinctrl-names = "default";
544 pinctrl-0 = <&pinctrl_uart3>; 544 pinctrl-0 = <&pinctrl_uart3>;
545 assigned-clocks = <&clk IMX8MM_CLK_UART3_SRC>; 545 assigned-clocks = <&clk IMX8MM_CLK_UART3_SRC>;
546 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 546 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
547 uart-has-rtscts; 547 uart-has-rtscts;
548 status = "okay"; 548 status = "okay";
549 }; 549 };
550 550
551 /* SER3 */ 551 /* SER3 */
552 &uart2 { /* console */ 552 &uart2 { /* console */
553 pinctrl-names = "default"; 553 pinctrl-names = "default";
554 pinctrl-0 = <&pinctrl_uart2>; 554 pinctrl-0 = <&pinctrl_uart2>;
555 status = "okay"; 555 status = "okay";
556 }; 556 };
557 557
558 &pwm1 { 558 &pwm1 {
559 status = "okay"; 559 status = "okay";
560 pinctrl-names = "default"; 560 pinctrl-names = "default";
561 pinctrl-0 = <&pinctrl_pwm1>; 561 pinctrl-0 = <&pinctrl_pwm1>;
562 }; 562 };
563 563
564 &usdhc1 { 564 &usdhc1 {
565 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 565 pinctrl-names = "default", "state_100mhz", "state_200mhz";
566 pinctrl-0 = <&pinctrl_usdhc1>; 566 pinctrl-0 = <&pinctrl_usdhc1>;
567 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 567 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
568 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 568 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
569 bus-width = <8>; 569 bus-width = <8>;
570 non-removable; 570 non-removable;
571 status = "okay"; 571 status = "okay";
572 }; 572 };
573 573
574 &usdhc2 { 574 &usdhc2 {
575 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 575 pinctrl-names = "default", "state_100mhz", "state_200mhz";
576 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 576 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
577 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 577 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
578 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 578 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
579 bus-width = <4>; 579 bus-width = <4>;
580 cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; 580 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
581 vmmc-supply = <&reg_usdhc2_vmmc>; 581 vmmc-supply = <&reg_usdhc2_vmmc>;
582 status = "okay"; 582 status = "okay";
583 }; 583 };
584 584
585 &wdog1 { 585 &wdog1 {
586 pinctrl-names = "default"; 586 pinctrl-names = "default";
587 pinctrl-0 = <&pinctrl_wdog>; 587 pinctrl-0 = <&pinctrl_wdog>;
588 fsl,ext-reset-output; 588 fsl,ext-reset-output;
589 status = "okay"; 589 status = "okay";
590 }; 590 };
591 591
592 &A53_0 { 592 &A53_0 {
593 arm-supply = <&buck2_reg>; 593 arm-supply = <&buck2_reg>;
594 }; 594 };
595 595
596 &usbotg1 { 596 &usbotg1 {
597 status = "okay"; 597 status = "okay";
598 dr_mode = "peripheral"; 598 dr_mode = "peripheral";
599 }; 599 };
600 600
601 &usbotg2 { 601 &usbotg2 {
602 status = "okay"; 602 status = "okay";
603 dr_mode = "host"; 603 dr_mode = "host";
604 }; 604 };
605 605