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Commit 35c471e509465366bbf0b92a589b5cdc69081a7d

Authored by Shengzhou Liu
Committed by York Sun
1 parent 22a240c32c
Exists in master and in 49 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

powerpc/t208x: some update to support t2081 

- fix serdes definition for t2081.
- fix clock speed for t2081.
- update ids, as CONFIG_FSL_SATA_V2 is needed only for t2080,
  T2081 has no SATA.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Showing 3 changed files with 5 additions and 3 deletions Inline Diff

arch/powerpc/cpu/mpc85xx/speed.c
Diff comments   View file @ 35c471e
1 /* 1 /*
2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
3 * 3 *
4 * (C) Copyright 2003 Motorola Inc. 4 * (C) Copyright 2003 Motorola Inc.
5 * Xianghua Xiao, (X.Xiao@motorola.com) 5 * Xianghua Xiao, (X.Xiao@motorola.com)
6 * 6 *
7 * (C) Copyright 2000 7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * 9 *
10 * SPDX-License-Identifier: GPL-2.0+ 10 * SPDX-License-Identifier: GPL-2.0+
11 */ 11 */
12 12
13 #include <common.h> 13 #include <common.h>
14 #include <ppc_asm.tmpl> 14 #include <ppc_asm.tmpl>
15 #include <linux/compiler.h> 15 #include <linux/compiler.h>
16 #include <asm/processor.h> 16 #include <asm/processor.h>
17 #include <asm/io.h> 17 #include <asm/io.h>
18 18
19 DECLARE_GLOBAL_DATA_PTR; 19 DECLARE_GLOBAL_DATA_PTR;
20 20
21 21
22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS 22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6 23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6
24 #endif 24 #endif
25 /* --------------------------------------------------------------- */ 25 /* --------------------------------------------------------------- */
26 26
27 void get_sys_info(sys_info_t *sys_info) 27 void get_sys_info(sys_info_t *sys_info)
28 { 28 {
29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
30 #ifdef CONFIG_FSL_IFC 30 #ifdef CONFIG_FSL_IFC
31 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; 31 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
32 u32 ccr; 32 u32 ccr;
33 #endif 33 #endif
34 #ifdef CONFIG_FSL_CORENET 34 #ifdef CONFIG_FSL_CORENET
35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); 35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
36 unsigned int cpu; 36 unsigned int cpu;
37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
38 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; 38 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
39 #endif 39 #endif
40 40
41 const u8 core_cplx_PLL[16] = { 41 const u8 core_cplx_PLL[16] = {
42 [ 0] = 0, /* CC1 PPL / 1 */ 42 [ 0] = 0, /* CC1 PPL / 1 */
43 [ 1] = 0, /* CC1 PPL / 2 */ 43 [ 1] = 0, /* CC1 PPL / 2 */
44 [ 2] = 0, /* CC1 PPL / 4 */ 44 [ 2] = 0, /* CC1 PPL / 4 */
45 [ 4] = 1, /* CC2 PPL / 1 */ 45 [ 4] = 1, /* CC2 PPL / 1 */
46 [ 5] = 1, /* CC2 PPL / 2 */ 46 [ 5] = 1, /* CC2 PPL / 2 */
47 [ 6] = 1, /* CC2 PPL / 4 */ 47 [ 6] = 1, /* CC2 PPL / 4 */
48 [ 8] = 2, /* CC3 PPL / 1 */ 48 [ 8] = 2, /* CC3 PPL / 1 */
49 [ 9] = 2, /* CC3 PPL / 2 */ 49 [ 9] = 2, /* CC3 PPL / 2 */
50 [10] = 2, /* CC3 PPL / 4 */ 50 [10] = 2, /* CC3 PPL / 4 */
51 [12] = 3, /* CC4 PPL / 1 */ 51 [12] = 3, /* CC4 PPL / 1 */
52 [13] = 3, /* CC4 PPL / 2 */ 52 [13] = 3, /* CC4 PPL / 2 */
53 [14] = 3, /* CC4 PPL / 4 */ 53 [14] = 3, /* CC4 PPL / 4 */
54 }; 54 };
55 55
56 const u8 core_cplx_pll_div[16] = { 56 const u8 core_cplx_pll_div[16] = {
57 [ 0] = 1, /* CC1 PPL / 1 */ 57 [ 0] = 1, /* CC1 PPL / 1 */
58 [ 1] = 2, /* CC1 PPL / 2 */ 58 [ 1] = 2, /* CC1 PPL / 2 */
59 [ 2] = 4, /* CC1 PPL / 4 */ 59 [ 2] = 4, /* CC1 PPL / 4 */
60 [ 4] = 1, /* CC2 PPL / 1 */ 60 [ 4] = 1, /* CC2 PPL / 1 */
61 [ 5] = 2, /* CC2 PPL / 2 */ 61 [ 5] = 2, /* CC2 PPL / 2 */
62 [ 6] = 4, /* CC2 PPL / 4 */ 62 [ 6] = 4, /* CC2 PPL / 4 */
63 [ 8] = 1, /* CC3 PPL / 1 */ 63 [ 8] = 1, /* CC3 PPL / 1 */
64 [ 9] = 2, /* CC3 PPL / 2 */ 64 [ 9] = 2, /* CC3 PPL / 2 */
65 [10] = 4, /* CC3 PPL / 4 */ 65 [10] = 4, /* CC3 PPL / 4 */
66 [12] = 1, /* CC4 PPL / 1 */ 66 [12] = 1, /* CC4 PPL / 1 */
67 [13] = 2, /* CC4 PPL / 2 */ 67 [13] = 2, /* CC4 PPL / 2 */
68 [14] = 4, /* CC4 PPL / 4 */ 68 [14] = 4, /* CC4 PPL / 4 */
69 }; 69 };
70 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; 70 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
71 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 71 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
72 uint rcw_tmp; 72 uint rcw_tmp;
73 #endif 73 #endif
74 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; 74 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
75 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; 75 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
76 uint mem_pll_rat; 76 uint mem_pll_rat;
77 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 77 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
78 uint single_src; 78 uint single_src;
79 #endif 79 #endif
80 80
81 sys_info->freq_systembus = sysclk; 81 sys_info->freq_systembus = sysclk;
82 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 82 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
83 /* 83 /*
84 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS 84 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
85 * are driven by separate DDR Refclock or single source 85 * are driven by separate DDR Refclock or single source
86 * differential clock. 86 * differential clock.
87 */ 87 */
88 single_src = (in_be32(&gur->rcwsr[5]) >> 88 single_src = (in_be32(&gur->rcwsr[5]) >>
89 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) & 89 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
90 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; 90 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
91 /* 91 /*
92 * For single source clocking, both ddrclock and syclock 92 * For single source clocking, both ddrclock and syclock
93 * are driven by differential sysclock. 93 * are driven by differential sysclock.
94 */ 94 */
95 if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) { 95 if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
96 printf("Single Source Clock Configuration\n"); 96 printf("Single Source Clock Configuration\n");
97 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; 97 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
98 } else 98 } else
99 #endif 99 #endif
100 #ifdef CONFIG_DDR_CLK_FREQ 100 #ifdef CONFIG_DDR_CLK_FREQ
101 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; 101 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
102 #else 102 #else
103 sys_info->freq_ddrbus = sysclk; 103 sys_info->freq_ddrbus = sysclk;
104 #endif 104 #endif
105 105
106 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 106 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
107 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 107 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
108 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) 108 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
109 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 109 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
110 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of 110 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
111 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 111 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
112 * it uses 6. 112 * it uses 6.
113 */ 113 */
114 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 114 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
115 if (SVR_MAJ(get_svr()) >= 2) 115 if (SVR_MAJ(get_svr()) >= 2)
116 mem_pll_rat *= 2; 116 mem_pll_rat *= 2;
117 #endif 117 #endif
118 if (mem_pll_rat > 2) 118 if (mem_pll_rat > 2)
119 sys_info->freq_ddrbus *= mem_pll_rat; 119 sys_info->freq_ddrbus *= mem_pll_rat;
120 else 120 else
121 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat; 121 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
122 122
123 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { 123 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
124 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; 124 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
125 if (ratio[i] > 4) 125 if (ratio[i] > 4)
126 freq_c_pll[i] = sysclk * ratio[i]; 126 freq_c_pll[i] = sysclk * ratio[i];
127 else 127 else
128 freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; 128 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
129 } 129 }
130 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 130 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
131 /* 131 /*
132 * As per CHASSIS2 architeture total 12 clusters are posible and 132 * As per CHASSIS2 architeture total 12 clusters are posible and
133 * Each cluster has up to 4 cores, sharing the same PLL selection. 133 * Each cluster has up to 4 cores, sharing the same PLL selection.
134 * The cluster clock assignment is SoC defined. 134 * The cluster clock assignment is SoC defined.
135 * 135 *
136 * Total 4 clock groups are possible with 3 PLLs each. 136 * Total 4 clock groups are possible with 3 PLLs each.
137 * as per array indices, clock group A has 0, 1, 2 numbered PLLs & 137 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
138 * clock group B has 3, 4, 6 and so on. 138 * clock group B has 3, 4, 6 and so on.
139 * 139 *
140 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster 140 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
141 * depends upon the SoC architeture. Same applies to other 141 * depends upon the SoC architeture. Same applies to other
142 * clock groups and clusters. 142 * clock groups and clusters.
143 * 143 *
144 */ 144 */
145 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 145 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
146 int cluster = fsl_qoriq_core_to_cluster(cpu); 146 int cluster = fsl_qoriq_core_to_cluster(cpu);
147 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) 147 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
148 & 0xf; 148 & 0xf;
149 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 149 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
150 cplx_pll += cc_group[cluster] - 1; 150 cplx_pll += cc_group[cluster] - 1;
151 sys_info->freq_processor[cpu] = 151 sys_info->freq_processor[cpu] =
152 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 152 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
153 } 153 }
154 #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) 154 #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) || \
155 defined(CONFIG_PPC_T2081)
155 #define FM1_CLK_SEL 0xe0000000 156 #define FM1_CLK_SEL 0xe0000000
156 #define FM1_CLK_SHIFT 29 157 #define FM1_CLK_SHIFT 29
157 #else 158 #else
158 #define PME_CLK_SEL 0xe0000000 159 #define PME_CLK_SEL 0xe0000000
159 #define PME_CLK_SHIFT 29 160 #define PME_CLK_SHIFT 29
160 #define FM1_CLK_SEL 0x1c000000 161 #define FM1_CLK_SEL 0x1c000000
161 #define FM1_CLK_SHIFT 26 162 #define FM1_CLK_SHIFT 26
162 #endif 163 #endif
163 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 164 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
164 rcw_tmp = in_be32(&gur->rcwsr[7]); 165 rcw_tmp = in_be32(&gur->rcwsr[7]);
165 #endif 166 #endif
166 167
167 #ifdef CONFIG_SYS_DPAA_PME 168 #ifdef CONFIG_SYS_DPAA_PME
168 #ifndef CONFIG_PME_PLAT_CLK_DIV 169 #ifndef CONFIG_PME_PLAT_CLK_DIV
169 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { 170 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
170 case 1: 171 case 1:
171 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; 172 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
172 break; 173 break;
173 case 2: 174 case 2:
174 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; 175 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
175 break; 176 break;
176 case 3: 177 case 3:
177 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; 178 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
178 break; 179 break;
179 case 4: 180 case 4:
180 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; 181 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
181 break; 182 break;
182 case 6: 183 case 6:
183 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; 184 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
184 break; 185 break;
185 case 7: 186 case 7:
186 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; 187 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
187 break; 188 break;
188 default: 189 default:
189 printf("Error: Unknown PME clock select!\n"); 190 printf("Error: Unknown PME clock select!\n");
190 case 0: 191 case 0:
191 sys_info->freq_pme = sys_info->freq_systembus / 2; 192 sys_info->freq_pme = sys_info->freq_systembus / 2;
192 break; 193 break;
193 194
194 } 195 }
195 #else 196 #else
196 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; 197 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
197 198
198 #endif 199 #endif
199 #endif 200 #endif
200 201
201 #ifdef CONFIG_SYS_DPAA_QBMAN 202 #ifdef CONFIG_SYS_DPAA_QBMAN
202 sys_info->freq_qman = sys_info->freq_systembus / 2; 203 sys_info->freq_qman = sys_info->freq_systembus / 2;
203 #endif 204 #endif
204 205
205 #ifdef CONFIG_SYS_DPAA_FMAN 206 #ifdef CONFIG_SYS_DPAA_FMAN
206 #ifndef CONFIG_FM_PLAT_CLK_DIV 207 #ifndef CONFIG_FM_PLAT_CLK_DIV
207 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { 208 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
208 case 1: 209 case 1:
209 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; 210 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
210 break; 211 break;
211 case 2: 212 case 2:
212 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; 213 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
213 break; 214 break;
214 case 3: 215 case 3:
215 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; 216 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
216 break; 217 break;
217 case 4: 218 case 4:
218 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; 219 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
219 break; 220 break;
220 case 5: 221 case 5:
221 sys_info->freq_fman[0] = sys_info->freq_systembus; 222 sys_info->freq_fman[0] = sys_info->freq_systembus;
222 break; 223 break;
223 case 6: 224 case 6:
224 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; 225 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
225 break; 226 break;
226 case 7: 227 case 7:
227 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; 228 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
228 break; 229 break;
229 default: 230 default:
230 printf("Error: Unknown FMan1 clock select!\n"); 231 printf("Error: Unknown FMan1 clock select!\n");
231 case 0: 232 case 0:
232 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 233 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
233 break; 234 break;
234 } 235 }
235 #if (CONFIG_SYS_NUM_FMAN) == 2 236 #if (CONFIG_SYS_NUM_FMAN) == 2
236 #ifdef CONFIG_SYS_FM2_CLK 237 #ifdef CONFIG_SYS_FM2_CLK
237 #define FM2_CLK_SEL 0x00000038 238 #define FM2_CLK_SEL 0x00000038
238 #define FM2_CLK_SHIFT 3 239 #define FM2_CLK_SHIFT 3
239 rcw_tmp = in_be32(&gur->rcwsr[15]); 240 rcw_tmp = in_be32(&gur->rcwsr[15]);
240 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { 241 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
241 case 1: 242 case 1:
242 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; 243 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
243 break; 244 break;
244 case 2: 245 case 2:
245 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; 246 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
246 break; 247 break;
247 case 3: 248 case 3:
248 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; 249 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
249 break; 250 break;
250 case 4: 251 case 4:
251 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; 252 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
252 break; 253 break;
253 case 5: 254 case 5:
254 sys_info->freq_fman[1] = sys_info->freq_systembus; 255 sys_info->freq_fman[1] = sys_info->freq_systembus;
255 break; 256 break;
256 case 6: 257 case 6:
257 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; 258 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
258 break; 259 break;
259 case 7: 260 case 7:
260 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; 261 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
261 break; 262 break;
262 default: 263 default:
263 printf("Error: Unknown FMan2 clock select!\n"); 264 printf("Error: Unknown FMan2 clock select!\n");
264 case 0: 265 case 0:
265 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 266 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
266 break; 267 break;
267 } 268 }
268 #endif 269 #endif
269 #endif /* CONFIG_SYS_NUM_FMAN == 2 */ 270 #endif /* CONFIG_SYS_NUM_FMAN == 2 */
270 #else 271 #else
271 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; 272 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
272 #endif 273 #endif
273 #endif 274 #endif
274 275
275 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 276 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
276 277
277 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 278 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
278 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) 279 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
279 & 0xf; 280 & 0xf;
280 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 281 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
281 282
282 sys_info->freq_processor[cpu] = 283 sys_info->freq_processor[cpu] =
283 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 284 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
284 } 285 }
285 #define PME_CLK_SEL 0x80000000 286 #define PME_CLK_SEL 0x80000000
286 #define FM1_CLK_SEL 0x40000000 287 #define FM1_CLK_SEL 0x40000000
287 #define FM2_CLK_SEL 0x20000000 288 #define FM2_CLK_SEL 0x20000000
288 #define HWA_ASYNC_DIV 0x04000000 289 #define HWA_ASYNC_DIV 0x04000000
289 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) 290 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
290 #define HWA_CC_PLL 1 291 #define HWA_CC_PLL 1
291 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3) 292 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
292 #define HWA_CC_PLL 2 293 #define HWA_CC_PLL 2
293 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) 294 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
294 #define HWA_CC_PLL 2 295 #define HWA_CC_PLL 2
295 #else 296 #else
296 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case 297 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
297 #endif 298 #endif
298 rcw_tmp = in_be32(&gur->rcwsr[7]); 299 rcw_tmp = in_be32(&gur->rcwsr[7]);
299 300
300 #ifdef CONFIG_SYS_DPAA_PME 301 #ifdef CONFIG_SYS_DPAA_PME
301 if (rcw_tmp & PME_CLK_SEL) { 302 if (rcw_tmp & PME_CLK_SEL) {
302 if (rcw_tmp & HWA_ASYNC_DIV) 303 if (rcw_tmp & HWA_ASYNC_DIV)
303 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4; 304 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
304 else 305 else
305 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2; 306 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
306 } else { 307 } else {
307 sys_info->freq_pme = sys_info->freq_systembus / 2; 308 sys_info->freq_pme = sys_info->freq_systembus / 2;
308 } 309 }
309 #endif 310 #endif
310 311
311 #ifdef CONFIG_SYS_DPAA_FMAN 312 #ifdef CONFIG_SYS_DPAA_FMAN
312 if (rcw_tmp & FM1_CLK_SEL) { 313 if (rcw_tmp & FM1_CLK_SEL) {
313 if (rcw_tmp & HWA_ASYNC_DIV) 314 if (rcw_tmp & HWA_ASYNC_DIV)
314 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4; 315 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
315 else 316 else
316 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2; 317 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
317 } else { 318 } else {
318 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 319 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
319 } 320 }
320 #if (CONFIG_SYS_NUM_FMAN) == 2 321 #if (CONFIG_SYS_NUM_FMAN) == 2
321 if (rcw_tmp & FM2_CLK_SEL) { 322 if (rcw_tmp & FM2_CLK_SEL) {
322 if (rcw_tmp & HWA_ASYNC_DIV) 323 if (rcw_tmp & HWA_ASYNC_DIV)
323 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; 324 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
324 else 325 else
325 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2; 326 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
326 } else { 327 } else {
327 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 328 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
328 } 329 }
329 #endif 330 #endif
330 #endif 331 #endif
331 332
332 #ifdef CONFIG_SYS_DPAA_QBMAN 333 #ifdef CONFIG_SYS_DPAA_QBMAN
333 sys_info->freq_qman = sys_info->freq_systembus / 2; 334 sys_info->freq_qman = sys_info->freq_systembus / 2;
334 #endif 335 #endif
335 336
336 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 337 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
337 338
338 #else /* CONFIG_FSL_CORENET */ 339 #else /* CONFIG_FSL_CORENET */
339 uint plat_ratio, e500_ratio, half_freq_systembus; 340 uint plat_ratio, e500_ratio, half_freq_systembus;
340 int i; 341 int i;
341 #ifdef CONFIG_QE 342 #ifdef CONFIG_QE
342 __maybe_unused u32 qe_ratio; 343 __maybe_unused u32 qe_ratio;
343 #endif 344 #endif
344 345
345 plat_ratio = (gur->porpllsr) & 0x0000003e; 346 plat_ratio = (gur->porpllsr) & 0x0000003e;
346 plat_ratio >>= 1; 347 plat_ratio >>= 1;
347 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; 348 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
348 349
349 /* Divide before multiply to avoid integer 350 /* Divide before multiply to avoid integer
350 * overflow for processor speeds above 2GHz */ 351 * overflow for processor speeds above 2GHz */
351 half_freq_systembus = sys_info->freq_systembus/2; 352 half_freq_systembus = sys_info->freq_systembus/2;
352 for (i = 0; i < cpu_numcores(); i++) { 353 for (i = 0; i < cpu_numcores(); i++) {
353 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; 354 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
354 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus; 355 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
355 } 356 }
356 357
357 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */ 358 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
358 sys_info->freq_ddrbus = sys_info->freq_systembus; 359 sys_info->freq_ddrbus = sys_info->freq_systembus;
359 360
360 #ifdef CONFIG_DDR_CLK_FREQ 361 #ifdef CONFIG_DDR_CLK_FREQ
361 { 362 {
362 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 363 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
363 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 364 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
364 if (ddr_ratio != 0x7) 365 if (ddr_ratio != 0x7)
365 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ; 366 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
366 } 367 }
367 #endif 368 #endif
368 369
369 #ifdef CONFIG_QE 370 #ifdef CONFIG_QE
370 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) 371 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
371 sys_info->freq_qe = sys_info->freq_systembus; 372 sys_info->freq_qe = sys_info->freq_systembus;
372 #else 373 #else
373 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) 374 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
374 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; 375 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
375 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ; 376 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
376 #endif 377 #endif
377 #endif 378 #endif
378 379
379 #ifdef CONFIG_SYS_DPAA_FMAN 380 #ifdef CONFIG_SYS_DPAA_FMAN
380 sys_info->freq_fman[0] = sys_info->freq_systembus; 381 sys_info->freq_fman[0] = sys_info->freq_systembus;
381 #endif 382 #endif
382 383
383 #endif /* CONFIG_FSL_CORENET */ 384 #endif /* CONFIG_FSL_CORENET */
384 385
385 #if defined(CONFIG_FSL_LBC) 386 #if defined(CONFIG_FSL_LBC)
386 uint lcrr_div; 387 uint lcrr_div;
387 #if defined(CONFIG_SYS_LBC_LCRR) 388 #if defined(CONFIG_SYS_LBC_LCRR)
388 /* We will program LCRR to this value later */ 389 /* We will program LCRR to this value later */
389 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; 390 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
390 #else 391 #else
391 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; 392 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
392 #endif 393 #endif
393 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { 394 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
394 #if defined(CONFIG_FSL_CORENET) 395 #if defined(CONFIG_FSL_CORENET)
395 /* If this is corenet based SoC, bit-representation 396 /* If this is corenet based SoC, bit-representation
396 * for four times the clock divider values. 397 * for four times the clock divider values.
397 */ 398 */
398 lcrr_div *= 4; 399 lcrr_div *= 4;
399 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ 400 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
400 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) 401 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
401 /* 402 /*
402 * Yes, the entire PQ38 family use the same 403 * Yes, the entire PQ38 family use the same
403 * bit-representation for twice the clock divider values. 404 * bit-representation for twice the clock divider values.
404 */ 405 */
405 lcrr_div *= 2; 406 lcrr_div *= 2;
406 #endif 407 #endif
407 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div; 408 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
408 } else { 409 } else {
409 /* In case anyone cares what the unknown value is */ 410 /* In case anyone cares what the unknown value is */
410 sys_info->freq_localbus = lcrr_div; 411 sys_info->freq_localbus = lcrr_div;
411 } 412 }
412 #endif 413 #endif
413 414
414 #if defined(CONFIG_FSL_IFC) 415 #if defined(CONFIG_FSL_IFC)
415 ccr = in_be32(&ifc_regs->ifc_ccr); 416 ccr = in_be32(&ifc_regs->ifc_ccr);
416 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; 417 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
417 418
418 sys_info->freq_localbus = sys_info->freq_systembus / ccr; 419 sys_info->freq_localbus = sys_info->freq_systembus / ccr;
419 #endif 420 #endif
420 } 421 }
421 422
422 423
423 int get_clocks (void) 424 int get_clocks (void)
424 { 425 {
425 sys_info_t sys_info; 426 sys_info_t sys_info;
426 #ifdef CONFIG_MPC8544 427 #ifdef CONFIG_MPC8544
427 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; 428 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
428 #endif 429 #endif
429 #if defined(CONFIG_CPM2) 430 #if defined(CONFIG_CPM2)
430 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 431 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
431 uint sccr, dfbrg; 432 uint sccr, dfbrg;
432 433
433 /* set VCO = 4 * BRG */ 434 /* set VCO = 4 * BRG */
434 cpm->im_cpm_intctl.sccr &= 0xfffffffc; 435 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
435 sccr = cpm->im_cpm_intctl.sccr; 436 sccr = cpm->im_cpm_intctl.sccr;
436 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; 437 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
437 #endif 438 #endif
438 get_sys_info (&sys_info); 439 get_sys_info (&sys_info);
439 gd->cpu_clk = sys_info.freq_processor[0]; 440 gd->cpu_clk = sys_info.freq_processor[0];
440 gd->bus_clk = sys_info.freq_systembus; 441 gd->bus_clk = sys_info.freq_systembus;
441 gd->mem_clk = sys_info.freq_ddrbus; 442 gd->mem_clk = sys_info.freq_ddrbus;
442 gd->arch.lbc_clk = sys_info.freq_localbus; 443 gd->arch.lbc_clk = sys_info.freq_localbus;
443 444
444 #ifdef CONFIG_QE 445 #ifdef CONFIG_QE
445 gd->arch.qe_clk = sys_info.freq_qe; 446 gd->arch.qe_clk = sys_info.freq_qe;
446 gd->arch.brg_clk = gd->arch.qe_clk / 2; 447 gd->arch.brg_clk = gd->arch.qe_clk / 2;
447 #endif 448 #endif
448 /* 449 /*
449 * The base clock for I2C depends on the actual SOC. Unfortunately, 450 * The base clock for I2C depends on the actual SOC. Unfortunately,
450 * there is no pattern that can be used to determine the frequency, so 451 * there is no pattern that can be used to determine the frequency, so
451 * the only choice is to look up the actual SOC number and use the value 452 * the only choice is to look up the actual SOC number and use the value
452 * for that SOC. This information is taken from application note 453 * for that SOC. This information is taken from application note
453 * AN2919. 454 * AN2919.
454 */ 455 */
455 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 456 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
456 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \ 457 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
457 defined(CONFIG_P1022) 458 defined(CONFIG_P1022)
458 gd->arch.i2c1_clk = sys_info.freq_systembus; 459 gd->arch.i2c1_clk = sys_info.freq_systembus;
459 #elif defined(CONFIG_MPC8544) 460 #elif defined(CONFIG_MPC8544)
460 /* 461 /*
461 * On the 8544, the I2C clock is the same as the SEC clock. This can be 462 * On the 8544, the I2C clock is the same as the SEC clock. This can be
462 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See 463 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
463 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all 464 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
464 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the 465 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
465 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. 466 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
466 */ 467 */
467 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) 468 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
468 gd->arch.i2c1_clk = sys_info.freq_systembus / 3; 469 gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
469 else 470 else
470 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 471 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
471 #else 472 #else
472 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ 473 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
473 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 474 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
474 #endif 475 #endif
475 gd->arch.i2c2_clk = gd->arch.i2c1_clk; 476 gd->arch.i2c2_clk = gd->arch.i2c1_clk;
476 477
477 #if defined(CONFIG_FSL_ESDHC) 478 #if defined(CONFIG_FSL_ESDHC)
478 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ 479 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
479 defined(CONFIG_P1014) 480 defined(CONFIG_P1014)
480 gd->arch.sdhc_clk = gd->bus_clk; 481 gd->arch.sdhc_clk = gd->bus_clk;
481 #else 482 #else
482 gd->arch.sdhc_clk = gd->bus_clk / 2; 483 gd->arch.sdhc_clk = gd->bus_clk / 2;
483 #endif 484 #endif
484 #endif /* defined(CONFIG_FSL_ESDHC) */ 485 #endif /* defined(CONFIG_FSL_ESDHC) */
485 486
486 #if defined(CONFIG_CPM2) 487 #if defined(CONFIG_CPM2)
487 gd->arch.vco_out = 2*sys_info.freq_systembus; 488 gd->arch.vco_out = 2*sys_info.freq_systembus;
488 gd->arch.cpm_clk = gd->arch.vco_out / 2; 489 gd->arch.cpm_clk = gd->arch.vco_out / 2;
489 gd->arch.scc_clk = gd->arch.vco_out / 4; 490 gd->arch.scc_clk = gd->arch.vco_out / 4;
490 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); 491 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
491 #endif 492 #endif
492 493
493 if(gd->cpu_clk != 0) return (0); 494 if(gd->cpu_clk != 0) return (0);
494 else return (1); 495 else return (1);
495 } 496 }
496 497
497 498
498 /******************************************** 499 /********************************************
499 * get_bus_freq 500 * get_bus_freq
500 * return system bus freq in Hz 501 * return system bus freq in Hz
501 *********************************************/ 502 *********************************************/
502 ulong get_bus_freq (ulong dummy) 503 ulong get_bus_freq (ulong dummy)
503 { 504 {
504 return gd->bus_clk; 505 return gd->bus_clk;
505 } 506 }
506 507
507 /******************************************** 508 /********************************************
508 * get_ddr_freq 509 * get_ddr_freq
509 * return ddr bus freq in Hz 510 * return ddr bus freq in Hz
510 *********************************************/ 511 *********************************************/
511 ulong get_ddr_freq (ulong dummy) 512 ulong get_ddr_freq (ulong dummy)
512 { 513 {
513 return gd->mem_clk; 514 return gd->mem_clk;
514 } 515 }
515 516
arch/powerpc/cpu/mpc85xx/t2080_ids.c
Diff comments   View file @ 35c471e
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <asm/fsl_portals.h> 8 #include <asm/fsl_portals.h>
9 #include <asm/fsl_liodn.h> 9 #include <asm/fsl_liodn.h>
10 10
11 #ifdef CONFIG_SYS_DPAA_QBMAN 11 #ifdef CONFIG_SYS_DPAA_QBMAN
12 struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { 12 struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
13 /* dqrr liodn, frame data liodn, liodn off, sdest */ 13 /* dqrr liodn, frame data liodn, liodn off, sdest */
14 SET_QP_INFO(1, 27, 1, 0), 14 SET_QP_INFO(1, 27, 1, 0),
15 SET_QP_INFO(2, 28, 1, 0), 15 SET_QP_INFO(2, 28, 1, 0),
16 SET_QP_INFO(3, 29, 1, 1), 16 SET_QP_INFO(3, 29, 1, 1),
17 SET_QP_INFO(4, 30, 1, 1), 17 SET_QP_INFO(4, 30, 1, 1),
18 SET_QP_INFO(5, 31, 1, 2), 18 SET_QP_INFO(5, 31, 1, 2),
19 SET_QP_INFO(6, 32, 1, 2), 19 SET_QP_INFO(6, 32, 1, 2),
20 SET_QP_INFO(7, 33, 1, 3), 20 SET_QP_INFO(7, 33, 1, 3),
21 SET_QP_INFO(8, 34, 1, 3), 21 SET_QP_INFO(8, 34, 1, 3),
22 SET_QP_INFO(9, 35, 1, 0), 22 SET_QP_INFO(9, 35, 1, 0),
23 SET_QP_INFO(10, 36, 1, 0), 23 SET_QP_INFO(10, 36, 1, 0),
24 SET_QP_INFO(11, 37, 1, 1), 24 SET_QP_INFO(11, 37, 1, 1),
25 SET_QP_INFO(12, 38, 1, 1), 25 SET_QP_INFO(12, 38, 1, 1),
26 SET_QP_INFO(13, 39, 1, 2), 26 SET_QP_INFO(13, 39, 1, 2),
27 SET_QP_INFO(14, 40, 1, 2), 27 SET_QP_INFO(14, 40, 1, 2),
28 SET_QP_INFO(15, 41, 1, 3), 28 SET_QP_INFO(15, 41, 1, 3),
29 SET_QP_INFO(16, 42, 1, 3), 29 SET_QP_INFO(16, 42, 1, 3),
30 SET_QP_INFO(17, 43, 1, 0), 30 SET_QP_INFO(17, 43, 1, 0),
31 SET_QP_INFO(18, 44, 1, 0), 31 SET_QP_INFO(18, 44, 1, 0),
32 }; 32 };
33 #endif 33 #endif
34 34
35 #ifdef CONFIG_SYS_SRIO 35 #ifdef CONFIG_SYS_SRIO
36 struct srio_liodn_id_table srio_liodn_tbl[] = { 36 struct srio_liodn_id_table srio_liodn_tbl[] = {
37 SET_SRIO_LIODN_BASE(1, 307), 37 SET_SRIO_LIODN_BASE(1, 307),
38 SET_SRIO_LIODN_BASE(2, 387), 38 SET_SRIO_LIODN_BASE(2, 387),
39 }; 39 };
40 int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); 40 int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
41 #endif 41 #endif
42 42
43 struct liodn_id_table liodn_tbl[] = { 43 struct liodn_id_table liodn_tbl[] = {
44 #ifdef CONFIG_SYS_DPAA_QBMAN 44 #ifdef CONFIG_SYS_DPAA_QBMAN
45 SET_QMAN_LIODN(62), 45 SET_QMAN_LIODN(62),
46 SET_BMAN_LIODN(63), 46 SET_BMAN_LIODN(63),
47 #endif 47 #endif
48 48
49 SET_SDHC_LIODN(1, 552), 49 SET_SDHC_LIODN(1, 552),
50 50
51 SET_PME_LIODN(117), 51 SET_PME_LIODN(117),
52 52
53 SET_USB_LIODN(1, "fsl-usb2-mph", 553), 53 SET_USB_LIODN(1, "fsl-usb2-mph", 553),
54 SET_USB_LIODN(2, "fsl-usb2-dr", 554), 54 SET_USB_LIODN(2, "fsl-usb2-dr", 554),
55 55
56 #ifdef CONFIG_FSL_SATA_V2
56 SET_SATA_LIODN(1, 555), 57 SET_SATA_LIODN(1, 555),
57 SET_SATA_LIODN(2, 556), 58 SET_SATA_LIODN(2, 556),
59 #endif
58 60
59 SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), 61 SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
60 SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), 62 SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
61 SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), 63 SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
62 SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), 64 SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
63 65
64 SET_DMA_LIODN(1, 147), 66 SET_DMA_LIODN(1, 147),
65 SET_DMA_LIODN(2, 227), 67 SET_DMA_LIODN(2, 227),
66 SET_DMA_LIODN(3, 226), 68 SET_DMA_LIODN(3, 226),
67 69
68 SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), 70 SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
69 SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), 71 SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
70 SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), 72 SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
71 SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), 73 SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
72 74
73 #ifdef CONFIG_SYS_PMAN 75 #ifdef CONFIG_SYS_PMAN
74 SET_PMAN_LIODN(1, 513), 76 SET_PMAN_LIODN(1, 513),
75 SET_PMAN_LIODN(2, 514), 77 SET_PMAN_LIODN(2, 514),
76 SET_PMAN_LIODN(3, 515), 78 SET_PMAN_LIODN(3, 515),
77 #endif 79 #endif
78 80
79 /* SET_NEXUS_LIODN(557), -- not yet implemented */ 81 /* SET_NEXUS_LIODN(557), -- not yet implemented */
80 }; 82 };
81 int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); 83 int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
82 84
83 #ifdef CONFIG_SYS_DPAA_FMAN 85 #ifdef CONFIG_SYS_DPAA_FMAN
84 struct liodn_id_table fman1_liodn_tbl[] = { 86 struct liodn_id_table fman1_liodn_tbl[] = {
85 SET_FMAN_RX_1G_LIODN(1, 0, 88), 87 SET_FMAN_RX_1G_LIODN(1, 0, 88),
86 SET_FMAN_RX_1G_LIODN(1, 1, 89), 88 SET_FMAN_RX_1G_LIODN(1, 1, 89),
87 SET_FMAN_RX_1G_LIODN(1, 2, 90), 89 SET_FMAN_RX_1G_LIODN(1, 2, 90),
88 SET_FMAN_RX_1G_LIODN(1, 3, 91), 90 SET_FMAN_RX_1G_LIODN(1, 3, 91),
89 SET_FMAN_RX_1G_LIODN(1, 4, 92), 91 SET_FMAN_RX_1G_LIODN(1, 4, 92),
90 SET_FMAN_RX_1G_LIODN(1, 5, 93), 92 SET_FMAN_RX_1G_LIODN(1, 5, 93),
91 SET_FMAN_RX_10G_LIODN(1, 0, 94), 93 SET_FMAN_RX_10G_LIODN(1, 0, 94),
92 SET_FMAN_RX_10G_LIODN(1, 1, 95), 94 SET_FMAN_RX_10G_LIODN(1, 1, 95),
93 }; 95 };
94 int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); 96 int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
95 #endif 97 #endif
96 98
97 struct liodn_id_table sec_liodn_tbl[] = { 99 struct liodn_id_table sec_liodn_tbl[] = {
98 SET_SEC_JR_LIODN_ENTRY(0, 454, 458), 100 SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
99 SET_SEC_JR_LIODN_ENTRY(1, 455, 459), 101 SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
100 SET_SEC_JR_LIODN_ENTRY(2, 456, 460), 102 SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
101 SET_SEC_JR_LIODN_ENTRY(3, 457, 461), 103 SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
102 SET_SEC_RTIC_LIODN_ENTRY(a, 453), 104 SET_SEC_RTIC_LIODN_ENTRY(a, 453),
103 SET_SEC_RTIC_LIODN_ENTRY(b, 549), 105 SET_SEC_RTIC_LIODN_ENTRY(b, 549),
104 SET_SEC_RTIC_LIODN_ENTRY(c, 550), 106 SET_SEC_RTIC_LIODN_ENTRY(c, 550),
105 SET_SEC_RTIC_LIODN_ENTRY(d, 551), 107 SET_SEC_RTIC_LIODN_ENTRY(d, 551),
106 SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), 108 SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
107 SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), 109 SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
108 SET_SEC_DECO_LIODN_ENTRY(2, 543, 612), 110 SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
109 SET_SEC_DECO_LIODN_ENTRY(3, 544, 613), 111 SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
110 SET_SEC_DECO_LIODN_ENTRY(4, 545, 614), 112 SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
111 SET_SEC_DECO_LIODN_ENTRY(5, 546, 615), 113 SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
112 SET_SEC_DECO_LIODN_ENTRY(6, 547, 616), 114 SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
113 SET_SEC_DECO_LIODN_ENTRY(7, 548, 617), 115 SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
114 }; 116 };
115 int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); 117 int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
116 118
117 #ifdef CONFIG_SYS_DPAA_RMAN 119 #ifdef CONFIG_SYS_DPAA_RMAN
118 struct liodn_id_table rman_liodn_tbl[] = { 120 struct liodn_id_table rman_liodn_tbl[] = {
119 /* Set RMan block 0-3 liodn offset */ 121 /* Set RMan block 0-3 liodn offset */
120 SET_RMAN_LIODN(0, 6), 122 SET_RMAN_LIODN(0, 6),
121 SET_RMAN_LIODN(1, 7), 123 SET_RMAN_LIODN(1, 7),
122 SET_RMAN_LIODN(2, 8), 124 SET_RMAN_LIODN(2, 8),
123 SET_RMAN_LIODN(3, 9), 125 SET_RMAN_LIODN(3, 9),
124 }; 126 };
125 int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); 127 int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
126 #endif 128 #endif
127 129
128 struct liodn_id_table liodn_bases[] = { 130 struct liodn_id_table liodn_bases[] = {
129 #ifdef CONFIG_SYS_DPAA_DCE 131 #ifdef CONFIG_SYS_DPAA_DCE
130 [FSL_HW_PORTAL_DCE] = SET_LIODN_BASE_2(618, 694), 132 [FSL_HW_PORTAL_DCE] = SET_LIODN_BASE_2(618, 694),
131 #endif 133 #endif
132 [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), 134 [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558),
133 #ifdef CONFIG_SYS_DPAA_FMAN 135 #ifdef CONFIG_SYS_DPAA_FMAN
134 [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), 136 [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
135 #endif 137 #endif
136 #ifdef CONFIG_SYS_DPAA_PME 138 #ifdef CONFIG_SYS_DPAA_PME
137 [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846), 139 [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846),
138 #endif 140 #endif
139 #ifdef CONFIG_SYS_DPAA_RMAN 141 #ifdef CONFIG_SYS_DPAA_RMAN
140 [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922), 142 [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
141 #endif 143 #endif
142 }; 144 };
143 145
arch/powerpc/cpu/mpc85xx/t2080_serdes.c
Diff comments   View file @ 35c471e
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * Shengzhou Liu <Shengzhou.Liu@freescale.com> 4 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #include <common.h> 9 #include <common.h>
10 #include <asm/fsl_serdes.h> 10 #include <asm/fsl_serdes.h>
11 #include <asm/processor.h> 11 #include <asm/processor.h>
12 #include "fsl_corenet2_serdes.h" 12 #include "fsl_corenet2_serdes.h"
13 13
14 struct serdes_config { 14 struct serdes_config {
15 u32 protocol; 15 u32 protocol;
16 u8 lanes[SRDS_MAX_LANES]; 16 u8 lanes[SRDS_MAX_LANES];
17 }; 17 };
18 18
19 static const struct serdes_config serdes1_cfg_tbl[] = { 19 static const struct serdes_config serdes1_cfg_tbl[] = {
20 /* SerDes 1 */ 20 /* SerDes 1 */
21 {0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10, 21 {0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10,
22 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 22 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
23 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 23 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
24 {0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1, 24 {0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1,
25 SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} }, 25 SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} },
26 {0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 26 {0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
27 SGMII_FM1_DTSEC2, PCIE4, PCIE4, 27 SGMII_FM1_DTSEC2, PCIE4, PCIE4,
28 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 28 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
29 {0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 29 {0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
30 SGMII_FM1_DTSEC2, PCIE4, PCIE4, 30 SGMII_FM1_DTSEC2, PCIE4, PCIE4,
31 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 31 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
32 {0xDE, {PCIE3, PCIE3, PCIE3, PCIE3, 32 {0xDE, {PCIE3, PCIE3, PCIE3, PCIE3,
33 PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, 33 PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
34 {0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, 34 {0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4,
35 PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 35 PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
36 {0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 36 {0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
37 SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, 37 SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
38 {0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 38 {0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
39 SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, 39 SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
40 {0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 40 {0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
41 SGMII_FM1_DTSEC2, PCIE4, PCIE1, 41 SGMII_FM1_DTSEC2, PCIE4, PCIE1,
42 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 42 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
43 {0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10, 43 {0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
44 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 44 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
45 PCIE4, PCIE4, PCIE4, PCIE4} }, 45 PCIE4, PCIE4, PCIE4, PCIE4} },
46 #if defined(CONFIG_PPC_T2080)
47 {0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 46 {0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
48 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 47 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
49 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 48 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
50 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 49 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
51 {0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 50 {0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
52 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 51 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
53 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 52 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
54 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 53 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
55 {0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 54 {0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
56 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 55 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
57 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 56 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
58 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 57 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
59 {0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 58 {0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
60 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 59 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
61 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 60 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
62 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 61 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
63 {0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 62 {0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
64 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 63 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
65 PCIE4, SGMII_FM1_DTSEC4, 64 PCIE4, SGMII_FM1_DTSEC4,
66 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 65 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
67 {0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 66 {0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
68 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 67 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
69 PCIE4, SGMII_FM1_DTSEC4, 68 PCIE4, SGMII_FM1_DTSEC4,
70 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 69 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
71 {0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 70 {0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
72 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, 71 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
73 PCIE4, SGMII_FM1_DTSEC4, 72 PCIE4, SGMII_FM1_DTSEC4,
74 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 73 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
75 {0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10, 74 {0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
76 XFI_FM1_MAC1, XFI_FM1_MAC2, 75 XFI_FM1_MAC1, XFI_FM1_MAC2,
77 PCIE4, SGMII_FM1_DTSEC4, 76 PCIE4, SGMII_FM1_DTSEC4,
78 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 77 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
79 {0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10, 78 {0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10,
80 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 79 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
81 PCIE4, PCIE4, PCIE4, PCIE4} }, 80 PCIE4, PCIE4, PCIE4, PCIE4} },
82 {0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10, 81 {0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10,
83 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, 82 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
84 SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 83 SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
85 {0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 84 {0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
86 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, 85 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
87 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 86 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
88 {0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 87 {0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
89 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, 88 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
90 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 89 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
91 {0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 90 {0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
92 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, 91 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
93 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 92 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
94 {0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 93 {0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
95 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 94 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
96 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 95 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
97 {0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 96 {0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
98 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 97 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
99 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 98 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
100 {0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 99 {0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
101 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 100 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
102 PCIE4, PCIE4, PCIE4, PCIE4} }, 101 PCIE4, PCIE4, PCIE4, PCIE4} },
103 {0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 102 {0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
104 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 103 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
105 PCIE4, PCIE4, PCIE4, PCIE4} }, 104 PCIE4, PCIE4, PCIE4, PCIE4} },
106 {0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, 105 {0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
107 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 106 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
108 PCIE4, PCIE4, PCIE4, PCIE4} }, 107 PCIE4, PCIE4, PCIE4, PCIE4} },
109 {0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10, 108 {0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10,
110 XFI_FM1_MAC1, XFI_FM1_MAC2, 109 XFI_FM1_MAC1, XFI_FM1_MAC2,
111 PCIE4, PCIE4, PCIE4, PCIE4} }, 110 PCIE4, PCIE4, PCIE4, PCIE4} },
112 {0xAB, {PCIE3, PCIE3, PCIE3, PCIE3, 111 {0xAB, {PCIE3, PCIE3, PCIE3, PCIE3,
113 PCIE4, PCIE4, PCIE4, PCIE4} }, 112 PCIE4, PCIE4, PCIE4, PCIE4} },
114 {0xDA, {PCIE3, PCIE3, PCIE3, PCIE3, 113 {0xDA, {PCIE3, PCIE3, PCIE3, PCIE3,
115 PCIE3, PCIE3, PCIE3, PCIE3} }, 114 PCIE3, PCIE3, PCIE3, PCIE3} },
116 {0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 115 {0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
117 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 116 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
118 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 117 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
119 {0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 118 {0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
120 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 119 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
121 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 120 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
122 {0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 121 {0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
123 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 122 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
124 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 123 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
125 {0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 124 {0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
126 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 125 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
127 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 126 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
128 {0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10, 127 {0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
129 XFI_FM1_MAC1, XFI_FM1_MAC2, 128 XFI_FM1_MAC1, XFI_FM1_MAC2,
130 PCIE4, PCIE4, PCIE4, PCIE4} }, 129 PCIE4, PCIE4, PCIE4, PCIE4} },
131 130
132 #elif defined(CONFIG_PPC_T2081) 131 #if defined(CONFIG_PPC_T2081)
133 {0xAA, {PCIE3, PCIE3, PCIE3, PCIE3, 132 {0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
134 PCIE4, PCIE4, PCIE4, PCIE4} }, 133 PCIE4, PCIE4, PCIE4, PCIE4} },
135 {0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, 134 {0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
136 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 135 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
137 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 136 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
138 {0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1, 137 {0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
139 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, 138 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
140 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, 139 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
141 #endif 140 #endif
142 {} 141 {}
143 }; 142 };
144 143
145 #ifndef CONFIG_PPC_T2081 144 #ifndef CONFIG_PPC_T2081
146 static const struct serdes_config serdes2_cfg_tbl[] = { 145 static const struct serdes_config serdes2_cfg_tbl[] = {
147 /* SerDes 2 */ 146 /* SerDes 2 */
148 {0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, 147 {0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
149 {0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, 148 {0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
150 {0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, 149 {0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
151 {0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, 150 {0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
152 {0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, 151 {0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
153 {0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, 152 {0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
154 {0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} }, 153 {0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
155 {0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, 154 {0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
156 {0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} }, 155 {0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
157 {} 156 {}
158 }; 157 };
159 #endif 158 #endif
160 159
161 static const struct serdes_config *serdes_cfg_tbl[] = { 160 static const struct serdes_config *serdes_cfg_tbl[] = {
162 serdes1_cfg_tbl, 161 serdes1_cfg_tbl,
163 #ifndef CONFIG_PPC_T2081 162 #ifndef CONFIG_PPC_T2081
164 serdes2_cfg_tbl, 163 serdes2_cfg_tbl,
165 #endif 164 #endif
166 }; 165 };
167 166
168 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) 167 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
169 { 168 {
170 const struct serdes_config *ptr; 169 const struct serdes_config *ptr;
171 170
172 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 171 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
173 return 0; 172 return 0;
174 173
175 ptr = serdes_cfg_tbl[serdes]; 174 ptr = serdes_cfg_tbl[serdes];
176 while (ptr->protocol) { 175 while (ptr->protocol) {
177 if (ptr->protocol == cfg) 176 if (ptr->protocol == cfg)
178 return ptr->lanes[lane]; 177 return ptr->lanes[lane];
179 ptr++; 178 ptr++;
180 } 179 }
181 return 0; 180 return 0;
182 } 181 }
183 182
184 int is_serdes_prtcl_valid(int serdes, u32 prtcl) 183 int is_serdes_prtcl_valid(int serdes, u32 prtcl)
185 { 184 {
186 int i; 185 int i;
187 const struct serdes_config *ptr; 186 const struct serdes_config *ptr;
188 187
189 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 188 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
190 return 0; 189 return 0;
191 190
192 ptr = serdes_cfg_tbl[serdes]; 191 ptr = serdes_cfg_tbl[serdes];
193 while (ptr->protocol) { 192 while (ptr->protocol) {
194 if (ptr->protocol == prtcl) 193 if (ptr->protocol == prtcl)
195 break; 194 break;
196 ptr++; 195 ptr++;
197 } 196 }
198 197
199 if (!ptr->protocol) 198 if (!ptr->protocol)
200 return 0; 199 return 0;
201 200
202 for (i = 0; i < SRDS_MAX_LANES; i++) { 201 for (i = 0; i < SRDS_MAX_LANES; i++) {
203 if (ptr->lanes[i] != NONE) 202 if (ptr->lanes[i] != NONE)
204 return 1; 203 return 1;
205 } 204 }
206 205
207 return 0; 206 return 0;
208 } 207 }
209 208