Eric Lee / smarc-uboot

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Commit 35fca4c44d429ae6f2f4feae6dd4b30a72449906

Authored by Wolfgang Denk
2 parents cda2a4a996 2dd7082e06
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx

Showing 4 changed files Inline Diff

board/amcc/canyonlands/config.mk
Diff comments   View file @ 35fca4c
1 # 1 #
2 # (C) Copyright 2008 2 # (C) Copyright 2008
3 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 # 4 #
5 # See file CREDITS for list of people who contributed to this 5 # See file CREDITS for list of people who contributed to this
6 # project. 6 # project.
7 # 7 #
8 # This program is free software; you can redistribute it and/or 8 # This program is free software; you can redistribute it and/or
9 # modify it under the terms of the GNU General Public License as 9 # modify it under the terms of the GNU General Public License as
10 # published by the Free Software Foundation; either version 2 of 10 # published by the Free Software Foundation; either version 2 of
11 # the License, or (at your option) any later version. 11 # the License, or (at your option) any later version.
12 # 12 #
13 # This program is distributed in the hope that it will be useful, 13 # This program is distributed in the hope that it will be useful,
14 # but WITHOUT ANY WARRANTY; without even the implied warranty of 14 # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 # GNU General Public License for more details. 16 # GNU General Public License for more details.
17 # 17 #
18 # You should have received a copy of the GNU General Public License 18 # You should have received a copy of the GNU General Public License
19 # along with this program; if not, write to the Free Software 19 # along with this program; if not, write to the Free Software
20 # Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 # MA 02111-1307 USA 21 # MA 02111-1307 USA
22 # 22 #
23 # 23 #
24 # AMCC 460EX/460GT Evaluation Board (Canyonlands) board 24 # AMCC 460EX/460GT Evaluation Board (Canyonlands) board
25 # 25 #
26 26
27 sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp 27 sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
28 28
29 ifndef TEXT_BASE 29 ifndef TEXT_BASE
30 TEXT_BASE = 0xFFFA0000 30 TEXT_BASE = 0xFFFA0000
31 endif 31 endif
32 32
33 ifeq ($(CONFIG_NAND_U_BOOT),y)
34 LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
35 endif
36
37 ifeq ($(CONFIG_PCIBOOT_U_BOOT),y)
38 LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
39 endif
40
41 PLATFORM_CPPFLAGS += -DCONFIG_440=1 33 PLATFORM_CPPFLAGS += -DCONFIG_440=1
42 34
43 ifeq ($(debug),1) 35 ifeq ($(debug),1)
44 PLATFORM_CPPFLAGS += -DDEBUG 36 PLATFORM_CPPFLAGS += -DDEBUG
45 endif 37 endif
46 38
47 ifeq ($(dbcr),1) 39 ifeq ($(dbcr),1)
48 PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 40 PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
49 endif 41 endif
50 42
board/amcc/kilauea/kilauea.c
Diff comments   View file @ 35fca4c
1 /* 1 /*
2 * (C) Copyright 2007 2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 #include <common.h> 24 #include <common.h>
25 #include <ppc4xx.h> 25 #include <ppc4xx.h>
26 #include <ppc405.h> 26 #include <ppc405.h>
27 #include <libfdt.h> 27 #include <libfdt.h>
28 #include <fdt_support.h> 28 #include <fdt_support.h>
29 #include <asm/processor.h> 29 #include <asm/processor.h>
30 #include <asm/io.h> 30 #include <asm/io.h>
31 31
32 #if defined(CONFIG_PCI) 32 #if defined(CONFIG_PCI)
33 #include <pci.h> 33 #include <pci.h>
34 #include <asm/4xx_pcie.h> 34 #include <asm/4xx_pcie.h>
35 #endif 35 #endif
36 36
37 DECLARE_GLOBAL_DATA_PTR; 37 DECLARE_GLOBAL_DATA_PTR;
38 38
39 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ 39 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
40 40
41 /* 41 /*
42 * Board early initialization function 42 * Board early initialization function
43 */ 43 */
44 int board_early_init_f (void) 44 int board_early_init_f (void)
45 { 45 {
46 u32 val; 46 u32 val;
47 47
48 /*--------------------------------------------------------------------+ 48 /*--------------------------------------------------------------------+
49 | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board. 49 | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
50 +--------------------------------------------------------------------+ 50 +--------------------------------------------------------------------+
51 +---------------------------------------------------------------------+ 51 +---------------------------------------------------------------------+
52 |Interrupt| Source | Pol. | Sensi.| Crit. | 52 |Interrupt| Source | Pol. | Sensi.| Crit. |
53 +---------+-----------------------------------+-------+-------+-------+ 53 +---------+-----------------------------------+-------+-------+-------+
54 | IRQ 00 | UART0 | High | Level | Non | 54 | IRQ 00 | UART0 | High | Level | Non |
55 | IRQ 01 | UART1 | High | Level | Non | 55 | IRQ 01 | UART1 | High | Level | Non |
56 | IRQ 02 | IIC0 | High | Level | Non | 56 | IRQ 02 | IIC0 | High | Level | Non |
57 | IRQ 03 | TBD | High | Level | Non | 57 | IRQ 03 | TBD | High | Level | Non |
58 | IRQ 04 | TBD | High | Level | Non | 58 | IRQ 04 | TBD | High | Level | Non |
59 | IRQ 05 | EBM | High | Level | Non | 59 | IRQ 05 | EBM | High | Level | Non |
60 | IRQ 06 | BGI | High | Level | Non | 60 | IRQ 06 | BGI | High | Level | Non |
61 | IRQ 07 | IIC1 | Rising| Edge | Non | 61 | IRQ 07 | IIC1 | Rising| Edge | Non |
62 | IRQ 08 | SPI | High | Lvl/ed| Non | 62 | IRQ 08 | SPI | High | Lvl/ed| Non |
63 | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non | 63 | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
64 | IRQ 10 | MAL TX EOB | High | Level | Non | 64 | IRQ 10 | MAL TX EOB | High | Level | Non |
65 | IRQ 11 | MAL RX EOB | High | Level | Non | 65 | IRQ 11 | MAL RX EOB | High | Level | Non |
66 | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non | 66 | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
67 | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non | 67 | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
68 | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non | 68 | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
69 | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non | 69 | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
70 | IRQ 16 | PCIE0 AL | high | Level | Non | 70 | IRQ 16 | PCIE0 AL | high | Level | Non |
71 | IRQ 17 | PCIE0 VPD access | rising| Edge | Non | 71 | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
72 | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non | 72 | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
73 | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non | 73 | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
74 | IRQ 20 | PCIE0 TCR | High | Level | Non | 74 | IRQ 20 | PCIE0 TCR | High | Level | Non |
75 | IRQ 21 | PCIE0 MSI level0 | High | Level | Non | 75 | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
76 | IRQ 22 | PCIE0 MSI level1 | High | Level | Non | 76 | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
77 | IRQ 23 | Security EIP-94 | High | Level | Non | 77 | IRQ 23 | Security EIP-94 | High | Level | Non |
78 | IRQ 24 | EMAC0 interrupt | High | Level | Non | 78 | IRQ 24 | EMAC0 interrupt | High | Level | Non |
79 | IRQ 25 | EMAC1 interrupt | High | Level | Non | 79 | IRQ 25 | EMAC1 interrupt | High | Level | Non |
80 | IRQ 26 | PCIE0 MSI level2 | High | Level | Non | 80 | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
81 | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non | 81 | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
82 | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non | 82 | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
83 | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. | 83 | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
84 | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non | 84 | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
85 | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. | 85 | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
86 |---------------------------------------------------------------------- 86 |----------------------------------------------------------------------
87 | IRQ 32 | MAL Serr | High | Level | Non | 87 | IRQ 32 | MAL Serr | High | Level | Non |
88 | IRQ 33 | MAL Txde | High | Level | Non | 88 | IRQ 33 | MAL Txde | High | Level | Non |
89 | IRQ 34 | MAL Rxde | High | Level | Non | 89 | IRQ 34 | MAL Rxde | High | Level | Non |
90 | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non | 90 | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
91 | IRQ 36 | PCIE0 DCR Error | High | Level | Non | 91 | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
92 | IRQ 37 | EBC | High |Lvl Edg| Non | 92 | IRQ 37 | EBC | High |Lvl Edg| Non |
93 | IRQ 38 | NDFC | High | Level | Non | 93 | IRQ 38 | NDFC | High | Level | Non |
94 | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non | 94 | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
95 | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non | 95 | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
96 | IRQ 41 | PCIE1 AL | high | Level | Non | 96 | IRQ 41 | PCIE1 AL | high | Level | Non |
97 | IRQ 42 | PCIE1 VPD access | rising| edge | Non | 97 | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
98 | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non | 98 | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
99 | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non | 99 | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
100 | IRQ 45 | PCIE1 TCR | High | Level | Non | 100 | IRQ 45 | PCIE1 TCR | High | Level | Non |
101 | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non | 101 | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
102 | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | 102 | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
103 | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | 103 | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
104 | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non | 104 | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
105 | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non | 105 | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
106 | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | 106 | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
107 | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non | 107 | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
108 | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non | 108 | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
109 | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non | 109 | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
110 | IRQ 55 | Serial ROM | High | Level | Non | 110 | IRQ 55 | Serial ROM | High | Level | Non |
111 | IRQ 56 | GPT Decrement Pulse | High | Level | Non | 111 | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
112 | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non | 112 | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
113 | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non | 113 | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
114 | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non | 114 | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
115 | IRQ 60 | EMAC0 Wake-up | High | Level | Non | 115 | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
116 | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non | 116 | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
117 | IRQ 62 | EMAC1 Wake-up | High | Level | Non | 117 | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
118 |---------------------------------------------------------------------- 118 |----------------------------------------------------------------------
119 | IRQ 64 | PE0 AL | High | Level | Non | 119 | IRQ 64 | PE0 AL | High | Level | Non |
120 | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | 120 | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
121 | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | 121 | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
122 | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | 122 | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
123 | IRQ 68 | PE0 TCR | High | Level | Non | 123 | IRQ 68 | PE0 TCR | High | Level | Non |
124 | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | 124 | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
125 | IRQ 70 | PE0 DCR Error | High | Level | Non | 125 | IRQ 70 | PE0 DCR Error | High | Level | Non |
126 | IRQ 71 | Reserved | N/A | N/A | Non | 126 | IRQ 71 | Reserved | N/A | N/A | Non |
127 | IRQ 72 | PE1 AL | High | Level | Non | 127 | IRQ 72 | PE1 AL | High | Level | Non |
128 | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | 128 | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
129 | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | 129 | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
130 | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | 130 | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
131 | IRQ 76 | PE1 TCR | High | Level | Non | 131 | IRQ 76 | PE1 TCR | High | Level | Non |
132 | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | 132 | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
133 | IRQ 78 | PE1 DCR Error | High | Level | Non | 133 | IRQ 78 | PE1 DCR Error | High | Level | Non |
134 | IRQ 79 | Reserved | N/A | N/A | Non | 134 | IRQ 79 | Reserved | N/A | N/A | Non |
135 | IRQ 80 | PE2 AL | High | Level | Non | 135 | IRQ 80 | PE2 AL | High | Level | Non |
136 | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | 136 | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
137 | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | 137 | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
138 | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | 138 | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
139 | IRQ 84 | PE2 TCR | High | Level | Non | 139 | IRQ 84 | PE2 TCR | High | Level | Non |
140 | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | 140 | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
141 | IRQ 86 | PE2 DCR Error | High | Level | Non | 141 | IRQ 86 | PE2 DCR Error | High | Level | Non |
142 | IRQ 87 | Reserved | N/A | N/A | Non | 142 | IRQ 87 | Reserved | N/A | N/A | Non |
143 | IRQ 88 | External IRQ(5) | Progr | Progr | Non | 143 | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
144 | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | 144 | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
145 | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | 145 | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
146 | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | 146 | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
147 | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | 147 | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
148 | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | 148 | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
149 | IRQ 94 | Reserved | N/A | N/A | Non | 149 | IRQ 94 | Reserved | N/A | N/A | Non |
150 | IRQ 95 | Reserved | N/A | N/A | Non | 150 | IRQ 95 | Reserved | N/A | N/A | Non |
151 |--------------------------------------------------------------------- 151 |---------------------------------------------------------------------
152 +---------+-----------------------------------+-------+-------+------*/ 152 +---------+-----------------------------------+-------+-------+------*/
153 /*--------------------------------------------------------------------+ 153 /*--------------------------------------------------------------------+
154 | Initialise UIC registers. Clear all interrupts. Disable all 154 | Initialise UIC registers. Clear all interrupts. Disable all
155 | interrupts. 155 | interrupts.
156 | Set critical interrupt values. Set interrupt polarities. Set 156 | Set critical interrupt values. Set interrupt polarities. Set
157 | interrupt trigger levels. Make bit 0 High priority. Clear all 157 | interrupt trigger levels. Make bit 0 High priority. Clear all
158 | interrupts again. 158 | interrupts again.
159 +-------------------------------------------------------------------*/ 159 +-------------------------------------------------------------------*/
160 160
161 mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ 161 mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
162 mtdcr (uic2er, 0x00000000); /* disable all interrupts */ 162 mtdcr (uic2er, 0x00000000); /* disable all interrupts */
163 mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */ 163 mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
164 mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */ 164 mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
165 mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */ 165 mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
166 mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ 166 mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
167 mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ 167 mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
168 mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ 168 mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
169 169
170 mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */ 170 mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
171 mtdcr (uic1er, 0x00000000); /* disable all interrupts */ 171 mtdcr (uic1er, 0x00000000); /* disable all interrupts */
172 mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */ 172 mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
173 mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */ 173 mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
174 mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */ 174 mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
175 mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ 175 mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
176 mtdcr (uic1sr, 0x00000000); /* clear all interrupts */ 176 mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
177 mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */ 177 mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
178 178
179 mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ 179 mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
180 mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */ 180 mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
181 /* Except cascade UIC0 and UIC1 */ 181 /* Except cascade UIC0 and UIC1 */
182 mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */ 182 mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
183 mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */ 183 mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
184 mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */ 184 mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
185 mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ 185 mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
186 mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ 186 mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
187 mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ 187 mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
188 188
189 /* 189 /*
190 * Note: Some cores are still in reset when the chip starts, so 190 * Note: Some cores are still in reset when the chip starts, so
191 * take them out of reset 191 * take them out of reset
192 */ 192 */
193 mtsdr(SDR0_SRST, 0); 193 mtsdr(SDR0_SRST, 0);
194 194
195 /* Configure 405EX for NAND usage */ 195 /* Configure 405EX for NAND usage */
196 val = SDR0_CUST0_MUX_NDFC_SEL | 196 val = SDR0_CUST0_MUX_NDFC_SEL |
197 SDR0_CUST0_NDFC_ENABLE | 197 SDR0_CUST0_NDFC_ENABLE |
198 SDR0_CUST0_NDFC_BW_8_BIT | 198 SDR0_CUST0_NDFC_BW_8_BIT |
199 SDR0_CUST0_NRB_BUSY | 199 SDR0_CUST0_NRB_BUSY |
200 (0x80000000 >> (28 + CFG_NAND_CS)); 200 (0x80000000 >> (28 + CFG_NAND_CS));
201 mtsdr(SDR0_CUST0, val); 201 mtsdr(SDR0_CUST0, val);
202 202
203 /* 203 /*
204 * Configure PFC (Pin Function Control) registers 204 * Configure PFC (Pin Function Control) registers
205 * -> Enable USB 205 * -> Enable USB
206 */ 206 */
207 val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ; 207 val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
208 mtsdr(SDR0_PFC1, val); 208 mtsdr(SDR0_PFC1, val);
209 209
210 /* 210 /*
211 * Configure FPGA register with PCIe reset 211 * Configure FPGA register with PCIe reset
212 */ 212 */
213 out_be32((void *)CFG_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */ 213 out_be32((void *)CFG_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */
214 mdelay(50); 214 mdelay(50);
215 out_be32((void *)CFG_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */ 215 out_be32((void *)CFG_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */
216 216
217 return 0; 217 return 0;
218 } 218 }
219 219
220 int misc_init_r(void) 220 int misc_init_r(void)
221 { 221 {
222 #ifdef CFG_ENV_IS_IN_FLASH 222 #ifdef CFG_ENV_IS_IN_FLASH
223 /* Monitor protection ON by default */ 223 /* Monitor protection ON by default */
224 flash_protect(FLAG_PROTECT_SET, 224 flash_protect(FLAG_PROTECT_SET,
225 -CFG_MONITOR_LEN, 225 -CFG_MONITOR_LEN,
226 0xffffffff, 226 0xffffffff,
227 &flash_info[0]); 227 &flash_info[0]);
228 #endif 228 #endif
229 229
230 return 0; 230 return 0;
231 } 231 }
232 232
233 int board_emac_count(void) 233 static int is_405exr(void)
234 { 234 {
235 u32 pvr = get_pvr(); 235 u32 pvr = get_pvr();
236 236
237 if (pvr & 0x00000004)
238 return 0; /* bit 2 set -> 405EX */
239
240 return 1; /* bit 2 cleared -> 405EXr */
241 }
242
243 int board_emac_count(void)
244 {
237 /* 245 /*
238 * 405EXr only has one EMAC interface, 405EX has two 246 * 405EXr only has one EMAC interface, 405EX has two
239 */ 247 */
240 if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA)) 248 if (is_405exr())
241 return 1; 249 return 1;
242 else 250 else
243 return 2; 251 return 2;
244 } 252 }
245 253
246 static int board_pcie_count(void) 254 static int board_pcie_count(void)
247 { 255 {
248 u32 pvr = get_pvr();
249
250 /* 256 /*
251 * 405EXr only has one EMAC interface, 405EX has two 257 * 405EXr only has one EMAC interface, 405EX has two
252 */ 258 */
253 if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA)) 259 if (is_405exr())
254 return 1; 260 return 1;
255 else 261 else
256 return 2; 262 return 2;
257 } 263 }
258 264
259 int checkboard (void) 265 int checkboard (void)
260 { 266 {
261 char *s = getenv("serial#"); 267 char *s = getenv("serial#");
262 u32 pvr = get_pvr();
263 268
264 if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA)) 269 if (is_405exr())
265 printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board"); 270 printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board");
266 else 271 else
267 printf("Board: Kilauea - AMCC PPC405EX Evaluation Board"); 272 printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
268 273
269 if (s != NULL) { 274 if (s != NULL) {
270 puts(", serial# "); 275 puts(", serial# ");
271 puts(s); 276 puts(s);
272 } 277 }
273 putc('\n'); 278 putc('\n');
274 279
275 return (0); 280 return (0);
276 } 281 }
277 282
278 /************************************************************************* 283 /*************************************************************************
279 * pci_pre_init 284 * pci_pre_init
280 * 285 *
281 * This routine is called just prior to registering the hose and gives 286 * This routine is called just prior to registering the hose and gives
282 * the board the opportunity to check things. Returning a value of zero 287 * the board the opportunity to check things. Returning a value of zero
283 * indicates that things are bad & PCI initialization should be aborted. 288 * indicates that things are bad & PCI initialization should be aborted.
284 * 289 *
285 * Different boards may wish to customize the pci controller structure 290 * Different boards may wish to customize the pci controller structure
286 * (add regions, override default access routines, etc) or perform 291 * (add regions, override default access routines, etc) or perform
287 * certain pre-initialization actions. 292 * certain pre-initialization actions.
288 * 293 *
289 ************************************************************************/ 294 ************************************************************************/
290 #if defined(CONFIG_PCI) 295 #if defined(CONFIG_PCI)
291 int pci_pre_init(struct pci_controller * hose ) 296 int pci_pre_init(struct pci_controller * hose )
292 { 297 {
293 return 0; 298 return 0;
294 } 299 }
295 #endif /* defined(CONFIG_PCI) */ 300 #endif /* defined(CONFIG_PCI) */
296 301
297 #ifdef CONFIG_PCI 302 #ifdef CONFIG_PCI
298 static struct pci_controller pcie_hose[2] = {{0},{0}}; 303 static struct pci_controller pcie_hose[2] = {{0},{0}};
299 304
300 void pcie_setup_hoses(int busno) 305 void pcie_setup_hoses(int busno)
301 { 306 {
302 struct pci_controller *hose; 307 struct pci_controller *hose;
303 int i, bus; 308 int i, bus;
304 int ret = 0; 309 int ret = 0;
305 bus = busno; 310 bus = busno;
306 char *env; 311 char *env;
307 unsigned int delay; 312 unsigned int delay;
308 313
309 for (i = 0; i < board_pcie_count(); i++) { 314 for (i = 0; i < board_pcie_count(); i++) {
310 315
311 if (is_end_point(i)) 316 if (is_end_point(i))
312 ret = ppc4xx_init_pcie_endport(i); 317 ret = ppc4xx_init_pcie_endport(i);
313 else 318 else
314 ret = ppc4xx_init_pcie_rootport(i); 319 ret = ppc4xx_init_pcie_rootport(i);
315 if (ret) { 320 if (ret) {
316 printf("PCIE%d: initialization as %s failed\n", i, 321 printf("PCIE%d: initialization as %s failed\n", i,
317 is_end_point(i) ? "endpoint" : "root-complex"); 322 is_end_point(i) ? "endpoint" : "root-complex");
318 continue; 323 continue;
319 } 324 }
320 325
321 hose = &pcie_hose[i]; 326 hose = &pcie_hose[i];
322 hose->first_busno = bus; 327 hose->first_busno = bus;
323 hose->last_busno = bus; 328 hose->last_busno = bus;
324 hose->current_busno = bus; 329 hose->current_busno = bus;
325 330
326 /* setup mem resource */ 331 /* setup mem resource */
327 pci_set_region(hose->regions + 0, 332 pci_set_region(hose->regions + 0,
328 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, 333 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
329 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, 334 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
330 CFG_PCIE_MEMSIZE, 335 CFG_PCIE_MEMSIZE,
331 PCI_REGION_MEM); 336 PCI_REGION_MEM);
332 hose->region_count = 1; 337 hose->region_count = 1;
333 pci_register_hose(hose); 338 pci_register_hose(hose);
334 339
335 if (is_end_point(i)) { 340 if (is_end_point(i)) {
336 ppc4xx_setup_pcie_endpoint(hose, i); 341 ppc4xx_setup_pcie_endpoint(hose, i);
337 /* 342 /*
338 * Reson for no scanning is endpoint can not generate 343 * Reson for no scanning is endpoint can not generate
339 * upstream configuration accesses. 344 * upstream configuration accesses.
340 */ 345 */
341 } else { 346 } else {
342 ppc4xx_setup_pcie_rootpoint(hose, i); 347 ppc4xx_setup_pcie_rootpoint(hose, i);
343 env = getenv ("pciscandelay"); 348 env = getenv ("pciscandelay");
344 if (env != NULL) { 349 if (env != NULL) {
345 delay = simple_strtoul(env, NULL, 10); 350 delay = simple_strtoul(env, NULL, 10);
346 if (delay > 5) 351 if (delay > 5)
347 printf("Warning, expect noticable delay before " 352 printf("Warning, expect noticable delay before "
348 "PCIe scan due to 'pciscandelay' value!\n"); 353 "PCIe scan due to 'pciscandelay' value!\n");
349 mdelay(delay * 1000); 354 mdelay(delay * 1000);
350 } 355 }
351 356
352 /* 357 /*
353 * Config access can only go down stream 358 * Config access can only go down stream
354 */ 359 */
355 hose->last_busno = pci_hose_scan(hose); 360 hose->last_busno = pci_hose_scan(hose);
356 bus = hose->last_busno + 1; 361 bus = hose->last_busno + 1;
357 } 362 }
358 } 363 }
359 } 364 }
360 #endif 365 #endif
361 366
362 #if defined(CONFIG_POST) 367 #if defined(CONFIG_POST)
363 /* 368 /*
364 * Returns 1 if keys pressed to start the power-on long-running tests 369 * Returns 1 if keys pressed to start the power-on long-running tests
365 * Called from board_init_f(). 370 * Called from board_init_f().
366 */ 371 */
367 int post_hotkeys_pressed(void) 372 int post_hotkeys_pressed(void)
368 { 373 {
369 return 0; /* No hotkeys supported */ 374 return 0; /* No hotkeys supported */
370 } 375 }
371 #endif /* CONFIG_POST */ 376 #endif /* CONFIG_POST */
372 377
373 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 378 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
374 void ft_board_setup(void *blob, bd_t *bd) 379 void ft_board_setup(void *blob, bd_t *bd)
375 { 380 {
376 u32 val[4]; 381 u32 val[4];
377 int rc; 382 int rc;
378 383
379 ft_cpu_setup(blob, bd); 384 ft_cpu_setup(blob, bd);
380 385
381 /* Fixup NOR mapping */ 386 /* Fixup NOR mapping */
382 val[0] = 0; /* chip select number */ 387 val[0] = 0; /* chip select number */
383 val[1] = 0; /* always 0 */ 388 val[1] = 0; /* always 0 */
384 val[2] = gd->bd->bi_flashstart; 389 val[2] = gd->bd->bi_flashstart;
385 val[3] = gd->bd->bi_flashsize; 390 val[3] = gd->bd->bi_flashsize;
386 rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", 391 rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
387 val, sizeof(val), 1); 392 val, sizeof(val), 1);
388 if (rc) 393 if (rc)
389 printf("Unable to update property NOR mapping, err=%s\n", 394 printf("Unable to update property NOR mapping, err=%s\n",
390 fdt_strerror(rc)); 395 fdt_strerror(rc));
1 /* 1 /*
2 * (C) Copyright 2000-2007 2 * (C) Copyright 2000-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 /* 24 /*
25 * CPU specific code 25 * CPU specific code
26 * 26 *
27 * written or collected and sometimes rewritten by 27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com> 28 * Magnus Damm <damm@bitsmart.com>
29 * 29 *
30 * minor modifications by 30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de> 31 * Wolfgang Denk <wd@denx.de>
32 */ 32 */
33 33
34 #include <common.h> 34 #include <common.h>
35 #include <watchdog.h> 35 #include <watchdog.h>
36 #include <command.h> 36 #include <command.h>
37 #include <asm/cache.h> 37 #include <asm/cache.h>
38 #include <ppc4xx.h> 38 #include <ppc4xx.h>
39 39
40 DECLARE_GLOBAL_DATA_PTR; 40 DECLARE_GLOBAL_DATA_PTR;
41 41
42 void board_reset(void); 42 void board_reset(void);
43 43
44 #if defined(CONFIG_405GP) || \ 44 #if defined(CONFIG_405GP) || \
45 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ 45 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
46 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) 46 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
47 47
48 #define PCI_ASYNC 48 #define PCI_ASYNC
49 49
50 static int pci_async_enabled(void) 50 static int pci_async_enabled(void)
51 { 51 {
52 #if defined(CONFIG_405GP) 52 #if defined(CONFIG_405GP)
53 return (mfdcr(strap) & PSR_PCI_ASYNC_EN); 53 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
54 #endif 54 #endif
55 55
56 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ 56 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
57 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 57 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
58 defined(CONFIG_460EX) || defined(CONFIG_460GT) 58 defined(CONFIG_460EX) || defined(CONFIG_460GT)
59 unsigned long val; 59 unsigned long val;
60 60
61 mfsdr(sdr_sdstp1, val); 61 mfsdr(sdr_sdstp1, val);
62 return (val & SDR0_SDSTP1_PAME_MASK); 62 return (val & SDR0_SDSTP1_PAME_MASK);
63 #endif 63 #endif
64 } 64 }
65 #endif 65 #endif
66 66
67 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \ 67 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
68 !defined(CONFIG_405) && !defined(CONFIG_405EX) 68 !defined(CONFIG_405) && !defined(CONFIG_405EX)
69 static int pci_arbiter_enabled(void) 69 static int pci_arbiter_enabled(void)
70 { 70 {
71 #if defined(CONFIG_405GP) 71 #if defined(CONFIG_405GP)
72 return (mfdcr(strap) & PSR_PCI_ARBIT_EN); 72 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
73 #endif 73 #endif
74 74
75 #if defined(CONFIG_405EP) 75 #if defined(CONFIG_405EP)
76 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN); 76 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
77 #endif 77 #endif
78 78
79 #if defined(CONFIG_440GP) 79 #if defined(CONFIG_440GP)
80 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK); 80 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
81 #endif 81 #endif
82 82
83 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) 83 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
84 unsigned long val; 84 unsigned long val;
85 85
86 mfsdr(sdr_xcr, val); 86 mfsdr(sdr_xcr, val);
87 return (val & 0x80000000); 87 return (val & 0x80000000);
88 #endif 88 #endif
89 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ 89 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
90 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 90 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
91 defined(CONFIG_460EX) || defined(CONFIG_460GT) 91 defined(CONFIG_460EX) || defined(CONFIG_460GT)
92 unsigned long val; 92 unsigned long val;
93 93
94 mfsdr(sdr_pci0, val); 94 mfsdr(sdr_pci0, val);
95 return (val & 0x80000000); 95 return (val & 0x80000000);
96 #endif 96 #endif
97 } 97 }
98 #endif 98 #endif
99 99
100 #if defined(CONFIG_405EP) 100 #if defined(CONFIG_405EP)
101 #define I2C_BOOTROM 101 #define I2C_BOOTROM
102 102
103 static int i2c_bootrom_enabled(void) 103 static int i2c_bootrom_enabled(void)
104 { 104 {
105 #if defined(CONFIG_405EP) 105 #if defined(CONFIG_405EP)
106 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP); 106 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
107 #else 107 #else
108 unsigned long val; 108 unsigned long val;
109 109
110 mfsdr(sdr_sdcs, val); 110 mfsdr(sdr_sdcs, val);
111 return (val & SDR0_SDCS_SDD); 111 return (val & SDR0_SDCS_SDD);
112 #endif 112 #endif
113 } 113 }
114 #endif 114 #endif
115 115
116 #if defined(CONFIG_440GX) 116 #if defined(CONFIG_440GX)
117 #define SDR0_PINSTP_SHIFT 29 117 #define SDR0_PINSTP_SHIFT 29
118 static char *bootstrap_str[] = { 118 static char *bootstrap_str[] = {
119 "EBC (16 bits)", 119 "EBC (16 bits)",
120 "EBC (8 bits)", 120 "EBC (8 bits)",
121 "EBC (32 bits)", 121 "EBC (32 bits)",
122 "EBC (8 bits)", 122 "EBC (8 bits)",
123 "PCI", 123 "PCI",
124 "I2C (Addr 0x54)", 124 "I2C (Addr 0x54)",
125 "Reserved", 125 "Reserved",
126 "I2C (Addr 0x50)", 126 "I2C (Addr 0x50)",
127 }; 127 };
128 static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' }; 128 static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
129 #endif 129 #endif
130 130
131 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) 131 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
132 #define SDR0_PINSTP_SHIFT 30 132 #define SDR0_PINSTP_SHIFT 30
133 static char *bootstrap_str[] = { 133 static char *bootstrap_str[] = {
134 "EBC (8 bits)", 134 "EBC (8 bits)",
135 "PCI", 135 "PCI",
136 "I2C (Addr 0x54)", 136 "I2C (Addr 0x54)",
137 "I2C (Addr 0x50)", 137 "I2C (Addr 0x50)",
138 }; 138 };
139 static char bootstrap_char[] = { 'A', 'B', 'C', 'D'}; 139 static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
140 #endif 140 #endif
141 141
142 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) 142 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
143 #define SDR0_PINSTP_SHIFT 29 143 #define SDR0_PINSTP_SHIFT 29
144 static char *bootstrap_str[] = { 144 static char *bootstrap_str[] = {
145 "EBC (8 bits)", 145 "EBC (8 bits)",
146 "PCI", 146 "PCI",
147 "NAND (8 bits)", 147 "NAND (8 bits)",
148 "EBC (16 bits)", 148 "EBC (16 bits)",
149 "EBC (16 bits)", 149 "EBC (16 bits)",
150 "I2C (Addr 0x54)", 150 "I2C (Addr 0x54)",
151 "PCI", 151 "PCI",
152 "I2C (Addr 0x52)", 152 "I2C (Addr 0x52)",
153 }; 153 };
154 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; 154 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
155 #endif 155 #endif
156 156
157 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) 157 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
158 #define SDR0_PINSTP_SHIFT 29 158 #define SDR0_PINSTP_SHIFT 29
159 static char *bootstrap_str[] = { 159 static char *bootstrap_str[] = {
160 "EBC (8 bits)", 160 "EBC (8 bits)",
161 "EBC (16 bits)", 161 "EBC (16 bits)",
162 "EBC (16 bits)", 162 "EBC (16 bits)",
163 "NAND (8 bits)", 163 "NAND (8 bits)",
164 "PCI", 164 "PCI",
165 "I2C (Addr 0x54)", 165 "I2C (Addr 0x54)",
166 "PCI", 166 "PCI",
167 "I2C (Addr 0x52)", 167 "I2C (Addr 0x52)",
168 }; 168 };
169 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; 169 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
170 #endif 170 #endif
171 171
172 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) 172 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
173 #define SDR0_PINSTP_SHIFT 29 173 #define SDR0_PINSTP_SHIFT 29
174 static char *bootstrap_str[] = { 174 static char *bootstrap_str[] = {
175 "EBC (8 bits)", 175 "EBC (8 bits)",
176 "EBC (16 bits)", 176 "EBC (16 bits)",
177 "PCI", 177 "PCI",
178 "PCI", 178 "PCI",
179 "EBC (16 bits)", 179 "EBC (16 bits)",
180 "NAND (8 bits)", 180 "NAND (8 bits)",
181 "I2C (Addr 0x54)", /* A8 */ 181 "I2C (Addr 0x54)", /* A8 */
182 "I2C (Addr 0x52)", /* A4 */ 182 "I2C (Addr 0x52)", /* A4 */
183 }; 183 };
184 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; 184 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
185 #endif 185 #endif
186 186
187 #if defined(CONFIG_405EZ) 187 #if defined(CONFIG_405EZ)
188 #define SDR0_PINSTP_SHIFT 28 188 #define SDR0_PINSTP_SHIFT 28
189 static char *bootstrap_str[] = { 189 static char *bootstrap_str[] = {
190 "EBC (8 bits)", 190 "EBC (8 bits)",
191 "SPI (fast)", 191 "SPI (fast)",
192 "NAND (512 page, 4 addr cycle)", 192 "NAND (512 page, 4 addr cycle)",
193 "I2C (Addr 0x50)", 193 "I2C (Addr 0x50)",
194 "EBC (32 bits)", 194 "EBC (32 bits)",
195 "I2C (Addr 0x50)", 195 "I2C (Addr 0x50)",
196 "NAND (2K page, 5 addr cycle)", 196 "NAND (2K page, 5 addr cycle)",
197 "I2C (Addr 0x50)", 197 "I2C (Addr 0x50)",
198 "EBC (16 bits)", 198 "EBC (16 bits)",
199 "Reserved", 199 "Reserved",
200 "NAND (2K page, 4 addr cycle)", 200 "NAND (2K page, 4 addr cycle)",
201 "I2C (Addr 0x50)", 201 "I2C (Addr 0x50)",
202 "NAND (512 page, 3 addr cycle)", 202 "NAND (512 page, 3 addr cycle)",
203 "I2C (Addr 0x50)", 203 "I2C (Addr 0x50)",
204 "SPI (slow)", 204 "SPI (slow)",
205 "I2C (Addr 0x50)", 205 "I2C (Addr 0x50)",
206 }; 206 };
207 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \ 207 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
208 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' }; 208 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
209 #endif 209 #endif
210 210
211 #if defined(CONFIG_405EX) 211 #if defined(CONFIG_405EX)
212 #define SDR0_PINSTP_SHIFT 29 212 #define SDR0_PINSTP_SHIFT 29
213 static char *bootstrap_str[] = { 213 static char *bootstrap_str[] = {
214 "EBC (8 bits)", 214 "EBC (8 bits)",
215 "EBC (16 bits)", 215 "EBC (16 bits)",
216 "EBC (16 bits)", 216 "EBC (16 bits)",
217 "NAND (8 bits)", 217 "NAND (8 bits)",
218 "NAND (8 bits)", 218 "NAND (8 bits)",
219 "I2C (Addr 0x54)", 219 "I2C (Addr 0x54)",
220 "EBC (8 bits)", 220 "EBC (8 bits)",
221 "I2C (Addr 0x52)", 221 "I2C (Addr 0x52)",
222 }; 222 };
223 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; 223 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
224 #endif 224 #endif
225 225
226 #if defined(SDR0_PINSTP_SHIFT) 226 #if defined(SDR0_PINSTP_SHIFT)
227 static int bootstrap_option(void) 227 static int bootstrap_option(void)
228 { 228 {
229 unsigned long val; 229 unsigned long val;
230 230
231 mfsdr(SDR_PINSTP, val); 231 mfsdr(SDR_PINSTP, val);
232 return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT); 232 return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
233 } 233 }
234 #endif /* SDR0_PINSTP_SHIFT */ 234 #endif /* SDR0_PINSTP_SHIFT */
235 235
236 236
237 #if defined(CONFIG_440) 237 #if defined(CONFIG_440)
238 static int do_chip_reset (unsigned long sys0, unsigned long sys1) 238 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
239 { 239 {
240 /* Changes to cpc0_sys0 and cpc0_sys1 require chip 240 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
241 * reset. 241 * reset.
242 */ 242 */
243 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */ 243 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
244 mtdcr (cpc0_sys0, sys0); 244 mtdcr (cpc0_sys0, sys0);
245 mtdcr (cpc0_sys1, sys1); 245 mtdcr (cpc0_sys1, sys1);
246 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */ 246 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
247 mtspr (dbcr0, 0x20000000); /* Reset the chip */ 247 mtspr (dbcr0, 0x20000000); /* Reset the chip */
248 248
249 return 1; 249 return 1;
250 } 250 }
251 #endif 251 #endif
252 252
253 253
254 int checkcpu (void) 254 int checkcpu (void)
255 { 255 {
256 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */ 256 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
257 uint pvr = get_pvr(); 257 uint pvr = get_pvr();
258 ulong clock = gd->cpu_clk; 258 ulong clock = gd->cpu_clk;
259 char buf[32]; 259 char buf[32];
260 260
261 #if !defined(CONFIG_IOP480) 261 #if !defined(CONFIG_IOP480)
262 char addstr[64] = ""; 262 char addstr[64] = "";
263 sys_info_t sys_info; 263 sys_info_t sys_info;
264 264
265 puts ("CPU: "); 265 puts ("CPU: ");
266 266
267 get_sys_info(&sys_info); 267 get_sys_info(&sys_info);
268 268
269 puts("AMCC PowerPC 4"); 269 puts("AMCC PowerPC 4");
270 270
271 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ 271 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
272 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ 272 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
273 defined(CONFIG_405EX) 273 defined(CONFIG_405EX)
274 puts("05"); 274 puts("05");
275 #endif 275 #endif
276 #if defined(CONFIG_440) 276 #if defined(CONFIG_440)
277 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) 277 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
278 puts("60"); 278 puts("60");
279 #else 279 #else
280 puts("40"); 280 puts("40");
281 #endif 281 #endif
282 #endif 282 #endif
283 283
284 switch (pvr) { 284 switch (pvr) {
285 case PVR_405GP_RB: 285 case PVR_405GP_RB:
286 puts("GP Rev. B"); 286 puts("GP Rev. B");
287 break; 287 break;
288 288
289 case PVR_405GP_RC: 289 case PVR_405GP_RC:
290 puts("GP Rev. C"); 290 puts("GP Rev. C");
291 break; 291 break;
292 292
293 case PVR_405GP_RD: 293 case PVR_405GP_RD:
294 puts("GP Rev. D"); 294 puts("GP Rev. D");
295 break; 295 break;
296 296
297 #ifdef CONFIG_405GP 297 #ifdef CONFIG_405GP
298 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */ 298 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
299 puts("GP Rev. E"); 299 puts("GP Rev. E");
300 break; 300 break;
301 #endif 301 #endif
302 302
303 case PVR_405CR_RA: 303 case PVR_405CR_RA:
304 puts("CR Rev. A"); 304 puts("CR Rev. A");
305 break; 305 break;
306 306
307 case PVR_405CR_RB: 307 case PVR_405CR_RB:
308 puts("CR Rev. B"); 308 puts("CR Rev. B");
309 break; 309 break;
310 310
311 #ifdef CONFIG_405CR 311 #ifdef CONFIG_405CR
312 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */ 312 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
313 puts("CR Rev. C"); 313 puts("CR Rev. C");
314 break; 314 break;
315 #endif 315 #endif
316 316
317 case PVR_405GPR_RB: 317 case PVR_405GPR_RB:
318 puts("GPr Rev. B"); 318 puts("GPr Rev. B");
319 break; 319 break;
320 320
321 case PVR_405EP_RB: 321 case PVR_405EP_RB:
322 puts("EP Rev. B"); 322 puts("EP Rev. B");
323 break; 323 break;
324 324
325 case PVR_405EZ_RA: 325 case PVR_405EZ_RA:
326 puts("EZ Rev. A"); 326 puts("EZ Rev. A");
327 break; 327 break;
328 328
329 case PVR_405EX1_RA: 329 case PVR_405EX1_RA:
330 puts("EX Rev. A"); 330 puts("EX Rev. A");
331 strcpy(addstr, "Security support"); 331 strcpy(addstr, "Security support");
332 break; 332 break;
333 333
334 case PVR_405EX2_RA: 334 case PVR_405EX2_RA:
335 puts("EX Rev. A"); 335 puts("EX Rev. A");
336 strcpy(addstr, "No Security support"); 336 strcpy(addstr, "No Security support");
337 break; 337 break;
338 338
339 case PVR_405EXR1_RA: 339 case PVR_405EXR1_RA:
340 puts("EXr Rev. A"); 340 puts("EXr Rev. A");
341 strcpy(addstr, "Security support"); 341 strcpy(addstr, "Security support");
342 break; 342 break;
343 343
344 case PVR_405EXR2_RA: 344 case PVR_405EXR2_RA:
345 puts("EXr Rev. A"); 345 puts("EXr Rev. A");
346 strcpy(addstr, "No Security support"); 346 strcpy(addstr, "No Security support");
347 break; 347 break;
348 348
349 case PVR_405EX1_RC:
350 puts("EX Rev. C");
351 strcpy(addstr, "Security support");
352 break;
353
354 case PVR_405EX2_RC:
355 puts("EX Rev. C");
356 strcpy(addstr, "No Security support");
357 break;
358
359 case PVR_405EXR1_RC:
360 puts("EXr Rev. C");
361 strcpy(addstr, "Security support");
362 break;
363
364 case PVR_405EXR2_RC:
365 puts("EXr Rev. C");
366 strcpy(addstr, "No Security support");
367 break;
368
349 #if defined(CONFIG_440) 369 #if defined(CONFIG_440)
350 case PVR_440GP_RB: 370 case PVR_440GP_RB:
351 puts("GP Rev. B"); 371 puts("GP Rev. B");
352 /* See errata 1.12: CHIP_4 */ 372 /* See errata 1.12: CHIP_4 */
353 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) || 373 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
354 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){ 374 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
355 puts ( "\n\t CPC0_SYSx DCRs corrupted. " 375 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
356 "Resetting chip ...\n"); 376 "Resetting chip ...\n");
357 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */ 377 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
358 do_chip_reset ( mfdcr(cpc0_strp0), 378 do_chip_reset ( mfdcr(cpc0_strp0),
359 mfdcr(cpc0_strp1) ); 379 mfdcr(cpc0_strp1) );
360 } 380 }
361 break; 381 break;
362 382
363 case PVR_440GP_RC: 383 case PVR_440GP_RC:
364 puts("GP Rev. C"); 384 puts("GP Rev. C");
365 break; 385 break;
366 386
367 case PVR_440GX_RA: 387 case PVR_440GX_RA:
368 puts("GX Rev. A"); 388 puts("GX Rev. A");
369 break; 389 break;
370 390
371 case PVR_440GX_RB: 391 case PVR_440GX_RB:
372 puts("GX Rev. B"); 392 puts("GX Rev. B");
373 break; 393 break;
374 394
375 case PVR_440GX_RC: 395 case PVR_440GX_RC:
376 puts("GX Rev. C"); 396 puts("GX Rev. C");
377 break; 397 break;
378 398
379 case PVR_440GX_RF: 399 case PVR_440GX_RF:
380 puts("GX Rev. F"); 400 puts("GX Rev. F");
381 break; 401 break;
382 402
383 case PVR_440EP_RA: 403 case PVR_440EP_RA:
384 puts("EP Rev. A"); 404 puts("EP Rev. A");
385 break; 405 break;
386 406
387 #ifdef CONFIG_440EP 407 #ifdef CONFIG_440EP
388 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */ 408 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
389 puts("EP Rev. B"); 409 puts("EP Rev. B");
390 break; 410 break;
391 411
392 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */ 412 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
393 puts("EP Rev. C"); 413 puts("EP Rev. C");
394 break; 414 break;
395 #endif /* CONFIG_440EP */ 415 #endif /* CONFIG_440EP */
396 416
397 #ifdef CONFIG_440GR 417 #ifdef CONFIG_440GR
398 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */ 418 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
399 puts("GR Rev. A"); 419 puts("GR Rev. A");
400 break; 420 break;
401 421
402 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */ 422 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
403 puts("GR Rev. B"); 423 puts("GR Rev. B");
404 break; 424 break;
405 #endif /* CONFIG_440GR */ 425 #endif /* CONFIG_440GR */
406 #endif /* CONFIG_440 */ 426 #endif /* CONFIG_440 */
407 427
408 #ifdef CONFIG_440EPX 428 #ifdef CONFIG_440EPX
409 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ 429 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
410 puts("EPx Rev. A"); 430 puts("EPx Rev. A");
411 strcpy(addstr, "Security/Kasumi support"); 431 strcpy(addstr, "Security/Kasumi support");
412 break; 432 break;
413 433
414 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ 434 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
415 puts("EPx Rev. A"); 435 puts("EPx Rev. A");
416 strcpy(addstr, "No Security/Kasumi support"); 436 strcpy(addstr, "No Security/Kasumi support");
417 break; 437 break;
418 #endif /* CONFIG_440EPX */ 438 #endif /* CONFIG_440EPX */
419 439
420 #ifdef CONFIG_440GRX 440 #ifdef CONFIG_440GRX
421 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ 441 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
422 puts("GRx Rev. A"); 442 puts("GRx Rev. A");
423 strcpy(addstr, "Security/Kasumi support"); 443 strcpy(addstr, "Security/Kasumi support");
424 break; 444 break;
425 445
426 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ 446 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
427 puts("GRx Rev. A"); 447 puts("GRx Rev. A");
428 strcpy(addstr, "No Security/Kasumi support"); 448 strcpy(addstr, "No Security/Kasumi support");
429 break; 449 break;
430 #endif /* CONFIG_440GRX */ 450 #endif /* CONFIG_440GRX */
431 451
432 case PVR_440SP_6_RAB: 452 case PVR_440SP_6_RAB:
433 puts("SP Rev. A/B"); 453 puts("SP Rev. A/B");
434 strcpy(addstr, "RAID 6 support"); 454 strcpy(addstr, "RAID 6 support");
435 break; 455 break;
436 456
437 case PVR_440SP_RAB: 457 case PVR_440SP_RAB:
438 puts("SP Rev. A/B"); 458 puts("SP Rev. A/B");
439 strcpy(addstr, "No RAID 6 support"); 459 strcpy(addstr, "No RAID 6 support");
440 break; 460 break;
441 461
442 case PVR_440SP_6_RC: 462 case PVR_440SP_6_RC:
443 puts("SP Rev. C"); 463 puts("SP Rev. C");
444 strcpy(addstr, "RAID 6 support"); 464 strcpy(addstr, "RAID 6 support");
445 break; 465 break;
446 466
447 case PVR_440SP_RC: 467 case PVR_440SP_RC:
448 puts("SP Rev. C"); 468 puts("SP Rev. C");
449 strcpy(addstr, "No RAID 6 support"); 469 strcpy(addstr, "No RAID 6 support");
450 break; 470 break;
451 471
452 case PVR_440SPe_6_RA: 472 case PVR_440SPe_6_RA:
453 puts("SPe Rev. A"); 473 puts("SPe Rev. A");
454 strcpy(addstr, "RAID 6 support"); 474 strcpy(addstr, "RAID 6 support");
455 break; 475 break;
456 476
457 case PVR_440SPe_RA: 477 case PVR_440SPe_RA:
458 puts("SPe Rev. A"); 478 puts("SPe Rev. A");
459 strcpy(addstr, "No RAID 6 support"); 479 strcpy(addstr, "No RAID 6 support");
460 break; 480 break;
461 481
462 case PVR_440SPe_6_RB: 482 case PVR_440SPe_6_RB:
463 puts("SPe Rev. B"); 483 puts("SPe Rev. B");
464 strcpy(addstr, "RAID 6 support"); 484 strcpy(addstr, "RAID 6 support");
465 break; 485 break;
466 486
467 case PVR_440SPe_RB: 487 case PVR_440SPe_RB:
468 puts("SPe Rev. B"); 488 puts("SPe Rev. B");
469 strcpy(addstr, "No RAID 6 support"); 489 strcpy(addstr, "No RAID 6 support");
470 break; 490 break;
471 491
472 case PVR_460EX_RA: 492 case PVR_460EX_RA:
473 puts("EX Rev. A"); 493 puts("EX Rev. A");
474 strcpy(addstr, "No Security/Kasumi support"); 494 strcpy(addstr, "No Security/Kasumi support");
475 break; 495 break;
476 496
477 case PVR_460EX_SE_RA: 497 case PVR_460EX_SE_RA:
478 puts("EX Rev. A"); 498 puts("EX Rev. A");
479 strcpy(addstr, "Security/Kasumi support"); 499 strcpy(addstr, "Security/Kasumi support");
480 break; 500 break;
481 501
482 case PVR_460GT_RA: 502 case PVR_460GT_RA:
483 puts("GT Rev. A"); 503 puts("GT Rev. A");
484 strcpy(addstr, "No Security/Kasumi support"); 504 strcpy(addstr, "No Security/Kasumi support");
485 break; 505 break;
486 506
487 case PVR_460GT_SE_RA: 507 case PVR_460GT_SE_RA:
488 puts("GT Rev. A"); 508 puts("GT Rev. A");
489 strcpy(addstr, "Security/Kasumi support"); 509 strcpy(addstr, "Security/Kasumi support");
490 break; 510 break;
491 511
492 default: 512 default:
493 printf (" UNKNOWN (PVR=%08x)", pvr); 513 printf (" UNKNOWN (PVR=%08x)", pvr);
494 break; 514 break;
495 } 515 }
496 516
497 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), 517 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
498 sys_info.freqPLB / 1000000, 518 sys_info.freqPLB / 1000000,
499 get_OPB_freq() / 1000000, 519 get_OPB_freq() / 1000000,
500 sys_info.freqEBC / 1000000); 520 sys_info.freqEBC / 1000000);
501 521
502 if (addstr[0] != 0) 522 if (addstr[0] != 0)
503 printf(" %s\n", addstr); 523 printf(" %s\n", addstr);
504 524
505 #if defined(I2C_BOOTROM) 525 #if defined(I2C_BOOTROM)
506 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis"); 526 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
507 #endif /* I2C_BOOTROM */ 527 #endif /* I2C_BOOTROM */
508 #if defined(SDR0_PINSTP_SHIFT) 528 #if defined(SDR0_PINSTP_SHIFT)
509 printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]); 529 printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
510 printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]); 530 printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
511 #endif /* SDR0_PINSTP_SHIFT */ 531 #endif /* SDR0_PINSTP_SHIFT */
512 532
513 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX) 533 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
514 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis"); 534 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
515 #endif 535 #endif
516 536
517 #if defined(PCI_ASYNC) 537 #if defined(PCI_ASYNC)
518 if (pci_async_enabled()) { 538 if (pci_async_enabled()) {
519 printf (", PCI async ext clock used"); 539 printf (", PCI async ext clock used");
520 } else { 540 } else {
521 printf (", PCI sync clock at %lu MHz", 541 printf (", PCI sync clock at %lu MHz",
522 sys_info.freqPLB / sys_info.pllPciDiv / 1000000); 542 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
523 } 543 }
524 #endif 544 #endif
525 545
526 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX) 546 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
527 putc('\n'); 547 putc('\n');
528 #endif 548 #endif
529 549
530 #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) 550 #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
531 printf (" 16 kB I-Cache 16 kB D-Cache"); 551 printf (" 16 kB I-Cache 16 kB D-Cache");
532 #elif defined(CONFIG_440) 552 #elif defined(CONFIG_440)
533 printf (" 32 kB I-Cache 32 kB D-Cache"); 553 printf (" 32 kB I-Cache 32 kB D-Cache");
534 #else 554 #else
535 printf (" 16 kB I-Cache %d kB D-Cache", 555 printf (" 16 kB I-Cache %d kB D-Cache",
536 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8); 556 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
537 #endif 557 #endif
538 #endif /* !defined(CONFIG_IOP480) */ 558 #endif /* !defined(CONFIG_IOP480) */
539 559
540 #if defined(CONFIG_IOP480) 560 #if defined(CONFIG_IOP480)
541 printf ("PLX IOP480 (PVR=%08x)", pvr); 561 printf ("PLX IOP480 (PVR=%08x)", pvr);
542 printf (" at %s MHz:", strmhz(buf, clock)); 562 printf (" at %s MHz:", strmhz(buf, clock));
543 printf (" %u kB I-Cache", 4); 563 printf (" %u kB I-Cache", 4);
544 printf (" %u kB D-Cache", 2); 564 printf (" %u kB D-Cache", 2);
545 #endif 565 #endif
546 566
547 #endif /* !defined(CONFIG_405) */ 567 #endif /* !defined(CONFIG_405) */
548 568
549 putc ('\n'); 569 putc ('\n');
550 570
551 return 0; 571 return 0;
552 } 572 }
553 573
554 int ppc440spe_revB() { 574 int ppc440spe_revB() {
555 unsigned int pvr; 575 unsigned int pvr;
556 576
557 pvr = get_pvr(); 577 pvr = get_pvr();
558 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB)) 578 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
559 return 1; 579 return 1;
560 else 580 else
561 return 0; 581 return 0;
562 } 582 }
563 583
564 /* ------------------------------------------------------------------------- */ 584 /* ------------------------------------------------------------------------- */
565 585
566 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) 586 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
567 { 587 {
568 #if defined(CONFIG_BOARD_RESET) 588 #if defined(CONFIG_BOARD_RESET)
569 board_reset(); 589 board_reset();
570 #else 590 #else
571 #if defined(CFG_4xx_RESET_TYPE) 591 #if defined(CFG_4xx_RESET_TYPE)
572 mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28); 592 mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28);
573 #else 593 #else
574 /* 594 /*
575 * Initiate system reset in debug control register DBCR 595 * Initiate system reset in debug control register DBCR
576 */ 596 */
577 mtspr(dbcr0, 0x30000000); 597 mtspr(dbcr0, 0x30000000);
578 #endif /* defined(CFG_4xx_RESET_TYPE) */ 598 #endif /* defined(CFG_4xx_RESET_TYPE) */
579 #endif /* defined(CONFIG_BOARD_RESET) */ 599 #endif /* defined(CONFIG_BOARD_RESET) */
580 600
581 return 1; 601 return 1;
582 } 602 }
583 603
584 604
585 /* 605 /*
586 * Get timebase clock frequency 606 * Get timebase clock frequency
587 */ 607 */
588 unsigned long get_tbclk (void) 608 unsigned long get_tbclk (void)
589 { 609 {
590 #if !defined(CONFIG_IOP480) 610 #if !defined(CONFIG_IOP480)
591 sys_info_t sys_info; 611 sys_info_t sys_info;
592 612
593 get_sys_info(&sys_info); 613 get_sys_info(&sys_info);
594 return (sys_info.freqProcessor); 614 return (sys_info.freqProcessor);
595 #else 615 #else
596 return (66000000); 616 return (66000000);
597 #endif 617 #endif
598 618
599 } 619 }
600 620
601 621
602 #if defined(CONFIG_WATCHDOG) 622 #if defined(CONFIG_WATCHDOG)
603 void watchdog_reset(void) 623 void watchdog_reset(void)
604 { 624 {
605 int re_enable = disable_interrupts(); 625 int re_enable = disable_interrupts();
606 reset_4xx_watchdog(); 626 reset_4xx_watchdog();
607 if (re_enable) enable_interrupts(); 627 if (re_enable) enable_interrupts();
608 } 628 }
609 629
610 void reset_4xx_watchdog(void) 630 void reset_4xx_watchdog(void)
611 { 631 {
612 /* 632 /*
613 * Clear TSR(WIS) bit 633 * Clear TSR(WIS) bit
614 */ 634 */
615 mtspr(tsr, 0x40000000); 635 mtspr(tsr, 0x40000000);
616 } 636 }
617 #endif /* CONFIG_WATCHDOG */ 637 #endif /* CONFIG_WATCHDOG */
618 638
include/asm-ppc/processor.h
Diff comments   View file @ 35fca4c
1 #ifndef __ASM_PPC_PROCESSOR_H 1 #ifndef __ASM_PPC_PROCESSOR_H
2 #define __ASM_PPC_PROCESSOR_H 2 #define __ASM_PPC_PROCESSOR_H
3 3
4 /* 4 /*
5 * Default implementation of macro that returns current 5 * Default implementation of macro that returns current
6 * instruction pointer ("program counter"). 6 * instruction pointer ("program counter").
7 */ 7 */
8 #define current_text_addr() ({ __label__ _l; _l: &&_l;}) 8 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
9 9
10 #include <linux/config.h> 10 #include <linux/config.h>
11 11
12 #include <asm/ptrace.h> 12 #include <asm/ptrace.h>
13 #include <asm/types.h> 13 #include <asm/types.h>
14 14
15 /* Machine State Register (MSR) Fields */ 15 /* Machine State Register (MSR) Fields */
16 16
17 #ifdef CONFIG_PPC64BRIDGE 17 #ifdef CONFIG_PPC64BRIDGE
18 #define MSR_SF (1<<63) 18 #define MSR_SF (1<<63)
19 #define MSR_ISF (1<<61) 19 #define MSR_ISF (1<<61)
20 #endif /* CONFIG_PPC64BRIDGE */ 20 #endif /* CONFIG_PPC64BRIDGE */
21 #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ 21 #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
22 #define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ 22 #define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */
23 #define MSR_SPE (1<<25) /* Enable SPE(e500) */ 23 #define MSR_SPE (1<<25) /* Enable SPE(e500) */
24 #define MSR_POW (1<<18) /* Enable Power Management */ 24 #define MSR_POW (1<<18) /* Enable Power Management */
25 #define MSR_WE (1<<18) /* Wait State Enable */ 25 #define MSR_WE (1<<18) /* Wait State Enable */
26 #define MSR_TGPR (1<<17) /* TLB Update registers in use */ 26 #define MSR_TGPR (1<<17) /* TLB Update registers in use */
27 #define MSR_CE (1<<17) /* Critical Interrupt Enable */ 27 #define MSR_CE (1<<17) /* Critical Interrupt Enable */
28 #define MSR_ILE (1<<16) /* Interrupt Little Endian */ 28 #define MSR_ILE (1<<16) /* Interrupt Little Endian */
29 #define MSR_EE (1<<15) /* External Interrupt Enable */ 29 #define MSR_EE (1<<15) /* External Interrupt Enable */
30 #define MSR_PR (1<<14) /* Problem State / Privilege Level */ 30 #define MSR_PR (1<<14) /* Problem State / Privilege Level */
31 #define MSR_FP (1<<13) /* Floating Point enable */ 31 #define MSR_FP (1<<13) /* Floating Point enable */
32 #define MSR_ME (1<<12) /* Machine Check Enable */ 32 #define MSR_ME (1<<12) /* Machine Check Enable */
33 #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ 33 #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
34 #define MSR_SE (1<<10) /* Single Step */ 34 #define MSR_SE (1<<10) /* Single Step */
35 #define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ 35 #define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
36 #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ 36 #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
37 #define MSR_BE (1<<9) /* Branch Trace */ 37 #define MSR_BE (1<<9) /* Branch Trace */
38 #define MSR_DE (1<<9) /* Debug Exception Enable */ 38 #define MSR_DE (1<<9) /* Debug Exception Enable */
39 #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ 39 #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
40 #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ 40 #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
41 #define MSR_IR (1<<5) /* Instruction Relocate */ 41 #define MSR_IR (1<<5) /* Instruction Relocate */
42 #define MSR_IS (1<<5) /* Book E Instruction space */ 42 #define MSR_IS (1<<5) /* Book E Instruction space */
43 #define MSR_DR (1<<4) /* Data Relocate */ 43 #define MSR_DR (1<<4) /* Data Relocate */
44 #define MSR_DS (1<<4) /* Book E Data space */ 44 #define MSR_DS (1<<4) /* Book E Data space */
45 #define MSR_PE (1<<3) /* Protection Enable */ 45 #define MSR_PE (1<<3) /* Protection Enable */
46 #define MSR_PX (1<<2) /* Protection Exclusive Mode */ 46 #define MSR_PX (1<<2) /* Protection Exclusive Mode */
47 #define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ 47 #define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
48 #define MSR_RI (1<<1) /* Recoverable Exception */ 48 #define MSR_RI (1<<1) /* Recoverable Exception */
49 #define MSR_LE (1<<0) /* Little Endian */ 49 #define MSR_LE (1<<0) /* Little Endian */
50 50
51 #ifdef CONFIG_APUS_FAST_EXCEPT 51 #ifdef CONFIG_APUS_FAST_EXCEPT
52 #define MSR_ MSR_ME|MSR_IP|MSR_RI 52 #define MSR_ MSR_ME|MSR_IP|MSR_RI
53 #else 53 #else
54 #define MSR_ MSR_ME|MSR_RI 54 #define MSR_ MSR_ME|MSR_RI
55 #endif 55 #endif
56 #ifndef CONFIG_E500 56 #ifndef CONFIG_E500
57 #define MSR_KERNEL MSR_|MSR_IR|MSR_DR 57 #define MSR_KERNEL MSR_|MSR_IR|MSR_DR
58 #else 58 #else
59 #define MSR_KERNEL MSR_ME 59 #define MSR_KERNEL MSR_ME
60 #endif 60 #endif
61 61
62 /* Floating Point Status and Control Register (FPSCR) Fields */ 62 /* Floating Point Status and Control Register (FPSCR) Fields */
63 63
64 #define FPSCR_FX 0x80000000 /* FPU exception summary */ 64 #define FPSCR_FX 0x80000000 /* FPU exception summary */
65 #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ 65 #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
66 #define FPSCR_VX 0x20000000 /* Invalid operation summary */ 66 #define FPSCR_VX 0x20000000 /* Invalid operation summary */
67 #define FPSCR_OX 0x10000000 /* Overflow exception summary */ 67 #define FPSCR_OX 0x10000000 /* Overflow exception summary */
68 #define FPSCR_UX 0x08000000 /* Underflow exception summary */ 68 #define FPSCR_UX 0x08000000 /* Underflow exception summary */
69 #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ 69 #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
70 #define FPSCR_XX 0x02000000 /* Inexact exception summary */ 70 #define FPSCR_XX 0x02000000 /* Inexact exception summary */
71 #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ 71 #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
72 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ 72 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
73 #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ 73 #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
74 #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ 74 #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
75 #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ 75 #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
76 #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ 76 #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
77 #define FPSCR_FR 0x00040000 /* Fraction rounded */ 77 #define FPSCR_FR 0x00040000 /* Fraction rounded */
78 #define FPSCR_FI 0x00020000 /* Fraction inexact */ 78 #define FPSCR_FI 0x00020000 /* Fraction inexact */
79 #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ 79 #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
80 #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ 80 #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
81 #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ 81 #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
82 #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ 82 #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
83 #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ 83 #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
84 #define FPSCR_VE 0x00000080 /* Invalid op exception enable */ 84 #define FPSCR_VE 0x00000080 /* Invalid op exception enable */
85 #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ 85 #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
86 #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ 86 #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
87 #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ 87 #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
88 #define FPSCR_XE 0x00000008 /* FP inexact exception enable */ 88 #define FPSCR_XE 0x00000008 /* FP inexact exception enable */
89 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ 89 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
90 #define FPSCR_RN 0x00000003 /* FPU rounding control */ 90 #define FPSCR_RN 0x00000003 /* FPU rounding control */
91 91
92 /* Special Purpose Registers (SPRNs)*/ 92 /* Special Purpose Registers (SPRNs)*/
93 93
94 /* PPC440 Architecture is BOOK-E */ 94 /* PPC440 Architecture is BOOK-E */
95 #ifdef CONFIG_440 95 #ifdef CONFIG_440
96 #define CONFIG_BOOKE 96 #define CONFIG_BOOKE
97 #endif 97 #endif
98 98
99 #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ 99 #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
100 #define SPRN_CTR 0x009 /* Count Register */ 100 #define SPRN_CTR 0x009 /* Count Register */
101 #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ 101 #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
102 #ifndef CONFIG_BOOKE 102 #ifndef CONFIG_BOOKE
103 #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ 103 #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
104 #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ 104 #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
105 #else 105 #else
106 #define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ 106 #define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */
107 #define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ 107 #define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */
108 #endif /* CONFIG_BOOKE */ 108 #endif /* CONFIG_BOOKE */
109 #define SPRN_DAR 0x013 /* Data Address Register */ 109 #define SPRN_DAR 0x013 /* Data Address Register */
110 #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ 110 #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
111 #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ 111 #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
112 #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ 112 #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
113 #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ 113 #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
114 #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ 114 #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
115 #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ 115 #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
116 #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ 116 #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
117 #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ 117 #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
118 #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ 118 #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
119 #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ 119 #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
120 #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ 120 #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
121 #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ 121 #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
122 #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ 122 #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
123 #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ 123 #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
124 #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ 124 #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
125 #define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ 125 #define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */
126 #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ 126 #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
127 #define DBCR_EDM 0x80000000 127 #define DBCR_EDM 0x80000000
128 #define DBCR_IDM 0x40000000 128 #define DBCR_IDM 0x40000000
129 #define DBCR_RST(x) (((x) & 0x3) << 28) 129 #define DBCR_RST(x) (((x) & 0x3) << 28)
130 #define DBCR_RST_NONE 0 130 #define DBCR_RST_NONE 0
131 #define DBCR_RST_CORE 1 131 #define DBCR_RST_CORE 1
132 #define DBCR_RST_CHIP 2 132 #define DBCR_RST_CHIP 2
133 #define DBCR_RST_SYSTEM 3 133 #define DBCR_RST_SYSTEM 3
134 #define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ 134 #define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
135 #define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ 135 #define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
136 #define DBCR_EDE 0x02000000 /* Exception Debug Event */ 136 #define DBCR_EDE 0x02000000 /* Exception Debug Event */
137 #define DBCR_TDE 0x01000000 /* TRAP Debug Event */ 137 #define DBCR_TDE 0x01000000 /* TRAP Debug Event */
138 #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ 138 #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
139 #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ 139 #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
140 #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ 140 #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
141 #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ 141 #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
142 #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ 142 #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
143 #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ 143 #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
144 #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ 144 #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
145 #define DAC_BYTE 0 145 #define DAC_BYTE 0
146 #define DAC_HALF 1 146 #define DAC_HALF 1
147 #define DAC_WORD 2 147 #define DAC_WORD 2
148 #define DAC_QUAD 3 148 #define DAC_QUAD 3
149 #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ 149 #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
150 #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ 150 #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
151 #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ 151 #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
152 #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ 152 #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
153 #define DBCR_SED 0x00000020 /* Second Exception Debug Event */ 153 #define DBCR_SED 0x00000020 /* Second Exception Debug Event */
154 #define DBCR_STD 0x00000010 /* Second Trap Debug Event */ 154 #define DBCR_STD 0x00000010 /* Second Trap Debug Event */
155 #define DBCR_SIA 0x00000008 /* Second IAC Enable */ 155 #define DBCR_SIA 0x00000008 /* Second IAC Enable */
156 #define DBCR_SDA 0x00000004 /* Second DAC Enable */ 156 #define DBCR_SDA 0x00000004 /* Second DAC Enable */
157 #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ 157 #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
158 #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ 158 #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
159 #ifndef CONFIG_BOOKE 159 #ifndef CONFIG_BOOKE
160 #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ 160 #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
161 #else 161 #else
162 #define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ 162 #define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
163 #endif /* CONFIG_BOOKE */ 163 #endif /* CONFIG_BOOKE */
164 #ifndef CONFIG_BOOKE 164 #ifndef CONFIG_BOOKE
165 #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ 165 #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
166 #define SPRN_DBSR 0x3F0 /* Debug Status Register */ 166 #define SPRN_DBSR 0x3F0 /* Debug Status Register */
167 #else 167 #else
168 #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ 168 #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
169 #define SPRN_DBSR 0x130 /* Book E Debug Status Register */ 169 #define SPRN_DBSR 0x130 /* Book E Debug Status Register */
170 #define DBSR_IC 0x08000000 /* Book E Instruction Completion */ 170 #define DBSR_IC 0x08000000 /* Book E Instruction Completion */
171 #define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ 171 #define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
172 #endif /* CONFIG_BOOKE */ 172 #endif /* CONFIG_BOOKE */
173 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ 173 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
174 #define DCCR_NOCACHE 0 /* Noncacheable */ 174 #define DCCR_NOCACHE 0 /* Noncacheable */
175 #define DCCR_CACHE 1 /* Cacheable */ 175 #define DCCR_CACHE 1 /* Cacheable */
176 #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ 176 #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
177 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ 177 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
178 #define DCWR_COPY 0 /* Copy-back */ 178 #define DCWR_COPY 0 /* Copy-back */
179 #define DCWR_WRITE 1 /* Write-through */ 179 #define DCWR_WRITE 1 /* Write-through */
180 #ifndef CONFIG_BOOKE 180 #ifndef CONFIG_BOOKE
181 #define SPRN_DEAR 0x3D5 /* Data Error Address Register */ 181 #define SPRN_DEAR 0x3D5 /* Data Error Address Register */
182 #else 182 #else
183 #define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ 183 #define SPRN_DEAR 0x03D /* Book E Data Error Address Register */
184 #endif /* CONFIG_BOOKE */ 184 #endif /* CONFIG_BOOKE */
185 #define SPRN_DEC 0x016 /* Decrement Register */ 185 #define SPRN_DEC 0x016 /* Decrement Register */
186 #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ 186 #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
187 #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ 187 #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
188 #define SPRN_EAR 0x11A /* External Address Register */ 188 #define SPRN_EAR 0x11A /* External Address Register */
189 #ifndef CONFIG_BOOKE 189 #ifndef CONFIG_BOOKE
190 #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ 190 #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
191 #else 191 #else
192 #define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ 192 #define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */
193 #endif /* CONFIG_BOOKE */ 193 #endif /* CONFIG_BOOKE */
194 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ 194 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
195 #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ 195 #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
196 #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ 196 #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
197 #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ 197 #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
198 #define ESR_PIL 0x08000000 /* Program Exception - Illegal */ 198 #define ESR_PIL 0x08000000 /* Program Exception - Illegal */
199 #define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ 199 #define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
200 #define ESR_PTR 0x02000000 /* Program Exception - Trap */ 200 #define ESR_PTR 0x02000000 /* Program Exception - Trap */
201 #define ESR_DST 0x00800000 /* Storage Exception - Data miss */ 201 #define ESR_DST 0x00800000 /* Storage Exception - Data miss */
202 #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ 202 #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
203 #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ 203 #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
204 #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ 204 #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
205 #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ 205 #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
206 #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ 206 #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
207 207
208 #define HID0_ICE_SHIFT 15 208 #define HID0_ICE_SHIFT 15
209 #define HID0_DCE_SHIFT 14 209 #define HID0_DCE_SHIFT 14
210 #define HID0_DLOCK_SHIFT 12 210 #define HID0_DLOCK_SHIFT 12
211 211
212 #define HID0_EMCP (1<<31) /* Enable Machine Check pin */ 212 #define HID0_EMCP (1<<31) /* Enable Machine Check pin */
213 #define HID0_EBA (1<<29) /* Enable Bus Address Parity */ 213 #define HID0_EBA (1<<29) /* Enable Bus Address Parity */
214 #define HID0_EBD (1<<28) /* Enable Bus Data Parity */ 214 #define HID0_EBD (1<<28) /* Enable Bus Data Parity */
215 #define HID0_SBCLK (1<<27) 215 #define HID0_SBCLK (1<<27)
216 #define HID0_EICE (1<<26) 216 #define HID0_EICE (1<<26)
217 #define HID0_ECLK (1<<25) 217 #define HID0_ECLK (1<<25)
218 #define HID0_PAR (1<<24) 218 #define HID0_PAR (1<<24)
219 #define HID0_DOZE (1<<23) 219 #define HID0_DOZE (1<<23)
220 #define HID0_NAP (1<<22) 220 #define HID0_NAP (1<<22)
221 #define HID0_SLEEP (1<<21) 221 #define HID0_SLEEP (1<<21)
222 #define HID0_DPM (1<<20) 222 #define HID0_DPM (1<<20)
223 #define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */ 223 #define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
224 #define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */ 224 #define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
225 #define HID0_TBEN (1<<14) /* Time Base Enable */ 225 #define HID0_TBEN (1<<14) /* Time Base Enable */
226 #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ 226 #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
227 #define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */ 227 #define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
228 #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ 228 #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
229 #define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */ 229 #define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
230 #define HID0_DCI HID0_DCFI 230 #define HID0_DCI HID0_DCFI
231 #define HID0_SPD (1<<9) /* Speculative disable */ 231 #define HID0_SPD (1<<9) /* Speculative disable */
232 #define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */ 232 #define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */
233 #define HID0_SGE (1<<7) /* Store Gathering Enable */ 233 #define HID0_SGE (1<<7) /* Store Gathering Enable */
234 #define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */ 234 #define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
235 #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ 235 #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
236 #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */ 236 #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
237 #define HID0_ABE (1<<3) /* Address Broadcast Enable */ 237 #define HID0_ABE (1<<3) /* Address Broadcast Enable */
238 #define HID0_BHTE (1<<2) /* Branch History Table Enable */ 238 #define HID0_BHTE (1<<2) /* Branch History Table Enable */
239 #define HID0_BTCD (1<<1) /* Branch target cache disable */ 239 #define HID0_BTCD (1<<1) /* Branch target cache disable */
240 #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ 240 #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
241 #define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ 241 #define HID1_RFXE (1<<17) /* Read Fault Exception Enable */
242 #define HID1_ASTME (1<<13) /* Address bus streaming mode */ 242 #define HID1_ASTME (1<<13) /* Address bus streaming mode */
243 #define HID1_ABE (1<<12) /* Address broadcast enable */ 243 #define HID1_ABE (1<<12) /* Address broadcast enable */
244 #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ 244 #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
245 #ifndef CONFIG_BOOKE 245 #ifndef CONFIG_BOOKE
246 #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ 246 #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
247 #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ 247 #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
248 #else 248 #else
249 #define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */ 249 #define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */
250 #define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */ 250 #define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */
251 #endif /* CONFIG_BOOKE */ 251 #endif /* CONFIG_BOOKE */
252 #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ 252 #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
253 #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ 253 #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
254 #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ 254 #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
255 #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ 255 #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
256 #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ 256 #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
257 #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ 257 #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
258 #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ 258 #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
259 #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ 259 #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
260 #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ 260 #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
261 #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ 261 #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
262 #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ 262 #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
263 #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ 263 #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
264 #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ 264 #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
265 #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ 265 #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
266 #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ 266 #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
267 #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ 267 #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
268 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ 268 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
269 #define ICCR_NOCACHE 0 /* Noncacheable */ 269 #define ICCR_NOCACHE 0 /* Noncacheable */
270 #define ICCR_CACHE 1 /* Cacheable */ 270 #define ICCR_CACHE 1 /* Cacheable */
271 #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ 271 #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
272 #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ 272 #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
273 #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ 273 #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
274 #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ 274 #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
275 #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ 275 #define SPRN_IMMR 0x27E /* Internal Memory Map Register */
276 #define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ 276 #define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
277 #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ 277 #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
278 #define SPRN_LR 0x008 /* Link Register */ 278 #define SPRN_LR 0x008 /* Link Register */
279 #define SPRN_MBAR 0x137 /* System memory base address */ 279 #define SPRN_MBAR 0x137 /* System memory base address */
280 #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ 280 #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
281 #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ 281 #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
282 #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ 282 #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
283 #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ 283 #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
284 #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ 284 #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
285 #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ 285 #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
286 #ifndef CONFIG_BOOKE 286 #ifndef CONFIG_BOOKE
287 #define SPRN_PID 0x3B1 /* Process ID */ 287 #define SPRN_PID 0x3B1 /* Process ID */
288 #define SPRN_PIR 0x3FF /* Processor Identification Register */ 288 #define SPRN_PIR 0x3FF /* Processor Identification Register */
289 #else 289 #else
290 #define SPRN_PID 0x030 /* Book E Process ID */ 290 #define SPRN_PID 0x030 /* Book E Process ID */
291 #define SPRN_PIR 0x11E /* Book E Processor Identification Register */ 291 #define SPRN_PIR 0x11E /* Book E Processor Identification Register */
292 #endif /* CONFIG_BOOKE */ 292 #endif /* CONFIG_BOOKE */
293 #define SPRN_PIT 0x3DB /* Programmable Interval Timer */ 293 #define SPRN_PIT 0x3DB /* Programmable Interval Timer */
294 #define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */ 294 #define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
295 #define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ 295 #define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
296 #define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */ 296 #define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
297 #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ 297 #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
298 #define SPRN_PVR 0x11F /* Processor Version Register */ 298 #define SPRN_PVR 0x11F /* Processor Version Register */
299 #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ 299 #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
300 #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ 300 #define SPRN_SDA 0x3BF /* Sampled Data Address Register */
301 #define SPRN_SDR1 0x019 /* MMU Hash Base Register */ 301 #define SPRN_SDR1 0x019 /* MMU Hash Base Register */
302 #define SPRN_SGR 0x3B9 /* Storage Guarded Register */ 302 #define SPRN_SGR 0x3B9 /* Storage Guarded Register */
303 #define SGR_NORMAL 0 303 #define SGR_NORMAL 0
304 #define SGR_GUARDED 1 304 #define SGR_GUARDED 1
305 #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ 305 #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
306 #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ 306 #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
307 #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ 307 #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
308 #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ 308 #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
309 #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ 309 #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
310 #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ 310 #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
311 #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ 311 #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
312 #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ 312 #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
313 #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ 313 #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
314 #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ 314 #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
315 #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ 315 #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
316 #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ 316 #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
317 #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ 317 #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
318 #ifdef CONFIG_BOOKE 318 #ifdef CONFIG_BOOKE
319 #define SPRN_SVR 0x3FF /* System Version Register */ 319 #define SPRN_SVR 0x3FF /* System Version Register */
320 #else 320 #else
321 #define SPRN_SVR 0x11E /* System Version Register */ 321 #define SPRN_SVR 0x11E /* System Version Register */
322 #endif 322 #endif
323 #define SPRN_TBHI 0x3DC /* Time Base High */ 323 #define SPRN_TBHI 0x3DC /* Time Base High */
324 #define SPRN_TBHU 0x3CC /* Time Base High User-mode */ 324 #define SPRN_TBHU 0x3CC /* Time Base High User-mode */
325 #define SPRN_TBLO 0x3DD /* Time Base Low */ 325 #define SPRN_TBLO 0x3DD /* Time Base Low */
326 #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ 326 #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
327 #define SPRN_TBRL 0x10C /* Time Base Read Lower Register */ 327 #define SPRN_TBRL 0x10C /* Time Base Read Lower Register */
328 #define SPRN_TBRU 0x10D /* Time Base Read Upper Register */ 328 #define SPRN_TBRU 0x10D /* Time Base Read Upper Register */
329 #define SPRN_TBWL 0x11C /* Time Base Write Lower Register */ 329 #define SPRN_TBWL 0x11C /* Time Base Write Lower Register */
330 #define SPRN_TBWU 0x11D /* Time Base Write Upper Register */ 330 #define SPRN_TBWU 0x11D /* Time Base Write Upper Register */
331 #ifndef CONFIG_BOOKE 331 #ifndef CONFIG_BOOKE
332 #define SPRN_TCR 0x3DA /* Timer Control Register */ 332 #define SPRN_TCR 0x3DA /* Timer Control Register */
333 #else 333 #else
334 #define SPRN_TCR 0x154 /* Book E Timer Control Register */ 334 #define SPRN_TCR 0x154 /* Book E Timer Control Register */
335 #endif /* CONFIG_BOOKE */ 335 #endif /* CONFIG_BOOKE */
336 #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ 336 #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
337 #define WP_2_17 0 /* 2^17 clocks */ 337 #define WP_2_17 0 /* 2^17 clocks */
338 #define WP_2_21 1 /* 2^21 clocks */ 338 #define WP_2_21 1 /* 2^21 clocks */
339 #define WP_2_25 2 /* 2^25 clocks */ 339 #define WP_2_25 2 /* 2^25 clocks */
340 #define WP_2_29 3 /* 2^29 clocks */ 340 #define WP_2_29 3 /* 2^29 clocks */
341 #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ 341 #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
342 #define WRC_NONE 0 /* No reset will occur */ 342 #define WRC_NONE 0 /* No reset will occur */
343 #define WRC_CORE 1 /* Core reset will occur */ 343 #define WRC_CORE 1 /* Core reset will occur */
344 #define WRC_CHIP 2 /* Chip reset will occur */ 344 #define WRC_CHIP 2 /* Chip reset will occur */
345 #define WRC_SYSTEM 3 /* System reset will occur */ 345 #define WRC_SYSTEM 3 /* System reset will occur */
346 #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ 346 #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
347 #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ 347 #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
348 #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ 348 #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
349 #define FP_2_9 0 /* 2^9 clocks */ 349 #define FP_2_9 0 /* 2^9 clocks */
350 #define FP_2_13 1 /* 2^13 clocks */ 350 #define FP_2_13 1 /* 2^13 clocks */
351 #define FP_2_17 2 /* 2^17 clocks */ 351 #define FP_2_17 2 /* 2^17 clocks */
352 #define FP_2_21 3 /* 2^21 clocks */ 352 #define FP_2_21 3 /* 2^21 clocks */
353 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ 353 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
354 #define TCR_ARE 0x00400000 /* Auto Reload Enable */ 354 #define TCR_ARE 0x00400000 /* Auto Reload Enable */
355 #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ 355 #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
356 #define THRM1_TIN (1<<0) 356 #define THRM1_TIN (1<<0)
357 #define THRM1_TIV (1<<1) 357 #define THRM1_TIV (1<<1)
358 #define THRM1_THRES (0x7f<<2) 358 #define THRM1_THRES (0x7f<<2)
359 #define THRM1_TID (1<<29) 359 #define THRM1_TID (1<<29)
360 #define THRM1_TIE (1<<30) 360 #define THRM1_TIE (1<<30)
361 #define THRM1_V (1<<31) 361 #define THRM1_V (1<<31)
362 #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ 362 #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
363 #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ 363 #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
364 #define THRM3_E (1<<31) 364 #define THRM3_E (1<<31)
365 #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ 365 #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
366 #ifndef CONFIG_BOOKE 366 #ifndef CONFIG_BOOKE
367 #define SPRN_TSR 0x3D8 /* Timer Status Register */ 367 #define SPRN_TSR 0x3D8 /* Timer Status Register */
368 #else 368 #else
369 #define SPRN_TSR 0x150 /* Book E Timer Status Register */ 369 #define SPRN_TSR 0x150 /* Book E Timer Status Register */
370 #endif /* CONFIG_BOOKE */ 370 #endif /* CONFIG_BOOKE */
371 #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ 371 #define TSR_ENW 0x80000000 /* Enable Next Watchdog */
372 #define TSR_WIS 0x40000000 /* WDT Interrupt Status */ 372 #define TSR_WIS 0x40000000 /* WDT Interrupt Status */
373 #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ 373 #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
374 #define WRS_NONE 0 /* No WDT reset occurred */ 374 #define WRS_NONE 0 /* No WDT reset occurred */
375 #define WRS_CORE 1 /* WDT forced core reset */ 375 #define WRS_CORE 1 /* WDT forced core reset */
376 #define WRS_CHIP 2 /* WDT forced chip reset */ 376 #define WRS_CHIP 2 /* WDT forced chip reset */
377 #define WRS_SYSTEM 3 /* WDT forced system reset */ 377 #define WRS_SYSTEM 3 /* WDT forced system reset */
378 #define TSR_PIS 0x08000000 /* PIT Interrupt Status */ 378 #define TSR_PIS 0x08000000 /* PIT Interrupt Status */
379 #define TSR_FIS 0x04000000 /* FIT Interrupt Status */ 379 #define TSR_FIS 0x04000000 /* FIT Interrupt Status */
380 #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ 380 #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
381 #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ 381 #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
382 #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ 382 #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
383 #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ 383 #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
384 #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ 384 #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
385 #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ 385 #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
386 #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ 386 #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
387 #define SPRN_XER 0x001 /* Fixed Point Exception Register */ 387 #define SPRN_XER 0x001 /* Fixed Point Exception Register */
388 #define SPRN_ZPR 0x3B0 /* Zone Protection Register */ 388 #define SPRN_ZPR 0x3B0 /* Zone Protection Register */
389 389
390 /* Book E definitions */ 390 /* Book E definitions */
391 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ 391 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
392 #define SPRN_CSRR0 0x03A /* Critical SRR0 */ 392 #define SPRN_CSRR0 0x03A /* Critical SRR0 */
393 #define SPRN_CSRR1 0x03B /* Critical SRR0 */ 393 #define SPRN_CSRR1 0x03B /* Critical SRR0 */
394 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ 394 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
395 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ 395 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
396 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ 396 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
397 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ 397 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
398 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ 398 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
399 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ 399 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
400 #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ 400 #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
401 #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ 401 #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
402 #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ 402 #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
403 #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ 403 #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
404 #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ 404 #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
405 #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ 405 #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
406 #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ 406 #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
407 #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ 407 #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
408 #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ 408 #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
409 #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ 409 #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
410 #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ 410 #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
411 #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ 411 #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
412 #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ 412 #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
413 #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ 413 #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
414 #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ 414 #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
415 #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ 415 #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
416 #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ 416 #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
417 #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ 417 #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
418 #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ 418 #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
419 #define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */ 419 #define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */
420 #define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */ 420 #define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */
421 #define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */ 421 #define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */
422 #define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */ 422 #define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */
423 #define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */ 423 #define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */
424 #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ 424 #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
425 425
426 /* e500 definitions */ 426 /* e500 definitions */
427 #define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */ 427 #define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */
428 #define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */ 428 #define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */
429 #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ 429 #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
430 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ 430 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
431 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ 431 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
432 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ 432 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
433 #define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ 433 #define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
434 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ 434 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
435 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ 435 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
436 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ 436 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
437 437
438 #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ 438 #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
439 #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ 439 #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
440 #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ 440 #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
441 #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ 441 #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
442 #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ 442 #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
443 #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ 443 #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
444 #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ 444 #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
445 #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ 445 #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
446 #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ 446 #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
447 447
448 #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ 448 #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
449 #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ 449 #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
450 #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ 450 #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
451 #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ 451 #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
452 #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ 452 #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
453 453
454 #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ 454 #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
455 #define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ 455 #define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
456 #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ 456 #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
457 #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ 457 #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
458 #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ 458 #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
459 #define SPRN_PID1 0x279 /* Process ID Register 1 */ 459 #define SPRN_PID1 0x279 /* Process ID Register 1 */
460 #define SPRN_PID2 0x27a /* Process ID Register 2 */ 460 #define SPRN_PID2 0x27a /* Process ID Register 2 */
461 #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ 461 #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
462 #define SPRN_MCAR 0x23d /* Machine Check Address register */ 462 #define SPRN_MCAR 0x23d /* Machine Check Address register */
463 #ifdef CONFIG_440 463 #ifdef CONFIG_440
464 #define MCSR_MCS 0x80000000 /* Machine Check Summary */ 464 #define MCSR_MCS 0x80000000 /* Machine Check Summary */
465 #define MCSR_IB 0x40000000 /* Instruction PLB Error */ 465 #define MCSR_IB 0x40000000 /* Instruction PLB Error */
466 #define MCSR_DRB 0x20000000 /* Data Read PLB Error */ 466 #define MCSR_DRB 0x20000000 /* Data Read PLB Error */
467 #define MCSR_DWB 0x10000000 /* Data Write PLB Error */ 467 #define MCSR_DWB 0x10000000 /* Data Write PLB Error */
468 #define MCSR_TLBP 0x08000000 /* TLB Parity Error */ 468 #define MCSR_TLBP 0x08000000 /* TLB Parity Error */
469 #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ 469 #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
470 #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ 470 #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
471 #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ 471 #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
472 #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ 472 #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
473 #endif 473 #endif
474 #define ESR_ST 0x00800000 /* Store Operation */ 474 #define ESR_ST 0x00800000 /* Store Operation */
475 475
476 #if defined(CONFIG_MPC86xx) 476 #if defined(CONFIG_MPC86xx)
477 #define SPRN_MSSCR0 0x3f6 477 #define SPRN_MSSCR0 0x3f6
478 #define SPRN_MSSSR0 0x3f7 478 #define SPRN_MSSSR0 0x3f7
479 #endif 479 #endif
480 480
481 /* Short-hand versions for a number of the above SPRNs */ 481 /* Short-hand versions for a number of the above SPRNs */
482 482
483 #define CTR SPRN_CTR /* Counter Register */ 483 #define CTR SPRN_CTR /* Counter Register */
484 #define DAR SPRN_DAR /* Data Address Register */ 484 #define DAR SPRN_DAR /* Data Address Register */
485 #define DABR SPRN_DABR /* Data Address Breakpoint Register */ 485 #define DABR SPRN_DABR /* Data Address Breakpoint Register */
486 #define DAC1 SPRN_DAC1 /* Data Address Register 1 */ 486 #define DAC1 SPRN_DAC1 /* Data Address Register 1 */
487 #define DAC2 SPRN_DAC2 /* Data Address Register 2 */ 487 #define DAC2 SPRN_DAC2 /* Data Address Register 2 */
488 #define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */ 488 #define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */
489 #define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */ 489 #define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */
490 #define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */ 490 #define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */
491 #define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */ 491 #define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */
492 #define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */ 492 #define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */
493 #define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */ 493 #define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */
494 #define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */ 494 #define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */
495 #define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */ 495 #define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */
496 #define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */ 496 #define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */
497 #define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */ 497 #define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */
498 #define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */ 498 #define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */
499 #define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */ 499 #define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */
500 #define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */ 500 #define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */
501 #define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */ 501 #define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
502 #define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */ 502 #define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
503 #define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */ 503 #define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
504 #define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */ 504 #define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
505 #define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */ 505 #define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
506 #define DBSR SPRN_DBSR /* Debug Status Register */ 506 #define DBSR SPRN_DBSR /* Debug Status Register */
507 #define DCMP SPRN_DCMP /* Data TLB Compare Register */ 507 #define DCMP SPRN_DCMP /* Data TLB Compare Register */
508 #define DEC SPRN_DEC /* Decrement Register */ 508 #define DEC SPRN_DEC /* Decrement Register */
509 #define DMISS SPRN_DMISS /* Data TLB Miss Register */ 509 #define DMISS SPRN_DMISS /* Data TLB Miss Register */
510 #define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ 510 #define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
511 #define EAR SPRN_EAR /* External Address Register */ 511 #define EAR SPRN_EAR /* External Address Register */
512 #define ESR SPRN_ESR /* Exception Syndrome Register */ 512 #define ESR SPRN_ESR /* Exception Syndrome Register */
513 #define HASH1 SPRN_HASH1 /* Primary Hash Address Register */ 513 #define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
514 #define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */ 514 #define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
515 #define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ 515 #define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
516 #define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */ 516 #define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
517 #define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ 517 #define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
518 #define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */ 518 #define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
519 #define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */ 519 #define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
520 #define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ 520 #define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
521 #define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */ 521 #define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */
522 #define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */ 522 #define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */
523 #define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */ 523 #define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */
524 #define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */ 524 #define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */
525 #define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */ 525 #define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */
526 #define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */ 526 #define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */
527 #define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */ 527 #define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */
528 #define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */ 528 #define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */
529 #define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */ 529 #define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */
530 #define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */ 530 #define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */
531 #define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */ 531 #define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
532 #define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */ 532 #define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
533 #define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */ 533 #define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
534 #define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ 534 #define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
535 #define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */ 535 #define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
536 #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ 536 #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
537 #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ 537 #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
538 #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ 538 #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
539 #define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ 539 #define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
540 #define L2CR SPRN_L2CR /* PPC 750 L2 control register */ 540 #define L2CR SPRN_L2CR /* PPC 750 L2 control register */
541 #define LR SPRN_LR 541 #define LR SPRN_LR
542 #define MBAR SPRN_MBAR /* System memory base address */ 542 #define MBAR SPRN_MBAR /* System memory base address */
543 #if defined(CONFIG_MPC86xx) 543 #if defined(CONFIG_MPC86xx)
544 #define MSSCR0 SPRN_MSSCR0 544 #define MSSCR0 SPRN_MSSCR0
545 #endif 545 #endif
546 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 546 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
547 #define PIR SPRN_PIR 547 #define PIR SPRN_PIR
548 #endif 548 #endif
549 #define SVR SPRN_SVR /* System-On-Chip Version Register */ 549 #define SVR SPRN_SVR /* System-On-Chip Version Register */
550 #define PVR SPRN_PVR /* Processor Version */ 550 #define PVR SPRN_PVR /* Processor Version */
551 #define RPA SPRN_RPA /* Required Physical Address Register */ 551 #define RPA SPRN_RPA /* Required Physical Address Register */
552 #define SDR1 SPRN_SDR1 /* MMU hash base register */ 552 #define SDR1 SPRN_SDR1 /* MMU hash base register */
553 #define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ 553 #define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
554 #define SPR1 SPRN_SPRG1 554 #define SPR1 SPRN_SPRG1
555 #define SPR2 SPRN_SPRG2 555 #define SPR2 SPRN_SPRG2
556 #define SPR3 SPRN_SPRG3 556 #define SPR3 SPRN_SPRG3
557 #define SPRG0 SPRN_SPRG0 557 #define SPRG0 SPRN_SPRG0
558 #define SPRG1 SPRN_SPRG1 558 #define SPRG1 SPRN_SPRG1
559 #define SPRG2 SPRN_SPRG2 559 #define SPRG2 SPRN_SPRG2
560 #define SPRG3 SPRN_SPRG3 560 #define SPRG3 SPRN_SPRG3
561 #define SPRG4 SPRN_SPRG4 561 #define SPRG4 SPRN_SPRG4
562 #define SPRG5 SPRN_SPRG5 562 #define SPRG5 SPRN_SPRG5
563 #define SPRG6 SPRN_SPRG6 563 #define SPRG6 SPRN_SPRG6
564 #define SPRG7 SPRN_SPRG7 564 #define SPRG7 SPRN_SPRG7
565 #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ 565 #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
566 #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ 566 #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
567 #define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */ 567 #define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */
568 #define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */ 568 #define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */
569 #define SVR SPRN_SVR /* System Version Register */ 569 #define SVR SPRN_SVR /* System Version Register */
570 #define TBRL SPRN_TBRL /* Time Base Read Lower Register */ 570 #define TBRL SPRN_TBRL /* Time Base Read Lower Register */
571 #define TBRU SPRN_TBRU /* Time Base Read Upper Register */ 571 #define TBRU SPRN_TBRU /* Time Base Read Upper Register */
572 #define TBWL SPRN_TBWL /* Time Base Write Lower Register */ 572 #define TBWL SPRN_TBWL /* Time Base Write Lower Register */
573 #define TBWU SPRN_TBWU /* Time Base Write Upper Register */ 573 #define TBWU SPRN_TBWU /* Time Base Write Upper Register */
574 #define TCR SPRN_TCR /* Timer Control Register */ 574 #define TCR SPRN_TCR /* Timer Control Register */
575 #define TSR SPRN_TSR /* Timer Status Register */ 575 #define TSR SPRN_TSR /* Timer Status Register */
576 #define ICTC 1019 576 #define ICTC 1019
577 #define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */ 577 #define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
578 #define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */ 578 #define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
579 #define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */ 579 #define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
580 #define XER SPRN_XER 580 #define XER SPRN_XER
581 581
582 #define DECAR SPRN_DECAR 582 #define DECAR SPRN_DECAR
583 #define CSRR0 SPRN_CSRR0 583 #define CSRR0 SPRN_CSRR0
584 #define CSRR1 SPRN_CSRR1 584 #define CSRR1 SPRN_CSRR1
585 #define IVPR SPRN_IVPR 585 #define IVPR SPRN_IVPR
586 #define USPRG0 SPRN_USPRG 586 #define USPRG0 SPRN_USPRG
587 #define SPRG4R SPRN_SPRG4R 587 #define SPRG4R SPRN_SPRG4R
588 #define SPRG5R SPRN_SPRG5R 588 #define SPRG5R SPRN_SPRG5R
589 #define SPRG6R SPRN_SPRG6R 589 #define SPRG6R SPRN_SPRG6R
590 #define SPRG7R SPRN_SPRG7R 590 #define SPRG7R SPRN_SPRG7R
591 #define SPRG4W SPRN_SPRG4W 591 #define SPRG4W SPRN_SPRG4W
592 #define SPRG5W SPRN_SPRG5W 592 #define SPRG5W SPRN_SPRG5W
593 #define SPRG6W SPRN_SPRG6W 593 #define SPRG6W SPRN_SPRG6W
594 #define SPRG7W SPRN_SPRG7W 594 #define SPRG7W SPRN_SPRG7W
595 #define DEAR SPRN_DEAR 595 #define DEAR SPRN_DEAR
596 #define DBCR2 SPRN_DBCR2 596 #define DBCR2 SPRN_DBCR2
597 #define IAC3 SPRN_IAC3 597 #define IAC3 SPRN_IAC3
598 #define IAC4 SPRN_IAC4 598 #define IAC4 SPRN_IAC4
599 #define DVC1 SPRN_DVC1 599 #define DVC1 SPRN_DVC1
600 #define DVC2 SPRN_DVC2 600 #define DVC2 SPRN_DVC2
601 #define IVOR0 SPRN_IVOR0 601 #define IVOR0 SPRN_IVOR0
602 #define IVOR1 SPRN_IVOR1 602 #define IVOR1 SPRN_IVOR1
603 #define IVOR2 SPRN_IVOR2 603 #define IVOR2 SPRN_IVOR2
604 #define IVOR3 SPRN_IVOR3 604 #define IVOR3 SPRN_IVOR3
605 #define IVOR4 SPRN_IVOR4 605 #define IVOR4 SPRN_IVOR4
606 #define IVOR5 SPRN_IVOR5 606 #define IVOR5 SPRN_IVOR5
607 #define IVOR6 SPRN_IVOR6 607 #define IVOR6 SPRN_IVOR6
608 #define IVOR7 SPRN_IVOR7 608 #define IVOR7 SPRN_IVOR7
609 #define IVOR8 SPRN_IVOR8 609 #define IVOR8 SPRN_IVOR8
610 #define IVOR9 SPRN_IVOR9 610 #define IVOR9 SPRN_IVOR9
611 #define IVOR10 SPRN_IVOR10 611 #define IVOR10 SPRN_IVOR10
612 #define IVOR11 SPRN_IVOR11 612 #define IVOR11 SPRN_IVOR11
613 #define IVOR12 SPRN_IVOR12 613 #define IVOR12 SPRN_IVOR12
614 #define IVOR13 SPRN_IVOR13 614 #define IVOR13 SPRN_IVOR13
615 #define IVOR14 SPRN_IVOR14 615 #define IVOR14 SPRN_IVOR14
616 #define IVOR15 SPRN_IVOR15 616 #define IVOR15 SPRN_IVOR15
617 #define IVOR32 SPRN_IVOR32 617 #define IVOR32 SPRN_IVOR32
618 #define IVOR33 SPRN_IVOR33 618 #define IVOR33 SPRN_IVOR33
619 #define IVOR34 SPRN_IVOR34 619 #define IVOR34 SPRN_IVOR34
620 #define IVOR35 SPRN_IVOR35 620 #define IVOR35 SPRN_IVOR35
621 #define MCSRR0 SPRN_MCSRR0 621 #define MCSRR0 SPRN_MCSRR0
622 #define MCSRR1 SPRN_MCSRR1 622 #define MCSRR1 SPRN_MCSRR1
623 #define L1CSR0 SPRN_L1CSR0 623 #define L1CSR0 SPRN_L1CSR0
624 #define L1CSR1 SPRN_L1CSR1 624 #define L1CSR1 SPRN_L1CSR1
625 #define L1CFG0 SPRN_L1CFG0 625 #define L1CFG0 SPRN_L1CFG0
626 #define L1CFG1 SPRN_L1CFG1 626 #define L1CFG1 SPRN_L1CFG1
627 #define MCSR SPRN_MCSR 627 #define MCSR SPRN_MCSR
628 #define MMUCSR0 SPRN_MMUCSR0 628 #define MMUCSR0 SPRN_MMUCSR0
629 #define BUCSR SPRN_BUCSR 629 #define BUCSR SPRN_BUCSR
630 #define PID0 SPRN_PID 630 #define PID0 SPRN_PID
631 #define PID1 SPRN_PID1 631 #define PID1 SPRN_PID1
632 #define PID2 SPRN_PID2 632 #define PID2 SPRN_PID2
633 #define MAS0 SPRN_MAS0 633 #define MAS0 SPRN_MAS0
634 #define MAS1 SPRN_MAS1 634 #define MAS1 SPRN_MAS1
635 #define MAS2 SPRN_MAS2 635 #define MAS2 SPRN_MAS2
636 #define MAS3 SPRN_MAS3 636 #define MAS3 SPRN_MAS3
637 #define MAS4 SPRN_MAS4 637 #define MAS4 SPRN_MAS4
638 #define MAS5 SPRN_MAS5 638 #define MAS5 SPRN_MAS5
639 #define MAS6 SPRN_MAS6 639 #define MAS6 SPRN_MAS6
640 #define MAS7 SPRN_MAS7 640 #define MAS7 SPRN_MAS7
641 641
642 #if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx) 642 #if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx)
643 #define DAR_DEAR DEAR 643 #define DAR_DEAR DEAR
644 #else 644 #else
645 #define DAR_DEAR DAR 645 #define DAR_DEAR DAR
646 #endif 646 #endif
647 647
648 /* Device Control Registers */ 648 /* Device Control Registers */
649 649
650 #define DCRN_BEAR 0x090 /* Bus Error Address Register */ 650 #define DCRN_BEAR 0x090 /* Bus Error Address Register */
651 #define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ 651 #define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
652 #define BESR_DSES 0x80000000 /* Data-Side Error Status */ 652 #define BESR_DSES 0x80000000 /* Data-Side Error Status */
653 #define BESR_DMES 0x40000000 /* DMA Error Status */ 653 #define BESR_DMES 0x40000000 /* DMA Error Status */
654 #define BESR_RWS 0x20000000 /* Read/Write Status */ 654 #define BESR_RWS 0x20000000 /* Read/Write Status */
655 #define BESR_ETMASK 0x1C000000 /* Error Type */ 655 #define BESR_ETMASK 0x1C000000 /* Error Type */
656 #define ET_PROT 0 656 #define ET_PROT 0
657 #define ET_PARITY 1 657 #define ET_PARITY 1
658 #define ET_NCFG 2 658 #define ET_NCFG 2
659 #define ET_BUSERR 4 659 #define ET_BUSERR 4
660 #define ET_BUSTO 6 660 #define ET_BUSTO 6
661 #define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */ 661 #define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */
662 #define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */ 662 #define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */
663 #define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */ 663 #define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */
664 #define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */ 664 #define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */
665 #define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */ 665 #define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */
666 #define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */ 666 #define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */
667 #define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */ 667 #define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */
668 #define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */ 668 #define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */
669 #define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */ 669 #define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */
670 #define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */ 670 #define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */
671 #define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */ 671 #define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */
672 #define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */ 672 #define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */
673 #define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */ 673 #define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */
674 #define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */ 674 #define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */
675 #define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */ 675 #define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */
676 #define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */ 676 #define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */
677 #define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */ 677 #define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */
678 #define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */ 678 #define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */
679 #define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */ 679 #define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */
680 #define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */ 680 #define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */
681 #define DCRN_DMASR 0x0E0 /* DMA Status Register */ 681 #define DCRN_DMASR 0x0E0 /* DMA Status Register */
682 #define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ 682 #define DCRN_EXIER 0x042 /* External Interrupt Enable Register */
683 #define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ 683 #define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
684 #define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ 684 #define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
685 #define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ 685 #define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
686 #define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ 686 #define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
687 #define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ 687 #define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
688 #define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ 688 #define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
689 #define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ 689 #define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
690 #define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ 690 #define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
691 #define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ 691 #define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
692 #define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ 692 #define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
693 #define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ 693 #define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
694 #define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ 694 #define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
695 #define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ 695 #define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
696 #define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ 696 #define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
697 #define DCRN_EXISR 0x040 /* External Interrupt Status Register */ 697 #define DCRN_EXISR 0x040 /* External Interrupt Status Register */
698 #define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ 698 #define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */
699 #define IOCR_E0TE 0x80000000 699 #define IOCR_E0TE 0x80000000
700 #define IOCR_E0LP 0x40000000 700 #define IOCR_E0LP 0x40000000
701 #define IOCR_E1TE 0x20000000 701 #define IOCR_E1TE 0x20000000
702 #define IOCR_E1LP 0x10000000 702 #define IOCR_E1LP 0x10000000
703 #define IOCR_E2TE 0x08000000 703 #define IOCR_E2TE 0x08000000
704 #define IOCR_E2LP 0x04000000 704 #define IOCR_E2LP 0x04000000
705 #define IOCR_E3TE 0x02000000 705 #define IOCR_E3TE 0x02000000
706 #define IOCR_E3LP 0x01000000 706 #define IOCR_E3LP 0x01000000
707 #define IOCR_E4TE 0x00800000 707 #define IOCR_E4TE 0x00800000
708 #define IOCR_E4LP 0x00400000 708 #define IOCR_E4LP 0x00400000
709 #define IOCR_EDT 0x00080000 709 #define IOCR_EDT 0x00080000
710 #define IOCR_SOR 0x00040000 710 #define IOCR_SOR 0x00040000
711 #define IOCR_EDO 0x00008000 711 #define IOCR_EDO 0x00008000
712 #define IOCR_2XC 0x00004000 712 #define IOCR_2XC 0x00004000
713 #define IOCR_ATC 0x00002000 713 #define IOCR_ATC 0x00002000
714 #define IOCR_SPD 0x00001000 714 #define IOCR_SPD 0x00001000
715 #define IOCR_BEM 0x00000800 715 #define IOCR_BEM 0x00000800
716 #define IOCR_PTD 0x00000400 716 #define IOCR_PTD 0x00000400
717 #define IOCR_ARE 0x00000080 717 #define IOCR_ARE 0x00000080
718 #define IOCR_DRC 0x00000020 718 #define IOCR_DRC 0x00000020
719 #define IOCR_RDM(x) (((x) & 0x3) << 3) 719 #define IOCR_RDM(x) (((x) & 0x3) << 3)
720 #define IOCR_TCS 0x00000004 720 #define IOCR_TCS 0x00000004
721 #define IOCR_SCS 0x00000002 721 #define IOCR_SCS 0x00000002
722 #define IOCR_SPC 0x00000001 722 #define IOCR_SPC 0x00000001
723 723
724 /* System-On-Chip Version Register */ 724 /* System-On-Chip Version Register */
725 725
726 /* System-On-Chip Version Register (SVR) field extraction */ 726 /* System-On-Chip Version Register (SVR) field extraction */
727 727
728 #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ 728 #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
729 #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ 729 #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
730 730
731 #define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ 731 #define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */
732 #define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ 732 #define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */
733 #define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ 733 #define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */
734 #define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ 734 #define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */
735 #define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ 735 #define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */
736 #define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ 736 #define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */
737 #define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ 737 #define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */
738 738
739 /* Processor Version Register */ 739 /* Processor Version Register */
740 740
741 /* Processor Version Register (PVR) field extraction */ 741 /* Processor Version Register (PVR) field extraction */
742 742
743 #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ 743 #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
744 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ 744 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
745 745
746 /* 746 /*
747 * AMCC has further subdivided the standard PowerPC 16-bit version and 747 * AMCC has further subdivided the standard PowerPC 16-bit version and
748 * revision subfields of the PVR for the PowerPC 403s into the following: 748 * revision subfields of the PVR for the PowerPC 403s into the following:
749 */ 749 */
750 750
751 #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ 751 #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
752 #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ 752 #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
753 #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ 753 #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
754 #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ 754 #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
755 #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ 755 #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
756 #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ 756 #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
757 757
758 /* Processor Version Numbers */ 758 /* Processor Version Numbers */
759 759
760 #define PVR_403GA 0x00200000 760 #define PVR_403GA 0x00200000
761 #define PVR_403GB 0x00200100 761 #define PVR_403GB 0x00200100
762 #define PVR_403GC 0x00200200 762 #define PVR_403GC 0x00200200
763 #define PVR_403GCX 0x00201400 763 #define PVR_403GCX 0x00201400
764 #define PVR_405GP 0x40110000 764 #define PVR_405GP 0x40110000
765 #define PVR_405GP_RB 0x40110040 765 #define PVR_405GP_RB 0x40110040
766 #define PVR_405GP_RC 0x40110082 766 #define PVR_405GP_RC 0x40110082
767 #define PVR_405GP_RD 0x401100C4 767 #define PVR_405GP_RD 0x401100C4
768 #define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ 768 #define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */
769 #define PVR_405CR_RA 0x40110041 769 #define PVR_405CR_RA 0x40110041
770 #define PVR_405CR_RB 0x401100C5 770 #define PVR_405CR_RB 0x401100C5
771 #define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ 771 #define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
772 #define PVR_405EP_RA 0x51210950 772 #define PVR_405EP_RA 0x51210950
773 #define PVR_405GPR_RB 0x50910951 773 #define PVR_405GPR_RB 0x50910951
774 #define PVR_405EZ_RA 0x41511460 774 #define PVR_405EZ_RA 0x41511460
775 #define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A with Security */ 775 #define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A/B with Security */
776 #define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A without Security */ 776 #define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */
777 #define PVR_405EX1_RA 0x12911477 /* 405EX rev A with Security */ 777 #define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */
778 #define PVR_405EX2_RA 0x12911475 /* 405EX rev A without Security */ 778 #define PVR_405EX2_RA 0x12911475 /* 405EX rev A/B without Security */
779 #define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */
780 #define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */
781 #define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */
782 #define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */
779 #define PVR_440GP_RB 0x40120440 783 #define PVR_440GP_RB 0x40120440
780 #define PVR_440GP_RC 0x40120481 784 #define PVR_440GP_RC 0x40120481
781 #define PVR_440EP_RA 0x42221850 785 #define PVR_440EP_RA 0x42221850
782 #define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ 786 #define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
783 #define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ 787 #define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
784 #define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ 788 #define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
785 #define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ 789 #define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
786 #define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ 790 #define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */
787 #define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ 791 #define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */
788 #define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */ 792 #define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */
789 #define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */ 793 #define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */
790 #define PVR_440GX_RA 0x51B21850 794 #define PVR_440GX_RA 0x51B21850
791 #define PVR_440GX_RB 0x51B21851 795 #define PVR_440GX_RB 0x51B21851
792 #define PVR_440GX_RC 0x51B21892 796 #define PVR_440GX_RC 0x51B21892
793 #define PVR_440GX_RF 0x51B21894 797 #define PVR_440GX_RF 0x51B21894
794 #define PVR_405EP_RB 0x51210950 798 #define PVR_405EP_RB 0x51210950
795 #define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */ 799 #define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */
796 #define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */ 800 #define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */
797 #define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */ 801 #define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */
798 #define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */ 802 #define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */
799 #define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */ 803 #define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */
800 #define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ 804 #define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */
801 #define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ 805 #define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */
802 #define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ 806 #define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */
803 #define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ 807 #define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */
804 #define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ 808 #define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */
805 #define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ 809 #define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */
806 #define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ 810 #define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */
807 #define PVR_601 0x00010000 811 #define PVR_601 0x00010000
808 #define PVR_602 0x00050000 812 #define PVR_602 0x00050000
809 #define PVR_603 0x00030000 813 #define PVR_603 0x00030000
810 #define PVR_603e 0x00060000 814 #define PVR_603e 0x00060000
811 #define PVR_603ev 0x00070000 815 #define PVR_603ev 0x00070000
812 #define PVR_603r 0x00071000 816 #define PVR_603r 0x00071000
813 #define PVR_604 0x00040000 817 #define PVR_604 0x00040000
814 #define PVR_604e 0x00090000 818 #define PVR_604e 0x00090000
815 #define PVR_604r 0x000A0000 819 #define PVR_604r 0x000A0000
816 #define PVR_620 0x00140000 820 #define PVR_620 0x00140000
817 #define PVR_740 0x00080000 821 #define PVR_740 0x00080000
818 #define PVR_750 PVR_740 822 #define PVR_750 PVR_740
819 #define PVR_740P 0x10080000 823 #define PVR_740P 0x10080000
820 #define PVR_750P PVR_740P 824 #define PVR_750P PVR_740P
821 #define PVR_7400 0x000C0000 825 #define PVR_7400 0x000C0000
822 #define PVR_7410 0x800C0000 826 #define PVR_7410 0x800C0000
823 #define PVR_7450 0x80000000 827 #define PVR_7450 0x80000000
824 828
825 #define PVR_85xx 0x80200000 829 #define PVR_85xx 0x80200000
826 #define PVR_85xx_REV1 (PVR_85xx | 0x0010) 830 #define PVR_85xx_REV1 (PVR_85xx | 0x0010)
827 #define PVR_85xx_REV2 (PVR_85xx | 0x0020) 831 #define PVR_85xx_REV2 (PVR_85xx | 0x0020)
828 832
829 #define PVR_86xx 0x80040000 833 #define PVR_86xx 0x80040000
830 #define PVR_86xx_REV1 (PVR_86xx | 0x0010) 834 #define PVR_86xx_REV1 (PVR_86xx | 0x0010)
831 835
832 /* 836 /*
833 * For the 8xx processors, all of them report the same PVR family for 837 * For the 8xx processors, all of them report the same PVR family for
834 * the PowerPC core. The various versions of these processors must be 838 * the PowerPC core. The various versions of these processors must be
835 * differentiated by the version number in the Communication Processor 839 * differentiated by the version number in the Communication Processor
836 * Module (CPM). 840 * Module (CPM).
837 */ 841 */
838 #define PVR_821 0x00500000 842 #define PVR_821 0x00500000
839 #define PVR_823 PVR_821 843 #define PVR_823 PVR_821
840 #define PVR_850 PVR_821 844 #define PVR_850 PVR_821
841 #define PVR_860 PVR_821 845 #define PVR_860 PVR_821
842 #define PVR_7400 0x000C0000 846 #define PVR_7400 0x000C0000
843 #define PVR_8240 0x00810100 847 #define PVR_8240 0x00810100
844 848
845 /* 849 /*
846 * PowerQUICC II family processors report different PVR values depending 850 * PowerQUICC II family processors report different PVR values depending
847 * on silicon process (HiP3, HiP4, HiP7, etc.) 851 * on silicon process (HiP3, HiP4, HiP7, etc.)
848 */ 852 */
849 #define PVR_8260 PVR_8240 853 #define PVR_8260 PVR_8240
850 #define PVR_8260_HIP3 0x00810101 854 #define PVR_8260_HIP3 0x00810101
851 #define PVR_8260_HIP4 0x80811014 855 #define PVR_8260_HIP4 0x80811014
852 #define PVR_8260_HIP7 0x80822011 856 #define PVR_8260_HIP7 0x80822011
853 #define PVR_8260_HIP7R1 0x80822013 857 #define PVR_8260_HIP7R1 0x80822013
854 #define PVR_8260_HIP7RA 0x80822014 858 #define PVR_8260_HIP7RA 0x80822014
855 859
856 /* 860 /*
857 * MPC 52xx 861 * MPC 52xx
858 */ 862 */
859 #define PVR_5200 0x80822011 863 #define PVR_5200 0x80822011
860 #define PVR_5200B 0x80822014 864 #define PVR_5200B 0x80822014
861 865
862 /* 866 /*
863 * System Version Register 867 * System Version Register
864 */ 868 */
865 869
866 /* System Version Register (SVR) field extraction */ 870 /* System Version Register (SVR) field extraction */
867 871
868 #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ 872 #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
869 #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ 873 #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */
870 874
871 #define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ 875 #define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */
872 876
873 #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ 877 #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
874 #define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ 878 #define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
875 879
876 #define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ 880 #define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
877 #define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ 881 #define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
878 882
879 /* Some parts define SVR[0:23] as the SOC version */ 883 /* Some parts define SVR[0:23] as the SOC version */
880 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ 884 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */
881 885
882 /* 886 /*
883 * SVR_SOC_VER() Version Values 887 * SVR_SOC_VER() Version Values
884 */ 888 */
885 889
886 #define SVR_8533 0x803400 890 #define SVR_8533 0x803400
887 #define SVR_8533_E 0x803C00 891 #define SVR_8533_E 0x803C00
888 #define SVR_8540 0x803000 892 #define SVR_8540 0x803000
889 #define SVR_8541 0x807200 893 #define SVR_8541 0x807200
890 #define SVR_8541_E 0x807A00 894 #define SVR_8541_E 0x807A00
891 #define SVR_8543 0x803200 895 #define SVR_8543 0x803200
892 #define SVR_8543_E 0x803A00 896 #define SVR_8543_E 0x803A00
893 #define SVR_8544 0x803401 897 #define SVR_8544 0x803401
894 #define SVR_8544_E 0x803C01 898 #define SVR_8544_E 0x803C01
895 #define SVR_8545 0x803102 899 #define SVR_8545 0x803102
896 #define SVR_8545_E 0x803902 900 #define SVR_8545_E 0x803902
897 #define SVR_8547_E 0x803901 901 #define SVR_8547_E 0x803901
898 #define SVR_8548 0x803100 902 #define SVR_8548 0x803100
899 #define SVR_8548_E 0x803900 903 #define SVR_8548_E 0x803900
900 #define SVR_8555 0x807100 904 #define SVR_8555 0x807100
901 #define SVR_8555_E 0x807900 905 #define SVR_8555_E 0x807900
902 #define SVR_8560 0x807000 906 #define SVR_8560 0x807000
903 #define SVR_8567 0x807600 907 #define SVR_8567 0x807600
904 #define SVR_8567_E 0x807E00 908 #define SVR_8567_E 0x807E00
905 #define SVR_8568 0x807500 909 #define SVR_8568 0x807500
906 #define SVR_8568_E 0x807D00 910 #define SVR_8568_E 0x807D00
907 #define SVR_8572 0x80E000 911 #define SVR_8572 0x80E000
908 #define SVR_8572_E 0x80E800 912 #define SVR_8572_E 0x80E800
909 913
910 #define SVR_8610 0x80A000 914 #define SVR_8610 0x80A000
911 #define SVR_8641 0x809000 915 #define SVR_8641 0x809000
912 #define SVR_8641D 0x809001 916 #define SVR_8641D 0x809001
913 917
914 #define _GLOBAL(n)\ 918 #define _GLOBAL(n)\
915 .globl n;\ 919 .globl n;\
916 n: 920 n:
917 921
918 /* Macros for setting and retrieving special purpose registers */ 922 /* Macros for setting and retrieving special purpose registers */
919 923
920 #define stringify(s) tostring(s) 924 #define stringify(s) tostring(s)
921 #define tostring(s) #s 925 #define tostring(s) #s
922 926
923 #define mfdcr(rn) ({unsigned int rval; \ 927 #define mfdcr(rn) ({unsigned int rval; \
924 asm volatile("mfdcr %0," stringify(rn) \ 928 asm volatile("mfdcr %0," stringify(rn) \
925 : "=r" (rval)); rval;}) 929 : "=r" (rval)); rval;})
926 #define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) 930 #define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
927 931
928 #define mfmsr() ({unsigned int rval; \ 932 #define mfmsr() ({unsigned int rval; \
929 asm volatile("mfmsr %0" : "=r" (rval)); rval;}) 933 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
930 #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) 934 #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
931 935
932 #define mfspr(rn) ({unsigned int rval; \ 936 #define mfspr(rn) ({unsigned int rval; \
933 asm volatile("mfspr %0," stringify(rn) \ 937 asm volatile("mfspr %0," stringify(rn) \
934 : "=r" (rval)); rval;}) 938 : "=r" (rval)); rval;})
935 #define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) 939 #define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
936 940
937 #define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) 941 #define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v))
938 942
939 /* Segment Registers */ 943 /* Segment Registers */
940 944
941 #define SR0 0 945 #define SR0 0
942 #define SR1 1 946 #define SR1 1
943 #define SR2 2 947 #define SR2 2
944 #define SR3 3 948 #define SR3 3
945 #define SR4 4 949 #define SR4 4
946 #define SR5 5 950 #define SR5 5
947 #define SR6 6 951 #define SR6 6
948 #define SR7 7 952 #define SR7 7
949 #define SR8 8 953 #define SR8 8
950 #define SR9 9 954 #define SR9 9
951 #define SR10 10 955 #define SR10 10
952 #define SR11 11 956 #define SR11 11
953 #define SR12 12 957 #define SR12 12
954 #define SR13 13 958 #define SR13 13
955 #define SR14 14 959 #define SR14 14
956 #define SR15 15 960 #define SR15 15
957 961
958 #ifndef __ASSEMBLY__ 962 #ifndef __ASSEMBLY__
959 #ifndef CONFIG_MACH_SPECIFIC 963 #ifndef CONFIG_MACH_SPECIFIC
960 extern int _machine; 964 extern int _machine;
961 extern int have_of; 965 extern int have_of;
962 #endif /* CONFIG_MACH_SPECIFIC */ 966 #endif /* CONFIG_MACH_SPECIFIC */
963 967
964 /* what kind of prep workstation we are */ 968 /* what kind of prep workstation we are */
965 extern int _prep_type; 969 extern int _prep_type;
966 /* 970 /*
967 * This is used to identify the board type from a given PReP board 971 * This is used to identify the board type from a given PReP board
968 * vendor. Board revision is also made available. 972 * vendor. Board revision is also made available.
969 */ 973 */
970 extern unsigned char ucSystemType; 974 extern unsigned char ucSystemType;
971 extern unsigned char ucBoardRev; 975 extern unsigned char ucBoardRev;
972 extern unsigned char ucBoardRevMaj, ucBoardRevMin; 976 extern unsigned char ucBoardRevMaj, ucBoardRevMin;
973 977
974 struct task_struct; 978 struct task_struct;
975 void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp); 979 void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
976 void release_thread(struct task_struct *); 980 void release_thread(struct task_struct *);
977 981
978 /* 982 /*
979 * Create a new kernel thread. 983 * Create a new kernel thread.
980 */ 984 */
981 extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); 985 extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
982 986
983 /* 987 /*
984 * Bus types 988 * Bus types
985 */ 989 */
986 #define EISA_bus 0 990 #define EISA_bus 0
987 #define EISA_bus__is_a_macro /* for versions in ksyms.c */ 991 #define EISA_bus__is_a_macro /* for versions in ksyms.c */
988 #define MCA_bus 0 992 #define MCA_bus 0
989 #define MCA_bus__is_a_macro /* for versions in ksyms.c */ 993 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
990 994
991 /* Lazy FPU handling on uni-processor */ 995 /* Lazy FPU handling on uni-processor */
992 extern struct task_struct *last_task_used_math; 996 extern struct task_struct *last_task_used_math;
993 extern struct task_struct *last_task_used_altivec; 997 extern struct task_struct *last_task_used_altivec;
994 998
995 /* 999 /*
996 * this is the minimum allowable io space due to the location 1000 * this is the minimum allowable io space due to the location
997 * of the io areas on prep (first one at 0x80000000) but 1001 * of the io areas on prep (first one at 0x80000000) but
998 * as soon as I get around to remapping the io areas with the BATs 1002 * as soon as I get around to remapping the io areas with the BATs
999 * to match the mac we can raise this. -- Cort 1003 * to match the mac we can raise this. -- Cort
1000 */ 1004 */
1001 #define TASK_SIZE (0x80000000UL) 1005 #define TASK_SIZE (0x80000000UL)
1002 1006
1003 /* This decides where the kernel will search for a free chunk of vm 1007 /* This decides where the kernel will search for a free chunk of vm
1004 * space during mmap's. 1008 * space during mmap's.
1005 */ 1009 */
1006 #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) 1010 #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
1007 1011
1008 typedef struct { 1012 typedef struct {
1009 unsigned long seg; 1013 unsigned long seg;
1010 } mm_segment_t; 1014 } mm_segment_t;
1011 1015
1012 struct thread_struct { 1016 struct thread_struct {
1013 unsigned long ksp; /* Kernel stack pointer */ 1017 unsigned long ksp; /* Kernel stack pointer */
1014 unsigned long wchan; /* Event task is sleeping on */ 1018 unsigned long wchan; /* Event task is sleeping on */
1015 struct pt_regs *regs; /* Pointer to saved register state */ 1019 struct pt_regs *regs; /* Pointer to saved register state */
1016 mm_segment_t fs; /* for get_fs() validation */ 1020 mm_segment_t fs; /* for get_fs() validation */
1017 void *pgdir; /* root of page-table tree */ 1021 void *pgdir; /* root of page-table tree */
1018 signed long last_syscall; 1022 signed long last_syscall;
1019 double fpr[32]; /* Complete floating point set */ 1023 double fpr[32]; /* Complete floating point set */
1020 unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ 1024 unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
1021 unsigned long fpscr; /* Floating point status */ 1025 unsigned long fpscr; /* Floating point status */
1022 #ifdef CONFIG_ALTIVEC 1026 #ifdef CONFIG_ALTIVEC
1023 vector128 vr[32]; /* Complete AltiVec set */ 1027 vector128 vr[32]; /* Complete AltiVec set */
1024 vector128 vscr; /* AltiVec status */ 1028 vector128 vscr; /* AltiVec status */
1025 unsigned long vrsave; 1029 unsigned long vrsave;
1026 #endif /* CONFIG_ALTIVEC */ 1030 #endif /* CONFIG_ALTIVEC */
1027 }; 1031 };
1028 1032
1029 #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) 1033 #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
1030 1034
1031 #define INIT_THREAD { \ 1035 #define INIT_THREAD { \
1032 INIT_SP, /* ksp */ \ 1036 INIT_SP, /* ksp */ \
1033 0, /* wchan */ \ 1037 0, /* wchan */ \
1034 (struct pt_regs *)INIT_SP - 1, /* regs */ \ 1038 (struct pt_regs *)INIT_SP - 1, /* regs */ \
1035 KERNEL_DS, /*fs*/ \ 1039 KERNEL_DS, /*fs*/ \
1036 swapper_pg_dir, /* pgdir */ \ 1040 swapper_pg_dir, /* pgdir */ \
1037 0, /* last_syscall */ \ 1041 0, /* last_syscall */ \
1038 {0}, 0, 0 \ 1042 {0}, 0, 0 \
1039 } 1043 }
1040 1044
1041 /* 1045 /*
1042 * Note: the vm_start and vm_end fields here should *not* 1046 * Note: the vm_start and vm_end fields here should *not*
1043 * be in kernel space. (Could vm_end == vm_start perhaps?) 1047 * be in kernel space. (Could vm_end == vm_start perhaps?)
1044 */ 1048 */
1045 #define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \ 1049 #define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
1046 PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ 1050 PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
1047 1, NULL, NULL } 1051 1, NULL, NULL }
1048 1052
1049 /* 1053 /*
1050 * Return saved PC of a blocked thread. For now, this is the "user" PC 1054 * Return saved PC of a blocked thread. For now, this is the "user" PC
1051 */ 1055 */
1052 static inline unsigned long thread_saved_pc(struct thread_struct *t) 1056 static inline unsigned long thread_saved_pc(struct thread_struct *t)
1053 { 1057 {
1054 return (t->regs) ? t->regs->nip : 0; 1058 return (t->regs) ? t->regs->nip : 0;
1055 } 1059 }
1056 1060
1057 #define copy_segments(tsk, mm) do { } while (0) 1061 #define copy_segments(tsk, mm) do { } while (0)
1058 #define release_segments(mm) do { } while (0) 1062 #define release_segments(mm) do { } while (0)
1059 #define forget_segments() do { } while (0) 1063 #define forget_segments() do { } while (0)
1060 1064
1061 unsigned long get_wchan(struct task_struct *p); 1065 unsigned long get_wchan(struct task_struct *p);
1062 1066
1063 #define KSTK_EIP(tsk) ((tsk)->thread.regs->nip) 1067 #define KSTK_EIP(tsk) ((tsk)->thread.regs->nip)
1064 #define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1]) 1068 #define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1])
1065 1069
1066 /* 1070 /*
1067 * NOTE! The task struct and the stack go together 1071 * NOTE! The task struct and the stack go together
1068 */ 1072 */
1069 #define THREAD_SIZE (2*PAGE_SIZE) 1073 #define THREAD_SIZE (2*PAGE_SIZE)
1070 #define alloc_task_struct() \ 1074 #define alloc_task_struct() \
1071 ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) 1075 ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
1072 #define free_task_struct(p) free_pages((unsigned long)(p),1) 1076 #define free_task_struct(p) free_pages((unsigned long)(p),1)
1073 #define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) 1077 #define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
1074 1078
1075 /* in process.c - for early bootup debug -- Cort */ 1079 /* in process.c - for early bootup debug -- Cort */
1076 int ll_printk(const char *, ...); 1080 int ll_printk(const char *, ...);
1077 void ll_puts(const char *); 1081 void ll_puts(const char *);
1078 1082
1079 #define init_task (init_task_union.task) 1083 #define init_task (init_task_union.task)
1080 #define init_stack (init_task_union.stack) 1084 #define init_stack (init_task_union.stack)
1081 1085
1082 /* In misc.c */ 1086 /* In misc.c */
1083 void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); 1087 void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
1084 1088
1085 #endif /* ndef ASSEMBLY*/ 1089 #endif /* ndef ASSEMBLY*/
1086 1090
1087 #ifdef CONFIG_MACH_SPECIFIC 1091 #ifdef CONFIG_MACH_SPECIFIC
1088 #if defined(CONFIG_8xx) 1092 #if defined(CONFIG_8xx)
1089 #define _machine _MACH_8xx 1093 #define _machine _MACH_8xx
1090 #define have_of 0 1094 #define have_of 0
1091 #elif defined(CONFIG_OAK) 1095 #elif defined(CONFIG_OAK)
1092 #define _machine _MACH_oak 1096 #define _machine _MACH_oak
1093 #define have_of 0 1097 #define have_of 0
1094 #elif defined(CONFIG_WALNUT) 1098 #elif defined(CONFIG_WALNUT)
1095 #define _machine _MACH_walnut 1099 #define _machine _MACH_walnut
1096 #define have_of 0 1100 #define have_of 0
1097 #elif defined(CONFIG_APUS) 1101 #elif defined(CONFIG_APUS)
1098 #define _machine _MACH_apus 1102 #define _machine _MACH_apus
1099 #define have_of 0 1103 #define have_of 0
1100 #elif defined(CONFIG_GEMINI) 1104 #elif defined(CONFIG_GEMINI)
1101 #define _machine _MACH_gemini 1105 #define _machine _MACH_gemini
1102 #define have_of 0 1106 #define have_of 0
1103 #elif defined(CONFIG_8260) 1107 #elif defined(CONFIG_8260)
1104 #define _machine _MACH_8260 1108 #define _machine _MACH_8260
1105 #define have_of 0 1109 #define have_of 0
1106 #elif defined(CONFIG_SANDPOINT) 1110 #elif defined(CONFIG_SANDPOINT)
1107 #define _machine _MACH_sandpoint 1111 #define _machine _MACH_sandpoint
1108 #elif defined(CONFIG_HIDDEN_DRAGON) 1112 #elif defined(CONFIG_HIDDEN_DRAGON)
1109 #define _machine _MACH_hidden_dragon 1113 #define _machine _MACH_hidden_dragon
1110 #define have_of 0 1114 #define have_of 0
1111 #else 1115 #else
1112 #error "Machine not defined correctly" 1116 #error "Machine not defined correctly"
1113 #endif 1117 #endif
1114 #endif /* CONFIG_MACH_SPECIFIC */ 1118 #endif /* CONFIG_MACH_SPECIFIC */
1115 1119
1116 #endif /* __ASM_PPC_PROCESSOR_H */ 1120 #endif /* __ASM_PPC_PROCESSOR_H */
1117 1121