Eric Lee / smarc-uboot | Embedian Git Server

Commit 3a34cae01160d207d50db267585b963cf0a0018d

Authored by Bin Meng 2017-04-21 22:24:37 +0800

x86: acpi: Resume OS if resume vector is found

In an S3 resume path, U-Boot does everything like a cold boot except
in the last_stage_init() it jumps to the OS resume vector.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>

Showing 4 changed files with 45 additions and 0 deletions Inline Diff

arch/x86/cpu/cpu.c
arch/x86/include/asm/acpi_s3.h
arch/x86/lib/Makefile
arch/x86/lib/acpi_s3.c

arch/x86/cpu/cpu.c

Diff comments View file @ 3a34cae

 /*
  * (C) Copyright 2008-2011
  * Graeme Russ, <graeme.russ@gmail.com>
  *
  * (C) Copyright 2002
  * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
  *
  * (C) Copyright 2002
  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Marius Groeger <mgroeger@sysgo.de>
  *
  * (C) Copyright 2002
  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Alex Zuepke <azu@sysgo.de>
  *
  * Part of this file is adapted from coreboot
  * src/arch/x86/lib/cpu.c
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <command.h>
 #include <dm.h>
 #include <errno.h>
 #include <malloc.h>
 #include <syscon.h>
 #include <asm/acpi_s3.h>
+#include <asm/acpi_table.h>
 #include <asm/control_regs.h>
 #include <asm/coreboot_tables.h>
 #include <asm/cpu.h>
 #include <asm/lapic.h>
 #include <asm/microcode.h>
 #include <asm/mp.h>
 #include <asm/mrccache.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/processor-flags.h>
 #include <asm/interrupt.h>
 #include <asm/tables.h>
 #include <linux/compiler.h>
 DECLARE_GLOBAL_DATA_PTR;
 static const char *const x86_vendor_name[] = {
 	[X86_VENDOR_INTEL]     = "Intel",
 	[X86_VENDOR_CYRIX]     = "Cyrix",
 	[X86_VENDOR_AMD]       = "AMD",
 	[X86_VENDOR_UMC]       = "UMC",
 	[X86_VENDOR_NEXGEN]    = "NexGen",
 	[X86_VENDOR_CENTAUR]   = "Centaur",
 	[X86_VENDOR_RISE]      = "Rise",
 	[X86_VENDOR_TRANSMETA] = "Transmeta",
 	[X86_VENDOR_NSC]       = "NSC",
 	[X86_VENDOR_SIS]       = "SiS",
 };
 int __weak x86_cleanup_before_linux(void)
 {
 #ifdef CONFIG_BOOTSTAGE_STASH
 	bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
 			CONFIG_BOOTSTAGE_STASH_SIZE);
 #endif
 	return 0;
 }
 int x86_init_cache(void)
 {
 	enable_caches();
 	return 0;
 }
 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	printf("resetting ...\n");
 	/* wait 50 ms */
 	udelay(50000);
 	disable_interrupts();
 	reset_cpu(0);
 	/*NOTREACHED*/
 	return 0;
 }
 void  flush_cache(unsigned long dummy1, unsigned long dummy2)
 {
 	asm("wbinvd\n");
 }
 __weak void reset_cpu(ulong addr)
 {
 	/* Do a hard reset through the chipset's reset control register */
 	outb(SYS_RST | RST_CPU, IO_PORT_RESET);
 	for (;;)
 		cpu_hlt();
 }
 void x86_full_reset(void)
 {
 	outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
 }
 /* Define these functions to allow ehch-hcd to function */
 void flush_dcache_range(unsigned long start, unsigned long stop)
 {
 }
 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
 }
 void dcache_enable(void)
 {
 	enable_caches();
 }
 void dcache_disable(void)
 {
 	disable_caches();
 }
 void icache_enable(void)
 {
 }
 void icache_disable(void)
 {
 }
 int icache_status(void)
 {
 	return 1;
 }
 const char *cpu_vendor_name(int vendor)
 {
 	const char *name;
 	name = "<invalid cpu vendor>";
 	if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
 	    (x86_vendor_name[vendor] != 0))
 		name = x86_vendor_name[vendor];
 	return name;
 }
 char *cpu_get_name(char *name)
 {
 	unsigned int *name_as_ints = (unsigned int *)name;
 	struct cpuid_result regs;
 	char *ptr;
 	int i;
 	/* This bit adds up to 48 bytes */
 	for (i = 0; i < 3; i++) {
 		regs = cpuid(0x80000002 + i);
 		name_as_ints[i * 4 + 0] = regs.eax;
 		name_as_ints[i * 4 + 1] = regs.ebx;
 		name_as_ints[i * 4 + 2] = regs.ecx;
 		name_as_ints[i * 4 + 3] = regs.edx;
 	}
 	name[CPU_MAX_NAME_LEN - 1] = '\0';
 	/* Skip leading spaces. */
 	ptr = name;
 	while (*ptr == ' ')
 		ptr++;
 	return ptr;
 }
 int default_print_cpuinfo(void)
 {
 	printf("CPU: %s, vendor %s, device %xh\n",
 	       cpu_has_64bit() ? "x86_64" : "x86",
 	       cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
 #ifdef CONFIG_HAVE_ACPI_RESUME
 	debug("ACPI previous sleep state: %s\n",
 	      acpi_ss_string(gd->arch.prev_sleep_state));
 #endif
 	return 0;
 }
 void show_boot_progress(int val)
 {
 	outb(val, POST_PORT);
 }
 #ifndef CONFIG_SYS_COREBOOT
 /*
  * Implement a weak default function for boards that optionally
  * need to clean up the system before jumping to the kernel.
  */
 __weak void board_final_cleanup(void)
 {
 }
 int last_stage_init(void)
 {
+#if CONFIG_HAVE_ACPI_RESUME
+	void *wake_vector = acpi_find_wakeup_vector();
+	if (wake_vector != NULL && gd->arch.prev_sleep_state == ACPI_S3)
+		acpi_resume(wake_vector);
+#endif
 	write_tables();
 	board_final_cleanup();
 	return 0;
 }
 #endif
 static int x86_init_cpus(void)
 {
 #ifdef CONFIG_SMP
 	debug("Init additional CPUs\n");
 	x86_mp_init();
 #else
 	struct udevice *dev;
 	/*
 	 * This causes the cpu-x86 driver to be probed.
 	 * We don't check return value here as we want to allow boards
 	 * which have not been converted to use cpu uclass driver to boot.
 	 */
 	uclass_first_device(UCLASS_CPU, &dev);
 #endif
 	return 0;
 }
 int cpu_init_r(void)
 {
 	struct udevice *dev;
 	int ret;
 	if (!ll_boot_init())
 		return 0;
 	ret = x86_init_cpus();
 	if (ret)
 		return ret;
 	/*
 	 * Set up the northbridge, PCH and LPC if available. Note that these
 	 * may have had some limited pre-relocation init if they were probed
 	 * before relocation, but this is post relocation.
 	 */
 	uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
 	uclass_first_device(UCLASS_PCH, &dev);
 	uclass_first_device(UCLASS_LPC, &dev);
 	/* Set up pin control if available */
 	ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
 	debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
 	return 0;
 }
 #ifndef CONFIG_EFI_STUB
 int reserve_arch(void)
 {
 #ifdef CONFIG_ENABLE_MRC_CACHE
 	mrccache_reserve();
 #endif
 #ifdef CONFIG_SEABIOS
 	high_table_reserve();
 #endif
 	return 0;
 }
 #endif

arch/x86/include/asm/acpi_s3.h

Diff comments View file @ 3a34cae

 /*
  * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __ASM_ACPI_S3_H__
 #define __ASM_ACPI_S3_H__
 #define WAKEUP_BASE	0x600
 /* PM1_STATUS register */
 #define WAK_STS		(1 << 15)
 #define PCIEXPWAK_STS	(1 << 14)
 #define RTC_STS		(1 << 10)
 #define SLPBTN_STS	(1 << 9)
 #define PWRBTN_STS	(1 << 8)
 #define GBL_STS		(1 << 5)
 #define BM_STS		(1 << 4)
 #define TMR_STS		(1 << 0)
 /* PM1_CNT register */
 #define SLP_EN		(1 << 13)
 #define SLP_TYP_SHIFT	10
 #define SLP_TYP		(7 << SLP_TYP_SHIFT)
 #define SLP_TYP_S0	0
 #define SLP_TYP_S1	1
 #define SLP_TYP_S3	5
 #define SLP_TYP_S4	6
 #define SLP_TYP_S5	7
 #ifndef __ASSEMBLY__
 extern char __wakeup[];
 extern int __wakeup_size;
 enum acpi_sleep_state {
 	ACPI_S0,
 	ACPI_S1,
 	ACPI_S2,
 	ACPI_S3,
 	ACPI_S4,
 	ACPI_S5,
 };
 /**
  * acpi_ss_string() - get ACPI-defined sleep state string
  *
  * @pm1_cnt:	ACPI-defined sleep state
  * @return:	a pointer to the sleep state string.
  */
 static inline char *acpi_ss_string(enum acpi_sleep_state state)
 {
 	char *ss_string[] = { "S0", "S1", "S2", "S3", "S4", "S5"};
 	return ss_string[state];
 }
 /**
  * acpi_sleep_from_pm1() - get ACPI-defined sleep state from PM1_CNT register
  *
  * @pm1_cnt:	PM1_CNT register value
  * @return:	ACPI-defined sleep state if given valid PM1_CNT register value,
  *		-EINVAL otherwise.
  */
 static inline enum acpi_sleep_state acpi_sleep_from_pm1(u32 pm1_cnt)
 {
 	switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
 	case SLP_TYP_S0:
 		return ACPI_S0;
 	case SLP_TYP_S1:
 		return ACPI_S1;
 	case SLP_TYP_S3:
 		return ACPI_S3;
 	case SLP_TYP_S4:
 		return ACPI_S4;
 	case SLP_TYP_S5:
 		return ACPI_S5;
 	}
 	return -EINVAL;
 }
 /**
  * chipset_prev_sleep_state() - Get chipset previous sleep state
  *
  * This returns chipset previous sleep state from ACPI registers.
  * Platform codes must supply this routine in order to support ACPI S3.
  *
  * @return ACPI_S0/S1/S2/S3/S4/S5.
  */
 enum acpi_sleep_state chipset_prev_sleep_state(void);
 /**
  * chipset_clear_sleep_state() - Clear chipset sleep state
  *
  * This clears chipset sleep state in ACPI registers.
  * Platform codes must supply this routine in order to support ACPI S3.
  */
 void chipset_clear_sleep_state(void);
+/**
+ * acpi_resume() - Do ACPI S3 resume
+ *
+ * This calls U-Boot wake up assembly stub and jumps to OS's wake up vector.
+ *
+ * @wake_vec:	OS wake up vector
+ * @return:	Never returns
+ */
+void acpi_resume(void *wake_vec);
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_ACPI_S3_H__ */

arch/x86/lib/Makefile

Diff comments View file @ 3a34cae

 #
 # (C) Copyright 2002-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 ifndef CONFIG_X86_64
 obj-y += bios.o
 obj-y += bios_asm.o
 obj-y += bios_interrupts.o
 endif
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 endif
 obj-y	+= cmd_boot.o
 obj-$(CONFIG_SEABIOS) += coreboot_table.o
 obj-$(CONFIG_EFI) += efi/
 obj-y	+= e820.o
 obj-y	+= gcc.o
 obj-y	+= init_helpers.o
 obj-y	+= interrupts.o
 obj-y	+= lpc-uclass.o
 obj-y	+= mpspec.o
 obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o
 obj-y += cmd_mtrr.o
 obj-y	+= northbridge-uclass.o
 obj-$(CONFIG_I8259_PIC) += i8259.o
 obj-$(CONFIG_I8254_TIMER) += i8254.o
 obj-y	+= pinctrl_ich6.o
 obj-y	+= pirq_routing.o
 obj-y	+= relocate.o
 obj-y += physmem.o
 obj-$(CONFIG_INTEL_MID) += pmu.o
 obj-$(CONFIG_X86_RAMTEST) += ramtest.o
 obj-$(CONFIG_INTEL_MID) += scu.o
 obj-y	+= sections.o
 obj-y += sfi.o
 obj-y	+= string.o
+obj-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.o
 ifndef CONFIG_QEMU
 obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
 endif
 obj-y	+= tables.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CMD_ZBOOT)	+= zimage.o
 endif
 obj-$(CONFIG_HAVE_FSP) += fsp/
 obj-$(CONFIG_SPL_BUILD) += spl.o
 extra-$(CONFIG_USE_PRIVATE_LIBGCC) += lib.a
 NORMAL_LIBGCC = $(shell $(CC) $(PLATFORM_CPPFLAGS) -print-libgcc-file-name)
 OBJCOPYFLAGS := --prefix-symbols=__normal_
 $(obj)/lib.a: $(NORMAL_LIBGCC) FORCE
 	$(call if_changed,objcopy)
 ifeq ($(CONFIG_$(SPL_)X86_64),)
 obj-$(CONFIG_EFI_APP) += crt0_ia32_efi.o reloc_ia32_efi.o
 endif
 ifneq ($(CONFIG_EFI_STUB),)
 CFLAGS_REMOVE_reloc_ia32_efi.o += -mregparm=3
 CFLAGS_reloc_ia32_efi.o += -fpic -fshort-wchar
 # When building for 64-bit we must remove the i386-specific flags
 CFLAGS_REMOVE_reloc_x86_64_efi.o += -mregparm=3 -march=i386 -m32
 CFLAGS_reloc_x86_64_efi.o += -fpic -fshort-wchar
 AFLAGS_REMOVE_crt0_x86_64_efi.o += -mregparm=3 -march=i386 -m32
 AFLAGS_crt0_x86_64_efi.o += -fpic -fshort-wchar
 extra-$(CONFIG_EFI_STUB_32BIT) += crt0_ia32_efi.o reloc_ia32_efi.o
 extra-$(CONFIG_EFI_STUB_64BIT) += crt0_x86_64_efi.o reloc_x86_64_efi.o
 endif
 ifneq ($(CONFIG_EFI_STUB)$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),)
 ifeq ($(CONFIG_$(SPL_)X86_64),)
 extra-y += $(EFI_CRT0) $(EFI_RELOC)
 endif
 endif

arch/x86/lib/acpi_s3.c

Diff comments View file @ 3a34cae

File was created	1	/*
	2	* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <asm/acpi_s3.h>
	9	#include <asm/post.h>
	10
	11	static void asmlinkage (acpi_do_wakeup)(void vector) = (void *)WAKEUP_BASE;
	12
	13	static void acpi_jump_to_wakeup(void *vector)
	14	{
	15	/* Copy wakeup trampoline in place */
	16	memcpy((void *)WAKEUP_BASE, __wakeup, __wakeup_size);
	17
	18	printf("Jumping to OS waking vector %p\n", vector);
	19	acpi_do_wakeup(vector);
	20	}
	21
	22	void acpi_resume(void *wake_vec)
	23	{
	24	post_code(POST_OS_RESUME);
	25	acpi_jump_to_wakeup(wake_vec);
	26	}
	27