Eric Lee / smarc-uboot

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Commit 3bf801a2176e3330a3ef696d974d0d198d99b7e9

Authored by Andrej Rosano
Committed by Stefano Babic
1 parent 424ee3d157
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: mx5: add support for USB armory board 

Add support for Inverse Path USB armory board, an open source
flash-drive sized computer based on Freescale i.MX53 SoC.

http://inversepath.com/usbarmory

Signed-off-by: Andrej Rosano <andrej@inversepath.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Chris Kuethe <chris.kuethe@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Tested-By: Vagrant Cascadian <vagrant@debian.org>
Tested-by: Chris Kuethe <chris.kuethe@gmail.com>

Showing 8 changed files with 670 additions and 0 deletions Inline Diff

arch/arm/cpu/armv7/mx5/Kconfig
Diff comments   View file @ 3bf801a
1 if ARCH_MX5 1 if ARCH_MX5
2 2
3 config MX5 3 config MX5
4 bool 4 bool
5 default y 5 default y
6 6
7 config MX51 7 config MX51
8 bool 8 bool
9 9
10 config MX53 10 config MX53
11 bool 11 bool
12 12
13 choice
14 prompt "MX5 board select"
15
16 config TARGET_USBARMORY
17 bool "Support USB armory"
18 select CPU_V7
19
20 endchoice
21
13 config SYS_SOC 22 config SYS_SOC
14 default "mx5" 23 default "mx5"
24
25 source "board/inversepath/usbarmory/Kconfig"
15 26
16 endif 27 endif
17 28
board/inversepath/usbarmory/Kconfig
Diff comments   View file @ 3bf801a
File was created 1 if TARGET_USBARMORY
2
3 config IMX_CONFIG
4 default "board/inversepath/usbarmory/imximage.cfg"
5
6 config SYS_BOARD
7 default "usbarmory"
8
9 config SYS_VENDOR
10 default "inversepath"
11
12 config SYS_CONFIG_NAME
13 default "usbarmory"
14
15 endif
16
board/inversepath/usbarmory/MAINTAINERS
Diff comments   View file @ 3bf801a
File was created 1 USBARMORY BOARD
2 M: Andrej Rosano <andrej@inversepath.com>
3 S: Maintained
4 F: board/inversepath/usbarmory/
5 F: include/configs/usbarmory.h
6 F: configs/usbarmory_defconfig
7
board/inversepath/usbarmory/Makefile
Diff comments   View file @ 3bf801a
File was created 1 #
2 # USB armory MkI board Makefile
3 # http://inversepath.com/usbarmory
4 #
5 # Copyright (C) 2015, Inverse Path
6 # Andrej Rosano <andrej@inversepath.com>
7 #
8 # SPDX-License-Identifier:|____GPL-2.0+
9
10 obj-y := usbarmory.o
11
board/inversepath/usbarmory/imximage.cfg
Diff comments   View file @ 3bf801a
File was created 1 /*
2 * USB armory MkI board imximage configuration
3 * http://inversepath.com/usbarmory
4 *
5 * Copyright (C) 2015, Inverse Path
6 * Andrej Rosano <andrej@inversepath.com>
7 *
8 * SPDX-License-Identifier:|____GPL-2.0+
9 */
10
11 IMAGE_VERSION 2
12 BOOT_FROM sd
13
14
15 /* IOMUX */
16
17 DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */
18 DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */
19 DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */
20 DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */
21
22 DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */
23 DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */
24 DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */
25
26 DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */
27 DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */
28 DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */
29
30 DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */
31 DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */
32 DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */
33
34 DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */
35 DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */
36 DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */
37
38 DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK0 */
39 DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK1 */
40
41 DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */
42 DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */
43 DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDS */
44 DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */
45
46 DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */
47 DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */
48
49
50 /* ESDCTL */
51
52 DATA 4 0x63fd9000 0x84180000 /* ESDCTL_ESDCTL */
53
54 DATA 4 0x63fd9004 0x0002002d /* ESDCTL_ESDPTC */
55 DATA 4 0x63fd9008 0x12273030 /* ESDCTL_ESDOTC */
56 DATA 4 0x63fd900c 0x9f5152e3 /* ESDCTL_ESDCFG0 */
57 DATA 4 0x63fd9010 0xb68e8a63 /* ESDCTL_ESDCFG1 */
58 DATA 4 0x63fd9014 0x01ff00db /* ESDCTL_ESDCFG2 */
59 DATA 4 0x63fd9018 0x00011740 /* ESDCTL_ESDMISC */
60
61 DATA 4 0x63fd901c 0x00008032 /* ESDCTL_ESDSCR */
62 DATA 4 0x63fd901c 0x00008033
63 DATA 4 0x63fd901c 0x00028031
64 DATA 4 0x63fd901c 0x052080b0
65 DATA 4 0x63fd901c 0x04008040
66 DATA 4 0x63fd901c 0x0000803a
67 DATA 4 0x63fd901c 0x0000803b
68 DATA 4 0x63fd901c 0x00028039
69 DATA 4 0x63fd901c 0x05208138
70 DATA 4 0x63fd901c 0x04008048
71 DATA 4 0x63fd901c 0x00000000
72
73 DATA 4 0x63fd9020 0x00005800 /* ESDCTL_ESDREF */
74 DATA 4 0x63fd902c 0x000026d2 /* ESDCTL_ESDEWD */
75 DATA 4 0x63fd9030 0x009f0e21 /* ESDCTL_ESDOR */
76 DATA 4 0x63fd9040 0x05380003 /* ESDCTL_ZQHWCTRL */
77 DATA 4 0x63fd9058 0x00022227 /* ESDCTL_ODTCTRL */
78
79 DATA 4 0x63fd907c 0x01370138 /* ESDCTL_DGCTRL0 */
80 DATA 4 0x63fd9080 0x013b013c /* ESDCTL_DGCTRL1 */
81 DATA 4 0x63fd9088 0x35343535 /* ESDCTL_RDDLCTL */
82 DATA 4 0x63fd9090 0x4d444c44 /* ESDCTL_WRDLCTL */
83
board/inversepath/usbarmory/usbarmory.c
Diff comments   View file @ 3bf801a
File was created 1 /*
2 * USB armory MkI board initialization
3 * http://inversepath.com/usbarmory
4 *
5 * Copyright (C) 2015, Inverse Path
6 * Andrej Rosano <andrej@inversepath.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #include <common.h>
12 #include <asm/io.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/arch/crm_regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/iomux-mx53.h>
18 #include <asm/errno.h>
19 #include <i2c.h>
20 #include <mmc.h>
21 #include <fsl_esdhc.h>
22 #include <asm/gpio.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 u32 get_board_rev(void)
27 {
28 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
29 struct fuse_bank *bank = &iim->bank[0];
30 struct fuse_bank0_regs *fuse =
31 (struct fuse_bank0_regs *)bank->fuse_regs;
32
33 int rev = readl(&fuse->gp[6]);
34
35 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
36 }
37
38 struct fsl_esdhc_cfg esdhc_cfg[1] = {
39 {MMC_SDHC1_BASE_ADDR}
40 };
41
42 int board_mmc_getcd(struct mmc *mmc)
43 {
44 /* CD not present */
45 return 1;
46 }
47
48 int board_mmc_init(bd_t *bis)
49 {
50 int ret = 0;
51
52 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
53 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
54
55 return ret;
56 }
57
58 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
59 PAD_CTL_PUS_100K_UP)
60 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
61 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
62 #define PAD_CTRL_UP PAD_CTL_PUS_100K_UP
63 #define PAD_CTRL_GND PAD_CTL_PUS_100K_DOWN
64
65 static void setup_iomux_sd(void)
66 {
67 static const iomux_v3_cfg_t pads[] = {
68 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
69 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, MX53_SDHC_PAD_CTRL),
70 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
71 MX53_SDHC_PAD_CTRL),
72 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
73 MX53_SDHC_PAD_CTRL),
74 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
75 MX53_SDHC_PAD_CTRL),
76 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
77 MX53_SDHC_PAD_CTRL),
78 MX53_PAD_EIM_DA13__GPIO3_13,
79 };
80
81 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
82 }
83
84 static void setup_iomux_led(void)
85 {
86 static const iomux_v3_cfg_t pads[] = {
87 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT6__GPIO4_27,
88 PAD_CTL_PUS_100K_DOWN),
89 };
90
91 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
92 }
93
94 static void setup_iomux_i2c(void)
95 {
96 static const iomux_v3_cfg_t pads[] = {
97 NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
98 NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
99 };
100
101 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
102 }
103
104 static void setup_iomux_pinheader(void)
105 {
106 static const iomux_v3_cfg_t pads[] = {
107 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__GPIO5_26, PAD_CTRL_UP),
108 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__GPIO5_27, PAD_CTRL_UP),
109 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
110 MX53_UART_PAD_CTRL),
111 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
112 MX53_UART_PAD_CTRL),
113 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__GPIO5_30, PAD_CTRL_UP),
114 };
115
116 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
117 }
118
119 static void setup_iomux_unused_boot(void)
120 {
121 static const iomux_v3_cfg_t pads[] = {
122 /* Pulled-up pads */
123 NEW_PAD_CTRL(MX53_PAD_EIM_A21__GPIO2_17, PAD_CTRL_UP),
124 NEW_PAD_CTRL(MX53_PAD_EIM_DA0__GPIO3_0, PAD_CTRL_UP),
125
126 /* Grounded pads */
127 NEW_PAD_CTRL(MX53_PAD_EIM_LBA__GPIO2_27, PAD_CTRL_GND),
128 NEW_PAD_CTRL(MX53_PAD_EIM_EB0__GPIO2_28, PAD_CTRL_GND),
129 NEW_PAD_CTRL(MX53_PAD_EIM_EB1__GPIO2_29, PAD_CTRL_GND),
130 NEW_PAD_CTRL(MX53_PAD_EIM_A16__GPIO2_22, PAD_CTRL_GND),
131 NEW_PAD_CTRL(MX53_PAD_EIM_A17__GPIO2_21, PAD_CTRL_GND),
132 NEW_PAD_CTRL(MX53_PAD_EIM_A18__GPIO2_20, PAD_CTRL_GND),
133 NEW_PAD_CTRL(MX53_PAD_EIM_A19__GPIO2_19, PAD_CTRL_GND),
134 NEW_PAD_CTRL(MX53_PAD_EIM_A20__GPIO2_18, PAD_CTRL_GND),
135 NEW_PAD_CTRL(MX53_PAD_EIM_A22__GPIO2_16, PAD_CTRL_GND),
136 NEW_PAD_CTRL(MX53_PAD_EIM_DA1__GPIO3_1, PAD_CTRL_GND),
137 NEW_PAD_CTRL(MX53_PAD_EIM_DA2__GPIO3_2, PAD_CTRL_GND),
138 NEW_PAD_CTRL(MX53_PAD_EIM_DA3__GPIO3_3, PAD_CTRL_GND),
139 NEW_PAD_CTRL(MX53_PAD_EIM_DA4__GPIO3_4, PAD_CTRL_GND),
140 NEW_PAD_CTRL(MX53_PAD_EIM_DA5__GPIO3_5, PAD_CTRL_GND),
141 NEW_PAD_CTRL(MX53_PAD_EIM_DA6__GPIO3_6, PAD_CTRL_GND),
142 NEW_PAD_CTRL(MX53_PAD_EIM_DA7__GPIO3_7, PAD_CTRL_GND),
143 NEW_PAD_CTRL(MX53_PAD_EIM_DA8__GPIO3_8, PAD_CTRL_GND),
144 NEW_PAD_CTRL(MX53_PAD_EIM_DA9__GPIO3_9, PAD_CTRL_GND),
145 NEW_PAD_CTRL(MX53_PAD_EIM_DA10__GPIO3_10, PAD_CTRL_GND),
146 };
147
148 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
149 }
150
151 static void setup_iomux_unused_nc(void)
152 {
153 /* Out of reset values define the pin values before the
154 ROM is executed so we force all the not connected pins
155 to a known state */
156 static const iomux_v3_cfg_t pads[] = {
157 /* CONTROL PINS block */
158 NEW_PAD_CTRL(MX53_PAD_GPIO_0__GPIO1_0, PAD_CTRL_UP),
159 NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, PAD_CTRL_UP),
160 NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2, PAD_CTRL_UP),
161 NEW_PAD_CTRL(MX53_PAD_GPIO_3__GPIO1_3, PAD_CTRL_UP),
162 NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4, PAD_CTRL_UP),
163 NEW_PAD_CTRL(MX53_PAD_GPIO_5__GPIO1_5, PAD_CTRL_UP),
164 NEW_PAD_CTRL(MX53_PAD_GPIO_6__GPIO1_6, PAD_CTRL_UP),
165 NEW_PAD_CTRL(MX53_PAD_GPIO_7__GPIO1_7, PAD_CTRL_UP),
166 NEW_PAD_CTRL(MX53_PAD_GPIO_8__GPIO1_8, PAD_CTRL_UP),
167 NEW_PAD_CTRL(MX53_PAD_GPIO_9__GPIO1_9, PAD_CTRL_UP),
168 NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0, PAD_CTRL_UP),
169 NEW_PAD_CTRL(MX53_PAD_GPIO_11__GPIO4_1, PAD_CTRL_UP),
170 NEW_PAD_CTRL(MX53_PAD_GPIO_12__GPIO4_2, PAD_CTRL_UP),
171 NEW_PAD_CTRL(MX53_PAD_GPIO_13__GPIO4_3, PAD_CTRL_UP),
172 NEW_PAD_CTRL(MX53_PAD_GPIO_14__GPIO4_4, PAD_CTRL_UP),
173 NEW_PAD_CTRL(MX53_PAD_GPIO_16__GPIO7_11, PAD_CTRL_UP),
174 NEW_PAD_CTRL(MX53_PAD_GPIO_17__GPIO7_12, PAD_CTRL_UP),
175 NEW_PAD_CTRL(MX53_PAD_GPIO_18__GPIO7_13, PAD_CTRL_UP),
176 NEW_PAD_CTRL(MX53_PAD_GPIO_19__GPIO4_5, PAD_CTRL_UP),
177
178 /* EIM block */
179 NEW_PAD_CTRL(MX53_PAD_EIM_OE__GPIO2_25, PAD_CTRL_UP),
180 NEW_PAD_CTRL(MX53_PAD_EIM_WAIT__GPIO5_0, PAD_CTRL_UP),
181 /* EIM_LBA: setup_iomux_unused_boot() */
182 NEW_PAD_CTRL(MX53_PAD_EIM_RW__GPIO2_26, PAD_CTRL_UP),
183 /* EIM_EB0: setup_iomux_unused_boot() */
184 /* EIM_EB1: setup_iomux_unused_boot() */
185 NEW_PAD_CTRL(MX53_PAD_EIM_EB2__GPIO2_30, PAD_CTRL_UP),
186 NEW_PAD_CTRL(MX53_PAD_EIM_EB3__GPIO2_31, PAD_CTRL_UP),
187 NEW_PAD_CTRL(MX53_PAD_EIM_CS0__GPIO2_23, PAD_CTRL_UP),
188 NEW_PAD_CTRL(MX53_PAD_EIM_CS1__GPIO2_24, PAD_CTRL_UP),
189 /* EIM_A16: setup_iomux_unused_boot() */
190 /* EIM_A17: setup_iomux_unused_boot() */
191 /* EIM_A18: setup_iomux_unused_boot() */
192 /* EIM_A19: setup_iomux_unused_boot() */
193 /* EIM_A20: setup_iomux_unused_boot() */
194 /* EIM_A21: setup_iomux_unused_boot() */
195 /* EIM_A22: setup_iomux_unused_boot() */
196 NEW_PAD_CTRL(MX53_PAD_EIM_A23__GPIO6_6, PAD_CTRL_UP),
197 NEW_PAD_CTRL(MX53_PAD_EIM_A24__GPIO5_4, PAD_CTRL_UP),
198 NEW_PAD_CTRL(MX53_PAD_EIM_A25__GPIO5_2, PAD_CTRL_UP),
199 NEW_PAD_CTRL(MX53_PAD_EIM_D16__GPIO3_16, PAD_CTRL_UP),
200 NEW_PAD_CTRL(MX53_PAD_EIM_D17__GPIO3_17, PAD_CTRL_UP),
201 NEW_PAD_CTRL(MX53_PAD_EIM_D18__GPIO3_18, PAD_CTRL_UP),
202 NEW_PAD_CTRL(MX53_PAD_EIM_D19__GPIO3_19, PAD_CTRL_UP),
203 NEW_PAD_CTRL(MX53_PAD_EIM_D20__GPIO3_20, PAD_CTRL_UP),
204 NEW_PAD_CTRL(MX53_PAD_EIM_D21__GPIO3_21, PAD_CTRL_UP),
205 NEW_PAD_CTRL(MX53_PAD_EIM_D22__GPIO3_22, PAD_CTRL_UP),
206 NEW_PAD_CTRL(MX53_PAD_EIM_D23__GPIO3_23, PAD_CTRL_UP),
207 NEW_PAD_CTRL(MX53_PAD_EIM_D24__GPIO3_24, PAD_CTRL_UP),
208 NEW_PAD_CTRL(MX53_PAD_EIM_D25__GPIO3_25, PAD_CTRL_UP),
209 NEW_PAD_CTRL(MX53_PAD_EIM_D26__GPIO3_26, PAD_CTRL_UP),
210 NEW_PAD_CTRL(MX53_PAD_EIM_D27__GPIO3_27, PAD_CTRL_UP),
211 /* EIM_D28: setup_iomux_unused_boot() */
212 /* EIM_D29: setup_iomux_unused_boot() */
213 NEW_PAD_CTRL(MX53_PAD_EIM_D30__GPIO3_30, PAD_CTRL_UP),
214 NEW_PAD_CTRL(MX53_PAD_EIM_D31__GPIO3_31, PAD_CTRL_UP),
215 /* EIM_DA0: setup_iomux_unused_boot() */
216 /* EIM_DA1: setup_iomux_unused_boot() */
217 /* EIM_DA2: setup_iomux_unused_boot() */
218 /* EIM_DA3: setup_iomux_unused_boot() */
219 /* EIM_DA4: setup_iomux_unused_boot() */
220 /* EIM_DA5: setup_iomux_unused_boot() */
221 /* EIM_DA6: setup_iomux_unused_boot() */
222 /* EIM_DA7: setup_iomux_unused_boot() */
223 /* EIM_DA8: setup_iomux_unused_boot() */
224 /* EIM_DA9: setup_iomux_unused_boot() */
225 /* EIM_DA10: setup_iomux_unused_boot() */
226 NEW_PAD_CTRL(MX53_PAD_EIM_DA11__GPIO3_11, PAD_CTRL_UP),
227 NEW_PAD_CTRL(MX53_PAD_EIM_DA12__GPIO3_12, PAD_CTRL_UP),
228 NEW_PAD_CTRL(MX53_PAD_EIM_DA13__GPIO3_13, PAD_CTRL_UP),
229 NEW_PAD_CTRL(MX53_PAD_EIM_DA14__GPIO3_14, PAD_CTRL_UP),
230 NEW_PAD_CTRL(MX53_PAD_EIM_DA15__GPIO3_15, PAD_CTRL_UP),
231 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__GPIO6_12, PAD_CTRL_UP),
232 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__GPIO6_13, PAD_CTRL_UP),
233 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__GPIO6_8, PAD_CTRL_UP),
234 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__GPIO6_7, PAD_CTRL_UP),
235 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__GPIO6_9, PAD_CTRL_UP),
236 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__GPIO6_10, PAD_CTRL_UP),
237 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__GPIO6_11, PAD_CTRL_UP),
238 NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__GPIO6_14, PAD_CTRL_UP),
239 NEW_PAD_CTRL(MX53_PAD_NANDF_CS2__GPIO6_15, PAD_CTRL_UP),
240 NEW_PAD_CTRL(MX53_PAD_NANDF_CS3__GPIO6_16, PAD_CTRL_UP),
241
242 /* MISC block */
243 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__GPIO1_31, PAD_CTRL_UP),
244 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__GPIO1_22, PAD_CTRL_UP),
245 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__GPIO1_25, PAD_CTRL_UP),
246 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__GPIO1_23, PAD_CTRL_UP),
247 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__GPIO1_24, PAD_CTRL_UP),
248 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__GPIO1_28, PAD_CTRL_UP),
249 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__GPIO1_27, PAD_CTRL_UP),
250 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__GPIO1_26, PAD_CTRL_UP),
251 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__GPIO1_30, PAD_CTRL_UP),
252 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__GPIO1_29, PAD_CTRL_UP),
253 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__GPIO4_6, PAD_CTRL_UP),
254 NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__GPIO4_7, PAD_CTRL_UP),
255 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__GPIO4_8, PAD_CTRL_UP),
256 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__GPIO4_9, PAD_CTRL_UP),
257 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__GPIO4_10, PAD_CTRL_UP),
258 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__GPIO4_11, PAD_CTRL_UP),
259 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__GPIO4_12, PAD_CTRL_UP),
260 NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__GPIO4_13, PAD_CTRL_UP),
261 NEW_PAD_CTRL(MX53_PAD_KEY_COL4__GPIO4_14, PAD_CTRL_UP),
262 NEW_PAD_CTRL(MX53_PAD_KEY_ROW4__GPIO4_15, PAD_CTRL_UP),
263 NEW_PAD_CTRL(MX53_PAD_SD2_CMD__GPIO1_11, PAD_CTRL_UP),
264 NEW_PAD_CTRL(MX53_PAD_SD2_CLK__GPIO1_10, PAD_CTRL_UP),
265 NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__GPIO1_15, PAD_CTRL_UP),
266 NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__GPIO1_14, PAD_CTRL_UP),
267 NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__GPIO1_13, PAD_CTRL_UP),
268 NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__GPIO1_12, PAD_CTRL_UP),
269 NEW_PAD_CTRL(MX53_PAD_PATA_BUFFER_EN__GPIO7_1, PAD_CTRL_UP),
270 NEW_PAD_CTRL(MX53_PAD_PATA_CS_0__GPIO7_9, PAD_CTRL_UP),
271 NEW_PAD_CTRL(MX53_PAD_PATA_CS_1__GPIO7_10, PAD_CTRL_UP),
272 NEW_PAD_CTRL(MX53_PAD_PATA_DA_0__GPIO7_6, PAD_CTRL_UP),
273 NEW_PAD_CTRL(MX53_PAD_PATA_DA_1__GPIO7_7, PAD_CTRL_UP),
274 NEW_PAD_CTRL(MX53_PAD_PATA_DA_2__GPIO7_8, PAD_CTRL_UP),
275 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__GPIO2_0, PAD_CTRL_UP),
276 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__GPIO2_1, PAD_CTRL_UP),
277 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__GPIO2_2, PAD_CTRL_UP),
278 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__GPIO2_3, PAD_CTRL_UP),
279 NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__GPIO2_4, PAD_CTRL_UP),
280 NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__GPIO2_5, PAD_CTRL_UP),
281 NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__GPIO2_6, PAD_CTRL_UP),
282 NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__GPIO2_7, PAD_CTRL_UP),
283 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__GPIO2_8, PAD_CTRL_UP),
284 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__GPIO2_9, PAD_CTRL_UP),
285 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__GPIO2_10, PAD_CTRL_UP),
286 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__GPIO2_11, PAD_CTRL_UP),
287 NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__GPIO2_12, PAD_CTRL_UP),
288 NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__GPIO2_13, PAD_CTRL_UP),
289 NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__GPIO2_14, PAD_CTRL_UP),
290 NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__GPIO2_15, PAD_CTRL_UP),
291 NEW_PAD_CTRL(MX53_PAD_PATA_DIOR__GPIO7_3, PAD_CTRL_UP),
292 NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__GPIO6_17, PAD_CTRL_UP),
293 NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__GPIO6_18, PAD_CTRL_UP),
294 NEW_PAD_CTRL(MX53_PAD_PATA_DMARQ__GPIO7_0, PAD_CTRL_UP),
295 NEW_PAD_CTRL(MX53_PAD_PATA_INTRQ__GPIO7_2, PAD_CTRL_UP),
296 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__GPIO7_5, PAD_CTRL_UP),
297 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__GPIO7_4, PAD_CTRL_UP),
298
299 /* IPU block */
300 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT4__GPIO5_22, PAD_CTRL_UP),
301 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT5__GPIO5_23, PAD_CTRL_UP),
302 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT6__GPIO5_24, PAD_CTRL_UP),
303 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT7__GPIO5_25, PAD_CTRL_UP),
304 /* CSI0_DAT8: setup_iomux_pinheader() */
305 /* CSI0_DAT9: setup_iomux_pinheader() */
306 /* CSI0_DAT10: setup_iomux_pinheader() */
307 /* CSI0_DAT11: setup_iomux_pinheader() */
308 /* CSI0_DAT12: setup_iomux_pinheader() */
309 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__GPIO5_31, PAD_CTRL_UP),
310 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT14__GPIO6_0, PAD_CTRL_UP),
311 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT15__GPIO6_1, PAD_CTRL_UP),
312 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT16__GPIO6_2, PAD_CTRL_UP),
313 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT17__GPIO6_3, PAD_CTRL_UP),
314 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT18__GPIO6_4, PAD_CTRL_UP),
315 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT19__GPIO6_5, PAD_CTRL_UP),
316 NEW_PAD_CTRL(MX53_PAD_CSI0_VSYNC__GPIO5_21, PAD_CTRL_UP),
317 NEW_PAD_CTRL(MX53_PAD_CSI0_PIXCLK__GPIO5_18, PAD_CTRL_UP),
318 NEW_PAD_CTRL(MX53_PAD_CSI0_MCLK__GPIO5_19, PAD_CTRL_UP),
319 NEW_PAD_CTRL(MX53_PAD_CSI0_DATA_EN__GPIO5_20, PAD_CTRL_UP),
320 NEW_PAD_CTRL(MX53_PAD_DI0_PIN2__GPIO4_18, PAD_CTRL_UP),
321 NEW_PAD_CTRL(MX53_PAD_DI0_PIN3__GPIO4_19, PAD_CTRL_UP),
322 NEW_PAD_CTRL(MX53_PAD_DI0_PIN4__GPIO4_20, PAD_CTRL_UP),
323 NEW_PAD_CTRL(MX53_PAD_DI0_PIN15__GPIO4_17, PAD_CTRL_UP),
324 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT0__GPIO4_21, PAD_CTRL_UP),
325 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT1__GPIO4_22, PAD_CTRL_UP),
326 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT2__GPIO4_23, PAD_CTRL_UP),
327 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT3__GPIO4_24, PAD_CTRL_UP),
328 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT4__GPIO4_25, PAD_CTRL_UP),
329 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT5__GPIO4_26, PAD_CTRL_UP),
330 /* DISP0_DAT6: setup_iomux_led() */
331 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT7__GPIO4_28, PAD_CTRL_UP),
332 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT8__GPIO4_29, PAD_CTRL_UP),
333 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT9__GPIO4_30, PAD_CTRL_UP),
334 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT10__GPIO4_31, PAD_CTRL_UP),
335 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT11__GPIO5_5, PAD_CTRL_UP),
336 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT12__GPIO5_6, PAD_CTRL_UP),
337 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT13__GPIO5_7, PAD_CTRL_UP),
338 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT14__GPIO5_8, PAD_CTRL_UP),
339 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT15__GPIO5_9, PAD_CTRL_UP),
340 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT16__GPIO5_10, PAD_CTRL_UP),
341 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT17__GPIO5_11, PAD_CTRL_UP),
342 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT18__GPIO5_12, PAD_CTRL_UP),
343 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT19__GPIO5_13, PAD_CTRL_UP),
344 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT20__GPIO5_14, PAD_CTRL_UP),
345 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT21__GPIO5_15, PAD_CTRL_UP),
346 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT22__GPIO5_16, PAD_CTRL_UP),
347 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT23__GPIO5_17, PAD_CTRL_UP),
348 NEW_PAD_CTRL(MX53_PAD_DI0_DISP_CLK__GPIO4_16, PAD_CTRL_UP),
349
350 /* LVDS block */
351 NEW_PAD_CTRL(MX53_PAD_LVDS0_TX0_P__GPIO7_30, PAD_CTRL_UP),
352 NEW_PAD_CTRL(MX53_PAD_LVDS0_TX1_P__GPIO7_28, PAD_CTRL_UP),
353 NEW_PAD_CTRL(MX53_PAD_LVDS0_TX2_P__GPIO7_26, PAD_CTRL_UP),
354 NEW_PAD_CTRL(MX53_PAD_LVDS0_TX3_P__GPIO7_22, PAD_CTRL_UP),
355 NEW_PAD_CTRL(MX53_PAD_LVDS1_TX0_P__GPIO6_30, PAD_CTRL_UP),
356 NEW_PAD_CTRL(MX53_PAD_LVDS1_TX1_P__GPIO6_28, PAD_CTRL_UP),
357 NEW_PAD_CTRL(MX53_PAD_LVDS1_TX2_P__GPIO6_24, PAD_CTRL_UP),
358 NEW_PAD_CTRL(MX53_PAD_LVDS1_TX3_P__GPIO6_22, PAD_CTRL_UP),
359 NEW_PAD_CTRL(MX53_PAD_LVDS0_CLK_P__GPIO7_24, PAD_CTRL_UP),
360 NEW_PAD_CTRL(MX53_PAD_LVDS1_CLK_P__GPIO6_26, PAD_CTRL_UP),
361 };
362
363 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
364 }
365
366 #define CPU_CLOCK 800
367
368 static void set_clock(void)
369 {
370 u32 ref_clk = MXC_HCLK;
371 const uint32_t cpuclk = CPU_CLOCK;
372 const uint32_t dramclk = 400;
373 int ret;
374
375 ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
376 if (ret)
377 printf("CPU: Switch CPU clock to %dMHZ failed\n", cpuclk);
378
379 ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
380 if (ret)
381 printf("CPU: Switch peripheral clock to %dMHz failed\n",
382 dramclk);
383
384 ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
385 if (ret)
386 printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
387 }
388
389 int board_early_init_f(void)
390 {
391 setup_iomux_unused_nc();
392 setup_iomux_unused_boot();
393 setup_iomux_sd();
394 setup_iomux_led();
395 setup_iomux_pinheader();
396 set_clock();
397 return 0;
398 }
399
400 int board_init(void)
401 {
402 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
403 setup_iomux_i2c();
404 return 0;
405 }
406
407 int dram_init(void)
408 {
409 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 1 << 30);
410 return 0;
411 }
412
413 int checkboard(void)
414 {
415 puts("Board: Inverse Path USB armory MkI\n");
416 return 0;
417 }
418
configs/usbarmory_defconfig
Diff comments   View file @ 3bf801a
File was created 1 CONFIG_ARM=y
2 CONFIG_ARCH_MX5=y
3 CONFIG_TARGET_USBARMORY=y
4
include/configs/usbarmory.h
Diff comments   View file @ 3bf801a
File was created 1 /*
2 * USB armory MkI board configuration settings
3 * http://inversepath.com/usbarmory
4 *
5 * Copyright (C) 2015, Inverse Path
6 * Andrej Rosano <andrej@inversepath.com>
7 *
8 * SPDX-License-Identifier:|____GPL-2.0+
9 */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #define CONFIG_MX53
15 #define CONFIG_DISPLAY_CPUINFO
16 #define CONFIG_DISPLAY_BOARDINFO
17 #define CONFIG_BOARD_EARLY_INIT_F
18 #define CONFIG_OF_LIBFDT
19 #define CONFIG_SYS_GENERIC_BOARD
20 #define CONFIG_MXC_GPIO
21
22 #include <asm/arch/imx-regs.h>
23 #include <config_cmd_default.h>
24
25 #include <config_distro_defaults.h>
26
27 /* U-Boot commands */
28 #define CONFIG_CMD_MEMTEST
29 #undef CONFIG_CMD_IMLS
30
31 /* U-Boot environment */
32 #define CONFIG_ENV_OVERWRITE
33 #define CONFIG_SYS_NO_FLASH
34 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
35 #define CONFIG_ENV_SIZE (8 * 1024)
36 #define CONFIG_ENV_IS_IN_MMC
37 #define CONFIG_SYS_MMC_ENV_DEV 0
38
39 /* U-Boot general configurations */
40 #define CONFIG_SYS_CBSIZE 512
41 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
42 #define CONFIG_SYS_MAXARGS 16
43 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
44
45 /* UART */
46 #define CONFIG_MXC_UART
47 #define CONFIG_MXC_UART_BASE UART1_BASE
48 #define CONFIG_CONS_INDEX 1
49 #define CONFIG_BAUDRATE 115200
50
51 /* SD/MMC */
52 #define CONFIG_CMD_MMC
53 #define CONFIG_FSL_ESDHC
54 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
55 #define CONFIG_SYS_FSL_ESDHC_NUM 1
56 #define CONFIG_MMC
57 #define CONFIG_GENERIC_MMC
58
59 /* USB */
60 #define CONFIG_CMD_USB
61 #define CONFIG_USB_EHCI
62 #define CONFIG_USB_EHCI_MX5
63 #define CONFIG_USB_STORAGE
64 #define CONFIG_MXC_USB_PORT 1
65 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
66 #define CONFIG_MXC_USB_FLAGS 0
67
68 /* I2C */
69 #define CONFIG_CMD_I2C
70 #define CONFIG_SYS_I2C
71 #define CONFIG_SYS_I2C_MXC
72
73 /* Fuse */
74 #define CONFIG_CMD_FUSE
75 #define CONFIG_FSL_IIM
76
77 /* Linux boot */
78 #define CONFIG_LOADADDR 0x72000000
79 #define CONFIG_SYS_TEXT_BASE 0x77800000
80 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
81 #define CONFIG_HOSTNAME usbarmory
82 #define CONFIG_BOOTCOMMAND \
83 "run distro_bootcmd; " \
84 "setenv bootargs console=${console} ${bootargs_default}; " \
85 "ext2load mmc 0:1 ${kernel_addr_r} /boot/uImage; " \
86 "ext2load mmc 0:1 ${fdt_addr_r} /boot/${fdtfile}; " \
87 "bootm ${kernel_addr_r} - ${fdt_addr_r}"
88
89 #define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 0)
90
91 #include <config_distro_bootcmd.h>
92
93 #define MEM_LAYOUT_ENV_SETTINGS \
94 "kernel_addr_r=0x70800000\0" \
95 "fdt_addr_r=0x71000000\0" \
96 "scriptaddr=0x70800000\0" \
97 "pxefile_addr_r=0x70800000\0" \
98 "ramdisk_addr_r=0x73000000\0"
99
100 #define CONFIG_EXTRA_ENV_SETTINGS \
101 MEM_LAYOUT_ENV_SETTINGS \
102 "bootargs_default=root=/dev/mmcblk0p1 rootwait rw\0" \
103 "fdtfile=imx53-usbarmory.dtb\0" \
104 "console=ttymxc0,115200\0" \
105 BOOTENV
106
107 /* Physical Memory Map */
108 #define CONFIG_NR_DRAM_BANKS 1
109 #define PHYS_SDRAM CSD0_BASE_ADDR
110 #define PHYS_SDRAM_SIZE (gd->ram_size)
111
112 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
113 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
114 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
115
116 #define CONFIG_SYS_INIT_SP_OFFSET \
117 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
118 #define CONFIG_SYS_INIT_SP_ADDR \
119 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
120
121 #define CONFIG_SYS_MEMTEST_START 0x70000000
122 #define CONFIG_SYS_MEMTEST_END 0x90000000
123
124 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
125
126 #endif /* __CONFIG_H */
127