Eric Lee / smarc-uboot | Embedian Git Server

Commit 3ddc0dd0011ea1448191ecb2461ed9a0ff7bf387

Authored by guoyin.chen 2014-12-02 17:56:50 +0800

MA-5830 Align Fastboot NAND config with bootloader partition 64M

Align the "MLK-9918: Reserve more space in uboot partition for NAND boot configurations"
to enlarge the bootloader partition to be 64M

Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>

Showing 4 changed files with 10 additions and 4 deletions Inline Diff

board/freescale/mx6qsabreauto/mx6qsabreauto.c
board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
include/configs/mx6sabreandroid_common.h
include/configs/mx6sxsabreautoandroid.h

board/freescale/mx6qsabreauto/mx6qsabreauto.c

Diff comments View file @ 3ddc0dd

 /*
  * Copyright (C) 2012-2014 Freescale Semiconductor, Inc.
  *
  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/mxc_i2c.h>
 #include <asm/imx-common/boot_mode.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mxc_hdmi.h>
 #include <linux/fb.h>
 #include <ipu_pixfmt.h>
 #include <i2c.h>
 #ifdef CONFIG_CMD_SATA
 #include <asm/imx-common/sata.h>
 #endif
 #ifdef CONFIG_FASTBOOT
 #include <fastboot.h>
 #ifdef CONFIG_ANDROID_RECOVERY
 #include <recovery.h>
 #endif
 #endif /*CONFIG_FASTBOOT*/
 #ifdef CONFIG_MAX7310_IOEXP
 #include <gpio_exp.h>
 #endif
 DECLARE_GLOBAL_DATA_PTR;
 #define I2C_EXP_RST IMX_GPIO_NR(1, 15)
 #define I2C3_STEER  IMX_GPIO_NR(5, 4)
 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 /*Need more drive strength for SD1 slot on base board*/
 #define USDHC1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
 	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 #define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 #define SPI_PAD_CTRL (PAD_CTL_HYS |				\
 	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
 	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
 			PAD_CTL_SRE_FAST)
 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
 int dram_init(void)
 {
 	gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
 	return 0;
 }
 iomux_v3_cfg_t const uart4_pads[] = {
 	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 iomux_v3_cfg_t const enet_pads[] = {
 	MX6_PAD_KEY_COL1__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_KEY_COL2__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 };
 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
 struct i2c_pads_info i2c_pad_info1 = {
 	.scl = {
 		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
 		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
 		.gp = IMX_GPIO_NR(2, 30)
 	},
 	.sda = {
 		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 		.gp = IMX_GPIO_NR(4, 13)
 	}
 };
 /*
  * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
  * Compass Sensor, Accelerometer, Res Touch
  */
 struct i2c_pads_info i2c_pad_info2 = {
 	.scl = {
 		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
 		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
 		.gp = IMX_GPIO_NR(1, 3)
 	},
 	.sda = {
 		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
 		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
 		.gp = IMX_GPIO_NR(3, 18)
 	}
 };
 iomux_v3_cfg_t const i2c3_pads[] = {
 	MX6_PAD_EIM_A24__GPIO5_IO04		| MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 iomux_v3_cfg_t const port_exp[] = {
 	MX6_PAD_SD2_DAT0__GPIO1_IO15		| MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 static void setup_iomux_enet(void)
 {
 	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 }
 iomux_v3_cfg_t const usdhc1_pads[] = {
 	/*To avoid pin conflict with NAND, set usdhc1 to 4 pins*/
 	MX6_PAD_SD1_CLK__SD1_CLK	| MUX_PAD_CTRL(USDHC1_PAD_CTRL),
 	MX6_PAD_SD1_CMD__SD1_CMD	| MUX_PAD_CTRL(USDHC1_PAD_CTRL),
 	MX6_PAD_SD1_DAT0__SD1_DATA0	| MUX_PAD_CTRL(USDHC1_PAD_CTRL),
 	MX6_PAD_SD1_DAT1__SD1_DATA1	| MUX_PAD_CTRL(USDHC1_PAD_CTRL),
 	MX6_PAD_SD1_DAT2__SD1_DATA2	| MUX_PAD_CTRL(USDHC1_PAD_CTRL),
 	MX6_PAD_SD1_DAT3__SD1_DATA3	| MUX_PAD_CTRL(USDHC1_PAD_CTRL),
 	/*CD pin*/
 	MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 iomux_v3_cfg_t const usdhc3_pads[] = {
 	MX6_PAD_SD3_CLK__SD3_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_CMD__SD3_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT0__SD3_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT1__SD3_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT2__SD3_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT3__SD3_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT4__SD3_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT5__SD3_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT6__SD3_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT7__SD3_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_NANDF_CS2__GPIO6_IO15   | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 #ifdef CONFIG_SYS_I2C_MXC
 /* set all switches APS in normal and PFM mode in standby */
 static int setup_pmic_mode(int chip)
 {
 	unsigned char offset, i, switch_num, value;
 	if (!chip) {
 		/* pfuze100 */
 		switch_num = 6;
 		offset = 0x31;
 	} else {
 		/* pfuze200 */
 		switch_num = 4;
 		offset = 0x38;
 	}
 	value = 0xc;
 	if (i2c_write(0x8, 0x23, 1, &value, 1)) {
 		printf("Set SW1AB mode error!\n");
 		return -1;
 	}
 	for (i = 0; i < switch_num - 1; i++) {
 		if (i2c_write(0x8, offset + i * 7, 1, &value, 1)) {
 			printf("Set switch%x mode error!\n", offset);
 			return -1;
 		}
 	}
 	return 0;
 }
 static int setup_pmic_voltages(void)
 {
 	unsigned char value, rev_id = 0 ;
 	i2c_set_bus_num(1);
 	if (!i2c_probe(0x8)) {
 		if (i2c_read(0x8, 0, 1, &value, 1)) {
 			printf("Read device ID error!\n");
 			return -1;
 		}
 		if (i2c_read(0x8, 3, 1, &rev_id, 1)) {
 			printf("Read Rev ID error!\n");
 			return -1;
 		}
 		printf("Found PFUZE100! deviceid=%x,revid=%x\n", value, rev_id);
 		if (setup_pmic_mode(value & 0xf)) {
 			printf("setup pmic mode error!\n");
 			return -1;
 		}
 		/* set SW1AB staby volatage 0.975V*/
 		if (i2c_read(0x8, 0x21, 1, &value, 1)) {
 			printf("Read SW1ABSTBY error!\n");
 			return -1;
 		}
 		value &= ~0x3f;
 		value |= 0x1b;
 		if (i2c_write(0x8, 0x21, 1, &value, 1)) {
 			printf("Set SW1ABSTBY error!\n");
 			return -1;
 		}
 		/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 		if (i2c_read(0x8, 0x24, 1, &value, 1)) {
 			printf("Read SW1ABSTBY error!\n");
 			return -1;
 		}
 		value &= ~0xc0;
 		value |= 0x40;
 		if (i2c_write(0x8, 0x24, 1, &value, 1)) {
 			printf("Set SW1ABSTBY error!\n");
 			return -1;
 		}
 		/* set SW1C staby volatage 0.975V*/
 		if (i2c_read(0x8, 0x2f, 1, &value, 1)) {
 			printf("Read SW1CSTBY error!\n");
 			return -1;
 		}
 		value &= ~0x3f;
 		value |= 0x1b;
 		if (i2c_write(0x8, 0x2f, 1, &value, 1)) {
 			printf("Set SW1CSTBY error!\n");
 			return -1;
 		}
 		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
 		if (i2c_read(0x8, 0x32, 1, &value, 1)) {
 			printf("Read SW1ABSTBY error!\n");
 			return -1;
 		}
 		value &= ~0xc0;
 		value |= 0x40;
 		if (i2c_write(0x8, 0x32, 1, &value, 1)) {
 			printf("Set SW1ABSTBY error!\n");
 			return -1;
 		}
 	}
 	return 0;
 }
 #ifdef CONFIG_LDO_BYPASS_CHECK
 void ldo_mode_set(int ldo_bypass)
 {
 	unsigned char value;
 	/* increase VDDARM/VDDSOC to support 1.2G chip */
 	if (check_1_2G()) {
 		ldo_bypass = 0;	/* ldo_enable on 1.2G chip */
 		printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
 		/* increase VDDARM to 1.425V */
 		if (i2c_read(0x8, 0x20, 1, &value, 1)) {
 			printf("Read SW1AB error!\n");
 			return;
 		}
 		value &= ~0x3f;
 		value |= 0x2d;
 		if (i2c_write(0x8, 0x20, 1, &value, 1)) {
 			printf("Set SW1AB error!\n");
 			return;
 		}
 		/* increase VDDSOC to 1.425V */
 		if (i2c_read(0x8, 0x2e, 1, &value, 1)) {
 			printf("Read SW1C error!\n");
 			return;
 		}
 		value &= ~0x3f;
 		value |= 0x2d;
 		if (i2c_write(0x8, 0x2e, 1, &value, 1)) {
 			printf("Set SW1C error!\n");
 			return;
 		}
 	}
 }
 #endif
 #endif
 static void setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 }
 #ifdef CONFIG_FSL_ESDHC
 #define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 1)
 #define USDHC3_CD_GPIO	IMX_GPIO_NR(6, 15)
 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 	{USDHC1_BASE_ADDR, 0, 4},
 	{USDHC3_BASE_ADDR},
 };
 int mmc_get_env_devno(void)
 {
 	u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
 	u32 dev_no;
 	u32 bootsel;
 	bootsel = (soc_sbmr & 0x000000FF) >> 6 ;
 	/* If not boot from sd/mmc, use default value */
 	if (bootsel != 1)
 		return CONFIG_SYS_MMC_ENV_DEV;
 	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
 	dev_no = (soc_sbmr & 0x00001800) >> 11;
 	/* need ubstract 1 to map to the mmc3 device id
 	 * see the comments in board_mmc_init function
 	 */
 	if (2 == dev_no)
 		dev_no--;
 	return dev_no;
 }
 int mmc_map_to_kernel_blk(int dev_no)
 {
 	if (1 == dev_no)
 		dev_no = 2;
 	return dev_no;
 }
 int board_mmc_getcd(struct mmc *mmc)
 {
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	int ret = 0;
 	switch (cfg->esdhc_base) {
 	case USDHC1_BASE_ADDR:
 		ret = !gpio_get_value(USDHC1_CD_GPIO);
 		break;
 	case USDHC3_BASE_ADDR:
 		ret = !gpio_get_value(USDHC3_CD_GPIO);
 		break;
 	}
 	return ret;
 }
 int board_mmc_init(bd_t *bis)
 {
 	int i;
 	/*
 	* According to the board_mmc_init() the following map is done:
 	* (U-boot device node)    (Physical Port)
 	* mmc0				USDHC1
 	* mmc1				USDHC3
 	*/
 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 		switch (i) {
 		case 0:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 			gpio_direction_input(USDHC1_CD_GPIO);
 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 			break;
 		case 1:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 			gpio_direction_input(USDHC3_CD_GPIO);
 			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 			break;
 		default:
 			printf("Warning: you configured more USDHC controllers"
 				"(%d) than supported by the board\n", i + 1);
 			return 0;
 			}
 		if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
 			printf("Warning: failed to initialize mmc dev %d\n", i);
 	}
 	return 0;
 }
 int check_mmc_autodetect(void)
 {
 	char *autodetect_str = getenv("mmcautodetect");
 	if ((autodetect_str != NULL) &&
 		(strcmp(autodetect_str, "yes") == 0)) {
 		return 1;
 	}
 	return 0;
 }
 void board_late_mmc_env_init(void)
 {
 	char cmd[32];
 	char mmcblk[32];
 	u32 dev_no = mmc_get_env_devno();
 	if (!check_mmc_autodetect())
 		return;
 	setenv_ulong("mmcdev", dev_no);
 	/* Set mmcblk env */
 	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
 		mmc_map_to_kernel_blk(dev_no));
 	setenv("mmcroot", mmcblk);
 	sprintf(cmd, "mmc dev %d", dev_no);
 	run_command(cmd, 0);
 }
 #endif
 #ifdef CONFIG_SYS_USE_SPINOR
 iomux_v3_cfg_t const ecspi1_pads[] = {
 	MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 	MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 	MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 	MX6_PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(NO_PAD_CTRL),
 	/* Steer logic */
 	MX6_PAD_EIM_A24__GPIO5_IO04  | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 void setup_spinor(void)
 {
 	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 					 ARRAY_SIZE(ecspi1_pads));
 	gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
 	gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
 }
 #endif
 #ifdef CONFIG_SYS_USE_EIMNOR
 iomux_v3_cfg_t eimnor_pads[] = {
 	MX6_PAD_EIM_D16__EIM_DATA16      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_D17__EIM_DATA17      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_D18__EIM_DATA18      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_D19__EIM_DATA19      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_D20__EIM_DATA20      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_D21__EIM_DATA21      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_D22__EIM_DATA22      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_D23__EIM_DATA23      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_D24__EIM_DATA24      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_D25__EIM_DATA25      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_D26__EIM_DATA26      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_D27__EIM_DATA27      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_D28__EIM_DATA28      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_D29__EIM_DATA29      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_D30__EIM_DATA30      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_D31__EIM_DATA31      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_DA0__EIM_AD00    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_DA1__EIM_AD01    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_DA2__EIM_AD02    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_DA3__EIM_AD03    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_DA4__EIM_AD04    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_DA5__EIM_AD05    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_DA6__EIM_AD06    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_DA7__EIM_AD07    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_DA8__EIM_AD08    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_DA9__EIM_AD09    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_DA10__EIM_AD10   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_DA11__EIM_AD11   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
 	MX6_PAD_EIM_DA12__EIM_AD12   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_DA13__EIM_AD13   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_DA14__EIM_AD14   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_DA15__EIM_AD15   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_A16__EIM_ADDR16      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_A17__EIM_ADDR17      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_A18__EIM_ADDR18      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_A19__EIM_ADDR19      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_A20__EIM_ADDR20      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_A21__EIM_ADDR21      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_A22__EIM_ADDR22      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_A23__EIM_ADDR23      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 	MX6_PAD_EIM_OE__EIM_OE_B         | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_EIM_RW__EIM_RW           | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_EIM_CS0__EIM_CS0_B       | MUX_PAD_CTRL(NO_PAD_CTRL),
 	/* Steer logic */
 	MX6_PAD_EIM_A24__GPIO5_IO04      | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 static void eimnor_cs_setup(void)
 {
 	writel(0x00000120, WEIM_BASE_ADDR + 0x090);
 	writel(0x00020181, WEIM_BASE_ADDR + 0x000);
 	writel(0x00000001, WEIM_BASE_ADDR + 0x004);
 	writel(0x0a020000, WEIM_BASE_ADDR + 0x008);
 	writel(0x0000c000, WEIM_BASE_ADDR + 0x00c);
 	writel(0x0804a240, WEIM_BASE_ADDR + 0x010);
 }
 static void setup_eimnor(void)
 {
 	imx_iomux_v3_setup_multiple_pads(eimnor_pads,
 			ARRAY_SIZE(eimnor_pads));
 	gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
 	eimnor_cs_setup();
 }
 #endif
 #ifdef CONFIG_SYS_USE_NAND
 iomux_v3_cfg_t gpmi_pads[] = {
 	MX6_PAD_NANDF_CLE__NAND_CLE		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6_PAD_NANDF_ALE__NAND_ALE		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6_PAD_NANDF_WP_B__NAND_WP_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6_PAD_NANDF_RB0__NAND_READY_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL0),
 	MX6_PAD_NANDF_CS0__NAND_CE0_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6_PAD_SD4_CMD__NAND_RE_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6_PAD_SD4_CLK__NAND_WE_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6_PAD_NANDF_D0__NAND_DATA00	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6_PAD_NANDF_D1__NAND_DATA01	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6_PAD_NANDF_D2__NAND_DATA02	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6_PAD_NANDF_D3__NAND_DATA03	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6_PAD_NANDF_D4__NAND_DATA04	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6_PAD_NANDF_D5__NAND_DATA05	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6_PAD_NANDF_D6__NAND_DATA06	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6_PAD_NANDF_D7__NAND_DATA07	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6_PAD_SD4_DAT0__NAND_DQS		| MUX_PAD_CTRL(GPMI_PAD_CTRL1),
 };
 static void setup_gpmi_nand(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	/* config gpmi nand iomux */
 	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
 	/* gate ENFC_CLK_ROOT clock first,before clk source switch */
 	clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 	/* config gpmi and bch clock to 100 MHz */
 	clrsetbits_le32(&mxc_ccm->cs2cdr,
 			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 	/* enable ENFC_CLK_ROOT clock */
 	setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 	/* enable gpmi and bch clock gating */
 	setbits_le32(&mxc_ccm->CCGR4,
 		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 	/* enable apbh clock gating */
 	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 }
 #endif
 #ifdef CONFIG_MAX7310_IOEXP
 void reset_max7310(void)
 {
 	gpio_direction_output(I2C_EXP_RST, 1);
 	imx_iomux_v3_setup_multiple_pads(port_exp,
 					ARRAY_SIZE(port_exp));
 }
 int setup_max7310(void)
 {
 #ifdef CONFIG_SYS_I2C_MXC
 	/* set steering config to i2c,
 	  * note: this causes pin conflicts with eimnor and spinor
 	  */
     gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
 	imx_iomux_v3_setup_multiple_pads(i2c3_pads,
 					ARRAY_SIZE(i2c3_pads));
 	/*setup i2c info 2*/
 	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 	gpio_exp_setup_port(1, 2, 0x30);
 	gpio_exp_setup_port(2, 2, 0x32);
 	gpio_exp_setup_port(3, 2, 0x34);
 	return 0;
 #else
 	return -EPERM;
 #endif
 }
 #endif
 int mx6_rgmii_rework(struct phy_device *phydev)
 {
 	unsigned short val;
 	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 	val &= 0xffe3;
 	val |= 0x18;
 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 	/* introduce tx clock delay */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 	val |= 0x0100;
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 	return 0;
 }
 int board_phy_config(struct phy_device *phydev)
 {
 	mx6_rgmii_rework(phydev);
 	if (phydev->drv->config)
 		phydev->drv->config(phydev);
 	return 0;
 }
 #if defined(CONFIG_VIDEO_IPUV3)
 struct display_info_t {
 	int	bus;
 	int	addr;
 	int	pixfmt;
 	int	(*detect)(struct display_info_t const *dev);
 	void	(*enable)(struct display_info_t const *dev);
 	struct	fb_videomode mode;
 };
 static void disable_lvds(struct display_info_t const *dev)
 {
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	int reg = readl(&iomux->gpr[2]);
 	reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 		 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 	writel(reg, &iomux->gpr[2]);
 }
 static void do_enable_hdmi(struct display_info_t const *dev)
 {
 	disable_lvds(dev);
 	imx_enable_hdmi_phy();
 }
 static struct display_info_t const displays[] = {{
 	.bus	= -1,
 	.addr	= 0,
 	.pixfmt	= IPU_PIX_FMT_RGB666,
 	.detect	= NULL,
 	.enable	= NULL,
 	.mode	= {
 		.name           = "Hannstar-XGA",
 		.refresh        = 60,
 		.xres           = 1024,
 		.yres           = 768,
 		.pixclock       = 15385,
 		.left_margin    = 220,
 		.right_margin   = 40,
 		.upper_margin   = 21,
 		.lower_margin   = 7,
 		.hsync_len      = 60,
 		.vsync_len      = 10,
 		.sync           = FB_SYNC_EXT,
 		.vmode          = FB_VMODE_NONINTERLACED
 } }, {
 	.bus	= -1,
 	.addr	= 0,
 	.pixfmt	= IPU_PIX_FMT_RGB24,
 	.detect	= NULL,
 	.enable	= do_enable_hdmi,
 	.mode	= {
 		.name           = "HDMI",
 		.refresh        = 60,
 		.xres           = 640,
 		.yres           = 480,
 		.pixclock       = 39721,
 		.left_margin    = 48,
 		.right_margin   = 16,
 		.upper_margin   = 33,
 		.lower_margin   = 10,
 		.hsync_len      = 96,
 		.vsync_len      = 2,
 		.sync           = 0,
 		.vmode          = FB_VMODE_NONINTERLACED
 } } };
 int board_video_skip(void)
 {
 	int i;
 	int ret;
 	char const *panel = getenv("panel");
 	if (!panel) {
 		for (i = 0; i < ARRAY_SIZE(displays); i++) {
 			struct display_info_t const *dev = displays+i;
 			if (dev->detect && dev->detect(dev)) {
 				panel = dev->mode.name;
 				printf("auto-detected panel %s\n", panel);
 				break;
 			}
 		}
 		if (!panel) {
 			panel = displays[0].mode.name;
 			printf("No panel detected: default to %s\n", panel);
 			i = 0;
 		}
 	} else {
 		for (i = 0; i < ARRAY_SIZE(displays); i++) {
 			if (!strcmp(panel, displays[i].mode.name))
 				break;
 		}
 	}
 	if (i < ARRAY_SIZE(displays)) {
 		ret = ipuv3_fb_init(&displays[i].mode, 0,
 				    displays[i].pixfmt);
 		if (!ret) {
 			if (displays[i].enable)
 				displays[i].enable(displays+i);
 			printf("Display: %s (%ux%u)\n",
 			       displays[i].mode.name,
 			       displays[i].mode.xres,
 			       displays[i].mode.yres);
 		} else
 			printf("LCD %s cannot be configured: %d\n",
 			       displays[i].mode.name, ret);
 	} else {
 		printf("unsupported panel %s\n", panel);
 		return -EINVAL;
 	}
 	return 0;
 }
 iomux_v3_cfg_t const backlight_pads[] = {
 	MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 };
 static void setup_iomux_backlight(void)
 {
 	gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
 	imx_iomux_v3_setup_multiple_pads(backlight_pads,
 					 ARRAY_SIZE(backlight_pads));
 }
 static void setup_display(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	int reg;
 	setup_iomux_backlight();
 	enable_ipu_clock();
 	imx_setup_hdmi();
 	/* Turn on LDB_DI0 and LDB_DI1 clocks */
 	reg = readl(&mxc_ccm->CCGR3);
 	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
 	writel(reg, &mxc_ccm->CCGR3);
 	/* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
 	reg = readl(&mxc_ccm->cs2cdr);
 	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
 		 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
 	       (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 	writel(reg, &mxc_ccm->cs2cdr);
 	reg = readl(&mxc_ccm->cscmr2);
 	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
 	writel(reg, &mxc_ccm->cscmr2);
 	reg = readl(&mxc_ccm->chsccdr);
 	reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
 		MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 	reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
 		MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 	writel(reg, &mxc_ccm->chsccdr);
 	reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 	      IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 	      IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 	      IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
 	      IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 	      IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
 	      IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 	      IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
 	writel(reg, &iomux->gpr[2]);
 	reg = readl(&iomux->gpr[3]);
 	reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 		 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 	reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 		IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
 	       (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 		IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
 	writel(reg, &iomux->gpr[3]);
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
 /*
  * Do not overwrite the console
  * Use always serial for U-Boot console
  */
 int overwrite_console(void)
 {
 	return 1;
 }
 int board_eth_init(bd_t *bis)
 {
 	setup_iomux_enet();
 	return cpu_eth_init(bis);
 }
 #define BOARD_REV_B  0x200
 #define BOARD_REV_A  0x100
 static int mx6sabre_rev(void)
 {
 	/*
 	 * Get Board ID information from OCOTP_GP1[15:8]
 	 * i.MX6Q ARD RevA: 0x01
 	 * i.MX6Q ARD RevB: 0x02
 	 */
 	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 	struct fuse_bank *bank = &ocotp->bank[4];
 	struct fuse_bank4_regs *fuse =
 			(struct fuse_bank4_regs *)bank->fuse_regs;
 	int reg = readl(&fuse->gp1);
 	int ret;
 	switch (reg >> 8 & 0x0F) {
 	case 0x02:
 		ret = BOARD_REV_B;
 		break;
 	case 0x01:
 	default:
 		ret = BOARD_REV_A;
 		break;
 	}
 	return ret;
 }
 u32 get_board_rev(void)
 {
 	int rev = mx6sabre_rev();
 	return (get_cpu_rev() & ~(0xF << 8)) | rev;
 }
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
 #ifdef CONFIG_MAX7310_IOEXP
 	/*Reset gpio expander at early stage*/
 	reset_max7310();
 #endif
 #if defined(CONFIG_VIDEO_IPUV3)
 	setup_display();
 #endif
 #ifdef CONFIG_SYS_USE_SPINOR
 	setup_spinor();
 #endif
 #ifdef CONFIG_SYS_USE_EIMNOR
 	setup_eimnor();
 #endif
 #ifdef CONFIG_SYS_USE_NAND
 	setup_gpmi_nand();
 #endif
 #ifdef CONFIG_CMD_SATA
 	setup_sata();
 #endif
 	return 0;
 }
 int board_init(void)
 {
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 	return 0;
 }
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
 	/* 4 bit bus width */
 	{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 	{NULL,   0},
 };
 #endif
 int board_late_init(void)
 {
 	int ret;
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
 #endif
 #ifdef CONFIG_SYS_I2C_MXC
 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 	ret = setup_pmic_voltages();
 	if (ret)
 		return -1;
 #endif
 #ifdef CONFIG_MAX7310_IOEXP
 	setup_max7310();
 #endif
 #ifdef CONFIG_ENV_IS_IN_MMC
 	board_late_mmc_env_init();
 #endif
 	return 0;
 }
 #ifdef CONFIG_FASTBOOT
 void board_fastboot_setup(void)
 {
 	switch (get_boot_device()) {
 #if defined(CONFIG_FASTBOOT_STORAGE_SATA)
 	case SATA_BOOT:
 		if (!getenv("fastboot_dev"))
 			setenv("fastboot_dev", "sata");
 		if (!getenv("bootcmd"))
 			setenv("bootcmd", "booti sata");
 		break;
 #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/
 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
 	case SD1_BOOT:
 	case MMC1_BOOT:
 		if (!getenv("fastboot_dev"))
 			setenv("fastboot_dev", "mmc0");
 		if (!getenv("bootcmd"))
 			setenv("bootcmd", "booti mmc0");
 		break;
 	case SD3_BOOT:
 	case MMC3_BOOT:
 		if (!getenv("fastboot_dev"))
 			setenv("fastboot_dev", "mmc1");
 		if (!getenv("bootcmd"))
 			setenv("bootcmd", "booti mmc1");
 		break;
 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
 #if defined(CONFIG_FASTBOOT_STORAGE_NAND)
 	case NAND_BOOT:
 		if (!getenv("fastboot_dev"))
 			setenv("fastboot_dev", "nand");
 		if (!getenv("fbparts"))
-			setenv("fbparts",
+			setenv("fbparts", ANDROID_FASTBOOT_NAND_PARTS);
-			 "16m@16m(boot) 16m@32m(recovery) 810m@48m(android_root)ubifs");
 		if (!getenv("bootcmd"))
 			setenv("bootcmd",
 				"nand read ${loadaddr} ${boot_nand_offset} "
 				"${boot_nand_size};booti ${loadaddr}");
 		break;
 #endif /*CONFIG_FASTBOOT_STORAGE_NAND*/
 	default:
 		printf("unsupported boot devices\n");
 		break;
 	}
 }
 #ifdef CONFIG_ANDROID_RECOVERY
 #define GPIO_VOL_DN_KEY IMX_GPIO_NR(5, 14)
 iomux_v3_cfg_t const recovery_key_pads[] = {
 	(MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 int check_recovery_cmd_file(void)
 {
 	int button_pressed = 0;
 	int recovery_mode = 0;
 	recovery_mode = recovery_check_and_clean_flag();
 	/* Check Recovery Combo Button press or not. */
 	imx_iomux_v3_setup_multiple_pads(recovery_key_pads,
 		ARRAY_SIZE(recovery_key_pads));
 	gpio_direction_input(GPIO_VOL_DN_KEY);
 	if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */
 		button_pressed = 1;
 		printf("Recovery key pressed\n");
 	}
 	return recovery_mode || button_pressed;
 }
 void board_recovery_setup(void)
 {
 	int bootdev = get_boot_device();
 	switch (bootdev) {
 #if defined(CONFIG_FASTBOOT_STORAGE_SATA)
 	case SATA_BOOT:
 		if (!getenv("bootcmd_android_recovery"))
 			setenv("bootcmd_android_recovery", "booti sata recovery");
 		break;
 #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/
 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
 	case SD1_BOOT:
 	case MMC1_BOOT:
 		if (!getenv("bootcmd_android_recovery"))
 			setenv("bootcmd_android_recovery", "booti mmc0 recovery");
 		break;
 	case SD3_BOOT:
 	case MMC3_BOOT:
 		if (!getenv("bootcmd_android_recovery"))
 			setenv("bootcmd_android_recovery", "booti mmc1 recovery");
 		break;
 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
 #if defined(CONFIG_FASTBOOT_STORAGE_NAND)
 	case NAND_BOOT:
 		if (!getenv("bootcmd_android_recovery"))
 			setenv("bootcmd_android_recovery",
 				"nand read ${loadaddr} ${recovery_nand_offset} "
 				"${recovery_nand_size};booti ${loadaddr}");
 		break;
 #endif /*CONFIG_FASTBOOT_STORAGE_NAND*/
 	default:
 		printf("Unsupported bootup device for recovery: dev: %d\n",
 			bootdev);
 		return;
 	}
 	printf("setup env for recovery..\n");
 	setenv("bootcmd", "run bootcmd_android_recovery");
 }
 #endif /*CONFIG_ANDROID_RECOVERY*/
 #endif /*CONFIG_FASTBOOT*/
 int checkboard(void)
 {
 	int rev = mx6sabre_rev();
 	char *revname;
 	switch (rev) {
 	case BOARD_REV_B:
 		revname = "B";
 		break;
 	case BOARD_REV_A:
 	default:
 		revname = "A";
 		break;
 	}
 	printf("Board: MX6-Sabreauto rev%s\n", revname);
 	return 0;
 }
 #ifdef CONFIG_IMX_UDC
 iomux_v3_cfg_t const otg_udc_pads[] = {
 	(MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 void udc_pins_setting(void)
 {
 	imx_iomux_v3_setup_multiple_pads(otg_udc_pads,
 		ARRAY_SIZE(otg_udc_pads));
 	/*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/
     mxc_iomux_set_gpr_register(1, 13, 1, 0);
 }
 #endif /*CONFIG_IMX_UDC*/
 #ifdef CONFIG_USB_EHCI_MX6
 #define USB_HOST1_PWR     IOEXP_GPIO_NR(2, 7)
 #define USB_OTG_PWR       IOEXP_GPIO_NR(3, 1)
 iomux_v3_cfg_t const usb_otg_pads[] = {
 	MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 int board_ehci_hcd_init(int port)
 {
 	switch (port) {
 	case 0:
 		imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 			ARRAY_SIZE(usb_otg_pads));
 		/*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/
 		mxc_iomux_set_gpr_register(1, 13, 1, 0);
 		break;
 	case 1:
 		break;
 	default:
 		printf("MXC USB port %d not yet supported\n", port);
 		return 1;
 	}
 	return 0;
 }
 int board_ehci_power(int port, int on)
 {
 	switch (port) {
 	case 0:
 		if (on)
 			gpio_exp_direction_output(USB_OTG_PWR, 1);
 		else
 			gpio_exp_direction_output(USB_OTG_PWR, 0);
 		break;
 	case 1:
 		if (on)
 			gpio_exp_direction_output(USB_HOST1_PWR, 1);
 		else
 			gpio_exp_direction_output(USB_HOST1_PWR, 0);
 		break;
 	default:
 		printf("MXC USB port %d not yet supported\n", port);
 		return 1;
 	}
 	return 0;
 }
 #endif

board/freescale/mx6sxsabreauto/mx6sxsabreauto.c

Diff comments View file @ 3ddc0dd

 /*
  * Copyright (C) 2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/boot_mode.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
 #include <fsl_esdhc.h>
 #include <mmc.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/crm_regs.h>
 #ifdef CONFIG_SYS_I2C_MXC
 #include <i2c.h>
 #include <asm/imx-common/mxc_i2c.h>
 #endif
 #ifdef CONFIG_MXC_RDC
 #include <asm/imx-common/rdc-sema.h>
 #include <asm/arch/imx-rdc.h>
 #endif
 #ifdef CONFIG_VIDEO_MXS
 #include <linux/fb.h>
 #include <mxsfb.h>
 #endif
 #ifdef CONFIG_MAX7310_IOEXP
 #include <gpio_exp.h>
 #endif
 #ifdef CONFIG_FASTBOOT
 #include <fastboot.h>
 #ifdef CONFIG_ANDROID_RECOVERY
 #include <recovery.h>
 #endif
 #endif /*CONFIG_FASTBOOT*/
 DECLARE_GLOBAL_DATA_PTR;
 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
 	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
 	PAD_CTL_SPEED_HIGH   |                                   \
 	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
 #define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
 	PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
 	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
 	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
 	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
 #define BUTTON_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE | \
 	PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_40ohm)
 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
 			PAD_CTL_SRE_FAST)
 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 /* I2C2 for PMIC */
 struct i2c_pads_info i2c_pad_info2 = {
 	.scl = {
 		.i2c_mode = MX6SX_PAD_GPIO1_IO02__I2C2_SCL | PC,
 		.gpio_mode = MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
 		.gp = IMX_GPIO_NR(1, 2),
 	},
 	.sda = {
 		.i2c_mode = MX6SX_PAD_GPIO1_IO03__I2C2_SDA | PC,
 		.gpio_mode = MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
 		.gp = IMX_GPIO_NR(1, 3),
 	},
 };
 /* I2C3 */
 struct i2c_pads_info i2c_pad_info3 = {
 	.scl = {
 		.i2c_mode = MX6SX_PAD_KEY_COL4__I2C3_SCL | PC,
 		.gpio_mode = MX6SX_PAD_KEY_COL4__GPIO2_IO_14 | PC,
 		.gp = IMX_GPIO_NR(2, 14),
 	},
 	.sda = {
 		.i2c_mode = MX6SX_PAD_KEY_ROW4__I2C3_SDA | PC,
 		.gpio_mode = MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 | PC,
 		.gp = IMX_GPIO_NR(2, 19),
 	},
 };
 #endif
 int dram_init(void)
 {
 	gd->ram_size = PHYS_SDRAM_SIZE;
 	return 0;
 }
 static iomux_v3_cfg_t const uart1_pads[] = {
 	MX6SX_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 	MX6SX_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 static iomux_v3_cfg_t const usdhc3_pads[] = {
 	MX6SX_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	/* CD pin */
 	MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	/* RST_B, used for power reset cycle */
 	MX6SX_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 static iomux_v3_cfg_t const usdhc4_pads[] = {
 	MX6SX_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	/* CD pin */
 	MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 #ifdef CONFIG_FEC_MXC
 static iomux_v3_cfg_t const fec1_pads[] = {
 	MX6SX_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6SX_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 };
 static iomux_v3_cfg_t const fec2_pads[] = {
 	MX6SX_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6SX_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 };
 static void setup_iomux_fec(int fec_id)
 {
 	if (0 == fec_id)
 		imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 	else
 		imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
 }
 #endif
 #ifdef CONFIG_MAX7310_IOEXP
 #define CPU_PER_RST_B	IOEXP_GPIO_NR(1, 4)
 #define LVDS_EN_PIN		IOEXP_GPIO_NR(1, 7)
 #define STEER_ENET		IOEXP_GPIO_NR(2, 2)
 int setup_max7310(void)
 {
 	/* Must call this function after i2c has setup */
 #ifdef CONFIG_SYS_I2C_MXC
 	gpio_exp_setup_port(1, 2, 0x30);
 	gpio_exp_setup_port(2, 2, 0x32);
 	return 0;
 #else
 	return -EPERM;
 #endif
 }
 #endif
 static void setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 #ifdef CONFIG_QSPI
 #define QSPI_PAD_CTRL1	\
 		(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
 		 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
 static iomux_v3_cfg_t const quadspi_pads[] = {
 	MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 	MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK     | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 	MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 	MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 	MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 	MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 	MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 	MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK     | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 	MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 	MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 	MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 	MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 };
 int board_qspi_init(void)
 {
 	/* Set the iomux */
 	imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
 	/* Set the clock */
 	enable_qspi_clk(0);
 	return 0;
 }
 #endif
 #ifdef CONFIG_SYS_USE_NAND
 iomux_v3_cfg_t gpmi_pads[] = {
 	MX6SX_PAD_NAND_CLE__RAWNAND_CLE		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6SX_PAD_NAND_ALE__RAWNAND_ALE		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL0),
 	MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 	MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 };
 static void setup_gpmi_nand(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	/* config gpmi nand iomux */
 	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
 	/* Disable the QSPI2 root clock */
 	clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
 				| MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 	/* config gpmi and bch clock to 100 MHz */
 	clrsetbits_le32(&mxc_ccm->cs2cdr,
 			MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
 			MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
 			MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
 			MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
 			MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
 			MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3));
 	/* enable gpmi and bch clock gating */
 	setbits_le32(&mxc_ccm->CCGR4,
 		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK |
 		     MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
 	/* enable apbh clock gating */
 	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 }
 #endif
 #ifdef CONFIG_FSL_ESDHC
 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 	{USDHC3_BASE_ADDR},
 	{USDHC4_BASE_ADDR},
 };
 #define USDHC3_CD_GPIO	IMX_GPIO_NR(7, 10)
 #define USDHC3_RST_GPIO	IMX_GPIO_NR(2, 11)
 #define USDHC4_CD_GPIO	IMX_GPIO_NR(7, 11)
 int mmc_get_env_devno(void)
 {
 	u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
 	int dev_no;
 	u32 bootsel;
 	bootsel = (soc_sbmr & 0x000000FF) >> 6 ;
 	/* If not boot from sd/mmc, use default value */
 	if (bootsel != 1)
 		return CONFIG_SYS_MMC_ENV_DEV;
 	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
 	dev_no = (soc_sbmr & 0x00001800) >> 11;
 	/* need ubstract 1 to map to the mmc device id
 	 * see the comments in board_mmc_init function
 	 */
 	dev_no -= 2;
 	return dev_no;
 }
 int mmc_map_to_kernel_blk(int dev_no)
 {
 	return dev_no + 2;
 }
 int board_mmc_getcd(struct mmc *mmc)
 {
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	int ret = 0;
 	switch (cfg->esdhc_base) {
 	case USDHC3_BASE_ADDR:
 		ret = !gpio_get_value(USDHC3_CD_GPIO);
 		break;
 	case USDHC4_BASE_ADDR:
 		ret = !gpio_get_value(USDHC4_CD_GPIO);
 		break;
 	}
 	return ret;
 }
 int board_mmc_init(bd_t *bis)
 {
 	int i;
 	/*
 	 * According to the board_mmc_init() the following map is done:
 	 * (U-boot device node)    (Physical Port)
 	 * mmc0                    USDHC3
 	 * mmc1                    USDHC4
 	 */
 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 		switch (i) {
 		case 0:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 			gpio_direction_input(USDHC3_CD_GPIO);
 			/* Need to set steer to B0 to A*/
 			gpio_direction_output(USDHC3_RST_GPIO, 1);
 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 			break;
 		case 1:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 			gpio_direction_input(USDHC4_CD_GPIO);
 			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 			break;
 		default:
 			printf("Warning: you configured more USDHC controllers"
 				"(%d) than supported by the board\n", i + 1);
 			return 0;
 			}
 			if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
 				printf("Warning: failed to initialize mmc dev %d\n", i);
 	}
 	return 0;
 }
 int check_mmc_autodetect(void)
 {
 	char *autodetect_str = getenv("mmcautodetect");
 	if ((autodetect_str != NULL) &&
 		(strcmp(autodetect_str, "yes") == 0)) {
 		return 1;
 	}
 	return 0;
 }
 void board_late_mmc_init(void)
 {
 	char cmd[32];
 	char mmcblk[32];
 	u32 dev_no = mmc_get_env_devno();
 	if (!check_mmc_autodetect())
 		return;
 	setenv_ulong("mmcdev", dev_no);
 	/* Set mmcblk env */
 	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
 		mmc_map_to_kernel_blk(dev_no));
 	setenv("mmcroot", mmcblk);
 	sprintf(cmd, "mmc dev %d", dev_no);
 	run_command(cmd, 0);
 }
 #endif
 #ifdef CONFIG_VIDEO_MXS
 static iomux_v3_cfg_t const lvds_ctrl_pads[] = {
 	/* Use GPIO for Brightness adjustment, duty cycle = period */
 	MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 static iomux_v3_cfg_t const lcd_pads[] = {
 	MX6SX_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 struct lcd_panel_info_t {
 	unsigned int lcdif_base_addr;
 	int depth;
 	void	(*enable)(struct lcd_panel_info_t const *dev);
 	struct fb_videomode mode;
 };
 void do_enable_lvds(struct lcd_panel_info_t const *dev)
 {
 	enable_lcdif_clock(dev->lcdif_base_addr);
 	enable_lvds(dev->lcdif_base_addr);
 	imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads,
 							ARRAY_SIZE(lvds_ctrl_pads));
 #ifdef CONFIG_MAX7310_IOEXP
 	/* LVDS Enable pin */
 	gpio_exp_direction_output(LVDS_EN_PIN , 1);
 #endif
 	/* Set Brightness to high */
 	gpio_direction_output(IMX_GPIO_NR(6, 3) , 1);
 }
 void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev)
 {
 	enable_lcdif_clock(dev->lcdif_base_addr);
 	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 	/* Power up the LCD */
 	gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
 }
 static struct lcd_panel_info_t const displays[] = {{
 	.lcdif_base_addr = LCDIF2_BASE_ADDR,
 	.depth = 18,
 	.enable	= do_enable_lvds,
 	.mode	= {
 		.name			= "Hannstar-XGA",
 		.xres           = 1024,
 		.yres           = 768,
 		.pixclock       = 15385,
 		.left_margin    = 220,
 		.right_margin   = 40,
 		.upper_margin   = 21,
 		.lower_margin   = 7,
 		.hsync_len      = 60,
 		.vsync_len      = 10,
 		.sync           = 0,
 		.vmode          = FB_VMODE_NONINTERLACED
 } }, {
 	.lcdif_base_addr = LCDIF1_BASE_ADDR,
 	.depth = 18,
 	.enable	= do_enable_parallel_lcd,
 	.mode	= {
 		.name			= "Boundary-LCD",
 		.xres           = 800,
 		.yres           = 480,
 		.pixclock       = 29850,
 		.left_margin    = 89,
 		.right_margin   = 164,
 		.upper_margin   = 23,
 		.lower_margin   = 10,
 		.hsync_len      = 10,
 		.vsync_len      = 10,
 		.sync           = 0,
 		.vmode          = FB_VMODE_NONINTERLACED
 } } };
 int board_video_skip(void)
 {
 	int i;
 	int ret;
 	char const *panel = getenv("panel");
 	if (!panel) {
 		panel = displays[0].mode.name;
 		printf("No panel detected: default to %s\n", panel);
 		i = 0;
 	} else {
 		for (i = 0; i < ARRAY_SIZE(displays); i++) {
 			if (!strcmp(panel, displays[i].mode.name))
 				break;
 		}
 	}
 	if (i < ARRAY_SIZE(displays)) {
 		ret = mxs_lcd_panel_setup(displays[i].mode, displays[i].depth,
 				    displays[i].lcdif_base_addr);
 		if (!ret) {
 			if (displays[i].enable)
 				displays[i].enable(displays+i);
 			printf("Display: %s (%ux%u)\n",
 			       displays[i].mode.name,
 			       displays[i].mode.xres,
 			       displays[i].mode.yres);
 		} else
 			printf("LCD %s cannot be configured: %d\n",
 			       displays[i].mode.name, ret);
 	} else {
 		printf("unsupported panel %s\n", panel);
 		return -EINVAL;
 	}
 	return 0;
 }
 #endif
 #ifdef CONFIG_FEC_MXC
 int board_eth_init(bd_t *bis)
 {
 	int ret;
 	setup_iomux_fec(CONFIG_FEC_ENET_DEV);
 	ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
 		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
 	if (ret)
 		printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
 	return 0;
 }
 static int setup_fec(int fec_id)
 {
 	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
 		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
 	int ret;
 	if (0 == fec_id)
 		/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
 		clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
 	else
 		/* Use 125M anatop REF_CLK1 for ENET2, clear gpr1[14], gpr1[18]*/
 		clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
 	ret = enable_fec_anatop_clock(fec_id, ENET_125MHz);
 	if (ret)
 		return ret;
 	enable_enet_clock();
 	return 0;
 }
 int board_phy_config(struct phy_device *phydev)
 {
 	/* Enable 1.8V(SEL_1P5_1P8_POS_REG) on Phy control debug reg 0 */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
 	/* rgmii tx clock delay enable */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
 	if (phydev->drv->config)
 		phydev->drv->config(phydev);
 	return 0;
 }
 #endif
 #ifdef CONFIG_PFUZE100_PMIC_I2C
 #define PFUZE100_DEVICEID	0x0
 #define PFUZE100_REVID		0x3
 #define PFUZE100_FABID		0x4
 #define PFUZE100_SW1ABVOL	0x20
 #define PFUZE100_SW1ABSTBY	0x21
 #define PFUZE100_SW1ABCONF	0x24
 #define PFUZE100_SW1CVOL	0x2e
 #define PFUZE100_SW1CSTBY	0x2f
 #define PFUZE100_SW1CCONF	0x32
 #define PFUZE100_SW1ABC_SETP(x)	((x - 3000) / 250)
 #define PFUZE100_VGEN5CTL	0x70
 /* set all switches APS in normal and PFM mode in standby */
 static int setup_pmic_mode(int chip)
 {
 	unsigned char offset, i, switch_num, value;
 	if (!chip) {
 		/* pfuze100 */
 		switch_num = 6;
 		offset = 0x31;
 	} else {
 		/* pfuze200 */
 		switch_num = 4;
 		offset = 0x38;
 	}
 	value = 0xc;
 	if (i2c_write(0x8, 0x23, 1, &value, 1)) {
 		printf("Set SW1AB mode error!\n");
 		return -1;
 	}
 	for (i = 0; i < switch_num - 1; i++) {
 		if (i2c_write(0x8, offset + i * 7, 1, &value, 1)) {
 			printf("Set switch%x mode error!\n", offset);
 			return -1;
 		}
 	}
 	return 0;
 }
 static int setup_pmic_voltages(void)
 {
 	unsigned char value, rev_id = 0;
 	i2c_set_bus_num(CONFIG_PMIC_I2C_BUS);
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_PMIC_I2C_SLAVE);
 	if (!i2c_probe(CONFIG_PMIC_I2C_SLAVE)) {
 		if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_DEVICEID, 1, &value, 1)) {
 			printf("Read device ID error!\n");
 			return -1;
 		}
 		if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_REVID, 1, &rev_id, 1)) {
 			printf("Read Rev ID error!\n");
 			return -1;
 		}
 		printf("Found PFUZE100! deviceid 0x%x, revid 0x%x\n", value, rev_id);
 		if (setup_pmic_mode(value & 0xf)) {
 			printf("setup pmic mode error!\n");
 			return -1;
 		}
 		/* set SW1AB standby volatage 0.975V */
 		if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABSTBY, 1, &value, 1)) {
 			printf("Read SW1ABSTBY error!\n");
 			return -1;
 		}
 		value &= ~0x3f;
 		value |= PFUZE100_SW1ABC_SETP(9750);
 		if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABSTBY, 1, &value, 1)) {
 			printf("Set SW1ABSTBY error!\n");
 			return -1;
 		}
 		/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 		if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABCONF, 1, &value, 1)) {
 			printf("Read SW1ABCONFIG error!\n");
 			return -1;
 		}
 		value &= ~0xc0;
 		value |= 0x40;
 		if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABCONF, 1, &value, 1)) {
 			printf("Set SW1ABCONFIG error!\n");
 			return -1;
 		}
 		/* set SW1C standby volatage 0.975V */
 		if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CSTBY, 1, &value, 1)) {
 			printf("Read SW1CSTBY error!\n");
 			return -1;
 		}
 		value &= ~0x3f;
 		value |= PFUZE100_SW1ABC_SETP(9750);
 		if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CSTBY, 1, &value, 1)) {
 			printf("Set SW1CSTBY error!\n");
 			return -1;
 		}
 		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
 		if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CCONF, 1, &value, 1)) {
 			printf("Read SW1CCONFIG error!\n");
 			return -1;
 		}
 		value &= ~0xc0;
 		value |= 0x40;
 		if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CCONF, 1, &value, 1)) {
 			printf("Set SW1CCONFIG error!\n");
 			return -1;
 		}
 		/* Enable power of VGEN5 3V3, needed for SD3 */
 		if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_VGEN5CTL, 1, &value, 1)) {
 			printf("Read VGEN5CTL error!\n");
 			return -1;
 		}
 		value &= ~0x1F;
 		value |= 0x1F;
 		if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_VGEN5CTL, 1, &value, 1)) {
 			printf("Set VGEN5CTL error!\n");
 			return -1;
 		}
 	}
 	return 0;
 }
 #ifdef CONFIG_LDO_BYPASS_CHECK
 void ldo_mode_set(int ldo_bypass)
 {
 	unsigned char value;
 	/* switch to ldo_bypass mode */
 	if (ldo_bypass) {
 		/* decrease VDDARM to 1.15V */
 		if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) {
 			printf("Read SW1AB error!\n");
 			return;
 		}
 		value &= ~0x3f;
 		value |= PFUZE100_SW1ABC_SETP(11500);
 		if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) {
 			printf("Set SW1AB error!\n");
 			return;
 		}
 		/* increase VDDSOC to 1.15V */
 		if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) {
 			printf("Read SW1C error!\n");
 			return;
 		}
 		value &= ~0x3f;
 		value |= PFUZE100_SW1ABC_SETP(11500);
 		if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) {
 			printf("Set SW1C error!\n");
 			return;
 		}
 		set_anatop_bypass(1);
 		printf("switch to ldo_bypass mode!\n");
 	}
 }
 #endif
 #endif
 #ifdef CONFIG_MXC_RDC
 static rdc_peri_cfg_t const shared_resources[] = {
 	(RDC_PER_GPIO1 | RDC_DOMAIN(0) | RDC_DOMAIN(1)),
 };
 #endif
 int board_early_init_f(void)
 {
 #ifdef CONFIG_MXC_RDC
 	imx_rdc_setup_peripherals(shared_resources, ARRAY_SIZE(shared_resources));
 #endif
 #ifdef CONFIG_SYS_AUXCORE_FASTUP
 	arch_auxiliary_core_up(0, CONFIG_SYS_AUXCORE_BOOTDATA);
 #endif
 	setup_iomux_uart();
 	return 0;
 }
 int board_init(void)
 {
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 #ifdef CONFIG_SYS_I2C_MXC
 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 #endif
 #ifdef CONFIG_MAX7310_IOEXP
 	setup_max7310();
 	/* Reset CPU_PER_RST_B signal for enet phy and PCIE */
 	gpio_exp_direction_output(CPU_PER_RST_B, 0);
 	udelay(500);
 	gpio_exp_direction_output(CPU_PER_RST_B, 1);
 	/* Set steering signal to L for selecting B0 */
 	gpio_exp_direction_output(STEER_ENET, 0);
 #endif
 #ifdef	CONFIG_FEC_MXC
 	setup_fec(CONFIG_FEC_ENET_DEV);
 #endif
 #ifdef CONFIG_SYS_USE_NAND
 	setup_gpmi_nand();
 #endif
 #ifdef CONFIG_QSPI
 	board_qspi_init();
 #endif
 	return 0;
 }
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
 	{"sda", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
 	{"sdb", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 	{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
 	{"nand", MAKE_CFGVAL(0x82, 0x00, 0x00, 0x00)},
 	{NULL,	 0},
 };
 #endif
 int board_late_init(void)
 {
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
 #endif
 #ifdef CONFIG_PFUZE100_PMIC_I2C
 	int ret = 0;
 	ret = setup_pmic_voltages();
 	if (ret)
 		return -1;
 #endif
 #ifdef CONFIG_ENV_IS_IN_MMC
 	board_late_mmc_init();
 #endif
 	return 0;
 }
 u32 get_board_rev(void)
 {
 	return get_cpu_rev();
 }
 int checkboard(void)
 {
 	puts("Board: MX6SX SABRE AUTO\n");
 	return 0;
 }
 #ifdef CONFIG_USB_EHCI_MX6
 iomux_v3_cfg_t const usb_otg1_pads[] = {
 	MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL)
 };
 iomux_v3_cfg_t const usb_host2_pads[] = {
 	MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 int board_ehci_hcd_init(int port)
 {
 	switch (port) {
 	case 0:
 		imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
 			ARRAY_SIZE(usb_otg1_pads));
 		break;
 	case 1:
 		imx_iomux_v3_setup_multiple_pads(usb_host2_pads,
 			ARRAY_SIZE(usb_host2_pads));
 		break;
 	default:
 		printf("MXC USB port %d not yet supported\n", port);
 		return 1;
 	}
 	return 0;
 }
 #endif
 #ifdef CONFIG_FASTBOOT
 void board_fastboot_setup(void)
 {
 	switch (get_boot_device()) {
 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
 	case SD3_BOOT:
 	case MMC3_BOOT:
 		if (!getenv("fastboot_dev"))
 			setenv("fastboot_dev", "mmc0");
 		if (!getenv("bootcmd"))
 			setenv("bootcmd", "booti mmc0");
 		break;
 	case SD4_BOOT:
 	case MMC4_BOOT:
 		if (!getenv("fastboot_dev"))
 			setenv("fastboot_dev", "mmc1");
 		if (!getenv("bootcmd"))
 			setenv("bootcmd", "booti mmc1");
 		break;
 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
 #if defined(CONFIG_FASTBOOT_STORAGE_NAND)
 	case NAND_BOOT:
 		if (!getenv("fastboot_dev"))
 			setenv("fastboot_dev", "nand");
 		if (!getenv("fbparts"))
-			setenv("fbparts",
+			setenv("fbparts", ANDROID_FASTBOOT_NAND_PARTS);
-			 "16m@16m(boot) 16m@32m(recovery) 810m@48m(android_root)ubifs");
 		if (!getenv("bootcmd"))
 			setenv("bootcmd",
 				"nand read ${loadaddr} ${boot_nand_offset} "
 				"${boot_nand_size};booti ${loadaddr}");
 		break;
 #endif /*CONFIG_FASTBOOT_STORAGE_NAND*/
 	default:
 		printf("unsupported boot devices\n");
 		break;
 	}
 }
 #ifdef CONFIG_ANDROID_RECOVERY
 int check_recovery_cmd_file(void)
 {
 	int recovery_mode = 0;
 	recovery_mode = recovery_check_and_clean_flag();
 	return recovery_mode;
 }
 void board_recovery_setup(void)
 {
 	int bootdev = get_boot_device();
 	switch (bootdev) {
 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
 	case SD3_BOOT:
 	case MMC3_BOOT:
 		if (!getenv("bootcmd_android_recovery"))
 			setenv("bootcmd_android_recovery", "booti mmc0 recovery");
 		break;
 	case SD4_BOOT:
 	case MMC4_BOOT:
 		if (!getenv("bootcmd_android_recovery"))
 			setenv("bootcmd_android_recovery", "booti mmc1 recovery");
 		break;
 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
 #if defined(CONFIG_FASTBOOT_STORAGE_NAND)
 	case NAND_BOOT:
 		if (!getenv("bootcmd_android_recovery"))
 			setenv("bootcmd_android_recovery",
 				"nand read ${loadaddr} ${recovery_nand_offset} "
 				"${recovery_nand_size};booti ${loadaddr}");
 		break;
 #endif /*CONFIG_FASTBOOT_STORAGE_NAND*/
 	default:
 		printf("Unsupported bootup device for recovery: dev: %d\n",
 			bootdev);
 		return;
 	}
 	printf("setup env for recovery..\n");
 	setenv("bootcmd", "run bootcmd_android_recovery");
 }
 #endif /*CONFIG_ANDROID_RECOVERY*/
 #endif /*CONFIG_FASTBOOT*/
 #ifdef CONFIG_IMX_UDC
 iomux_v3_cfg_t const otg_udc_pads[] = {
 	(MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 void udc_pins_setting(void)
 {
 	imx_iomux_v3_setup_multiple_pads(otg_udc_pads,
 		ARRAY_SIZE(otg_udc_pads));
 }
 #endif /*CONFIG_IMX_UDC*/

include/configs/mx6sabreandroid_common.h

Diff comments View file @ 3ddc0dd

 /*
  * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef MX6_SABRE_ANDROID_COMMON_H
 #define MX6_SABRE_ANDROID_COMMON_H
 #define CONFIG_SERIAL_TAG
 #define CONFIG_USB_DEVICE
 #define CONFIG_IMX_UDC		       1
 #define CONFIG_FASTBOOT		       1
 #define CONFIG_FASTBOOT_VENDOR_ID      0x18d1
 #define CONFIG_FASTBOOT_PRODUCT_ID     0x0d02
 #define CONFIG_FASTBOOT_BCD_DEVICE     0x311
 #define CONFIG_FASTBOOT_MANUFACTURER_STR  "Freescale"
 #define CONFIG_FASTBOOT_PRODUCT_NAME_STR "i.mx6 Sabre Board"
 #define CONFIG_FASTBOOT_INTERFACE_STR	 "Android fastboot"
 #define CONFIG_FASTBOOT_CONFIGURATION_STR  "Android fastboot"
 #define CONFIG_FASTBOOT_SERIAL_NUM	"12345"
 #define CONFIG_FASTBOOT_SATA_NO		 0
 #if defined CONFIG_SYS_BOOT_NAND
 #define CONFIG_FASTBOOT_STORAGE_NAND
 #elif defined CONFIG_SYS_BOOT_SATA
 #define CONFIG_FASTBOOT_STORAGE_SATA
 #else
 #define CONFIG_FASTBOOT_STORAGE_MMC
 #endif
 /*  For system.img growing up more than 256MB, more buffer needs
 *   to receive the system.img*/
 #define CONFIG_FASTBOOT_TRANSFER_BUF	0x2c000000
 #define CONFIG_FASTBOOT_TRANSFER_BUF_SIZE 0x19000000 /* 400M byte */
 #define CONFIG_CMD_BOOTI
 #define CONFIG_ANDROID_RECOVERY
 /* which mmc bus is your main storage ? */
 #define CONFIG_ANDROID_MAIN_MMC_BUS 2
 #define CONFIG_ANDROID_BOOT_PARTITION_MMC 1
 #define CONFIG_ANDROID_SYSTEM_PARTITION_MMC 5
 #define CONFIG_ANDROID_RECOVERY_PARTITION_MMC 2
 #define CONFIG_ANDROID_CACHE_PARTITION_MMC 6
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #undef CONFIG_BOOTCOMMAND
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"splashpos=m,m\0"	  \
 	"fdt_high=0xffffffff\0"	  \
 	"initrd_high=0xffffffff\0" \
+#if defined(CONFIG_FASTBOOT_STORAGE_NAND)
+#define ANDROID_FASTBOOT_NAND_PARTS "16m@64m(boot) 16m@80m(recovery) 810m@96m(android_root)ubifs"
+#endif
 #endif /* MX6_SABRE_ANDROID_COMMON_H */

include/configs/mx6sxsabreautoandroid.h

Diff comments View file @ 3ddc0dd

 /*
  * Copyright (C) 2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __MX6SX_SABREAUTO_ANDROID_H
 #define __MX6SX_SABREAUTO_ANDROID_H
 #define CONFIG_SERIAL_TAG
 #define CONFIG_USB_DEVICE
 #define CONFIG_IMX_UDC		       1
 #define CONFIG_FASTBOOT		       1
 #define CONFIG_FASTBOOT_VENDOR_ID      0x18d1
 #define CONFIG_FASTBOOT_PRODUCT_ID     0x0d02
 #define CONFIG_FASTBOOT_BCD_DEVICE     0x311
 #define CONFIG_FASTBOOT_MANUFACTURER_STR  "Freescale"
 #define CONFIG_FASTBOOT_PRODUCT_NAME_STR "i.mx6sx SABRE-AUTO Board"
 #define CONFIG_FASTBOOT_INTERFACE_STR	 "Android fastboot"
 #define CONFIG_FASTBOOT_CONFIGURATION_STR  "Android fastboot"
 #define CONFIG_FASTBOOT_SERIAL_NUM	"12345"
 #define CONFIG_FASTBOOT_SATA_NO		 0
 #if defined CONFIG_SYS_BOOT_NAND
 #define CONFIG_FASTBOOT_STORAGE_NAND
 #else
 #define CONFIG_FASTBOOT_STORAGE_MMC
 #endif
 /*  For system.img growing up more than 256MB, more buffer needs
 *   to receive the system.img*/
 #define CONFIG_FASTBOOT_TRANSFER_BUF	0x8c000000
 #define CONFIG_FASTBOOT_TRANSFER_BUF_SIZE 0x19000000 /* 400M byte */
 #define CONFIG_CMD_BOOTI
 #define CONFIG_ANDROID_RECOVERY
 /* which mmc bus is your main storage ? */
 #define CONFIG_ANDROID_MAIN_MMC_BUS 2
 #define CONFIG_ANDROID_BOOT_PARTITION_MMC 1
 #define CONFIG_ANDROID_SYSTEM_PARTITION_MMC 5
 #define CONFIG_ANDROID_RECOVERY_PARTITION_MMC 2
 #define CONFIG_ANDROID_CACHE_PARTITION_MMC 6
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #undef CONFIG_BOOTCOMMAND
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"splashpos=m,m\0"	  \
 	"fdt_high=0xffffffff\0"	  \
 	"initrd_high=0xffffffff\0" \
+#if defined(CONFIG_FASTBOOT_STORAGE_NAND)
+#define ANDROID_FASTBOOT_NAND_PARTS "16m@64m(boot) 16m@80m(recovery) 810m@96m(android_root)ubifs"
+#endif
 #endif