Eric Lee / smarc-uboot | Embedian Git Server

Commit 47f9b4e1f3c2422ab72c66065eb92c66a9159c45

Authored by Marek Vasut 2014-09-08 20:08:45 +0800

Exists in v2017.01-smarct4x and in 37 other branches

arm: socfpga: Clean up SoCFPGA configuration

Reorganize and cleanup the configuration file for SoCFPGA. There
is no functional change after this cleanup. This was necessary,
since the file was a wild mess and it was impossible to make sense
of it's content, let alone change something without breaking some
other thing. This patch puts the contents on par with regular U-Boot
standards.

Also remove unused preprocessor symbols CONFIG_SINGLE_BOOTOADER
and CONFIG_USE_IRQ, which is undefined by default. Finally, do
logical reordering of the defines in the file so it's much more
readable. The reordering was also necessary for the splitting
as the initial one was messy.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

Showing 1 changed file with 187 additions and 218 deletions Inline Diff

include/configs/socfpga_cyclone5.h

include/configs/socfpga_cyclone5.h

Diff comments View file @ 47f9b4e

1	/*	1	/*
2	* Copyright (C) 2012 Altera Corporation <www.altera.com>	2	* Copyright (C) 2012 Altera Corporation <www.altera.com>
3	*	3	*
4	* SPDX-License-Identifier: GPL-2.0+	4	* SPDX-License-Identifier: GPL-2.0+
5	*/	5	*/
6	#ifndef __CONFIG_H	6	#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
7	#define __CONFIG_H	7	#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
8		8
9	#include <asm/arch/socfpga_base_addrs.h>	9	#include <asm/arch/socfpga_base_addrs.h>
10	#include "../../board/altera/socfpga/pinmux_config.h"	10	#include "../../board/altera/socfpga/pinmux_config.h"
11	#include "../../board/altera/socfpga/iocsr_config.h"	11	#include "../../board/altera/socfpga/iocsr_config.h"
12	#include "../../board/altera/socfpga/pll_config.h"	12	#include "../../board/altera/socfpga/pll_config.h"
13		13
14	/*	14	#define CONFIG_SYS_GENERIC_BOARD
15	* High level configuration	15
16	*/
17	/* Virtual target or real hardware */	16	/* Virtual target or real hardware */
18	#undef CONFIG_SOCFPGA_VIRTUAL_TARGET	17	#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
19		18
20	#define CONFIG_ARMV7	19	#define CONFIG_ARMV7
21	#undef CONFIG_USE_IRQ	20	#define CONFIG_SYS_THUMB_BUILD
22		21
23	#define CONFIG_MISC_INIT_R
24	#define CONFIG_SINGLE_BOOTLOADER
25	#define CONFIG_SOCFPGA	22	#define CONFIG_SOCFPGA
26	#define CONFIG_CLOCKS
27		23
28	#define CONFIG_SYS_ARM_CACHE_WRITEALLOC	24	/* U-Boot Commands */
29	#define CONFIG_SYS_CACHELINE_SIZE 32	25	#define CONFIG_SYS_NO_FLASH
30	#define CONFIG_SYS_L2_PL310	26	#include <config_cmd_default.h>
31	#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS	27	#define CONFIG_DOS_PARTITION
		28	#define CONFIG_FAT_WRITE
		29	#define CONFIG_HW_WATCHDOG
32		30
33	/* base address for .text section */	31	#define CONFIG_CMD_ASKENV
34	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET	32	#define CONFIG_CMD_BOOTZ
35	#define CONFIG_SYS_TEXT_BASE 0x08000040	33	#define CONFIG_CMD_CACHE
36	#else	34	#define CONFIG_CMD_DHCP
37	#define CONFIG_SYS_TEXT_BASE 0x01000040	35	#define CONFIG_CMD_EXT4
38	#endif	36	#define CONFIG_CMD_EXT4_WRITE
39	#define CONFIG_SYS_LOAD_ADDR 0x7fc0	37	#define CONFIG_CMD_FAT
		38	#define CONFIG_CMD_FPGA
		39	#define CONFIG_CMD_GREPENV
		40	#define CONFIG_CMD_MII
		41	#define CONFIG_CMD_MMC
		42	#define CONFIG_CMD_NET
		43	#define CONFIG_CMD_PING
		44	#define CONFIG_CMD_SETEXPR
40		45
41	/* Console I/O Buffer Size */	46	#define CONFIG_REGEX /* Enable regular expression support */
42	#define CONFIG_SYS_CBSIZE 256
43	/* Monitor Command Prompt */
44	#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # "
45	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
46	sizeof(CONFIG_SYS_PROMPT) + 16)
47		47
48	/*	48	/*
49	* Display CPU and Board Info	49	* High level configuration
50	*/	50	*/
51	#define CONFIG_DISPLAY_CPUINFO	51	#define CONFIG_DISPLAY_CPUINFO
52	#define CONFIG_DISPLAY_BOARDINFO	52	#define CONFIG_DISPLAY_BOARDINFO
53
54	/*
55	* Enable early stage initialization at C environment
56	*/
57	#define CONFIG_BOARD_EARLY_INIT_F	53	#define CONFIG_BOARD_EARLY_INIT_F
		54	#define CONFIG_MISC_INIT_R
		55	#define CONFIG_SYS_NO_FLASH
		56	#define CONFIG_CLOCKS
58		57
59	/* flat device tree */	58	#define CONFIG_FIT
60	#define CONFIG_OF_LIBFDT	59	#define CONFIG_OF_LIBFDT
61	/* skip updating the FDT blob */	60	#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
62	#define CONFIG_FDT_BLOB_SKIP_UPDATE
63	/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
64	#define CONFIG_SYS_BOOTMAPSZ ((25610241024) - (4*1024))
65		61
66	#define CONFIG_SPL_RAM_DEVICE	62	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
67	#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
68	#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
69	#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
70		63
71	/*	64	/*
72	* Memory allocation (MALLOC)	65	* Memory configurations
73	*/	66	*/
74	/* Room required on the stack for the environment data */	67	#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
75	#define CONFIG_ENV_SIZE 1024	68	#define CONFIG_NR_DRAM_BANKS 1
76	/* Size of DRAM reserved for malloc() use */	69	#define PHYS_SDRAM_1 0x0
77	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)	70	#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
		71	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
		72	#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
78		73
79	/* SP location before relocation, must use scratch RAM */
80	#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000	74	#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
81	/* Reserving 0x100 space at back of scratch RAM for debug info */
82	#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)	75	#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
83	/* Stack pointer prior relocation, must situated at on-chip RAM */	76	#define CONFIG_SYS_INIT_SP_ADDR \
84	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \	77	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \
85	CONFIG_SYS_INIT_RAM_SIZE - \	78	GENERATED_GBL_DATA_SIZE)
86	GENERATED_GBL_DATA_SIZE)
87		79
88		80	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
89	/*	81	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
90	* Command line configuration.	82	#define CONFIG_SYS_TEXT_BASE 0x08000040
91	*/	83	#else
92	#define CONFIG_SYS_NO_FLASH	84	#define CONFIG_SYS_TEXT_BASE 0x01000040
93	#include <config_cmd_default.h>
94	/* FAT file system support */
95	#define CONFIG_CMD_FAT
96	/* bootz command support */
97	#define CONFIG_CMD_BOOTZ
98
99
100	/*
101	* Misc
102	*/
103	#define CONFIG_DOS_PARTITION 1
104
105	#ifdef CONFIG_SPL_BUILD
106	#undef CONFIG_PARTITIONS
107	#endif	85	#endif
108		86
109	/*	87	/* Booting Linux */
110	* Environment setup	88	#define CONFIG_BOOTDELAY 3
111	*/	89	#define CONFIG_BOOTFILE "zImage"
112		90	#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE)
113	/* Delay before automatically booting the default image */
114	#define CONFIG_BOOTDELAY 3
115	/* Enable auto completion of commands using TAB */
116	#define CONFIG_AUTO_COMPLETE
117	/* use "hush" command parser */
118	#define CONFIG_SYS_HUSH_PARSER
119	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
120	#define CONFIG_CMD_RUN
121
122	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET	91	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
123	#define CONFIG_BOOTCOMMAND "run ramboot"	92	#define CONFIG_BOOTCOMMAND "run ramboot"
124	#else	93	#else
125	#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"	94	#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
126	#endif	95	#endif
		96	#define CONFIG_LOADADDR 0x8000
		97	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
127		98
128	/*	99	/*
129	* arguments passed to the bootm command. The value of	100	* U-Boot general configurations
130	* CONFIG_BOOTARGS goes into the environment value "bootargs".
131	* Do note the value will overide also the chosen node in FDT blob.
132	*/	101	*/
133	#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)	102	#define CONFIG_SYS_LONGHELP
		103	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
		104	#define CONFIG_SYS_PBSIZE \
		105	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
		106	/* Print buffer size */
		107	#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
		108	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
		109	/* Boot argument buffer size */
		110	#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
		111	#define CONFIG_AUTO_COMPLETE /* Command auto complete */
		112	#define CONFIG_CMDLINE_EDITING /* Command history etc */
		113	#define CONFIG_SYS_HUSH_PARSER
134		114
135	#define CONFIG_EXTRA_ENV_SETTINGS \
136	"verify=n\0" \
137	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
138	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
139	"bootm ${loadaddr} - ${fdt_addr}\0" \
140	"bootimage=zImage\0" \
141	"fdt_addr=100\0" \
142	"fdtimage=socfpga.dtb\0" \
143	"fsloadcmd=ext2load\0" \
144	"bootm ${loadaddr} - ${fdt_addr}\0" \
145	"mmcroot=/dev/mmcblk0p2\0" \
146	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
147	" root=${mmcroot} rw rootwait;" \
148	"bootz ${loadaddr} - ${fdt_addr}\0" \
149	"mmcload=mmc rescan;" \
150	"fatload mmc 0:1 ${loadaddr} ${bootimage};" \
151	"fatload mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
152	"qspiroot=/dev/mtdblock0\0" \
153	"qspirootfstype=jffs2\0" \
154	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
155	" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
156	"bootm ${loadaddr} - ${fdt_addr}\0"
157
158	/* using environment setting for stdin, stdout, stderr */
159	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
160	/* Enable the call to overwrite_console() */
161	#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
162	/* Enable overwrite of previous console environment settings */
163	#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
164
165	/* max number of command args */
166	#define CONFIG_SYS_MAXARGS 16
167
168
169	/*	115	/*
170	* Hardware drivers	116	* Cache
171	*/	117	*/
		118	#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
		119	#define CONFIG_SYS_CACHELINE_SIZE 32
		120	#define CONFIG_SYS_L2_PL310
		121	#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
172		122
173	/*	123	/*
174	* SDRAM Memory Map	124	* Ethernet on SoC (EMAC)
175	*/	125	*/
176	/* We have 1 bank of DRAM */	126	#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
177	#define CONFIG_NR_DRAM_BANKS 1	127	#define CONFIG_DESIGNWARE_ETH
178	/* SDRAM Bank #1 */	128	#define CONFIG_NET_MULTI
179	#define CONFIG_SYS_SDRAM_BASE 0x00000000	129	#define CONFIG_DW_ALTDESCRIPTOR
180	/* SDRAM memory size */	130	#define CONFIG_MII
181	#define PHYS_SDRAM_1_SIZE 0x40000000	131	#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
		132	#define CONFIG_PHYLIB
		133	#define CONFIG_PHY_GIGE
182		134
183	#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE	135	#define CONFIG_EMAC_BASE SOCFPGA_EMAC0_ADDRESS
184	#define CONFIG_SYS_MEMTEST_START 0x00000000	136	#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
185	#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE	137	#define CONFIG_EPHY0_PHY_ADDR 0
186		138
187	/*	139	/* PHY */
188	* NS16550 Configuration	140	#define CONFIG_EPHY1_PHY_ADDR 4
189	*/	141	#define CONFIG_PHY_MICREL
190	#define UART0_BASE SOCFPGA_UART0_ADDRESS	142	#define CONFIG_PHY_MICREL_KSZ9021
191	#define CONFIG_SYS_NS16550	143	#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
192	#define CONFIG_SYS_NS16550_SERIAL	144	#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
193	#define CONFIG_SYS_NS16550_REG_SIZE -4	145	#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
194	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK	146	#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
195	#define CONFIG_CONS_INDEX 1	147
196	#define CONFIG_SYS_NS16550_COM1 UART0_BASE
197	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
198	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
199	#define V_NS16550_CLK 1000000
200	#else
201	#define V_NS16550_CLK 100000000
202	#endif	148	#endif
203	#define CONFIG_BAUDRATE 115200
204		149
205	/*	150	/*
206	* FLASH	151	* FPGA Driver
207	*/	152	*/
208	#define CONFIG_SYS_NO_FLASH	153	#ifdef CONFIG_CMD_FPGA
		154	#define CONFIG_FPGA
		155	#define CONFIG_FPGA_ALTERA
		156	#define CONFIG_FPGA_SOCFPGA
		157	#define CONFIG_FPGA_COUNT 1
		158	#endif
209		159
210	/*	160	/*
211	* L4 OSC1 Timer 0	161	* L4 OSC1 Timer 0
212	*/	162	*/
213	/* This timer use eosc1 where the clock frequency is fixed	163	/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
214	* throughout any condition */
215	#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS	164	#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
216	/* Timer info */	165	#define CONFIG_SYS_TIMER_COUNTS_DOWN
		166	#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
217	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET	167	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
218	#define CONFIG_SYS_TIMER_RATE 2400000	168	#define CONFIG_SYS_TIMER_RATE 2400000
219	#else	169	#else
220	#define CONFIG_SYS_TIMER_RATE 25000000	170	#define CONFIG_SYS_TIMER_RATE 25000000
221	#endif	171	#endif
222	#define CONFIG_SYS_TIMER_COUNTS_DOWN
223	#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
224		172
225	#define CONFIG_ENV_IS_NOWHERE
226
227	/*	173	/*
228	* network support
229	*/
230	#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
231	#define CONFIG_DESIGNWARE_ETH 1
232	#endif
233
234	#ifdef CONFIG_DESIGNWARE_ETH
235	#define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS
236	#define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS
237	/* console support for network */
238	#define CONFIG_CMD_DHCP
239	#define CONFIG_CMD_MII
240	#define CONFIG_CMD_NET
241	#define CONFIG_CMD_PING
242	/* designware */
243	#define CONFIG_NET_MULTI
244	#define CONFIG_DW_ALTDESCRIPTOR
245	#define CONFIG_MII
246	#define CONFIG_PHY_GIGE
247	#define CONFIG_DW_AUTONEG
248	#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
249	#define CONFIG_PHYLIB
250	#define CONFIG_PHY_MICREL
251	#define CONFIG_PHY_MICREL_KSZ9021
252	/* EMAC controller and PHY used */
253	#define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE
254	#define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR
255	#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
256	#endif /* CONFIG_DESIGNWARE_ETH */
257
258	/*
259	* L4 Watchdog	174	* L4 Watchdog
260	*/	175	*/
261	#define CONFIG_HW_WATCHDOG	176	#ifdef CONFIG_HW_WATCHDOG
262	#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000
263	#define CONFIG_DESIGNWARE_WATCHDOG	177	#define CONFIG_DESIGNWARE_WATCHDOG
264	#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS	178	#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
265	/* Clocks source frequency to watchdog timer */
266	#define CONFIG_DW_WDT_CLOCK_KHZ 25000	179	#define CONFIG_DW_WDT_CLOCK_KHZ 25000
		180	#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000
		181	#endif
267		182
268	/*	183	/*
269	* MMC support	184	* MMC Driver
270	*/	185	*/
		186	#ifdef CONFIG_CMD_MMC
271	#define CONFIG_MMC	187	#define CONFIG_MMC
272	#ifdef CONFIG_MMC
273	#define CONFIG_BOUNCE_BUFFER	188	#define CONFIG_BOUNCE_BUFFER
274	#define CONFIG_CMD_MMC
275	#define CONFIG_GENERIC_MMC	189	#define CONFIG_GENERIC_MMC
276	#define CONFIG_DWMMC	190	#define CONFIG_DWMMC
277	#define CONFIG_SOCFPGA_DWMMC	191	#define CONFIG_SOCFPGA_DWMMC
278	#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024	192	#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024