Commit 4c0f3e7f7b7fc29d0bdbef20e849e3360c432891
Committed by
Marek Vasut
1 parent
45fa6f1dd5
Exists in
smarc_8mq_lf_v2020.04
and in
18 other branches
ARM: socfpga: boot0 hook: remove macro from boot0 header file
Commit ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole header file") miss out cleaning macro in this header file, and this has broken implementation of a boot header capability in socfpga SPL. Remove the macro in this file, and recovering it back to proper functioning. Fixes: ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole header file") Signed-off-by: Chee, Tien Fong <tien.fong.chee@intel.com>
Showing 1 changed file with 10 additions and 14 deletions Inline Diff
arch/arm/mach-socfpga/include/mach/boot0.h
1 | /* | 1 | /* |
2 | * Specialty padding for the Altera SoCFPGA preloader image | 2 | * Specialty padding for the Altera SoCFPGA preloader image |
3 | * | 3 | * |
4 | * SPDX-License-Identifier: GPL-2.0+ | 4 | * SPDX-License-Identifier: GPL-2.0+ |
5 | */ | 5 | */ |
6 | 6 | ||
7 | #ifndef __BOOT0_H | 7 | #ifndef __BOOT0_H |
8 | #define __BOOT0_H | 8 | #define __BOOT0_H |
9 | 9 | ||
10 | #ifdef CONFIG_SPL_BUILD | 10 | #ifdef CONFIG_SPL_BUILD |
11 | #define ARM_SOC_BOOT0_HOOK \ | 11 | .balignl 64,0xf33db33f; |
12 | .balignl 64,0xf33db33f; \ | 12 | |
13 | \ | 13 | .word 0x1337c0d3; /* SoCFPGA preloader validation word */ |
14 | .word 0x1337c0d3; /* SoCFPGA preloader validation word */ \ | 14 | .word 0xc01df00d; /* Version, flags, length */ |
15 | .word 0xc01df00d; /* Version, flags, length */ \ | 15 | .word 0xcafec0d3; /* Checksum, zero-pad */ |
16 | .word 0xcafec0d3; /* Checksum, zero-pad */ \ | ||
17 | nop; \ | ||
18 | \ | ||
19 | b reset; /* SoCFPGA jumps here */ \ | ||
20 | nop; \ | ||
21 | nop; \ | ||
22 | nop; | 16 | nop; |
23 | #else | ||
24 | #define ARM_SOC_BOOT0_HOOK | ||
25 | #endif | ||
26 | 17 | ||
18 | b reset; /* SoCFPGA jumps here */ | ||
19 | nop; | ||
20 | nop; |