Eric Lee / smarc-uboot

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Commit 4c4ca6cdd5836a416fcebe0d8dea585ad4a00681

Authored by Christophe Leroy
Committed by Tom Rini
1 parent 749c9aae9d
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

board: MCR3000: use new DM watchdog 

This patch switches MCR3000 board to the new DM watchdog.

The change in u-boot.lds is because MCR3000.o grows a bit
with this patch and doesn't fit anymore below env_offset on
some versions of GCC.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>

Showing 4 changed files with 22 additions and 1 deletions Inline Diff

arch/powerpc/dts/mcr3000.dts
Diff comments   View file @ 4c4ca6c
1 /* 1 /*
2 * MCR3000 Device Tree Source 2 * MCR3000 Device Tree Source
3 * 3 *
4 * Copyright 2017 CS Systemes d'Information 4 * Copyright 2017 CS Systemes d'Information
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 / { 11 / {
12 WDT: watchdog@0 {
13 compatible = "fsl,pq1-wdt";
14 };
12 }; 15 };
13 16
board/cssi/MCR3000/MCR3000.c
Diff comments   View file @ 4c4ca6c
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright (C) 2010-2017 CS Systemes d'Information 3 * Copyright (C) 2010-2017 CS Systemes d'Information
4 * Florent Trinh Thai <florent.trinh-thai@c-s.fr> 4 * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
5 * Christophe Leroy <christophe.leroy@c-s.fr> 5 * Christophe Leroy <christophe.leroy@c-s.fr>
6 * 6 *
7 * Board specific routines for the MCR3000 board 7 * Board specific routines for the MCR3000 board
8 */ 8 */
9 9
10 #include <common.h> 10 #include <common.h>
11 #include <hwconfig.h> 11 #include <hwconfig.h>
12 #include <mpc8xx.h> 12 #include <mpc8xx.h>
13 #include <fdt_support.h> 13 #include <fdt_support.h>
14 #include <asm/io.h> 14 #include <asm/io.h>
15 #include <dm/uclass.h>
16 #include <wdt.h>
15 17
16 DECLARE_GLOBAL_DATA_PTR; 18 DECLARE_GLOBAL_DATA_PTR;
17 19
18 #define SDRAM_MAX_SIZE (32 * 1024 * 1024) 20 #define SDRAM_MAX_SIZE (32 * 1024 * 1024)
19 21
20 static const uint cs1_dram_table_66[] = { 22 static const uint cs1_dram_table_66[] = {
21 /* DRAM - single read. (offset 0 in upm RAM) */ 23 /* DRAM - single read. (offset 0 in upm RAM) */
22 0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400, 24 0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
23 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 25 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
24 26
25 /* DRAM - burst read. (offset 8 in upm RAM) */ 27 /* DRAM - burst read. (offset 8 in upm RAM) */
26 0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00, 28 0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
27 0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05, 29 0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
28 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 30 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
29 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 31 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
30 32
31 /* DRAM - single write. (offset 18 in upm RAM) */ 33 /* DRAM - single write. (offset 18 in upm RAM) */
32 0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804, 34 0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
33 0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 35 0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
34 36
35 /* DRAM - burst write. (offset 20 in upm RAM) */ 37 /* DRAM - burst write. (offset 20 in upm RAM) */
36 0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00, 38 0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
37 0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404, 39 0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404,
38 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 40 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
39 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 41 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
40 42
41 /* refresh (offset 30 in upm RAM) */ 43 /* refresh (offset 30 in upm RAM) */
42 0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04, 44 0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
43 0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF, 45 0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
44 46
45 /* init */ 47 /* init */
46 0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF, 48 0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
47 49
48 /* exception. (offset 3c in upm RAM) */ 50 /* exception. (offset 3c in upm RAM) */
49 0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 51 0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
50 }; 52 };
51 53
52 int ft_board_setup(void *blob, bd_t *bd) 54 int ft_board_setup(void *blob, bd_t *bd)
53 { 55 {
54 const char *sync = "receive"; 56 const char *sync = "receive";
55 57
56 ft_cpu_setup(blob, bd); 58 ft_cpu_setup(blob, bd);
57 59
58 /* BRG */ 60 /* BRG */
59 do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency", 61 do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
60 bd->bi_busfreq, 1); 62 bd->bi_busfreq, 1);
61 63
62 /* MAC addr */ 64 /* MAC addr */
63 fdt_fixup_ethernet(blob); 65 fdt_fixup_ethernet(blob);
64 66
65 /* Bus Frequency for CPM */ 67 /* Bus Frequency for CPM */
66 do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1); 68 do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
67 69
68 /* E1 interface - Set data rate */ 70 /* E1 interface - Set data rate */
69 do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1); 71 do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
70 72
71 /* E1 interface - Set channel phase to 0 */ 73 /* E1 interface - Set channel phase to 0 */
72 do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1); 74 do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
73 75
74 /* E1 interface - rising edge sync pulse transmit */ 76 /* E1 interface - rising edge sync pulse transmit */
75 do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse", 77 do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
76 sync, strlen(sync), 1); 78 sync, strlen(sync), 1);
77 79
78 return 0; 80 return 0;
79 } 81 }
80 82
81 int checkboard(void) 83 int checkboard(void)
82 { 84 {
83 serial_puts("BOARD: MCR3000 CSSI\n"); 85 serial_puts("BOARD: MCR3000 CSSI\n");
84 86
85 return 0; 87 return 0;
86 } 88 }
87 89
88 int dram_init(void) 90 int dram_init(void)
89 { 91 {
90 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; 92 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
91 memctl8xx_t __iomem *memctl = &immap->im_memctl; 93 memctl8xx_t __iomem *memctl = &immap->im_memctl;
92 94
93 printf("UPMA init for SDRAM (CAS latency 2), "); 95 printf("UPMA init for SDRAM (CAS latency 2), ");
94 printf("init address 0x%08x, size ", (int)dram_init); 96 printf("init address 0x%08x, size ", (int)dram_init);
95 /* Configure UPMA for cs1 */ 97 /* Configure UPMA for cs1 */
96 upmconfig(UPMA, (uint *)cs1_dram_table_66, 98 upmconfig(UPMA, (uint *)cs1_dram_table_66,
97 sizeof(cs1_dram_table_66) / sizeof(uint)); 99 sizeof(cs1_dram_table_66) / sizeof(uint));
98 udelay(10); 100 udelay(10);
99 out_be16(&memctl->memc_mptpr, 0x0200); 101 out_be16(&memctl->memc_mptpr, 0x0200);
100 out_be32(&memctl->memc_mamr, 0x14904000); 102 out_be32(&memctl->memc_mamr, 0x14904000);
101 udelay(10); 103 udelay(10);
102 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM); 104 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
103 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM); 105 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
104 udelay(10); 106 udelay(10);
105 out_be32(&memctl->memc_mcr, 0x80002830); 107 out_be32(&memctl->memc_mcr, 0x80002830);
106 out_be32(&memctl->memc_mar, 0x00000088); 108 out_be32(&memctl->memc_mar, 0x00000088);
107 out_be32(&memctl->memc_mcr, 0x80002038); 109 out_be32(&memctl->memc_mcr, 0x80002038);
108 udelay(200); 110 udelay(200);
109 111
110 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 112 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
111 SDRAM_MAX_SIZE); 113 SDRAM_MAX_SIZE);
112 114
113 return 0; 115 return 0;
114 } 116 }
115 117
116 int misc_init_r(void) 118 int misc_init_r(void)
117 { 119 {
118 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; 120 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
119 iop8xx_t __iomem *iop = &immr->im_ioport; 121 iop8xx_t __iomem *iop = &immr->im_ioport;
120 122
121 /* Set port C13 as GPIO (BTN_ACQ_AL) */ 123 /* Set port C13 as GPIO (BTN_ACQ_AL) */
122 clrbits_be16(&iop->iop_pcpar, 0x4); 124 clrbits_be16(&iop->iop_pcpar, 0x4);
123 clrbits_be16(&iop->iop_pcdir, 0x4); 125 clrbits_be16(&iop->iop_pcdir, 0x4);
124 126
125 /* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */ 127 /* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
126 if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0) 128 if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
127 env_set("bootdelay", "60"); 129 env_set("bootdelay", "60");
128 130
129 return 0; 131 return 0;
130 } 132 }
131 133
132 int board_early_init_f(void) 134 int board_early_init_f(void)
133 { 135 {
134 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; 136 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
135 137
136 /* 138 /*
137 * Erase FPGA(s) for reboot 139 * Erase FPGA(s) for reboot
138 */ 140 */
139 clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */ 141 clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */
140 setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */ 142 setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */
141 udelay(1); /* Wait more than 300ns */ 143 udelay(1); /* Wait more than 300ns */
142 setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */ 144 setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
145
146 return 0;
147 }
148
149 int board_early_init_r(void)
150 {
151 struct udevice *watchdog_dev = NULL;
152
153 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
154 puts("Cannot find watchdog!\n");
155 } else {
156 puts("Enabling watchdog.\n");
157 wdt_start(watchdog_dev, 0xffff, 0);
158 }
143 159
144 return 0; 160 return 0;
145 } 161 }
146 162
board/cssi/MCR3000/u-boot.lds
Diff comments   View file @ 4c4ca6c
1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * Copyright (C) 2010-2017 CS Systemes d'Information 3 * Copyright (C) 2010-2017 CS Systemes d'Information
4 * Christophe Leroy <christophe.leroy@c-s.fr> 4 * Christophe Leroy <christophe.leroy@c-s.fr>
5 * 5 *
6 * (C) Copyright 2001-2003 6 * (C) Copyright 2001-2003
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * 8 *
9 * Modified by Yuli Barcohen <yuli@arabellasw.com> 9 * Modified by Yuli Barcohen <yuli@arabellasw.com>
10 */ 10 */
11 11
12 OUTPUT_ARCH(powerpc) 12 OUTPUT_ARCH(powerpc)
13 SECTIONS 13 SECTIONS
14 { 14 {
15 /* Read-only sections, merged into text segment: */ 15 /* Read-only sections, merged into text segment: */
16 . = + SIZEOF_HEADERS; 16 . = + SIZEOF_HEADERS;
17 .text : 17 .text :
18 { 18 {
19 arch/powerpc/cpu/mpc8xx/start.o (.text) 19 arch/powerpc/cpu/mpc8xx/start.o (.text)
20 arch/powerpc/cpu/mpc8xx/traps.o (.text*) 20 arch/powerpc/cpu/mpc8xx/traps.o (.text*)
21 arch/powerpc/lib/built-in.o (.text*) 21 arch/powerpc/lib/built-in.o (.text*)
22 board/cssi/MCR3000/built-in.o (.text*)
23 drivers/net/built-in.o (.text*) 22 drivers/net/built-in.o (.text*)
24 23
25 . = DEFINED(env_offset) ? env_offset : .; 24 . = DEFINED(env_offset) ? env_offset : .;
26 env/embedded.o (.text.environment) 25 env/embedded.o (.text.environment)
27 26
28 *(.text) 27 *(.text)
29 } 28 }
30 _etext = .; 29 _etext = .;
31 PROVIDE (etext = .); 30 PROVIDE (etext = .);
32 .rodata : 31 .rodata :
33 { 32 {
34 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) 33 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
35 } 34 }
36 35
37 /* Read-write section, merged into data segment: */ 36 /* Read-write section, merged into data segment: */
38 . = (. + 0x0FFF) & 0xFFFFF000; 37 . = (. + 0x0FFF) & 0xFFFFF000;
39 _erotext = .; 38 _erotext = .;
40 PROVIDE (erotext = .); 39 PROVIDE (erotext = .);
41 .reloc : 40 .reloc :
42 { 41 {
43 _GOT2_TABLE_ = .; 42 _GOT2_TABLE_ = .;
44 KEEP(*(.got2)) 43 KEEP(*(.got2))
45 KEEP(*(.got)) 44 KEEP(*(.got))
46 _FIXUP_TABLE_ = .; 45 _FIXUP_TABLE_ = .;
47 KEEP(*(.fixup)) 46 KEEP(*(.fixup))
48 } 47 }
49 __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; 48 __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
50 __fixup_entries = (. - _FIXUP_TABLE_) >> 2; 49 __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
51 50
52 .data : 51 .data :
53 { 52 {
54 *(.data*) 53 *(.data*)
55 *(.sdata*) 54 *(.sdata*)
56 } 55 }
57 _edata = .; 56 _edata = .;
58 PROVIDE (edata = .); 57 PROVIDE (edata = .);
59 58
60 . = .; 59 . = .;
61 60
62 . = ALIGN(4); 61 . = ALIGN(4);
63 .u_boot_list : { 62 .u_boot_list : {
64 KEEP(*(SORT(.u_boot_list*))); 63 KEEP(*(SORT(.u_boot_list*)));
65 } 64 }
66 65
67 . = .; 66 . = .;
68 __start___ex_table = .; 67 __start___ex_table = .;
69 __ex_table : { *(__ex_table) } 68 __ex_table : { *(__ex_table) }
70 __stop___ex_table = .; 69 __stop___ex_table = .;
71 70
72 /* 71 /*
73 * _end - This is end of u-boot.bin image. 72 * _end - This is end of u-boot.bin image.
74 * dtb will be appended here to make u-boot-dtb.bin 73 * dtb will be appended here to make u-boot-dtb.bin
75 */ 74 */
76 _end = .; 75 _end = .;
77 76
78 . = ALIGN(4096); 77 . = ALIGN(4096);
79 __init_begin = .; 78 __init_begin = .;
80 .text.init : { *(.text.init) } 79 .text.init : { *(.text.init) }
81 .data.init : { *(.data.init) } 80 .data.init : { *(.data.init) }
82 . = ALIGN(4096); 81 . = ALIGN(4096);
83 __init_end = .; 82 __init_end = .;
84 83
85 __bss_start = .; 84 __bss_start = .;
86 .bss (NOLOAD) : 85 .bss (NOLOAD) :
87 { 86 {
88 *(.bss*) 87 *(.bss*)
89 *(.sbss*) 88 *(.sbss*)
90 *(COMMON) 89 *(COMMON)
91 . = ALIGN(4); 90 . = ALIGN(4);
92 } 91 }
93 __bss_end = . ; 92 __bss_end = . ;
94 PROVIDE (end = .); 93 PROVIDE (end = .);
95 } 94 }
96 ENTRY(_start) 95 ENTRY(_start)
97 96
configs/MCR3000_defconfig
Diff comments   View file @ 4c4ca6c
1 CONFIG_PPC=y 1 CONFIG_PPC=y
2 CONFIG_SYS_TEXT_BASE=0x4000000 2 CONFIG_SYS_TEXT_BASE=0x4000000
3 CONFIG_MPC8xx=y 3 CONFIG_MPC8xx=y
4 CONFIG_TARGET_MCR3000=y 4 CONFIG_TARGET_MCR3000=y
5 CONFIG_8xx_GCLK_FREQ=132000000 5 CONFIG_8xx_GCLK_FREQ=132000000
6 CONFIG_CMD_IMMAP=y 6 CONFIG_CMD_IMMAP=y
7 CONFIG_SYS_SIUMCR=0x00600400 7 CONFIG_SYS_SIUMCR=0x00600400
8 CONFIG_SYS_SYPCR=0xFFFFFF8F 8 CONFIG_SYS_SYPCR=0xFFFFFF8F
9 CONFIG_SYS_TBSCR=0x00C3 9 CONFIG_SYS_TBSCR=0x00C3
10 CONFIG_SYS_PISCR=0x0000 10 CONFIG_SYS_PISCR=0x0000
11 CONFIG_SYS_PLPRCR_BOOL=y 11 CONFIG_SYS_PLPRCR_BOOL=y
12 CONFIG_SYS_PLPRCR=0x00460004 12 CONFIG_SYS_PLPRCR=0x00460004
13 CONFIG_SYS_SCCR=0x00C20000 13 CONFIG_SYS_SCCR=0x00C20000
14 CONFIG_SYS_SCCR_MASK=0x60000000 14 CONFIG_SYS_SCCR_MASK=0x60000000
15 CONFIG_SYS_DER=0x2002000F 15 CONFIG_SYS_DER=0x2002000F
16 CONFIG_SYS_BR0_PRELIM=0x04000801 16 CONFIG_SYS_BR0_PRELIM=0x04000801
17 CONFIG_SYS_OR0_PRELIM=0xFFC00926 17 CONFIG_SYS_OR0_PRELIM=0xFFC00926
18 CONFIG_SYS_BR1_PRELIM_BOOL=y 18 CONFIG_SYS_BR1_PRELIM_BOOL=y
19 CONFIG_SYS_BR1_PRELIM=0x00000081 19 CONFIG_SYS_BR1_PRELIM=0x00000081
20 CONFIG_SYS_OR1_PRELIM=0xFE000E00 20 CONFIG_SYS_OR1_PRELIM=0xFE000E00
21 CONFIG_SYS_BR2_PRELIM_BOOL=y 21 CONFIG_SYS_BR2_PRELIM_BOOL=y
22 CONFIG_SYS_BR2_PRELIM=0x08000801 22 CONFIG_SYS_BR2_PRELIM=0x08000801
23 CONFIG_SYS_OR2_PRELIM=0xFFFF8F2A 23 CONFIG_SYS_OR2_PRELIM=0xFFFF8F2A
24 CONFIG_SYS_BR3_PRELIM_BOOL=y 24 CONFIG_SYS_BR3_PRELIM_BOOL=y
25 CONFIG_SYS_BR3_PRELIM=0x0C000401 25 CONFIG_SYS_BR3_PRELIM=0x0C000401
26 CONFIG_SYS_OR3_PRELIM=0xFFFF8142 26 CONFIG_SYS_OR3_PRELIM=0xFFFF8142
27 CONFIG_SYS_BR4_PRELIM_BOOL=y 27 CONFIG_SYS_BR4_PRELIM_BOOL=y
28 CONFIG_SYS_BR4_PRELIM=0x10000801 28 CONFIG_SYS_BR4_PRELIM=0x10000801
29 CONFIG_SYS_OR4_PRELIM=0xFFFF8D08 29 CONFIG_SYS_OR4_PRELIM=0xFFFF8D08
30 CONFIG_SYS_BR5_PRELIM_BOOL=y 30 CONFIG_SYS_BR5_PRELIM_BOOL=y
31 CONFIG_SYS_BR5_PRELIM=0x14000801 31 CONFIG_SYS_BR5_PRELIM=0x14000801
32 CONFIG_SYS_OR5_PRELIM=0xFFFF8916 32 CONFIG_SYS_OR5_PRELIM=0xFFFF8916
33 CONFIG_SYS_BR6_PRELIM_BOOL=y 33 CONFIG_SYS_BR6_PRELIM_BOOL=y
34 CONFIG_SYS_BR6_PRELIM=0x18000801 34 CONFIG_SYS_BR6_PRELIM=0x18000801
35 CONFIG_SYS_OR6_PRELIM=0xFFFF0908 35 CONFIG_SYS_OR6_PRELIM=0xFFFF0908
36 CONFIG_SYS_BR7_PRELIM_BOOL=y 36 CONFIG_SYS_BR7_PRELIM_BOOL=y
37 CONFIG_SYS_BR7_PRELIM=0x1C000001 37 CONFIG_SYS_BR7_PRELIM=0x1C000001
38 CONFIG_SYS_OR7_PRELIM=0xFFFF810A 38 CONFIG_SYS_OR7_PRELIM=0xFFFF810A
39 CONFIG_SYS_IMMR=0xFF000000 39 CONFIG_SYS_IMMR=0xFF000000
40 CONFIG_OF_BOARD_SETUP=y 40 CONFIG_OF_BOARD_SETUP=y
41 CONFIG_BOOTDELAY=5 41 CONFIG_BOOTDELAY=5
42 CONFIG_USE_BOOTCOMMAND=y 42 CONFIG_USE_BOOTCOMMAND=y
43 CONFIG_BOOTCOMMAND="run flashboot" 43 CONFIG_BOOTCOMMAND="run flashboot"
44 CONFIG_MISC_INIT_R=y 44 CONFIG_MISC_INIT_R=y
45 CONFIG_BOARD_EARLY_INIT_R=y
45 CONFIG_HUSH_PARSER=y 46 CONFIG_HUSH_PARSER=y
46 # CONFIG_AUTO_COMPLETE is not set 47 # CONFIG_AUTO_COMPLETE is not set
47 CONFIG_SYS_PROMPT="S3K> " 48 CONFIG_SYS_PROMPT="S3K> "
48 CONFIG_AUTOBOOT_KEYED=y 49 CONFIG_AUTOBOOT_KEYED=y
49 CONFIG_AUTOBOOT_PROMPT="\nEnter password - autoboot in %d sec...\n" 50 CONFIG_AUTOBOOT_PROMPT="\nEnter password - autoboot in %d sec...\n"
50 CONFIG_AUTOBOOT_DELAY_STR="root" 51 CONFIG_AUTOBOOT_DELAY_STR="root"
51 # CONFIG_CMD_BDI is not set 52 # CONFIG_CMD_BDI is not set
52 # CONFIG_CMD_CONSOLE is not set 53 # CONFIG_CMD_CONSOLE is not set
53 # CONFIG_CMD_IMI is not set 54 # CONFIG_CMD_IMI is not set
54 CONFIG_CMD_ASKENV=y 55 CONFIG_CMD_ASKENV=y
55 # CONFIG_CMD_LOADB is not set 56 # CONFIG_CMD_LOADB is not set
56 # CONFIG_CMD_LOADS is not set 57 # CONFIG_CMD_LOADS is not set
57 CONFIG_CMD_NAND=y 58 CONFIG_CMD_NAND=y
58 # CONFIG_CMD_ECHO is not set 59 # CONFIG_CMD_ECHO is not set
59 # CONFIG_CMD_ITEST is not set 60 # CONFIG_CMD_ITEST is not set
60 # CONFIG_CMD_SOURCE is not set 61 # CONFIG_CMD_SOURCE is not set
61 # CONFIG_CMD_SETEXPR is not set 62 # CONFIG_CMD_SETEXPR is not set
62 CONFIG_CMD_DHCP=y 63 CONFIG_CMD_DHCP=y
63 CONFIG_CMD_MII=y 64 CONFIG_CMD_MII=y
64 CONFIG_CMD_PING=y 65 CONFIG_CMD_PING=y
65 # CONFIG_CMD_MISC is not set 66 # CONFIG_CMD_MISC is not set
66 CONFIG_ENV_IS_IN_FLASH=y 67 CONFIG_ENV_IS_IN_FLASH=y
67 # CONFIG_MMC is not set 68 # CONFIG_MMC is not set
68 CONFIG_MTD_NOR_FLASH=y 69 CONFIG_MTD_NOR_FLASH=y
69 CONFIG_FLASH_CFI_DRIVER=y 70 CONFIG_FLASH_CFI_DRIVER=y
70 CONFIG_SYS_FLASH_CFI=y 71 CONFIG_SYS_FLASH_CFI=y
71 CONFIG_MPC8XX_FEC=y 72 CONFIG_MPC8XX_FEC=y
72 # CONFIG_PCI is not set 73 # CONFIG_PCI is not set
73 CONFIG_SHA256=y 74 CONFIG_SHA256=y
74 CONFIG_LZMA=y 75 CONFIG_LZMA=y
75 CONFIG_OF_LIBFDT=y 76 CONFIG_OF_LIBFDT=y
76 CONFIG_DM=y 77 CONFIG_DM=y
77 CONFIG_OF_CONTROL=y 78 CONFIG_OF_CONTROL=y
78 CONFIG_DEFAULT_DEVICE_TREE="mcr3000" 79 CONFIG_DEFAULT_DEVICE_TREE="mcr3000"
80 CONFIG_WDT=y
81 CONFIG_WDT_MPC8xx=y
79 82