Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 4c9d4a75f12f9ae7a1164f62cee532ef7a48e5f5

Authored by Ashish Kumar
Committed by York Sun
1 parent 5b595df338
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

ls1088a: Move CONFIG_FSL_QSPI to defconfig 

Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 9 changed files with 7 additions and 2 deletions Inline Diff

configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
Diff comments   View file @ 4c9d4a7
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_TARGET_LS1088AQDS=y 2 CONFIG_TARGET_LS1088AQDS=y
3 CONFIG_SYS_TEXT_BASE=0x20100000 3 CONFIG_SYS_TEXT_BASE=0x20100000
4 CONFIG_SECURE_BOOT=y 4 CONFIG_SECURE_BOOT=y
5 CONFIG_FSL_LS_PPA=y 5 CONFIG_FSL_LS_PPA=y
6 CONFIG_QSPI_AHB_INIT=y 6 CONFIG_QSPI_AHB_INIT=y
7 CONFIG_DISTRO_DEFAULTS=y 7 CONFIG_DISTRO_DEFAULTS=y
8 CONFIG_NR_DRAM_BANKS=2 8 CONFIG_NR_DRAM_BANKS=2
9 # CONFIG_SYS_MALLOC_F is not set 9 # CONFIG_SYS_MALLOC_F is not set
10 CONFIG_FIT_VERBOSE=y 10 CONFIG_FIT_VERBOSE=y
11 CONFIG_OF_BOARD_SETUP=y 11 CONFIG_OF_BOARD_SETUP=y
12 CONFIG_OF_STDOUT_VIA_ALIAS=y 12 CONFIG_OF_STDOUT_VIA_ALIAS=y
13 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" 13 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
14 CONFIG_USE_BOOTARGS=y 14 CONFIG_USE_BOOTARGS=y
15 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" 15 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
16 # CONFIG_USE_BOOTCOMMAND is not set 16 # CONFIG_USE_BOOTCOMMAND is not set
17 # CONFIG_DISPLAY_BOARDINFO is not set 17 # CONFIG_DISPLAY_BOARDINFO is not set
18 CONFIG_DISPLAY_BOARDINFO_LATE=y 18 CONFIG_DISPLAY_BOARDINFO_LATE=y
19 CONFIG_CMD_GREPENV=y 19 CONFIG_CMD_GREPENV=y
20 CONFIG_CMD_MEMTEST=y 20 CONFIG_CMD_MEMTEST=y
21 CONFIG_CMD_I2C=y 21 CONFIG_CMD_I2C=y
22 CONFIG_CMD_MMC=y 22 CONFIG_CMD_MMC=y
23 CONFIG_CMD_SF=y 23 CONFIG_CMD_SF=y
24 CONFIG_CMD_USB=y 24 CONFIG_CMD_USB=y
25 # CONFIG_CMD_SETEXPR is not set 25 # CONFIG_CMD_SETEXPR is not set
26 CONFIG_MP=y 26 CONFIG_MP=y
27 CONFIG_OF_CONTROL=y 27 CONFIG_OF_CONTROL=y
28 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" 28 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
29 CONFIG_NET_RANDOM_ETHADDR=y 29 CONFIG_NET_RANDOM_ETHADDR=y
30 CONFIG_DM=y 30 CONFIG_DM=y
31 CONFIG_SCSI_AHCI=y 31 CONFIG_SCSI_AHCI=y
32 CONFIG_DM_MMC=y 32 CONFIG_DM_MMC=y
33 CONFIG_FSL_ESDHC=y 33 CONFIG_FSL_ESDHC=y
34 CONFIG_DM_SPI_FLASH=y 34 CONFIG_DM_SPI_FLASH=y
35 CONFIG_SPI_FLASH=y 35 CONFIG_SPI_FLASH=y
36 CONFIG_SPI_FLASH_SPANSION=y 36 CONFIG_SPI_FLASH_SPANSION=y
37 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set 37 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
38 CONFIG_E1000=y 38 CONFIG_E1000=y
39 CONFIG_MII=y 39 CONFIG_MII=y
40 CONFIG_PCI=y 40 CONFIG_PCI=y
41 CONFIG_DM_PCI=y 41 CONFIG_DM_PCI=y
42 CONFIG_DM_PCI_COMPAT=y 42 CONFIG_DM_PCI_COMPAT=y
43 CONFIG_PCIE_LAYERSCAPE=y 43 CONFIG_PCIE_LAYERSCAPE=y
44 CONFIG_SYS_NS16550=y 44 CONFIG_SYS_NS16550=y
45 CONFIG_SPI=y 45 CONFIG_SPI=y
46 CONFIG_DM_SPI=y 46 CONFIG_DM_SPI=y
47 CONFIG_FSL_DSPI=y 47 CONFIG_FSL_DSPI=y
48 CONFIG_FSL_QSPI=y
48 CONFIG_USB=y 49 CONFIG_USB=y
49 CONFIG_DM_USB=y 50 CONFIG_DM_USB=y
50 CONFIG_USB_XHCI_HCD=y 51 CONFIG_USB_XHCI_HCD=y
51 CONFIG_USB_XHCI_DWC3=y 52 CONFIG_USB_XHCI_DWC3=y
52 CONFIG_USB_DWC3=y 53 CONFIG_USB_DWC3=y
53 CONFIG_USB_STORAGE=y 54 CONFIG_USB_STORAGE=y
54 CONFIG_USB_GADGET=y 55 CONFIG_USB_GADGET=y
55 CONFIG_RSA=y 56 CONFIG_RSA=y
56 CONFIG_RSA_SOFTWARE_EXP=y 57 CONFIG_RSA_SOFTWARE_EXP=y
57 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 58 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
58 59
configs/ls1088aqds_qspi_defconfig
Diff comments   View file @ 4c9d4a7
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_TARGET_LS1088AQDS=y 2 CONFIG_TARGET_LS1088AQDS=y
3 CONFIG_SYS_TEXT_BASE=0x20100000 3 CONFIG_SYS_TEXT_BASE=0x20100000
4 CONFIG_FSL_LS_PPA=y 4 CONFIG_FSL_LS_PPA=y
5 CONFIG_QSPI_AHB_INIT=y 5 CONFIG_QSPI_AHB_INIT=y
6 CONFIG_DISTRO_DEFAULTS=y 6 CONFIG_DISTRO_DEFAULTS=y
7 CONFIG_NR_DRAM_BANKS=2 7 CONFIG_NR_DRAM_BANKS=2
8 # CONFIG_SYS_MALLOC_F is not set 8 # CONFIG_SYS_MALLOC_F is not set
9 CONFIG_FIT_VERBOSE=y 9 CONFIG_FIT_VERBOSE=y
10 CONFIG_OF_BOARD_SETUP=y 10 CONFIG_OF_BOARD_SETUP=y
11 CONFIG_OF_STDOUT_VIA_ALIAS=y 11 CONFIG_OF_STDOUT_VIA_ALIAS=y
12 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" 12 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
13 CONFIG_USE_BOOTARGS=y 13 CONFIG_USE_BOOTARGS=y
14 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" 14 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
15 # CONFIG_USE_BOOTCOMMAND is not set 15 # CONFIG_USE_BOOTCOMMAND is not set
16 # CONFIG_DISPLAY_BOARDINFO is not set 16 # CONFIG_DISPLAY_BOARDINFO is not set
17 CONFIG_DISPLAY_BOARDINFO_LATE=y 17 CONFIG_DISPLAY_BOARDINFO_LATE=y
18 CONFIG_CMD_GREPENV=y 18 CONFIG_CMD_GREPENV=y
19 CONFIG_CMD_MEMTEST=y 19 CONFIG_CMD_MEMTEST=y
20 CONFIG_CMD_I2C=y 20 CONFIG_CMD_I2C=y
21 CONFIG_CMD_MMC=y 21 CONFIG_CMD_MMC=y
22 CONFIG_CMD_SF=y 22 CONFIG_CMD_SF=y
23 CONFIG_CMD_USB=y 23 CONFIG_CMD_USB=y
24 # CONFIG_CMD_SETEXPR is not set 24 # CONFIG_CMD_SETEXPR is not set
25 CONFIG_MP=y 25 CONFIG_MP=y
26 CONFIG_OF_CONTROL=y 26 CONFIG_OF_CONTROL=y
27 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" 27 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
28 CONFIG_ENV_IS_IN_SPI_FLASH=y 28 CONFIG_ENV_IS_IN_SPI_FLASH=y
29 CONFIG_NET_RANDOM_ETHADDR=y 29 CONFIG_NET_RANDOM_ETHADDR=y
30 CONFIG_DM=y 30 CONFIG_DM=y
31 CONFIG_SCSI_AHCI=y 31 CONFIG_SCSI_AHCI=y
32 CONFIG_DM_MMC=y 32 CONFIG_DM_MMC=y
33 CONFIG_FSL_ESDHC=y 33 CONFIG_FSL_ESDHC=y
34 CONFIG_DM_SPI_FLASH=y 34 CONFIG_DM_SPI_FLASH=y
35 CONFIG_SPI_FLASH=y 35 CONFIG_SPI_FLASH=y
36 CONFIG_SPI_FLASH_SPANSION=y 36 CONFIG_SPI_FLASH_SPANSION=y
37 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set 37 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
38 CONFIG_E1000=y 38 CONFIG_E1000=y
39 CONFIG_MII=y 39 CONFIG_MII=y
40 CONFIG_PCI=y 40 CONFIG_PCI=y
41 CONFIG_DM_PCI=y 41 CONFIG_DM_PCI=y
42 CONFIG_DM_PCI_COMPAT=y 42 CONFIG_DM_PCI_COMPAT=y
43 CONFIG_PCIE_LAYERSCAPE=y 43 CONFIG_PCIE_LAYERSCAPE=y
44 CONFIG_SYS_NS16550=y 44 CONFIG_SYS_NS16550=y
45 CONFIG_SPI=y 45 CONFIG_SPI=y
46 CONFIG_DM_SPI=y 46 CONFIG_DM_SPI=y
47 CONFIG_FSL_DSPI=y 47 CONFIG_FSL_DSPI=y
48 CONFIG_FSL_QSPI=y
48 CONFIG_USB=y 49 CONFIG_USB=y
49 CONFIG_DM_USB=y 50 CONFIG_DM_USB=y
50 CONFIG_USB_XHCI_HCD=y 51 CONFIG_USB_XHCI_HCD=y
51 CONFIG_USB_XHCI_DWC3=y 52 CONFIG_USB_XHCI_DWC3=y
52 CONFIG_USB_DWC3=y 53 CONFIG_USB_DWC3=y
53 CONFIG_USB_STORAGE=y 54 CONFIG_USB_STORAGE=y
54 CONFIG_USB_GADGET=y 55 CONFIG_USB_GADGET=y
55 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 56 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
56 57
configs/ls1088aqds_sdcard_qspi_defconfig
Diff comments   View file @ 4c9d4a7
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_TARGET_LS1088AQDS=y 2 CONFIG_TARGET_LS1088AQDS=y
3 CONFIG_SYS_TEXT_BASE=0x80400000 3 CONFIG_SYS_TEXT_BASE=0x80400000
4 CONFIG_SPL_LIBCOMMON_SUPPORT=y 4 CONFIG_SPL_LIBCOMMON_SUPPORT=y
5 CONFIG_SPL_LIBGENERIC_SUPPORT=y 5 CONFIG_SPL_LIBGENERIC_SUPPORT=y
6 CONFIG_FSL_LS_PPA=y 6 CONFIG_FSL_LS_PPA=y
7 CONFIG_SPL_MMC_SUPPORT=y 7 CONFIG_SPL_MMC_SUPPORT=y
8 CONFIG_SPL_SERIAL_SUPPORT=y 8 CONFIG_SPL_SERIAL_SUPPORT=y
9 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y 9 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
10 CONFIG_SPL=y 10 CONFIG_SPL=y
11 CONFIG_DISTRO_DEFAULTS=y 11 CONFIG_DISTRO_DEFAULTS=y
12 CONFIG_NR_DRAM_BANKS=2 12 CONFIG_NR_DRAM_BANKS=2
13 # CONFIG_SYS_MALLOC_F is not set 13 # CONFIG_SYS_MALLOC_F is not set
14 CONFIG_FIT_VERBOSE=y 14 CONFIG_FIT_VERBOSE=y
15 CONFIG_OF_BOARD_SETUP=y 15 CONFIG_OF_BOARD_SETUP=y
16 CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI" 16 CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
17 CONFIG_SD_BOOT=y 17 CONFIG_SD_BOOT=y
18 CONFIG_USE_BOOTARGS=y 18 CONFIG_USE_BOOTARGS=y
19 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" 19 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
20 # CONFIG_USE_BOOTCOMMAND is not set 20 # CONFIG_USE_BOOTCOMMAND is not set
21 # CONFIG_DISPLAY_BOARDINFO is not set 21 # CONFIG_DISPLAY_BOARDINFO is not set
22 CONFIG_DISPLAY_BOARDINFO_LATE=y 22 CONFIG_DISPLAY_BOARDINFO_LATE=y
23 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y 23 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
24 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 24 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
25 CONFIG_SPL_ENV_SUPPORT=y 25 CONFIG_SPL_ENV_SUPPORT=y
26 CONFIG_SPL_I2C_SUPPORT=y 26 CONFIG_SPL_I2C_SUPPORT=y
27 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y 27 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
28 CONFIG_CMD_GREPENV=y 28 CONFIG_CMD_GREPENV=y
29 CONFIG_CMD_MEMTEST=y 29 CONFIG_CMD_MEMTEST=y
30 CONFIG_CMD_I2C=y 30 CONFIG_CMD_I2C=y
31 CONFIG_CMD_MMC=y 31 CONFIG_CMD_MMC=y
32 CONFIG_CMD_SF=y 32 CONFIG_CMD_SF=y
33 CONFIG_CMD_USB=y 33 CONFIG_CMD_USB=y
34 # CONFIG_CMD_SETEXPR is not set 34 # CONFIG_CMD_SETEXPR is not set
35 CONFIG_MP=y 35 CONFIG_MP=y
36 CONFIG_OF_CONTROL=y 36 CONFIG_OF_CONTROL=y
37 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" 37 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
38 CONFIG_ENV_IS_IN_MMC=y 38 CONFIG_ENV_IS_IN_MMC=y
39 CONFIG_NET_RANDOM_ETHADDR=y 39 CONFIG_NET_RANDOM_ETHADDR=y
40 CONFIG_DM=y 40 CONFIG_DM=y
41 CONFIG_SCSI_AHCI=y 41 CONFIG_SCSI_AHCI=y
42 CONFIG_DM_MMC=y 42 CONFIG_DM_MMC=y
43 CONFIG_FSL_ESDHC=y 43 CONFIG_FSL_ESDHC=y
44 CONFIG_DM_SPI_FLASH=y 44 CONFIG_DM_SPI_FLASH=y
45 CONFIG_SPI_FLASH=y 45 CONFIG_SPI_FLASH=y
46 CONFIG_SPI_FLASH_SPANSION=y 46 CONFIG_SPI_FLASH_SPANSION=y
47 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set 47 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
48 CONFIG_E1000=y 48 CONFIG_E1000=y
49 CONFIG_MII=y 49 CONFIG_MII=y
50 CONFIG_PCI=y 50 CONFIG_PCI=y
51 CONFIG_DM_PCI=y 51 CONFIG_DM_PCI=y
52 CONFIG_DM_PCI_COMPAT=y 52 CONFIG_DM_PCI_COMPAT=y
53 CONFIG_PCIE_LAYERSCAPE=y 53 CONFIG_PCIE_LAYERSCAPE=y
54 CONFIG_SYS_NS16550=y 54 CONFIG_SYS_NS16550=y
55 CONFIG_SPI=y 55 CONFIG_SPI=y
56 CONFIG_DM_SPI=y 56 CONFIG_DM_SPI=y
57 CONFIG_FSL_DSPI=y 57 CONFIG_FSL_DSPI=y
58 CONFIG_FSL_QSPI=y
58 CONFIG_USB=y 59 CONFIG_USB=y
59 CONFIG_DM_USB=y 60 CONFIG_DM_USB=y
60 CONFIG_USB_XHCI_HCD=y 61 CONFIG_USB_XHCI_HCD=y
61 CONFIG_USB_XHCI_DWC3=y 62 CONFIG_USB_XHCI_DWC3=y
62 CONFIG_USB_DWC3=y 63 CONFIG_USB_DWC3=y
63 CONFIG_USB_STORAGE=y 64 CONFIG_USB_STORAGE=y
64 CONFIG_USB_GADGET=y 65 CONFIG_USB_GADGET=y
65 66
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
Diff comments   View file @ 4c9d4a7
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_TARGET_LS1088ARDB=y 2 CONFIG_TARGET_LS1088ARDB=y
3 CONFIG_SYS_TEXT_BASE=0x20100000 3 CONFIG_SYS_TEXT_BASE=0x20100000
4 CONFIG_SECURE_BOOT=y 4 CONFIG_SECURE_BOOT=y
5 CONFIG_FSL_LS_PPA=y 5 CONFIG_FSL_LS_PPA=y
6 CONFIG_QSPI_AHB_INIT=y 6 CONFIG_QSPI_AHB_INIT=y
7 CONFIG_DISTRO_DEFAULTS=y 7 CONFIG_DISTRO_DEFAULTS=y
8 CONFIG_NR_DRAM_BANKS=2 8 CONFIG_NR_DRAM_BANKS=2
9 # CONFIG_SYS_MALLOC_F is not set 9 # CONFIG_SYS_MALLOC_F is not set
10 CONFIG_FIT_VERBOSE=y 10 CONFIG_FIT_VERBOSE=y
11 CONFIG_OF_BOARD_SETUP=y 11 CONFIG_OF_BOARD_SETUP=y
12 CONFIG_OF_STDOUT_VIA_ALIAS=y 12 CONFIG_OF_STDOUT_VIA_ALIAS=y
13 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" 13 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
14 CONFIG_USE_BOOTARGS=y 14 CONFIG_USE_BOOTARGS=y
15 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" 15 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
16 # CONFIG_USE_BOOTCOMMAND is not set 16 # CONFIG_USE_BOOTCOMMAND is not set
17 CONFIG_MISC_INIT_R=y 17 CONFIG_MISC_INIT_R=y
18 # CONFIG_DISPLAY_BOARDINFO is not set 18 # CONFIG_DISPLAY_BOARDINFO is not set
19 CONFIG_DISPLAY_BOARDINFO_LATE=y 19 CONFIG_DISPLAY_BOARDINFO_LATE=y
20 CONFIG_CMD_GREPENV=y 20 CONFIG_CMD_GREPENV=y
21 CONFIG_CMD_MEMTEST=y 21 CONFIG_CMD_MEMTEST=y
22 CONFIG_CMD_I2C=y 22 CONFIG_CMD_I2C=y
23 CONFIG_CMD_MMC=y 23 CONFIG_CMD_MMC=y
24 CONFIG_CMD_SF=y 24 CONFIG_CMD_SF=y
25 CONFIG_CMD_USB=y 25 CONFIG_CMD_USB=y
26 # CONFIG_CMD_SETEXPR is not set 26 # CONFIG_CMD_SETEXPR is not set
27 CONFIG_MP=y 27 CONFIG_MP=y
28 CONFIG_OF_CONTROL=y 28 CONFIG_OF_CONTROL=y
29 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" 29 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
30 CONFIG_NET_RANDOM_ETHADDR=y 30 CONFIG_NET_RANDOM_ETHADDR=y
31 CONFIG_DM=y 31 CONFIG_DM=y
32 CONFIG_SCSI_AHCI=y 32 CONFIG_SCSI_AHCI=y
33 CONFIG_DM_MMC=y 33 CONFIG_DM_MMC=y
34 CONFIG_FSL_ESDHC=y 34 CONFIG_FSL_ESDHC=y
35 CONFIG_DM_SPI_FLASH=y 35 CONFIG_DM_SPI_FLASH=y
36 CONFIG_SPI_FLASH=y 36 CONFIG_SPI_FLASH=y
37 CONFIG_SPI_FLASH_SPANSION=y 37 CONFIG_SPI_FLASH_SPANSION=y
38 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set 38 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
39 CONFIG_E1000=y 39 CONFIG_E1000=y
40 CONFIG_MII=y 40 CONFIG_MII=y
41 CONFIG_PCI=y 41 CONFIG_PCI=y
42 CONFIG_DM_PCI=y 42 CONFIG_DM_PCI=y
43 CONFIG_DM_PCI_COMPAT=y 43 CONFIG_DM_PCI_COMPAT=y
44 CONFIG_PCIE_LAYERSCAPE=y 44 CONFIG_PCIE_LAYERSCAPE=y
45 CONFIG_SYS_NS16550=y 45 CONFIG_SYS_NS16550=y
46 CONFIG_SPI=y 46 CONFIG_SPI=y
47 CONFIG_DM_SPI=y 47 CONFIG_DM_SPI=y
48 CONFIG_FSL_DSPI=y 48 CONFIG_FSL_DSPI=y
49 CONFIG_FSL_QSPI=y
49 CONFIG_USB=y 50 CONFIG_USB=y
50 CONFIG_DM_USB=y 51 CONFIG_DM_USB=y
51 CONFIG_USB_XHCI_HCD=y 52 CONFIG_USB_XHCI_HCD=y
52 CONFIG_USB_XHCI_DWC3=y 53 CONFIG_USB_XHCI_DWC3=y
53 CONFIG_USB_DWC3=y 54 CONFIG_USB_DWC3=y
54 CONFIG_USB_STORAGE=y 55 CONFIG_USB_STORAGE=y
55 CONFIG_USB_GADGET=y 56 CONFIG_USB_GADGET=y
56 CONFIG_RSA=y 57 CONFIG_RSA=y
57 CONFIG_RSA_SOFTWARE_EXP=y 58 CONFIG_RSA_SOFTWARE_EXP=y
58 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 59 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
59 60
configs/ls1088ardb_qspi_defconfig
Diff comments   View file @ 4c9d4a7
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_TARGET_LS1088ARDB=y 2 CONFIG_TARGET_LS1088ARDB=y
3 CONFIG_SYS_TEXT_BASE=0x20100000 3 CONFIG_SYS_TEXT_BASE=0x20100000
4 CONFIG_FSL_LS_PPA=y 4 CONFIG_FSL_LS_PPA=y
5 CONFIG_QSPI_AHB_INIT=y 5 CONFIG_QSPI_AHB_INIT=y
6 CONFIG_AHCI=y 6 CONFIG_AHCI=y
7 CONFIG_DISTRO_DEFAULTS=y 7 CONFIG_DISTRO_DEFAULTS=y
8 CONFIG_NR_DRAM_BANKS=2 8 CONFIG_NR_DRAM_BANKS=2
9 # CONFIG_SYS_MALLOC_F is not set 9 # CONFIG_SYS_MALLOC_F is not set
10 CONFIG_FIT_VERBOSE=y 10 CONFIG_FIT_VERBOSE=y
11 CONFIG_OF_BOARD_SETUP=y 11 CONFIG_OF_BOARD_SETUP=y
12 CONFIG_OF_STDOUT_VIA_ALIAS=y 12 CONFIG_OF_STDOUT_VIA_ALIAS=y
13 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" 13 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
14 CONFIG_USE_BOOTARGS=y 14 CONFIG_USE_BOOTARGS=y
15 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" 15 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
16 # CONFIG_USE_BOOTCOMMAND is not set 16 # CONFIG_USE_BOOTCOMMAND is not set
17 CONFIG_MISC_INIT_R=y 17 CONFIG_MISC_INIT_R=y
18 # CONFIG_DISPLAY_BOARDINFO is not set 18 # CONFIG_DISPLAY_BOARDINFO is not set
19 CONFIG_DISPLAY_BOARDINFO_LATE=y 19 CONFIG_DISPLAY_BOARDINFO_LATE=y
20 CONFIG_CMD_GREPENV=y 20 CONFIG_CMD_GREPENV=y
21 CONFIG_CMD_MEMTEST=y 21 CONFIG_CMD_MEMTEST=y
22 CONFIG_CMD_I2C=y 22 CONFIG_CMD_I2C=y
23 CONFIG_CMD_MMC=y 23 CONFIG_CMD_MMC=y
24 CONFIG_CMD_SF=y 24 CONFIG_CMD_SF=y
25 CONFIG_CMD_USB=y 25 CONFIG_CMD_USB=y
26 # CONFIG_CMD_SETEXPR is not set 26 # CONFIG_CMD_SETEXPR is not set
27 CONFIG_MP=y 27 CONFIG_MP=y
28 CONFIG_OF_CONTROL=y 28 CONFIG_OF_CONTROL=y
29 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" 29 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
30 CONFIG_ENV_IS_IN_SPI_FLASH=y 30 CONFIG_ENV_IS_IN_SPI_FLASH=y
31 CONFIG_NET_RANDOM_ETHADDR=y 31 CONFIG_NET_RANDOM_ETHADDR=y
32 CONFIG_DM=y 32 CONFIG_DM=y
33 CONFIG_SCSI_AHCI=y 33 CONFIG_SCSI_AHCI=y
34 CONFIG_SATA_CEVA=y 34 CONFIG_SATA_CEVA=y
35 CONFIG_DM_MMC=y 35 CONFIG_DM_MMC=y
36 CONFIG_FSL_ESDHC=y 36 CONFIG_FSL_ESDHC=y
37 CONFIG_DM_SPI_FLASH=y 37 CONFIG_DM_SPI_FLASH=y
38 CONFIG_SPI_FLASH=y 38 CONFIG_SPI_FLASH=y
39 CONFIG_SPI_FLASH_SPANSION=y 39 CONFIG_SPI_FLASH_SPANSION=y
40 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set 40 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
41 CONFIG_E1000=y 41 CONFIG_E1000=y
42 CONFIG_MII=y 42 CONFIG_MII=y
43 CONFIG_PCI=y 43 CONFIG_PCI=y
44 CONFIG_DM_PCI=y 44 CONFIG_DM_PCI=y
45 CONFIG_DM_PCI_COMPAT=y 45 CONFIG_DM_PCI_COMPAT=y
46 CONFIG_PCIE_LAYERSCAPE=y 46 CONFIG_PCIE_LAYERSCAPE=y
47 CONFIG_DM_SCSI=y 47 CONFIG_DM_SCSI=y
48 CONFIG_SYS_NS16550=y 48 CONFIG_SYS_NS16550=y
49 CONFIG_SPI=y 49 CONFIG_SPI=y
50 CONFIG_DM_SPI=y 50 CONFIG_DM_SPI=y
51 CONFIG_FSL_DSPI=y 51 CONFIG_FSL_DSPI=y
52 CONFIG_FSL_QSPI=y
52 CONFIG_USB=y 53 CONFIG_USB=y
53 CONFIG_DM_USB=y 54 CONFIG_DM_USB=y
54 CONFIG_USB_XHCI_HCD=y 55 CONFIG_USB_XHCI_HCD=y
55 CONFIG_USB_XHCI_DWC3=y 56 CONFIG_USB_XHCI_DWC3=y
56 CONFIG_USB_DWC3=y 57 CONFIG_USB_DWC3=y
57 CONFIG_USB_GADGET=y 58 CONFIG_USB_GADGET=y
58 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y 59 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
59 60
configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
Diff comments   View file @ 4c9d4a7
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_TARGET_LS1088ARDB=y 2 CONFIG_TARGET_LS1088ARDB=y
3 CONFIG_SYS_TEXT_BASE=0x80400000 3 CONFIG_SYS_TEXT_BASE=0x80400000
4 CONFIG_SPL_LIBCOMMON_SUPPORT=y 4 CONFIG_SPL_LIBCOMMON_SUPPORT=y
5 CONFIG_SPL_LIBGENERIC_SUPPORT=y 5 CONFIG_SPL_LIBGENERIC_SUPPORT=y
6 CONFIG_SECURE_BOOT=y 6 CONFIG_SECURE_BOOT=y
7 CONFIG_FSL_LS_PPA=y 7 CONFIG_FSL_LS_PPA=y
8 CONFIG_SPL_MMC_SUPPORT=y 8 CONFIG_SPL_MMC_SUPPORT=y
9 CONFIG_SPL_SERIAL_SUPPORT=y 9 CONFIG_SPL_SERIAL_SUPPORT=y
10 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y 10 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
11 CONFIG_SPL=y 11 CONFIG_SPL=y
12 CONFIG_DISTRO_DEFAULTS=y 12 CONFIG_DISTRO_DEFAULTS=y
13 CONFIG_NR_DRAM_BANKS=2 13 CONFIG_NR_DRAM_BANKS=2
14 # CONFIG_SYS_MALLOC_F is not set 14 # CONFIG_SYS_MALLOC_F is not set
15 CONFIG_FIT_VERBOSE=y 15 CONFIG_FIT_VERBOSE=y
16 CONFIG_OF_BOARD_SETUP=y 16 CONFIG_OF_BOARD_SETUP=y
17 CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI" 17 CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
18 CONFIG_SD_BOOT=y 18 CONFIG_SD_BOOT=y
19 CONFIG_USE_BOOTARGS=y 19 CONFIG_USE_BOOTARGS=y
20 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" 20 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
21 # CONFIG_USE_BOOTCOMMAND is not set 21 # CONFIG_USE_BOOTCOMMAND is not set
22 CONFIG_MISC_INIT_R=y 22 CONFIG_MISC_INIT_R=y
23 # CONFIG_DISPLAY_BOARDINFO is not set 23 # CONFIG_DISPLAY_BOARDINFO is not set
24 CONFIG_DISPLAY_BOARDINFO_LATE=y 24 CONFIG_DISPLAY_BOARDINFO_LATE=y
25 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y 25 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
26 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 26 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
27 CONFIG_SPL_CRYPTO_SUPPORT=y 27 CONFIG_SPL_CRYPTO_SUPPORT=y
28 CONFIG_SPL_HASH_SUPPORT=y 28 CONFIG_SPL_HASH_SUPPORT=y
29 CONFIG_SPL_ENV_SUPPORT=y 29 CONFIG_SPL_ENV_SUPPORT=y
30 CONFIG_SPL_I2C_SUPPORT=y 30 CONFIG_SPL_I2C_SUPPORT=y
31 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y 31 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
32 CONFIG_CMD_GREPENV=y 32 CONFIG_CMD_GREPENV=y
33 CONFIG_CMD_MEMTEST=y 33 CONFIG_CMD_MEMTEST=y
34 CONFIG_CMD_I2C=y 34 CONFIG_CMD_I2C=y
35 CONFIG_CMD_MMC=y 35 CONFIG_CMD_MMC=y
36 CONFIG_CMD_SF=y 36 CONFIG_CMD_SF=y
37 CONFIG_CMD_USB=y 37 CONFIG_CMD_USB=y
38 # CONFIG_CMD_SETEXPR is not set 38 # CONFIG_CMD_SETEXPR is not set
39 CONFIG_MP=y 39 CONFIG_MP=y
40 CONFIG_OF_CONTROL=y 40 CONFIG_OF_CONTROL=y
41 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" 41 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
42 CONFIG_NET_RANDOM_ETHADDR=y 42 CONFIG_NET_RANDOM_ETHADDR=y
43 CONFIG_DM=y 43 CONFIG_DM=y
44 CONFIG_SPL_DM=y 44 CONFIG_SPL_DM=y
45 CONFIG_SCSI_AHCI=y 45 CONFIG_SCSI_AHCI=y
46 CONFIG_FSL_ESDHC=y 46 CONFIG_FSL_ESDHC=y
47 CONFIG_DM_SPI_FLASH=y 47 CONFIG_DM_SPI_FLASH=y
48 CONFIG_SPI_FLASH=y 48 CONFIG_SPI_FLASH=y
49 CONFIG_SPI_FLASH_SPANSION=y 49 CONFIG_SPI_FLASH_SPANSION=y
50 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set 50 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
51 CONFIG_E1000=y 51 CONFIG_E1000=y
52 CONFIG_MII=y 52 CONFIG_MII=y
53 CONFIG_PCI=y 53 CONFIG_PCI=y
54 CONFIG_DM_PCI=y 54 CONFIG_DM_PCI=y
55 CONFIG_DM_PCI_COMPAT=y 55 CONFIG_DM_PCI_COMPAT=y
56 CONFIG_PCIE_LAYERSCAPE=y 56 CONFIG_PCIE_LAYERSCAPE=y
57 CONFIG_SYS_NS16550=y 57 CONFIG_SYS_NS16550=y
58 CONFIG_SPI=y 58 CONFIG_SPI=y
59 CONFIG_DM_SPI=y 59 CONFIG_DM_SPI=y
60 CONFIG_FSL_DSPI=y 60 CONFIG_FSL_DSPI=y
61 CONFIG_FSL_QSPI=y
61 CONFIG_USB=y 62 CONFIG_USB=y
62 CONFIG_DM_USB=y 63 CONFIG_DM_USB=y
63 CONFIG_USB_XHCI_HCD=y 64 CONFIG_USB_XHCI_HCD=y
64 CONFIG_USB_XHCI_DWC3=y 65 CONFIG_USB_XHCI_DWC3=y
65 CONFIG_USB_DWC3=y 66 CONFIG_USB_DWC3=y
66 CONFIG_USB_STORAGE=y 67 CONFIG_USB_STORAGE=y
67 CONFIG_RSA=y 68 CONFIG_RSA=y
68 CONFIG_SPL_RSA=y 69 CONFIG_SPL_RSA=y
69 70
configs/ls1088ardb_sdcard_qspi_defconfig
Diff comments   View file @ 4c9d4a7
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_TARGET_LS1088ARDB=y 2 CONFIG_TARGET_LS1088ARDB=y
3 CONFIG_SYS_TEXT_BASE=0x80400000 3 CONFIG_SYS_TEXT_BASE=0x80400000
4 CONFIG_SPL_LIBCOMMON_SUPPORT=y 4 CONFIG_SPL_LIBCOMMON_SUPPORT=y
5 CONFIG_SPL_LIBGENERIC_SUPPORT=y 5 CONFIG_SPL_LIBGENERIC_SUPPORT=y
6 CONFIG_FSL_LS_PPA=y 6 CONFIG_FSL_LS_PPA=y
7 CONFIG_SPL_MMC_SUPPORT=y 7 CONFIG_SPL_MMC_SUPPORT=y
8 CONFIG_SPL_SERIAL_SUPPORT=y 8 CONFIG_SPL_SERIAL_SUPPORT=y
9 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y 9 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
10 CONFIG_SPL=y 10 CONFIG_SPL=y
11 CONFIG_DISTRO_DEFAULTS=y 11 CONFIG_DISTRO_DEFAULTS=y
12 CONFIG_NR_DRAM_BANKS=2 12 CONFIG_NR_DRAM_BANKS=2
13 # CONFIG_SYS_MALLOC_F is not set 13 # CONFIG_SYS_MALLOC_F is not set
14 CONFIG_FIT_VERBOSE=y 14 CONFIG_FIT_VERBOSE=y
15 CONFIG_OF_BOARD_SETUP=y 15 CONFIG_OF_BOARD_SETUP=y
16 CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI" 16 CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
17 CONFIG_SD_BOOT=y 17 CONFIG_SD_BOOT=y
18 CONFIG_USE_BOOTARGS=y 18 CONFIG_USE_BOOTARGS=y
19 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" 19 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
20 # CONFIG_USE_BOOTCOMMAND is not set 20 # CONFIG_USE_BOOTCOMMAND is not set
21 CONFIG_MISC_INIT_R=y 21 CONFIG_MISC_INIT_R=y
22 # CONFIG_DISPLAY_BOARDINFO is not set 22 # CONFIG_DISPLAY_BOARDINFO is not set
23 CONFIG_DISPLAY_BOARDINFO_LATE=y 23 CONFIG_DISPLAY_BOARDINFO_LATE=y
24 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y 24 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
25 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 25 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
26 CONFIG_SPL_ENV_SUPPORT=y 26 CONFIG_SPL_ENV_SUPPORT=y
27 CONFIG_SPL_I2C_SUPPORT=y 27 CONFIG_SPL_I2C_SUPPORT=y
28 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y 28 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
29 CONFIG_CMD_GREPENV=y 29 CONFIG_CMD_GREPENV=y
30 CONFIG_CMD_MEMTEST=y 30 CONFIG_CMD_MEMTEST=y
31 CONFIG_CMD_I2C=y 31 CONFIG_CMD_I2C=y
32 CONFIG_CMD_MMC=y 32 CONFIG_CMD_MMC=y
33 CONFIG_CMD_SF=y 33 CONFIG_CMD_SF=y
34 CONFIG_CMD_USB=y 34 CONFIG_CMD_USB=y
35 # CONFIG_CMD_SETEXPR is not set 35 # CONFIG_CMD_SETEXPR is not set
36 CONFIG_MP=y 36 CONFIG_MP=y
37 CONFIG_OF_CONTROL=y 37 CONFIG_OF_CONTROL=y
38 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" 38 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
39 CONFIG_ENV_IS_IN_MMC=y 39 CONFIG_ENV_IS_IN_MMC=y
40 CONFIG_NET_RANDOM_ETHADDR=y 40 CONFIG_NET_RANDOM_ETHADDR=y
41 CONFIG_DM=y 41 CONFIG_DM=y
42 CONFIG_SCSI_AHCI=y 42 CONFIG_SCSI_AHCI=y
43 CONFIG_DM_MMC=y 43 CONFIG_DM_MMC=y
44 CONFIG_FSL_ESDHC=y 44 CONFIG_FSL_ESDHC=y
45 CONFIG_DM_SPI_FLASH=y 45 CONFIG_DM_SPI_FLASH=y
46 CONFIG_SPI_FLASH=y 46 CONFIG_SPI_FLASH=y
47 CONFIG_SPI_FLASH_SPANSION=y 47 CONFIG_SPI_FLASH_SPANSION=y
48 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set 48 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
49 CONFIG_E1000=y 49 CONFIG_E1000=y
50 CONFIG_MII=y 50 CONFIG_MII=y
51 CONFIG_PCI=y 51 CONFIG_PCI=y
52 CONFIG_DM_PCI=y 52 CONFIG_DM_PCI=y
53 CONFIG_DM_PCI_COMPAT=y 53 CONFIG_DM_PCI_COMPAT=y
54 CONFIG_PCIE_LAYERSCAPE=y 54 CONFIG_PCIE_LAYERSCAPE=y
55 CONFIG_SYS_NS16550=y 55 CONFIG_SYS_NS16550=y
56 CONFIG_SPI=y 56 CONFIG_SPI=y
57 CONFIG_DM_SPI=y 57 CONFIG_DM_SPI=y
58 CONFIG_FSL_DSPI=y 58 CONFIG_FSL_DSPI=y
59 CONFIG_FSL_QSPI=y
59 CONFIG_USB=y 60 CONFIG_USB=y
60 CONFIG_DM_USB=y 61 CONFIG_DM_USB=y
61 CONFIG_USB_XHCI_HCD=y 62 CONFIG_USB_XHCI_HCD=y
62 CONFIG_USB_XHCI_DWC3=y 63 CONFIG_USB_XHCI_DWC3=y
63 CONFIG_USB_DWC3=y 64 CONFIG_USB_DWC3=y
64 CONFIG_USB_STORAGE=y 65 CONFIG_USB_STORAGE=y
65 CONFIG_USB_GADGET=y 66 CONFIG_USB_GADGET=y
66 67
include/configs/ls1088aqds.h
Diff comments   View file @ 4c9d4a7
1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 */ 4 */
5 5
6 #ifndef __LS1088A_QDS_H 6 #ifndef __LS1088A_QDS_H
7 #define __LS1088A_QDS_H 7 #define __LS1088A_QDS_H
8 8
9 #include "ls1088a_common.h" 9 #include "ls1088a_common.h"
10 10
11 11
12 #ifndef __ASSEMBLY__ 12 #ifndef __ASSEMBLY__
13 unsigned long get_board_sys_clk(void); 13 unsigned long get_board_sys_clk(void);
14 unsigned long get_board_ddr_clk(void); 14 unsigned long get_board_ddr_clk(void);
15 #endif 15 #endif
16 16
17 17
18 #if defined(CONFIG_QSPI_BOOT) 18 #if defined(CONFIG_QSPI_BOOT)
19 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 19 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
20 #define CONFIG_ENV_SECT_SIZE 0x40000 20 #define CONFIG_ENV_SECT_SIZE 0x40000
21 #elif defined(CONFIG_SD_BOOT) 21 #elif defined(CONFIG_SD_BOOT)
22 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 22 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
23 #define CONFIG_SYS_MMC_ENV_DEV 0 23 #define CONFIG_SYS_MMC_ENV_DEV 0
24 #define CONFIG_ENV_SIZE 0x2000 24 #define CONFIG_ENV_SIZE 0x2000
25 #else 25 #else
26 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 26 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
27 #define CONFIG_ENV_SECT_SIZE 0x20000 27 #define CONFIG_ENV_SECT_SIZE 0x20000
28 #define CONFIG_ENV_SIZE 0x20000 28 #define CONFIG_ENV_SIZE 0x20000
29 #endif 29 #endif
30 30
31 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 31 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
32 #define CONFIG_QIXIS_I2C_ACCESS 32 #define CONFIG_QIXIS_I2C_ACCESS
33 #define SYS_NO_FLASH 33 #define SYS_NO_FLASH
34 34
35 #undef CONFIG_CMD_IMLS 35 #undef CONFIG_CMD_IMLS
36 #define CONFIG_SYS_CLK_FREQ 100000000 36 #define CONFIG_SYS_CLK_FREQ 100000000
37 #define CONFIG_DDR_CLK_FREQ 100000000 37 #define CONFIG_DDR_CLK_FREQ 100000000
38 #else 38 #else
39 #define CONFIG_QIXIS_I2C_ACCESS 39 #define CONFIG_QIXIS_I2C_ACCESS
40 #define CONFIG_SYS_I2C_EARLY_INIT 40 #define CONFIG_SYS_I2C_EARLY_INIT
41 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 41 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
42 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 42 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
43 #endif 43 #endif
44 44
45 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 45 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
46 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 46 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
47 47
48 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 48 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
49 49
50 #define CONFIG_DDR_SPD 50 #define CONFIG_DDR_SPD
51 #define CONFIG_DDR_ECC 51 #define CONFIG_DDR_ECC
52 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 52 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
53 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 53 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
54 #define SPD_EEPROM_ADDRESS 0x51 54 #define SPD_EEPROM_ADDRESS 0x51
55 #define CONFIG_SYS_SPD_BUS_NUM 0 55 #define CONFIG_SYS_SPD_BUS_NUM 0
56 56
57 57
58 /* 58 /*
59 * IFC Definitions 59 * IFC Definitions
60 */ 60 */
61 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 61 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
62 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 62 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
63 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 63 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
64 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 64 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
65 65
66 #define CONFIG_SYS_NOR0_CSPR \ 66 #define CONFIG_SYS_NOR0_CSPR \
67 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 67 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
68 CSPR_PORT_SIZE_16 | \ 68 CSPR_PORT_SIZE_16 | \
69 CSPR_MSEL_NOR | \ 69 CSPR_MSEL_NOR | \
70 CSPR_V) 70 CSPR_V)
71 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 71 #define CONFIG_SYS_NOR0_CSPR_EARLY \
72 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 72 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
73 CSPR_PORT_SIZE_16 | \ 73 CSPR_PORT_SIZE_16 | \
74 CSPR_MSEL_NOR | \ 74 CSPR_MSEL_NOR | \
75 CSPR_V) 75 CSPR_V)
76 #define CONFIG_SYS_NOR1_CSPR \ 76 #define CONFIG_SYS_NOR1_CSPR \
77 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 77 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
78 CSPR_PORT_SIZE_16 | \ 78 CSPR_PORT_SIZE_16 | \
79 CSPR_MSEL_NOR | \ 79 CSPR_MSEL_NOR | \
80 CSPR_V) 80 CSPR_V)
81 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 81 #define CONFIG_SYS_NOR1_CSPR_EARLY \
82 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 82 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
83 CSPR_PORT_SIZE_16 | \ 83 CSPR_PORT_SIZE_16 | \
84 CSPR_MSEL_NOR | \ 84 CSPR_MSEL_NOR | \
85 CSPR_V) 85 CSPR_V)
86 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 86 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
87 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 87 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
88 FTIM0_NOR_TEADC(0x5) | \ 88 FTIM0_NOR_TEADC(0x5) | \
89 FTIM0_NOR_TAVDS(0x6) | \ 89 FTIM0_NOR_TAVDS(0x6) | \
90 FTIM0_NOR_TEAHC(0x5)) 90 FTIM0_NOR_TEAHC(0x5))
91 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 91 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
92 FTIM1_NOR_TRAD_NOR(0x1a) | \ 92 FTIM1_NOR_TRAD_NOR(0x1a) | \
93 FTIM1_NOR_TSEQRAD_NOR(0x13)) 93 FTIM1_NOR_TSEQRAD_NOR(0x13))
94 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ 94 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
95 FTIM2_NOR_TCH(0x8) | \ 95 FTIM2_NOR_TCH(0x8) | \
96 FTIM2_NOR_TWPH(0xe) | \ 96 FTIM2_NOR_TWPH(0xe) | \
97 FTIM2_NOR_TWP(0x1c)) 97 FTIM2_NOR_TWP(0x1c))
98 #define CONFIG_SYS_NOR_FTIM3 0x04000000 98 #define CONFIG_SYS_NOR_FTIM3 0x04000000
99 #define CONFIG_SYS_IFC_CCR 0x01000000 99 #define CONFIG_SYS_IFC_CCR 0x01000000
100 100
101 #ifndef SYS_NO_FLASH 101 #ifndef SYS_NO_FLASH
102 #define CONFIG_SYS_FLASH_QUIET_TEST 102 #define CONFIG_SYS_FLASH_QUIET_TEST
103 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 103 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
104 104
105 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 105 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
106 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 106 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
107 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 107 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
108 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 108 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
109 109
110 #define CONFIG_SYS_FLASH_EMPTY_INFO 110 #define CONFIG_SYS_FLASH_EMPTY_INFO
111 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 111 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
112 CONFIG_SYS_FLASH_BASE + 0x40000000} 112 CONFIG_SYS_FLASH_BASE + 0x40000000}
113 #endif 113 #endif
114 #endif 114 #endif
115 115
116 #define CONFIG_NAND_FSL_IFC 116 #define CONFIG_NAND_FSL_IFC
117 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 117 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
118 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 118 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
119 119
120 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 120 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
121 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 121 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
122 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 122 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
123 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 123 | CSPR_MSEL_NAND /* MSEL = NAND */ \
124 | CSPR_V) 124 | CSPR_V)
125 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 125 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
126 126
127 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 127 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
128 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 128 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
129 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 129 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
130 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 130 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
131 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 131 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
132 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 132 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
133 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 133 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
134 134
135 #define CONFIG_SYS_NAND_ONFI_DETECTION 135 #define CONFIG_SYS_NAND_ONFI_DETECTION
136 136
137 /* ONFI NAND Flash mode0 Timing Params */ 137 /* ONFI NAND Flash mode0 Timing Params */
138 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 138 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
139 FTIM0_NAND_TWP(0x18) | \ 139 FTIM0_NAND_TWP(0x18) | \
140 FTIM0_NAND_TWCHT(0x07) | \ 140 FTIM0_NAND_TWCHT(0x07) | \
141 FTIM0_NAND_TWH(0x0a)) 141 FTIM0_NAND_TWH(0x0a))
142 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 142 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
143 FTIM1_NAND_TWBE(0x39) | \ 143 FTIM1_NAND_TWBE(0x39) | \
144 FTIM1_NAND_TRR(0x0e) | \ 144 FTIM1_NAND_TRR(0x0e) | \
145 FTIM1_NAND_TRP(0x18)) 145 FTIM1_NAND_TRP(0x18))
146 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 146 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
147 FTIM2_NAND_TREH(0x0a) | \ 147 FTIM2_NAND_TREH(0x0a) | \
148 FTIM2_NAND_TWHRE(0x1e)) 148 FTIM2_NAND_TWHRE(0x1e))
149 #define CONFIG_SYS_NAND_FTIM3 0x0 149 #define CONFIG_SYS_NAND_FTIM3 0x0
150 150
151 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 151 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
152 #define CONFIG_SYS_MAX_NAND_DEVICE 1 152 #define CONFIG_SYS_MAX_NAND_DEVICE 1
153 #define CONFIG_MTD_NAND_VERIFY_WRITE 153 #define CONFIG_MTD_NAND_VERIFY_WRITE
154 #define CONFIG_CMD_NAND 154 #define CONFIG_CMD_NAND
155 155
156 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 156 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
157 157
158 #define CONFIG_FSL_QIXIS 158 #define CONFIG_FSL_QIXIS
159 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 159 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
160 #define QIXIS_LBMAP_SWITCH 6 160 #define QIXIS_LBMAP_SWITCH 6
161 #define QIXIS_QMAP_MASK 0xe0 161 #define QIXIS_QMAP_MASK 0xe0
162 #define QIXIS_QMAP_SHIFT 5 162 #define QIXIS_QMAP_SHIFT 5
163 #define QIXIS_LBMAP_MASK 0x0f 163 #define QIXIS_LBMAP_MASK 0x0f
164 #define QIXIS_LBMAP_SHIFT 0 164 #define QIXIS_LBMAP_SHIFT 0
165 #define QIXIS_LBMAP_DFLTBANK 0x0e 165 #define QIXIS_LBMAP_DFLTBANK 0x0e
166 #define QIXIS_LBMAP_ALTBANK 0x2e 166 #define QIXIS_LBMAP_ALTBANK 0x2e
167 #define QIXIS_LBMAP_SD 0x00 167 #define QIXIS_LBMAP_SD 0x00
168 #define QIXIS_LBMAP_EMMC 0x00 168 #define QIXIS_LBMAP_EMMC 0x00
169 #define QIXIS_LBMAP_IFC 0x00 169 #define QIXIS_LBMAP_IFC 0x00
170 #define QIXIS_LBMAP_SD_QSPI 0x0e 170 #define QIXIS_LBMAP_SD_QSPI 0x0e
171 #define QIXIS_LBMAP_QSPI 0x0e 171 #define QIXIS_LBMAP_QSPI 0x0e
172 #define QIXIS_RCW_SRC_IFC 0x25 172 #define QIXIS_RCW_SRC_IFC 0x25
173 #define QIXIS_RCW_SRC_SD 0x40 173 #define QIXIS_RCW_SRC_SD 0x40
174 #define QIXIS_RCW_SRC_EMMC 0x41 174 #define QIXIS_RCW_SRC_EMMC 0x41
175 #define QIXIS_RCW_SRC_QSPI 0x62 175 #define QIXIS_RCW_SRC_QSPI 0x62
176 #define QIXIS_RST_CTL_RESET 0x41 176 #define QIXIS_RST_CTL_RESET 0x41
177 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 177 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
178 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 178 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
179 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 179 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
180 #define QIXIS_RST_FORCE_MEM 0x01 180 #define QIXIS_RST_FORCE_MEM 0x01
181 #define QIXIS_STAT_PRES1 0xb 181 #define QIXIS_STAT_PRES1 0xb
182 #define QIXIS_SDID_MASK 0x07 182 #define QIXIS_SDID_MASK 0x07
183 #define QIXIS_ESDHC_NO_ADAPTER 0x7 183 #define QIXIS_ESDHC_NO_ADAPTER 0x7
184 184
185 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 185 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
186 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 186 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
187 | CSPR_PORT_SIZE_8 \ 187 | CSPR_PORT_SIZE_8 \
188 | CSPR_MSEL_GPCM \ 188 | CSPR_MSEL_GPCM \
189 | CSPR_V) 189 | CSPR_V)
190 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 190 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
191 | CSPR_PORT_SIZE_8 \ 191 | CSPR_PORT_SIZE_8 \
192 | CSPR_MSEL_GPCM \ 192 | CSPR_MSEL_GPCM \
193 | CSPR_V) 193 | CSPR_V)
194 194
195 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 195 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
196 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 196 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
197 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 197 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
198 #else 198 #else
199 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) 199 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
200 #endif 200 #endif
201 /* QIXIS Timing parameters*/ 201 /* QIXIS Timing parameters*/
202 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 202 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
203 FTIM0_GPCM_TEADC(0x0e) | \ 203 FTIM0_GPCM_TEADC(0x0e) | \
204 FTIM0_GPCM_TEAHC(0x0e)) 204 FTIM0_GPCM_TEAHC(0x0e))
205 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 205 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
206 FTIM1_GPCM_TRAD(0x3f)) 206 FTIM1_GPCM_TRAD(0x3f))
207 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 207 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
208 FTIM2_GPCM_TCH(0xf) | \ 208 FTIM2_GPCM_TCH(0xf) | \
209 FTIM2_GPCM_TWP(0x3E)) 209 FTIM2_GPCM_TWP(0x3E))
210 #define SYS_FPGA_CS_FTIM3 0x0 210 #define SYS_FPGA_CS_FTIM3 0x0
211 211
212 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 212 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
213 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 213 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
214 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 214 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
215 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 215 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
216 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 216 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
217 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 217 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
218 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 218 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
219 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 219 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
220 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 220 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
221 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 221 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
222 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 222 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
223 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 223 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
224 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK 224 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
225 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 225 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
226 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 226 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
227 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 227 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
228 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 228 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
229 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 229 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
230 #else 230 #else
231 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 231 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
232 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 232 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
233 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 233 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
234 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 234 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
235 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 235 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
236 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 236 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
237 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 237 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
238 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 238 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
239 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 239 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
240 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 240 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
241 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 241 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
242 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 242 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
243 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 243 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
244 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 244 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
245 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 245 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
246 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 246 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
247 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 247 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
248 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 248 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
249 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 249 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
250 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 250 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
251 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 251 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
252 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 252 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
253 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 253 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
254 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 254 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
255 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 255 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
256 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 256 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
257 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 257 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
258 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 258 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
259 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 259 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
260 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL 260 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
261 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK 261 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
262 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 262 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
263 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 263 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
264 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 264 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
265 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 265 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
266 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 266 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
267 #endif 267 #endif
268 268
269 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 269 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
270 270
271 /* 271 /*
272 * I2C bus multiplexer 272 * I2C bus multiplexer
273 */ 273 */
274 #define I2C_MUX_PCA_ADDR_PRI 0x77 274 #define I2C_MUX_PCA_ADDR_PRI 0x77
275 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 275 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
276 #define I2C_RETIMER_ADDR 0x18 276 #define I2C_RETIMER_ADDR 0x18
277 #define I2C_RETIMER_ADDR2 0x19 277 #define I2C_RETIMER_ADDR2 0x19
278 #define I2C_MUX_CH_DEFAULT 0x8 278 #define I2C_MUX_CH_DEFAULT 0x8
279 #define I2C_MUX_CH5 0xD 279 #define I2C_MUX_CH5 0xD
280 280
281 #define I2C_MUX_CH_VOL_MONITOR 0xA 281 #define I2C_MUX_CH_VOL_MONITOR 0xA
282 282
283 /* Voltage monitor on channel 2*/ 283 /* Voltage monitor on channel 2*/
284 #define I2C_VOL_MONITOR_ADDR 0x63 284 #define I2C_VOL_MONITOR_ADDR 0x63
285 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 285 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
286 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 286 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
287 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 287 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
288 #define I2C_SVDD_MONITOR_ADDR 0x4F 288 #define I2C_SVDD_MONITOR_ADDR 0x4F
289 289
290 #define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv" 290 #define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv"
291 #define CONFIG_VID 291 #define CONFIG_VID
292 292
293 /* The lowest and highest voltage allowed for LS1088AQDS */ 293 /* The lowest and highest voltage allowed for LS1088AQDS */
294 #define VDD_MV_MIN 819 294 #define VDD_MV_MIN 819
295 #define VDD_MV_MAX 1212 295 #define VDD_MV_MAX 1212
296 296
297 #define CONFIG_VOL_MONITOR_LTC3882_SET 297 #define CONFIG_VOL_MONITOR_LTC3882_SET
298 #define CONFIG_VOL_MONITOR_LTC3882_READ 298 #define CONFIG_VOL_MONITOR_LTC3882_READ
299 299
300 /* PM Bus commands code for LTC3882*/ 300 /* PM Bus commands code for LTC3882*/
301 #define PMBUS_CMD_PAGE 0x0 301 #define PMBUS_CMD_PAGE 0x0
302 #define PMBUS_CMD_READ_VOUT 0x8B 302 #define PMBUS_CMD_READ_VOUT 0x8B
303 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 303 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
304 #define PMBUS_CMD_VOUT_COMMAND 0x21 304 #define PMBUS_CMD_VOUT_COMMAND 0x21
305 305
306 #define PWM_CHANNEL0 0x0 306 #define PWM_CHANNEL0 0x0
307 307
308 /* 308 /*
309 * RTC configuration 309 * RTC configuration
310 */ 310 */
311 #define RTC 311 #define RTC
312 #define CONFIG_RTC_PCF8563 1 312 #define CONFIG_RTC_PCF8563 1
313 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 313 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
314 #define CONFIG_CMD_DATE 314 #define CONFIG_CMD_DATE
315 315
316 /* EEPROM */ 316 /* EEPROM */
317 #define CONFIG_ID_EEPROM 317 #define CONFIG_ID_EEPROM
318 #define CONFIG_SYS_I2C_EEPROM_NXID 318 #define CONFIG_SYS_I2C_EEPROM_NXID
319 #define CONFIG_SYS_EEPROM_BUS_NUM 0 319 #define CONFIG_SYS_EEPROM_BUS_NUM 0
320 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 320 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
321 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 321 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
322 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 322 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
323 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 323 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
324 324
325 /* QSPI device */ 325 /* QSPI device */
326 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 326 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
327 #define CONFIG_FSL_QSPI
328 #define FSL_QSPI_FLASH_SIZE (1 << 26) 327 #define FSL_QSPI_FLASH_SIZE (1 << 26)
329 #define FSL_QSPI_FLASH_NUM 2 328 #define FSL_QSPI_FLASH_NUM 2
330 329
331 #endif 330 #endif
332 331
333 #ifdef CONFIG_FSL_DSPI 332 #ifdef CONFIG_FSL_DSPI
334 #define CONFIG_SPI_FLASH_STMICRO 333 #define CONFIG_SPI_FLASH_STMICRO
335 #define CONFIG_SPI_FLASH_SST 334 #define CONFIG_SPI_FLASH_SST
336 #define CONFIG_SPI_FLASH_EON 335 #define CONFIG_SPI_FLASH_EON
337 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 336 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
338 #define CONFIG_SF_DEFAULT_BUS 1 337 #define CONFIG_SF_DEFAULT_BUS 1
339 #define CONFIG_SF_DEFAULT_CS 0 338 #define CONFIG_SF_DEFAULT_CS 0
340 #endif 339 #endif
341 #endif 340 #endif
342 341
343 #define CONFIG_CMD_MEMINFO 342 #define CONFIG_CMD_MEMINFO
344 #define CONFIG_SYS_MEMTEST_START 0x80000000 343 #define CONFIG_SYS_MEMTEST_START 0x80000000
345 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 344 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
346 345
347 #ifdef CONFIG_SPL_BUILD 346 #ifdef CONFIG_SPL_BUILD
348 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 347 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
349 #else 348 #else
350 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 349 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
351 #endif 350 #endif
352 351
353 #define CONFIG_FSL_MEMAC 352 #define CONFIG_FSL_MEMAC
354 353
355 /* MMC */ 354 /* MMC */
356 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 355 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
357 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 356 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
358 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 357 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
359 358
360 /* Initial environment variables */ 359 /* Initial environment variables */
361 #ifdef CONFIG_SECURE_BOOT 360 #ifdef CONFIG_SECURE_BOOT
362 #undef CONFIG_EXTRA_ENV_SETTINGS 361 #undef CONFIG_EXTRA_ENV_SETTINGS
363 #define CONFIG_EXTRA_ENV_SETTINGS \ 362 #define CONFIG_EXTRA_ENV_SETTINGS \
364 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 363 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
365 "loadaddr=0x90100000\0" \ 364 "loadaddr=0x90100000\0" \
366 "kernel_addr=0x100000\0" \ 365 "kernel_addr=0x100000\0" \
367 "ramdisk_addr=0x800000\0" \ 366 "ramdisk_addr=0x800000\0" \
368 "ramdisk_size=0x2000000\0" \ 367 "ramdisk_size=0x2000000\0" \
369 "fdt_high=0xa0000000\0" \ 368 "fdt_high=0xa0000000\0" \
370 "initrd_high=0xffffffffffffffff\0" \ 369 "initrd_high=0xffffffffffffffff\0" \
371 "kernel_start=0x1000000\0" \ 370 "kernel_start=0x1000000\0" \
372 "kernel_load=0xa0000000\0" \ 371 "kernel_load=0xa0000000\0" \
373 "kernel_size=0x2800000\0" \ 372 "kernel_size=0x2800000\0" \
374 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \ 373 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \
375 "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \ 374 "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \
376 "sf read 0xa0e00000 0xe00000 0x100000;" \ 375 "sf read 0xa0e00000 0xe00000 0x100000;" \
377 "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \ 376 "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \
378 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \ 377 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
379 "mcmemsize=0x70000000 \0" 378 "mcmemsize=0x70000000 \0"
380 #else /* if !(CONFIG_SECURE_BOOT) */ 379 #else /* if !(CONFIG_SECURE_BOOT) */
381 #if defined(CONFIG_QSPI_BOOT) 380 #if defined(CONFIG_QSPI_BOOT)
382 #undef CONFIG_EXTRA_ENV_SETTINGS 381 #undef CONFIG_EXTRA_ENV_SETTINGS
383 #define CONFIG_EXTRA_ENV_SETTINGS \ 382 #define CONFIG_EXTRA_ENV_SETTINGS \
384 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 383 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
385 "loadaddr=0x90100000\0" \ 384 "loadaddr=0x90100000\0" \
386 "kernel_addr=0x100000\0" \ 385 "kernel_addr=0x100000\0" \
387 "ramdisk_addr=0x800000\0" \ 386 "ramdisk_addr=0x800000\0" \
388 "ramdisk_size=0x2000000\0" \ 387 "ramdisk_size=0x2000000\0" \
389 "fdt_high=0xa0000000\0" \ 388 "fdt_high=0xa0000000\0" \
390 "initrd_high=0xffffffffffffffff\0" \ 389 "initrd_high=0xffffffffffffffff\0" \
391 "kernel_start=0x1000000\0" \ 390 "kernel_start=0x1000000\0" \
392 "kernel_load=0xa0000000\0" \ 391 "kernel_load=0xa0000000\0" \
393 "kernel_size=0x2800000\0" \ 392 "kernel_size=0x2800000\0" \
394 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 393 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
395 "sf read 0x80100000 0xE00000 0x100000;" \ 394 "sf read 0x80100000 0xE00000 0x100000;" \
396 "fsl_mc start mc 0x80000000 0x80100000\0" \ 395 "fsl_mc start mc 0x80000000 0x80100000\0" \
397 "mcmemsize=0x70000000 \0" 396 "mcmemsize=0x70000000 \0"
398 #elif defined(CONFIG_SD_BOOT) 397 #elif defined(CONFIG_SD_BOOT)
399 #undef CONFIG_EXTRA_ENV_SETTINGS 398 #undef CONFIG_EXTRA_ENV_SETTINGS
400 #define CONFIG_EXTRA_ENV_SETTINGS \ 399 #define CONFIG_EXTRA_ENV_SETTINGS \
401 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 400 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
402 "loadaddr=0x90100000\0" \ 401 "loadaddr=0x90100000\0" \
403 "kernel_addr=0x800\0" \ 402 "kernel_addr=0x800\0" \
404 "ramdisk_addr=0x800000\0" \ 403 "ramdisk_addr=0x800000\0" \
405 "ramdisk_size=0x2000000\0" \ 404 "ramdisk_size=0x2000000\0" \
406 "fdt_high=0xa0000000\0" \ 405 "fdt_high=0xa0000000\0" \
407 "initrd_high=0xffffffffffffffff\0" \ 406 "initrd_high=0xffffffffffffffff\0" \
408 "kernel_start=0x8000\0" \ 407 "kernel_start=0x8000\0" \
409 "kernel_load=0xa0000000\0" \ 408 "kernel_load=0xa0000000\0" \
410 "kernel_size=0x14000\0" \ 409 "kernel_size=0x14000\0" \
411 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 410 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
412 "mmc read 0x80100000 0x7000 0x800;" \ 411 "mmc read 0x80100000 0x7000 0x800;" \
413 "fsl_mc start mc 0x80000000 0x80100000\0" \ 412 "fsl_mc start mc 0x80000000 0x80100000\0" \
414 "mcmemsize=0x70000000 \0" 413 "mcmemsize=0x70000000 \0"
415 #else /* NOR BOOT */ 414 #else /* NOR BOOT */
416 #undef CONFIG_EXTRA_ENV_SETTINGS 415 #undef CONFIG_EXTRA_ENV_SETTINGS
417 #define CONFIG_EXTRA_ENV_SETTINGS \ 416 #define CONFIG_EXTRA_ENV_SETTINGS \
418 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 417 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
419 "loadaddr=0x90100000\0" \ 418 "loadaddr=0x90100000\0" \
420 "kernel_addr=0x100000\0" \ 419 "kernel_addr=0x100000\0" \
421 "ramdisk_addr=0x800000\0" \ 420 "ramdisk_addr=0x800000\0" \
422 "ramdisk_size=0x2000000\0" \ 421 "ramdisk_size=0x2000000\0" \
423 "fdt_high=0xa0000000\0" \ 422 "fdt_high=0xa0000000\0" \
424 "initrd_high=0xffffffffffffffff\0" \ 423 "initrd_high=0xffffffffffffffff\0" \
425 "kernel_start=0x1000000\0" \ 424 "kernel_start=0x1000000\0" \
426 "kernel_load=0xa0000000\0" \ 425 "kernel_load=0xa0000000\0" \
427 "kernel_size=0x2800000\0" \ 426 "kernel_size=0x2800000\0" \
428 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \ 427 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
429 "mcmemsize=0x70000000 \0" 428 "mcmemsize=0x70000000 \0"
430 #endif 429 #endif
431 #endif /* CONFIG_SECURE_BOOT */ 430 #endif /* CONFIG_SECURE_BOOT */
432 431
433 #ifdef CONFIG_FSL_MC_ENET 432 #ifdef CONFIG_FSL_MC_ENET
434 #define CONFIG_FSL_MEMAC 433 #define CONFIG_FSL_MEMAC
435 #define CONFIG_PHYLIB 434 #define CONFIG_PHYLIB
436 #define CONFIG_PHYLIB_10G 435 #define CONFIG_PHYLIB_10G
437 #define CONFIG_PHY_VITESSE 436 #define CONFIG_PHY_VITESSE
438 #define CONFIG_PHY_REALTEK 437 #define CONFIG_PHY_REALTEK
439 #define CONFIG_PHY_TERANETICS 438 #define CONFIG_PHY_TERANETICS
440 #define RGMII_PHY1_ADDR 0x1 439 #define RGMII_PHY1_ADDR 0x1
441 #define RGMII_PHY2_ADDR 0x2 440 #define RGMII_PHY2_ADDR 0x2
442 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 441 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
443 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 442 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
444 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 443 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
445 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 444 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
446 445
447 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 446 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
448 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 447 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
449 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 448 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
450 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 449 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
451 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 450 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
452 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 451 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
453 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 452 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
454 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 453 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
455 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 454 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
456 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 455 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
457 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 456 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
458 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 457 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
459 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 458 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
460 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 459 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
461 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 460 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
462 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 461 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
463 462
464 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 463 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
465 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 464 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
466 465
467 #endif 466 #endif
468 467
469 #define BOOT_TARGET_DEVICES(func) \ 468 #define BOOT_TARGET_DEVICES(func) \
470 func(USB, usb, 0) \ 469 func(USB, usb, 0) \
471 func(MMC, mmc, 0) \ 470 func(MMC, mmc, 0) \
472 func(SCSI, scsi, 0) \ 471 func(SCSI, scsi, 0) \
473 func(DHCP, dhcp, na) 472 func(DHCP, dhcp, na)
474 #include <config_distro_bootcmd.h> 473 #include <config_distro_bootcmd.h>
475 474
476 #include <asm/fsl_secure_boot.h> 475 #include <asm/fsl_secure_boot.h>
477 476
478 #endif /* __LS1088A_QDS_H */ 477 #endif /* __LS1088A_QDS_H */
479 478
include/configs/ls1088ardb.h
Diff comments   View file @ 4c9d4a7
1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 */ 4 */
5 5
6 #ifndef __LS1088A_RDB_H 6 #ifndef __LS1088A_RDB_H
7 #define __LS1088A_RDB_H 7 #define __LS1088A_RDB_H
8 8
9 #include "ls1088a_common.h" 9 #include "ls1088a_common.h"
10 10
11 #if defined(CONFIG_QSPI_BOOT) 11 #if defined(CONFIG_QSPI_BOOT)
12 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 12 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
13 #define CONFIG_ENV_SECT_SIZE 0x40000 13 #define CONFIG_ENV_SECT_SIZE 0x40000
14 #elif defined(CONFIG_SD_BOOT) 14 #elif defined(CONFIG_SD_BOOT)
15 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 15 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
16 #define CONFIG_SYS_MMC_ENV_DEV 0 16 #define CONFIG_SYS_MMC_ENV_DEV 0
17 #define CONFIG_ENV_SIZE 0x2000 17 #define CONFIG_ENV_SIZE 0x2000
18 #else 18 #else
19 #define CONFIG_ENV_IS_IN_FLASH 19 #define CONFIG_ENV_IS_IN_FLASH
20 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 20 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
21 #define CONFIG_ENV_SECT_SIZE 0x20000 21 #define CONFIG_ENV_SECT_SIZE 0x20000
22 #define CONFIG_ENV_SIZE 0x20000 22 #define CONFIG_ENV_SIZE 0x20000
23 #endif 23 #endif
24 24
25 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 25 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
26 #ifndef CONFIG_SPL_BUILD 26 #ifndef CONFIG_SPL_BUILD
27 #define CONFIG_QIXIS_I2C_ACCESS 27 #define CONFIG_QIXIS_I2C_ACCESS
28 #endif 28 #endif
29 #define SYS_NO_FLASH 29 #define SYS_NO_FLASH
30 #undef CONFIG_CMD_IMLS 30 #undef CONFIG_CMD_IMLS
31 #endif 31 #endif
32 32
33 #define CONFIG_SYS_CLK_FREQ 100000000 33 #define CONFIG_SYS_CLK_FREQ 100000000
34 #define CONFIG_DDR_CLK_FREQ 100000000 34 #define CONFIG_DDR_CLK_FREQ 100000000
35 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ 35 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
36 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 36 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
37 37
38 #define CONFIG_DDR_SPD 38 #define CONFIG_DDR_SPD
39 #ifdef CONFIG_EMU 39 #ifdef CONFIG_EMU
40 #define CONFIG_SYS_FSL_DDR_EMU 40 #define CONFIG_SYS_FSL_DDR_EMU
41 #define CONFIG_SYS_MXC_I2C1_SPEED 40000000 41 #define CONFIG_SYS_MXC_I2C1_SPEED 40000000
42 #define CONFIG_SYS_MXC_I2C2_SPEED 40000000 42 #define CONFIG_SYS_MXC_I2C2_SPEED 40000000
43 #else 43 #else
44 #define CONFIG_DDR_ECC 44 #define CONFIG_DDR_ECC
45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
47 #endif 47 #endif
48 #define SPD_EEPROM_ADDRESS 0x51 48 #define SPD_EEPROM_ADDRESS 0x51
49 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 49 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
50 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 50 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
51 51
52 52
53 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 53 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
54 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 54 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
55 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 55 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
56 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) 56 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
57 57
58 #define CONFIG_SYS_NOR0_CSPR \ 58 #define CONFIG_SYS_NOR0_CSPR \
59 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 59 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
60 CSPR_PORT_SIZE_16 | \ 60 CSPR_PORT_SIZE_16 | \
61 CSPR_MSEL_NOR | \ 61 CSPR_MSEL_NOR | \
62 CSPR_V) 62 CSPR_V)
63 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 63 #define CONFIG_SYS_NOR0_CSPR_EARLY \
64 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 64 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
65 CSPR_PORT_SIZE_16 | \ 65 CSPR_PORT_SIZE_16 | \
66 CSPR_MSEL_NOR | \ 66 CSPR_MSEL_NOR | \
67 CSPR_V) 67 CSPR_V)
68 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) 68 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
69 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 69 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
70 FTIM0_NOR_TEADC(0x1) | \ 70 FTIM0_NOR_TEADC(0x1) | \
71 FTIM0_NOR_TEAHC(0x1)) 71 FTIM0_NOR_TEAHC(0x1))
72 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 72 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
73 FTIM1_NOR_TRAD_NOR(0x1)) 73 FTIM1_NOR_TRAD_NOR(0x1))
74 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 74 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
75 FTIM2_NOR_TCH(0x0) | \ 75 FTIM2_NOR_TCH(0x0) | \
76 FTIM2_NOR_TWP(0x1)) 76 FTIM2_NOR_TWP(0x1))
77 #define CONFIG_SYS_NOR_FTIM3 0x04000000 77 #define CONFIG_SYS_NOR_FTIM3 0x04000000
78 #define CONFIG_SYS_IFC_CCR 0x01000000 78 #define CONFIG_SYS_IFC_CCR 0x01000000
79 79
80 #ifndef SYS_NO_FLASH 80 #ifndef SYS_NO_FLASH
81 #define CONFIG_SYS_FLASH_QUIET_TEST 81 #define CONFIG_SYS_FLASH_QUIET_TEST
82 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 82 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
83 83
84 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 84 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
85 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 85 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
86 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 86 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
87 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 87 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
88 88
89 #define CONFIG_SYS_FLASH_EMPTY_INFO 89 #define CONFIG_SYS_FLASH_EMPTY_INFO
90 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 90 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
91 #endif 91 #endif
92 #endif 92 #endif
93 93
94 #ifndef SPL_NO_IFC 94 #ifndef SPL_NO_IFC
95 #define CONFIG_NAND_FSL_IFC 95 #define CONFIG_NAND_FSL_IFC
96 #endif 96 #endif
97 97
98 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 98 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
99 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 99 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
100 100
101 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 101 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
102 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 102 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
103 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 103 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
104 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 104 | CSPR_MSEL_NAND /* MSEL = NAND */ \
105 | CSPR_V) 105 | CSPR_V)
106 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 106 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
107 107
108 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 108 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
109 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 109 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
110 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 110 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
111 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 111 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
112 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 112 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
113 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 113 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
114 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 114 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
115 115
116 #define CONFIG_SYS_NAND_ONFI_DETECTION 116 #define CONFIG_SYS_NAND_ONFI_DETECTION
117 117
118 /* ONFI NAND Flash mode0 Timing Params */ 118 /* ONFI NAND Flash mode0 Timing Params */
119 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 119 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
120 FTIM0_NAND_TWP(0x18) | \ 120 FTIM0_NAND_TWP(0x18) | \
121 FTIM0_NAND_TWCHT(0x07) | \ 121 FTIM0_NAND_TWCHT(0x07) | \
122 FTIM0_NAND_TWH(0x0a)) 122 FTIM0_NAND_TWH(0x0a))
123 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 123 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
124 FTIM1_NAND_TWBE(0x39) | \ 124 FTIM1_NAND_TWBE(0x39) | \
125 FTIM1_NAND_TRR(0x0e) | \ 125 FTIM1_NAND_TRR(0x0e) | \
126 FTIM1_NAND_TRP(0x18)) 126 FTIM1_NAND_TRP(0x18))
127 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 127 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
128 FTIM2_NAND_TREH(0x0a) | \ 128 FTIM2_NAND_TREH(0x0a) | \
129 FTIM2_NAND_TWHRE(0x1e)) 129 FTIM2_NAND_TWHRE(0x1e))
130 #define CONFIG_SYS_NAND_FTIM3 0x0 130 #define CONFIG_SYS_NAND_FTIM3 0x0
131 131
132 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 132 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
133 #define CONFIG_SYS_MAX_NAND_DEVICE 1 133 #define CONFIG_SYS_MAX_NAND_DEVICE 1
134 #define CONFIG_MTD_NAND_VERIFY_WRITE 134 #define CONFIG_MTD_NAND_VERIFY_WRITE
135 #define CONFIG_CMD_NAND 135 #define CONFIG_CMD_NAND
136 136
137 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 137 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
138 138
139 #ifndef SPL_NO_QIXIS 139 #ifndef SPL_NO_QIXIS
140 #define CONFIG_FSL_QIXIS 140 #define CONFIG_FSL_QIXIS
141 #endif 141 #endif
142 142
143 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 143 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
144 #define QIXIS_BRDCFG4_OFFSET 0x54 144 #define QIXIS_BRDCFG4_OFFSET 0x54
145 #define QIXIS_LBMAP_SWITCH 2 145 #define QIXIS_LBMAP_SWITCH 2
146 #define QIXIS_QMAP_MASK 0xe0 146 #define QIXIS_QMAP_MASK 0xe0
147 #define QIXIS_QMAP_SHIFT 5 147 #define QIXIS_QMAP_SHIFT 5
148 #define QIXIS_LBMAP_MASK 0x1f 148 #define QIXIS_LBMAP_MASK 0x1f
149 #define QIXIS_LBMAP_SHIFT 5 149 #define QIXIS_LBMAP_SHIFT 5
150 #define QIXIS_LBMAP_DFLTBANK 0x00 150 #define QIXIS_LBMAP_DFLTBANK 0x00
151 #define QIXIS_LBMAP_ALTBANK 0x20 151 #define QIXIS_LBMAP_ALTBANK 0x20
152 #define QIXIS_LBMAP_SD 0x00 152 #define QIXIS_LBMAP_SD 0x00
153 #define QIXIS_LBMAP_EMMC 0x00 153 #define QIXIS_LBMAP_EMMC 0x00
154 #define QIXIS_LBMAP_SD_QSPI 0x00 154 #define QIXIS_LBMAP_SD_QSPI 0x00
155 #define QIXIS_LBMAP_QSPI 0x00 155 #define QIXIS_LBMAP_QSPI 0x00
156 #define QIXIS_RCW_SRC_SD 0x40 156 #define QIXIS_RCW_SRC_SD 0x40
157 #define QIXIS_RCW_SRC_EMMC 0x41 157 #define QIXIS_RCW_SRC_EMMC 0x41
158 #define QIXIS_RCW_SRC_QSPI 0x62 158 #define QIXIS_RCW_SRC_QSPI 0x62
159 #define QIXIS_RST_CTL_RESET 0x31 159 #define QIXIS_RST_CTL_RESET 0x31
160 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 160 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
161 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 161 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
162 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 162 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
163 #define QIXIS_RST_FORCE_MEM 0x01 163 #define QIXIS_RST_FORCE_MEM 0x01
164 164
165 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 165 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
166 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 166 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
167 | CSPR_PORT_SIZE_8 \ 167 | CSPR_PORT_SIZE_8 \
168 | CSPR_MSEL_GPCM \ 168 | CSPR_MSEL_GPCM \
169 | CSPR_V) 169 | CSPR_V)
170 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 170 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
171 | CSPR_PORT_SIZE_8 \ 171 | CSPR_PORT_SIZE_8 \
172 | CSPR_MSEL_GPCM \ 172 | CSPR_MSEL_GPCM \
173 | CSPR_V) 173 | CSPR_V)
174 174
175 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) 175 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
176 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 176 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
177 /* QIXIS Timing parameters*/ 177 /* QIXIS Timing parameters*/
178 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 178 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
179 FTIM0_GPCM_TEADC(0x0e) | \ 179 FTIM0_GPCM_TEADC(0x0e) | \
180 FTIM0_GPCM_TEAHC(0x0e)) 180 FTIM0_GPCM_TEAHC(0x0e))
181 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 181 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
182 FTIM1_GPCM_TRAD(0x3f)) 182 FTIM1_GPCM_TRAD(0x3f))
183 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 183 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
184 FTIM2_GPCM_TCH(0xf) | \ 184 FTIM2_GPCM_TCH(0xf) | \
185 FTIM2_GPCM_TWP(0x3E)) 185 FTIM2_GPCM_TWP(0x3E))
186 #define SYS_FPGA_CS_FTIM3 0x0 186 #define SYS_FPGA_CS_FTIM3 0x0
187 187
188 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 188 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
189 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 189 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
190 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 190 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
191 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 191 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
192 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 192 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
193 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 193 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
194 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 194 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
195 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 195 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
196 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 196 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
197 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 197 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
198 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 198 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
199 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 199 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
200 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK 200 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
201 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 201 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
202 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 202 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
203 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 203 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
204 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 204 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
205 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 205 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
206 #else 206 #else
207 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 207 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
208 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 208 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
209 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 209 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
210 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 210 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
211 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 211 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
212 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 212 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
213 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 213 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
214 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 214 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
215 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 215 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
216 #endif 216 #endif
217 217
218 218
219 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 219 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
220 220
221 #define I2C_MUX_CH_VOL_MONITOR 0xA 221 #define I2C_MUX_CH_VOL_MONITOR 0xA
222 /* Voltage monitor on channel 2*/ 222 /* Voltage monitor on channel 2*/
223 #define I2C_VOL_MONITOR_ADDR 0x63 223 #define I2C_VOL_MONITOR_ADDR 0x63
224 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 224 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
225 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 225 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
226 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 226 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
227 #define I2C_SVDD_MONITOR_ADDR 0x4F 227 #define I2C_SVDD_MONITOR_ADDR 0x4F
228 228
229 #define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv" 229 #define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv"
230 #define CONFIG_VID 230 #define CONFIG_VID
231 231
232 /* The lowest and highest voltage allowed for LS1088ARDB */ 232 /* The lowest and highest voltage allowed for LS1088ARDB */
233 #define VDD_MV_MIN 819 233 #define VDD_MV_MIN 819
234 #define VDD_MV_MAX 1212 234 #define VDD_MV_MAX 1212
235 235
236 #define CONFIG_VOL_MONITOR_LTC3882_SET 236 #define CONFIG_VOL_MONITOR_LTC3882_SET
237 #define CONFIG_VOL_MONITOR_LTC3882_READ 237 #define CONFIG_VOL_MONITOR_LTC3882_READ
238 238
239 /* PM Bus commands code for LTC3882*/ 239 /* PM Bus commands code for LTC3882*/
240 #define PMBUS_CMD_PAGE 0x0 240 #define PMBUS_CMD_PAGE 0x0
241 #define PMBUS_CMD_READ_VOUT 0x8B 241 #define PMBUS_CMD_READ_VOUT 0x8B
242 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 242 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
243 #define PMBUS_CMD_VOUT_COMMAND 0x21 243 #define PMBUS_CMD_VOUT_COMMAND 0x21
244 244
245 #define PWM_CHANNEL0 0x0 245 #define PWM_CHANNEL0 0x0
246 246
247 /* 247 /*
248 * I2C bus multiplexer 248 * I2C bus multiplexer
249 */ 249 */
250 #define I2C_MUX_PCA_ADDR_PRI 0x77 250 #define I2C_MUX_PCA_ADDR_PRI 0x77
251 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 251 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
252 #define I2C_RETIMER_ADDR 0x18 252 #define I2C_RETIMER_ADDR 0x18
253 #define I2C_MUX_CH_DEFAULT 0x8 253 #define I2C_MUX_CH_DEFAULT 0x8
254 #define I2C_MUX_CH5 0xD 254 #define I2C_MUX_CH5 0xD
255 255
256 #ifndef SPL_NO_RTC 256 #ifndef SPL_NO_RTC
257 /* 257 /*
258 * RTC configuration 258 * RTC configuration
259 */ 259 */
260 #define RTC 260 #define RTC
261 #define CONFIG_RTC_PCF8563 1 261 #define CONFIG_RTC_PCF8563 1
262 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 262 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
263 #define CONFIG_CMD_DATE 263 #define CONFIG_CMD_DATE
264 #endif 264 #endif
265 265
266 /* EEPROM */ 266 /* EEPROM */
267 #define CONFIG_ID_EEPROM 267 #define CONFIG_ID_EEPROM
268 #define CONFIG_SYS_I2C_EEPROM_NXID 268 #define CONFIG_SYS_I2C_EEPROM_NXID
269 #define CONFIG_SYS_EEPROM_BUS_NUM 0 269 #define CONFIG_SYS_EEPROM_BUS_NUM 0
270 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 270 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
271 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 271 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
272 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 272 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
273 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 273 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
274 274
275 #ifndef SPL_NO_QSPI 275 #ifndef SPL_NO_QSPI
276 /* QSPI device */ 276 /* QSPI device */
277 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 277 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
278 #define CONFIG_FSL_QSPI
279 #define FSL_QSPI_FLASH_SIZE (1 << 26) 278 #define FSL_QSPI_FLASH_SIZE (1 << 26)
280 #define FSL_QSPI_FLASH_NUM 2 279 #define FSL_QSPI_FLASH_NUM 2
281 #endif 280 #endif
282 #endif 281 #endif
283 282
284 #define CONFIG_CMD_MEMINFO 283 #define CONFIG_CMD_MEMINFO
285 #define CONFIG_SYS_MEMTEST_START 0x80000000 284 #define CONFIG_SYS_MEMTEST_START 0x80000000
286 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 285 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
287 286
288 #ifdef CONFIG_SPL_BUILD 287 #ifdef CONFIG_SPL_BUILD
289 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 288 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
290 #else 289 #else
291 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 290 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
292 #endif 291 #endif
293 292
294 #define CONFIG_FSL_MEMAC 293 #define CONFIG_FSL_MEMAC
295 294
296 #ifndef SPL_NO_ENV 295 #ifndef SPL_NO_ENV
297 /* Initial environment variables */ 296 /* Initial environment variables */
298 #if defined(CONFIG_QSPI_BOOT) 297 #if defined(CONFIG_QSPI_BOOT)
299 #define MC_INIT_CMD \ 298 #define MC_INIT_CMD \
300 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 299 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
301 "sf read 0x80100000 0xE00000 0x100000;" \ 300 "sf read 0x80100000 0xE00000 0x100000;" \
302 "env exists secureboot && " \ 301 "env exists secureboot && " \
303 "sf read 0x80700000 0x700000 0x40000 && " \ 302 "sf read 0x80700000 0x700000 0x40000 && " \
304 "sf read 0x80740000 0x740000 0x40000 && " \ 303 "sf read 0x80740000 0x740000 0x40000 && " \
305 "esbc_validate 0x80700000 && " \ 304 "esbc_validate 0x80700000 && " \
306 "esbc_validate 0x80740000 ;" \ 305 "esbc_validate 0x80740000 ;" \
307 "fsl_mc start mc 0x80000000 0x80100000\0" \ 306 "fsl_mc start mc 0x80000000 0x80100000\0" \
308 "mcmemsize=0x70000000\0" 307 "mcmemsize=0x70000000\0"
309 #elif defined(CONFIG_SD_BOOT) 308 #elif defined(CONFIG_SD_BOOT)
310 #define MC_INIT_CMD \ 309 #define MC_INIT_CMD \
311 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 310 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
312 "mmc read 0x80100000 0x7000 0x800;" \ 311 "mmc read 0x80100000 0x7000 0x800;" \
313 "env exists secureboot && " \ 312 "env exists secureboot && " \
314 "mmc read 0x80700000 0x3800 0x10 && " \ 313 "mmc read 0x80700000 0x3800 0x10 && " \
315 "mmc read 0x80740000 0x3A00 0x10 && " \ 314 "mmc read 0x80740000 0x3A00 0x10 && " \
316 "esbc_validate 0x80700000 && " \ 315 "esbc_validate 0x80700000 && " \
317 "esbc_validate 0x80740000 ;" \ 316 "esbc_validate 0x80740000 ;" \
318 "fsl_mc start mc 0x80000000 0x80100000\0" \ 317 "fsl_mc start mc 0x80000000 0x80100000\0" \
319 "mcmemsize=0x70000000\0" 318 "mcmemsize=0x70000000\0"
320 #endif 319 #endif
321 320
322 #undef CONFIG_EXTRA_ENV_SETTINGS 321 #undef CONFIG_EXTRA_ENV_SETTINGS
323 #define CONFIG_EXTRA_ENV_SETTINGS \ 322 #define CONFIG_EXTRA_ENV_SETTINGS \
324 "BOARD=ls1088ardb\0" \ 323 "BOARD=ls1088ardb\0" \
325 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 324 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
326 "ramdisk_addr=0x800000\0" \ 325 "ramdisk_addr=0x800000\0" \
327 "ramdisk_size=0x2000000\0" \ 326 "ramdisk_size=0x2000000\0" \
328 "fdt_high=0xa0000000\0" \ 327 "fdt_high=0xa0000000\0" \
329 "initrd_high=0xffffffffffffffff\0" \ 328 "initrd_high=0xffffffffffffffff\0" \
330 "fdt_addr=0x64f00000\0" \ 329 "fdt_addr=0x64f00000\0" \
331 "kernel_addr=0x1000000\0" \ 330 "kernel_addr=0x1000000\0" \
332 "kernel_addr_sd=0x8000\0" \ 331 "kernel_addr_sd=0x8000\0" \
333 "kernelhdr_addr_sd=0x4000\0" \ 332 "kernelhdr_addr_sd=0x4000\0" \
334 "kernel_start=0x580100000\0" \ 333 "kernel_start=0x580100000\0" \
335 "kernelheader_start=0x580800000\0" \ 334 "kernelheader_start=0x580800000\0" \
336 "scriptaddr=0x80000000\0" \ 335 "scriptaddr=0x80000000\0" \
337 "scripthdraddr=0x80080000\0" \ 336 "scripthdraddr=0x80080000\0" \
338 "fdtheader_addr_r=0x80100000\0" \ 337 "fdtheader_addr_r=0x80100000\0" \
339 "kernelheader_addr=0x800000\0" \ 338 "kernelheader_addr=0x800000\0" \
340 "kernelheader_addr_r=0x80200000\0" \ 339 "kernelheader_addr_r=0x80200000\0" \
341 "kernel_addr_r=0x81000000\0" \ 340 "kernel_addr_r=0x81000000\0" \
342 "kernelheader_size=0x40000\0" \ 341 "kernelheader_size=0x40000\0" \
343 "fdt_addr_r=0x90000000\0" \ 342 "fdt_addr_r=0x90000000\0" \
344 "load_addr=0xa0000000\0" \ 343 "load_addr=0xa0000000\0" \
345 "kernel_size=0x2800000\0" \ 344 "kernel_size=0x2800000\0" \
346 "kernel_size_sd=0x14000\0" \ 345 "kernel_size_sd=0x14000\0" \
347 "kernelhdr_size_sd=0x10\0" \ 346 "kernelhdr_size_sd=0x10\0" \
348 MC_INIT_CMD \ 347 MC_INIT_CMD \
349 BOOTENV \ 348 BOOTENV \
350 "boot_scripts=ls1088ardb_boot.scr\0" \ 349 "boot_scripts=ls1088ardb_boot.scr\0" \
351 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \ 350 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
352 "scan_dev_for_boot_part=" \ 351 "scan_dev_for_boot_part=" \
353 "part list ${devtype} ${devnum} devplist; " \ 352 "part list ${devtype} ${devnum} devplist; " \
354 "env exists devplist || setenv devplist 1; " \ 353 "env exists devplist || setenv devplist 1; " \
355 "for distro_bootpart in ${devplist}; do " \ 354 "for distro_bootpart in ${devplist}; do " \
356 "if fstype ${devtype} " \ 355 "if fstype ${devtype} " \
357 "${devnum}:${distro_bootpart} " \ 356 "${devnum}:${distro_bootpart} " \
358 "bootfstype; then " \ 357 "bootfstype; then " \
359 "run scan_dev_for_boot; " \ 358 "run scan_dev_for_boot; " \
360 "fi; " \ 359 "fi; " \
361 "done\0" \ 360 "done\0" \
362 "scan_dev_for_boot=" \ 361 "scan_dev_for_boot=" \
363 "echo Scanning ${devtype} " \ 362 "echo Scanning ${devtype} " \
364 "${devnum}:${distro_bootpart}...; " \ 363 "${devnum}:${distro_bootpart}...; " \
365 "for prefix in ${boot_prefixes}; do " \ 364 "for prefix in ${boot_prefixes}; do " \
366 "run scan_dev_for_scripts; " \ 365 "run scan_dev_for_scripts; " \
367 "done;\0" \ 366 "done;\0" \
368 "boot_a_script=" \ 367 "boot_a_script=" \
369 "load ${devtype} ${devnum}:${distro_bootpart} " \ 368 "load ${devtype} ${devnum}:${distro_bootpart} " \
370 "${scriptaddr} ${prefix}${script}; " \ 369 "${scriptaddr} ${prefix}${script}; " \
371 "env exists secureboot && load ${devtype} " \ 370 "env exists secureboot && load ${devtype} " \
372 "${devnum}:${distro_bootpart} " \ 371 "${devnum}:${distro_bootpart} " \
373 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 372 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
374 "&& esbc_validate ${scripthdraddr};" \ 373 "&& esbc_validate ${scripthdraddr};" \
375 "source ${scriptaddr}\0" \ 374 "source ${scriptaddr}\0" \
376 "installer=load mmc 0:2 $load_addr " \ 375 "installer=load mmc 0:2 $load_addr " \
377 "/flex_installer_arm64.itb; " \ 376 "/flex_installer_arm64.itb; " \
378 "env exists mcinitcmd && run mcinitcmd && " \ 377 "env exists mcinitcmd && run mcinitcmd && " \
379 "mmc read 0x80001000 0x6800 0x800;" \ 378 "mmc read 0x80001000 0x6800 0x800;" \
380 "fsl_mc lazyapply dpl 0x80001000;" \ 379 "fsl_mc lazyapply dpl 0x80001000;" \
381 "bootm $load_addr#ls1088ardb\0" \ 380 "bootm $load_addr#ls1088ardb\0" \
382 "qspi_bootcmd=echo Trying load from qspi..;" \ 381 "qspi_bootcmd=echo Trying load from qspi..;" \
383 "sf probe && sf read $load_addr " \ 382 "sf probe && sf read $load_addr " \
384 "$kernel_addr $kernel_size ; env exists secureboot " \ 383 "$kernel_addr $kernel_size ; env exists secureboot " \
385 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 384 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
386 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 385 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
387 "bootm $load_addr#$BOARD\0" \ 386 "bootm $load_addr#$BOARD\0" \
388 "sd_bootcmd=echo Trying load from sd card..;" \ 387 "sd_bootcmd=echo Trying load from sd card..;" \
389 "mmcinfo; mmc read $load_addr " \ 388 "mmcinfo; mmc read $load_addr " \
390 "$kernel_addr_sd $kernel_size_sd ;" \ 389 "$kernel_addr_sd $kernel_size_sd ;" \
391 "env exists secureboot && mmc read $kernelheader_addr_r "\ 390 "env exists secureboot && mmc read $kernelheader_addr_r "\
392 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 391 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
393 " && esbc_validate ${kernelheader_addr_r};" \ 392 " && esbc_validate ${kernelheader_addr_r};" \
394 "bootm $load_addr#$BOARD\0" 393 "bootm $load_addr#$BOARD\0"
395 394
396 #undef CONFIG_BOOTCOMMAND 395 #undef CONFIG_BOOTCOMMAND
397 #if defined(CONFIG_QSPI_BOOT) 396 #if defined(CONFIG_QSPI_BOOT)
398 /* Try to boot an on-QSPI kernel first, then do normal distro boot */ 397 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
399 #define CONFIG_BOOTCOMMAND \ 398 #define CONFIG_BOOTCOMMAND \
400 "sf read 0x80001000 0xd00000 0x100000;" \ 399 "sf read 0x80001000 0xd00000 0x100000;" \
401 "env exists mcinitcmd && env exists secureboot " \ 400 "env exists mcinitcmd && env exists secureboot " \
402 " && sf read 0x80780000 0x780000 0x100000 " \ 401 " && sf read 0x80780000 0x780000 0x100000 " \
403 "&& esbc_validate 0x80780000;env exists mcinitcmd " \ 402 "&& esbc_validate 0x80780000;env exists mcinitcmd " \
404 "&& fsl_mc lazyapply dpl 0x80001000;" \ 403 "&& fsl_mc lazyapply dpl 0x80001000;" \
405 "run distro_bootcmd;run qspi_bootcmd;" \ 404 "run distro_bootcmd;run qspi_bootcmd;" \
406 "env exists secureboot && esbc_halt;" 405 "env exists secureboot && esbc_halt;"
407 406
408 /* Try to boot an on-SD kernel first, then do normal distro boot */ 407 /* Try to boot an on-SD kernel first, then do normal distro boot */
409 #elif defined(CONFIG_SD_BOOT) 408 #elif defined(CONFIG_SD_BOOT)
410 #define CONFIG_BOOTCOMMAND \ 409 #define CONFIG_BOOTCOMMAND \
411 "env exists mcinitcmd && mmcinfo; " \ 410 "env exists mcinitcmd && mmcinfo; " \
412 "mmc read 0x80001000 0x6800 0x800; " \ 411 "mmc read 0x80001000 0x6800 0x800; " \
413 "env exists mcinitcmd && env exists secureboot " \ 412 "env exists mcinitcmd && env exists secureboot " \
414 " && mmc read 0x80780000 0x3C00 0x10 " \ 413 " && mmc read 0x80780000 0x3C00 0x10 " \
415 "&& esbc_validate 0x80780000;env exists mcinitcmd " \ 414 "&& esbc_validate 0x80780000;env exists mcinitcmd " \
416 "&& fsl_mc lazyapply dpl 0x80001000;" \ 415 "&& fsl_mc lazyapply dpl 0x80001000;" \
417 "run distro_bootcmd;run sd_bootcmd;" \ 416 "run distro_bootcmd;run sd_bootcmd;" \
418 "env exists secureboot && esbc_halt;" 417 "env exists secureboot && esbc_halt;"
419 #endif 418 #endif
420 419
421 /* MAC/PHY configuration */ 420 /* MAC/PHY configuration */
422 #ifdef CONFIG_FSL_MC_ENET 421 #ifdef CONFIG_FSL_MC_ENET
423 #define CONFIG_PHYLIB 422 #define CONFIG_PHYLIB
424 423
425 #define CONFIG_PHY_VITESSE 424 #define CONFIG_PHY_VITESSE
426 #define AQ_PHY_ADDR1 0x00 425 #define AQ_PHY_ADDR1 0x00
427 #define AQR105_IRQ_MASK 0x00000004 426 #define AQR105_IRQ_MASK 0x00000004
428 427
429 #define QSGMII1_PORT1_PHY_ADDR 0x0c 428 #define QSGMII1_PORT1_PHY_ADDR 0x0c
430 #define QSGMII1_PORT2_PHY_ADDR 0x0d 429 #define QSGMII1_PORT2_PHY_ADDR 0x0d
431 #define QSGMII1_PORT3_PHY_ADDR 0x0e 430 #define QSGMII1_PORT3_PHY_ADDR 0x0e
432 #define QSGMII1_PORT4_PHY_ADDR 0x0f 431 #define QSGMII1_PORT4_PHY_ADDR 0x0f
433 #define QSGMII2_PORT1_PHY_ADDR 0x1c 432 #define QSGMII2_PORT1_PHY_ADDR 0x1c
434 #define QSGMII2_PORT2_PHY_ADDR 0x1d 433 #define QSGMII2_PORT2_PHY_ADDR 0x1d
435 #define QSGMII2_PORT3_PHY_ADDR 0x1e 434 #define QSGMII2_PORT3_PHY_ADDR 0x1e
436 #define QSGMII2_PORT4_PHY_ADDR 0x1f 435 #define QSGMII2_PORT4_PHY_ADDR 0x1f
437 436
438 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 437 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
439 #define CONFIG_PHY_GIGE 438 #define CONFIG_PHY_GIGE
440 #endif 439 #endif
441 #endif 440 #endif
442 441
443 /* MMC */ 442 /* MMC */
444 #ifdef CONFIG_MMC 443 #ifdef CONFIG_MMC
445 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 444 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
446 #endif 445 #endif
447 446
448 #ifndef SPL_NO_ENV 447 #ifndef SPL_NO_ENV
449 448
450 #define BOOT_TARGET_DEVICES(func) \ 449 #define BOOT_TARGET_DEVICES(func) \
451 func(MMC, mmc, 0) \ 450 func(MMC, mmc, 0) \
452 func(SCSI, scsi, 0) 451 func(SCSI, scsi, 0)
453 #include <config_distro_bootcmd.h> 452 #include <config_distro_bootcmd.h>
454 #endif 453 #endif
455 454
456 #include <asm/fsl_secure_boot.h> 455 #include <asm/fsl_secure_boot.h>
457 456
458 #endif /* __LS1088A_RDB_H */ 457 #endif /* __LS1088A_RDB_H */
459 458