Eric Lee / smarc-uboot

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Commit 4d0da8e30cf0b3b86ef1b48315e2cd8d14e5ea10

Authored by Ye Li
1 parent 6ec7af8eed
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

MLK-25291-3 imx8mq_evk: Applying default LPDDR4 script for B2 

Both i.MX8MQ B1 and B2 should use default LPDDR4 script, while B0
has another dedicated script.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 2beb72ddfd5416be7d8fa6e9fb36b1e29a0f0cb7)

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

board/freescale/imx8mq_evk/spl.c
Diff comments   View file @ 4d0da8e
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2018 NXP 3 * Copyright 2018 NXP
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <cpu_func.h> 9 #include <cpu_func.h>
10 #include <hang.h> 10 #include <hang.h>
11 #include <asm/io.h> 11 #include <asm/io.h>
12 #include <errno.h> 12 #include <errno.h>
13 #include <asm/io.h> 13 #include <asm/io.h>
14 #include <asm/arch/ddr.h> 14 #include <asm/arch/ddr.h>
15 #include <asm/arch/imx8mq_pins.h> 15 #include <asm/arch/imx8mq_pins.h>
16 #include <asm/arch/sys_proto.h> 16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/clock.h> 17 #include <asm/arch/clock.h>
18 #include <asm/mach-imx/iomux-v3.h> 18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/gpio.h> 19 #include <asm/mach-imx/gpio.h>
20 #include <asm/mach-imx/mxc_i2c.h> 20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <fsl_esdhc_imx.h> 21 #include <fsl_esdhc_imx.h>
22 #include <mmc.h> 22 #include <mmc.h>
23 #include <power/pmic.h> 23 #include <power/pmic.h>
24 #include <power/pfuze100_pmic.h> 24 #include <power/pfuze100_pmic.h>
25 #include <spl.h> 25 #include <spl.h>
26 #include "../common/pfuze.h" 26 #include "../common/pfuze.h"
27 27
28 DECLARE_GLOBAL_DATA_PTR; 28 DECLARE_GLOBAL_DATA_PTR;
29 29
30 extern struct dram_timing_info dram_timing_b0; 30 extern struct dram_timing_info dram_timing_b0;
31 31
32 static void spl_dram_init(void) 32 static void spl_dram_init(void)
33 { 33 {
34 /* ddr init */ 34 /* ddr init */
35 if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1) 35 if (soc_rev() >= CHIP_REV_2_1)
36 ddr_init(&dram_timing); 36 ddr_init(&dram_timing);
37 else 37 else
38 ddr_init(&dram_timing_b0); 38 ddr_init(&dram_timing_b0);
39 } 39 }
40 40
41 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) 41 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
42 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 42 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
43 static struct i2c_pads_info i2c_pad_info1 = { 43 static struct i2c_pads_info i2c_pad_info1 = {
44 .scl = { 44 .scl = {
45 .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, 45 .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
46 .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, 46 .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
47 .gp = IMX_GPIO_NR(5, 14), 47 .gp = IMX_GPIO_NR(5, 14),
48 }, 48 },
49 .sda = { 49 .sda = {
50 .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, 50 .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
51 .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, 51 .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
52 .gp = IMX_GPIO_NR(5, 15), 52 .gp = IMX_GPIO_NR(5, 15),
53 }, 53 },
54 }; 54 };
55 55
56 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) 56 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
57 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) 57 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
58 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) 58 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
59 59
60 int board_mmc_getcd(struct mmc *mmc) 60 int board_mmc_getcd(struct mmc *mmc)
61 { 61 {
62 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 62 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
63 int ret = 0; 63 int ret = 0;
64 64
65 switch (cfg->esdhc_base) { 65 switch (cfg->esdhc_base) {
66 case USDHC1_BASE_ADDR: 66 case USDHC1_BASE_ADDR:
67 ret = 1; 67 ret = 1;
68 break; 68 break;
69 case USDHC2_BASE_ADDR: 69 case USDHC2_BASE_ADDR:
70 ret = !gpio_get_value(USDHC2_CD_GPIO); 70 ret = !gpio_get_value(USDHC2_CD_GPIO);
71 return ret; 71 return ret;
72 } 72 }
73 73
74 return 1; 74 return 1;
75 } 75 }
76 76
77 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ 77 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
78 PAD_CTL_FSEL2) 78 PAD_CTL_FSEL2)
79 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) 79 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
80 80
81 static iomux_v3_cfg_t const usdhc1_pads[] = { 81 static iomux_v3_cfg_t const usdhc1_pads[] = {
82 IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 82 IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
83 IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 83 IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
84 IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 84 IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85 IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 85 IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 86 IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 87 IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 88 IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 89 IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 90 IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 91 IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 92 IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
93 }; 93 };
94 94
95 static iomux_v3_cfg_t const usdhc2_pads[] = { 95 static iomux_v3_cfg_t const usdhc2_pads[] = {
96 IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ 96 IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
97 IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ 97 IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
98 IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ 98 IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
99 IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ 99 IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
100 IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ 100 IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
101 IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ 101 IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
102 IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), 102 IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
103 IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), 103 IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
104 }; 104 };
105 105
106 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 106 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
107 {USDHC1_BASE_ADDR, 0, 8}, 107 {USDHC1_BASE_ADDR, 0, 8},
108 {USDHC2_BASE_ADDR, 0, 4}, 108 {USDHC2_BASE_ADDR, 0, 4},
109 }; 109 };
110 110
111 int board_mmc_init(bd_t *bis) 111 int board_mmc_init(bd_t *bis)
112 { 112 {
113 int i, ret; 113 int i, ret;
114 /* 114 /*
115 * According to the board_mmc_init() the following map is done: 115 * According to the board_mmc_init() the following map is done:
116 * (U-Boot device node) (Physical Port) 116 * (U-Boot device node) (Physical Port)
117 * mmc0 USDHC1 117 * mmc0 USDHC1
118 * mmc1 USDHC2 118 * mmc1 USDHC2
119 */ 119 */
120 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 120 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
121 switch (i) { 121 switch (i) {
122 case 0: 122 case 0:
123 init_clk_usdhc(0); 123 init_clk_usdhc(0);
124 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 124 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
125 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, 125 imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
126 ARRAY_SIZE(usdhc1_pads)); 126 ARRAY_SIZE(usdhc1_pads));
127 gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); 127 gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
128 gpio_direction_output(USDHC1_PWR_GPIO, 0); 128 gpio_direction_output(USDHC1_PWR_GPIO, 0);
129 udelay(500); 129 udelay(500);
130 gpio_direction_output(USDHC1_PWR_GPIO, 1); 130 gpio_direction_output(USDHC1_PWR_GPIO, 1);
131 break; 131 break;
132 case 1: 132 case 1:
133 init_clk_usdhc(1); 133 init_clk_usdhc(1);
134 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 134 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
135 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, 135 imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
136 ARRAY_SIZE(usdhc2_pads)); 136 ARRAY_SIZE(usdhc2_pads));
137 gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); 137 gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
138 gpio_direction_output(USDHC2_PWR_GPIO, 0); 138 gpio_direction_output(USDHC2_PWR_GPIO, 0);
139 udelay(500); 139 udelay(500);
140 gpio_direction_output(USDHC2_PWR_GPIO, 1); 140 gpio_direction_output(USDHC2_PWR_GPIO, 1);
141 break; 141 break;
142 default: 142 default:
143 printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1); 143 printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
144 return -EINVAL; 144 return -EINVAL;
145 } 145 }
146 146
147 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 147 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
148 if (ret) 148 if (ret)
149 return ret; 149 return ret;
150 } 150 }
151 151
152 return 0; 152 return 0;
153 } 153 }
154 154
155 #ifdef CONFIG_POWER 155 #ifdef CONFIG_POWER
156 #define I2C_PMIC 0 156 #define I2C_PMIC 0
157 int power_init_board(void) 157 int power_init_board(void)
158 { 158 {
159 struct pmic *p; 159 struct pmic *p;
160 int ret; 160 int ret;
161 unsigned int reg; 161 unsigned int reg;
162 162
163 ret = power_pfuze100_init(I2C_PMIC); 163 ret = power_pfuze100_init(I2C_PMIC);
164 if (ret) 164 if (ret)
165 return -ENODEV; 165 return -ENODEV;
166 166
167 p = pmic_get("PFUZE100"); 167 p = pmic_get("PFUZE100");
168 ret = pmic_probe(p); 168 ret = pmic_probe(p);
169 if (ret) 169 if (ret)
170 return -ENODEV; 170 return -ENODEV;
171 171
172 pmic_reg_read(p, PFUZE100_DEVICEID, &reg); 172 pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
173 printf("PMIC: PFUZE100 ID=0x%02x\n", reg); 173 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
174 174
175 pmic_reg_read(p, PFUZE100_SW3AVOL, &reg); 175 pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
176 if ((reg & 0x3f) != 0x18) { 176 if ((reg & 0x3f) != 0x18) {
177 reg &= ~0x3f; 177 reg &= ~0x3f;
178 reg |= 0x18; 178 reg |= 0x18;
179 pmic_reg_write(p, PFUZE100_SW3AVOL, reg); 179 pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
180 } 180 }
181 181
182 ret = pfuze_mode_init(p, APS_PFM); 182 ret = pfuze_mode_init(p, APS_PFM);
183 if (ret < 0) 183 if (ret < 0)
184 return ret; 184 return ret;
185 185
186 /* set SW3A standby mode to off */ 186 /* set SW3A standby mode to off */
187 pmic_reg_read(p, PFUZE100_SW3AMODE, &reg); 187 pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
188 reg &= ~0xf; 188 reg &= ~0xf;
189 reg |= APS_OFF; 189 reg |= APS_OFF;
190 pmic_reg_write(p, PFUZE100_SW3AMODE, reg); 190 pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
191 191
192 return 0; 192 return 0;
193 } 193 }
194 #endif 194 #endif
195 195
196 void spl_board_init(void) 196 void spl_board_init(void)
197 { 197 {
198 #ifndef CONFIG_SPL_USB_SDP_SUPPORT 198 #ifndef CONFIG_SPL_USB_SDP_SUPPORT
199 /* Serial download mode */ 199 /* Serial download mode */
200 if (is_usb_boot()) { 200 if (is_usb_boot()) {
201 puts("Back to ROM, SDP\n"); 201 puts("Back to ROM, SDP\n");
202 restore_boot_params(); 202 restore_boot_params();
203 } 203 }
204 #endif 204 #endif
205 205
206 init_usb_clk(); 206 init_usb_clk();
207 207
208 puts("Normal Boot\n"); 208 puts("Normal Boot\n");
209 } 209 }
210 210
211 #ifdef CONFIG_SPL_LOAD_FIT 211 #ifdef CONFIG_SPL_LOAD_FIT
212 int board_fit_config_name_match(const char *name) 212 int board_fit_config_name_match(const char *name)
213 { 213 {
214 /* Just empty function now - can't decide what to choose */ 214 /* Just empty function now - can't decide what to choose */
215 debug("%s: %s\n", __func__, name); 215 debug("%s: %s\n", __func__, name);
216 216
217 return 0; 217 return 0;
218 } 218 }
219 #endif 219 #endif
220 220
221 void board_init_f(ulong dummy) 221 void board_init_f(ulong dummy)
222 { 222 {
223 int ret; 223 int ret;
224 224
225 /* Clear the BSS. */ 225 /* Clear the BSS. */
226 memset(__bss_start, 0, __bss_end - __bss_start); 226 memset(__bss_start, 0, __bss_end - __bss_start);
227 227
228 arch_cpu_init(); 228 arch_cpu_init();
229 229
230 init_uart_clk(0); 230 init_uart_clk(0);
231 231
232 board_early_init_f(); 232 board_early_init_f();
233 233
234 timer_init(); 234 timer_init();
235 235
236 preloader_console_init(); 236 preloader_console_init();
237 237
238 ret = spl_init(); 238 ret = spl_init();
239 if (ret) { 239 if (ret) {
240 debug("spl_init() failed: %d\n", ret); 240 debug("spl_init() failed: %d\n", ret);
241 hang(); 241 hang();
242 } 242 }
243 243
244 enable_tzc380(); 244 enable_tzc380();
245 245
246 /* Adjust pmic voltage to 1.0V for 800M */ 246 /* Adjust pmic voltage to 1.0V for 800M */
247 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 247 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
248 248
249 power_init_board(); 249 power_init_board();
250 250
251 /* DDR initialization */ 251 /* DDR initialization */
252 spl_dram_init(); 252 spl_dram_init();
253 253
254 board_init_r(NULL, 0); 254 board_init_r(NULL, 0);
255 } 255 }
256 256
257 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 257 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
258 { 258 {
259 puts ("resetting ...\n"); 259 puts ("resetting ...\n");
260 260
261 reset_cpu(WDOG1_BASE_ADDR); 261 reset_cpu(WDOG1_BASE_ADDR);
262 262
263 return 0; 263 return 0;
264 } 264 }
265 265