Eric Lee / smarc-uboot

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Commit 4daafb3509b1143e96b6f66cfb12e71396b900bc

Authored by Ye Li
1 parent 0ff7f22efa
Exists in smarc_8mm-imx_v2019.04_4.19.35_1.1.0 and in 1 other branch smarc_8m-imx_v2019.04_4.19.35_1.1.0

MLK-22853 DTS: imx: fix the regulator off-on-delay property 

The property was changed to "u-boot,off-on-delay-us" in u-boot fixed
regulator. Update the dts to use the new name

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit e68d12af8d17ae1017eacfc73b72ab999ef9837f)

Showing 16 changed files with 19 additions and 19 deletions Inline Diff

arch/arm/dts/fsl-imx8mm-ddr4-val.dts
Diff comments   View file @ 4daafb3
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2018 NXP 3 * Copyright 2018 NXP
4 */ 4 */
5 5
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include "fsl-imx8mm.dtsi" 9 #include "fsl-imx8mm.dtsi"
10 10
11 / { 11 / {
12 model = "FSL i.MX8MM DDR4 Validation board"; 12 model = "FSL i.MX8MM DDR4 Validation board";
13 compatible = "fsl,imx8mm-val", "fsl,imx8mm"; 13 compatible = "fsl,imx8mm-val", "fsl,imx8mm";
14 14
15 chosen { 15 chosen {
16 bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; 16 bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
17 stdout-patch = &uart2; 17 stdout-patch = &uart2;
18 }; 18 };
19 19
20 reg_usdhc2_vmmc: regulator-usdhc2 { 20 reg_usdhc2_vmmc: regulator-usdhc2 {
21 compatible = "regulator-fixed"; 21 compatible = "regulator-fixed";
22 regulator-name = "VSD_3V3"; 22 regulator-name = "VSD_3V3";
23 regulator-min-microvolt = <3300000>; 23 regulator-min-microvolt = <3300000>;
24 regulator-max-microvolt = <3300000>; 24 regulator-max-microvolt = <3300000>;
25 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 25 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
26 enable-active-high; 26 enable-active-high;
27 startup-delay-us = <100>; 27 startup-delay-us = <100>;
28 off-on-delay-us = <12000>; 28 u-boot,off-on-delay-us = <12000>;
29 }; 29 };
30 }; 30 };
31 31
32 &iomuxc { 32 &iomuxc {
33 pinctrl-names = "default"; 33 pinctrl-names = "default";
34 34
35 imx8mm-val { 35 imx8mm-val {
36 pinctrl_fec1: fec1grp { 36 pinctrl_fec1: fec1grp {
37 fsl,pins = < 37 fsl,pins = <
38 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 38 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
39 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 39 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
40 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 40 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
41 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 41 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
42 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 42 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
43 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 43 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
44 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 44 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
45 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 45 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
46 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 46 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
47 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 47 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
48 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 48 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
49 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 49 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
50 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 50 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
51 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 51 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
52 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 52 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
53 >; 53 >;
54 }; 54 };
55 55
56 pinctrl_flexspi: flexspigrp { 56 pinctrl_flexspi: flexspigrp {
57 fsl,pins = < 57 fsl,pins = <
58 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 58 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
59 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 59 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
60 60
61 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 61 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
62 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 62 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
63 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 63 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
64 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 64 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
65 >; 65 >;
66 }; 66 };
67 67
68 pinctrl_i2c1: i2c1grp { 68 pinctrl_i2c1: i2c1grp {
69 fsl,pins = < 69 fsl,pins = <
70 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 70 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
71 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 71 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
72 >; 72 >;
73 }; 73 };
74 74
75 pinctrl_i2c2: i2c2grp { 75 pinctrl_i2c2: i2c2grp {
76 fsl,pins = < 76 fsl,pins = <
77 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 77 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
78 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 78 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
79 >; 79 >;
80 }; 80 };
81 81
82 pinctrl_i2c3: i2c3grp { 82 pinctrl_i2c3: i2c3grp {
83 fsl,pins = < 83 fsl,pins = <
84 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 84 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
85 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 85 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
86 >; 86 >;
87 }; 87 };
88 88
89 pinctrl_i2c1_gpio: i2c1grp-gpio { 89 pinctrl_i2c1_gpio: i2c1grp-gpio {
90 fsl,pins = < 90 fsl,pins = <
91 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 91 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3
92 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 92 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3
93 >; 93 >;
94 }; 94 };
95 95
96 pinctrl_i2c2_gpio: i2c2grp-gpio { 96 pinctrl_i2c2_gpio: i2c2grp-gpio {
97 fsl,pins = < 97 fsl,pins = <
98 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 98 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
99 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 99 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
100 >; 100 >;
101 }; 101 };
102 102
103 pinctrl_i2c3_gpio: i2c3grp-gpio { 103 pinctrl_i2c3_gpio: i2c3grp-gpio {
104 fsl,pins = < 104 fsl,pins = <
105 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 105 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
106 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 106 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
107 >; 107 >;
108 }; 108 };
109 109
110 pinctrl_pmic: pmicirq { 110 pinctrl_pmic: pmicirq {
111 fsl,pins = < 111 fsl,pins = <
112 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 112 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
113 >; 113 >;
114 }; 114 };
115 115
116 pinctrl_uart2: uart1grp { 116 pinctrl_uart2: uart1grp {
117 fsl,pins = < 117 fsl,pins = <
118 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 118 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
119 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 119 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
120 >; 120 >;
121 }; 121 };
122 122
123 pinctrl_usdhc2_gpio: usdhc2grpgpio { 123 pinctrl_usdhc2_gpio: usdhc2grpgpio {
124 fsl,pins = < 124 fsl,pins = <
125 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 125 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
126 >; 126 >;
127 }; 127 };
128 128
129 pinctrl_usdhc2: usdhc2grp { 129 pinctrl_usdhc2: usdhc2grp {
130 fsl,pins = < 130 fsl,pins = <
131 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 131 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
132 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 132 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
133 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 133 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
134 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 134 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
135 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 135 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
136 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 136 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
137 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 137 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
138 >; 138 >;
139 }; 139 };
140 140
141 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 141 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
142 fsl,pins = < 142 fsl,pins = <
143 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 143 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
144 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 144 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
145 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 145 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
146 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 146 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
147 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 147 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
148 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 148 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
149 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 149 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
150 >; 150 >;
151 }; 151 };
152 152
153 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 153 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
154 fsl,pins = < 154 fsl,pins = <
155 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 155 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
156 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 156 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
157 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 157 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
158 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 158 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
159 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 159 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
160 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 160 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
161 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 161 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
162 >; 162 >;
163 }; 163 };
164 164
165 pinctrl_usdhc3: usdhc3grp { 165 pinctrl_usdhc3: usdhc3grp {
166 fsl,pins = < 166 fsl,pins = <
167 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 167 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
168 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 168 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
169 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 169 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
170 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 170 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
171 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 171 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
172 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 172 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
173 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 173 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
174 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 174 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
175 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 175 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
176 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 176 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
177 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 177 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
178 >; 178 >;
179 }; 179 };
180 180
181 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 181 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
182 fsl,pins = < 182 fsl,pins = <
183 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 183 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
184 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 184 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
185 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 185 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
186 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 186 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
187 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 187 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
188 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 188 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
189 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 189 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
190 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 190 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
191 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 191 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
192 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 192 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
193 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 193 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
194 >; 194 >;
195 }; 195 };
196 196
197 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 197 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
198 fsl,pins = < 198 fsl,pins = <
199 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 199 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
200 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 200 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
201 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 201 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
202 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 202 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
203 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 203 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
204 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 204 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
205 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 205 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
206 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 206 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
207 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 207 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
208 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 208 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
209 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 209 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
210 >; 210 >;
211 }; 211 };
212 212
213 pinctrl_wdog: wdoggrp { 213 pinctrl_wdog: wdoggrp {
214 fsl,pins = < 214 fsl,pins = <
215 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 215 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
216 >; 216 >;
217 }; 217 };
218 }; 218 };
219 }; 219 };
220 220
221 &i2c1 { 221 &i2c1 {
222 clock-frequency = <400000>; 222 clock-frequency = <400000>;
223 pinctrl-names = "default", "gpio"; 223 pinctrl-names = "default", "gpio";
224 pinctrl-0 = <&pinctrl_i2c1>; 224 pinctrl-0 = <&pinctrl_i2c1>;
225 pinctrl-1 = <&pinctrl_i2c1_gpio>; 225 pinctrl-1 = <&pinctrl_i2c1_gpio>;
226 scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; 226 scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
227 sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; 227 sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
228 status = "okay"; 228 status = "okay";
229 229
230 pmic: bd71837@4b { 230 pmic: bd71837@4b {
231 reg = <0x4b>; 231 reg = <0x4b>;
232 compatible = "rohm,bd71837"; 232 compatible = "rohm,bd71837";
233 /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ 233 /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */
234 pinctrl-0 = <&pinctrl_pmic>; 234 pinctrl-0 = <&pinctrl_pmic>;
235 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; 235 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
236 236
237 gpo { 237 gpo {
238 rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ 238 rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
239 }; 239 };
240 240
241 regulators { 241 regulators {
242 #address-cells = <1>; 242 #address-cells = <1>;
243 #size-cells = <0>; 243 #size-cells = <0>;
244 244
245 bd71837,pmic-buck2-uses-i2c-dvs; 245 bd71837,pmic-buck2-uses-i2c-dvs;
246 bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ 246 bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
247 247
248 buck1_reg: regulator@0 { 248 buck1_reg: regulator@0 {
249 reg = <0>; 249 reg = <0>;
250 regulator-compatible = "buck1"; 250 regulator-compatible = "buck1";
251 regulator-min-microvolt = <700000>; 251 regulator-min-microvolt = <700000>;
252 regulator-max-microvolt = <1300000>; 252 regulator-max-microvolt = <1300000>;
253 regulator-boot-on; 253 regulator-boot-on;
254 regulator-always-on; 254 regulator-always-on;
255 regulator-ramp-delay = <1250>; 255 regulator-ramp-delay = <1250>;
256 }; 256 };
257 257
258 buck2_reg: regulator@1 { 258 buck2_reg: regulator@1 {
259 reg = <1>; 259 reg = <1>;
260 regulator-compatible = "buck2"; 260 regulator-compatible = "buck2";
261 regulator-min-microvolt = <700000>; 261 regulator-min-microvolt = <700000>;
262 regulator-max-microvolt = <1300000>; 262 regulator-max-microvolt = <1300000>;
263 regulator-boot-on; 263 regulator-boot-on;
264 regulator-always-on; 264 regulator-always-on;
265 regulator-ramp-delay = <1250>; 265 regulator-ramp-delay = <1250>;
266 }; 266 };
267 267
268 buck3_reg: regulator@2 { 268 buck3_reg: regulator@2 {
269 reg = <2>; 269 reg = <2>;
270 regulator-compatible = "buck3"; 270 regulator-compatible = "buck3";
271 regulator-min-microvolt = <700000>; 271 regulator-min-microvolt = <700000>;
272 regulator-max-microvolt = <1300000>; 272 regulator-max-microvolt = <1300000>;
273 }; 273 };
274 274
275 buck4_reg: regulator@3 { 275 buck4_reg: regulator@3 {
276 reg = <3>; 276 reg = <3>;
277 regulator-compatible = "buck4"; 277 regulator-compatible = "buck4";
278 regulator-min-microvolt = <700000>; 278 regulator-min-microvolt = <700000>;
279 regulator-max-microvolt = <1300000>; 279 regulator-max-microvolt = <1300000>;
280 }; 280 };
281 281
282 buck5_reg: regulator@4 { 282 buck5_reg: regulator@4 {
283 reg = <4>; 283 reg = <4>;
284 regulator-compatible = "buck5"; 284 regulator-compatible = "buck5";
285 regulator-min-microvolt = <700000>; 285 regulator-min-microvolt = <700000>;
286 regulator-max-microvolt = <1350000>; 286 regulator-max-microvolt = <1350000>;
287 regulator-boot-on; 287 regulator-boot-on;
288 regulator-always-on; 288 regulator-always-on;
289 }; 289 };
290 290
291 buck6_reg: regulator@5 { 291 buck6_reg: regulator@5 {
292 reg = <5>; 292 reg = <5>;
293 regulator-compatible = "buck6"; 293 regulator-compatible = "buck6";
294 regulator-min-microvolt = <3000000>; 294 regulator-min-microvolt = <3000000>;
295 regulator-max-microvolt = <3300000>; 295 regulator-max-microvolt = <3300000>;
296 regulator-boot-on; 296 regulator-boot-on;
297 regulator-always-on; 297 regulator-always-on;
298 }; 298 };
299 299
300 buck7_reg: regulator@6 { 300 buck7_reg: regulator@6 {
301 reg = <6>; 301 reg = <6>;
302 regulator-compatible = "buck7"; 302 regulator-compatible = "buck7";
303 regulator-min-microvolt = <1605000>; 303 regulator-min-microvolt = <1605000>;
304 regulator-max-microvolt = <1995000>; 304 regulator-max-microvolt = <1995000>;
305 regulator-boot-on; 305 regulator-boot-on;
306 regulator-always-on; 306 regulator-always-on;
307 }; 307 };
308 308
309 buck8_reg: regulator@7 { 309 buck8_reg: regulator@7 {
310 reg = <7>; 310 reg = <7>;
311 regulator-compatible = "buck8"; 311 regulator-compatible = "buck8";
312 regulator-min-microvolt = <800000>; 312 regulator-min-microvolt = <800000>;
313 regulator-max-microvolt = <1400000>; 313 regulator-max-microvolt = <1400000>;
314 regulator-boot-on; 314 regulator-boot-on;
315 regulator-always-on; 315 regulator-always-on;
316 }; 316 };
317 317
318 ldo1_reg: regulator@8 { 318 ldo1_reg: regulator@8 {
319 reg = <8>; 319 reg = <8>;
320 regulator-compatible = "ldo1"; 320 regulator-compatible = "ldo1";
321 regulator-min-microvolt = <3000000>; 321 regulator-min-microvolt = <3000000>;
322 regulator-max-microvolt = <3300000>; 322 regulator-max-microvolt = <3300000>;
323 regulator-boot-on; 323 regulator-boot-on;
324 regulator-always-on; 324 regulator-always-on;
325 }; 325 };
326 326
327 ldo2_reg: regulator@9 { 327 ldo2_reg: regulator@9 {
328 reg = <9>; 328 reg = <9>;
329 regulator-compatible = "ldo2"; 329 regulator-compatible = "ldo2";
330 regulator-min-microvolt = <900000>; 330 regulator-min-microvolt = <900000>;
331 regulator-max-microvolt = <900000>; 331 regulator-max-microvolt = <900000>;
332 regulator-boot-on; 332 regulator-boot-on;
333 regulator-always-on; 333 regulator-always-on;
334 }; 334 };
335 335
336 ldo3_reg: regulator@10 { 336 ldo3_reg: regulator@10 {
337 reg = <10>; 337 reg = <10>;
338 regulator-compatible = "ldo3"; 338 regulator-compatible = "ldo3";
339 regulator-min-microvolt = <1800000>; 339 regulator-min-microvolt = <1800000>;
340 regulator-max-microvolt = <3300000>; 340 regulator-max-microvolt = <3300000>;
341 regulator-boot-on; 341 regulator-boot-on;
342 regulator-always-on; 342 regulator-always-on;
343 }; 343 };
344 344
345 ldo4_reg: regulator@11 { 345 ldo4_reg: regulator@11 {
346 reg = <11>; 346 reg = <11>;
347 regulator-compatible = "ldo4"; 347 regulator-compatible = "ldo4";
348 regulator-min-microvolt = <900000>; 348 regulator-min-microvolt = <900000>;
349 regulator-max-microvolt = <1800000>; 349 regulator-max-microvolt = <1800000>;
350 regulator-boot-on; 350 regulator-boot-on;
351 regulator-always-on; 351 regulator-always-on;
352 }; 352 };
353 353
354 ldo5_reg: regulator@12 { 354 ldo5_reg: regulator@12 {
355 reg = <12>; 355 reg = <12>;
356 regulator-compatible = "ldo5"; 356 regulator-compatible = "ldo5";
357 regulator-min-microvolt = <1800000>; 357 regulator-min-microvolt = <1800000>;
358 regulator-max-microvolt = <3300000>; 358 regulator-max-microvolt = <3300000>;
359 }; 359 };
360 360
361 ldo6_reg: regulator@13 { 361 ldo6_reg: regulator@13 {
362 reg = <13>; 362 reg = <13>;
363 regulator-compatible = "ldo6"; 363 regulator-compatible = "ldo6";
364 regulator-min-microvolt = <900000>; 364 regulator-min-microvolt = <900000>;
365 regulator-max-microvolt = <1800000>; 365 regulator-max-microvolt = <1800000>;
366 regulator-boot-on; 366 regulator-boot-on;
367 regulator-always-on; 367 regulator-always-on;
368 }; 368 };
369 369
370 ldo7_reg: regulator@14 { 370 ldo7_reg: regulator@14 {
371 reg = <14>; 371 reg = <14>;
372 regulator-compatible = "ldo7"; 372 regulator-compatible = "ldo7";
373 regulator-min-microvolt = <1800000>; 373 regulator-min-microvolt = <1800000>;
374 regulator-max-microvolt = <3300000>; 374 regulator-max-microvolt = <3300000>;
375 }; 375 };
376 }; 376 };
377 }; 377 };
378 }; 378 };
379 379
380 &i2c2 { 380 &i2c2 {
381 clock-frequency = <400000>; 381 clock-frequency = <400000>;
382 pinctrl-names = "default", "gpio"; 382 pinctrl-names = "default", "gpio";
383 pinctrl-0 = <&pinctrl_i2c2>; 383 pinctrl-0 = <&pinctrl_i2c2>;
384 pinctrl-1 = <&pinctrl_i2c2_gpio>; 384 pinctrl-1 = <&pinctrl_i2c2_gpio>;
385 scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; 385 scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
386 sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; 386 sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
387 status = "okay"; 387 status = "okay";
388 388
389 typec_ptn5110_1: ptn5110@50 { 389 typec_ptn5110_1: ptn5110@50 {
390 compatible = "usb,tcpci"; 390 compatible = "usb,tcpci";
391 reg = <0x50>; 391 reg = <0x50>;
392 src-pdos = <0x380190c8>; 392 src-pdos = <0x380190c8>;
393 snk-pdos = <0x380190c8 0x3802d0c8>; 393 snk-pdos = <0x380190c8 0x3802d0c8>;
394 max-snk-mv = <9000>; 394 max-snk-mv = <9000>;
395 max-snk-ma = <2000>; 395 max-snk-ma = <2000>;
396 op-snk-mw = <9000>; 396 op-snk-mw = <9000>;
397 max-snk-mw = <18000>; 397 max-snk-mw = <18000>;
398 port-type = "drp"; 398 port-type = "drp";
399 default-role = "sink"; 399 default-role = "sink";
400 }; 400 };
401 401
402 typec_ptn5110_2: ptn5110@52 { 402 typec_ptn5110_2: ptn5110@52 {
403 compatible = "usb,tcpci"; 403 compatible = "usb,tcpci";
404 reg = <0x52>; 404 reg = <0x52>;
405 src-pdos = <0x380190c8>; 405 src-pdos = <0x380190c8>;
406 snk-pdos = <0x380190c8 0x3802d0c8>; 406 snk-pdos = <0x380190c8 0x3802d0c8>;
407 max-snk-mv = <9000>; 407 max-snk-mv = <9000>;
408 max-snk-ma = <2000>; 408 max-snk-ma = <2000>;
409 op-snk-mw = <9000>; 409 op-snk-mw = <9000>;
410 max-snk-mw = <18000>; 410 max-snk-mw = <18000>;
411 port-type = "drp"; 411 port-type = "drp";
412 default-role = "sink"; 412 default-role = "sink";
413 }; 413 };
414 }; 414 };
415 415
416 &i2c3 { 416 &i2c3 {
417 clock-frequency = <100000>; 417 clock-frequency = <100000>;
418 pinctrl-names = "default", "gpio"; 418 pinctrl-names = "default", "gpio";
419 pinctrl-0 = <&pinctrl_i2c3>; 419 pinctrl-0 = <&pinctrl_i2c3>;
420 pinctrl-1 = <&pinctrl_i2c3_gpio>; 420 pinctrl-1 = <&pinctrl_i2c3_gpio>;
421 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; 421 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
422 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; 422 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
423 status = "okay"; 423 status = "okay";
424 }; 424 };
425 425
426 &flexspi { 426 &flexspi {
427 pinctrl-names = "default"; 427 pinctrl-names = "default";
428 pinctrl-0 = <&pinctrl_flexspi>; 428 pinctrl-0 = <&pinctrl_flexspi>;
429 status = "okay"; 429 status = "okay";
430 430
431 flash0: n25q256a@0 { 431 flash0: n25q256a@0 {
432 reg = <0>; 432 reg = <0>;
433 #address-cells = <1>; 433 #address-cells = <1>;
434 #size-cells = <1>; 434 #size-cells = <1>;
435 compatible = "spi-flash"; 435 compatible = "spi-flash";
436 spi-max-frequency = <29000000>; 436 spi-max-frequency = <29000000>;
437 spi-nor,ddr-quad-read-dummy = <8>; 437 spi-nor,ddr-quad-read-dummy = <8>;
438 }; 438 };
439 }; 439 };
440 440
441 &fec1 { 441 &fec1 {
442 pinctrl-names = "default"; 442 pinctrl-names = "default";
443 pinctrl-0 = <&pinctrl_fec1>; 443 pinctrl-0 = <&pinctrl_fec1>;
444 phy-mode = "rgmii-id"; 444 phy-mode = "rgmii-id";
445 phy-handle = <&ethphy0>; 445 phy-handle = <&ethphy0>;
446 fsl,magic-packet; 446 fsl,magic-packet;
447 status = "okay"; 447 status = "okay";
448 448
449 mdio { 449 mdio {
450 #address-cells = <1>; 450 #address-cells = <1>;
451 #size-cells = <0>; 451 #size-cells = <0>;
452 452
453 ethphy0: ethernet-phy@0 { 453 ethphy0: ethernet-phy@0 {
454 compatible = "ethernet-phy-ieee802.3-c22"; 454 compatible = "ethernet-phy-ieee802.3-c22";
455 reg = <0>; 455 reg = <0>;
456 at803x,led-act-blind-workaround; 456 at803x,led-act-blind-workaround;
457 at803x,eee-okay; 457 at803x,eee-okay;
458 at803x,vddio-1p8v; 458 at803x,vddio-1p8v;
459 }; 459 };
460 }; 460 };
461 }; 461 };
462 462
463 &uart2 { /* console */ 463 &uart2 { /* console */
464 pinctrl-names = "default"; 464 pinctrl-names = "default";
465 pinctrl-0 = <&pinctrl_uart2>; 465 pinctrl-0 = <&pinctrl_uart2>;
466 status = "okay"; 466 status = "okay";
467 }; 467 };
468 468
469 &usdhc2 { 469 &usdhc2 {
470 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 470 pinctrl-names = "default", "state_100mhz", "state_200mhz";
471 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 471 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
472 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 472 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
473 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 473 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
474 bus-width = <4>; 474 bus-width = <4>;
475 non-removable; 475 non-removable;
476 vmmc-supply = <&reg_usdhc2_vmmc>; 476 vmmc-supply = <&reg_usdhc2_vmmc>;
477 status = "okay"; 477 status = "okay";
478 }; 478 };
479 479
480 &usdhc3 { 480 &usdhc3 {
481 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 481 pinctrl-names = "default", "state_100mhz", "state_200mhz";
482 pinctrl-0 = <&pinctrl_usdhc3>; 482 pinctrl-0 = <&pinctrl_usdhc3>;
483 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 483 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
484 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 484 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
485 bus-width = <8>; 485 bus-width = <8>;
486 non-removable; 486 non-removable;
487 status = "okay"; 487 status = "okay";
488 }; 488 };
489 489
490 &wdog1 { 490 &wdog1 {
491 pinctrl-names = "default"; 491 pinctrl-names = "default";
492 pinctrl-0 = <&pinctrl_wdog>; 492 pinctrl-0 = <&pinctrl_wdog>;
493 fsl,ext-reset-output; 493 fsl,ext-reset-output;
494 status = "okay"; 494 status = "okay";
495 }; 495 };
496 496
497 &A53_0 { 497 &A53_0 {
498 arm-supply = <&buck2_reg>; 498 arm-supply = <&buck2_reg>;
499 }; 499 };
500 500
501 &usbotg1 { 501 &usbotg1 {
502 status = "okay"; 502 status = "okay";
503 extcon = <&typec_ptn5110_1>; 503 extcon = <&typec_ptn5110_1>;
504 }; 504 };
505 505
506 &usbotg2 { 506 &usbotg2 {
507 status = "okay"; 507 status = "okay";
508 extcon = <&typec_ptn5110_2>; 508 extcon = <&typec_ptn5110_2>;
509 }; 509 };
510 510
arch/arm/dts/fsl-imx8mm-evk.dts
Diff comments   View file @ 4daafb3
1 /* 1 /*
2 * Copyright 2018 NXP 2 * Copyright 2018 NXP
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2 6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version. 7 * of the License, or (at your option) any later version.
8 * 8 *
9 * This program is distributed in the hope that it will be useful, 9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 */ 13 */
14 14
15 /dts-v1/; 15 /dts-v1/;
16 16
17 #include "fsl-imx8mm.dtsi" 17 #include "fsl-imx8mm.dtsi"
18 18
19 / { 19 / {
20 model = "FSL i.MX8MM EVK board"; 20 model = "FSL i.MX8MM EVK board";
21 compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; 21 compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
22 22
23 chosen { 23 chosen {
24 bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; 24 bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
25 stdout-patch = &uart2; 25 stdout-patch = &uart2;
26 }; 26 };
27 27
28 firmware { 28 firmware {
29 optee { 29 optee {
30 compatible = "linaro,optee-tz"; 30 compatible = "linaro,optee-tz";
31 method = "smc"; 31 method = "smc";
32 }; 32 };
33 }; 33 };
34 34
35 reg_usdhc2_vmmc: regulator-usdhc2 { 35 reg_usdhc2_vmmc: regulator-usdhc2 {
36 compatible = "regulator-fixed"; 36 compatible = "regulator-fixed";
37 regulator-name = "VSD_3V3"; 37 regulator-name = "VSD_3V3";
38 regulator-min-microvolt = <3300000>; 38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>;
40 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 40 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
41 enable-active-high; 41 enable-active-high;
42 startup-delay-us = <100>; 42 startup-delay-us = <100>;
43 off-on-delay-us = <12000>; 43 u-boot,off-on-delay-us = <12000>;
44 }; 44 };
45 }; 45 };
46 46
47 &iomuxc { 47 &iomuxc {
48 pinctrl-names = "default"; 48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_hog_1>; 49 pinctrl-0 = <&pinctrl_hog_1>;
50 50
51 imx8mm-evk { 51 imx8mm-evk {
52 pinctrl_hog_1: hoggrp-1 { 52 pinctrl_hog_1: hoggrp-1 {
53 fsl,pins = < 53 fsl,pins = <
54 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 54 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
55 >; 55 >;
56 }; 56 };
57 57
58 pinctrl_fec1: fec1grp { 58 pinctrl_fec1: fec1grp {
59 fsl,pins = < 59 fsl,pins = <
60 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 60 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
61 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 61 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
62 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 62 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
63 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 63 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
64 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 64 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
65 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 65 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
66 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 66 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
67 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 67 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
68 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 68 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
69 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 69 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
70 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 70 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
71 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 71 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
72 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 72 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
73 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 73 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
74 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 74 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
75 >; 75 >;
76 }; 76 };
77 77
78 pinctrl_flexspi: flexspigrp { 78 pinctrl_flexspi: flexspigrp {
79 fsl,pins = < 79 fsl,pins = <
80 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 80 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
81 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 81 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
82 82
83 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 83 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
84 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 84 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
85 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 85 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
86 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 86 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
87 >; 87 >;
88 }; 88 };
89 89
90 pinctrl_i2c1: i2c1grp { 90 pinctrl_i2c1: i2c1grp {
91 fsl,pins = < 91 fsl,pins = <
92 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 92 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
93 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 93 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
94 >; 94 >;
95 }; 95 };
96 96
97 pinctrl_i2c2: i2c2grp { 97 pinctrl_i2c2: i2c2grp {
98 fsl,pins = < 98 fsl,pins = <
99 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 99 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
100 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 100 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
101 >; 101 >;
102 }; 102 };
103 103
104 pinctrl_i2c3: i2c3grp { 104 pinctrl_i2c3: i2c3grp {
105 fsl,pins = < 105 fsl,pins = <
106 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 106 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
107 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 107 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
108 >; 108 >;
109 }; 109 };
110 110
111 pinctrl_i2c1_gpio: i2c1grp-gpio { 111 pinctrl_i2c1_gpio: i2c1grp-gpio {
112 fsl,pins = < 112 fsl,pins = <
113 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 113 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3
114 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 114 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3
115 >; 115 >;
116 }; 116 };
117 117
118 pinctrl_i2c2_gpio: i2c2grp-gpio { 118 pinctrl_i2c2_gpio: i2c2grp-gpio {
119 fsl,pins = < 119 fsl,pins = <
120 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 120 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
121 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 121 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
122 >; 122 >;
123 }; 123 };
124 124
125 pinctrl_i2c3_gpio: i2c3grp-gpio { 125 pinctrl_i2c3_gpio: i2c3grp-gpio {
126 fsl,pins = < 126 fsl,pins = <
127 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 127 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
128 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 128 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
129 >; 129 >;
130 }; 130 };
131 131
132 pinctrl_pmic: pmicirq { 132 pinctrl_pmic: pmicirq {
133 fsl,pins = < 133 fsl,pins = <
134 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 134 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
135 >; 135 >;
136 }; 136 };
137 137
138 pinctrl_uart2: uart1grp { 138 pinctrl_uart2: uart1grp {
139 fsl,pins = < 139 fsl,pins = <
140 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 140 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
141 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 141 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
142 >; 142 >;
143 }; 143 };
144 144
145 pinctrl_usdhc2_gpio: usdhc2grpgpio { 145 pinctrl_usdhc2_gpio: usdhc2grpgpio {
146 fsl,pins = < 146 fsl,pins = <
147 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 147 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
148 >; 148 >;
149 }; 149 };
150 150
151 pinctrl_usdhc2: usdhc2grp { 151 pinctrl_usdhc2: usdhc2grp {
152 fsl,pins = < 152 fsl,pins = <
153 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 153 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
154 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 154 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
155 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 155 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
156 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 156 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
157 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 157 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
158 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 158 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
159 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 159 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
160 >; 160 >;
161 }; 161 };
162 162
163 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 163 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
164 fsl,pins = < 164 fsl,pins = <
165 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 165 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
166 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 166 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
167 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 167 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
168 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 168 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
169 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 169 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
170 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 170 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
171 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 171 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
172 >; 172 >;
173 }; 173 };
174 174
175 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 175 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
176 fsl,pins = < 176 fsl,pins = <
177 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 177 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
178 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 178 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
179 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 179 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
180 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 180 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
181 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 181 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
182 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 182 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
183 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 183 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
184 >; 184 >;
185 }; 185 };
186 186
187 pinctrl_usdhc3: usdhc3grp { 187 pinctrl_usdhc3: usdhc3grp {
188 fsl,pins = < 188 fsl,pins = <
189 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 189 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
190 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 190 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
191 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 191 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
192 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 192 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
193 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 193 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
194 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 194 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
195 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 195 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
196 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 196 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
197 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 197 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
198 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 198 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
199 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 199 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
200 >; 200 >;
201 }; 201 };
202 202
203 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 203 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
204 fsl,pins = < 204 fsl,pins = <
205 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 205 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
206 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 206 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
207 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 207 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
208 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 208 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
209 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 209 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
210 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 210 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
211 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 211 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
212 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 212 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
213 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 213 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
214 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 214 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
215 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 215 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
216 >; 216 >;
217 }; 217 };
218 218
219 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 219 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
220 fsl,pins = < 220 fsl,pins = <
221 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 221 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
222 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 222 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
223 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 223 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
224 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 224 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
225 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 225 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
226 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 226 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
227 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 227 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
228 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 228 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
229 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 229 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
230 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 230 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
231 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 231 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
232 >; 232 >;
233 }; 233 };
234 234
235 pinctrl_wdog: wdoggrp { 235 pinctrl_wdog: wdoggrp {
236 fsl,pins = < 236 fsl,pins = <
237 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 237 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
238 >; 238 >;
239 }; 239 };
240 }; 240 };
241 }; 241 };
242 242
243 &i2c1 { 243 &i2c1 {
244 clock-frequency = <400000>; 244 clock-frequency = <400000>;
245 pinctrl-names = "default", "gpio"; 245 pinctrl-names = "default", "gpio";
246 pinctrl-0 = <&pinctrl_i2c1>; 246 pinctrl-0 = <&pinctrl_i2c1>;
247 pinctrl-1 = <&pinctrl_i2c1_gpio>; 247 pinctrl-1 = <&pinctrl_i2c1_gpio>;
248 scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; 248 scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
249 sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; 249 sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
250 status = "okay"; 250 status = "okay";
251 251
252 pmic: bd71837@4b { 252 pmic: bd71837@4b {
253 reg = <0x4b>; 253 reg = <0x4b>;
254 compatible = "rohm,bd71837"; 254 compatible = "rohm,bd71837";
255 /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ 255 /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */
256 pinctrl-0 = <&pinctrl_pmic>; 256 pinctrl-0 = <&pinctrl_pmic>;
257 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; 257 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
258 258
259 gpo { 259 gpo {
260 rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ 260 rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
261 }; 261 };
262 262
263 regulators { 263 regulators {
264 #address-cells = <1>; 264 #address-cells = <1>;
265 #size-cells = <0>; 265 #size-cells = <0>;
266 266
267 bd71837,pmic-buck2-uses-i2c-dvs; 267 bd71837,pmic-buck2-uses-i2c-dvs;
268 bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ 268 bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
269 269
270 buck1_reg: regulator@0 { 270 buck1_reg: regulator@0 {
271 reg = <0>; 271 reg = <0>;
272 regulator-compatible = "buck1"; 272 regulator-compatible = "buck1";
273 regulator-min-microvolt = <700000>; 273 regulator-min-microvolt = <700000>;
274 regulator-max-microvolt = <1300000>; 274 regulator-max-microvolt = <1300000>;
275 regulator-boot-on; 275 regulator-boot-on;
276 regulator-always-on; 276 regulator-always-on;
277 regulator-ramp-delay = <1250>; 277 regulator-ramp-delay = <1250>;
278 }; 278 };
279 279
280 buck2_reg: regulator@1 { 280 buck2_reg: regulator@1 {
281 reg = <1>; 281 reg = <1>;
282 regulator-compatible = "buck2"; 282 regulator-compatible = "buck2";
283 regulator-min-microvolt = <700000>; 283 regulator-min-microvolt = <700000>;
284 regulator-max-microvolt = <1300000>; 284 regulator-max-microvolt = <1300000>;
285 regulator-boot-on; 285 regulator-boot-on;
286 regulator-always-on; 286 regulator-always-on;
287 regulator-ramp-delay = <1250>; 287 regulator-ramp-delay = <1250>;
288 }; 288 };
289 289
290 buck3_reg: regulator@2 { 290 buck3_reg: regulator@2 {
291 reg = <2>; 291 reg = <2>;
292 regulator-compatible = "buck3"; 292 regulator-compatible = "buck3";
293 regulator-min-microvolt = <700000>; 293 regulator-min-microvolt = <700000>;
294 regulator-max-microvolt = <1300000>; 294 regulator-max-microvolt = <1300000>;
295 }; 295 };
296 296
297 buck4_reg: regulator@3 { 297 buck4_reg: regulator@3 {
298 reg = <3>; 298 reg = <3>;
299 regulator-compatible = "buck4"; 299 regulator-compatible = "buck4";
300 regulator-min-microvolt = <700000>; 300 regulator-min-microvolt = <700000>;
301 regulator-max-microvolt = <1300000>; 301 regulator-max-microvolt = <1300000>;
302 }; 302 };
303 303
304 buck5_reg: regulator@4 { 304 buck5_reg: regulator@4 {
305 reg = <4>; 305 reg = <4>;
306 regulator-compatible = "buck5"; 306 regulator-compatible = "buck5";
307 regulator-min-microvolt = <700000>; 307 regulator-min-microvolt = <700000>;
308 regulator-max-microvolt = <1350000>; 308 regulator-max-microvolt = <1350000>;
309 regulator-boot-on; 309 regulator-boot-on;
310 regulator-always-on; 310 regulator-always-on;
311 }; 311 };
312 312
313 buck6_reg: regulator@5 { 313 buck6_reg: regulator@5 {
314 reg = <5>; 314 reg = <5>;
315 regulator-compatible = "buck6"; 315 regulator-compatible = "buck6";
316 regulator-min-microvolt = <3000000>; 316 regulator-min-microvolt = <3000000>;
317 regulator-max-microvolt = <3300000>; 317 regulator-max-microvolt = <3300000>;
318 regulator-boot-on; 318 regulator-boot-on;
319 regulator-always-on; 319 regulator-always-on;
320 }; 320 };
321 321
322 buck7_reg: regulator@6 { 322 buck7_reg: regulator@6 {
323 reg = <6>; 323 reg = <6>;
324 regulator-compatible = "buck7"; 324 regulator-compatible = "buck7";
325 regulator-min-microvolt = <1605000>; 325 regulator-min-microvolt = <1605000>;
326 regulator-max-microvolt = <1995000>; 326 regulator-max-microvolt = <1995000>;
327 regulator-boot-on; 327 regulator-boot-on;
328 regulator-always-on; 328 regulator-always-on;
329 }; 329 };
330 330
331 buck8_reg: regulator@7 { 331 buck8_reg: regulator@7 {
332 reg = <7>; 332 reg = <7>;
333 regulator-compatible = "buck8"; 333 regulator-compatible = "buck8";
334 regulator-min-microvolt = <800000>; 334 regulator-min-microvolt = <800000>;
335 regulator-max-microvolt = <1400000>; 335 regulator-max-microvolt = <1400000>;
336 regulator-boot-on; 336 regulator-boot-on;
337 regulator-always-on; 337 regulator-always-on;
338 }; 338 };
339 339
340 ldo1_reg: regulator@8 { 340 ldo1_reg: regulator@8 {
341 reg = <8>; 341 reg = <8>;
342 regulator-compatible = "ldo1"; 342 regulator-compatible = "ldo1";
343 regulator-min-microvolt = <3000000>; 343 regulator-min-microvolt = <3000000>;
344 regulator-max-microvolt = <3300000>; 344 regulator-max-microvolt = <3300000>;
345 regulator-boot-on; 345 regulator-boot-on;
346 regulator-always-on; 346 regulator-always-on;
347 }; 347 };
348 348
349 ldo2_reg: regulator@9 { 349 ldo2_reg: regulator@9 {
350 reg = <9>; 350 reg = <9>;
351 regulator-compatible = "ldo2"; 351 regulator-compatible = "ldo2";
352 regulator-min-microvolt = <900000>; 352 regulator-min-microvolt = <900000>;
353 regulator-max-microvolt = <900000>; 353 regulator-max-microvolt = <900000>;
354 regulator-boot-on; 354 regulator-boot-on;
355 regulator-always-on; 355 regulator-always-on;
356 }; 356 };
357 357
358 ldo3_reg: regulator@10 { 358 ldo3_reg: regulator@10 {
359 reg = <10>; 359 reg = <10>;
360 regulator-compatible = "ldo3"; 360 regulator-compatible = "ldo3";
361 regulator-min-microvolt = <1800000>; 361 regulator-min-microvolt = <1800000>;
362 regulator-max-microvolt = <3300000>; 362 regulator-max-microvolt = <3300000>;
363 regulator-boot-on; 363 regulator-boot-on;
364 regulator-always-on; 364 regulator-always-on;
365 }; 365 };
366 366
367 ldo4_reg: regulator@11 { 367 ldo4_reg: regulator@11 {
368 reg = <11>; 368 reg = <11>;
369 regulator-compatible = "ldo4"; 369 regulator-compatible = "ldo4";
370 regulator-min-microvolt = <900000>; 370 regulator-min-microvolt = <900000>;
371 regulator-max-microvolt = <1800000>; 371 regulator-max-microvolt = <1800000>;
372 regulator-boot-on; 372 regulator-boot-on;
373 regulator-always-on; 373 regulator-always-on;
374 }; 374 };
375 375
376 ldo5_reg: regulator@12 { 376 ldo5_reg: regulator@12 {
377 reg = <12>; 377 reg = <12>;
378 regulator-compatible = "ldo5"; 378 regulator-compatible = "ldo5";
379 regulator-min-microvolt = <1800000>; 379 regulator-min-microvolt = <1800000>;
380 regulator-max-microvolt = <3300000>; 380 regulator-max-microvolt = <3300000>;
381 }; 381 };
382 382
383 ldo6_reg: regulator@13 { 383 ldo6_reg: regulator@13 {
384 reg = <13>; 384 reg = <13>;
385 regulator-compatible = "ldo6"; 385 regulator-compatible = "ldo6";
386 regulator-min-microvolt = <900000>; 386 regulator-min-microvolt = <900000>;
387 regulator-max-microvolt = <1800000>; 387 regulator-max-microvolt = <1800000>;
388 regulator-boot-on; 388 regulator-boot-on;
389 regulator-always-on; 389 regulator-always-on;
390 }; 390 };
391 391
392 ldo7_reg: regulator@14 { 392 ldo7_reg: regulator@14 {
393 reg = <14>; 393 reg = <14>;
394 regulator-compatible = "ldo7"; 394 regulator-compatible = "ldo7";
395 regulator-min-microvolt = <1800000>; 395 regulator-min-microvolt = <1800000>;
396 regulator-max-microvolt = <3300000>; 396 regulator-max-microvolt = <3300000>;
397 }; 397 };
398 }; 398 };
399 }; 399 };
400 }; 400 };
401 401
402 &i2c2 { 402 &i2c2 {
403 clock-frequency = <400000>; 403 clock-frequency = <400000>;
404 pinctrl-names = "default", "gpio"; 404 pinctrl-names = "default", "gpio";
405 pinctrl-0 = <&pinctrl_i2c2>; 405 pinctrl-0 = <&pinctrl_i2c2>;
406 pinctrl-1 = <&pinctrl_i2c2_gpio>; 406 pinctrl-1 = <&pinctrl_i2c2_gpio>;
407 scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; 407 scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
408 sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; 408 sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
409 status = "okay"; 409 status = "okay";
410 410
411 typec_ptn5110_1: ptn5110@50 { 411 typec_ptn5110_1: ptn5110@50 {
412 compatible = "usb,tcpci"; 412 compatible = "usb,tcpci";
413 reg = <0x50>; 413 reg = <0x50>;
414 src-pdos = <0x380190c8>; 414 src-pdos = <0x380190c8>;
415 snk-pdos = <0x380190c8 0x3802d0c8>; 415 snk-pdos = <0x380190c8 0x3802d0c8>;
416 max-snk-mv = <9000>; 416 max-snk-mv = <9000>;
417 max-snk-ma = <2000>; 417 max-snk-ma = <2000>;
418 op-snk-mw = <9000>; 418 op-snk-mw = <9000>;
419 max-snk-mw = <18000>; 419 max-snk-mw = <18000>;
420 port-type = "drp"; 420 port-type = "drp";
421 default-role = "sink"; 421 default-role = "sink";
422 }; 422 };
423 423
424 typec_ptn5110_2: ptn5110@52 { 424 typec_ptn5110_2: ptn5110@52 {
425 compatible = "usb,tcpci"; 425 compatible = "usb,tcpci";
426 reg = <0x52>; 426 reg = <0x52>;
427 src-pdos = <0x380190c8>; 427 src-pdos = <0x380190c8>;
428 snk-pdos = <0x380190c8 0x3802d0c8>; 428 snk-pdos = <0x380190c8 0x3802d0c8>;
429 max-snk-mv = <9000>; 429 max-snk-mv = <9000>;
430 max-snk-ma = <2000>; 430 max-snk-ma = <2000>;
431 op-snk-mw = <9000>; 431 op-snk-mw = <9000>;
432 max-snk-mw = <18000>; 432 max-snk-mw = <18000>;
433 port-type = "drp"; 433 port-type = "drp";
434 default-role = "sink"; 434 default-role = "sink";
435 }; 435 };
436 }; 436 };
437 437
438 &i2c3 { 438 &i2c3 {
439 clock-frequency = <100000>; 439 clock-frequency = <100000>;
440 pinctrl-names = "default", "gpio"; 440 pinctrl-names = "default", "gpio";
441 pinctrl-0 = <&pinctrl_i2c3>; 441 pinctrl-0 = <&pinctrl_i2c3>;
442 pinctrl-1 = <&pinctrl_i2c3_gpio>; 442 pinctrl-1 = <&pinctrl_i2c3_gpio>;
443 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; 443 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
444 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; 444 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
445 status = "okay"; 445 status = "okay";
446 }; 446 };
447 447
448 &flexspi { 448 &flexspi {
449 pinctrl-names = "default"; 449 pinctrl-names = "default";
450 pinctrl-0 = <&pinctrl_flexspi>; 450 pinctrl-0 = <&pinctrl_flexspi>;
451 status = "okay"; 451 status = "okay";
452 452
453 flash0: n25q256a@0 { 453 flash0: n25q256a@0 {
454 reg = <0>; 454 reg = <0>;
455 #address-cells = <1>; 455 #address-cells = <1>;
456 #size-cells = <1>; 456 #size-cells = <1>;
457 compatible = "spi-flash"; 457 compatible = "spi-flash";
458 spi-max-frequency = <29000000>; 458 spi-max-frequency = <29000000>;
459 spi-nor,ddr-quad-read-dummy = <8>; 459 spi-nor,ddr-quad-read-dummy = <8>;
460 }; 460 };
461 }; 461 };
462 462
463 &fec1 { 463 &fec1 {
464 pinctrl-names = "default"; 464 pinctrl-names = "default";
465 pinctrl-0 = <&pinctrl_fec1>; 465 pinctrl-0 = <&pinctrl_fec1>;
466 phy-mode = "rgmii-id"; 466 phy-mode = "rgmii-id";
467 phy-handle = <&ethphy0>; 467 phy-handle = <&ethphy0>;
468 fsl,magic-packet; 468 fsl,magic-packet;
469 status = "okay"; 469 status = "okay";
470 470
471 mdio { 471 mdio {
472 #address-cells = <1>; 472 #address-cells = <1>;
473 #size-cells = <0>; 473 #size-cells = <0>;
474 474
475 ethphy0: ethernet-phy@0 { 475 ethphy0: ethernet-phy@0 {
476 compatible = "ethernet-phy-ieee802.3-c22"; 476 compatible = "ethernet-phy-ieee802.3-c22";
477 reg = <0>; 477 reg = <0>;
478 at803x,led-act-blind-workaround; 478 at803x,led-act-blind-workaround;
479 at803x,eee-okay; 479 at803x,eee-okay;
480 at803x,vddio-1p8v; 480 at803x,vddio-1p8v;
481 }; 481 };
482 }; 482 };
483 }; 483 };
484 484
485 &uart2 { /* console */ 485 &uart2 { /* console */
486 pinctrl-names = "default"; 486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_uart2>; 487 pinctrl-0 = <&pinctrl_uart2>;
488 status = "okay"; 488 status = "okay";
489 }; 489 };
490 490
491 &usdhc2 { 491 &usdhc2 {
492 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 492 pinctrl-names = "default", "state_100mhz", "state_200mhz";
493 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 493 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
494 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 494 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
495 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 495 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
496 bus-width = <4>; 496 bus-width = <4>;
497 non-removable; 497 non-removable;
498 vmmc-supply = <&reg_usdhc2_vmmc>; 498 vmmc-supply = <&reg_usdhc2_vmmc>;
499 status = "okay"; 499 status = "okay";
500 }; 500 };
501 501
502 &usdhc3 { 502 &usdhc3 {
503 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 503 pinctrl-names = "default", "state_100mhz", "state_200mhz";
504 pinctrl-0 = <&pinctrl_usdhc3>; 504 pinctrl-0 = <&pinctrl_usdhc3>;
505 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 505 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
506 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 506 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
507 bus-width = <8>; 507 bus-width = <8>;
508 non-removable; 508 non-removable;
509 status = "okay"; 509 status = "okay";
510 }; 510 };
511 511
512 &wdog1 { 512 &wdog1 {
513 pinctrl-names = "default"; 513 pinctrl-names = "default";
514 pinctrl-0 = <&pinctrl_wdog>; 514 pinctrl-0 = <&pinctrl_wdog>;
515 fsl,ext-reset-output; 515 fsl,ext-reset-output;
516 status = "okay"; 516 status = "okay";
517 }; 517 };
518 518
519 &A53_0 { 519 &A53_0 {
520 arm-supply = <&buck2_reg>; 520 arm-supply = <&buck2_reg>;
521 }; 521 };
522 522
523 &usbotg1 { 523 &usbotg1 {
524 status = "okay"; 524 status = "okay";
525 extcon = <&typec_ptn5110_1>; 525 extcon = <&typec_ptn5110_1>;
526 }; 526 };
527 527
528 &usbotg2 { 528 &usbotg2 {
529 status = "okay"; 529 status = "okay";
530 extcon = <&typec_ptn5110_2>; 530 extcon = <&typec_ptn5110_2>;
531 }; 531 };
532 532
arch/arm/dts/fsl-imx8mn-ddr4-evk.dts
Diff comments   View file @ 4daafb3
1 /* 1 /*
2 * Copyright 2018-2019 NXP 2 * Copyright 2018-2019 NXP
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2 6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version. 7 * of the License, or (at your option) any later version.
8 * 8 *
9 * This program is distributed in the hope that it will be useful, 9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 */ 13 */
14 14
15 /dts-v1/; 15 /dts-v1/;
16 16
17 #include "fsl-imx8mn.dtsi" 17 #include "fsl-imx8mn.dtsi"
18 18
19 / { 19 / {
20 model = "NXP i.MX8MNano EVK board"; 20 model = "NXP i.MX8MNano EVK board";
21 compatible = "fsl,imx8mn-evk", "fsl,imx8mn"; 21 compatible = "fsl,imx8mn-evk", "fsl,imx8mn";
22 22
23 chosen { 23 chosen {
24 bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; 24 bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
25 stdout-path = &uart2; 25 stdout-path = &uart2;
26 }; 26 };
27 27
28 firmware { 28 firmware {
29 optee { 29 optee {
30 compatible = "linaro,optee-tz"; 30 compatible = "linaro,optee-tz";
31 method = "smc"; 31 method = "smc";
32 }; 32 };
33 }; 33 };
34 34
35 reg_usdhc2_vmmc: regulator-usdhc2 { 35 reg_usdhc2_vmmc: regulator-usdhc2 {
36 compatible = "regulator-fixed"; 36 compatible = "regulator-fixed";
37 regulator-name = "VSD_3V3"; 37 regulator-name = "VSD_3V3";
38 regulator-min-microvolt = <3300000>; 38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>;
40 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 40 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
41 enable-active-high; 41 enable-active-high;
42 startup-delay-us = <100>; 42 startup-delay-us = <100>;
43 off-on-delay-us = <12000>; 43 u-boot,off-on-delay-us = <12000>;
44 }; 44 };
45 }; 45 };
46 46
47 &iomuxc { 47 &iomuxc {
48 pinctrl-names = "default"; 48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_hog_1>; 49 pinctrl-0 = <&pinctrl_hog_1>;
50 50
51 imx8mn-evk { 51 imx8mn-evk {
52 pinctrl_hog_1: hoggrp-1 { 52 pinctrl_hog_1: hoggrp-1 {
53 fsl,pins = < 53 fsl,pins = <
54 MX8MN_IOMUXC_GPIO1_IO08__GPIO1_IO8 0x16 54 MX8MN_IOMUXC_GPIO1_IO08__GPIO1_IO8 0x16
55 >; 55 >;
56 }; 56 };
57 57
58 pinctrl_fec1: fec1grp { 58 pinctrl_fec1: fec1grp {
59 fsl,pins = < 59 fsl,pins = <
60 MX8MN_IOMUXC_ENET_MDC__ENET1_MDC 0x3 60 MX8MN_IOMUXC_ENET_MDC__ENET1_MDC 0x3
61 MX8MN_IOMUXC_ENET_MDIO__ENET1_MDIO 0x3 61 MX8MN_IOMUXC_ENET_MDIO__ENET1_MDIO 0x3
62 MX8MN_IOMUXC_ENET_TD3__ENET1_RGMII_TD3 0x1f 62 MX8MN_IOMUXC_ENET_TD3__ENET1_RGMII_TD3 0x1f
63 MX8MN_IOMUXC_ENET_TD2__ENET1_RGMII_TD2 0x1f 63 MX8MN_IOMUXC_ENET_TD2__ENET1_RGMII_TD2 0x1f
64 MX8MN_IOMUXC_ENET_TD1__ENET1_RGMII_TD1 0x1f 64 MX8MN_IOMUXC_ENET_TD1__ENET1_RGMII_TD1 0x1f
65 MX8MN_IOMUXC_ENET_TD0__ENET1_RGMII_TD0 0x1f 65 MX8MN_IOMUXC_ENET_TD0__ENET1_RGMII_TD0 0x1f
66 MX8MN_IOMUXC_ENET_RD3__ENET1_RGMII_RD3 0x91 66 MX8MN_IOMUXC_ENET_RD3__ENET1_RGMII_RD3 0x91
67 MX8MN_IOMUXC_ENET_RD2__ENET1_RGMII_RD2 0x91 67 MX8MN_IOMUXC_ENET_RD2__ENET1_RGMII_RD2 0x91
68 MX8MN_IOMUXC_ENET_RD1__ENET1_RGMII_RD1 0x91 68 MX8MN_IOMUXC_ENET_RD1__ENET1_RGMII_RD1 0x91
69 MX8MN_IOMUXC_ENET_RD0__ENET1_RGMII_RD0 0x91 69 MX8MN_IOMUXC_ENET_RD0__ENET1_RGMII_RD0 0x91
70 MX8MN_IOMUXC_ENET_TXC__ENET1_RGMII_TXC 0x1f 70 MX8MN_IOMUXC_ENET_TXC__ENET1_RGMII_TXC 0x1f
71 MX8MN_IOMUXC_ENET_RXC__ENET1_RGMII_RXC 0x91 71 MX8MN_IOMUXC_ENET_RXC__ENET1_RGMII_RXC 0x91
72 MX8MN_IOMUXC_ENET_RX_CTL__ENET1_RGMII_RX_CTL 0x91 72 MX8MN_IOMUXC_ENET_RX_CTL__ENET1_RGMII_RX_CTL 0x91
73 MX8MN_IOMUXC_ENET_TX_CTL__ENET1_RGMII_TX_CTL 0x1f 73 MX8MN_IOMUXC_ENET_TX_CTL__ENET1_RGMII_TX_CTL 0x1f
74 MX8MN_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 74 MX8MN_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
75 >; 75 >;
76 }; 76 };
77 77
78 pinctrl_flexspi0: flexspi0grp { 78 pinctrl_flexspi0: flexspi0grp {
79 fsl,pins = < 79 fsl,pins = <
80 MX8MN_IOMUXC_NAND_ALE__QSPI_A_SCLK 0x1c4 80 MX8MN_IOMUXC_NAND_ALE__QSPI_A_SCLK 0x1c4
81 MX8MN_IOMUXC_NAND_CE0_B__QSPI_A_SS0_B 0x84 81 MX8MN_IOMUXC_NAND_CE0_B__QSPI_A_SS0_B 0x84
82 82
83 MX8MN_IOMUXC_NAND_DQS__QSPI_A_DQS 0x40000084 83 MX8MN_IOMUXC_NAND_DQS__QSPI_A_DQS 0x40000084
84 MX8MN_IOMUXC_NAND_DATA00__QSPI_A_DATA0 0x84 84 MX8MN_IOMUXC_NAND_DATA00__QSPI_A_DATA0 0x84
85 MX8MN_IOMUXC_NAND_DATA01__QSPI_A_DATA1 0x84 85 MX8MN_IOMUXC_NAND_DATA01__QSPI_A_DATA1 0x84
86 MX8MN_IOMUXC_NAND_DATA02__QSPI_A_DATA2 0x84 86 MX8MN_IOMUXC_NAND_DATA02__QSPI_A_DATA2 0x84
87 MX8MN_IOMUXC_NAND_DATA03__QSPI_A_DATA3 0x84 87 MX8MN_IOMUXC_NAND_DATA03__QSPI_A_DATA3 0x84
88 >; 88 >;
89 }; 89 };
90 90
91 pinctrl_i2c1: i2c1grp { 91 pinctrl_i2c1: i2c1grp {
92 fsl,pins = < 92 fsl,pins = <
93 MX8MN_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 93 MX8MN_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
94 MX8MN_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 94 MX8MN_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
95 >; 95 >;
96 }; 96 };
97 97
98 pinctrl_i2c2: i2c2grp { 98 pinctrl_i2c2: i2c2grp {
99 fsl,pins = < 99 fsl,pins = <
100 MX8MN_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 100 MX8MN_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
101 MX8MN_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 101 MX8MN_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
102 >; 102 >;
103 }; 103 };
104 104
105 pinctrl_i2c3: i2c3grp { 105 pinctrl_i2c3: i2c3grp {
106 fsl,pins = < 106 fsl,pins = <
107 MX8MN_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 107 MX8MN_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
108 MX8MN_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 108 MX8MN_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
109 >; 109 >;
110 }; 110 };
111 111
112 pinctrl_i2c1_gpio: i2c1grp-gpio { 112 pinctrl_i2c1_gpio: i2c1grp-gpio {
113 fsl,pins = < 113 fsl,pins = <
114 MX8MN_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3 114 MX8MN_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
115 MX8MN_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3 115 MX8MN_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
116 >; 116 >;
117 }; 117 };
118 118
119 pinctrl_i2c2_gpio: i2c2grp-gpio { 119 pinctrl_i2c2_gpio: i2c2grp-gpio {
120 fsl,pins = < 120 fsl,pins = <
121 MX8MN_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3 121 MX8MN_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3
122 MX8MN_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3 122 MX8MN_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3
123 >; 123 >;
124 }; 124 };
125 125
126 pinctrl_i2c3_gpio: i2c3grp-gpio { 126 pinctrl_i2c3_gpio: i2c3grp-gpio {
127 fsl,pins = < 127 fsl,pins = <
128 MX8MN_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3 128 MX8MN_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3
129 MX8MN_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3 129 MX8MN_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3
130 >; 130 >;
131 }; 131 };
132 132
133 pinctrl_pmic: pmicirq { 133 pinctrl_pmic: pmicirq {
134 fsl,pins = < 134 fsl,pins = <
135 MX8MN_IOMUXC_GPIO1_IO03__GPIO1_IO3 0x41 135 MX8MN_IOMUXC_GPIO1_IO03__GPIO1_IO3 0x41
136 >; 136 >;
137 }; 137 };
138 138
139 pinctrl_uart2: uart1grp { 139 pinctrl_uart2: uart1grp {
140 fsl,pins = < 140 fsl,pins = <
141 MX8MN_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 141 MX8MN_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
142 MX8MN_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 142 MX8MN_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
143 >; 143 >;
144 }; 144 };
145 145
146 pinctrl_usdhc2_gpio: usdhc2grpgpio { 146 pinctrl_usdhc2_gpio: usdhc2grpgpio {
147 fsl,pins = < 147 fsl,pins = <
148 MX8MN_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4 148 MX8MN_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4
149 MX8MN_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 149 MX8MN_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
150 >; 150 >;
151 }; 151 };
152 152
153 pinctrl_usdhc2: usdhc2grp { 153 pinctrl_usdhc2: usdhc2grp {
154 fsl,pins = < 154 fsl,pins = <
155 MX8MN_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 155 MX8MN_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
156 MX8MN_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 156 MX8MN_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
157 MX8MN_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 157 MX8MN_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
158 MX8MN_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 158 MX8MN_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
159 MX8MN_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 159 MX8MN_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
160 MX8MN_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 160 MX8MN_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
161 MX8MN_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 161 MX8MN_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0
162 >; 162 >;
163 }; 163 };
164 164
165 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 165 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
166 fsl,pins = < 166 fsl,pins = <
167 MX8MN_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 167 MX8MN_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
168 MX8MN_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 168 MX8MN_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
169 MX8MN_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 169 MX8MN_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
170 MX8MN_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 170 MX8MN_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
171 MX8MN_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 171 MX8MN_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
172 MX8MN_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 172 MX8MN_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
173 MX8MN_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 173 MX8MN_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0
174 >; 174 >;
175 }; 175 };
176 176
177 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 177 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
178 fsl,pins = < 178 fsl,pins = <
179 MX8MN_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 179 MX8MN_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
180 MX8MN_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 180 MX8MN_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
181 MX8MN_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 181 MX8MN_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
182 MX8MN_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 182 MX8MN_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
183 MX8MN_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 183 MX8MN_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
184 MX8MN_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 184 MX8MN_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
185 MX8MN_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 185 MX8MN_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0
186 >; 186 >;
187 }; 187 };
188 188
189 pinctrl_usdhc3: usdhc3grp { 189 pinctrl_usdhc3: usdhc3grp {
190 fsl,pins = < 190 fsl,pins = <
191 MX8MN_IOMUXC_NAND_WE_B__USDHC3_CLK 0x40000190 191 MX8MN_IOMUXC_NAND_WE_B__USDHC3_CLK 0x40000190
192 MX8MN_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 192 MX8MN_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
193 MX8MN_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 193 MX8MN_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
194 MX8MN_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 194 MX8MN_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
195 MX8MN_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 195 MX8MN_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
196 MX8MN_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 196 MX8MN_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
197 MX8MN_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 197 MX8MN_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
198 MX8MN_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 198 MX8MN_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
199 MX8MN_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 199 MX8MN_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
200 MX8MN_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 200 MX8MN_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
201 MX8MN_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 201 MX8MN_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
202 >; 202 >;
203 }; 203 };
204 204
205 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 205 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
206 fsl,pins = < 206 fsl,pins = <
207 MX8MN_IOMUXC_NAND_WE_B__USDHC3_CLK 0x40000194 207 MX8MN_IOMUXC_NAND_WE_B__USDHC3_CLK 0x40000194
208 MX8MN_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 208 MX8MN_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
209 MX8MN_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 209 MX8MN_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
210 MX8MN_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 210 MX8MN_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
211 MX8MN_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 211 MX8MN_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
212 MX8MN_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 212 MX8MN_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
213 MX8MN_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 213 MX8MN_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
214 MX8MN_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 214 MX8MN_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
215 MX8MN_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 215 MX8MN_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
216 MX8MN_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 216 MX8MN_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
217 MX8MN_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 217 MX8MN_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
218 >; 218 >;
219 }; 219 };
220 220
221 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 221 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
222 fsl,pins = < 222 fsl,pins = <
223 MX8MN_IOMUXC_NAND_WE_B__USDHC3_CLK 0x40000196 223 MX8MN_IOMUXC_NAND_WE_B__USDHC3_CLK 0x40000196
224 MX8MN_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 224 MX8MN_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
225 MX8MN_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 225 MX8MN_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
226 MX8MN_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 226 MX8MN_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
227 MX8MN_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 227 MX8MN_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
228 MX8MN_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 228 MX8MN_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
229 MX8MN_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 229 MX8MN_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
230 MX8MN_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 230 MX8MN_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
231 MX8MN_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 231 MX8MN_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
232 MX8MN_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 232 MX8MN_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
233 MX8MN_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 233 MX8MN_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
234 >; 234 >;
235 }; 235 };
236 236
237 pinctrl_wdog: wdoggrp { 237 pinctrl_wdog: wdoggrp {
238 fsl,pins = < 238 fsl,pins = <
239 MX8MN_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 239 MX8MN_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
240 >; 240 >;
241 }; 241 };
242 }; 242 };
243 }; 243 };
244 244
245 &i2c1 { 245 &i2c1 {
246 clock-frequency = <400000>; 246 clock-frequency = <400000>;
247 pinctrl-names = "default", "gpio"; 247 pinctrl-names = "default", "gpio";
248 pinctrl-0 = <&pinctrl_i2c1>; 248 pinctrl-0 = <&pinctrl_i2c1>;
249 pinctrl-1 = <&pinctrl_i2c1_gpio>; 249 pinctrl-1 = <&pinctrl_i2c1_gpio>;
250 scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; 250 scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
251 sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; 251 sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
252 status = "okay"; 252 status = "okay";
253 253
254 pmic: bd71837@4b { 254 pmic: bd71837@4b {
255 reg = <0x4b>; 255 reg = <0x4b>;
256 compatible = "rohm,bd71837"; 256 compatible = "rohm,bd71837";
257 /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ 257 /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */
258 pinctrl-0 = <&pinctrl_pmic>; 258 pinctrl-0 = <&pinctrl_pmic>;
259 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; 259 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
260 260
261 gpo { 261 gpo {
262 rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ 262 rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
263 }; 263 };
264 264
265 regulators { 265 regulators {
266 #address-cells = <1>; 266 #address-cells = <1>;
267 #size-cells = <0>; 267 #size-cells = <0>;
268 268
269 bd71837,pmic-buck2-uses-i2c-dvs; 269 bd71837,pmic-buck2-uses-i2c-dvs;
270 bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ 270 bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
271 271
272 buck1_reg: regulator@0 { 272 buck1_reg: regulator@0 {
273 reg = <0>; 273 reg = <0>;
274 regulator-compatible = "buck1"; 274 regulator-compatible = "buck1";
275 regulator-min-microvolt = <700000>; 275 regulator-min-microvolt = <700000>;
276 regulator-max-microvolt = <1300000>; 276 regulator-max-microvolt = <1300000>;
277 regulator-boot-on; 277 regulator-boot-on;
278 regulator-always-on; 278 regulator-always-on;
279 regulator-ramp-delay = <1250>; 279 regulator-ramp-delay = <1250>;
280 }; 280 };
281 281
282 buck2_reg: regulator@1 { 282 buck2_reg: regulator@1 {
283 reg = <1>; 283 reg = <1>;
284 regulator-compatible = "buck2"; 284 regulator-compatible = "buck2";
285 regulator-min-microvolt = <700000>; 285 regulator-min-microvolt = <700000>;
286 regulator-max-microvolt = <1300000>; 286 regulator-max-microvolt = <1300000>;
287 regulator-boot-on; 287 regulator-boot-on;
288 regulator-always-on; 288 regulator-always-on;
289 regulator-ramp-delay = <1250>; 289 regulator-ramp-delay = <1250>;
290 }; 290 };
291 291
292 buck3_reg: regulator@2 { 292 buck3_reg: regulator@2 {
293 reg = <2>; 293 reg = <2>;
294 regulator-compatible = "buck3"; 294 regulator-compatible = "buck3";
295 regulator-min-microvolt = <700000>; 295 regulator-min-microvolt = <700000>;
296 regulator-max-microvolt = <1300000>; 296 regulator-max-microvolt = <1300000>;
297 }; 297 };
298 298
299 buck4_reg: regulator@3 { 299 buck4_reg: regulator@3 {
300 reg = <3>; 300 reg = <3>;
301 regulator-compatible = "buck4"; 301 regulator-compatible = "buck4";
302 regulator-min-microvolt = <700000>; 302 regulator-min-microvolt = <700000>;
303 regulator-max-microvolt = <1300000>; 303 regulator-max-microvolt = <1300000>;
304 }; 304 };
305 305
306 buck5_reg: regulator@4 { 306 buck5_reg: regulator@4 {
307 reg = <4>; 307 reg = <4>;
308 regulator-compatible = "buck5"; 308 regulator-compatible = "buck5";
309 regulator-min-microvolt = <700000>; 309 regulator-min-microvolt = <700000>;
310 regulator-max-microvolt = <1350000>; 310 regulator-max-microvolt = <1350000>;
311 }; 311 };
312 312
313 buck6_reg: regulator@5 { 313 buck6_reg: regulator@5 {
314 reg = <5>; 314 reg = <5>;
315 regulator-compatible = "buck6"; 315 regulator-compatible = "buck6";
316 regulator-min-microvolt = <3000000>; 316 regulator-min-microvolt = <3000000>;
317 regulator-max-microvolt = <3300000>; 317 regulator-max-microvolt = <3300000>;
318 regulator-boot-on; 318 regulator-boot-on;
319 regulator-always-on; 319 regulator-always-on;
320 }; 320 };
321 321
322 buck7_reg: regulator@6 { 322 buck7_reg: regulator@6 {
323 reg = <6>; 323 reg = <6>;
324 regulator-compatible = "buck7"; 324 regulator-compatible = "buck7";
325 regulator-min-microvolt = <1605000>; 325 regulator-min-microvolt = <1605000>;
326 regulator-max-microvolt = <1995000>; 326 regulator-max-microvolt = <1995000>;
327 regulator-boot-on; 327 regulator-boot-on;
328 regulator-always-on; 328 regulator-always-on;
329 }; 329 };
330 330
331 buck8_reg: regulator@7 { 331 buck8_reg: regulator@7 {
332 reg = <7>; 332 reg = <7>;
333 regulator-compatible = "buck8"; 333 regulator-compatible = "buck8";
334 regulator-min-microvolt = <800000>; 334 regulator-min-microvolt = <800000>;
335 regulator-max-microvolt = <1400000>; 335 regulator-max-microvolt = <1400000>;
336 regulator-boot-on; 336 regulator-boot-on;
337 regulator-always-on; 337 regulator-always-on;
338 }; 338 };
339 339
340 ldo1_reg: regulator@8 { 340 ldo1_reg: regulator@8 {
341 reg = <8>; 341 reg = <8>;
342 regulator-compatible = "ldo1"; 342 regulator-compatible = "ldo1";
343 regulator-min-microvolt = <3000000>; 343 regulator-min-microvolt = <3000000>;
344 regulator-max-microvolt = <3300000>; 344 regulator-max-microvolt = <3300000>;
345 regulator-boot-on; 345 regulator-boot-on;
346 regulator-always-on; 346 regulator-always-on;
347 }; 347 };
348 348
349 ldo2_reg: regulator@9 { 349 ldo2_reg: regulator@9 {
350 reg = <9>; 350 reg = <9>;
351 regulator-compatible = "ldo2"; 351 regulator-compatible = "ldo2";
352 regulator-min-microvolt = <900000>; 352 regulator-min-microvolt = <900000>;
353 regulator-max-microvolt = <900000>; 353 regulator-max-microvolt = <900000>;
354 regulator-boot-on; 354 regulator-boot-on;
355 regulator-always-on; 355 regulator-always-on;
356 }; 356 };
357 357
358 ldo3_reg: regulator@10 { 358 ldo3_reg: regulator@10 {
359 reg = <10>; 359 reg = <10>;
360 regulator-compatible = "ldo3"; 360 regulator-compatible = "ldo3";
361 regulator-min-microvolt = <1800000>; 361 regulator-min-microvolt = <1800000>;
362 regulator-max-microvolt = <3300000>; 362 regulator-max-microvolt = <3300000>;
363 regulator-boot-on; 363 regulator-boot-on;
364 regulator-always-on; 364 regulator-always-on;
365 }; 365 };
366 366
367 ldo4_reg: regulator@11 { 367 ldo4_reg: regulator@11 {
368 reg = <11>; 368 reg = <11>;
369 regulator-compatible = "ldo4"; 369 regulator-compatible = "ldo4";
370 regulator-min-microvolt = <900000>; 370 regulator-min-microvolt = <900000>;
371 regulator-max-microvolt = <1800000>; 371 regulator-max-microvolt = <1800000>;
372 }; 372 };
373 373
374 ldo5_reg: regulator@12 { 374 ldo5_reg: regulator@12 {
375 reg = <12>; 375 reg = <12>;
376 regulator-compatible = "ldo5"; 376 regulator-compatible = "ldo5";
377 regulator-min-microvolt = <1800000>; 377 regulator-min-microvolt = <1800000>;
378 regulator-max-microvolt = <3300000>; 378 regulator-max-microvolt = <3300000>;
379 }; 379 };
380 380
381 ldo6_reg: regulator@13 { 381 ldo6_reg: regulator@13 {
382 reg = <13>; 382 reg = <13>;
383 regulator-compatible = "ldo6"; 383 regulator-compatible = "ldo6";
384 regulator-min-microvolt = <900000>; 384 regulator-min-microvolt = <900000>;
385 regulator-max-microvolt = <1800000>; 385 regulator-max-microvolt = <1800000>;
386 regulator-boot-on; 386 regulator-boot-on;
387 regulator-always-on; 387 regulator-always-on;
388 }; 388 };
389 389
390 ldo7_reg: regulator@14 { 390 ldo7_reg: regulator@14 {
391 reg = <14>; 391 reg = <14>;
392 regulator-compatible = "ldo7"; 392 regulator-compatible = "ldo7";
393 regulator-min-microvolt = <1800000>; 393 regulator-min-microvolt = <1800000>;
394 regulator-max-microvolt = <3300000>; 394 regulator-max-microvolt = <3300000>;
395 }; 395 };
396 }; 396 };
397 }; 397 };
398 }; 398 };
399 399
400 &i2c2 { 400 &i2c2 {
401 clock-frequency = <400000>; 401 clock-frequency = <400000>;
402 pinctrl-names = "default", "gpio"; 402 pinctrl-names = "default", "gpio";
403 pinctrl-0 = <&pinctrl_i2c2>; 403 pinctrl-0 = <&pinctrl_i2c2>;
404 pinctrl-1 = <&pinctrl_i2c2_gpio>; 404 pinctrl-1 = <&pinctrl_i2c2_gpio>;
405 scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; 405 scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
406 sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; 406 sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
407 status = "okay"; 407 status = "okay";
408 408
409 typec_ptn5110_1: ptn5110@50 { 409 typec_ptn5110_1: ptn5110@50 {
410 compatible = "usb,tcpci"; 410 compatible = "usb,tcpci";
411 reg = <0x50>; 411 reg = <0x50>;
412 src-pdos = <0x380190c8>; 412 src-pdos = <0x380190c8>;
413 snk-pdos = <0x380190c8 0x3802d0c8>; 413 snk-pdos = <0x380190c8 0x3802d0c8>;
414 max-snk-mv = <9000>; 414 max-snk-mv = <9000>;
415 max-snk-ma = <2000>; 415 max-snk-ma = <2000>;
416 op-snk-mw = <9000>; 416 op-snk-mw = <9000>;
417 max-snk-mw = <18000>; 417 max-snk-mw = <18000>;
418 port-type = "drp"; 418 port-type = "drp";
419 default-role = "sink"; 419 default-role = "sink";
420 }; 420 };
421 421
422 typec_ptn5110_2: ptn5110@52 { 422 typec_ptn5110_2: ptn5110@52 {
423 compatible = "usb,tcpci"; 423 compatible = "usb,tcpci";
424 reg = <0x52>; 424 reg = <0x52>;
425 src-pdos = <0x380190c8>; 425 src-pdos = <0x380190c8>;
426 snk-pdos = <0x380190c8 0x3802d0c8>; 426 snk-pdos = <0x380190c8 0x3802d0c8>;
427 max-snk-mv = <9000>; 427 max-snk-mv = <9000>;
428 max-snk-ma = <2000>; 428 max-snk-ma = <2000>;
429 op-snk-mw = <9000>; 429 op-snk-mw = <9000>;
430 max-snk-mw = <18000>; 430 max-snk-mw = <18000>;
431 port-type = "drp"; 431 port-type = "drp";
432 default-role = "sink"; 432 default-role = "sink";
433 }; 433 };
434 }; 434 };
435 435
436 &i2c3 { 436 &i2c3 {
437 clock-frequency = <100000>; 437 clock-frequency = <100000>;
438 pinctrl-names = "default", "gpio"; 438 pinctrl-names = "default", "gpio";
439 pinctrl-0 = <&pinctrl_i2c3>; 439 pinctrl-0 = <&pinctrl_i2c3>;
440 pinctrl-1 = <&pinctrl_i2c3_gpio>; 440 pinctrl-1 = <&pinctrl_i2c3_gpio>;
441 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; 441 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
442 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; 442 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
443 status = "okay"; 443 status = "okay";
444 }; 444 };
445 445
446 &flexspi0 { 446 &flexspi0 {
447 pinctrl-names = "default"; 447 pinctrl-names = "default";
448 pinctrl-0 = <&pinctrl_flexspi0>; 448 pinctrl-0 = <&pinctrl_flexspi0>;
449 status = "okay"; 449 status = "okay";
450 450
451 flash0: n25q256a@0 { 451 flash0: n25q256a@0 {
452 reg = <0>; 452 reg = <0>;
453 #address-cells = <1>; 453 #address-cells = <1>;
454 #size-cells = <1>; 454 #size-cells = <1>;
455 compatible = "spi-flash"; 455 compatible = "spi-flash";
456 spi-max-frequency = <29000000>; 456 spi-max-frequency = <29000000>;
457 spi-nor,ddr-quad-read-dummy = <8>; 457 spi-nor,ddr-quad-read-dummy = <8>;
458 }; 458 };
459 }; 459 };
460 460
461 &fec1 { 461 &fec1 {
462 pinctrl-names = "default"; 462 pinctrl-names = "default";
463 pinctrl-0 = <&pinctrl_fec1>; 463 pinctrl-0 = <&pinctrl_fec1>;
464 phy-mode = "rgmii-id"; 464 phy-mode = "rgmii-id";
465 phy-handle = <&ethphy0>; 465 phy-handle = <&ethphy0>;
466 fsl,magic-packet; 466 fsl,magic-packet;
467 status = "okay"; 467 status = "okay";
468 468
469 mdio { 469 mdio {
470 #address-cells = <1>; 470 #address-cells = <1>;
471 #size-cells = <0>; 471 #size-cells = <0>;
472 472
473 ethphy0: ethernet-phy@0 { 473 ethphy0: ethernet-phy@0 {
474 compatible = "ethernet-phy-ieee802.3-c22"; 474 compatible = "ethernet-phy-ieee802.3-c22";
475 reg = <0>; 475 reg = <0>;
476 at803x,led-act-blind-workaround; 476 at803x,led-act-blind-workaround;
477 at803x,eee-okay; 477 at803x,eee-okay;
478 at803x,vddio-1p8v; 478 at803x,vddio-1p8v;
479 }; 479 };
480 }; 480 };
481 }; 481 };
482 482
483 &uart2 { /* console */ 483 &uart2 { /* console */
484 pinctrl-names = "default"; 484 pinctrl-names = "default";
485 pinctrl-0 = <&pinctrl_uart2>; 485 pinctrl-0 = <&pinctrl_uart2>;
486 status = "okay"; 486 status = "okay";
487 }; 487 };
488 488
489 &usdhc2 { 489 &usdhc2 {
490 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 490 pinctrl-names = "default", "state_100mhz", "state_200mhz";
491 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 491 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
492 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 492 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
493 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 493 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
494 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 494 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
495 bus-width = <4>; 495 bus-width = <4>;
496 vmmc-supply = <&reg_usdhc2_vmmc>; 496 vmmc-supply = <&reg_usdhc2_vmmc>;
497 status = "okay"; 497 status = "okay";
498 }; 498 };
499 499
500 &usdhc3 { 500 &usdhc3 {
501 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 501 pinctrl-names = "default", "state_100mhz", "state_200mhz";
502 pinctrl-0 = <&pinctrl_usdhc3>; 502 pinctrl-0 = <&pinctrl_usdhc3>;
503 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 503 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
504 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 504 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
505 bus-width = <8>; 505 bus-width = <8>;
506 non-removable; 506 non-removable;
507 status = "okay"; 507 status = "okay";
508 }; 508 };
509 509
510 &wdog1 { 510 &wdog1 {
511 pinctrl-names = "default"; 511 pinctrl-names = "default";
512 pinctrl-0 = <&pinctrl_wdog>; 512 pinctrl-0 = <&pinctrl_wdog>;
513 fsl,ext-reset-output; 513 fsl,ext-reset-output;
514 status = "okay"; 514 status = "okay";
515 }; 515 };
516 516
517 &A53_0 { 517 &A53_0 {
518 arm-supply = <&buck2_reg>; 518 arm-supply = <&buck2_reg>;
519 }; 519 };
520 520
521 &usbotg1 { 521 &usbotg1 {
522 status = "okay"; 522 status = "okay";
523 extcon = <&typec_ptn5110_1>; 523 extcon = <&typec_ptn5110_1>;
524 }; 524 };
525 525
526 &usbotg2 { 526 &usbotg2 {
527 status = "okay"; 527 status = "okay";
528 extcon = <&typec_ptn5110_2>; 528 extcon = <&typec_ptn5110_2>;
529 }; 529 };
530 530
arch/arm/dts/imx6qdl-sabreauto.dtsi
Diff comments   View file @ 4daafb3
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 // 2 //
3 // Copyright 2012 Freescale Semiconductor, Inc. 3 // Copyright 2012 Freescale Semiconductor, Inc.
4 // Copyright 2011 Linaro Ltd. 4 // Copyright 2011 Linaro Ltd.
5 // Copyright 2017 NXP. 5 // Copyright 2017 NXP.
6 6
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h> 8 #include <dt-bindings/input/input.h>
9 9
10 / { 10 / {
11 aliases { 11 aliases {
12 mxcfb0 = &mxcfb1; 12 mxcfb0 = &mxcfb1;
13 mxcfb1 = &mxcfb2; 13 mxcfb1 = &mxcfb2;
14 mxcfb2 = &mxcfb3; 14 mxcfb2 = &mxcfb3;
15 mxcfb3 = &mxcfb4; 15 mxcfb3 = &mxcfb4;
16 }; 16 };
17 17
18 chosen { 18 chosen {
19 stdout-path = &uart4; 19 stdout-path = &uart4;
20 }; 20 };
21 21
22 gpio-keys { 22 gpio-keys {
23 compatible = "gpio-keys1"; 23 compatible = "gpio-keys1";
24 pinctrl-names = "default"; 24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_gpio_keys>; 25 pinctrl-0 = <&pinctrl_gpio_keys>;
26 26
27 home { 27 home {
28 label = "Home"; 28 label = "Home";
29 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 29 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
30 gpio-key,wakeup; 30 gpio-key,wakeup;
31 linux,code = <KEY_HOME>; 31 linux,code = <KEY_HOME>;
32 }; 32 };
33 33
34 back { 34 back {
35 label = "Back"; 35 label = "Back";
36 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 36 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
37 gpio-key,wakeup; 37 gpio-key,wakeup;
38 linux,code = <KEY_BACK>; 38 linux,code = <KEY_BACK>;
39 }; 39 };
40 40
41 program { 41 program {
42 label = "Program"; 42 label = "Program";
43 gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 43 gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
44 gpio-key,wakeup; 44 gpio-key,wakeup;
45 linux,code = <KEY_PROGRAM>; 45 linux,code = <KEY_PROGRAM>;
46 }; 46 };
47 47
48 volume-up { 48 volume-up {
49 label = "Volume Up"; 49 label = "Volume Up";
50 gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; 50 gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
51 gpio-key,wakeup; 51 gpio-key,wakeup;
52 linux,code = <KEY_VOLUMEUP>; 52 linux,code = <KEY_VOLUMEUP>;
53 }; 53 };
54 54
55 volume-down { 55 volume-down {
56 label = "Volume Down"; 56 label = "Volume Down";
57 gpios = <&gpio5 14 GPIO_ACTIVE_LOW>; 57 gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
58 gpio-key,wakeup; 58 gpio-key,wakeup;
59 linux,code = <KEY_VOLUMEDOWN>; 59 linux,code = <KEY_VOLUMEDOWN>;
60 }; 60 };
61 }; 61 };
62 62
63 memory: memory { 63 memory: memory {
64 reg = <0x10000000 0x80000000>; 64 reg = <0x10000000 0x80000000>;
65 }; 65 };
66 66
67 leds { 67 leds {
68 compatible = "gpio-leds"; 68 compatible = "gpio-leds";
69 pinctrl-names = "default"; 69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_gpio_leds>; 70 pinctrl-0 = <&pinctrl_gpio_leds>;
71 71
72 user { 72 user {
73 label = "debug"; 73 label = "debug";
74 gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; 74 gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
75 }; 75 };
76 }; 76 };
77 77
78 clocks { 78 clocks {
79 codec_osc: anaclk2 { 79 codec_osc: anaclk2 {
80 compatible = "fixed-clock"; 80 compatible = "fixed-clock";
81 #clock-cells = <0>; 81 #clock-cells = <0>;
82 clock-frequency = <24576000>; 82 clock-frequency = <24576000>;
83 }; 83 };
84 }; 84 };
85 85
86 regulators { 86 regulators {
87 compatible = "simple-bus"; 87 compatible = "simple-bus";
88 #address-cells = <1>; 88 #address-cells = <1>;
89 #size-cells = <0>; 89 #size-cells = <0>;
90 90
91 reg_audio: regulator@0 { 91 reg_audio: regulator@0 {
92 compatible = "regulator-fixed"; 92 compatible = "regulator-fixed";
93 reg = <0>; 93 reg = <0>;
94 regulator-name = "cs42888_supply"; 94 regulator-name = "cs42888_supply";
95 regulator-min-microvolt = <3300000>; 95 regulator-min-microvolt = <3300000>;
96 regulator-max-microvolt = <3300000>; 96 regulator-max-microvolt = <3300000>;
97 regulator-always-on; 97 regulator-always-on;
98 }; 98 };
99 99
100 reg_3p3v: 3p3v { 100 reg_3p3v: 3p3v {
101 compatible = "regulator-fixed"; 101 compatible = "regulator-fixed";
102 regulator-name = "3P3V"; 102 regulator-name = "3P3V";
103 regulator-min-microvolt = <3300000>; 103 regulator-min-microvolt = <3300000>;
104 regulator-max-microvolt = <3300000>; 104 regulator-max-microvolt = <3300000>;
105 regulator-always-on; 105 regulator-always-on;
106 }; 106 };
107 107
108 reg_usb_h1_vbus: regulator@1 { 108 reg_usb_h1_vbus: regulator@1 {
109 compatible = "regulator-fixed"; 109 compatible = "regulator-fixed";
110 reg = <1>; 110 reg = <1>;
111 regulator-name = "usb_h1_vbus"; 111 regulator-name = "usb_h1_vbus";
112 regulator-min-microvolt = <5000000>; 112 regulator-min-microvolt = <5000000>;
113 regulator-max-microvolt = <5000000>; 113 regulator-max-microvolt = <5000000>;
114 gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; 114 gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
115 enable-active-high; 115 enable-active-high;
116 }; 116 };
117 117
118 reg_usb_otg_vbus: regulator@2 { 118 reg_usb_otg_vbus: regulator@2 {
119 compatible = "regulator-fixed"; 119 compatible = "regulator-fixed";
120 reg = <2>; 120 reg = <2>;
121 regulator-name = "usb_otg_vbus"; 121 regulator-name = "usb_otg_vbus";
122 regulator-min-microvolt = <5000000>; 122 regulator-min-microvolt = <5000000>;
123 regulator-max-microvolt = <5000000>; 123 regulator-max-microvolt = <5000000>;
124 gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>; 124 gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
125 enable-active-high; 125 enable-active-high;
126 }; 126 };
127 127
128 reg_si4763_vio1: regulator@3 { 128 reg_si4763_vio1: regulator@3 {
129 compatible = "regulator-fixed"; 129 compatible = "regulator-fixed";
130 reg = <3>; 130 reg = <3>;
131 regulator-name = "vio1"; 131 regulator-name = "vio1";
132 regulator-min-microvolt = <3300000>; 132 regulator-min-microvolt = <3300000>;
133 regulator-max-microvolt = <3300000>; 133 regulator-max-microvolt = <3300000>;
134 regulator-always-on; 134 regulator-always-on;
135 }; 135 };
136 136
137 reg_si4763_vio2: regulator@4 { 137 reg_si4763_vio2: regulator@4 {
138 compatible = "regulator-fixed"; 138 compatible = "regulator-fixed";
139 reg = <4>; 139 reg = <4>;
140 regulator-name = "vio2"; 140 regulator-name = "vio2";
141 regulator-min-microvolt = <3300000>; 141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <3300000>; 142 regulator-max-microvolt = <3300000>;
143 regulator-always-on; 143 regulator-always-on;
144 }; 144 };
145 145
146 reg_si4763_vd: regulator@5 { 146 reg_si4763_vd: regulator@5 {
147 compatible = "regulator-fixed"; 147 compatible = "regulator-fixed";
148 reg = <5>; 148 reg = <5>;
149 regulator-name = "vd"; 149 regulator-name = "vd";
150 regulator-min-microvolt = <3300000>; 150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>; 151 regulator-max-microvolt = <3300000>;
152 regulator-always-on; 152 regulator-always-on;
153 }; 153 };
154 154
155 reg_si4763_va: regulator@6 { 155 reg_si4763_va: regulator@6 {
156 compatible = "regulator-fixed"; 156 compatible = "regulator-fixed";
157 reg = <6>; 157 reg = <6>;
158 regulator-name = "va"; 158 regulator-name = "va";
159 regulator-min-microvolt = <5000000>; 159 regulator-min-microvolt = <5000000>;
160 regulator-max-microvolt = <5000000>; 160 regulator-max-microvolt = <5000000>;
161 regulator-always-on; 161 regulator-always-on;
162 }; 162 };
163 163
164 reg_sd3_vmmc: regulator@7 { 164 reg_sd3_vmmc: regulator@7 {
165 compatible = "regulator-fixed"; 165 compatible = "regulator-fixed";
166 regulator-name = "P3V3_SDa_SWITCHED"; 166 regulator-name = "P3V3_SDa_SWITCHED";
167 regulator-min-microvolt = <3300000>; 167 regulator-min-microvolt = <3300000>;
168 regulator-max-microvolt = <3300000>; 168 regulator-max-microvolt = <3300000>;
169 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; 169 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
170 enable-active-high; 170 enable-active-high;
171 off-on-delay = <20000>; 171 u-boot,off-on-delay-us = <20000>;
172 /* remove below line to enable this regulator */ 172 /* remove below line to enable this regulator */
173 status = "disabled"; 173 status = "disabled";
174 }; 174 };
175 175
176 reg_can_en: regulator@8 { 176 reg_can_en: regulator@8 {
177 compatible = "regulator-fixed"; 177 compatible = "regulator-fixed";
178 reg = <8>; 178 reg = <8>;
179 regulator-name = "can-en"; 179 regulator-name = "can-en";
180 regulator-min-microvolt = <3300000>; 180 regulator-min-microvolt = <3300000>;
181 regulator-max-microvolt = <3300000>; 181 regulator-max-microvolt = <3300000>;
182 gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>; 182 gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>;
183 enable-active-high; 183 enable-active-high;
184 }; 184 };
185 185
186 reg_can_stby: regulator@9 { 186 reg_can_stby: regulator@9 {
187 compatible = "regulator-fixed"; 187 compatible = "regulator-fixed";
188 reg = <9>; 188 reg = <9>;
189 regulator-name = "can-stby"; 189 regulator-name = "can-stby";
190 regulator-min-microvolt = <3300000>; 190 regulator-min-microvolt = <3300000>;
191 regulator-max-microvolt = <3300000>; 191 regulator-max-microvolt = <3300000>;
192 gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; 192 gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
193 enable-active-high; 193 enable-active-high;
194 vin-supply = <&reg_can_en>; 194 vin-supply = <&reg_can_en>;
195 }; 195 };
196 }; 196 };
197 197
198 hannstar_cabc { 198 hannstar_cabc {
199 compatible = "hannstar,cabc"; 199 compatible = "hannstar,cabc";
200 200
201 lvds_share { 201 lvds_share {
202 gpios = <&max7310_a 0 GPIO_ACTIVE_HIGH>; 202 gpios = <&max7310_a 0 GPIO_ACTIVE_HIGH>;
203 }; 203 };
204 }; 204 };
205 205
206 sound-hdmi { 206 sound-hdmi {
207 compatible = "fsl,imx6q-audio-hdmi", 207 compatible = "fsl,imx6q-audio-hdmi",
208 "fsl,imx-audio-hdmi"; 208 "fsl,imx-audio-hdmi";
209 model = "imx-audio-hdmi"; 209 model = "imx-audio-hdmi";
210 hdmi-controller = <&hdmi_audio>; 210 hdmi-controller = <&hdmi_audio>;
211 }; 211 };
212 212
213 mxcfb1: fb@0 { 213 mxcfb1: fb@0 {
214 compatible = "fsl,mxc_sdc_fb"; 214 compatible = "fsl,mxc_sdc_fb";
215 disp_dev = "ldb"; 215 disp_dev = "ldb";
216 interface_pix_fmt = "RGB666"; 216 interface_pix_fmt = "RGB666";
217 default_bpp = <16>; 217 default_bpp = <16>;
218 int_clk = <0>; 218 int_clk = <0>;
219 late_init = <0>; 219 late_init = <0>;
220 status = "disabled"; 220 status = "disabled";
221 }; 221 };
222 222
223 mxcfb2: fb@1 { 223 mxcfb2: fb@1 {
224 compatible = "fsl,mxc_sdc_fb"; 224 compatible = "fsl,mxc_sdc_fb";
225 disp_dev = "hdmi"; 225 disp_dev = "hdmi";
226 interface_pix_fmt = "RGB24"; 226 interface_pix_fmt = "RGB24";
227 mode_str ="1920x1080M@60"; 227 mode_str ="1920x1080M@60";
228 default_bpp = <24>; 228 default_bpp = <24>;
229 int_clk = <0>; 229 int_clk = <0>;
230 late_init = <0>; 230 late_init = <0>;
231 status = "disabled"; 231 status = "disabled";
232 }; 232 };
233 233
234 mxcfb3: fb@2 { 234 mxcfb3: fb@2 {
235 compatible = "fsl,mxc_sdc_fb"; 235 compatible = "fsl,mxc_sdc_fb";
236 disp_dev = "lcd"; 236 disp_dev = "lcd";
237 interface_pix_fmt = "RGB565"; 237 interface_pix_fmt = "RGB565";
238 mode_str ="CLAA-WVGA"; 238 mode_str ="CLAA-WVGA";
239 default_bpp = <16>; 239 default_bpp = <16>;
240 int_clk = <0>; 240 int_clk = <0>;
241 late_init = <0>; 241 late_init = <0>;
242 status = "disabled"; 242 status = "disabled";
243 }; 243 };
244 244
245 mxcfb4: fb@3 { 245 mxcfb4: fb@3 {
246 compatible = "fsl,mxc_sdc_fb"; 246 compatible = "fsl,mxc_sdc_fb";
247 disp_dev = "ldb"; 247 disp_dev = "ldb";
248 interface_pix_fmt = "RGB666"; 248 interface_pix_fmt = "RGB666";
249 default_bpp = <16>; 249 default_bpp = <16>;
250 int_clk = <0>; 250 int_clk = <0>;
251 late_init = <0>; 251 late_init = <0>;
252 status = "disabled"; 252 status = "disabled";
253 }; 253 };
254 254
255 clocks { 255 clocks {
256 codec_osc: anaclk2 { 256 codec_osc: anaclk2 {
257 compatible = "fixed-clock"; 257 compatible = "fixed-clock";
258 #clock-cells = <0>; 258 #clock-cells = <0>;
259 clock-frequency = <24576000>; 259 clock-frequency = <24576000>;
260 }; 260 };
261 }; 261 };
262 262
263 sound-cs42888 { 263 sound-cs42888 {
264 compatible = "fsl,imx6-sabreauto-cs42888", 264 compatible = "fsl,imx6-sabreauto-cs42888",
265 "fsl,imx-audio-cs42888"; 265 "fsl,imx-audio-cs42888";
266 model = "imx-cs42888"; 266 model = "imx-cs42888";
267 esai-controller = <&esai>; 267 esai-controller = <&esai>;
268 asrc-controller = <&asrc>; 268 asrc-controller = <&asrc>;
269 audio-codec = <&codec>; 269 audio-codec = <&codec>;
270 }; 270 };
271 271
272 sound-fm { 272 sound-fm {
273 compatible = "fsl,imx-audio-si476x", 273 compatible = "fsl,imx-audio-si476x",
274 "fsl,imx-tuner-si476x"; 274 "fsl,imx-tuner-si476x";
275 model = "imx-radio-si4763"; 275 model = "imx-radio-si4763";
276 ssi-controller = <&ssi2>; 276 ssi-controller = <&ssi2>;
277 fm-controller = <&si476x_codec>; 277 fm-controller = <&si476x_codec>;
278 mux-int-port = <2>; 278 mux-int-port = <2>;
279 mux-ext-port = <5>; 279 mux-ext-port = <5>;
280 }; 280 };
281 281
282 sound-spdif { 282 sound-spdif {
283 compatible = "fsl,imx-audio-spdif", 283 compatible = "fsl,imx-audio-spdif",
284 "fsl,imx-sabreauto-spdif"; 284 "fsl,imx-sabreauto-spdif";
285 model = "imx-spdif"; 285 model = "imx-spdif";
286 spdif-controller = <&spdif>; 286 spdif-controller = <&spdif>;
287 spdif-in; 287 spdif-in;
288 }; 288 };
289 289
290 backlight { 290 backlight {
291 compatible = "pwm-backlight"; 291 compatible = "pwm-backlight";
292 pwms = <&pwm3 0 5000000>; 292 pwms = <&pwm3 0 5000000>;
293 brightness-levels = <0 4 8 16 32 64 128 255>; 293 brightness-levels = <0 4 8 16 32 64 128 255>;
294 default-brightness-level = <7>; 294 default-brightness-level = <7>;
295 status = "okay"; 295 status = "okay";
296 }; 296 };
297 297
298 i2cmux { 298 i2cmux {
299 compatible = "i2c-mux-gpio"; 299 compatible = "i2c-mux-gpio";
300 #address-cells = <1>; 300 #address-cells = <1>;
301 #size-cells = <0>; 301 #size-cells = <0>;
302 pinctrl-names = "default"; 302 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_i2c3mux>; 303 pinctrl-0 = <&pinctrl_i2c3mux>;
304 mux-gpios = <&gpio5 4 0>; 304 mux-gpios = <&gpio5 4 0>;
305 i2c-parent = <&i2c3>; 305 i2c-parent = <&i2c3>;
306 idle-state = <0>; 306 idle-state = <0>;
307 307
308 i2c@1 { 308 i2c@1 {
309 #address-cells = <1>; 309 #address-cells = <1>;
310 #size-cells = <0>; 310 #size-cells = <0>;
311 reg = <1>; 311 reg = <1>;
312 312
313 adv7180: adv7180@21 { 313 adv7180: adv7180@21 {
314 compatible = "adv,adv7180"; 314 compatible = "adv,adv7180";
315 reg = <0x21>; 315 reg = <0x21>;
316 pinctrl-names = "default"; 316 pinctrl-names = "default";
317 pinctrl-0 = <&pinctrl_ipu1_1>; 317 pinctrl-0 = <&pinctrl_ipu1_1>;
318 clocks = <&clks IMX6QDL_CLK_CKO>; 318 clocks = <&clks IMX6QDL_CLK_CKO>;
319 clock-names = "csi_mclk"; 319 clock-names = "csi_mclk";
320 DOVDD-supply = <&reg_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */ 320 DOVDD-supply = <&reg_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */
321 AVDD-supply = <&reg_3p3v>; /* 1.8v */ 321 AVDD-supply = <&reg_3p3v>; /* 1.8v */
322 DVDD-supply = <&reg_3p3v>; /* 1.8v */ 322 DVDD-supply = <&reg_3p3v>; /* 1.8v */
323 PVDD-supply = <&reg_3p3v>; /* 1.8v */ 323 PVDD-supply = <&reg_3p3v>; /* 1.8v */
324 pwn-gpios = <&max7310_b 2 0>; 324 pwn-gpios = <&max7310_b 2 0>;
325 csi_id = <0>; 325 csi_id = <0>;
326 mclk = <24000000>; 326 mclk = <24000000>;
327 mclk_source = <0>; 327 mclk_source = <0>;
328 cvbs = <1>; 328 cvbs = <1>;
329 }; 329 };
330 330
331 max7310_a: gpio@30 { 331 max7310_a: gpio@30 {
332 compatible = "maxim,max7310"; 332 compatible = "maxim,max7310";
333 reg = <0x30>; 333 reg = <0x30>;
334 gpio-controller; 334 gpio-controller;
335 #gpio-cells = <2>; 335 #gpio-cells = <2>;
336 }; 336 };
337 337
338 max7310_b: gpio@32 { 338 max7310_b: gpio@32 {
339 compatible = "maxim,max7310"; 339 compatible = "maxim,max7310";
340 reg = <0x32>; 340 reg = <0x32>;
341 gpio-controller; 341 gpio-controller;
342 #gpio-cells = <2>; 342 #gpio-cells = <2>;
343 pinctrl-names = "default"; 343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_max7310>; 344 pinctrl-0 = <&pinctrl_max7310>;
345 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 345 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
346 }; 346 };
347 347
348 max7310_c: gpio@34 { 348 max7310_c: gpio@34 {
349 compatible = "maxim,max7310"; 349 compatible = "maxim,max7310";
350 reg = <0x34>; 350 reg = <0x34>;
351 gpio-controller; 351 gpio-controller;
352 #gpio-cells = <2>; 352 #gpio-cells = <2>;
353 }; 353 };
354 354
355 isl29023@44 { 355 isl29023@44 {
356 compatible = "fsl,isl29023"; 356 compatible = "fsl,isl29023";
357 reg = <0x44>; 357 reg = <0x44>;
358 rext = <499>; 358 rext = <499>;
359 interrupt-parent = <&gpio5>; 359 interrupt-parent = <&gpio5>;
360 interrupts = <17 2>; 360 interrupts = <17 2>;
361 }; 361 };
362 362
363 mag3110@0e { 363 mag3110@0e {
364 compatible = "fsl,mag3110"; 364 compatible = "fsl,mag3110";
365 reg = <0x0e>; 365 reg = <0x0e>;
366 position = <2>; 366 position = <2>;
367 interrupt-parent = <&gpio2>; 367 interrupt-parent = <&gpio2>;
368 interrupts = <29 1>; 368 interrupts = <29 1>;
369 }; 369 };
370 370
371 mma8451@1c { 371 mma8451@1c {
372 compatible = "fsl,mma8451"; 372 compatible = "fsl,mma8451";
373 reg = <0x1c>; 373 reg = <0x1c>;
374 position = <7>; 374 position = <7>;
375 interrupt-parent = <&gpio6>; 375 interrupt-parent = <&gpio6>;
376 interrupts = <31 8>; 376 interrupts = <31 8>;
377 interrupt-route = <1>; 377 interrupt-route = <1>;
378 }; 378 };
379 }; 379 };
380 }; 380 };
381 381
382 v4l2_cap_0 { 382 v4l2_cap_0 {
383 compatible = "fsl,imx6q-v4l2-capture"; 383 compatible = "fsl,imx6q-v4l2-capture";
384 ipu_id = <0>; 384 ipu_id = <0>;
385 csi_id = <0>; 385 csi_id = <0>;
386 mclk_source = <0>; 386 mclk_source = <0>;
387 status = "okay"; 387 status = "okay";
388 }; 388 };
389 389
390 v4l2_out { 390 v4l2_out {
391 compatible = "fsl,mxc_v4l2_output"; 391 compatible = "fsl,mxc_v4l2_output";
392 status = "okay"; 392 status = "okay";
393 }; 393 };
394 }; 394 };
395 395
396 &ipu1_csi0_from_ipu1_csi0_mux { 396 &ipu1_csi0_from_ipu1_csi0_mux {
397 bus-width = <8>; 397 bus-width = <8>;
398 }; 398 };
399 399
400 &ipu1_csi0_mux_from_parallel_sensor { 400 &ipu1_csi0_mux_from_parallel_sensor {
401 /* Downstream driver doesn't use endpoints */ 401 /* Downstream driver doesn't use endpoints */
402 /* 402 /*
403 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; 403 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
404 */ 404 */
405 bus-width = <8>; 405 bus-width = <8>;
406 }; 406 };
407 407
408 &ipu1_csi0 { 408 &ipu1_csi0 {
409 pinctrl-names = "default"; 409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_ipu1_csi0>; 410 pinctrl-0 = <&pinctrl_ipu1_csi0>;
411 }; 411 };
412 412
413 &audmux { 413 &audmux {
414 pinctrl-names = "default"; 414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_audmux>; 415 pinctrl-0 = <&pinctrl_audmux>;
416 status = "okay"; 416 status = "okay";
417 }; 417 };
418 418
419 &clks { 419 &clks {
420 assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>, 420 assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
421 <&clks IMX6QDL_PLL4_BYPASS>, 421 <&clks IMX6QDL_PLL4_BYPASS>,
422 <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 422 <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
423 <&clks IMX6QDL_CLK_LDB_DI1_SEL>, 423 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
424 <&clks IMX6QDL_CLK_PLL4_POST_DIV>; 424 <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
425 assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, 425 assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
426 <&clks IMX6QDL_PLL4_BYPASS_SRC>, 426 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
427 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, 427 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
428 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; 428 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
429 assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>; 429 assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
430 }; 430 };
431 431
432 &dcic1 { 432 &dcic1 {
433 dcic_id = <0>; 433 dcic_id = <0>;
434 dcic_mux = "dcic-hdmi"; 434 dcic_mux = "dcic-hdmi";
435 status = "okay"; 435 status = "okay";
436 }; 436 };
437 437
438 &dcic2 { 438 &dcic2 {
439 dcic_id = <1>; 439 dcic_id = <1>;
440 dcic_mux = "dcic-lvds0"; 440 dcic_mux = "dcic-lvds0";
441 status = "okay"; 441 status = "okay";
442 }; 442 };
443 443
444 &ecspi1 { 444 &ecspi1 {
445 fsl,spi-num-chipselects = <1>; 445 fsl,spi-num-chipselects = <1>;
446 cs-gpios = <&gpio3 19 0>; 446 cs-gpios = <&gpio3 19 0>;
447 pinctrl-names = "default"; 447 pinctrl-names = "default";
448 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 448 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
449 status = "disabled"; /* pin conflict with WEIM NOR */ 449 status = "disabled"; /* pin conflict with WEIM NOR */
450 450
451 flash: m25p80@0 { 451 flash: m25p80@0 {
452 #address-cells = <1>; 452 #address-cells = <1>;
453 #size-cells = <1>; 453 #size-cells = <1>;
454 compatible = "st,m25p32", "jedec,spi-nor"; 454 compatible = "st,m25p32", "jedec,spi-nor";
455 spi-max-frequency = <20000000>; 455 spi-max-frequency = <20000000>;
456 reg = <0>; 456 reg = <0>;
457 }; 457 };
458 }; 458 };
459 459
460 &esai { 460 &esai {
461 pinctrl-names = "default"; 461 pinctrl-names = "default";
462 pinctrl-0 = <&pinctrl_esai>; 462 pinctrl-0 = <&pinctrl_esai>;
463 assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>, 463 assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
464 <&clks IMX6QDL_CLK_ESAI_EXTAL>; 464 <&clks IMX6QDL_CLK_ESAI_EXTAL>;
465 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; 465 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
466 assigned-clock-rates = <0>, <24576000>; 466 assigned-clock-rates = <0>, <24576000>;
467 status = "okay"; 467 status = "okay";
468 }; 468 };
469 469
470 &fec { 470 &fec {
471 pinctrl-names = "default"; 471 pinctrl-names = "default";
472 pinctrl-0 = <&pinctrl_enet>; 472 pinctrl-0 = <&pinctrl_enet>;
473 phy-mode = "rgmii"; 473 phy-mode = "rgmii";
474 fsl,magic-packet; 474 fsl,magic-packet;
475 fsl,err006687-workaround-present; 475 fsl,err006687-workaround-present;
476 status = "okay"; 476 status = "okay";
477 }; 477 };
478 478
479 &can1 { 479 &can1 {
480 pinctrl-names = "default"; 480 pinctrl-names = "default";
481 pinctrl-0 = <&pinctrl_flexcan1>; 481 pinctrl-0 = <&pinctrl_flexcan1>;
482 pinctrl-assert-gpios = <&max7310_b 3 GPIO_ACTIVE_HIGH>; /* TX */ 482 pinctrl-assert-gpios = <&max7310_b 3 GPIO_ACTIVE_HIGH>; /* TX */
483 xceiver-supply = <&reg_can_stby>; 483 xceiver-supply = <&reg_can_stby>;
484 status = "disabled"; /* pin conflict with fec */ 484 status = "disabled"; /* pin conflict with fec */
485 }; 485 };
486 486
487 &can2 { 487 &can2 {
488 pinctrl-names = "default"; 488 pinctrl-names = "default";
489 pinctrl-0 = <&pinctrl_flexcan2>; 489 pinctrl-0 = <&pinctrl_flexcan2>;
490 xceiver-supply = <&reg_can_stby>; 490 xceiver-supply = <&reg_can_stby>;
491 status = "okay"; 491 status = "okay";
492 }; 492 };
493 493
494 &gpmi { 494 &gpmi {
495 pinctrl-names = "default"; 495 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_gpmi_nand>; 496 pinctrl-0 = <&pinctrl_gpmi_nand>;
497 status = "disabled"; /* pin conflict with uart3 */ 497 status = "disabled"; /* pin conflict with uart3 */
498 nand-on-flash-bbt; 498 nand-on-flash-bbt;
499 }; 499 };
500 500
501 &hdmi_audio { 501 &hdmi_audio {
502 status = "okay"; 502 status = "okay";
503 }; 503 };
504 504
505 &hdmi_cec { 505 &hdmi_cec {
506 pinctrl-names = "default"; 506 pinctrl-names = "default";
507 pinctrl-0 = <&pinctrl_hdmi_cec>; 507 pinctrl-0 = <&pinctrl_hdmi_cec>;
508 status = "okay"; 508 status = "okay";
509 }; 509 };
510 510
511 &hdmi_core { 511 &hdmi_core {
512 ipu_id = <0>; 512 ipu_id = <0>;
513 disp_id = <1>; 513 disp_id = <1>;
514 status = "okay"; 514 status = "okay";
515 }; 515 };
516 516
517 &hdmi_video { 517 &hdmi_video {
518 fsl,phy_reg_vlev = <0x0294>; 518 fsl,phy_reg_vlev = <0x0294>;
519 fsl,phy_reg_cksymtx = <0x800d>; 519 fsl,phy_reg_cksymtx = <0x800d>;
520 status = "okay"; 520 status = "okay";
521 }; 521 };
522 522
523 &i2c2 { 523 &i2c2 {
524 clock-frequency = <100000>; 524 clock-frequency = <100000>;
525 pinctrl-names = "default", "gpio"; 525 pinctrl-names = "default", "gpio";
526 pinctrl-0 = <&pinctrl_i2c2>; 526 pinctrl-0 = <&pinctrl_i2c2>;
527 pinctrl-1 = <&pinctrl_i2c2_gpio>; 527 pinctrl-1 = <&pinctrl_i2c2_gpio>;
528 scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; 528 scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
529 sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; 529 sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
530 status = "okay"; 530 status = "okay";
531 531
532 egalax_ts@04 { 532 egalax_ts@04 {
533 compatible = "eeti,egalax_ts"; 533 compatible = "eeti,egalax_ts";
534 reg = <0x04>; 534 reg = <0x04>;
535 pinctrl-names = "default"; 535 pinctrl-names = "default";
536 pinctrl-0 = <&pinctrl_egalax_int>; 536 pinctrl-0 = <&pinctrl_egalax_int>;
537 interrupt-parent = <&gpio2>; 537 interrupt-parent = <&gpio2>;
538 interrupts = <28 2>; 538 interrupts = <28 2>;
539 wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; 539 wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
540 }; 540 };
541 541
542 pmic: pfuze100@08 { 542 pmic: pfuze100@08 {
543 compatible = "fsl,pfuze100"; 543 compatible = "fsl,pfuze100";
544 reg = <0x08>; 544 reg = <0x08>;
545 545
546 regulators { 546 regulators {
547 sw1a_reg: sw1ab { 547 sw1a_reg: sw1ab {
548 regulator-min-microvolt = <300000>; 548 regulator-min-microvolt = <300000>;
549 regulator-max-microvolt = <1875000>; 549 regulator-max-microvolt = <1875000>;
550 regulator-boot-on; 550 regulator-boot-on;
551 regulator-always-on; 551 regulator-always-on;
552 regulator-ramp-delay = <6250>; 552 regulator-ramp-delay = <6250>;
553 }; 553 };
554 554
555 sw1c_reg: sw1c { 555 sw1c_reg: sw1c {
556 regulator-min-microvolt = <300000>; 556 regulator-min-microvolt = <300000>;
557 regulator-max-microvolt = <1875000>; 557 regulator-max-microvolt = <1875000>;
558 regulator-boot-on; 558 regulator-boot-on;
559 regulator-always-on; 559 regulator-always-on;
560 regulator-ramp-delay = <6250>; 560 regulator-ramp-delay = <6250>;
561 }; 561 };
562 562
563 sw2_reg: sw2 { 563 sw2_reg: sw2 {
564 regulator-min-microvolt = <800000>; 564 regulator-min-microvolt = <800000>;
565 regulator-max-microvolt = <3300000>; 565 regulator-max-microvolt = <3300000>;
566 regulator-boot-on; 566 regulator-boot-on;
567 regulator-always-on; 567 regulator-always-on;
568 }; 568 };
569 569
570 sw3a_reg: sw3a { 570 sw3a_reg: sw3a {
571 regulator-min-microvolt = <400000>; 571 regulator-min-microvolt = <400000>;
572 regulator-max-microvolt = <1975000>; 572 regulator-max-microvolt = <1975000>;
573 regulator-boot-on; 573 regulator-boot-on;
574 regulator-always-on; 574 regulator-always-on;
575 }; 575 };
576 576
577 sw3b_reg: sw3b { 577 sw3b_reg: sw3b {
578 regulator-min-microvolt = <400000>; 578 regulator-min-microvolt = <400000>;
579 regulator-max-microvolt = <1975000>; 579 regulator-max-microvolt = <1975000>;
580 regulator-boot-on; 580 regulator-boot-on;
581 regulator-always-on; 581 regulator-always-on;
582 }; 582 };
583 583
584 sw4_reg: sw4 { 584 sw4_reg: sw4 {
585 regulator-min-microvolt = <800000>; 585 regulator-min-microvolt = <800000>;
586 regulator-max-microvolt = <3300000>; 586 regulator-max-microvolt = <3300000>;
587 regulator-always-on; 587 regulator-always-on;
588 }; 588 };
589 589
590 swbst_reg: swbst { 590 swbst_reg: swbst {
591 regulator-min-microvolt = <5000000>; 591 regulator-min-microvolt = <5000000>;
592 regulator-max-microvolt = <5150000>; 592 regulator-max-microvolt = <5150000>;
593 }; 593 };
594 594
595 snvs_reg: vsnvs { 595 snvs_reg: vsnvs {
596 regulator-min-microvolt = <1000000>; 596 regulator-min-microvolt = <1000000>;
597 regulator-max-microvolt = <3000000>; 597 regulator-max-microvolt = <3000000>;
598 regulator-boot-on; 598 regulator-boot-on;
599 regulator-always-on; 599 regulator-always-on;
600 }; 600 };
601 601
602 vref_reg: vrefddr { 602 vref_reg: vrefddr {
603 regulator-boot-on; 603 regulator-boot-on;
604 regulator-always-on; 604 regulator-always-on;
605 }; 605 };
606 606
607 vgen1_reg: vgen1 { 607 vgen1_reg: vgen1 {
608 regulator-min-microvolt = <800000>; 608 regulator-min-microvolt = <800000>;
609 regulator-max-microvolt = <1550000>; 609 regulator-max-microvolt = <1550000>;
610 }; 610 };
611 611
612 vgen2_reg: vgen2 { 612 vgen2_reg: vgen2 {
613 regulator-min-microvolt = <800000>; 613 regulator-min-microvolt = <800000>;
614 regulator-max-microvolt = <1550000>; 614 regulator-max-microvolt = <1550000>;
615 }; 615 };
616 616
617 vgen3_reg: vgen3 { 617 vgen3_reg: vgen3 {
618 regulator-min-microvolt = <1800000>; 618 regulator-min-microvolt = <1800000>;
619 regulator-max-microvolt = <3300000>; 619 regulator-max-microvolt = <3300000>;
620 }; 620 };
621 621
622 vgen4_reg: vgen4 { 622 vgen4_reg: vgen4 {
623 regulator-min-microvolt = <1800000>; 623 regulator-min-microvolt = <1800000>;
624 regulator-max-microvolt = <3300000>; 624 regulator-max-microvolt = <3300000>;
625 regulator-always-on; 625 regulator-always-on;
626 }; 626 };
627 627
628 vgen5_reg: vgen5 { 628 vgen5_reg: vgen5 {
629 regulator-min-microvolt = <1800000>; 629 regulator-min-microvolt = <1800000>;
630 regulator-max-microvolt = <3300000>; 630 regulator-max-microvolt = <3300000>;
631 regulator-always-on; 631 regulator-always-on;
632 }; 632 };
633 633
634 vgen6_reg: vgen6 { 634 vgen6_reg: vgen6 {
635 regulator-min-microvolt = <1800000>; 635 regulator-min-microvolt = <1800000>;
636 regulator-max-microvolt = <3300000>; 636 regulator-max-microvolt = <3300000>;
637 regulator-always-on; 637 regulator-always-on;
638 }; 638 };
639 }; 639 };
640 }; 640 };
641 641
642 hdmi_edid: edid@50 { 642 hdmi_edid: edid@50 {
643 compatible = "fsl,imx6-hdmi-i2c"; 643 compatible = "fsl,imx6-hdmi-i2c";
644 reg = <0x50>; 644 reg = <0x50>;
645 }; 645 };
646 646
647 codec: cs42888@48 { 647 codec: cs42888@48 {
648 compatible = "cirrus,cs42888"; 648 compatible = "cirrus,cs42888";
649 reg = <0x48>; 649 reg = <0x48>;
650 clocks = <&codec_osc>; 650 clocks = <&codec_osc>;
651 clock-names = "mclk"; 651 clock-names = "mclk";
652 VA-supply = <&reg_audio>; 652 VA-supply = <&reg_audio>;
653 VD-supply = <&reg_audio>; 653 VD-supply = <&reg_audio>;
654 VLS-supply = <&reg_audio>; 654 VLS-supply = <&reg_audio>;
655 VLC-supply = <&reg_audio>; 655 VLC-supply = <&reg_audio>;
656 }; 656 };
657 657
658 si4763: si4763@63 { 658 si4763: si4763@63 {
659 compatible = "si4761"; 659 compatible = "si4761";
660 reg = <0x63>; 660 reg = <0x63>;
661 va-supply = <&reg_si4763_va>; 661 va-supply = <&reg_si4763_va>;
662 vd-supply = <&reg_si4763_vd>; 662 vd-supply = <&reg_si4763_vd>;
663 vio1-supply = <&reg_si4763_vio1>; 663 vio1-supply = <&reg_si4763_vio1>;
664 vio2-supply = <&reg_si4763_vio2>; 664 vio2-supply = <&reg_si4763_vio2>;
665 revision-a10; /* set to default A10 compatible command set */ 665 revision-a10; /* set to default A10 compatible command set */
666 666
667 si476x_codec: si476x-codec { 667 si476x_codec: si476x-codec {
668 compatible = "si476x-codec"; 668 compatible = "si476x-codec";
669 }; 669 };
670 }; 670 };
671 }; 671 };
672 672
673 &i2c3 { 673 &i2c3 {
674 pinctrl-names = "default", "gpio"; 674 pinctrl-names = "default", "gpio";
675 pinctrl-0 = <&pinctrl_i2c3>; 675 pinctrl-0 = <&pinctrl_i2c3>;
676 pinctrl-1 = <&pinctrl_i2c3_gpio>; 676 pinctrl-1 = <&pinctrl_i2c3_gpio>;
677 scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 677 scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
678 sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; 678 sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
679 status = "okay"; 679 status = "okay";
680 }; 680 };
681 681
682 &iomuxc { 682 &iomuxc {
683 pinctrl-names = "default"; 683 pinctrl-names = "default";
684 pinctrl-0 = <&pinctrl_hog>; 684 pinctrl-0 = <&pinctrl_hog>;
685 685
686 imx6qdl-sabreauto { 686 imx6qdl-sabreauto {
687 pinctrl_audmux: audmux { 687 pinctrl_audmux: audmux {
688 fsl,pins = < 688 fsl,pins = <
689 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 689 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
690 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 690 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
691 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 691 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
692 >; 692 >;
693 }; 693 };
694 694
695 pinctrl_hog: hoggrp { 695 pinctrl_hog: hoggrp {
696 fsl,pins = < 696 fsl,pins = <
697 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1f059 697 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1f059
698 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 698 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
699 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 699 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
700 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000 700 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000
701 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 701 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000
702 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x80000000 702 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x80000000
703 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000 703 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
704 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x17059 704 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x17059
705 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x17059 705 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x17059
706 >; 706 >;
707 }; 707 };
708 708
709 pinctrl_ecspi1: ecspi1grp { 709 pinctrl_ecspi1: ecspi1grp {
710 fsl,pins = < 710 fsl,pins = <
711 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 711 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
712 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 712 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
713 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 713 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
714 >; 714 >;
715 }; 715 };
716 716
717 pinctrl_ecspi1_cs: ecspi1cs { 717 pinctrl_ecspi1_cs: ecspi1cs {
718 fsl,pins = < 718 fsl,pins = <
719 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 719 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
720 >; 720 >;
721 }; 721 };
722 722
723 pinctrl_egalax_int: egalax_intgrp { 723 pinctrl_egalax_int: egalax_intgrp {
724 fsl,pins = < 724 fsl,pins = <
725 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000 725 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000
726 >; 726 >;
727 }; 727 };
728 728
729 pinctrl_enet: enetgrp { 729 pinctrl_enet: enetgrp {
730 fsl,pins = < 730 fsl,pins = <
731 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 731 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
732 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 732 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
733 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 733 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
734 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 734 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
735 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 735 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
736 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 736 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
737 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 737 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
738 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 738 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
739 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 739 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
740 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 740 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
741 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 741 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
742 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 742 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
743 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 743 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
744 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 744 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
745 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 745 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
746 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 746 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
747 >; 747 >;
748 }; 748 };
749 749
750 pinctrl_enet_irq: enetirqgrp { 750 pinctrl_enet_irq: enetirqgrp {
751 fsl,pins = < 751 fsl,pins = <
752 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 752 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
753 >; 753 >;
754 }; 754 };
755 755
756 pinctrl_esai: esaigrp { 756 pinctrl_esai: esaigrp {
757 fsl,pins = < 757 fsl,pins = <
758 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 758 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
759 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 759 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
760 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 760 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
761 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 761 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
762 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 762 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
763 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 763 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
764 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 764 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
765 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 765 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
766 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 766 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
767 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 767 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
768 >; 768 >;
769 }; 769 };
770 770
771 pinctrl_flexcan1: flexcan1grp { 771 pinctrl_flexcan1: flexcan1grp {
772 fsl,pins = < 772 fsl,pins = <
773 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059 773 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059
774 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059 774 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059
775 >; 775 >;
776 }; 776 };
777 777
778 pinctrl_flexcan2: flexcan2grp { 778 pinctrl_flexcan2: flexcan2grp {
779 fsl,pins = < 779 fsl,pins = <
780 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059 780 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059
781 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059 781 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059
782 >; 782 >;
783 }; 783 };
784 784
785 pinctrl_gpio_keys: gpio_keysgrp { 785 pinctrl_gpio_keys: gpio_keysgrp {
786 fsl,pins = < 786 fsl,pins = <
787 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 787 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
788 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 788 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
789 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 789 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
790 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 790 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0
791 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 791 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
792 >; 792 >;
793 }; 793 };
794 794
795 pinctrl_gpio_leds: gpioledsgrp { 795 pinctrl_gpio_leds: gpioledsgrp {
796 fsl,pins = < 796 fsl,pins = <
797 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 797 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
798 >; 798 >;
799 }; 799 };
800 800
801 pinctrl_gpmi_nand: gpminandgrp { 801 pinctrl_gpmi_nand: gpminandgrp {
802 fsl,pins = < 802 fsl,pins = <
803 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 803 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
804 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 804 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
805 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 805 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
806 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 806 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
807 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 807 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
808 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 808 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
809 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 809 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
810 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 810 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
811 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 811 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
812 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 812 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
813 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 813 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
814 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 814 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
815 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 815 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
816 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 816 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
817 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 817 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
818 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 818 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
819 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 819 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
820 >; 820 >;
821 }; 821 };
822 822
823 pinctrl_i2c2: i2c2grp { 823 pinctrl_i2c2: i2c2grp {
824 fsl,pins = < 824 fsl,pins = <
825 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 825 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
826 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 826 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
827 >; 827 >;
828 }; 828 };
829 829
830 pinctrl_i2c2_gpio: i2c2grp_gpio { 830 pinctrl_i2c2_gpio: i2c2grp_gpio {
831 fsl,pins = < 831 fsl,pins = <
832 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b8b1 832 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b8b1
833 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b8b1 833 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b8b1
834 >; 834 >;
835 }; 835 };
836 836
837 pinctrl_ipu1_1: ipu1grp-1 { /* parallel port 16-bit */ 837 pinctrl_ipu1_1: ipu1grp-1 { /* parallel port 16-bit */
838 fsl,pins = < 838 fsl,pins = <
839 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 839 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
840 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 840 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
841 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 841 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
842 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 842 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
843 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 843 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
844 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 844 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
845 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 845 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
846 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 846 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
847 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 847 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
848 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 848 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
849 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 849 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
850 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 850 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
851 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 851 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
852 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 852 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
853 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 853 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
854 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 854 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
855 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 855 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
856 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 856 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
857 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 857 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
858 >; 858 >;
859 }; 859 };
860 860
861 pinctrl_i2c3: i2c3grp { 861 pinctrl_i2c3: i2c3grp {
862 fsl,pins = < 862 fsl,pins = <
863 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 863 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
864 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 864 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
865 >; 865 >;
866 }; 866 };
867 867
868 pinctrl_i2c3_gpio: i2c3grp_gpio { 868 pinctrl_i2c3_gpio: i2c3grp_gpio {
869 fsl,pins = < 869 fsl,pins = <
870 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b8b1 870 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b8b1
871 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b8b1 871 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b8b1
872 >; 872 >;
873 }; 873 };
874 874
875 pinctrl_i2c3mux: i2c3muxgrp { 875 pinctrl_i2c3mux: i2c3muxgrp {
876 fsl,pins = < 876 fsl,pins = <
877 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1 877 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
878 >; 878 >;
879 }; 879 };
880 880
881 pinctrl_ipu1_csi0: ipu1csi0grp { 881 pinctrl_ipu1_csi0: ipu1csi0grp {
882 fsl,pins = < 882 fsl,pins = <
883 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 883 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
884 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 884 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
885 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 885 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
886 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 886 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
887 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 887 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
888 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 888 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
889 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 889 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
890 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 890 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
891 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 891 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
892 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 892 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
893 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 893 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
894 >; 894 >;
895 }; 895 };
896 896
897 pinctrl_max7310: max7310grp { 897 pinctrl_max7310: max7310grp {
898 fsl,pins = < 898 fsl,pins = <
899 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 899 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
900 >; 900 >;
901 }; 901 };
902 902
903 pinctrl_mlb: mlb { 903 pinctrl_mlb: mlb {
904 fsl,pins = < 904 fsl,pins = <
905 MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000 905 MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000
906 MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000 906 MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000
907 MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000 907 MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000
908 >; 908 >;
909 }; 909 };
910 910
911 pinctrl_pwm3: pwm1grp { 911 pinctrl_pwm3: pwm1grp {
912 fsl,pins = < 912 fsl,pins = <
913 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 913 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
914 >; 914 >;
915 }; 915 };
916 916
917 pinctrl_gpt_input_capture0: gptinputcapture0grp { 917 pinctrl_gpt_input_capture0: gptinputcapture0grp {
918 fsl,pins = < 918 fsl,pins = <
919 MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0 919 MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0
920 >; 920 >;
921 }; 921 };
922 922
923 pinctrl_gpt_input_capture1: gptinputcapture1grp { 923 pinctrl_gpt_input_capture1: gptinputcapture1grp {
924 fsl,pins = < 924 fsl,pins = <
925 MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0 925 MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0
926 >; 926 >;
927 }; 927 };
928 928
929 pinctrl_spdif: spdifgrp { 929 pinctrl_spdif: spdifgrp {
930 fsl,pins = < 930 fsl,pins = <
931 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 931 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
932 >; 932 >;
933 }; 933 };
934 934
935 pinctrl_uart3_1: uart3grp-1 { 935 pinctrl_uart3_1: uart3grp-1 {
936 fsl,pins = < 936 fsl,pins = <
937 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 937 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
938 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 938 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
939 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 939 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
940 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 940 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
941 >; 941 >;
942 }; 942 };
943 943
944 pinctrl_uart3dte_1: uart3dtegrp-1 { 944 pinctrl_uart3dte_1: uart3dtegrp-1 {
945 fsl,pins = < 945 fsl,pins = <
946 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 946 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
947 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 947 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
948 MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 948 MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1
949 MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1 949 MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1
950 >; 950 >;
951 }; 951 };
952 952
953 pinctrl_uart4: uart4grp { 953 pinctrl_uart4: uart4grp {
954 fsl,pins = < 954 fsl,pins = <
955 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 955 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
956 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 956 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
957 >; 957 >;
958 }; 958 };
959 959
960 pinctrl_usbotg: usbotggrp { 960 pinctrl_usbotg: usbotggrp {
961 fsl,pins = < 961 fsl,pins = <
962 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 962 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
963 >; 963 >;
964 }; 964 };
965 965
966 pinctrl_usdhc1: usdhc1grp { 966 pinctrl_usdhc1: usdhc1grp {
967 fsl,pins = < 967 fsl,pins = <
968 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 968 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
969 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 969 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
970 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 970 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
971 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 971 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
972 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 972 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
973 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 973 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
974 >; 974 >;
975 }; 975 };
976 976
977 pinctrl_usdhc3: usdhc3grp { 977 pinctrl_usdhc3: usdhc3grp {
978 fsl,pins = < 978 fsl,pins = <
979 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 979 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
980 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 980 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
981 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 981 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
982 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 982 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
983 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 983 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
984 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 984 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
985 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 985 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
986 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 986 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
987 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 987 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
988 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 988 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
989 >; 989 >;
990 }; 990 };
991 991
992 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 992 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
993 fsl,pins = < 993 fsl,pins = <
994 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 994 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
995 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 995 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
996 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 996 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
997 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 997 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
998 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 998 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
999 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 999 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
1000 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 1000 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
1001 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 1001 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
1002 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 1002 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
1003 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 1003 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
1004 >; 1004 >;
1005 }; 1005 };
1006 1006
1007 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 1007 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
1008 fsl,pins = < 1008 fsl,pins = <
1009 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 1009 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
1010 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 1010 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
1011 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 1011 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
1012 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 1012 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
1013 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 1013 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
1014 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 1014 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
1015 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 1015 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
1016 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 1016 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
1017 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 1017 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
1018 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 1018 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
1019 >; 1019 >;
1020 }; 1020 };
1021 1021
1022 pinctrl_weim_cs0: weimcs0grp { 1022 pinctrl_weim_cs0: weimcs0grp {
1023 fsl,pins = < 1023 fsl,pins = <
1024 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 1024 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
1025 >; 1025 >;
1026 }; 1026 };
1027 1027
1028 pinctrl_weim_nor: weimnorgrp { 1028 pinctrl_weim_nor: weimnorgrp {
1029 fsl,pins = < 1029 fsl,pins = <
1030 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 1030 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
1031 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 1031 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
1032 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 1032 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
1033 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 1033 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
1034 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 1034 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
1035 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 1035 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
1036 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 1036 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
1037 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 1037 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
1038 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 1038 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
1039 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 1039 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
1040 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 1040 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
1041 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 1041 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
1042 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 1042 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
1043 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 1043 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
1044 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 1044 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
1045 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 1045 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
1046 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 1046 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
1047 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 1047 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
1048 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 1048 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
1049 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 1049 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
1050 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 1050 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
1051 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 1051 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
1052 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 1052 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
1053 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 1053 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
1054 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 1054 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
1055 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 1055 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
1056 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 1056 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
1057 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 1057 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
1058 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 1058 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
1059 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 1059 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
1060 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 1060 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
1061 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 1061 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
1062 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 1062 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
1063 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 1063 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
1064 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 1064 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
1065 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 1065 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
1066 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 1066 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
1067 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 1067 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
1068 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 1068 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
1069 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 1069 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
1070 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 1070 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
1071 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 1071 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
1072 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 1072 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
1073 >; 1073 >;
1074 }; 1074 };
1075 1075
1076 pinctrl_hdmi_cec: hdmicecgrp { 1076 pinctrl_hdmi_cec: hdmicecgrp {
1077 fsl,pins = < 1077 fsl,pins = <
1078 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 1078 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
1079 >; 1079 >;
1080 }; 1080 };
1081 }; 1081 };
1082 }; 1082 };
1083 1083
1084 &ldb { 1084 &ldb {
1085 status = "okay"; 1085 status = "okay";
1086 1086
1087 lvds-channel@0 { 1087 lvds-channel@0 {
1088 fsl,data-mapping = "spwg"; 1088 fsl,data-mapping = "spwg";
1089 fsl,data-width = <18>; 1089 fsl,data-width = <18>;
1090 primary; 1090 primary;
1091 status = "okay"; 1091 status = "okay";
1092 1092
1093 display-timings { 1093 display-timings {
1094 native-mode = <&timing0>; 1094 native-mode = <&timing0>;
1095 timing0: hsd100pxn1 { 1095 timing0: hsd100pxn1 {
1096 clock-frequency = <65000000>; 1096 clock-frequency = <65000000>;
1097 hactive = <1024>; 1097 hactive = <1024>;
1098 vactive = <768>; 1098 vactive = <768>;
1099 hback-porch = <220>; 1099 hback-porch = <220>;
1100 hfront-porch = <40>; 1100 hfront-porch = <40>;
1101 vback-porch = <21>; 1101 vback-porch = <21>;
1102 vfront-porch = <7>; 1102 vfront-porch = <7>;
1103 hsync-len = <60>; 1103 hsync-len = <60>;
1104 vsync-len = <10>; 1104 vsync-len = <10>;
1105 }; 1105 };
1106 }; 1106 };
1107 }; 1107 };
1108 1108
1109 lvds-channel@1 { 1109 lvds-channel@1 {
1110 fsl,data-mapping = "spwg"; 1110 fsl,data-mapping = "spwg";
1111 fsl,data-width = <18>; 1111 fsl,data-width = <18>;
1112 status = "okay"; 1112 status = "okay";
1113 1113
1114 display-timings { 1114 display-timings {
1115 native-mode = <&timing1>; 1115 native-mode = <&timing1>;
1116 timing1: hsd100pxn1 { 1116 timing1: hsd100pxn1 {
1117 clock-frequency = <65000000>; 1117 clock-frequency = <65000000>;
1118 hactive = <1024>; 1118 hactive = <1024>;
1119 vactive = <768>; 1119 vactive = <768>;
1120 hback-porch = <220>; 1120 hback-porch = <220>;
1121 hfront-porch = <40>; 1121 hfront-porch = <40>;
1122 vback-porch = <21>; 1122 vback-porch = <21>;
1123 vfront-porch = <7>; 1123 vfront-porch = <7>;
1124 hsync-len = <60>; 1124 hsync-len = <60>;
1125 vsync-len = <10>; 1125 vsync-len = <10>;
1126 }; 1126 };
1127 }; 1127 };
1128 }; 1128 };
1129 }; 1129 };
1130 1130
1131 &mlb { 1131 &mlb {
1132 pinctrl-names = "default"; 1132 pinctrl-names = "default";
1133 pinctrl-0 = <&pinctrl_mlb>; 1133 pinctrl-0 = <&pinctrl_mlb>;
1134 status = "okay"; 1134 status = "okay";
1135 }; 1135 };
1136 1136
1137 &pwm3 { 1137 &pwm3 {
1138 pinctrl-names = "default"; 1138 pinctrl-names = "default";
1139 pinctrl-0 = <&pinctrl_pwm3>; 1139 pinctrl-0 = <&pinctrl_pwm3>;
1140 status = "okay"; 1140 status = "okay";
1141 }; 1141 };
1142 1142
1143 &pcie { 1143 &pcie {
1144 status = "okay"; 1144 status = "okay";
1145 }; 1145 };
1146 1146
1147 &spdif { 1147 &spdif {
1148 pinctrl-names = "default"; 1148 pinctrl-names = "default";
1149 pinctrl-0 = <&pinctrl_spdif>; 1149 pinctrl-0 = <&pinctrl_spdif>;
1150 assigned-clocks = <&clks IMX6QDL_CLK_SPDIF_SEL>, 1150 assigned-clocks = <&clks IMX6QDL_CLK_SPDIF_SEL>,
1151 <&clks IMX6QDL_CLK_SPDIF_PODF>; 1151 <&clks IMX6QDL_CLK_SPDIF_PODF>;
1152 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_PFD3_454M>; 1152 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_PFD3_454M>;
1153 assigned-clock-rates = <0>, <227368421>; 1153 assigned-clock-rates = <0>, <227368421>;
1154 status = "okay"; 1154 status = "okay";
1155 }; 1155 };
1156 1156
1157 &snvs_poweroff { 1157 &snvs_poweroff {
1158 status = "okay"; 1158 status = "okay";
1159 }; 1159 };
1160 1160
1161 &ssi2 { 1161 &ssi2 {
1162 assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>; 1162 assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>;
1163 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; 1163 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
1164 assigned-clock-rates = <0>; 1164 assigned-clock-rates = <0>;
1165 fsl,mode = "i2s-master"; 1165 fsl,mode = "i2s-master";
1166 status = "okay"; 1166 status = "okay";
1167 }; 1167 };
1168 1168
1169 &uart3 { 1169 &uart3 {
1170 pinctrl-names = "default"; 1170 pinctrl-names = "default";
1171 pinctrl-0 = <&pinctrl_uart3_1>; 1171 pinctrl-0 = <&pinctrl_uart3_1>;
1172 pinctrl-assert-gpios = <&max7310_b 4 GPIO_ACTIVE_HIGH>, /* CTS */ 1172 pinctrl-assert-gpios = <&max7310_b 4 GPIO_ACTIVE_HIGH>, /* CTS */
1173 <&max7310_c 3 GPIO_ACTIVE_HIGH>; /* RXD and TXD */ 1173 <&max7310_c 3 GPIO_ACTIVE_HIGH>; /* RXD and TXD */
1174 fsl,uart-has-rtscts; 1174 fsl,uart-has-rtscts;
1175 status = "okay"; 1175 status = "okay";
1176 /* for DTE mode, add below change */ 1176 /* for DTE mode, add below change */
1177 /* fsl,dte-mode; */ 1177 /* fsl,dte-mode; */
1178 /* pinctrl-0 = <&pinctrl_uart3dte_1>; */ 1178 /* pinctrl-0 = <&pinctrl_uart3dte_1>; */
1179 }; 1179 };
1180 1180
1181 &uart4 { 1181 &uart4 {
1182 pinctrl-names = "default"; 1182 pinctrl-names = "default";
1183 pinctrl-0 = <&pinctrl_uart4>; 1183 pinctrl-0 = <&pinctrl_uart4>;
1184 status = "okay"; 1184 status = "okay";
1185 }; 1185 };
1186 1186
1187 &usbh1 { 1187 &usbh1 {
1188 vbus-supply = <&reg_usb_h1_vbus>; 1188 vbus-supply = <&reg_usb_h1_vbus>;
1189 status = "okay"; 1189 status = "okay";
1190 }; 1190 };
1191 1191
1192 &usbotg { 1192 &usbotg {
1193 vbus-supply = <&reg_usb_otg_vbus>; 1193 vbus-supply = <&reg_usb_otg_vbus>;
1194 pinctrl-names = "default"; 1194 pinctrl-names = "default";
1195 pinctrl-0 = <&pinctrl_usbotg>; 1195 pinctrl-0 = <&pinctrl_usbotg>;
1196 srp-disable; 1196 srp-disable;
1197 hnp-disable; 1197 hnp-disable;
1198 adp-disable; 1198 adp-disable;
1199 status = "okay"; 1199 status = "okay";
1200 }; 1200 };
1201 1201
1202 &usdhc1 { 1202 &usdhc1 {
1203 pinctrl-names = "default"; 1203 pinctrl-names = "default";
1204 pinctrl-0 = <&pinctrl_usdhc1>; 1204 pinctrl-0 = <&pinctrl_usdhc1>;
1205 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 1205 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
1206 no-1-8-v; 1206 no-1-8-v;
1207 keep-power-in-suspend; 1207 keep-power-in-suspend;
1208 enable-sdio-wakeup; 1208 enable-sdio-wakeup;
1209 status = "okay"; 1209 status = "okay";
1210 }; 1210 };
1211 1211
1212 &usdhc3 { 1212 &usdhc3 {
1213 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 1213 pinctrl-names = "default", "state_100mhz", "state_200mhz";
1214 pinctrl-0 = <&pinctrl_usdhc3>; 1214 pinctrl-0 = <&pinctrl_usdhc3>;
1215 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 1215 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
1216 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 1216 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
1217 cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; 1217 cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
1218 wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 1218 wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
1219 /* 1219 /*
1220 * Due to board issue, we can not use external regulator for card slot 1220 * Due to board issue, we can not use external regulator for card slot
1221 * by default since the card power is shared with card detect pullup. 1221 * by default since the card power is shared with card detect pullup.
1222 * Disabling the vmmc regulator will cause unexpected card detect 1222 * Disabling the vmmc regulator will cause unexpected card detect
1223 * interrupts. 1223 * interrupts.
1224 * HW rework is needed to fix this isssue. Remove R695 first, then you 1224 * HW rework is needed to fix this isssue. Remove R695 first, then you
1225 * can open below line to enable the using of external regulator. 1225 * can open below line to enable the using of external regulator.
1226 * Then you will be able to power off the card during suspend. This is 1226 * Then you will be able to power off the card during suspend. This is
1227 * especially needed for a SD3.0 card re-enumeration working on UHS mode 1227 * especially needed for a SD3.0 card re-enumeration working on UHS mode
1228 * Note: reg_sd3_vmmc is also need to be enabled 1228 * Note: reg_sd3_vmmc is also need to be enabled
1229 */ 1229 */
1230 /* vmmc-supply = <&reg_sd3_vmmc>; */ 1230 /* vmmc-supply = <&reg_sd3_vmmc>; */
1231 keep-power-in-suspend; 1231 keep-power-in-suspend;
1232 enable-sdio-wakeup; 1232 enable-sdio-wakeup;
1233 status = "okay"; 1233 status = "okay";
1234 }; 1234 };
1235 1235
1236 &weim { 1236 &weim {
1237 pinctrl-names = "default"; 1237 pinctrl-names = "default";
1238 pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; 1238 pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
1239 ranges = <0 0 0x08000000 0x08000000>; 1239 ranges = <0 0 0x08000000 0x08000000>;
1240 status = "disabled"; /* pin conflict with SPI NOR */ 1240 status = "disabled"; /* pin conflict with SPI NOR */
1241 1241
1242 nor@0,0 { 1242 nor@0,0 {
1243 compatible = "cfi-flash"; 1243 compatible = "cfi-flash";
1244 reg = <0 0 0x02000000>; 1244 reg = <0 0 0x02000000>;
1245 #address-cells = <1>; 1245 #address-cells = <1>;
1246 #size-cells = <1>; 1246 #size-cells = <1>;
1247 bank-width = <2>; 1247 bank-width = <2>;
1248 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 1248 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
1249 0x0000c000 0x1404a38e 0x00000000>; 1249 0x0000c000 0x1404a38e 0x00000000>;
1250 }; 1250 };
1251 }; 1251 };
1252 1252
arch/arm/dts/imx6sll-evk.dts
Diff comments   View file @ 4daafb3
1 /* 1 /*
2 * Copyright (C) 2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP. 3 * Copyright 2017 NXP.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as 6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
8 */ 8 */
9 9
10 /dts-v1/; 10 /dts-v1/;
11 11
12 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h> 13 #include <dt-bindings/input/input.h>
14 #include "imx6sll.dtsi" 14 #include "imx6sll.dtsi"
15 15
16 / { 16 / {
17 model = "Freescale i.MX6SLL EVK Board"; 17 model = "Freescale i.MX6SLL EVK Board";
18 compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; 18 compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
19 19
20 chosen { 20 chosen {
21 stdout-path = &uart1; 21 stdout-path = &uart1;
22 }; 22 };
23 23
24 memory { 24 memory {
25 reg = <0x80000000 0x80000000>; 25 reg = <0x80000000 0x80000000>;
26 }; 26 };
27 27
28 backlight { 28 backlight {
29 compatible = "pwm-backlight"; 29 compatible = "pwm-backlight";
30 pwms = <&pwm1 0 5000000>; 30 pwms = <&pwm1 0 5000000>;
31 brightness-levels = <0 4 8 16 32 64 128 255>; 31 brightness-levels = <0 4 8 16 32 64 128 255>;
32 default-brightness-level = <6>; 32 default-brightness-level = <6>;
33 status = "okay"; 33 status = "okay";
34 }; 34 };
35 35
36 battery: max8903@0 { 36 battery: max8903@0 {
37 compatible = "fsl,max8903-charger"; 37 compatible = "fsl,max8903-charger";
38 pinctrl-names = "default"; 38 pinctrl-names = "default";
39 dok_input = <&gpio4 13 1>; 39 dok_input = <&gpio4 13 1>;
40 uok_input = <&gpio4 13 1>; 40 uok_input = <&gpio4 13 1>;
41 chg_input = <&gpio4 15 1>; 41 chg_input = <&gpio4 15 1>;
42 flt_input = <&gpio4 14 1>; 42 flt_input = <&gpio4 14 1>;
43 fsl,dcm_always_high; 43 fsl,dcm_always_high;
44 fsl,dc_valid; 44 fsl,dc_valid;
45 fsl,adc_disable; 45 fsl,adc_disable;
46 status = "okay"; 46 status = "okay";
47 }; 47 };
48 48
49 pxp_v4l2_out { 49 pxp_v4l2_out {
50 compatible = "fsl,imx6sl-pxp-v4l2"; 50 compatible = "fsl,imx6sl-pxp-v4l2";
51 status = "okay"; 51 status = "okay";
52 }; 52 };
53 53
54 regulators { 54 regulators {
55 compatible = "simple-bus"; 55 compatible = "simple-bus";
56 #address-cells = <1>; 56 #address-cells = <1>;
57 #size-cells = <0>; 57 #size-cells = <0>;
58 58
59 reg_usb_otg1_vbus: regulator@0 { 59 reg_usb_otg1_vbus: regulator@0 {
60 compatible = "regulator-fixed"; 60 compatible = "regulator-fixed";
61 reg = <0>; 61 reg = <0>;
62 regulator-name = "usb_otg1_vbus"; 62 regulator-name = "usb_otg1_vbus";
63 regulator-min-microvolt = <5000000>; 63 regulator-min-microvolt = <5000000>;
64 regulator-max-microvolt = <5000000>; 64 regulator-max-microvolt = <5000000>;
65 gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; 65 gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
66 enable-active-high; 66 enable-active-high;
67 }; 67 };
68 68
69 reg_usb_otg2_vbus: regulator@1 { 69 reg_usb_otg2_vbus: regulator@1 {
70 compatible = "regulator-fixed"; 70 compatible = "regulator-fixed";
71 reg = <1>; 71 reg = <1>;
72 regulator-name = "usb_otg2_vbus"; 72 regulator-name = "usb_otg2_vbus";
73 regulator-min-microvolt = <5000000>; 73 regulator-min-microvolt = <5000000>;
74 regulator-max-microvolt = <5000000>; 74 regulator-max-microvolt = <5000000>;
75 gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; 75 gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
76 enable-active-high; 76 enable-active-high;
77 }; 77 };
78 78
79 reg_aud3v: regulator@2 { 79 reg_aud3v: regulator@2 {
80 compatible = "regulator-fixed"; 80 compatible = "regulator-fixed";
81 reg = <2>; 81 reg = <2>;
82 regulator-name = "wm8962-supply-3v15"; 82 regulator-name = "wm8962-supply-3v15";
83 regulator-min-microvolt = <3150000>; 83 regulator-min-microvolt = <3150000>;
84 regulator-max-microvolt = <3150000>; 84 regulator-max-microvolt = <3150000>;
85 regulator-boot-on; 85 regulator-boot-on;
86 }; 86 };
87 87
88 reg_aud4v: regulator@3 { 88 reg_aud4v: regulator@3 {
89 compatible = "regulator-fixed"; 89 compatible = "regulator-fixed";
90 reg = <3>; 90 reg = <3>;
91 regulator-name = "wm8962-supply-4v2"; 91 regulator-name = "wm8962-supply-4v2";
92 regulator-min-microvolt = <4325000>; 92 regulator-min-microvolt = <4325000>;
93 regulator-max-microvolt = <4325000>; 93 regulator-max-microvolt = <4325000>;
94 regulator-boot-on; 94 regulator-boot-on;
95 }; 95 };
96 96
97 reg_lcd: regulator@4 { 97 reg_lcd: regulator@4 {
98 compatible = "regulator-fixed"; 98 compatible = "regulator-fixed";
99 reg = <4>; 99 reg = <4>;
100 regulator-name = "lcd-pwr"; 100 regulator-name = "lcd-pwr";
101 gpio = <&gpio4 8 0>; 101 gpio = <&gpio4 8 0>;
102 enable-active-high; 102 enable-active-high;
103 }; 103 };
104 104
105 reg_sd1_vmmc: sd1_vmmc { 105 reg_sd1_vmmc: sd1_vmmc {
106 compatible = "regulator-fixed"; 106 compatible = "regulator-fixed";
107 regulator-name = "SD1_SPWR"; 107 regulator-name = "SD1_SPWR";
108 regulator-min-microvolt = <3000000>; 108 regulator-min-microvolt = <3000000>;
109 regulator-max-microvolt = <3000000>; 109 regulator-max-microvolt = <3000000>;
110 gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; 110 gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
111 off-on-delay = <20000>; 111 u-boot,off-on-delay-us = <20000>;
112 enable-active-high; 112 enable-active-high;
113 }; 113 };
114 114
115 reg_sd2_vmmc: sd2_vmmc { 115 reg_sd2_vmmc: sd2_vmmc {
116 compatible = "regulator-fixed"; 116 compatible = "regulator-fixed";
117 regulator-name = "eMMC-VCCQ"; 117 regulator-name = "eMMC-VCCQ";
118 regulator-min-microvolt = <1800000>; 118 regulator-min-microvolt = <1800000>;
119 regulator-max-microvolt = <1800000>; 119 regulator-max-microvolt = <1800000>;
120 regulator-boot-on; 120 regulator-boot-on;
121 }; 121 };
122 122
123 reg_sd3_vmmc: sd3_vmmc { 123 reg_sd3_vmmc: sd3_vmmc {
124 compatible = "regulator-fixed"; 124 compatible = "regulator-fixed";
125 regulator-name = "SD3_WIFI"; 125 regulator-name = "SD3_WIFI";
126 regulator-min-microvolt = <3000000>; 126 regulator-min-microvolt = <3000000>;
127 regulator-max-microvolt = <3000000>; 127 regulator-max-microvolt = <3000000>;
128 gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; 128 gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
129 off-on-delay = <20000>; 129 u-boot,off-on-delay-us = <20000>;
130 enable-active-high; 130 enable-active-high;
131 }; 131 };
132 132
133 }; 133 };
134 134
135 sound { 135 sound {
136 compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; 136 compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
137 model = "wm8962-audio"; 137 model = "wm8962-audio";
138 cpu-dai = <&ssi2>; 138 cpu-dai = <&ssi2>;
139 audio-codec = <&codec>; 139 audio-codec = <&codec>;
140 audio-routing = 140 audio-routing =
141 "Headphone Jack", "HPOUTL", 141 "Headphone Jack", "HPOUTL",
142 "Headphone Jack", "HPOUTR", 142 "Headphone Jack", "HPOUTR",
143 "Ext Spk", "SPKOUTL", 143 "Ext Spk", "SPKOUTL",
144 "Ext Spk", "SPKOUTR", 144 "Ext Spk", "SPKOUTR",
145 "AMIC", "MICBIAS", 145 "AMIC", "MICBIAS",
146 "IN3R", "AMIC"; 146 "IN3R", "AMIC";
147 mux-int-port = <2>; 147 mux-int-port = <2>;
148 mux-ext-port = <3>; 148 mux-ext-port = <3>;
149 codec-master; 149 codec-master;
150 hp-det-gpios = <&gpio4 24 1>; 150 hp-det-gpios = <&gpio4 24 1>;
151 }; 151 };
152 }; 152 };
153 153
154 &audmux { 154 &audmux {
155 pinctrl-names = "default"; 155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_audmux3>; 156 pinctrl-0 = <&pinctrl_audmux3>;
157 status = "okay"; 157 status = "okay";
158 }; 158 };
159 159
160 &clks { 160 &clks {
161 assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; 161 assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
162 assigned-clock-rates = <393216000>; 162 assigned-clock-rates = <393216000>;
163 }; 163 };
164 164
165 &cpu0 { 165 &cpu0 {
166 arm-supply = <&sw1a_reg>; 166 arm-supply = <&sw1a_reg>;
167 soc-supply = <&sw1c_reg>; 167 soc-supply = <&sw1c_reg>;
168 }; 168 };
169 169
170 &i2c1 { 170 &i2c1 {
171 clock-frequency = <100000>; 171 clock-frequency = <100000>;
172 pinctrl-names = "default", "gpio"; 172 pinctrl-names = "default", "gpio";
173 pinctrl-0 = <&pinctrl_i2c1>; 173 pinctrl-0 = <&pinctrl_i2c1>;
174 pinctrl-1 = <&pinctrl_i2c1_gpio>; 174 pinctrl-1 = <&pinctrl_i2c1_gpio>;
175 scl-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; 175 scl-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
176 sda-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; 176 sda-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
177 status = "okay"; 177 status = "okay";
178 178
179 pmic: pfuze100@08 { 179 pmic: pfuze100@08 {
180 compatible = "fsl,pfuze100"; 180 compatible = "fsl,pfuze100";
181 reg = <0x08>; 181 reg = <0x08>;
182 182
183 regulators { 183 regulators {
184 sw1a_reg: sw1ab { 184 sw1a_reg: sw1ab {
185 regulator-min-microvolt = <300000>; 185 regulator-min-microvolt = <300000>;
186 regulator-max-microvolt = <1875000>; 186 regulator-max-microvolt = <1875000>;
187 regulator-boot-on; 187 regulator-boot-on;
188 regulator-always-on; 188 regulator-always-on;
189 regulator-ramp-delay = <6250>; 189 regulator-ramp-delay = <6250>;
190 }; 190 };
191 191
192 sw1c_reg: sw1c { 192 sw1c_reg: sw1c {
193 regulator-min-microvolt = <300000>; 193 regulator-min-microvolt = <300000>;
194 regulator-max-microvolt = <1875000>; 194 regulator-max-microvolt = <1875000>;
195 regulator-boot-on; 195 regulator-boot-on;
196 regulator-always-on; 196 regulator-always-on;
197 regulator-ramp-delay = <6250>; 197 regulator-ramp-delay = <6250>;
198 }; 198 };
199 199
200 sw2_reg: sw2 { 200 sw2_reg: sw2 {
201 regulator-min-microvolt = <800000>; 201 regulator-min-microvolt = <800000>;
202 regulator-max-microvolt = <3300000>; 202 regulator-max-microvolt = <3300000>;
203 regulator-boot-on; 203 regulator-boot-on;
204 regulator-always-on; 204 regulator-always-on;
205 }; 205 };
206 206
207 sw3a_reg: sw3a { 207 sw3a_reg: sw3a {
208 regulator-min-microvolt = <400000>; 208 regulator-min-microvolt = <400000>;
209 regulator-max-microvolt = <1975000>; 209 regulator-max-microvolt = <1975000>;
210 regulator-boot-on; 210 regulator-boot-on;
211 regulator-always-on; 211 regulator-always-on;
212 }; 212 };
213 213
214 sw3b_reg: sw3b { 214 sw3b_reg: sw3b {
215 regulator-min-microvolt = <400000>; 215 regulator-min-microvolt = <400000>;
216 regulator-max-microvolt = <1975000>; 216 regulator-max-microvolt = <1975000>;
217 regulator-boot-on; 217 regulator-boot-on;
218 regulator-always-on; 218 regulator-always-on;
219 }; 219 };
220 220
221 sw4_reg: sw4 { 221 sw4_reg: sw4 {
222 regulator-min-microvolt = <800000>; 222 regulator-min-microvolt = <800000>;
223 regulator-max-microvolt = <3300000>; 223 regulator-max-microvolt = <3300000>;
224 regulator-always-on; 224 regulator-always-on;
225 }; 225 };
226 226
227 swbst_reg: swbst { 227 swbst_reg: swbst {
228 regulator-min-microvolt = <5000000>; 228 regulator-min-microvolt = <5000000>;
229 regulator-max-microvolt = <5150000>; 229 regulator-max-microvolt = <5150000>;
230 }; 230 };
231 231
232 snvs_reg: vsnvs { 232 snvs_reg: vsnvs {
233 regulator-min-microvolt = <1000000>; 233 regulator-min-microvolt = <1000000>;
234 regulator-max-microvolt = <3000000>; 234 regulator-max-microvolt = <3000000>;
235 regulator-boot-on; 235 regulator-boot-on;
236 regulator-always-on; 236 regulator-always-on;
237 }; 237 };
238 238
239 vref_reg: vrefddr { 239 vref_reg: vrefddr {
240 regulator-boot-on; 240 regulator-boot-on;
241 regulator-always-on; 241 regulator-always-on;
242 }; 242 };
243 243
244 vgen1_reg: vgen1 { 244 vgen1_reg: vgen1 {
245 regulator-min-microvolt = <800000>; 245 regulator-min-microvolt = <800000>;
246 regulator-max-microvolt = <1550000>; 246 regulator-max-microvolt = <1550000>;
247 regulator-always-on; 247 regulator-always-on;
248 }; 248 };
249 249
250 vgen2_reg: vgen2 { 250 vgen2_reg: vgen2 {
251 regulator-min-microvolt = <800000>; 251 regulator-min-microvolt = <800000>;
252 regulator-max-microvolt = <1550000>; 252 regulator-max-microvolt = <1550000>;
253 }; 253 };
254 254
255 vgen3_reg: vgen3 { 255 vgen3_reg: vgen3 {
256 regulator-min-microvolt = <1800000>; 256 regulator-min-microvolt = <1800000>;
257 regulator-max-microvolt = <3300000>; 257 regulator-max-microvolt = <3300000>;
258 }; 258 };
259 259
260 vgen4_reg: vgen4 { 260 vgen4_reg: vgen4 {
261 regulator-min-microvolt = <1800000>; 261 regulator-min-microvolt = <1800000>;
262 regulator-max-microvolt = <3300000>; 262 regulator-max-microvolt = <3300000>;
263 regulator-always-on; 263 regulator-always-on;
264 }; 264 };
265 265
266 vgen5_reg: vgen5 { 266 vgen5_reg: vgen5 {
267 regulator-min-microvolt = <1800000>; 267 regulator-min-microvolt = <1800000>;
268 regulator-max-microvolt = <3300000>; 268 regulator-max-microvolt = <3300000>;
269 regulator-always-on; 269 regulator-always-on;
270 }; 270 };
271 271
272 vgen6_reg: vgen6 { 272 vgen6_reg: vgen6 {
273 regulator-min-microvolt = <1800000>; 273 regulator-min-microvolt = <1800000>;
274 regulator-max-microvolt = <3300000>; 274 regulator-max-microvolt = <3300000>;
275 regulator-always-on; 275 regulator-always-on;
276 }; 276 };
277 }; 277 };
278 }; 278 };
279 279
280 max17135: max17135@48 { 280 max17135: max17135@48 {
281 pinctrl-names = "default"; 281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_max17135>; 282 pinctrl-0 = <&pinctrl_max17135>;
283 compatible = "maxim,max17135"; 283 compatible = "maxim,max17135";
284 reg = <0x48>; 284 reg = <0x48>;
285 status = "okay"; 285 status = "okay";
286 286
287 vneg_pwrup = <1>; 287 vneg_pwrup = <1>;
288 gvee_pwrup = <2>; 288 gvee_pwrup = <2>;
289 vpos_pwrup = <10>; 289 vpos_pwrup = <10>;
290 gvdd_pwrup = <12>; 290 gvdd_pwrup = <12>;
291 gvdd_pwrdn = <1>; 291 gvdd_pwrdn = <1>;
292 vpos_pwrdn = <2>; 292 vpos_pwrdn = <2>;
293 gvee_pwrdn = <8>; 293 gvee_pwrdn = <8>;
294 vneg_pwrdn = <10>; 294 vneg_pwrdn = <10>;
295 gpio_pmic_pwrgood = <&gpio2 13 0>; 295 gpio_pmic_pwrgood = <&gpio2 13 0>;
296 gpio_pmic_vcom_ctrl = <&gpio2 3 0>; 296 gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
297 gpio_pmic_wakeup = <&gpio2 14 0>; 297 gpio_pmic_wakeup = <&gpio2 14 0>;
298 gpio_pmic_v3p3 = <&gpio2 7 0>; 298 gpio_pmic_v3p3 = <&gpio2 7 0>;
299 gpio_pmic_intr = <&gpio2 12 0>; 299 gpio_pmic_intr = <&gpio2 12 0>;
300 300
301 regulators { 301 regulators {
302 DISPLAY_reg: DISPLAY { 302 DISPLAY_reg: DISPLAY {
303 regulator-name = "DISPLAY"; 303 regulator-name = "DISPLAY";
304 }; 304 };
305 305
306 GVDD_reg: GVDD { 306 GVDD_reg: GVDD {
307 /* 20v */ 307 /* 20v */
308 regulator-name = "GVDD"; 308 regulator-name = "GVDD";
309 }; 309 };
310 310
311 GVEE_reg: GVEE { 311 GVEE_reg: GVEE {
312 /* -22v */ 312 /* -22v */
313 regulator-name = "GVEE"; 313 regulator-name = "GVEE";
314 }; 314 };
315 315
316 HVINN_reg: HVINN { 316 HVINN_reg: HVINN {
317 /* -22v */ 317 /* -22v */
318 regulator-name = "HVINN"; 318 regulator-name = "HVINN";
319 }; 319 };
320 320
321 HVINP_reg: HVINP { 321 HVINP_reg: HVINP {
322 /* 20v */ 322 /* 20v */
323 regulator-name = "HVINP"; 323 regulator-name = "HVINP";
324 }; 324 };
325 325
326 VCOM_reg: VCOM { 326 VCOM_reg: VCOM {
327 regulator-name = "VCOM"; 327 regulator-name = "VCOM";
328 /* Real max value: -500000 */ 328 /* Real max value: -500000 */
329 regulator-max-microvolt = <4325000>; 329 regulator-max-microvolt = <4325000>;
330 /* Real min value: -4325000 */ 330 /* Real min value: -4325000 */
331 regulator-min-microvolt = <500000>; 331 regulator-min-microvolt = <500000>;
332 }; 332 };
333 333
334 VNEG_reg: VNEG { 334 VNEG_reg: VNEG {
335 /* -15v */ 335 /* -15v */
336 regulator-name = "VNEG"; 336 regulator-name = "VNEG";
337 }; 337 };
338 338
339 VPOS_reg: VPOS { 339 VPOS_reg: VPOS {
340 /* 15v */ 340 /* 15v */
341 regulator-name = "VPOS"; 341 regulator-name = "VPOS";
342 }; 342 };
343 343
344 V3P3_reg: V3P3 { 344 V3P3_reg: V3P3 {
345 regulator-name = "V3P3"; 345 regulator-name = "V3P3";
346 }; 346 };
347 }; 347 };
348 }; 348 };
349 }; 349 };
350 350
351 &i2c3 { 351 &i2c3 {
352 clock-frequency = <100000>; 352 clock-frequency = <100000>;
353 pinctrl-names = "default", "gpio"; 353 pinctrl-names = "default", "gpio";
354 pinctrl-0 = <&pinctrl_i2c3>; 354 pinctrl-0 = <&pinctrl_i2c3>;
355 pinctrl-1 = <&pinctrl_i2c3_gpio>; 355 pinctrl-1 = <&pinctrl_i2c3_gpio>;
356 scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; 356 scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
357 sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 357 sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
358 status = "okay"; 358 status = "okay";
359 359
360 codec: wm8962@1a { 360 codec: wm8962@1a {
361 compatible = "wlf,wm8962"; 361 compatible = "wlf,wm8962";
362 reg = <0x1a>; 362 reg = <0x1a>;
363 clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>; 363 clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>;
364 DCVDD-supply = <&vgen3_reg>; 364 DCVDD-supply = <&vgen3_reg>;
365 DBVDD-supply = <&reg_aud3v>; 365 DBVDD-supply = <&reg_aud3v>;
366 AVDD-supply = <&vgen3_reg>; 366 AVDD-supply = <&vgen3_reg>;
367 CPVDD-supply = <&vgen3_reg>; 367 CPVDD-supply = <&vgen3_reg>;
368 MICVDD-supply = <&reg_aud3v>; 368 MICVDD-supply = <&reg_aud3v>;
369 PLLVDD-supply = <&vgen3_reg>; 369 PLLVDD-supply = <&vgen3_reg>;
370 SPKVDD1-supply = <&reg_aud4v>; 370 SPKVDD1-supply = <&reg_aud4v>;
371 SPKVDD2-supply = <&reg_aud4v>; 371 SPKVDD2-supply = <&reg_aud4v>;
372 amic-mono; 372 amic-mono;
373 }; 373 };
374 }; 374 };
375 375
376 &gpc { 376 &gpc {
377 fsl,ldo-bypass = <1>; 377 fsl,ldo-bypass = <1>;
378 }; 378 };
379 379
380 &iomuxc { 380 &iomuxc {
381 pinctrl-names = "default"; 381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_hog>; 382 pinctrl-0 = <&pinctrl_hog>;
383 383
384 imx6sll-evk { 384 imx6sll-evk {
385 pinctrl_hog: hoggrp { 385 pinctrl_hog: hoggrp {
386 fsl,pins = < 386 fsl,pins = <
387 MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 387 MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
388 MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059 388 MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059
389 MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059 389 MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059
390 /* 390 /*
391 * Must set the LVE of pad SD2_RESET, otherwise current 391 * Must set the LVE of pad SD2_RESET, otherwise current
392 * leakage through eMMC chip will pull high the VCCQ to 392 * leakage through eMMC chip will pull high the VCCQ to
393 * 2.6v, which will impact SD1 and SD3 SD3.0 voltage switch. 393 * 2.6v, which will impact SD1 and SD3 SD3.0 voltage switch.
394 */ 394 */
395 MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059 395 MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059
396 MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 396 MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
397 MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */ 397 MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */
398 MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */ 398 MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */
399 MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 399 MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059
400 MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */ 400 MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */
401 /* CHG_FLT, CHG_UOK/DOK, CHG_STATUS */ 401 /* CHG_FLT, CHG_UOK/DOK, CHG_STATUS */
402 MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000 402 MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
403 MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000 403 MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
404 MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000 404 MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000
405 >; 405 >;
406 }; 406 };
407 407
408 pinctrl_audmux3: audmux3grp { 408 pinctrl_audmux3: audmux3grp {
409 fsl,pins = < 409 fsl,pins = <
410 MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 410 MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
411 MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 411 MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
412 MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 412 MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
413 MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 413 MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
414 MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 414 MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
415 >; 415 >;
416 }; 416 };
417 417
418 pinctrl_csi1: csi1grp { 418 pinctrl_csi1: csi1grp {
419 fsl,pins = < 419 fsl,pins = <
420 MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x1b088 420 MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x1b088
421 MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x1b088 421 MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x1b088
422 MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x1b088 422 MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x1b088
423 MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x1b088 423 MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x1b088
424 MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x1b088 424 MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x1b088
425 MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x1b088 425 MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x1b088
426 MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x1b088 426 MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x1b088
427 MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x1b088 427 MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x1b088
428 MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x1b088 428 MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x1b088
429 MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x1b088 429 MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x1b088
430 MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x1b088 430 MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x1b088
431 MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x1b088 431 MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x1b088
432 MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000 432 MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000
433 MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000 433 MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000
434 >; 434 >;
435 }; 435 };
436 436
437 pinctrl_epdc0: epdcgrp0 { 437 pinctrl_epdc0: epdcgrp0 {
438 fsl,pins = < 438 fsl,pins = <
439 MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x100b1 439 MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x100b1
440 MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x100b1 440 MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x100b1
441 MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x100b1 441 MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x100b1
442 MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x100b1 442 MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x100b1
443 MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x100b1 443 MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x100b1
444 MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x100b1 444 MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x100b1
445 MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x100b1 445 MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x100b1
446 MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x100b1 446 MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x100b1
447 MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x100b1 447 MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x100b1
448 MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x100b1 448 MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x100b1
449 MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x100b1 449 MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x100b1
450 MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x100b1 450 MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x100b1
451 MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x100b1 451 MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x100b1
452 MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x100b1 452 MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x100b1
453 MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x100b1 453 MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x100b1
454 MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x100b1 454 MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x100b1
455 MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x100b1 455 MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x100b1
456 MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x100b1 456 MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x100b1
457 MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x100b1 457 MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x100b1
458 MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x100b1 458 MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x100b1
459 MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100b1 459 MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100b1
460 MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x100b1 460 MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x100b1
461 MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x100b1 461 MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x100b1
462 MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x100b1 462 MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x100b1
463 MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x100b1 463 MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x100b1
464 >; 464 >;
465 }; 465 };
466 466
467 pinctrl_lcdif_dat: lcdifdatgrp { 467 pinctrl_lcdif_dat: lcdifdatgrp {
468 fsl,pins = < 468 fsl,pins = <
469 MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79 469 MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79
470 MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79 470 MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79
471 MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79 471 MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79
472 MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79 472 MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79
473 MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79 473 MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79
474 MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79 474 MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79
475 MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79 475 MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79
476 MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79 476 MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79
477 MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79 477 MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79
478 MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79 478 MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79
479 MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79 479 MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79
480 MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79 480 MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79
481 MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79 481 MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79
482 MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79 482 MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79
483 MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79 483 MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79
484 MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79 484 MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79
485 MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79 485 MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79
486 MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79 486 MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79
487 MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79 487 MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79
488 MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79 488 MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79
489 MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79 489 MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79
490 MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79 490 MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79
491 MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79 491 MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79
492 MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79 492 MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79
493 >; 493 >;
494 }; 494 };
495 495
496 pinctrl_lcdif_ctrl: lcdifctrlgrp { 496 pinctrl_lcdif_ctrl: lcdifctrlgrp {
497 fsl,pins = < 497 fsl,pins = <
498 MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79 498 MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79
499 MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79 499 MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79
500 MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79 500 MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79
501 MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79 501 MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79
502 MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79 502 MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79
503 MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x79 503 MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x79
504 >; 504 >;
505 }; 505 };
506 506
507 pinctrl_max17135: max17135grp-1 { 507 pinctrl_max17135: max17135grp-1 {
508 fsl,pins = < 508 fsl,pins = <
509 MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x80000000 /* pwrgood */ 509 MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x80000000 /* pwrgood */
510 MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000 /* vcom_ctrl */ 510 MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000 /* vcom_ctrl */
511 MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x80000000 /* wakeup */ 511 MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x80000000 /* wakeup */
512 MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x80000000 /* v3p3 */ 512 MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x80000000 /* v3p3 */
513 MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x80000000 /* pwr int */ 513 MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x80000000 /* pwr int */
514 >; 514 >;
515 }; 515 };
516 516
517 pinctrl_spdif: spdifgrp { 517 pinctrl_spdif: spdifgrp {
518 fsl,pins = < 518 fsl,pins = <
519 MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x4130b0 519 MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x4130b0
520 >; 520 >;
521 }; 521 };
522 522
523 pinctrl_uart1: uart1grp { 523 pinctrl_uart1: uart1grp {
524 fsl,pins = < 524 fsl,pins = <
525 MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 525 MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
526 MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 526 MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
527 >; 527 >;
528 }; 528 };
529 529
530 pinctrl_uart5: uart5grp { 530 pinctrl_uart5: uart5grp {
531 fsl,pins = < 531 fsl,pins = <
532 MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x1b0b1 /* bt reg on */ 532 MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x1b0b1 /* bt reg on */
533 MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x1b0b1 533 MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x1b0b1
534 MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x1b0b1 534 MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x1b0b1
535 MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x1b0b1 535 MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x1b0b1
536 MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x1b0b1 536 MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x1b0b1
537 >; 537 >;
538 }; 538 };
539 539
540 pinctrl_uart5dte: uart5dtegrp { 540 pinctrl_uart5dte: uart5dtegrp {
541 fsl,pins = < 541 fsl,pins = <
542 MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x1b0b1 542 MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x1b0b1
543 MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x1b0b1 543 MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x1b0b1
544 MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x1b0b1 544 MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x1b0b1
545 MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x1b0b1 545 MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x1b0b1
546 >; 546 >;
547 }; 547 };
548 548
549 pinctrl_usdhc1: usdhc1grp { 549 pinctrl_usdhc1: usdhc1grp {
550 fsl,pins = < 550 fsl,pins = <
551 MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17061 551 MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17061
552 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13061 552 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13061
553 MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17061 553 MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17061
554 MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17061 554 MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17061
555 MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17061 555 MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17061
556 MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17061 556 MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17061
557 >; 557 >;
558 }; 558 };
559 559
560 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { 560 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
561 fsl,pins = < 561 fsl,pins = <
562 MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170a1 562 MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170a1
563 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130a1 563 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130a1
564 MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170a1 564 MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170a1
565 MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170a1 565 MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170a1
566 MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170a1 566 MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170a1
567 MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170a1 567 MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170a1
568 >; 568 >;
569 }; 569 };
570 570
571 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { 571 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
572 fsl,pins = < 572 fsl,pins = <
573 MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170e9 573 MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170e9
574 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9 574 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9
575 MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170e9 575 MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170e9
576 MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170e9 576 MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170e9
577 MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170e9 577 MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170e9
578 MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170e9 578 MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170e9
579 >; 579 >;
580 }; 580 };
581 581
582 pinctrl_usdhc2: usdhc2grp { 582 pinctrl_usdhc2: usdhc2grp {
583 fsl,pins = < 583 fsl,pins = <
584 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 584 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059
585 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 585 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059
586 MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 586 MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059
587 MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 587 MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059
588 MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 588 MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059
589 MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 589 MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059
590 MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059 590 MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059
591 MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059 591 MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059
592 MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059 592 MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059
593 MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059 593 MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059
594 MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x413059 594 MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x413059
595 >; 595 >;
596 }; 596 };
597 597
598 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { 598 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
599 fsl,pins = < 599 fsl,pins = <
600 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 600 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9
601 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 601 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9
602 MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 602 MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9
603 MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 603 MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9
604 MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 604 MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9
605 MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 605 MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9
606 MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9 606 MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9
607 MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9 607 MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9
608 MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9 608 MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9
609 MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9 609 MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9
610 MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130b9 610 MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130b9
611 >; 611 >;
612 }; 612 };
613 613
614 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { 614 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
615 fsl,pins = < 615 fsl,pins = <
616 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 616 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9
617 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 617 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9
618 MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 618 MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9
619 MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 619 MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9
620 MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 620 MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9
621 MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 621 MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9
622 MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9 622 MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9
623 MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9 623 MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9
624 MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9 624 MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9
625 MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9 625 MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9
626 MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130f9 626 MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130f9
627 >; 627 >;
628 }; 628 };
629 629
630 pinctrl_usdhc3: usdhc3grp { 630 pinctrl_usdhc3: usdhc3grp {
631 fsl,pins = < 631 fsl,pins = <
632 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17061 632 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17061
633 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13061 633 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13061
634 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17061 634 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17061
635 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17061 635 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17061
636 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17061 636 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17061
637 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17061 637 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17061
638 >; 638 >;
639 }; 639 };
640 640
641 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { 641 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
642 fsl,pins = < 642 fsl,pins = <
643 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170a1 643 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170a1
644 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130a1 644 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130a1
645 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170a1 645 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170a1
646 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170a1 646 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170a1
647 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170a1 647 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170a1
648 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170a1 648 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170a1
649 >; 649 >;
650 }; 650 };
651 651
652 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { 652 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
653 fsl,pins = < 653 fsl,pins = <
654 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170e9 654 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170e9
655 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9 655 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9
656 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170e9 656 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170e9
657 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170e9 657 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170e9
658 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170e9 658 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170e9
659 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170e9 659 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170e9
660 >; 660 >;
661 }; 661 };
662 662
663 pinctrl_usbotg1: usbotg1grp { 663 pinctrl_usbotg1: usbotg1grp {
664 fsl,pins = < 664 fsl,pins = <
665 MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 665 MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
666 >; 666 >;
667 }; 667 };
668 668
669 pinctrl_i2c1: i2c1grp { 669 pinctrl_i2c1: i2c1grp {
670 fsl,pins = < 670 fsl,pins = <
671 MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 671 MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
672 MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 672 MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
673 >; 673 >;
674 }; 674 };
675 675
676 pinctrl_i2c1_gpio: i2c1grp_gpio { 676 pinctrl_i2c1_gpio: i2c1grp_gpio {
677 fsl,pins = < 677 fsl,pins = <
678 MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x1b8b1 678 MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x1b8b1
679 MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x1b8b1 679 MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x1b8b1
680 >; 680 >;
681 }; 681 };
682 682
683 pinctrl_i2c3: i2c3grp { 683 pinctrl_i2c3: i2c3grp {
684 fsl,pins = < 684 fsl,pins = <
685 MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1 685 MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1
686 MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1 686 MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1
687 >; 687 >;
688 }; 688 };
689 689
690 pinctrl_i2c3_gpio: i2c3grp_gpio { 690 pinctrl_i2c3_gpio: i2c3grp_gpio {
691 fsl,pins = < 691 fsl,pins = <
692 MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0x41b8b1 692 MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0x41b8b1
693 MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0x41b8b1 693 MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0x41b8b1
694 >; 694 >;
695 }; 695 };
696 696
697 pinctrl_pwm1: pmw1grp { 697 pinctrl_pwm1: pmw1grp {
698 fsl,pins = < 698 fsl,pins = <
699 MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 699 MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0
700 >; 700 >;
701 }; 701 };
702 702
703 pinctrl_wdog1: wdog1grp { 703 pinctrl_wdog1: wdog1grp {
704 fsl,pins = < 704 fsl,pins = <
705 MX6SLL_PAD_WDOG_B__WDOG1_B 0x170b0 705 MX6SLL_PAD_WDOG_B__WDOG1_B 0x170b0
706 >; 706 >;
707 }; 707 };
708 }; 708 };
709 }; 709 };
710 710
711 &lcdif { 711 &lcdif {
712 pinctrl-names = "default"; 712 pinctrl-names = "default";
713 pinctrl-0 = <&pinctrl_lcdif_dat 713 pinctrl-0 = <&pinctrl_lcdif_dat
714 &pinctrl_lcdif_ctrl>; 714 &pinctrl_lcdif_ctrl>;
715 lcd-supply = <&reg_lcd>; 715 lcd-supply = <&reg_lcd>;
716 display = <&display0>; 716 display = <&display0>;
717 status = "okay"; 717 status = "okay";
718 718
719 display0: display@0 { 719 display0: display@0 {
720 bits-per-pixel = <16>; 720 bits-per-pixel = <16>;
721 bus-width = <24>; 721 bus-width = <24>;
722 722
723 display-timings { 723 display-timings {
724 native-mode = <&timing0>; 724 native-mode = <&timing0>;
725 timing0: timing0 { 725 timing0: timing0 {
726 clock-frequency = <33500000>; 726 clock-frequency = <33500000>;
727 hactive = <800>; 727 hactive = <800>;
728 vactive = <480>; 728 vactive = <480>;
729 hback-porch = <89>; 729 hback-porch = <89>;
730 hfront-porch = <164>; 730 hfront-porch = <164>;
731 vback-porch = <23>; 731 vback-porch = <23>;
732 vfront-porch = <10>; 732 vfront-porch = <10>;
733 hsync-len = <10>; 733 hsync-len = <10>;
734 vsync-len = <10>; 734 vsync-len = <10>;
735 hsync-active = <0>; 735 hsync-active = <0>;
736 vsync-active = <0>; 736 vsync-active = <0>;
737 de-active = <1>; 737 de-active = <1>;
738 pixelclk-active = <0>; 738 pixelclk-active = <0>;
739 }; 739 };
740 }; 740 };
741 }; 741 };
742 }; 742 };
743 743
744 &pxp { 744 &pxp {
745 status = "okay"; 745 status = "okay";
746 }; 746 };
747 747
748 &pwm1 { 748 &pwm1 {
749 pinctrl-names = "default"; 749 pinctrl-names = "default";
750 pinctrl-0 = <&pinctrl_pwm1>; 750 pinctrl-0 = <&pinctrl_pwm1>;
751 status = "okay"; 751 status = "okay";
752 }; 752 };
753 753
754 &uart1 { 754 &uart1 {
755 pinctrl-names = "default"; 755 pinctrl-names = "default";
756 pinctrl-0 = <&pinctrl_uart1>; 756 pinctrl-0 = <&pinctrl_uart1>;
757 status = "okay"; 757 status = "okay";
758 }; 758 };
759 759
760 &uart5 { 760 &uart5 {
761 pinctrl-names = "default"; 761 pinctrl-names = "default";
762 pinctrl-0 = <&pinctrl_uart5>; 762 pinctrl-0 = <&pinctrl_uart5>;
763 fsl,uart-has-rtscts; 763 fsl,uart-has-rtscts;
764 /* for DTE mode, add below change */ 764 /* for DTE mode, add below change */
765 /* fsl,dte-mode; */ 765 /* fsl,dte-mode; */
766 /* pinctrl-0 = <&pinctrl_uart5dte>; */ 766 /* pinctrl-0 = <&pinctrl_uart5dte>; */
767 status = "disabled"; 767 status = "disabled";
768 }; 768 };
769 769
770 &usdhc1 { 770 &usdhc1 {
771 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 771 pinctrl-names = "default", "state_100mhz", "state_200mhz";
772 pinctrl-0 = <&pinctrl_usdhc1>; 772 pinctrl-0 = <&pinctrl_usdhc1>;
773 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 773 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
774 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 774 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
775 cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; 775 cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
776 wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; 776 wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
777 keep-power-in-suspend; 777 keep-power-in-suspend;
778 enable-sdio-wakeup; 778 enable-sdio-wakeup;
779 vmmc-supply = <&reg_sd1_vmmc>; 779 vmmc-supply = <&reg_sd1_vmmc>;
780 status = "okay"; 780 status = "okay";
781 }; 781 };
782 782
783 &usdhc2 { 783 &usdhc2 {
784 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 784 pinctrl-names = "default", "state_100mhz", "state_200mhz";
785 pinctrl-0 = <&pinctrl_usdhc2>; 785 pinctrl-0 = <&pinctrl_usdhc2>;
786 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 786 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
787 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 787 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
788 vqmmc-supply = <&reg_sd2_vmmc>; 788 vqmmc-supply = <&reg_sd2_vmmc>;
789 bus-width = <8>; 789 bus-width = <8>;
790 non-removable; 790 non-removable;
791 status = "okay"; 791 status = "okay";
792 }; 792 };
793 793
794 &usdhc3 { 794 &usdhc3 {
795 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 795 pinctrl-names = "default", "state_100mhz", "state_200mhz";
796 pinctrl-0 = <&pinctrl_usdhc3>; 796 pinctrl-0 = <&pinctrl_usdhc3>;
797 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 797 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
798 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 798 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
799 cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; 799 cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
800 keep-power-in-suspend; 800 keep-power-in-suspend;
801 enable-sdio-wakeup; 801 enable-sdio-wakeup;
802 vmmc-supply = <&reg_sd3_vmmc>; 802 vmmc-supply = <&reg_sd3_vmmc>;
803 status = "okay"; 803 status = "okay";
804 }; 804 };
805 805
806 &usbotg1 { 806 &usbotg1 {
807 vbus-supply = <&reg_usb_otg1_vbus>; 807 vbus-supply = <&reg_usb_otg1_vbus>;
808 pinctrl-names = "default"; 808 pinctrl-names = "default";
809 pinctrl-0 = <&pinctrl_usbotg1>; 809 pinctrl-0 = <&pinctrl_usbotg1>;
810 disable-over-current; 810 disable-over-current;
811 srp-disable; 811 srp-disable;
812 hnp-disable; 812 hnp-disable;
813 adp-disable; 813 adp-disable;
814 status = "okay"; 814 status = "okay";
815 }; 815 };
816 816
817 &usbotg2 { 817 &usbotg2 {
818 vbus-supply = <&reg_usb_otg2_vbus>; 818 vbus-supply = <&reg_usb_otg2_vbus>;
819 dr_mode = "host"; 819 dr_mode = "host";
820 disable-over-current; 820 disable-over-current;
821 status = "okay"; 821 status = "okay";
822 }; 822 };
823 823
824 &epdc { 824 &epdc {
825 pinctrl-names = "default"; 825 pinctrl-names = "default";
826 pinctrl-0 = <&pinctrl_epdc0>; 826 pinctrl-0 = <&pinctrl_epdc0>;
827 V3P3-supply = <&V3P3_reg>; 827 V3P3-supply = <&V3P3_reg>;
828 VCOM-supply = <&VCOM_reg>; 828 VCOM-supply = <&VCOM_reg>;
829 DISPLAY-supply = <&DISPLAY_reg>; 829 DISPLAY-supply = <&DISPLAY_reg>;
830 status = "okay"; 830 status = "okay";
831 }; 831 };
832 832
833 &ssi2 { 833 &ssi2 {
834 status = "okay"; 834 status = "okay";
835 }; 835 };
836 836
837 &wdog1 { 837 &wdog1 {
838 pinctrl-names = "default"; 838 pinctrl-names = "default";
839 pinctrl-0 = <&pinctrl_wdog1>; 839 pinctrl-0 = <&pinctrl_wdog1>;
840 fsl,ext-reset-output; 840 fsl,ext-reset-output;
841 }; 841 };
842 842
arch/arm/dts/imx6sll-lpddr3-arm2.dts
Diff comments   View file @ 4daafb3
1 /* 1 /*
2 * Copyright (C) 2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h> 12 #include <dt-bindings/input/input.h>
13 #include "imx6sll.dtsi" 13 #include "imx6sll.dtsi"
14 14
15 / { 15 / {
16 model = "Freescale i.MX6SLL LPDDR3 ARM2 Board"; 16 model = "Freescale i.MX6SLL LPDDR3 ARM2 Board";
17 compatible = "fsl,imx6sll-lpddr3-arm2", "fsl,imx6sll"; 17 compatible = "fsl,imx6sll-lpddr3-arm2", "fsl,imx6sll";
18 18
19 memory { 19 memory {
20 reg = <0x80000000 0x80000000>; 20 reg = <0x80000000 0x80000000>;
21 }; 21 };
22 22
23 leds { 23 leds {
24 compatible = "gpio-leds"; 24 compatible = "gpio-leds";
25 pinctrl-names = "default"; 25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_led>; 26 pinctrl-0 = <&pinctrl_led>;
27 27
28 users { 28 users {
29 label = "debug"; 29 label = "debug";
30 gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; 30 gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
31 linux,default-trigger = "heartbeat"; 31 linux,default-trigger = "heartbeat";
32 }; 32 };
33 }; 33 };
34 34
35 backlight { 35 backlight {
36 compatible = "pwm-backlight"; 36 compatible = "pwm-backlight";
37 pwms = <&pwm1 0 5000000>; 37 pwms = <&pwm1 0 5000000>;
38 brightness-levels = <0 4 8 16 32 64 128 255>; 38 brightness-levels = <0 4 8 16 32 64 128 255>;
39 default-brightness-level = <6>; 39 default-brightness-level = <6>;
40 status = "okay"; 40 status = "okay";
41 }; 41 };
42 42
43 pxp_v4l2_out { 43 pxp_v4l2_out {
44 compatible = "fsl,imx6sl-pxp-v4l2"; 44 compatible = "fsl,imx6sl-pxp-v4l2";
45 status = "okay"; 45 status = "okay";
46 }; 46 };
47 47
48 regulators { 48 regulators {
49 compatible = "simple-bus"; 49 compatible = "simple-bus";
50 #address-cells = <1>; 50 #address-cells = <1>;
51 #size-cells = <0>; 51 #size-cells = <0>;
52 52
53 reg_usb_otg1_vbus: regulator@0 { 53 reg_usb_otg1_vbus: regulator@0 {
54 compatible = "regulator-fixed"; 54 compatible = "regulator-fixed";
55 reg = <0>; 55 reg = <0>;
56 regulator-name = "usb_otg1_vbus"; 56 regulator-name = "usb_otg1_vbus";
57 regulator-min-microvolt = <5000000>; 57 regulator-min-microvolt = <5000000>;
58 regulator-max-microvolt = <5000000>; 58 regulator-max-microvolt = <5000000>;
59 gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; 59 gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
60 enable-active-high; 60 enable-active-high;
61 vin-supply = <&swbst_reg>; 61 vin-supply = <&swbst_reg>;
62 }; 62 };
63 63
64 reg_usb_otg2_vbus: regulator@1 { 64 reg_usb_otg2_vbus: regulator@1 {
65 compatible = "regulator-fixed"; 65 compatible = "regulator-fixed";
66 reg = <1>; 66 reg = <1>;
67 regulator-name = "usb_otg2_vbus"; 67 regulator-name = "usb_otg2_vbus";
68 regulator-min-microvolt = <5000000>; 68 regulator-min-microvolt = <5000000>;
69 regulator-max-microvolt = <5000000>; 69 regulator-max-microvolt = <5000000>;
70 gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; 70 gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
71 enable-active-high; 71 enable-active-high;
72 vin-supply = <&swbst_reg>; 72 vin-supply = <&swbst_reg>;
73 }; 73 };
74 74
75 reg_aud3v: regulator@2 { 75 reg_aud3v: regulator@2 {
76 compatible = "regulator-fixed"; 76 compatible = "regulator-fixed";
77 reg = <2>; 77 reg = <2>;
78 regulator-name = "wm8962-supply-3v15"; 78 regulator-name = "wm8962-supply-3v15";
79 regulator-min-microvolt = <3150000>; 79 regulator-min-microvolt = <3150000>;
80 regulator-max-microvolt = <3150000>; 80 regulator-max-microvolt = <3150000>;
81 regulator-boot-on; 81 regulator-boot-on;
82 }; 82 };
83 83
84 reg_aud4v: regulator@3 { 84 reg_aud4v: regulator@3 {
85 compatible = "regulator-fixed"; 85 compatible = "regulator-fixed";
86 reg = <3>; 86 reg = <3>;
87 regulator-name = "wm8962-supply-4v2"; 87 regulator-name = "wm8962-supply-4v2";
88 regulator-min-microvolt = <4325000>; 88 regulator-min-microvolt = <4325000>;
89 regulator-max-microvolt = <4325000>; 89 regulator-max-microvolt = <4325000>;
90 regulator-boot-on; 90 regulator-boot-on;
91 }; 91 };
92 92
93 reg_lcd: regulator@4 { 93 reg_lcd: regulator@4 {
94 compatible = "regulator-fixed"; 94 compatible = "regulator-fixed";
95 reg = <4>; 95 reg = <4>;
96 regulator-name = "lcd-pwr"; 96 regulator-name = "lcd-pwr";
97 gpio = <&gpio4 8 0>; 97 gpio = <&gpio4 8 0>;
98 enable-active-high; 98 enable-active-high;
99 }; 99 };
100 100
101 reg_sd1_vmmc: sd1_vmmc { 101 reg_sd1_vmmc: sd1_vmmc {
102 compatible = "regulator-fixed"; 102 compatible = "regulator-fixed";
103 regulator-name = "SD1_SPWR"; 103 regulator-name = "SD1_SPWR";
104 regulator-min-microvolt = <3000000>; 104 regulator-min-microvolt = <3000000>;
105 regulator-max-microvolt = <3000000>; 105 regulator-max-microvolt = <3000000>;
106 gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; 106 gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
107 off-on-delay = <20000>; 107 u-boot,off-on-delay-us = <20000>;
108 enable-active-high; 108 enable-active-high;
109 }; 109 };
110 110
111 reg_sd2_vmmc: sd2_vmmc { 111 reg_sd2_vmmc: sd2_vmmc {
112 compatible = "regulator-fixed"; 112 compatible = "regulator-fixed";
113 regulator-name = "eMMC_VCCQ"; 113 regulator-name = "eMMC_VCCQ";
114 regulator-min-microvolt = <1800000>; 114 regulator-min-microvolt = <1800000>;
115 regulator-max-microvolt = <1800000>; 115 regulator-max-microvolt = <1800000>;
116 regulator-boot-on; 116 regulator-boot-on;
117 }; 117 };
118 118
119 reg_sd3_vmmc: sd3_vmmc { 119 reg_sd3_vmmc: sd3_vmmc {
120 compatible = "regulator-fixed"; 120 compatible = "regulator-fixed";
121 regulator-name = "SD3_WIFI"; 121 regulator-name = "SD3_WIFI";
122 regulator-min-microvolt = <3000000>; 122 regulator-min-microvolt = <3000000>;
123 regulator-max-microvolt = <3000000>; 123 regulator-max-microvolt = <3000000>;
124 gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; 124 gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
125 off-on-delay = <20000>; 125 u-boot,off-on-delay-us = <20000>;
126 enable-active-high; 126 enable-active-high;
127 }; 127 };
128 128
129 }; 129 };
130 130
131 sound { 131 sound {
132 compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; 132 compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
133 model = "wm8962-audio"; 133 model = "wm8962-audio";
134 cpu-dai = <&ssi2>; 134 cpu-dai = <&ssi2>;
135 audio-codec = <&codec>; 135 audio-codec = <&codec>;
136 audio-routing = 136 audio-routing =
137 "Headphone Jack", "HPOUTL", 137 "Headphone Jack", "HPOUTL",
138 "Headphone Jack", "HPOUTR", 138 "Headphone Jack", "HPOUTR",
139 "Ext Spk", "SPKOUTL", 139 "Ext Spk", "SPKOUTL",
140 "Ext Spk", "SPKOUTR", 140 "Ext Spk", "SPKOUTR",
141 "AMIC", "MICBIAS", 141 "AMIC", "MICBIAS",
142 "IN3R", "AMIC"; 142 "IN3R", "AMIC";
143 mux-int-port = <2>; 143 mux-int-port = <2>;
144 mux-ext-port = <3>; 144 mux-ext-port = <3>;
145 codec-master; 145 codec-master;
146 hp-det-gpios = <&gpio4 24 1>; 146 hp-det-gpios = <&gpio4 24 1>;
147 }; 147 };
148 }; 148 };
149 149
150 &audmux { 150 &audmux {
151 pinctrl-names = "default"; 151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_audmux3>; 152 pinctrl-0 = <&pinctrl_audmux3>;
153 status = "okay"; 153 status = "okay";
154 }; 154 };
155 155
156 &clks { 156 &clks {
157 assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; 157 assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
158 assigned-clock-rates = <393216000>; 158 assigned-clock-rates = <393216000>;
159 }; 159 };
160 160
161 &cpu0 { 161 &cpu0 {
162 arm-supply = <&sw1a_reg>; 162 arm-supply = <&sw1a_reg>;
163 soc-supply = <&sw1c_reg>; 163 soc-supply = <&sw1c_reg>;
164 }; 164 };
165 165
166 &csi { 166 &csi {
167 status = "disabled"; 167 status = "disabled";
168 168
169 port { 169 port {
170 csi1_ep: endpoint { 170 csi1_ep: endpoint {
171 remote-endpoint = <&ov5640_ep>; 171 remote-endpoint = <&ov5640_ep>;
172 }; 172 };
173 }; 173 };
174 }; 174 };
175 175
176 &i2c1 { 176 &i2c1 {
177 clock-frequency = <100000>; 177 clock-frequency = <100000>;
178 pinctrl-names = "default", "gpio"; 178 pinctrl-names = "default", "gpio";
179 pinctrl-0 = <&pinctrl_i2c1>; 179 pinctrl-0 = <&pinctrl_i2c1>;
180 pinctrl-1 = <&pinctrl_i2c1_gpio>; 180 pinctrl-1 = <&pinctrl_i2c1_gpio>;
181 scl-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; 181 scl-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
182 sda-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; 182 sda-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
183 status = "okay"; 183 status = "okay";
184 184
185 pmic: pfuze100@08 { 185 pmic: pfuze100@08 {
186 compatible = "fsl,pfuze100"; 186 compatible = "fsl,pfuze100";
187 reg = <0x08>; 187 reg = <0x08>;
188 188
189 regulators { 189 regulators {
190 sw1a_reg: sw1ab { 190 sw1a_reg: sw1ab {
191 regulator-min-microvolt = <300000>; 191 regulator-min-microvolt = <300000>;
192 regulator-max-microvolt = <1875000>; 192 regulator-max-microvolt = <1875000>;
193 regulator-boot-on; 193 regulator-boot-on;
194 regulator-always-on; 194 regulator-always-on;
195 regulator-ramp-delay = <6250>; 195 regulator-ramp-delay = <6250>;
196 }; 196 };
197 197
198 sw1c_reg: sw1c { 198 sw1c_reg: sw1c {
199 regulator-min-microvolt = <300000>; 199 regulator-min-microvolt = <300000>;
200 regulator-max-microvolt = <1875000>; 200 regulator-max-microvolt = <1875000>;
201 regulator-boot-on; 201 regulator-boot-on;
202 regulator-always-on; 202 regulator-always-on;
203 regulator-ramp-delay = <6250>; 203 regulator-ramp-delay = <6250>;
204 }; 204 };
205 205
206 sw2_reg: sw2 { 206 sw2_reg: sw2 {
207 regulator-min-microvolt = <800000>; 207 regulator-min-microvolt = <800000>;
208 regulator-max-microvolt = <3300000>; 208 regulator-max-microvolt = <3300000>;
209 regulator-boot-on; 209 regulator-boot-on;
210 regulator-always-on; 210 regulator-always-on;
211 }; 211 };
212 212
213 sw3a_reg: sw3a { 213 sw3a_reg: sw3a {
214 regulator-min-microvolt = <400000>; 214 regulator-min-microvolt = <400000>;
215 regulator-max-microvolt = <1975000>; 215 regulator-max-microvolt = <1975000>;
216 regulator-boot-on; 216 regulator-boot-on;
217 regulator-always-on; 217 regulator-always-on;
218 }; 218 };
219 219
220 sw3b_reg: sw3b { 220 sw3b_reg: sw3b {
221 regulator-min-microvolt = <400000>; 221 regulator-min-microvolt = <400000>;
222 regulator-max-microvolt = <1975000>; 222 regulator-max-microvolt = <1975000>;
223 regulator-boot-on; 223 regulator-boot-on;
224 regulator-always-on; 224 regulator-always-on;
225 }; 225 };
226 226
227 sw4_reg: sw4 { 227 sw4_reg: sw4 {
228 regulator-min-microvolt = <800000>; 228 regulator-min-microvolt = <800000>;
229 regulator-max-microvolt = <3300000>; 229 regulator-max-microvolt = <3300000>;
230 regulator-always-on; 230 regulator-always-on;
231 }; 231 };
232 232
233 swbst_reg: swbst { 233 swbst_reg: swbst {
234 regulator-min-microvolt = <5000000>; 234 regulator-min-microvolt = <5000000>;
235 regulator-max-microvolt = <5150000>; 235 regulator-max-microvolt = <5150000>;
236 }; 236 };
237 237
238 snvs_reg: vsnvs { 238 snvs_reg: vsnvs {
239 regulator-min-microvolt = <1000000>; 239 regulator-min-microvolt = <1000000>;
240 regulator-max-microvolt = <3000000>; 240 regulator-max-microvolt = <3000000>;
241 regulator-boot-on; 241 regulator-boot-on;
242 regulator-always-on; 242 regulator-always-on;
243 }; 243 };
244 244
245 vref_reg: vrefddr { 245 vref_reg: vrefddr {
246 regulator-boot-on; 246 regulator-boot-on;
247 regulator-always-on; 247 regulator-always-on;
248 }; 248 };
249 249
250 vgen1_reg: vgen1 { 250 vgen1_reg: vgen1 {
251 regulator-min-microvolt = <800000>; 251 regulator-min-microvolt = <800000>;
252 regulator-max-microvolt = <1550000>; 252 regulator-max-microvolt = <1550000>;
253 regulator-always-on; 253 regulator-always-on;
254 }; 254 };
255 255
256 vgen2_reg: vgen2 { 256 vgen2_reg: vgen2 {
257 regulator-min-microvolt = <800000>; 257 regulator-min-microvolt = <800000>;
258 regulator-max-microvolt = <1550000>; 258 regulator-max-microvolt = <1550000>;
259 }; 259 };
260 260
261 vgen3_reg: vgen3 { 261 vgen3_reg: vgen3 {
262 regulator-min-microvolt = <1800000>; 262 regulator-min-microvolt = <1800000>;
263 regulator-max-microvolt = <3300000>; 263 regulator-max-microvolt = <3300000>;
264 }; 264 };
265 265
266 vgen4_reg: vgen4 { 266 vgen4_reg: vgen4 {
267 regulator-min-microvolt = <1800000>; 267 regulator-min-microvolt = <1800000>;
268 regulator-max-microvolt = <3300000>; 268 regulator-max-microvolt = <3300000>;
269 regulator-always-on; 269 regulator-always-on;
270 }; 270 };
271 271
272 vgen5_reg: vgen5 { 272 vgen5_reg: vgen5 {
273 regulator-min-microvolt = <1800000>; 273 regulator-min-microvolt = <1800000>;
274 regulator-max-microvolt = <3300000>; 274 regulator-max-microvolt = <3300000>;
275 regulator-always-on; 275 regulator-always-on;
276 }; 276 };
277 277
278 vgen6_reg: vgen6 { 278 vgen6_reg: vgen6 {
279 regulator-min-microvolt = <1800000>; 279 regulator-min-microvolt = <1800000>;
280 regulator-max-microvolt = <3300000>; 280 regulator-max-microvolt = <3300000>;
281 regulator-always-on; 281 regulator-always-on;
282 }; 282 };
283 }; 283 };
284 }; 284 };
285 285
286 max17135: max17135@48 { 286 max17135: max17135@48 {
287 pinctrl-names = "default"; 287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_max17135>; 288 pinctrl-0 = <&pinctrl_max17135>;
289 compatible = "maxim,max17135"; 289 compatible = "maxim,max17135";
290 reg = <0x48>; 290 reg = <0x48>;
291 status = "okay"; 291 status = "okay";
292 292
293 vneg_pwrup = <1>; 293 vneg_pwrup = <1>;
294 gvee_pwrup = <2>; 294 gvee_pwrup = <2>;
295 vpos_pwrup = <10>; 295 vpos_pwrup = <10>;
296 gvdd_pwrup = <12>; 296 gvdd_pwrup = <12>;
297 gvdd_pwrdn = <1>; 297 gvdd_pwrdn = <1>;
298 vpos_pwrdn = <2>; 298 vpos_pwrdn = <2>;
299 gvee_pwrdn = <8>; 299 gvee_pwrdn = <8>;
300 vneg_pwrdn = <10>; 300 vneg_pwrdn = <10>;
301 gpio_pmic_pwrgood = <&gpio2 13 0>; 301 gpio_pmic_pwrgood = <&gpio2 13 0>;
302 gpio_pmic_vcom_ctrl = <&gpio2 3 0>; 302 gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
303 gpio_pmic_wakeup = <&gpio2 14 0>; 303 gpio_pmic_wakeup = <&gpio2 14 0>;
304 gpio_pmic_v3p3 = <&gpio2 7 0>; 304 gpio_pmic_v3p3 = <&gpio2 7 0>;
305 gpio_pmic_intr = <&gpio2 12 0>; 305 gpio_pmic_intr = <&gpio2 12 0>;
306 306
307 regulators { 307 regulators {
308 DISPLAY_reg: DISPLAY { 308 DISPLAY_reg: DISPLAY {
309 regulator-name = "DISPLAY"; 309 regulator-name = "DISPLAY";
310 }; 310 };
311 311
312 GVDD_reg: GVDD { 312 GVDD_reg: GVDD {
313 /* 20v */ 313 /* 20v */
314 regulator-name = "GVDD"; 314 regulator-name = "GVDD";
315 }; 315 };
316 316
317 GVEE_reg: GVEE { 317 GVEE_reg: GVEE {
318 /* -22v */ 318 /* -22v */
319 regulator-name = "GVEE"; 319 regulator-name = "GVEE";
320 }; 320 };
321 321
322 HVINN_reg: HVINN { 322 HVINN_reg: HVINN {
323 /* -22v */ 323 /* -22v */
324 regulator-name = "HVINN"; 324 regulator-name = "HVINN";
325 }; 325 };
326 326
327 HVINP_reg: HVINP { 327 HVINP_reg: HVINP {
328 /* 20v */ 328 /* 20v */
329 regulator-name = "HVINP"; 329 regulator-name = "HVINP";
330 }; 330 };
331 331
332 VCOM_reg: VCOM { 332 VCOM_reg: VCOM {
333 regulator-name = "VCOM"; 333 regulator-name = "VCOM";
334 /* Real max value: -500000 */ 334 /* Real max value: -500000 */
335 regulator-max-microvolt = <4325000>; 335 regulator-max-microvolt = <4325000>;
336 /* Real min value: -4325000 */ 336 /* Real min value: -4325000 */
337 regulator-min-microvolt = <500000>; 337 regulator-min-microvolt = <500000>;
338 }; 338 };
339 339
340 VNEG_reg: VNEG { 340 VNEG_reg: VNEG {
341 /* -15v */ 341 /* -15v */
342 regulator-name = "VNEG"; 342 regulator-name = "VNEG";
343 }; 343 };
344 344
345 VPOS_reg: VPOS { 345 VPOS_reg: VPOS {
346 /* 15v */ 346 /* 15v */
347 regulator-name = "VPOS"; 347 regulator-name = "VPOS";
348 }; 348 };
349 349
350 V3P3_reg: V3P3 { 350 V3P3_reg: V3P3 {
351 regulator-name = "V3P3"; 351 regulator-name = "V3P3";
352 }; 352 };
353 }; 353 };
354 }; 354 };
355 }; 355 };
356 356
357 &i2c3 { 357 &i2c3 {
358 clock-frequency = <100000>; 358 clock-frequency = <100000>;
359 pinctrl-names = "default", "gpio"; 359 pinctrl-names = "default", "gpio";
360 pinctrl-0 = <&pinctrl_i2c3>; 360 pinctrl-0 = <&pinctrl_i2c3>;
361 pinctrl-1 = <&pinctrl_i2c3_gpio>; 361 pinctrl-1 = <&pinctrl_i2c3_gpio>;
362 scl-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; 362 scl-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
363 sda-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; 363 sda-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
364 status = "okay"; 364 status = "okay";
365 365
366 codec: wm8962@1a { 366 codec: wm8962@1a {
367 compatible = "wlf,wm8962"; 367 compatible = "wlf,wm8962";
368 reg = <0x1a>; 368 reg = <0x1a>;
369 clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>; 369 clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>;
370 DCVDD-supply = <&vgen3_reg>; 370 DCVDD-supply = <&vgen3_reg>;
371 DBVDD-supply = <&reg_aud3v>; 371 DBVDD-supply = <&reg_aud3v>;
372 AVDD-supply = <&vgen3_reg>; 372 AVDD-supply = <&vgen3_reg>;
373 CPVDD-supply = <&vgen3_reg>; 373 CPVDD-supply = <&vgen3_reg>;
374 MICVDD-supply = <&reg_aud3v>; 374 MICVDD-supply = <&reg_aud3v>;
375 PLLVDD-supply = <&vgen3_reg>; 375 PLLVDD-supply = <&vgen3_reg>;
376 SPKVDD1-supply = <&reg_aud4v>; 376 SPKVDD1-supply = <&reg_aud4v>;
377 SPKVDD2-supply = <&reg_aud4v>; 377 SPKVDD2-supply = <&reg_aud4v>;
378 amic-mono; 378 amic-mono;
379 }; 379 };
380 380
381 ov5640: ov5640@3c { 381 ov5640: ov5640@3c {
382 compatible = "ovti,ov5640"; 382 compatible = "ovti,ov5640";
383 reg = <0x3c>; 383 reg = <0x3c>;
384 pinctrl-names = "default"; 384 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_csi1>; 385 pinctrl-0 = <&pinctrl_csi1>;
386 clocks = <&clks IMX6SLL_CLK_CSI>; 386 clocks = <&clks IMX6SLL_CLK_CSI>;
387 clock-names = "csi_mclk"; 387 clock-names = "csi_mclk";
388 AVDD-supply = <&vgen6_reg>; /* 2.8v */ 388 AVDD-supply = <&vgen6_reg>; /* 2.8v */
389 DVDD-supply = <&vgen2_reg>; /* 1.5v*/ 389 DVDD-supply = <&vgen2_reg>; /* 1.5v*/
390 pwn-gpios = <&gpio1 25 1>; 390 pwn-gpios = <&gpio1 25 1>;
391 rst-gpios = <&gpio1 26 0>; 391 rst-gpios = <&gpio1 26 0>;
392 csi_id = <0>; 392 csi_id = <0>;
393 mclk = <24000000>; 393 mclk = <24000000>;
394 mclk_source = <0>; 394 mclk_source = <0>;
395 status = "disabled"; 395 status = "disabled";
396 port { 396 port {
397 ov5640_ep: endpoint { 397 ov5640_ep: endpoint {
398 remote-endpoint = <&csi1_ep>; 398 remote-endpoint = <&csi1_ep>;
399 }; 399 };
400 }; 400 };
401 }; 401 };
402 }; 402 };
403 403
404 &gpc { 404 &gpc {
405 fsl,ldo-bypass = <1>; 405 fsl,ldo-bypass = <1>;
406 }; 406 };
407 407
408 &iomuxc { 408 &iomuxc {
409 pinctrl-names = "default"; 409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_hog &pinctrl_hog_sd2_reset>; 410 pinctrl-0 = <&pinctrl_hog &pinctrl_hog_sd2_reset>;
411 411
412 imx6sll-lpddr3-arm2 { 412 imx6sll-lpddr3-arm2 {
413 pinctrl_hog: hoggrp { 413 pinctrl_hog: hoggrp {
414 fsl,pins = < 414 fsl,pins = <
415 MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 415 MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
416 MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059 416 MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059
417 MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059 417 MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059
418 MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 418 MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
419 MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */ 419 MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */
420 MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */ 420 MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */
421 MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 421 MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059
422 MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */ 422 MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */
423 >; 423 >;
424 }; 424 };
425 425
426 pinctrl_hog_sd2_reset: hoggrp-1 { 426 pinctrl_hog_sd2_reset: hoggrp-1 {
427 fsl,pins = < 427 fsl,pins = <
428 MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059 428 MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059
429 >; 429 >;
430 }; 430 };
431 431
432 pinctrl_audmux3: audmux3grp { 432 pinctrl_audmux3: audmux3grp {
433 fsl,pins = < 433 fsl,pins = <
434 MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 434 MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
435 MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 435 MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
436 MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 436 MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
437 MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 437 MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
438 MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 438 MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
439 >; 439 >;
440 }; 440 };
441 441
442 pinctrl_csi1: csi1grp { 442 pinctrl_csi1: csi1grp {
443 fsl,pins = < 443 fsl,pins = <
444 MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x1b088 444 MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x1b088
445 MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x1b088 445 MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x1b088
446 MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x1b088 446 MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x1b088
447 MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x1b088 447 MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x1b088
448 MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x1b088 448 MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x1b088
449 MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x1b088 449 MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x1b088
450 MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x1b088 450 MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x1b088
451 MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x1b088 451 MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x1b088
452 MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x1b088 452 MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x1b088
453 MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x1b088 453 MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x1b088
454 MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x1b088 454 MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x1b088
455 MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x1b088 455 MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x1b088
456 MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000 456 MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000
457 MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000 457 MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000
458 >; 458 >;
459 }; 459 };
460 460
461 pinctrl_led: ledgrp { 461 pinctrl_led: ledgrp {
462 fsl,pins = < 462 fsl,pins = <
463 MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x17059 463 MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x17059
464 >; 464 >;
465 }; 465 };
466 466
467 pinctrl_epdc0: epdcgrp0 { 467 pinctrl_epdc0: epdcgrp0 {
468 fsl,pins = < 468 fsl,pins = <
469 MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x100b1 469 MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x100b1
470 MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x100b1 470 MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x100b1
471 MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x100b1 471 MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x100b1
472 MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x100b1 472 MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x100b1
473 MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x100b1 473 MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x100b1
474 MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x100b1 474 MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x100b1
475 MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x100b1 475 MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x100b1
476 MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x100b1 476 MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x100b1
477 MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x100b1 477 MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x100b1
478 MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x100b1 478 MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x100b1
479 MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x100b1 479 MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x100b1
480 MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x100b1 480 MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x100b1
481 MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x100b1 481 MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x100b1
482 MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x100b1 482 MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x100b1
483 MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x100b1 483 MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x100b1
484 MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x100b1 484 MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x100b1
485 MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x100b1 485 MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x100b1
486 MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x100b1 486 MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x100b1
487 MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x100b1 487 MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x100b1
488 MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x100b1 488 MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x100b1
489 MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100b1 489 MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100b1
490 MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x100b1 490 MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x100b1
491 MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x100b1 491 MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x100b1
492 MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x100b1 492 MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x100b1
493 MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x100b1 493 MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x100b1
494 >; 494 >;
495 }; 495 };
496 496
497 pinctrl_lcdif_dat: lcdifdatgrp { 497 pinctrl_lcdif_dat: lcdifdatgrp {
498 fsl,pins = < 498 fsl,pins = <
499 MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79 499 MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79
500 MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79 500 MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79
501 MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79 501 MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79
502 MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79 502 MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79
503 MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79 503 MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79
504 MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79 504 MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79
505 MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79 505 MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79
506 MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79 506 MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79
507 MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79 507 MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79
508 MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79 508 MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79
509 MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79 509 MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79
510 MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79 510 MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79
511 MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79 511 MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79
512 MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79 512 MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79
513 MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79 513 MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79
514 MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79 514 MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79
515 MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79 515 MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79
516 MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79 516 MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79
517 MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79 517 MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79
518 MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79 518 MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79
519 MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79 519 MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79
520 MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79 520 MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79
521 MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79 521 MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79
522 MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79 522 MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79
523 >; 523 >;
524 }; 524 };
525 525
526 pinctrl_lcdif_ctrl: lcdifctrlgrp { 526 pinctrl_lcdif_ctrl: lcdifctrlgrp {
527 fsl,pins = < 527 fsl,pins = <
528 MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79 528 MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79
529 MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79 529 MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79
530 MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79 530 MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79
531 MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79 531 MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79
532 MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79 532 MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79
533 MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x79 533 MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x79
534 >; 534 >;
535 }; 535 };
536 536
537 pinctrl_max17135: max17135grp-1 { 537 pinctrl_max17135: max17135grp-1 {
538 fsl,pins = < 538 fsl,pins = <
539 MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x80000000 /* pwrgood */ 539 MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x80000000 /* pwrgood */
540 MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000 /* vcom_ctrl */ 540 MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000 /* vcom_ctrl */
541 MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x80000000 /* wakeup */ 541 MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x80000000 /* wakeup */
542 MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x80000000 /* v3p3 */ 542 MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x80000000 /* v3p3 */
543 MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x80000000 /* pwr int */ 543 MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x80000000 /* pwr int */
544 >; 544 >;
545 }; 545 };
546 546
547 pinctrl_spdif: spdifgrp { 547 pinctrl_spdif: spdifgrp {
548 fsl,pins = < 548 fsl,pins = <
549 MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x4130b0 549 MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x4130b0
550 >; 550 >;
551 }; 551 };
552 552
553 pinctrl_uart1: uart1grp { 553 pinctrl_uart1: uart1grp {
554 fsl,pins = < 554 fsl,pins = <
555 MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 555 MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
556 MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 556 MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
557 >; 557 >;
558 }; 558 };
559 559
560 pinctrl_usdhc1: usdhc1grp { 560 pinctrl_usdhc1: usdhc1grp {
561 fsl,pins = < 561 fsl,pins = <
562 MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 562 MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059
563 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x17059 563 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x17059
564 MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059 564 MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059
565 MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059 565 MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059
566 MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059 566 MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059
567 MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 567 MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059
568 >; 568 >;
569 }; 569 };
570 570
571 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { 571 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
572 fsl,pins = < 572 fsl,pins = <
573 MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 573 MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9
574 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170b9 574 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170b9
575 MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 575 MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9
576 MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 576 MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9
577 MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 577 MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9
578 MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 578 MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9
579 >; 579 >;
580 }; 580 };
581 581
582 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { 582 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
583 fsl,pins = < 583 fsl,pins = <
584 MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 584 MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9
585 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170f9 585 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170f9
586 MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 586 MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9
587 MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 587 MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9
588 MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 588 MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9
589 MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 589 MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9
590 >; 590 >;
591 }; 591 };
592 592
593 pinctrl_usdhc2: usdhc2grp { 593 pinctrl_usdhc2: usdhc2grp {
594 fsl,pins = < 594 fsl,pins = <
595 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 595 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059
596 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 596 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059
597 MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 597 MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059
598 MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 598 MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059
599 MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 599 MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059
600 MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 600 MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059
601 MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059 601 MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059
602 MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059 602 MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059
603 MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059 603 MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059
604 MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059 604 MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059
605 MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x413059 605 MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x413059
606 >; 606 >;
607 }; 607 };
608 608
609 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { 609 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
610 fsl,pins = < 610 fsl,pins = <
611 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 611 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9
612 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 612 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9
613 MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 613 MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9
614 MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 614 MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9
615 MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 615 MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9
616 MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 616 MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9
617 MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9 617 MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9
618 MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9 618 MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9
619 MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9 619 MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9
620 MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9 620 MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9
621 MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130b9 621 MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130b9
622 >; 622 >;
623 }; 623 };
624 624
625 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { 625 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
626 fsl,pins = < 626 fsl,pins = <
627 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 627 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9
628 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 628 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9
629 MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 629 MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9
630 MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 630 MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9
631 MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 631 MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9
632 MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 632 MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9
633 MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9 633 MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9
634 MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9 634 MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9
635 MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9 635 MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9
636 MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9 636 MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9
637 MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130f9 637 MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130f9
638 >; 638 >;
639 }; 639 };
640 pinctrl_usdhc3: usdhc3grp { 640 pinctrl_usdhc3: usdhc3grp {
641 fsl,pins = < 641 fsl,pins = <
642 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17059 642 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17059
643 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x17059 643 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x17059
644 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17059 644 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17059
645 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17059 645 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17059
646 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17059 646 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17059
647 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17059 647 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17059
648 >; 648 >;
649 }; 649 };
650 650
651 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { 651 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
652 fsl,pins = < 652 fsl,pins = <
653 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 653 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9
654 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9 654 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9
655 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 655 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9
656 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 656 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9
657 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 657 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9
658 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 658 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9
659 >; 659 >;
660 }; 660 };
661 661
662 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { 662 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
663 fsl,pins = < 663 fsl,pins = <
664 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 664 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9
665 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9 665 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9
666 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9 666 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9
667 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9 667 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9
668 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9 668 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9
669 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9 669 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9
670 >; 670 >;
671 }; 671 };
672 672
673 pinctrl_usbotg1: usbotg1grp { 673 pinctrl_usbotg1: usbotg1grp {
674 fsl,pins = < 674 fsl,pins = <
675 MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 675 MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
676 >; 676 >;
677 }; 677 };
678 678
679 pinctrl_i2c1: i2c1grp { 679 pinctrl_i2c1: i2c1grp {
680 fsl,pins = < 680 fsl,pins = <
681 MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 681 MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
682 MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 682 MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
683 >; 683 >;
684 }; 684 };
685 685
686 pinctrl_i2c1_gpio: i2c1grp_gpio { 686 pinctrl_i2c1_gpio: i2c1grp_gpio {
687 fsl,pins = < 687 fsl,pins = <
688 MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x1b8b1 688 MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x1b8b1
689 MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x1b8b1 689 MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x1b8b1
690 >; 690 >;
691 }; 691 };
692 692
693 pinctrl_i2c3: i2c3grp { 693 pinctrl_i2c3: i2c3grp {
694 fsl,pins = < 694 fsl,pins = <
695 MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x4041b8b1 695 MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x4041b8b1
696 MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x4041b8b1 696 MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x4041b8b1
697 >; 697 >;
698 }; 698 };
699 699
700 pinctrl_i2c3_gpio: i2c3grp_gpio { 700 pinctrl_i2c3_gpio: i2c3grp_gpio {
701 fsl,pins = < 701 fsl,pins = <
702 MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0x41b8b1 702 MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0x41b8b1
703 MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0x41b8b1 703 MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0x41b8b1
704 >; 704 >;
705 }; 705 };
706 706
707 pinctrl_pwm1: pmw1grp { 707 pinctrl_pwm1: pmw1grp {
708 fsl,pins = < 708 fsl,pins = <
709 MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 709 MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0
710 >; 710 >;
711 }; 711 };
712 712
713 pinctrl_ecspi1: ecspi1grp { 713 pinctrl_ecspi1: ecspi1grp {
714 fsl,pins = < 714 fsl,pins = <
715 MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 715 MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
716 MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 716 MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
717 MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 717 MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
718 MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x100b1 718 MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x100b1
719 >; 719 >;
720 }; 720 };
721 }; 721 };
722 }; 722 };
723 723
724 &lcdif { 724 &lcdif {
725 pinctrl-names = "default"; 725 pinctrl-names = "default";
726 pinctrl-0 = <&pinctrl_lcdif_dat 726 pinctrl-0 = <&pinctrl_lcdif_dat
727 &pinctrl_lcdif_ctrl>; 727 &pinctrl_lcdif_ctrl>;
728 lcd-supply = <&reg_lcd>; 728 lcd-supply = <&reg_lcd>;
729 display = <&display0>; 729 display = <&display0>;
730 status = "okay"; 730 status = "okay";
731 731
732 display0: display@0 { 732 display0: display@0 {
733 bits-per-pixel = <16>; 733 bits-per-pixel = <16>;
734 bus-width = <24>; 734 bus-width = <24>;
735 735
736 display-timings { 736 display-timings {
737 native-mode = <&timing0>; 737 native-mode = <&timing0>;
738 timing0: timing0 { 738 timing0: timing0 {
739 clock-frequency = <33500000>; 739 clock-frequency = <33500000>;
740 hactive = <800>; 740 hactive = <800>;
741 vactive = <480>; 741 vactive = <480>;
742 hback-porch = <89>; 742 hback-porch = <89>;
743 hfront-porch = <164>; 743 hfront-porch = <164>;
744 vback-porch = <23>; 744 vback-porch = <23>;
745 vfront-porch = <10>; 745 vfront-porch = <10>;
746 hsync-len = <10>; 746 hsync-len = <10>;
747 vsync-len = <10>; 747 vsync-len = <10>;
748 hsync-active = <0>; 748 hsync-active = <0>;
749 vsync-active = <0>; 749 vsync-active = <0>;
750 de-active = <1>; 750 de-active = <1>;
751 pixelclk-active = <0>; 751 pixelclk-active = <0>;
752 }; 752 };
753 }; 753 };
754 }; 754 };
755 }; 755 };
756 756
757 &pxp { 757 &pxp {
758 status = "okay"; 758 status = "okay";
759 }; 759 };
760 760
761 &pwm1 { 761 &pwm1 {
762 pinctrl-names = "default"; 762 pinctrl-names = "default";
763 pinctrl-0 = <&pinctrl_pwm1>; 763 pinctrl-0 = <&pinctrl_pwm1>;
764 status = "okay"; 764 status = "okay";
765 }; 765 };
766 766
767 &uart1 { 767 &uart1 {
768 pinctrl-names = "default"; 768 pinctrl-names = "default";
769 pinctrl-0 = <&pinctrl_uart1>; 769 pinctrl-0 = <&pinctrl_uart1>;
770 status = "okay"; 770 status = "okay";
771 }; 771 };
772 772
773 &usdhc1 { 773 &usdhc1 {
774 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 774 pinctrl-names = "default", "state_100mhz", "state_200mhz";
775 pinctrl-0 = <&pinctrl_usdhc1>; 775 pinctrl-0 = <&pinctrl_usdhc1>;
776 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 776 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
777 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 777 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
778 cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; 778 cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
779 wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; 779 wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
780 keep-power-in-suspend; 780 keep-power-in-suspend;
781 enable-sdio-wakeup; 781 enable-sdio-wakeup;
782 vmmc-supply = <&reg_sd1_vmmc>; 782 vmmc-supply = <&reg_sd1_vmmc>;
783 status = "okay"; 783 status = "okay";
784 }; 784 };
785 785
786 &usdhc2 { 786 &usdhc2 {
787 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 787 pinctrl-names = "default", "state_100mhz", "state_200mhz";
788 pinctrl-0 = <&pinctrl_usdhc2>; 788 pinctrl-0 = <&pinctrl_usdhc2>;
789 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 789 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
790 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 790 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
791 vqmmc-supply = <&reg_sd2_vmmc>; 791 vqmmc-supply = <&reg_sd2_vmmc>;
792 bus-width = <8>; 792 bus-width = <8>;
793 no-removable; 793 no-removable;
794 status = "okay"; 794 status = "okay";
795 }; 795 };
796 796
797 &usdhc3 { 797 &usdhc3 {
798 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 798 pinctrl-names = "default", "state_100mhz", "state_200mhz";
799 pinctrl-0 = <&pinctrl_usdhc3>; 799 pinctrl-0 = <&pinctrl_usdhc3>;
800 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 800 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
801 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 801 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
802 cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; 802 cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
803 keep-power-in-suspend; 803 keep-power-in-suspend;
804 enable-sdio-wakeup; 804 enable-sdio-wakeup;
805 vmmc-supply = <&reg_sd3_vmmc>; 805 vmmc-supply = <&reg_sd3_vmmc>;
806 status = "okay"; 806 status = "okay";
807 }; 807 };
808 808
809 &usbotg1 { 809 &usbotg1 {
810 vbus-supply = <&reg_usb_otg1_vbus>; 810 vbus-supply = <&reg_usb_otg1_vbus>;
811 pinctrl-names = "default"; 811 pinctrl-names = "default";
812 pinctrl-0 = <&pinctrl_usbotg1>; 812 pinctrl-0 = <&pinctrl_usbotg1>;
813 disable-over-current; 813 disable-over-current;
814 srp-disable; 814 srp-disable;
815 hnp-disable; 815 hnp-disable;
816 adp-disable; 816 adp-disable;
817 status = "okay"; 817 status = "okay";
818 }; 818 };
819 819
820 &usbotg2 { 820 &usbotg2 {
821 vbus-supply = <&reg_usb_otg2_vbus>; 821 vbus-supply = <&reg_usb_otg2_vbus>;
822 dr_mode = "host"; 822 dr_mode = "host";
823 disable-over-current; 823 disable-over-current;
824 status = "okay"; 824 status = "okay";
825 }; 825 };
826 826
827 &ecspi1 { 827 &ecspi1 {
828 fsl,spi-num-chipselects = <1>; 828 fsl,spi-num-chipselects = <1>;
829 cs-gpios = <&gpio4 11 0>; 829 cs-gpios = <&gpio4 11 0>;
830 pinctrl-names = "default"; 830 pinctrl-names = "default";
831 pinctrl-0 = <&pinctrl_ecspi1>; 831 pinctrl-0 = <&pinctrl_ecspi1>;
832 status = "disabled"; 832 status = "disabled";
833 833
834 #address-cells = <1>; 834 #address-cells = <1>;
835 #size-cells = <0>; 835 #size-cells = <0>;
836 836
837 flash: m25p80@0 { 837 flash: m25p80@0 {
838 compatible = "st,m25p32", "jedec,spi-nor"; 838 compatible = "st,m25p32", "jedec,spi-nor";
839 spi-max-frequency = <20000000>; 839 spi-max-frequency = <20000000>;
840 reg = <0>; 840 reg = <0>;
841 }; 841 };
842 }; 842 };
843 843
844 &epdc { 844 &epdc {
845 pinctrl-names = "default"; 845 pinctrl-names = "default";
846 pinctrl-0 = <&pinctrl_epdc0>; 846 pinctrl-0 = <&pinctrl_epdc0>;
847 V3P3-supply = <&V3P3_reg>; 847 V3P3-supply = <&V3P3_reg>;
848 VCOM-supply = <&VCOM_reg>; 848 VCOM-supply = <&VCOM_reg>;
849 DISPLAY-supply = <&DISPLAY_reg>; 849 DISPLAY-supply = <&DISPLAY_reg>;
850 status = "okay"; 850 status = "okay";
851 }; 851 };
852 852
853 &ssi2 { 853 &ssi2 {
854 status = "okay"; 854 status = "okay";
855 }; 855 };
856 856
arch/arm/dts/imx6sx-14x14-arm2.dts
Diff comments   View file @ 4daafb3
1 /* 1 /*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include "imx6sx.dtsi" 11 #include "imx6sx.dtsi"
12 12
13 / { 13 / {
14 model = "Freescale i.MX6 SoloX 14x14 ARM2 Board"; 14 model = "Freescale i.MX6 SoloX 14x14 ARM2 Board";
15 compatible = "fsl,imx6sx-14x14-lpddr2-arm2", "fsl,imx6sx"; 15 compatible = "fsl,imx6sx-14x14-lpddr2-arm2", "fsl,imx6sx";
16 16
17 backlight { 17 backlight {
18 compatible = "pwm-backlight"; 18 compatible = "pwm-backlight";
19 pwms = <&pwm3 0 5000000>; 19 pwms = <&pwm3 0 5000000>;
20 brightness-levels = <0 4 8 16 32 64 128 255>; 20 brightness-levels = <0 4 8 16 32 64 128 255>;
21 default-brightness-level = <6>; 21 default-brightness-level = <6>;
22 }; 22 };
23 23
24 clocks { 24 clocks {
25 codec_osc: codec_osc { 25 codec_osc: codec_osc {
26 #clock-cells = <0>; 26 #clock-cells = <0>;
27 compatible = "fixed-clock"; 27 compatible = "fixed-clock";
28 clock-frequency = <12000000>; 28 clock-frequency = <12000000>;
29 }; 29 };
30 }; 30 };
31 31
32 max7322_reset: max7322-reset { 32 max7322_reset: max7322-reset {
33 compatible = "gpio-reset"; 33 compatible = "gpio-reset";
34 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 34 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
35 reset-delay-us = <1>; 35 reset-delay-us = <1>;
36 #reset-cells = <0>; 36 #reset-cells = <0>;
37 }; 37 };
38 38
39 pxp_v4l2_out { 39 pxp_v4l2_out {
40 compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; 40 compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
41 status = "okay"; 41 status = "okay";
42 }; 42 };
43 43
44 regulators { 44 regulators {
45 compatible = "simple-bus"; 45 compatible = "simple-bus";
46 46
47 reg_3p3v: 3p3v { 47 reg_3p3v: 3p3v {
48 compatible = "regulator-fixed"; 48 compatible = "regulator-fixed";
49 regulator-name = "3P3V"; 49 regulator-name = "3P3V";
50 regulator-min-microvolt = <3300000>; 50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <3300000>; 51 regulator-max-microvolt = <3300000>;
52 regulator-always-on; 52 regulator-always-on;
53 }; 53 };
54 54
55 reg_sdb_vmmc: sdb_vmmc{ 55 reg_sdb_vmmc: sdb_vmmc{
56 compatible = "regulator-fixed"; 56 compatible = "regulator-fixed";
57 regulator-name = "SD2_SPWR"; 57 regulator-name = "SD2_SPWR";
58 regulator-min-microvolt = <3300000>; 58 regulator-min-microvolt = <3300000>;
59 regulator-max-microvolt = <3300000>; 59 regulator-max-microvolt = <3300000>;
60 gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; 60 gpio = <&gpio2 11 GPIO_ACTIVE_LOW>;
61 off-on-delay = <20000>; 61 u-boot,off-on-delay-us = <20000>;
62 }; 62 };
63 63
64 reg_usb_otg1_vbus: usb_otg1_vbus { 64 reg_usb_otg1_vbus: usb_otg1_vbus {
65 compatible = "regulator-fixed"; 65 compatible = "regulator-fixed";
66 regulator-name = "usb_otg1_vbus"; 66 regulator-name = "usb_otg1_vbus";
67 regulator-min-microvolt = <5000000>; 67 regulator-min-microvolt = <5000000>;
68 regulator-max-microvolt = <5000000>; 68 regulator-max-microvolt = <5000000>;
69 gpio = <&gpio1 9 0>; 69 gpio = <&gpio1 9 0>;
70 enable-active-high; 70 enable-active-high;
71 }; 71 };
72 72
73 reg_usb_otg2_vbus: usb_otg2_vbus { 73 reg_usb_otg2_vbus: usb_otg2_vbus {
74 compatible = "regulator-fixed"; 74 compatible = "regulator-fixed";
75 regulator-name = "usb_otg2_vbus"; 75 regulator-name = "usb_otg2_vbus";
76 regulator-min-microvolt = <5000000>; 76 regulator-min-microvolt = <5000000>;
77 regulator-max-microvolt = <5000000>; 77 regulator-max-microvolt = <5000000>;
78 gpio = <&gpio1 12 0>; 78 gpio = <&gpio1 12 0>;
79 enable-active-high; 79 enable-active-high;
80 }; 80 };
81 81
82 reg_vref_3v3: regulator@0 { 82 reg_vref_3v3: regulator@0 {
83 compatible = "regulator-fixed"; 83 compatible = "regulator-fixed";
84 regulator-name = "vref-3v3"; 84 regulator-name = "vref-3v3";
85 regulator-min-microvolt = <3300000>; 85 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <3300000>; 86 regulator-max-microvolt = <3300000>;
87 }; 87 };
88 }; 88 };
89 89
90 memory { 90 memory {
91 reg = <0x80000000 0x40000000>; 91 reg = <0x80000000 0x40000000>;
92 }; 92 };
93 93
94 sound { 94 sound {
95 compatible = "fsl,imx6sx-arm2-sgtl5000", 95 compatible = "fsl,imx6sx-arm2-sgtl5000",
96 "fsl,imx-audio-sgtl5000"; 96 "fsl,imx-audio-sgtl5000";
97 model = "imx6sx-arm2-sgtl5000"; 97 model = "imx6sx-arm2-sgtl5000";
98 cpu-dai = <&ssi1>; 98 cpu-dai = <&ssi1>;
99 audio-codec = <&codec>; 99 audio-codec = <&codec>;
100 audio-routing = 100 audio-routing =
101 "LINE_IN", "Line In Jack", 101 "LINE_IN", "Line In Jack",
102 "Headphone Jack", "HP_OUT"; 102 "Headphone Jack", "HP_OUT";
103 mux-int-port = <1>; 103 mux-int-port = <1>;
104 mux-ext-port = <4>; 104 mux-ext-port = <4>;
105 }; 105 };
106 }; 106 };
107 107
108 &adc1 { 108 &adc1 {
109 vref-supply = <&reg_vref_3v3>; 109 vref-supply = <&reg_vref_3v3>;
110 status = "okay"; 110 status = "okay";
111 }; 111 };
112 112
113 &adc2 { 113 &adc2 {
114 vref-supply = <&reg_vref_3v3>; 114 vref-supply = <&reg_vref_3v3>;
115 status = "okay"; 115 status = "okay";
116 }; 116 };
117 117
118 &audmux { 118 &audmux {
119 pinctrl-names = "default"; 119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_audmux_2>; 120 pinctrl-0 = <&pinctrl_audmux_2>;
121 status = "okay"; 121 status = "okay";
122 }; 122 };
123 123
124 &cpu0 { 124 &cpu0 {
125 operating-points = < 125 operating-points = <
126 /* kHz uV */ 126 /* kHz uV */
127 996000 1250000 127 996000 1250000
128 792000 1175000 128 792000 1175000
129 396000 1175000 129 396000 1175000
130 >; 130 >;
131 fsl,soc-operating-points = < 131 fsl,soc-operating-points = <
132 /* ARM kHz SOC uV */ 132 /* ARM kHz SOC uV */
133 996000 1250000 133 996000 1250000
134 792000 1175000 134 792000 1175000
135 396000 1175000 135 396000 1175000
136 >; 136 >;
137 fsl,arm-soc-shared = <1>; 137 fsl,arm-soc-shared = <1>;
138 }; 138 };
139 139
140 &reg_arm { 140 &reg_arm {
141 vin-supply = <&sw1a_reg>; 141 vin-supply = <&sw1a_reg>;
142 regulator-allow-bypass; 142 regulator-allow-bypass;
143 }; 143 };
144 144
145 &reg_soc { 145 &reg_soc {
146 vin-supply = <&sw1a_reg>; 146 vin-supply = <&sw1a_reg>;
147 regulator-allow-bypass; 147 regulator-allow-bypass;
148 }; 148 };
149 149
150 &ecspi4 { 150 &ecspi4 {
151 fsl,spi-num-chipselects = <1>; 151 fsl,spi-num-chipselects = <1>;
152 cs-gpios = <&gpio7 4 0>; 152 cs-gpios = <&gpio7 4 0>;
153 pinctrl-names = "default"; 153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>; 154 pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>;
155 status = "disabled"; /* pin conflict with USDHC3 */ 155 status = "disabled"; /* pin conflict with USDHC3 */
156 156
157 flash: m25p80@0 { 157 flash: m25p80@0 {
158 #address-cells = <1>; 158 #address-cells = <1>;
159 #size-cells = <1>; 159 #size-cells = <1>;
160 compatible = "st,m25p32"; 160 compatible = "st,m25p32";
161 spi-max-frequency = <20000000>; 161 spi-max-frequency = <20000000>;
162 reg = <0>; 162 reg = <0>;
163 }; 163 };
164 }; 164 };
165 165
166 &fec1 { 166 &fec1 {
167 pinctrl-names = "default"; 167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_enet1_1>; 168 pinctrl-0 = <&pinctrl_enet1_1>;
169 phy-mode = "rgmii"; 169 phy-mode = "rgmii";
170 phy-id = <1>; 170 phy-id = <1>;
171 fsl,num_tx_queues=<3>; 171 fsl,num_tx_queues=<3>;
172 fsl,num_rx_queues=<3>; 172 fsl,num_rx_queues=<3>;
173 pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>; 173 pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>;
174 fsl,magic-packet; 174 fsl,magic-packet;
175 status = "okay"; 175 status = "okay";
176 }; 176 };
177 177
178 &fec2 { 178 &fec2 {
179 pinctrl-names = "default"; 179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_enet2_1>; 180 pinctrl-0 = <&pinctrl_enet2_1>;
181 phy-mode = "rgmii"; 181 phy-mode = "rgmii";
182 phy-id = <0>; 182 phy-id = <0>;
183 fsl,num_tx_queues=<3>; 183 fsl,num_tx_queues=<3>;
184 fsl,num_rx_queues=<3>; 184 fsl,num_rx_queues=<3>;
185 pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>; 185 pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>;
186 fsl,magic-packet; 186 fsl,magic-packet;
187 status = "okay"; 187 status = "okay";
188 }; 188 };
189 189
190 &flexcan1 { 190 &flexcan1 {
191 pinctrl-names = "default"; 191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_flexcan1_1>; 192 pinctrl-0 = <&pinctrl_flexcan1_1>;
193 trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; 193 trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
194 trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 194 trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
195 trx-err-gpio = <&gpio4 24 GPIO_ACTIVE_HIGH>; 195 trx-err-gpio = <&gpio4 24 GPIO_ACTIVE_HIGH>;
196 status = "okay"; 196 status = "okay";
197 }; 197 };
198 198
199 &flexcan2 { 199 &flexcan2 {
200 pinctrl-names = "default"; 200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_flexcan2_1>; 201 pinctrl-0 = <&pinctrl_flexcan2_1>;
202 trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; 202 trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
203 trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 203 trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
204 trx-err-gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; 204 trx-err-gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
205 status = "okay"; 205 status = "okay";
206 }; 206 };
207 207
208 &gpc { 208 &gpc {
209 fsl,cpu_pdnscr_iso2sw = <0x1>; 209 fsl,cpu_pdnscr_iso2sw = <0x1>;
210 fsl,cpu_pdnscr_iso = <0x1>; 210 fsl,cpu_pdnscr_iso = <0x1>;
211 fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ 211 fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
212 }; 212 };
213 213
214 &gpmi { 214 &gpmi {
215 pinctrl-names = "default"; 215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_gpmi_nand_1>; 216 pinctrl-0 = <&pinctrl_gpmi_nand_1>;
217 status = "disabled"; /* pin conflict with qspi*/ 217 status = "disabled"; /* pin conflict with qspi*/
218 nand-on-flash-bbt; 218 nand-on-flash-bbt;
219 }; 219 };
220 220
221 &i2c1 { 221 &i2c1 {
222 clock-frequency = <100000>; 222 clock-frequency = <100000>;
223 pinctrl-names = "default", "gpio"; 223 pinctrl-names = "default", "gpio";
224 pinctrl-0 = <&pinctrl_i2c1_1>; 224 pinctrl-0 = <&pinctrl_i2c1_1>;
225 pinctrl-1 = <&pinctrl_i2c1_1_gpio>; 225 pinctrl-1 = <&pinctrl_i2c1_1_gpio>;
226 scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; 226 scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
227 sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 227 sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
228 status = "okay"; 228 status = "okay";
229 229
230 pmic: pfuze100@08 { 230 pmic: pfuze100@08 {
231 compatible = "fsl,pfuze200"; 231 compatible = "fsl,pfuze200";
232 reg = <0x08>; 232 reg = <0x08>;
233 233
234 regulators { 234 regulators {
235 sw1a_reg: sw1ab { 235 sw1a_reg: sw1ab {
236 regulator-min-microvolt = <300000>; 236 regulator-min-microvolt = <300000>;
237 regulator-max-microvolt = <1875000>; 237 regulator-max-microvolt = <1875000>;
238 regulator-boot-on; 238 regulator-boot-on;
239 regulator-always-on; 239 regulator-always-on;
240 regulator-ramp-delay = <6250>; 240 regulator-ramp-delay = <6250>;
241 }; 241 };
242 242
243 sw2_reg: sw2 { 243 sw2_reg: sw2 {
244 regulator-min-microvolt = <800000>; 244 regulator-min-microvolt = <800000>;
245 regulator-max-microvolt = <3300000>; 245 regulator-max-microvolt = <3300000>;
246 regulator-boot-on; 246 regulator-boot-on;
247 regulator-always-on; 247 regulator-always-on;
248 }; 248 };
249 249
250 sw3a_reg: sw3a { 250 sw3a_reg: sw3a {
251 regulator-min-microvolt = <400000>; 251 regulator-min-microvolt = <400000>;
252 regulator-max-microvolt = <1975000>; 252 regulator-max-microvolt = <1975000>;
253 regulator-boot-on; 253 regulator-boot-on;
254 regulator-always-on; 254 regulator-always-on;
255 }; 255 };
256 256
257 sw3b_reg: sw3b { 257 sw3b_reg: sw3b {
258 regulator-min-microvolt = <400000>; 258 regulator-min-microvolt = <400000>;
259 regulator-max-microvolt = <1975000>; 259 regulator-max-microvolt = <1975000>;
260 regulator-boot-on; 260 regulator-boot-on;
261 regulator-always-on; 261 regulator-always-on;
262 }; 262 };
263 263
264 swbst_reg: swbst { 264 swbst_reg: swbst {
265 regulator-min-microvolt = <5000000>; 265 regulator-min-microvolt = <5000000>;
266 regulator-max-microvolt = <5150000>; 266 regulator-max-microvolt = <5150000>;
267 }; 267 };
268 268
269 snvs_reg: vsnvs { 269 snvs_reg: vsnvs {
270 regulator-min-microvolt = <1000000>; 270 regulator-min-microvolt = <1000000>;
271 regulator-max-microvolt = <3000000>; 271 regulator-max-microvolt = <3000000>;
272 regulator-boot-on; 272 regulator-boot-on;
273 regulator-always-on; 273 regulator-always-on;
274 }; 274 };
275 275
276 vref_reg: vrefddr { 276 vref_reg: vrefddr {
277 regulator-boot-on; 277 regulator-boot-on;
278 regulator-always-on; 278 regulator-always-on;
279 }; 279 };
280 280
281 vgen1_reg: vgen1 { 281 vgen1_reg: vgen1 {
282 regulator-min-microvolt = <800000>; 282 regulator-min-microvolt = <800000>;
283 regulator-max-microvolt = <1550000>; 283 regulator-max-microvolt = <1550000>;
284 }; 284 };
285 285
286 vgen2_reg: vgen2 { 286 vgen2_reg: vgen2 {
287 regulator-min-microvolt = <800000>; 287 regulator-min-microvolt = <800000>;
288 regulator-max-microvolt = <1550000>; 288 regulator-max-microvolt = <1550000>;
289 }; 289 };
290 290
291 vgen3_reg: vgen3 { 291 vgen3_reg: vgen3 {
292 regulator-min-microvolt = <1800000>; 292 regulator-min-microvolt = <1800000>;
293 regulator-max-microvolt = <3300000>; 293 regulator-max-microvolt = <3300000>;
294 regulator-always-on; 294 regulator-always-on;
295 }; 295 };
296 296
297 vgen4_reg: vgen4 { 297 vgen4_reg: vgen4 {
298 regulator-min-microvolt = <1800000>; 298 regulator-min-microvolt = <1800000>;
299 regulator-max-microvolt = <3300000>; 299 regulator-max-microvolt = <3300000>;
300 regulator-always-on; 300 regulator-always-on;
301 }; 301 };
302 302
303 vgen5_reg: vgen5 { 303 vgen5_reg: vgen5 {
304 regulator-min-microvolt = <1800000>; 304 regulator-min-microvolt = <1800000>;
305 regulator-max-microvolt = <3300000>; 305 regulator-max-microvolt = <3300000>;
306 regulator-always-on; 306 regulator-always-on;
307 }; 307 };
308 308
309 vgen6_reg: vgen6 { 309 vgen6_reg: vgen6 {
310 regulator-min-microvolt = <1800000>; 310 regulator-min-microvolt = <1800000>;
311 regulator-max-microvolt = <3300000>; 311 regulator-max-microvolt = <3300000>;
312 regulator-always-on; 312 regulator-always-on;
313 }; 313 };
314 }; 314 };
315 }; 315 };
316 }; 316 };
317 317
318 &i2c2 { 318 &i2c2 {
319 clock-frequency = <100000>; 319 clock-frequency = <100000>;
320 pinctrl-names = "default", "gpio"; 320 pinctrl-names = "default", "gpio";
321 pinctrl-0 = <&pinctrl_i2c2_1>; 321 pinctrl-0 = <&pinctrl_i2c2_1>;
322 pinctrl-1 = <&pinctrl_i2c2_1_gpio>; 322 pinctrl-1 = <&pinctrl_i2c2_1_gpio>;
323 scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 323 scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
324 sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 324 sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
325 status = "okay"; 325 status = "okay";
326 326
327 max7322_1: gpio@68 { 327 max7322_1: gpio@68 {
328 compatible = "maxim,max7322"; 328 compatible = "maxim,max7322";
329 reg = <0x68>; 329 reg = <0x68>;
330 gpio-controller; 330 gpio-controller;
331 #gpio-cells = <2>; 331 #gpio-cells = <2>;
332 resets = <&max7322_reset>; 332 resets = <&max7322_reset>;
333 }; 333 };
334 334
335 max7322_2: gpio@69 { 335 max7322_2: gpio@69 {
336 compatible = "maxim,max7322"; 336 compatible = "maxim,max7322";
337 reg = <0x69>; 337 reg = <0x69>;
338 gpio-controller; 338 gpio-controller;
339 #gpio-cells = <2>; 339 #gpio-cells = <2>;
340 resets = <&max7322_reset>; 340 resets = <&max7322_reset>;
341 }; 341 };
342 342
343 codec: sgtl5000@0a { 343 codec: sgtl5000@0a {
344 compatible = "fsl,sgtl5000"; 344 compatible = "fsl,sgtl5000";
345 reg = <0x0a>; 345 reg = <0x0a>;
346 clocks = <&codec_osc>; 346 clocks = <&codec_osc>;
347 VDDA-supply = <&vgen4_reg>; 347 VDDA-supply = <&vgen4_reg>;
348 VDDIO-supply = <&reg_3p3v>; 348 VDDIO-supply = <&reg_3p3v>;
349 }; 349 };
350 }; 350 };
351 351
352 352
353 &i2c3 { 353 &i2c3 {
354 clock-frequency = <100000>; 354 clock-frequency = <100000>;
355 pinctrl-names = "default", "gpio"; 355 pinctrl-names = "default", "gpio";
356 pinctrl-0 = <&pinctrl_i2c3_1>; 356 pinctrl-0 = <&pinctrl_i2c3_1>;
357 pinctrl-1 = <&pinctrl_i2c3_1_gpio>; 357 pinctrl-1 = <&pinctrl_i2c3_1_gpio>;
358 scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; 358 scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
359 sda-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; 359 sda-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
360 status = "okay"; 360 status = "okay";
361 }; 361 };
362 362
363 &i2c4 { 363 &i2c4 {
364 clock-frequency = <100000>; 364 clock-frequency = <100000>;
365 pinctrl-names = "default", "gpio"; 365 pinctrl-names = "default", "gpio";
366 pinctrl-0 = <&pinctrl_i2c4_1>; 366 pinctrl-0 = <&pinctrl_i2c4_1>;
367 pinctrl-1 = <&pinctrl_i2c4_1_gpio>; 367 pinctrl-1 = <&pinctrl_i2c4_1_gpio>;
368 scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; 368 scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
369 sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; 369 sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
370 status = "okay"; 370 status = "okay";
371 }; 371 };
372 372
373 &iomuxc { 373 &iomuxc {
374 pinctrl-names = "default"; 374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_hog_1>; 375 pinctrl-0 = <&pinctrl_hog_1>;
376 376
377 hog { 377 hog {
378 pinctrl_hog_1: hoggrp-1 { 378 pinctrl_hog_1: hoggrp-1 {
379 fsl,pins = < 379 fsl,pins = <
380 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x1f059 380 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x1f059
381 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x1f059 381 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x1f059
382 MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x80000000 382 MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x80000000
383 /* CAN1_2_EN */ 383 /* CAN1_2_EN */
384 MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059 384 MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059
385 /* CAN1_2_STBY_B */ 385 /* CAN1_2_STBY_B */
386 MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059 386 MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059
387 /* CAN1_ERR_B */ 387 /* CAN1_ERR_B */
388 MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x17059 388 MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x17059
389 /* CAN2_ERR_B */ 389 /* CAN2_ERR_B */
390 MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x17059 390 MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x17059
391 /* SD2_PWROFF */ 391 /* SD2_PWROFF */
392 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 392 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
393 >; 393 >;
394 }; 394 };
395 }; 395 };
396 }; 396 };
397 397
398 &lcdif1 { 398 &lcdif1 {
399 pinctrl-names = "default"; 399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_lcdif_dat_0 400 pinctrl-0 = <&pinctrl_lcdif_dat_0
401 &pinctrl_lcdif_ctrl_0>; 401 &pinctrl_lcdif_ctrl_0>;
402 display = <&display0>; 402 display = <&display0>;
403 status = "okay"; 403 status = "okay";
404 404
405 display0: display@0 { 405 display0: display@0 {
406 bits-per-pixel = <16>; 406 bits-per-pixel = <16>;
407 bus-width = <24>; 407 bus-width = <24>;
408 408
409 display-timings { 409 display-timings {
410 native-mode = <&timing0>; 410 native-mode = <&timing0>;
411 timing0: timing0 { 411 timing0: timing0 {
412 clock-frequency = <33500000>; 412 clock-frequency = <33500000>;
413 hactive = <800>; 413 hactive = <800>;
414 vactive = <480>; 414 vactive = <480>;
415 hback-porch = <89>; 415 hback-porch = <89>;
416 hfront-porch = <164>; 416 hfront-porch = <164>;
417 vback-porch = <23>; 417 vback-porch = <23>;
418 vfront-porch = <10>; 418 vfront-porch = <10>;
419 hsync-len = <10>; 419 hsync-len = <10>;
420 vsync-len = <10>; 420 vsync-len = <10>;
421 hsync-active = <0>; 421 hsync-active = <0>;
422 vsync-active = <0>; 422 vsync-active = <0>;
423 de-active = <1>; 423 de-active = <1>;
424 pixelclk-active = <0>; 424 pixelclk-active = <0>;
425 }; 425 };
426 }; 426 };
427 }; 427 };
428 }; 428 };
429 429
430 &mlb { 430 &mlb {
431 pinctrl-names = "default"; 431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_mlb_1>; 432 pinctrl-0 = <&pinctrl_mlb_1>;
433 status = "disabled";/* pin conflict with usdhc2*/ 433 status = "disabled";/* pin conflict with usdhc2*/
434 }; 434 };
435 435
436 &pwm3 { 436 &pwm3 {
437 pinctrl-names = "default"; 437 pinctrl-names = "default";
438 pinctrl-0 = <&pinctrl_pwm3_0>; 438 pinctrl-0 = <&pinctrl_pwm3_0>;
439 status = "okay"; 439 status = "okay";
440 }; 440 };
441 441
442 &pxp { 442 &pxp {
443 status = "okay"; 443 status = "okay";
444 }; 444 };
445 445
446 &qspi2 { 446 &qspi2 {
447 pinctrl-names = "default"; 447 pinctrl-names = "default";
448 pinctrl-0 = <&pinctrl_qspi2_1>; 448 pinctrl-0 = <&pinctrl_qspi2_1>;
449 status = "okay"; 449 status = "okay";
450 ddrsmp=<2>; 450 ddrsmp=<2>;
451 451
452 flash0: n25q256a@0 { 452 flash0: n25q256a@0 {
453 #address-cells = <1>; 453 #address-cells = <1>;
454 #size-cells = <1>; 454 #size-cells = <1>;
455 compatible = "micron,n25q256a", "jedec,spi-nor"; 455 compatible = "micron,n25q256a", "jedec,spi-nor";
456 spi-max-frequency = <29000000>; 456 spi-max-frequency = <29000000>;
457 reg = <0>; 457 reg = <0>;
458 }; 458 };
459 459
460 flash1: n25q256a@1 { 460 flash1: n25q256a@1 {
461 #address-cells = <1>; 461 #address-cells = <1>;
462 #size-cells = <1>; 462 #size-cells = <1>;
463 compatible = "micron,n25q256a", "jedec,spi-nor"; 463 compatible = "micron,n25q256a", "jedec,spi-nor";
464 spi-max-frequency = <29000000>; 464 spi-max-frequency = <29000000>;
465 reg = <1>; 465 reg = <1>;
466 }; 466 };
467 }; 467 };
468 468
469 &sai2 { 469 &sai2 {
470 pinctrl-names = "default"; 470 pinctrl-names = "default";
471 pinctrl-0 = <&pinctrl_sai2_1>; 471 pinctrl-0 = <&pinctrl_sai2_1>;
472 status = "disabled"; 472 status = "disabled";
473 }; 473 };
474 474
475 &spdif { 475 &spdif {
476 pinctrl-names = "default"; 476 pinctrl-names = "default";
477 pinctrl-0 = <&pinctrl_spdif_1>; 477 pinctrl-0 = <&pinctrl_spdif_1>;
478 status = "disabled"; 478 status = "disabled";
479 }; 479 };
480 480
481 &ssi1 { 481 &ssi1 {
482 fsl,mode = "i2s-slave"; 482 fsl,mode = "i2s-slave";
483 status = "okay"; 483 status = "okay";
484 }; 484 };
485 485
486 &snvs_poweroff { 486 &snvs_poweroff {
487 status = "okay"; 487 status = "okay";
488 }; 488 };
489 489
490 &uart1 { 490 &uart1 {
491 pinctrl-names = "default"; 491 pinctrl-names = "default";
492 pinctrl-0 = <&pinctrl_uart1_1>; 492 pinctrl-0 = <&pinctrl_uart1_1>;
493 status = "okay"; 493 status = "okay";
494 }; 494 };
495 495
496 &uart2 { 496 &uart2 {
497 pinctrl-names = "default"; 497 pinctrl-names = "default";
498 pinctrl-0 = <&pinctrl_uart2_1>; 498 pinctrl-0 = <&pinctrl_uart2_1>;
499 status = "okay"; 499 status = "okay";
500 }; 500 };
501 501
502 &usbh { 502 &usbh {
503 pinctrl-names = "idle", "active"; 503 pinctrl-names = "idle", "active";
504 pinctrl-0 = <&pinctrl_usbh_1>; 504 pinctrl-0 = <&pinctrl_usbh_1>;
505 pinctrl-1 = <&pinctrl_usbh_2>; 505 pinctrl-1 = <&pinctrl_usbh_2>;
506 osc-clkgate-delay = <0x3>; 506 osc-clkgate-delay = <0x3>;
507 pad-supply = <&vgen1_reg>; 507 pad-supply = <&vgen1_reg>;
508 status = "okay"; 508 status = "okay";
509 }; 509 };
510 510
511 &usbotg1 { 511 &usbotg1 {
512 vbus-supply = <&reg_usb_otg1_vbus>; 512 vbus-supply = <&reg_usb_otg1_vbus>;
513 pinctrl-names = "default"; 513 pinctrl-names = "default";
514 pinctrl-0 = <&pinctrl_usbotg1_1>; 514 pinctrl-0 = <&pinctrl_usbotg1_1>;
515 disable-over-current; 515 disable-over-current;
516 status = "okay"; 516 status = "okay";
517 }; 517 };
518 518
519 &usbotg2 { 519 &usbotg2 {
520 /* 520 /*
521 * Pin conflict with others, need to switch R580 & R579 521 * Pin conflict with others, need to switch R580 & R579
522 * to B and disable pwm3 to enable it. 522 * to B and disable pwm3 to enable it.
523 */ 523 */
524 vbus-supply = <&reg_usb_otg2_vbus>; 524 vbus-supply = <&reg_usb_otg2_vbus>;
525 disable-over-current; 525 disable-over-current;
526 pinctrl-names = "default"; 526 pinctrl-names = "default";
527 pinctrl-0 = <&pinctrl_usbotg2_1>; 527 pinctrl-0 = <&pinctrl_usbotg2_1>;
528 status = "disabled"; 528 status = "disabled";
529 }; 529 };
530 530
531 &usdhc2 { 531 &usdhc2 {
532 pinctrl-names = "default"; 532 pinctrl-names = "default";
533 pinctrl-0 = <&pinctrl_usdhc2_1>; 533 pinctrl-0 = <&pinctrl_usdhc2_1>;
534 non-removable; 534 non-removable;
535 /* need hw rework to enable signal voltage switch */ 535 /* need hw rework to enable signal voltage switch */
536 no-1-8-v; 536 no-1-8-v;
537 keep-power-in-suspend; 537 keep-power-in-suspend;
538 enable-sdio-wakeup; 538 enable-sdio-wakeup;
539 status = "okay"; 539 status = "okay";
540 }; 540 };
541 541
542 &usdhc3 { 542 &usdhc3 {
543 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 543 pinctrl-names = "default", "state_100mhz", "state_200mhz";
544 pinctrl-0 = <&pinctrl_usdhc3_1>; 544 pinctrl-0 = <&pinctrl_usdhc3_1>;
545 pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; 545 pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
546 pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; 546 pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
547 bus-width = <8>; 547 bus-width = <8>;
548 cd-gpios = <&gpio2 10 0>; 548 cd-gpios = <&gpio2 10 0>;
549 wp-gpios = <&gpio2 15 0>; 549 wp-gpios = <&gpio2 15 0>;
550 keep-power-in-suspend; 550 keep-power-in-suspend;
551 enable-sdio-wakeup; 551 enable-sdio-wakeup;
552 vmmc-supply = <&reg_sdb_vmmc>; 552 vmmc-supply = <&reg_sdb_vmmc>;
553 status = "okay"; 553 status = "okay";
554 }; 554 };
555 555
556 &usdhc4 { 556 &usdhc4 {
557 pinctrl-names = "default"; 557 pinctrl-names = "default";
558 pinctrl-0 = <&pinctrl_usdhc4_1>; 558 pinctrl-0 = <&pinctrl_usdhc4_1>;
559 bus-width = <8>; 559 bus-width = <8>;
560 non-removable; 560 non-removable;
561 /* need hw rework to enable signal voltage switch */ 561 /* need hw rework to enable signal voltage switch */
562 no-1-8-v; 562 no-1-8-v;
563 status = "okay"; 563 status = "okay";
564 }; 564 };
565 565
566 &wdog1 { 566 &wdog1 {
567 pinctrl-names = "default"; 567 pinctrl-names = "default";
568 pinctrl-0 = <&pinctrl_wdog>; 568 pinctrl-0 = <&pinctrl_wdog>;
569 fsl,wdog_b; 569 fsl,wdog_b;
570 }; 570 };
571 571
572 &iomuxc { 572 &iomuxc {
573 audmux { 573 audmux {
574 pinctrl_audmux_1: audmuxgrp-1 { 574 pinctrl_audmux_1: audmuxgrp-1 {
575 fsl,pins = < 575 fsl,pins = <
576 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130B0 576 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130B0
577 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130B0 577 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130B0
578 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120B0 578 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120B0
579 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130B0 579 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130B0
580 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 580 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0
581 >; 581 >;
582 }; 582 };
583 583
584 pinctrl_audmux_2: audmuxgrp-2 { 584 pinctrl_audmux_2: audmuxgrp-2 {
585 fsl,pins = < 585 fsl,pins = <
586 MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x130b0 586 MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x130b0
587 MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x130b0 587 MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x130b0
588 MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0 588 MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0
589 MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x130b0 589 MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x130b0
590 >; 590 >;
591 }; 591 };
592 592
593 pinctrl_audmux_3: audmux-3 { 593 pinctrl_audmux_3: audmux-3 {
594 fsl,pins = < 594 fsl,pins = <
595 MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x130b0 595 MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x130b0
596 MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x130b0 596 MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x130b0
597 MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x130b0 597 MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x130b0
598 >; 598 >;
599 }; 599 };
600 }; 600 };
601 601
602 ecspi4 { 602 ecspi4 {
603 pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 { 603 pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 {
604 fsl,pins = < 604 fsl,pins = <
605 MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000 605 MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000
606 >; 606 >;
607 }; 607 };
608 608
609 pinctrl_ecspi4_1: ecspi4grp-1 { 609 pinctrl_ecspi4_1: ecspi4grp-1 {
610 fsl,pins = < 610 fsl,pins = <
611 MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1 611 MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1
612 MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1 612 MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1
613 MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1 613 MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1
614 >; 614 >;
615 }; 615 };
616 }; 616 };
617 617
618 csi { 618 csi {
619 pinctrl_csi_0: csigrp-0 { 619 pinctrl_csi_0: csigrp-0 {
620 fsl,pins = < 620 fsl,pins = <
621 MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 621 MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0
622 MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 622 MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0
623 MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 623 MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0
624 MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 624 MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0
625 MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 625 MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0
626 MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 626 MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0
627 MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 627 MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0
628 MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 628 MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0
629 MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 629 MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0
630 MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 630 MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0
631 MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 631 MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0
632 MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 632 MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0
633 MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 633 MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0
634 MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 634 MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0
635 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 635 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000
636 MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 636 MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000
637 >; 637 >;
638 }; 638 };
639 639
640 pinctrl_csi_1: csigrp-1 { 640 pinctrl_csi_1: csigrp-1 {
641 fsl,pins = < 641 fsl,pins = <
642 MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0 642 MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0
643 MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0 643 MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0
644 MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0 644 MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0
645 MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0 645 MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0
646 MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0 646 MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0
647 MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0 647 MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0
648 MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0 648 MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0
649 MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0 649 MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0
650 MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0 650 MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0
651 MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0 651 MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0
652 MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0 652 MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0
653 MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0 653 MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0
654 654
655 MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x80000000 655 MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x80000000
656 MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x80000000 656 MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x80000000
657 >; 657 >;
658 }; 658 };
659 }; 659 };
660 660
661 enet1 { 661 enet1 {
662 pinctrl_enet1_1: enet1grp-1 { 662 pinctrl_enet1_1: enet1grp-1 {
663 fsl,pins = < 663 fsl,pins = <
664 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 664 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
665 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 665 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
666 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 666 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
667 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 667 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
668 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 668 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
669 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 669 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
670 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 670 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
671 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 671 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
672 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 672 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
673 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 673 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
674 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 674 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
675 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 675 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
676 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 676 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
677 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 677 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
678 >; 678 >;
679 }; 679 };
680 680
681 pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 { 681 pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 {
682 fsl,pins = < 682 fsl,pins = <
683 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 683 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
684 >; 684 >;
685 }; 685 };
686 }; 686 };
687 687
688 enet2 { 688 enet2 {
689 pinctrl_enet2_1: enet2grp-1 { 689 pinctrl_enet2_1: enet2grp-1 {
690 fsl,pins = < 690 fsl,pins = <
691 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 691 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
692 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 692 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
693 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 693 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
694 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 694 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
695 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 695 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
696 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 696 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
697 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 697 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
698 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 698 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
699 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 699 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
700 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 700 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
701 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 701 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
702 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 702 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
703 >; 703 >;
704 }; 704 };
705 }; 705 };
706 706
707 esai { 707 esai {
708 pinctrl_esai_1: esaigrp-1 { 708 pinctrl_esai_1: esaigrp-1 {
709 fsl,pins = < 709 fsl,pins = <
710 MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030 710 MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030
711 MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 711 MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030
712 MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 712 MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030
713 MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 713 MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030
714 MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 714 MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030
715 MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 715 MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030
716 MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 716 MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030
717 MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 717 MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030
718 MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 718 MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030
719 MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 719 MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030
720 MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 720 MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030
721 >; 721 >;
722 }; 722 };
723 723
724 pinctrl_esai_2: esaigrp-2 { 724 pinctrl_esai_2: esaigrp-2 {
725 fsl,pins = < 725 fsl,pins = <
726 MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 726 MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030
727 MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 727 MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030
728 MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 728 MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030
729 MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 729 MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030
730 MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 730 MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030
731 MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 731 MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030
732 MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 732 MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030
733 MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 733 MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030
734 MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 734 MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030
735 MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 735 MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030
736 >; 736 >;
737 }; 737 };
738 }; 738 };
739 739
740 flexcan1 { 740 flexcan1 {
741 pinctrl_flexcan1_1: flexcan1grp-1 { 741 pinctrl_flexcan1_1: flexcan1grp-1 {
742 fsl,pins = < 742 fsl,pins = <
743 MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 743 MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
744 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 744 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
745 >; 745 >;
746 }; 746 };
747 }; 747 };
748 748
749 flexcan2 { 749 flexcan2 {
750 pinctrl_flexcan2_1: flexcan2grp-1 { 750 pinctrl_flexcan2_1: flexcan2grp-1 {
751 fsl,pins = < 751 fsl,pins = <
752 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 752 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
753 MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 753 MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020
754 >; 754 >;
755 }; 755 };
756 }; 756 };
757 757
758 gpmi-nand { 758 gpmi-nand {
759 pinctrl_gpmi_nand_1: gpmi-nand-1 { 759 pinctrl_gpmi_nand_1: gpmi-nand-1 {
760 fsl,pins = < 760 fsl,pins = <
761 MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 761 MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
762 MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 762 MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
763 MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 763 MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
764 MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 764 MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
765 MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 765 MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
766 MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 766 MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
767 MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 767 MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
768 MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 768 MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
769 MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 769 MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
770 MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 770 MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
771 MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 771 MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
772 MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 772 MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
773 MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 773 MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
774 MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 774 MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
775 MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 775 MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
776 MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 776 MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
777 >; 777 >;
778 }; 778 };
779 }; 779 };
780 780
781 i2c1 { 781 i2c1 {
782 pinctrl_i2c1_1: i2c1grp-1 { 782 pinctrl_i2c1_1: i2c1grp-1 {
783 fsl,pins = < 783 fsl,pins = <
784 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 784 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
785 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 785 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
786 >; 786 >;
787 }; 787 };
788 788
789 pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { 789 pinctrl_i2c1_1_gpio: i2c1grp-1-gpio {
790 fsl,pins = < 790 fsl,pins = <
791 MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x1b8b1 791 MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x1b8b1
792 MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x1b8b1 792 MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x1b8b1
793 >; 793 >;
794 }; 794 };
795 795
796 pinctrl_i2c1_2: i2c1grp-2 { 796 pinctrl_i2c1_2: i2c1grp-2 {
797 fsl,pins = < 797 fsl,pins = <
798 MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1 798 MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1
799 MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1 799 MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1
800 >; 800 >;
801 }; 801 };
802 }; 802 };
803 803
804 i2c2 { 804 i2c2 {
805 pinctrl_i2c2_1: i2c2grp-1 { 805 pinctrl_i2c2_1: i2c2grp-1 {
806 fsl,pins = < 806 fsl,pins = <
807 MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 807 MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
808 MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 808 MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
809 >; 809 >;
810 }; 810 };
811 811
812 pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { 812 pinctrl_i2c2_1_gpio: i2c2grp-1-gpio {
813 fsl,pins = < 813 fsl,pins = <
814 MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1 814 MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1
815 MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1 815 MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1
816 >; 816 >;
817 }; 817 };
818 }; 818 };
819 819
820 i2c3 { 820 i2c3 {
821 pinctrl_i2c3_1: i2c3grp-1 { 821 pinctrl_i2c3_1: i2c3grp-1 {
822 fsl,pins = < 822 fsl,pins = <
823 MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1 823 MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1
824 MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 824 MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
825 >; 825 >;
826 }; 826 };
827 827
828 pinctrl_i2c3_1_gpio: i2c3grp-1-gpio { 828 pinctrl_i2c3_1_gpio: i2c3grp-1-gpio {
829 fsl,pins = < 829 fsl,pins = <
830 MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x1b8b1 830 MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x1b8b1
831 MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1 831 MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1
832 >; 832 >;
833 }; 833 };
834 834
835 pinctrl_i2c3_2: i2c3grp-2 { 835 pinctrl_i2c3_2: i2c3grp-2 {
836 fsl,pins = < 836 fsl,pins = <
837 MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 837 MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
838 MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 838 MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
839 >; 839 >;
840 }; 840 };
841 }; 841 };
842 842
843 i2c4 { 843 i2c4 {
844 pinctrl_i2c4_1: i2c4grp-1 { 844 pinctrl_i2c4_1: i2c4grp-1 {
845 fsl,pins = < 845 fsl,pins = <
846 MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 846 MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
847 MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 847 MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
848 >; 848 >;
849 }; 849 };
850 850
851 pinctrl_i2c4_1_gpio: i2c4grp-1-gpio { 851 pinctrl_i2c4_1_gpio: i2c4grp-1-gpio {
852 fsl,pins = < 852 fsl,pins = <
853 MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x1b8b1 853 MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x1b8b1
854 MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x1b8b1 854 MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x1b8b1
855 >; 855 >;
856 }; 856 };
857 857
858 pinctrl_i2c4_2: i2c4grp-2 { 858 pinctrl_i2c4_2: i2c4grp-2 {
859 fsl,pins = < 859 fsl,pins = <
860 MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1 860 MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1
861 MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1 861 MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1
862 >; 862 >;
863 }; 863 };
864 }; 864 };
865 865
866 lcdif1 { 866 lcdif1 {
867 pinctrl_lcdif_dat_0: lcdifdatgrp-0 { 867 pinctrl_lcdif_dat_0: lcdifdatgrp-0 {
868 fsl,pins = < 868 fsl,pins = <
869 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 869 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
870 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 870 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
871 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 871 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
872 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 872 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
873 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 873 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
874 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 874 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
875 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 875 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
876 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 876 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
877 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 877 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
878 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 878 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
879 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 879 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
880 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 880 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
881 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 881 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
882 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 882 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
883 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 883 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
884 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 884 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
885 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 885 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
886 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 886 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
887 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 887 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
888 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 888 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
889 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 889 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
890 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 890 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
891 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 891 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
892 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 892 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
893 >; 893 >;
894 }; 894 };
895 895
896 pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 { 896 pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 {
897 fsl,pins = < 897 fsl,pins = <
898 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 898 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
899 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 899 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
900 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 900 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
901 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 901 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
902 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x1b0b0 902 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x1b0b0
903 >; 903 >;
904 }; 904 };
905 }; 905 };
906 906
907 mlb { 907 mlb {
908 pinctrl_mlb_1: mlbgrp-1 { 908 pinctrl_mlb_1: mlbgrp-1 {
909 fsl,pins = < 909 fsl,pins = <
910 MX6SX_PAD_SD2_DATA3__MLB_DATA 0x31 910 MX6SX_PAD_SD2_DATA3__MLB_DATA 0x31
911 MX6SX_PAD_SD2_CLK__MLB_SIG 0x31 911 MX6SX_PAD_SD2_CLK__MLB_SIG 0x31
912 MX6SX_PAD_SD2_CMD__MLB_CLK 0x31 912 MX6SX_PAD_SD2_CMD__MLB_CLK 0x31
913 >; 913 >;
914 }; 914 };
915 915
916 pinctrl_mlb_2: mlbgrp-2 { 916 pinctrl_mlb_2: mlbgrp-2 {
917 fsl,pins = < 917 fsl,pins = <
918 MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x31 918 MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x31
919 MX6SX_PAD_ENET2_CRS__MLB_SIG 0x31 919 MX6SX_PAD_ENET2_CRS__MLB_SIG 0x31
920 MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x31 920 MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x31
921 >; 921 >;
922 }; 922 };
923 }; 923 };
924 924
925 mqs { 925 mqs {
926 pinctrl_mqs_1: mqsgrp-1 { 926 pinctrl_mqs_1: mqsgrp-1 {
927 fsl,pins = < 927 fsl,pins = <
928 MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x80000000 928 MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x80000000
929 MX6SX_PAD_SD2_CMD__MQS_LEFT 0x80000000 929 MX6SX_PAD_SD2_CMD__MQS_LEFT 0x80000000
930 >; 930 >;
931 }; 931 };
932 }; 932 };
933 933
934 pwm3 { 934 pwm3 {
935 pinctrl_pwm3_0: pwm3grp-0 { 935 pinctrl_pwm3_0: pwm3grp-0 {
936 fsl,pins = < 936 fsl,pins = <
937 MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0 937 MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0
938 >; 938 >;
939 }; 939 };
940 940
941 pinctrl_pwm3_1: pwm3grp-1 { 941 pinctrl_pwm3_1: pwm3grp-1 {
942 fsl,pins = < 942 fsl,pins = <
943 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 943 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
944 >; 944 >;
945 }; 945 };
946 }; 946 };
947 947
948 pwm4 { 948 pwm4 {
949 pinctrl_pwm4_0: pwm4grp-0 { 949 pinctrl_pwm4_0: pwm4grp-0 {
950 fsl,pins = < 950 fsl,pins = <
951 MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 951 MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
952 >; 952 >;
953 }; 953 };
954 }; 954 };
955 955
956 qspi1 { 956 qspi1 {
957 pinctrl_qspi1_1: qspi1grp_1 { 957 pinctrl_qspi1_1: qspi1grp_1 {
958 fsl,pins = < 958 fsl,pins = <
959 MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1 959 MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1
960 MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1 960 MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1
961 MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1 961 MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1
962 MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1 962 MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1
963 MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1 963 MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1
964 MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1 964 MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1
965 MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1 965 MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1
966 MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1 966 MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1
967 MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1 967 MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1
968 MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1 968 MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1
969 MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1 969 MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1
970 MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1 970 MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1
971 >; 971 >;
972 }; 972 };
973 }; 973 };
974 974
975 qspi2 { 975 qspi2 {
976 pinctrl_qspi2_1: qspi2grp_1 { 976 pinctrl_qspi2_1: qspi2grp_1 {
977 fsl,pins = < 977 fsl,pins = <
978 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70a1 978 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70a1
979 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70a1 979 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70a1
980 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70a1 980 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70a1
981 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70a1 981 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70a1
982 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70a1 982 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70a1
983 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70a1 983 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70a1
984 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70a1 984 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70a1
985 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70a1 985 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70a1
986 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70a1 986 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70a1
987 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70a1 987 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70a1
988 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70a1 988 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70a1
989 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70a1 989 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70a1
990 >; 990 >;
991 }; 991 };
992 }; 992 };
993 993
994 sai1 { 994 sai1 {
995 pinctrl_sai1_1: sai1grp_1 { 995 pinctrl_sai1_1: sai1grp_1 {
996 fsl,pins = < 996 fsl,pins = <
997 MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030 997 MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030
998 MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030 998 MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030
999 MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030 999 MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030
1000 MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030 1000 MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030
1001 MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030 1001 MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030
1002 MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030 1002 MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030
1003 >; 1003 >;
1004 }; 1004 };
1005 1005
1006 pinctrl_sai1_2: sai1grp_2 { 1006 pinctrl_sai1_2: sai1grp_2 {
1007 fsl,pins = < 1007 fsl,pins = <
1008 MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130B0 1008 MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130B0
1009 MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130B0 1009 MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130B0
1010 MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120B0 1010 MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120B0
1011 MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130B0 1011 MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130B0
1012 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 1012 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0
1013 >; 1013 >;
1014 }; 1014 };
1015 }; 1015 };
1016 1016
1017 sai2 { 1017 sai2 {
1018 pinctrl_sai2_1: sai2grp_1 { 1018 pinctrl_sai2_1: sai2grp_1 {
1019 fsl,pins = < 1019 fsl,pins = <
1020 MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x1b030 1020 MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x1b030
1021 MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x1b030 1021 MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x1b030
1022 MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x1b030 1022 MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x1b030
1023 MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x1b030 1023 MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x1b030
1024 >; 1024 >;
1025 }; 1025 };
1026 }; 1026 };
1027 1027
1028 1028
1029 spdif { 1029 spdif {
1030 pinctrl_spdif_1: spdifgrp-1 { 1030 pinctrl_spdif_1: spdifgrp-1 {
1031 fsl,pins = < 1031 fsl,pins = <
1032 MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0 1032 MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0
1033 MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 1033 MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0
1034 >; 1034 >;
1035 }; 1035 };
1036 1036
1037 pinctrl_spdif_2: spdifgrp-2 { 1037 pinctrl_spdif_2: spdifgrp-2 {
1038 fsl,pins = < 1038 fsl,pins = <
1039 MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 1039 MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0
1040 >; 1040 >;
1041 }; 1041 };
1042 1042
1043 pinctrl_spdif_3: spdifgrp-3 { 1043 pinctrl_spdif_3: spdifgrp-3 {
1044 fsl,pins = < 1044 fsl,pins = <
1045 MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 1045 MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0
1046 >; 1046 >;
1047 }; 1047 };
1048 }; 1048 };
1049 1049
1050 uart1 { 1050 uart1 {
1051 pinctrl_uart1_1: uart1grp-1 { 1051 pinctrl_uart1_1: uart1grp-1 {
1052 fsl,pins = < 1052 fsl,pins = <
1053 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 1053 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
1054 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 1054 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
1055 >; 1055 >;
1056 }; 1056 };
1057 1057
1058 pinctrl_uart1_2: uart1grp-2 { 1058 pinctrl_uart1_2: uart1grp-2 {
1059 fsl,pins = < 1059 fsl,pins = <
1060 MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1 1060 MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1
1061 MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1 1061 MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1
1062 >; 1062 >;
1063 }; 1063 };
1064 }; 1064 };
1065 1065
1066 uart2 { 1066 uart2 {
1067 pinctrl_uart2_1: uart2grp-1 { 1067 pinctrl_uart2_1: uart2grp-1 {
1068 fsl,pins = < 1068 fsl,pins = <
1069 MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 1069 MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
1070 MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 1070 MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
1071 >; 1071 >;
1072 }; 1072 };
1073 1073
1074 pinctrl_uart2_2: uart2grp-2 { 1074 pinctrl_uart2_2: uart2grp-2 {
1075 fsl,pins = < 1075 fsl,pins = <
1076 MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1 1076 MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1
1077 MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1 1077 MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1
1078 >; 1078 >;
1079 }; 1079 };
1080 }; 1080 };
1081 1081
1082 uart5 { 1082 uart5 {
1083 pinctrl_uart5_1: uart5grp-1 { 1083 pinctrl_uart5_1: uart5grp-1 {
1084 fsl,pins = < 1084 fsl,pins = <
1085 MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 1085 MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
1086 MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 1086 MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
1087 MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 1087 MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
1088 MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 1088 MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
1089 >; 1089 >;
1090 }; 1090 };
1091 1091
1092 pinctrl_uart5dte_1: uart5dtegrp-1 { 1092 pinctrl_uart5dte_1: uart5dtegrp-1 {
1093 fsl,pins = < 1093 fsl,pins = <
1094 MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 1094 MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1
1095 MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 1095 MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1
1096 MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 1096 MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1
1097 MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 1097 MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1
1098 >; 1098 >;
1099 }; 1099 };
1100 }; 1100 };
1101 1101
1102 usbh { 1102 usbh {
1103 pinctrl_usbh_1: usbhgrp-1 { 1103 pinctrl_usbh_1: usbhgrp-1 {
1104 fsl,pins = < 1104 fsl,pins = <
1105 MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40013030 1105 MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40013030
1106 MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030 1106 MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030
1107 >; 1107 >;
1108 }; 1108 };
1109 1109
1110 pinctrl_usbh_2: usbhgrp-2 { 1110 pinctrl_usbh_2: usbhgrp-2 {
1111 fsl,pins = < 1111 fsl,pins = <
1112 MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40017030 1112 MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40017030
1113 >; 1113 >;
1114 }; 1114 };
1115 }; 1115 };
1116 1116
1117 usbotg1 { 1117 usbotg1 {
1118 pinctrl_usbotg1_1: usbotg1grp-1 { 1118 pinctrl_usbotg1_1: usbotg1grp-1 {
1119 fsl,pins = < 1119 fsl,pins = <
1120 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 1120 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
1121 >; 1121 >;
1122 }; 1122 };
1123 1123
1124 pinctrl_usbotg1_2: usbotg1grp-2 { 1124 pinctrl_usbotg1_2: usbotg1grp-2 {
1125 fsl,pins = < 1125 fsl,pins = <
1126 MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059 1126 MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059
1127 >; 1127 >;
1128 }; 1128 };
1129 1129
1130 pinctrl_usbotg1_3: usbotg1grp-3 { 1130 pinctrl_usbotg1_3: usbotg1grp-3 {
1131 fsl,pins = < 1131 fsl,pins = <
1132 MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059 1132 MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059
1133 >; 1133 >;
1134 }; 1134 };
1135 }; 1135 };
1136 1136
1137 usbotg2 { 1137 usbotg2 {
1138 pinctrl_usbotg2_1: usbotg2grp-1 { 1138 pinctrl_usbotg2_1: usbotg2grp-1 {
1139 fsl,pins = < 1139 fsl,pins = <
1140 MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059 1140 MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059
1141 >; 1141 >;
1142 }; 1142 };
1143 1143
1144 pinctrl_usbotg2_2: usbotg2grp-2 { 1144 pinctrl_usbotg2_2: usbotg2grp-2 {
1145 fsl,pins = < 1145 fsl,pins = <
1146 MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059 1146 MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059
1147 >; 1147 >;
1148 }; 1148 };
1149 1149
1150 pinctrl_usbotg2_3: usbotg2grp-3 { 1150 pinctrl_usbotg2_3: usbotg2grp-3 {
1151 fsl,pins = < 1151 fsl,pins = <
1152 MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059 1152 MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059
1153 >; 1153 >;
1154 }; 1154 };
1155 }; 1155 };
1156 1156
1157 usdhc1 { 1157 usdhc1 {
1158 pinctrl_usdhc1_1: usdhc1grp-1 { 1158 pinctrl_usdhc1_1: usdhc1grp-1 {
1159 fsl,pins = < 1159 fsl,pins = <
1160 MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059 1160 MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059
1161 MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059 1161 MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059
1162 MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 1162 MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
1163 MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 1163 MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
1164 MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 1164 MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
1165 MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 1165 MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
1166 >; 1166 >;
1167 }; 1167 };
1168 }; 1168 };
1169 1169
1170 usdhc2 { 1170 usdhc2 {
1171 pinctrl_usdhc2_1: usdhc2grp-1 { 1171 pinctrl_usdhc2_1: usdhc2grp-1 {
1172 fsl,pins = < 1172 fsl,pins = <
1173 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 1173 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
1174 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 1174 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
1175 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 1175 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
1176 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 1176 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
1177 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 1177 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
1178 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 1178 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
1179 >; 1179 >;
1180 }; 1180 };
1181 }; 1181 };
1182 1182
1183 usdhc3 { 1183 usdhc3 {
1184 pinctrl_usdhc3_1: usdhc3grp-1 { 1184 pinctrl_usdhc3_1: usdhc3grp-1 {
1185 fsl,pins = < 1185 fsl,pins = <
1186 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 1186 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
1187 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 1187 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
1188 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 1188 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
1189 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 1189 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
1190 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 1190 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
1191 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 1191 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
1192 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 1192 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
1193 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 1193 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
1194 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 1194 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
1195 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 1195 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
1196 >; 1196 >;
1197 }; 1197 };
1198 1198
1199 pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { 1199 pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
1200 fsl,pins = < 1200 fsl,pins = <
1201 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 1201 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
1202 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 1202 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
1203 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 1203 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
1204 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 1204 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
1205 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 1205 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
1206 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 1206 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
1207 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 1207 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
1208 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 1208 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
1209 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 1209 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
1210 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 1210 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
1211 >; 1211 >;
1212 }; 1212 };
1213 1213
1214 pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { 1214 pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
1215 fsl,pins = < 1215 fsl,pins = <
1216 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 1216 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
1217 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 1217 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
1218 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 1218 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
1219 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 1219 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
1220 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 1220 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
1221 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 1221 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
1222 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 1222 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
1223 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 1223 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
1224 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 1224 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
1225 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 1225 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
1226 >; 1226 >;
1227 }; 1227 };
1228 1228
1229 }; 1229 };
1230 1230
1231 usdhc4 { 1231 usdhc4 {
1232 pinctrl_usdhc4_1: usdhc4grp-1 { 1232 pinctrl_usdhc4_1: usdhc4grp-1 {
1233 fsl,pins = < 1233 fsl,pins = <
1234 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 1234 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
1235 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 1235 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
1236 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 1236 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
1237 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 1237 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
1238 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 1238 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
1239 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 1239 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
1240 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 1240 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
1241 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 1241 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
1242 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 1242 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
1243 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 1243 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
1244 >; 1244 >;
1245 }; 1245 };
1246 1246
1247 pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { 1247 pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz {
1248 fsl,pins = < 1248 fsl,pins = <
1249 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 1249 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
1250 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 1250 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
1251 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 1251 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
1252 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 1252 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
1253 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 1253 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
1254 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 1254 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
1255 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 1255 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
1256 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 1256 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
1257 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 1257 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
1258 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 1258 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
1259 >; 1259 >;
1260 }; 1260 };
1261 1261
1262 pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { 1262 pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz {
1263 fsl,pins = < 1263 fsl,pins = <
1264 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 1264 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
1265 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 1265 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
1266 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 1266 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
1267 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 1267 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
1268 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 1268 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
1269 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 1269 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
1270 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 1270 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
1271 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 1271 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
1272 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 1272 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
1273 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 1273 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
1274 >; 1274 >;
1275 }; 1275 };
1276 1276
1277 pinctrl_usdhc4_2: usdhc4grp-2 { 1277 pinctrl_usdhc4_2: usdhc4grp-2 {
1278 fsl,pins = < 1278 fsl,pins = <
1279 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 1279 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
1280 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 1280 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
1281 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 1281 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
1282 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 1282 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
1283 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 1283 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
1284 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 1284 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
1285 >; 1285 >;
1286 }; 1286 };
1287 1287
1288 pinctrl_usdhc4_3: usdhc4grp-3 { 1288 pinctrl_usdhc4_3: usdhc4grp-3 {
1289 fsl,pins = < 1289 fsl,pins = <
1290 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 1290 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071
1291 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 1291 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071
1292 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 1292 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071
1293 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 1293 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071
1294 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 1294 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071
1295 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 1295 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071
1296 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071 1296 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071
1297 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071 1297 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071
1298 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071 1298 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071
1299 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071 1299 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071
1300 >; 1300 >;
1301 }; 1301 };
1302 1302
1303 }; 1303 };
1304 1304
1305 wdog { 1305 wdog {
1306 pinctrl_wdog: wdoggrp { 1306 pinctrl_wdog: wdoggrp {
1307 fsl,pins = < 1307 fsl,pins = <
1308 MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0 1308 MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0
1309 >; 1309 >;
1310 }; 1310 };
1311 }; 1311 };
1312 1312
1313 weim { 1313 weim {
1314 pinctrl_weim_cs0_1: weim_cs0grp-1 { 1314 pinctrl_weim_cs0_1: weim_cs0grp-1 {
1315 fsl,pins = < 1315 fsl,pins = <
1316 MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1 1316 MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1
1317 >; 1317 >;
1318 }; 1318 };
1319 1319
1320 pinctrl_weim_nor_1: weim_norgrp-1 { 1320 pinctrl_weim_nor_1: weim_norgrp-1 {
1321 fsl,pins = < 1321 fsl,pins = <
1322 MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1 1322 MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1
1323 MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1 1323 MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1
1324 MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060 1324 MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060
1325 /* data */ 1325 /* data */
1326 MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0 1326 MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0
1327 MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0 1327 MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0
1328 MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0 1328 MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0
1329 MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0 1329 MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0
1330 MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0 1330 MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0
1331 MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0 1331 MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0
1332 MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0 1332 MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0
1333 MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0 1333 MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0
1334 MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0 1334 MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0
1335 MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0 1335 MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0
1336 MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0 1336 MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0
1337 MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0 1337 MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0
1338 MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0 1338 MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0
1339 MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0 1339 MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0
1340 MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0 1340 MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0
1341 MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0 1341 MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0
1342 /* address */ 1342 /* address */
1343 MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1 1343 MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1
1344 MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1 1344 MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1
1345 MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1 1345 MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1
1346 MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1 1346 MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1
1347 MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1 1347 MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1
1348 MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1 1348 MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1
1349 MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1 1349 MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1
1350 MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1 1350 MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1
1351 MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1 1351 MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1
1352 MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1 1352 MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1
1353 MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1 1353 MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1
1354 MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1 1354 MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1
1355 MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1 1355 MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1
1356 MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1 1356 MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1
1357 MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1 1357 MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1
1358 MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1 1358 MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1
1359 MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1 1359 MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1
1360 MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1 1360 MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1
1361 MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1 1361 MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1
1362 MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1 1362 MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1
1363 MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1 1363 MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1
1364 MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1 1364 MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1
1365 MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1 1365 MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1
1366 MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1 1366 MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1
1367 MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1 1367 MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1
1368 MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1 1368 MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1
1369 >; 1369 >;
1370 }; 1370 };
1371 }; 1371 };
1372 }; 1372 };
1373 1373
arch/arm/dts/imx6sx-sdb.dtsi
Diff comments   View file @ 4daafb3
1 /* 1 /*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc. 2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h> 12 #include <dt-bindings/input/input.h>
13 #include "imx6sx.dtsi" 13 #include "imx6sx.dtsi"
14 14
15 / { 15 / {
16 model = "Freescale i.MX6 SoloX SDB Board"; 16 model = "Freescale i.MX6 SoloX SDB Board";
17 compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; 17 compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
18 18
19 chosen { 19 chosen {
20 stdout-path = &uart1; 20 stdout-path = &uart1;
21 }; 21 };
22 22
23 memory { 23 memory {
24 reg = <0x80000000 0x40000000>; 24 reg = <0x80000000 0x40000000>;
25 }; 25 };
26 26
27 backlight1 { 27 backlight1 {
28 compatible = "pwm-backlight"; 28 compatible = "pwm-backlight";
29 pwms = <&pwm3 0 5000000>; 29 pwms = <&pwm3 0 5000000>;
30 brightness-levels = <0 4 8 16 32 64 128 255>; 30 brightness-levels = <0 4 8 16 32 64 128 255>;
31 default-brightness-level = <6>; 31 default-brightness-level = <6>;
32 fb-names = "mxs-lcdif0"; 32 fb-names = "mxs-lcdif0";
33 }; 33 };
34 backlight2 { 34 backlight2 {
35 compatible = "pwm-backlight"; 35 compatible = "pwm-backlight";
36 pwms = <&pwm4 0 5000000>; 36 pwms = <&pwm4 0 5000000>;
37 brightness-levels = <0 4 8 16 32 64 128 255>; 37 brightness-levels = <0 4 8 16 32 64 128 255>;
38 default-brightness-level = <6>; 38 default-brightness-level = <6>;
39 fb-names = "mxs-lcdif1"; 39 fb-names = "mxs-lcdif1";
40 }; 40 };
41 41
42 gpio-keys { 42 gpio-keys {
43 compatible = "gpio-keys"; 43 compatible = "gpio-keys";
44 pinctrl-names = "default"; 44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_gpio_keys>; 45 pinctrl-0 = <&pinctrl_gpio_keys>;
46 46
47 volume-up { 47 volume-up {
48 label = "Volume Up"; 48 label = "Volume Up";
49 gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; 49 gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
50 linux,code = <KEY_VOLUMEUP>; 50 linux,code = <KEY_VOLUMEUP>;
51 }; 51 };
52 52
53 volume-down { 53 volume-down {
54 label = "Volume Down"; 54 label = "Volume Down";
55 gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 55 gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
56 linux,code = <KEY_VOLUMEDOWN>; 56 linux,code = <KEY_VOLUMEDOWN>;
57 }; 57 };
58 }; 58 };
59 59
60 hannstar_cabc { 60 hannstar_cabc {
61 compatible = "hannstar,cabc"; 61 compatible = "hannstar,cabc";
62 lvds0 { 62 lvds0 {
63 gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; 63 gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
64 }; 64 };
65 }; 65 };
66 66
67 pxp_v4l2_out { 67 pxp_v4l2_out {
68 compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; 68 compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
69 status = "okay"; 69 status = "okay";
70 }; 70 };
71 71
72 regulators { 72 regulators {
73 compatible = "simple-bus"; 73 compatible = "simple-bus";
74 #address-cells = <1>; 74 #address-cells = <1>;
75 #size-cells = <0>; 75 #size-cells = <0>;
76 76
77 vcc_sd3: regulator@0 { 77 vcc_sd3: regulator@0 {
78 compatible = "regulator-fixed"; 78 compatible = "regulator-fixed";
79 reg = <0>; 79 reg = <0>;
80 pinctrl-names = "default"; 80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_vcc_sd3>; 81 pinctrl-0 = <&pinctrl_vcc_sd3>;
82 regulator-name = "VCC_SD3"; 82 regulator-name = "VCC_SD3";
83 regulator-min-microvolt = <3000000>; 83 regulator-min-microvolt = <3000000>;
84 regulator-max-microvolt = <3000000>; 84 regulator-max-microvolt = <3000000>;
85 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; 85 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
86 off-on-delay = <20000>; 86 u-boot,off-on-delay-us = <20000>;
87 enable-active-high; 87 enable-active-high;
88 }; 88 };
89 89
90 reg_usb_otg1_vbus: regulator@1 { 90 reg_usb_otg1_vbus: regulator@1 {
91 compatible = "regulator-fixed"; 91 compatible = "regulator-fixed";
92 reg = <1>; 92 reg = <1>;
93 pinctrl-names = "default"; 93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_usb_otg1>; 94 pinctrl-0 = <&pinctrl_usb_otg1>;
95 regulator-name = "usb_otg1_vbus"; 95 regulator-name = "usb_otg1_vbus";
96 regulator-min-microvolt = <5000000>; 96 regulator-min-microvolt = <5000000>;
97 regulator-max-microvolt = <5000000>; 97 regulator-max-microvolt = <5000000>;
98 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 98 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
99 enable-active-high; 99 enable-active-high;
100 }; 100 };
101 101
102 reg_usb_otg2_vbus: regulator@2 { 102 reg_usb_otg2_vbus: regulator@2 {
103 compatible = "regulator-fixed"; 103 compatible = "regulator-fixed";
104 reg = <2>; 104 reg = <2>;
105 pinctrl-names = "default"; 105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_usb_otg2>; 106 pinctrl-0 = <&pinctrl_usb_otg2>;
107 regulator-name = "usb_otg2_vbus"; 107 regulator-name = "usb_otg2_vbus";
108 regulator-min-microvolt = <5000000>; 108 regulator-min-microvolt = <5000000>;
109 regulator-max-microvolt = <5000000>; 109 regulator-max-microvolt = <5000000>;
110 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 110 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
111 enable-active-high; 111 enable-active-high;
112 }; 112 };
113 113
114 reg_psu_5v: regulator@3 { 114 reg_psu_5v: regulator@3 {
115 compatible = "regulator-fixed"; 115 compatible = "regulator-fixed";
116 reg = <3>; 116 reg = <3>;
117 regulator-name = "PSU-5V0"; 117 regulator-name = "PSU-5V0";
118 regulator-min-microvolt = <5000000>; 118 regulator-min-microvolt = <5000000>;
119 regulator-max-microvolt = <5000000>; 119 regulator-max-microvolt = <5000000>;
120 }; 120 };
121 121
122 reg_lcd_3v3: regulator@4 { 122 reg_lcd_3v3: regulator@4 {
123 compatible = "regulator-fixed"; 123 compatible = "regulator-fixed";
124 reg = <4>; 124 reg = <4>;
125 regulator-name = "lcd-3v3"; 125 regulator-name = "lcd-3v3";
126 gpio = <&gpio3 27 0>; 126 gpio = <&gpio3 27 0>;
127 enable-active-high; 127 enable-active-high;
128 status = "disabled"; 128 status = "disabled";
129 }; 129 };
130 130
131 reg_peri_3v3: regulator@5 { 131 reg_peri_3v3: regulator@5 {
132 compatible = "regulator-fixed"; 132 compatible = "regulator-fixed";
133 reg = <5>; 133 reg = <5>;
134 pinctrl-names = "default"; 134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_peri_3v3>; 135 pinctrl-0 = <&pinctrl_peri_3v3>;
136 regulator-name = "peri_3v3"; 136 regulator-name = "peri_3v3";
137 regulator-min-microvolt = <3300000>; 137 regulator-min-microvolt = <3300000>;
138 regulator-max-microvolt = <3300000>; 138 regulator-max-microvolt = <3300000>;
139 gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; 139 gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
140 enable-active-high; 140 enable-active-high;
141 regulator-always-on; 141 regulator-always-on;
142 }; 142 };
143 143
144 reg_enet_3v3: regulator@6 { 144 reg_enet_3v3: regulator@6 {
145 compatible = "regulator-fixed"; 145 compatible = "regulator-fixed";
146 reg = <6>; 146 reg = <6>;
147 pinctrl-names = "default"; 147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_enet_3v3>; 148 pinctrl-0 = <&pinctrl_enet_3v3>;
149 regulator-name = "enet_3v3"; 149 regulator-name = "enet_3v3";
150 regulator-min-microvolt = <3300000>; 150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>; 151 regulator-max-microvolt = <3300000>;
152 gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; 152 gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
153 }; 153 };
154 154
155 reg_vref_3v3: regulator@7 { 155 reg_vref_3v3: regulator@7 {
156 compatible = "regulator-fixed"; 156 compatible = "regulator-fixed";
157 reg = <7>; 157 reg = <7>;
158 regulator-name = "vref-3v3"; 158 regulator-name = "vref-3v3";
159 regulator-min-microvolt = <3300000>; 159 regulator-min-microvolt = <3300000>;
160 regulator-max-microvolt = <3300000>; 160 regulator-max-microvolt = <3300000>;
161 }; 161 };
162 162
163 reg_pcie: regulator@8 { 163 reg_pcie: regulator@8 {
164 compatible = "regulator-fixed"; 164 compatible = "regulator-fixed";
165 reg = <8>; 165 reg = <8>;
166 pinctrl-names = "default"; 166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_pcie_reg>; 167 pinctrl-0 = <&pinctrl_pcie_reg>;
168 regulator-name = "MPCIE_3V3"; 168 regulator-name = "MPCIE_3V3";
169 regulator-min-microvolt = <3300000>; 169 regulator-min-microvolt = <3300000>;
170 regulator-max-microvolt = <3300000>; 170 regulator-max-microvolt = <3300000>;
171 gpio = <&gpio2 1 0>; 171 gpio = <&gpio2 1 0>;
172 regulator-always-on; 172 regulator-always-on;
173 enable-active-high; 173 enable-active-high;
174 }; 174 };
175 175
176 reg_can_en: regulator@9 { 176 reg_can_en: regulator@9 {
177 compatible = "regulator-fixed"; 177 compatible = "regulator-fixed";
178 reg = <9>; 178 reg = <9>;
179 regulator-name = "can-en"; 179 regulator-name = "can-en";
180 regulator-min-microvolt = <3300000>; 180 regulator-min-microvolt = <3300000>;
181 regulator-max-microvolt = <3300000>; 181 regulator-max-microvolt = <3300000>;
182 }; 182 };
183 183
184 reg_can_stby: regulator@10 { 184 reg_can_stby: regulator@10 {
185 compatible = "regulator-fixed"; 185 compatible = "regulator-fixed";
186 reg = <10>; 186 reg = <10>;
187 regulator-name = "can-stby"; 187 regulator-name = "can-stby";
188 regulator-min-microvolt = <3300000>; 188 regulator-min-microvolt = <3300000>;
189 regulator-max-microvolt = <3300000>; 189 regulator-max-microvolt = <3300000>;
190 }; 190 };
191 }; 191 };
192 192
193 sound { 193 sound {
194 compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; 194 compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
195 model = "wm8962-audio"; 195 model = "wm8962-audio";
196 cpu-dai = <&ssi2>; 196 cpu-dai = <&ssi2>;
197 audio-codec = <&codec>; 197 audio-codec = <&codec>;
198 audio-routing = 198 audio-routing =
199 "Headphone Jack", "HPOUTL", 199 "Headphone Jack", "HPOUTL",
200 "Headphone Jack", "HPOUTR", 200 "Headphone Jack", "HPOUTR",
201 "Ext Spk", "SPKOUTL", 201 "Ext Spk", "SPKOUTL",
202 "Ext Spk", "SPKOUTR", 202 "Ext Spk", "SPKOUTR",
203 "AMIC", "MICBIAS", 203 "AMIC", "MICBIAS",
204 "IN3R", "AMIC"; 204 "IN3R", "AMIC";
205 mux-int-port = <2>; 205 mux-int-port = <2>;
206 mux-ext-port = <6>; 206 mux-ext-port = <6>;
207 codec-master; 207 codec-master;
208 hp-det-gpios = <&gpio1 17 1>; 208 hp-det-gpios = <&gpio1 17 1>;
209 }; 209 };
210 210
211 sound-spdif { 211 sound-spdif {
212 compatible = "fsl,imx-audio-spdif", 212 compatible = "fsl,imx-audio-spdif",
213 "fsl,imx6sx-sdb-spdif"; 213 "fsl,imx6sx-sdb-spdif";
214 model = "imx-spdif"; 214 model = "imx-spdif";
215 spdif-controller = <&spdif>; 215 spdif-controller = <&spdif>;
216 spdif-out; 216 spdif-out;
217 }; 217 };
218 218
219 sii902x_reset: sii902x-reset { 219 sii902x_reset: sii902x-reset {
220 compatible = "gpio-reset"; 220 compatible = "gpio-reset";
221 reset-gpios = <&gpio3 27 1>; 221 reset-gpios = <&gpio3 27 1>;
222 reset-delay-us = <100000>; 222 reset-delay-us = <100000>;
223 #reset-cells = <0>; 223 #reset-cells = <0>;
224 status = "disabled"; 224 status = "disabled";
225 }; 225 };
226 }; 226 };
227 227
228 &adc1 { 228 &adc1 {
229 vref-supply = <&reg_vref_3v3>; 229 vref-supply = <&reg_vref_3v3>;
230 status = "okay"; 230 status = "okay";
231 }; 231 };
232 232
233 &adc2 { 233 &adc2 {
234 vref-supply = <&reg_vref_3v3>; 234 vref-supply = <&reg_vref_3v3>;
235 status = "okay"; 235 status = "okay";
236 }; 236 };
237 237
238 &audmux { 238 &audmux {
239 pinctrl-names = "default"; 239 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_audmux>; 240 pinctrl-0 = <&pinctrl_audmux>;
241 status = "okay"; 241 status = "okay";
242 }; 242 };
243 243
244 244
245 &gpc { 245 &gpc {
246 fsl,ldo-bypass = <1>; 246 fsl,ldo-bypass = <1>;
247 }; 247 };
248 248
249 &fec1 { 249 &fec1 {
250 pinctrl-names = "default"; 250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_enet1>; 251 pinctrl-0 = <&pinctrl_enet1>;
252 phy-supply = <&reg_enet_3v3>; 252 phy-supply = <&reg_enet_3v3>;
253 phy-mode = "rgmii"; 253 phy-mode = "rgmii";
254 phy-handle = <&ethphy1>; 254 phy-handle = <&ethphy1>;
255 status = "okay"; 255 status = "okay";
256 256
257 mdio { 257 mdio {
258 #address-cells = <1>; 258 #address-cells = <1>;
259 #size-cells = <0>; 259 #size-cells = <0>;
260 260
261 ethphy1: ethernet-phy@1 { 261 ethphy1: ethernet-phy@1 {
262 reg = <1>; 262 reg = <1>;
263 }; 263 };
264 264
265 ethphy2: ethernet-phy@2 { 265 ethphy2: ethernet-phy@2 {
266 reg = <2>; 266 reg = <2>;
267 }; 267 };
268 }; 268 };
269 }; 269 };
270 270
271 &csi1 { 271 &csi1 {
272 status = "okay"; 272 status = "okay";
273 273
274 port { 274 port {
275 csi1_ep: endpoint { 275 csi1_ep: endpoint {
276 remote-endpoint = <&ov5640_ep>; 276 remote-endpoint = <&ov5640_ep>;
277 }; 277 };
278 }; 278 };
279 }; 279 };
280 280
281 &csi2 { 281 &csi2 {
282 status = "okay"; 282 status = "okay";
283 port { 283 port {
284 csi2_ep: endpoint { 284 csi2_ep: endpoint {
285 remote-endpoint = <&vadc_ep>; 285 remote-endpoint = <&vadc_ep>;
286 }; 286 };
287 }; 287 };
288 }; 288 };
289 289
290 &dcic1 { 290 &dcic1 {
291 dcic_id = <0>; 291 dcic_id = <0>;
292 dcic_mux = "dcic-lcdif1"; 292 dcic_mux = "dcic-lcdif1";
293 status = "okay"; 293 status = "okay";
294 }; 294 };
295 295
296 &dcic2 { 296 &dcic2 {
297 dcic_id = <1>; 297 dcic_id = <1>;
298 dcic_mux = "dcic-lvds"; 298 dcic_mux = "dcic-lvds";
299 status = "okay"; 299 status = "okay";
300 }; 300 };
301 301
302 &fec2 { 302 &fec2 {
303 pinctrl-names = "default"; 303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_enet2>; 304 pinctrl-0 = <&pinctrl_enet2>;
305 phy-mode = "rgmii"; 305 phy-mode = "rgmii";
306 phy-handle = <&ethphy2>; 306 phy-handle = <&ethphy2>;
307 status = "okay"; 307 status = "okay";
308 }; 308 };
309 309
310 &flexcan1 { 310 &flexcan1 {
311 pinctrl-names = "default"; 311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_flexcan1>; 312 pinctrl-0 = <&pinctrl_flexcan1>;
313 xceiver-supply = <&reg_can_stby>; 313 xceiver-supply = <&reg_can_stby>;
314 status = "okay"; 314 status = "okay";
315 }; 315 };
316 316
317 &flexcan2 { 317 &flexcan2 {
318 pinctrl-names = "default"; 318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_flexcan2>; 319 pinctrl-0 = <&pinctrl_flexcan2>;
320 xceiver-supply = <&reg_can_stby>; 320 xceiver-supply = <&reg_can_stby>;
321 status = "okay"; 321 status = "okay";
322 }; 322 };
323 323
324 &i2c1 { 324 &i2c1 {
325 clock-frequency = <100000>; 325 clock-frequency = <100000>;
326 pinctrl-names = "default", "gpio"; 326 pinctrl-names = "default", "gpio";
327 pinctrl-0 = <&pinctrl_i2c1>; 327 pinctrl-0 = <&pinctrl_i2c1>;
328 pinctrl-1 = <&pinctrl_i2c1_gpio>; 328 pinctrl-1 = <&pinctrl_i2c1_gpio>;
329 scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; 329 scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
330 sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 330 sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
331 status = "okay"; 331 status = "okay";
332 332
333 pmic: pfuze100@08 { 333 pmic: pfuze100@08 {
334 compatible = "fsl,pfuze200"; 334 compatible = "fsl,pfuze200";
335 reg = <0x08>; 335 reg = <0x08>;
336 336
337 regulators { 337 regulators {
338 sw1a_reg: sw1ab { 338 sw1a_reg: sw1ab {
339 regulator-min-microvolt = <300000>; 339 regulator-min-microvolt = <300000>;
340 regulator-max-microvolt = <1875000>; 340 regulator-max-microvolt = <1875000>;
341 regulator-boot-on; 341 regulator-boot-on;
342 regulator-always-on; 342 regulator-always-on;
343 regulator-ramp-delay = <6250>; 343 regulator-ramp-delay = <6250>;
344 }; 344 };
345 345
346 sw2_reg: sw2 { 346 sw2_reg: sw2 {
347 regulator-min-microvolt = <800000>; 347 regulator-min-microvolt = <800000>;
348 regulator-max-microvolt = <3300000>; 348 regulator-max-microvolt = <3300000>;
349 regulator-boot-on; 349 regulator-boot-on;
350 regulator-always-on; 350 regulator-always-on;
351 }; 351 };
352 352
353 sw3a_reg: sw3a { 353 sw3a_reg: sw3a {
354 regulator-min-microvolt = <400000>; 354 regulator-min-microvolt = <400000>;
355 regulator-max-microvolt = <1975000>; 355 regulator-max-microvolt = <1975000>;
356 regulator-boot-on; 356 regulator-boot-on;
357 regulator-always-on; 357 regulator-always-on;
358 }; 358 };
359 359
360 sw3b_reg: sw3b { 360 sw3b_reg: sw3b {
361 regulator-min-microvolt = <400000>; 361 regulator-min-microvolt = <400000>;
362 regulator-max-microvolt = <1975000>; 362 regulator-max-microvolt = <1975000>;
363 regulator-boot-on; 363 regulator-boot-on;
364 regulator-always-on; 364 regulator-always-on;
365 }; 365 };
366 366
367 swbst_reg: swbst { 367 swbst_reg: swbst {
368 regulator-min-microvolt = <5000000>; 368 regulator-min-microvolt = <5000000>;
369 regulator-max-microvolt = <5150000>; 369 regulator-max-microvolt = <5150000>;
370 }; 370 };
371 371
372 snvs_reg: vsnvs { 372 snvs_reg: vsnvs {
373 regulator-min-microvolt = <1000000>; 373 regulator-min-microvolt = <1000000>;
374 regulator-max-microvolt = <3000000>; 374 regulator-max-microvolt = <3000000>;
375 regulator-boot-on; 375 regulator-boot-on;
376 regulator-always-on; 376 regulator-always-on;
377 }; 377 };
378 378
379 vref_reg: vrefddr { 379 vref_reg: vrefddr {
380 regulator-boot-on; 380 regulator-boot-on;
381 regulator-always-on; 381 regulator-always-on;
382 }; 382 };
383 383
384 vgen1_reg: vgen1 { 384 vgen1_reg: vgen1 {
385 regulator-min-microvolt = <800000>; 385 regulator-min-microvolt = <800000>;
386 regulator-max-microvolt = <1550000>; 386 regulator-max-microvolt = <1550000>;
387 regulator-always-on; 387 regulator-always-on;
388 }; 388 };
389 389
390 vgen2_reg: vgen2 { 390 vgen2_reg: vgen2 {
391 regulator-min-microvolt = <800000>; 391 regulator-min-microvolt = <800000>;
392 regulator-max-microvolt = <1550000>; 392 regulator-max-microvolt = <1550000>;
393 }; 393 };
394 394
395 vgen3_reg: vgen3 { 395 vgen3_reg: vgen3 {
396 regulator-min-microvolt = <1800000>; 396 regulator-min-microvolt = <1800000>;
397 regulator-max-microvolt = <3300000>; 397 regulator-max-microvolt = <3300000>;
398 regulator-always-on; 398 regulator-always-on;
399 }; 399 };
400 400
401 vgen4_reg: vgen4 { 401 vgen4_reg: vgen4 {
402 regulator-min-microvolt = <1800000>; 402 regulator-min-microvolt = <1800000>;
403 regulator-max-microvolt = <3300000>; 403 regulator-max-microvolt = <3300000>;
404 regulator-always-on; 404 regulator-always-on;
405 }; 405 };
406 406
407 vgen5_reg: vgen5 { 407 vgen5_reg: vgen5 {
408 regulator-min-microvolt = <1800000>; 408 regulator-min-microvolt = <1800000>;
409 regulator-max-microvolt = <3300000>; 409 regulator-max-microvolt = <3300000>;
410 regulator-always-on; 410 regulator-always-on;
411 }; 411 };
412 412
413 vgen6_reg: vgen6 { 413 vgen6_reg: vgen6 {
414 regulator-min-microvolt = <1800000>; 414 regulator-min-microvolt = <1800000>;
415 regulator-max-microvolt = <3300000>; 415 regulator-max-microvolt = <3300000>;
416 regulator-always-on; 416 regulator-always-on;
417 }; 417 };
418 }; 418 };
419 }; 419 };
420 420
421 ov5640: ov5640@3c { 421 ov5640: ov5640@3c {
422 compatible = "ovti,ov5640"; 422 compatible = "ovti,ov5640";
423 reg = <0x3c>; 423 reg = <0x3c>;
424 pinctrl-names = "default"; 424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_csi_0>; 425 pinctrl-0 = <&pinctrl_csi_0>;
426 clocks = <&clks IMX6SX_CLK_CSI>; 426 clocks = <&clks IMX6SX_CLK_CSI>;
427 clock-names = "csi_mclk"; 427 clock-names = "csi_mclk";
428 AVDD-supply = <&vgen3_reg>; /* 2.8v */ 428 AVDD-supply = <&vgen3_reg>; /* 2.8v */
429 DVDD-supply = <&vgen2_reg>; /* 1.5v*/ 429 DVDD-supply = <&vgen2_reg>; /* 1.5v*/
430 pwn-gpios = <&gpio3 28 1>; 430 pwn-gpios = <&gpio3 28 1>;
431 rst-gpios = <&gpio3 27 0>; 431 rst-gpios = <&gpio3 27 0>;
432 csi_id = <0>; 432 csi_id = <0>;
433 mclk = <24000000>; 433 mclk = <24000000>;
434 mclk_source = <0>; 434 mclk_source = <0>;
435 port { 435 port {
436 ov5640_ep: endpoint { 436 ov5640_ep: endpoint {
437 remote-endpoint = <&csi1_ep>; 437 remote-endpoint = <&csi1_ep>;
438 }; 438 };
439 }; 439 };
440 }; 440 };
441 441
442 sii902x@39 { 442 sii902x@39 {
443 compatible = "SiI,sii902x"; 443 compatible = "SiI,sii902x";
444 interrupt-parent = <&gpio4>; 444 interrupt-parent = <&gpio4>;
445 interrupts = <21 2>; 445 interrupts = <21 2>;
446 mode_str ="1280x720M@60"; 446 mode_str ="1280x720M@60";
447 bits-per-pixel = <16>; 447 bits-per-pixel = <16>;
448 resets = <&sii902x_reset>; 448 resets = <&sii902x_reset>;
449 reg = <0x39>; 449 reg = <0x39>;
450 status = "disabled"; 450 status = "disabled";
451 }; 451 };
452 }; 452 };
453 453
454 &i2c2 { 454 &i2c2 {
455 clock-frequency = <100000>; 455 clock-frequency = <100000>;
456 pinctrl-names = "default", "gpio"; 456 pinctrl-names = "default", "gpio";
457 pinctrl-0 = <&pinctrl_i2c2>; 457 pinctrl-0 = <&pinctrl_i2c2>;
458 pinctrl-1 = <&pinctrl_i2c2_gpio>; 458 pinctrl-1 = <&pinctrl_i2c2_gpio>;
459 scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 459 scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
460 sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 460 sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
461 status = "okay"; 461 status = "okay";
462 462
463 egalax_ts@04 { 463 egalax_ts@04 {
464 compatible = "eeti,egalax_ts"; 464 compatible = "eeti,egalax_ts";
465 reg = <0x04>; 465 reg = <0x04>;
466 pinctrl-names = "default"; 466 pinctrl-names = "default";
467 pinctrl-0 = <&pinctrl_egalax_int>; 467 pinctrl-0 = <&pinctrl_egalax_int>;
468 interrupt-parent = <&gpio4>; 468 interrupt-parent = <&gpio4>;
469 interrupts = <19 2>; 469 interrupts = <19 2>;
470 wakeup-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; 470 wakeup-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
471 }; 471 };
472 }; 472 };
473 473
474 &i2c3 { 474 &i2c3 {
475 clock-frequency = <100000>; 475 clock-frequency = <100000>;
476 pinctrl-names = "default", "gpio"; 476 pinctrl-names = "default", "gpio";
477 pinctrl-0 = <&pinctrl_i2c3>; 477 pinctrl-0 = <&pinctrl_i2c3>;
478 pinctrl-1 = <&pinctrl_i2c3_gpio>; 478 pinctrl-1 = <&pinctrl_i2c3_gpio>;
479 scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; 479 scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
480 sda-gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; 480 sda-gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
481 status = "okay"; 481 status = "okay";
482 482
483 isl29023@44 { 483 isl29023@44 {
484 compatible = "fsl,isl29023"; 484 compatible = "fsl,isl29023";
485 reg = <0x44>; 485 reg = <0x44>;
486 rext = <499>; 486 rext = <499>;
487 interrupt-parent = <&gpio6>; 487 interrupt-parent = <&gpio6>;
488 interrupts = <5 1>; 488 interrupts = <5 1>;
489 shared-interrupt; 489 shared-interrupt;
490 }; 490 };
491 491
492 mag3110@0e { 492 mag3110@0e {
493 compatible = "fsl,mag3110"; 493 compatible = "fsl,mag3110";
494 reg = <0x0e>; 494 reg = <0x0e>;
495 position = <2>; 495 position = <2>;
496 interrupt-parent = <&gpio6>; 496 interrupt-parent = <&gpio6>;
497 interrupts = <5 1>; 497 interrupts = <5 1>;
498 shared-interrupt; 498 shared-interrupt;
499 }; 499 };
500 500
501 mma8451@1c { 501 mma8451@1c {
502 compatible = "fsl,mma8451"; 502 compatible = "fsl,mma8451";
503 reg = <0x1c>; 503 reg = <0x1c>;
504 position = <1>; 504 position = <1>;
505 interrupt-parent = <&gpio6>; 505 interrupt-parent = <&gpio6>;
506 interrupts = <2 8>; 506 interrupts = <2 8>;
507 interrupt-route = <2>; 507 interrupt-route = <2>;
508 }; 508 };
509 }; 509 };
510 510
511 &i2c4 { 511 &i2c4 {
512 clock-frequency = <100000>; 512 clock-frequency = <100000>;
513 pinctrl-names = "default", "gpio"; 513 pinctrl-names = "default", "gpio";
514 pinctrl-0 = <&pinctrl_i2c4>; 514 pinctrl-0 = <&pinctrl_i2c4>;
515 pinctrl-1 = <&pinctrl_i2c4_gpio>; 515 pinctrl-1 = <&pinctrl_i2c4_gpio>;
516 scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; 516 scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
517 sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; 517 sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
518 status = "okay"; 518 status = "okay";
519 519
520 codec: wm8962@1a { 520 codec: wm8962@1a {
521 compatible = "wlf,wm8962"; 521 compatible = "wlf,wm8962";
522 reg = <0x1a>; 522 reg = <0x1a>;
523 clocks = <&clks IMX6SX_CLK_AUDIO>; 523 clocks = <&clks IMX6SX_CLK_AUDIO>;
524 DCVDD-supply = <&vgen4_reg>; 524 DCVDD-supply = <&vgen4_reg>;
525 DBVDD-supply = <&vgen4_reg>; 525 DBVDD-supply = <&vgen4_reg>;
526 AVDD-supply = <&vgen4_reg>; 526 AVDD-supply = <&vgen4_reg>;
527 CPVDD-supply = <&vgen4_reg>; 527 CPVDD-supply = <&vgen4_reg>;
528 MICVDD-supply = <&vgen3_reg>; 528 MICVDD-supply = <&vgen3_reg>;
529 PLLVDD-supply = <&vgen4_reg>; 529 PLLVDD-supply = <&vgen4_reg>;
530 SPKVDD1-supply = <&reg_psu_5v>; 530 SPKVDD1-supply = <&reg_psu_5v>;
531 SPKVDD2-supply = <&reg_psu_5v>; 531 SPKVDD2-supply = <&reg_psu_5v>;
532 amic-mono; 532 amic-mono;
533 }; 533 };
534 }; 534 };
535 535
536 &lcdif1 { 536 &lcdif1 {
537 pinctrl-names = "default"; 537 pinctrl-names = "default";
538 pinctrl-0 = <&pinctrl_lcd>; 538 pinctrl-0 = <&pinctrl_lcd>;
539 lcd-supply = <&reg_lcd_3v3>; 539 lcd-supply = <&reg_lcd_3v3>;
540 display = <&display0>; 540 display = <&display0>;
541 status = "disabled"; 541 status = "disabled";
542 542
543 display0: display@0 { 543 display0: display@0 {
544 bits-per-pixel = <16>; 544 bits-per-pixel = <16>;
545 bus-width = <24>; 545 bus-width = <24>;
546 546
547 display-timings { 547 display-timings {
548 native-mode = <&timing0>; 548 native-mode = <&timing0>;
549 timing0: timing0 { 549 timing0: timing0 {
550 clock-frequency = <33500000>; 550 clock-frequency = <33500000>;
551 hactive = <800>; 551 hactive = <800>;
552 vactive = <480>; 552 vactive = <480>;
553 hback-porch = <89>; 553 hback-porch = <89>;
554 hfront-porch = <164>; 554 hfront-porch = <164>;
555 vback-porch = <23>; 555 vback-porch = <23>;
556 vfront-porch = <10>; 556 vfront-porch = <10>;
557 hsync-len = <10>; 557 hsync-len = <10>;
558 vsync-len = <10>; 558 vsync-len = <10>;
559 hsync-active = <0>; 559 hsync-active = <0>;
560 vsync-active = <0>; 560 vsync-active = <0>;
561 de-active = <1>; 561 de-active = <1>;
562 pixelclk-active = <0>; 562 pixelclk-active = <0>;
563 }; 563 };
564 }; 564 };
565 }; 565 };
566 }; 566 };
567 567
568 &pcie { 568 &pcie {
569 pinctrl-names = "default"; 569 pinctrl-names = "default";
570 pinctrl-0 = <&pinctrl_pcie>; 570 pinctrl-0 = <&pinctrl_pcie>;
571 reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>; 571 reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>;
572 status = "okay"; 572 status = "okay";
573 }; 573 };
574 574
575 &lcdif2 { 575 &lcdif2 {
576 display = <&display1>; 576 display = <&display1>;
577 disp-dev = "ldb"; 577 disp-dev = "ldb";
578 status = "okay"; 578 status = "okay";
579 display1: display@1 { 579 display1: display@1 {
580 bits-per-pixel = <16>; 580 bits-per-pixel = <16>;
581 bus-width = <18>; 581 bus-width = <18>;
582 }; 582 };
583 }; 583 };
584 &ldb { 584 &ldb {
585 status = "okay"; 585 status = "okay";
586 lvds-channel@0 { 586 lvds-channel@0 {
587 fsl,data-mapping = "spwg"; 587 fsl,data-mapping = "spwg";
588 fsl,data-width = <18>; 588 fsl,data-width = <18>;
589 crtc = "lcdif2"; 589 crtc = "lcdif2";
590 status = "okay"; 590 status = "okay";
591 display-timings { 591 display-timings {
592 native-mode = <&timing1>; 592 native-mode = <&timing1>;
593 timing1: hsd100pxn1 { 593 timing1: hsd100pxn1 {
594 clock-frequency = <65000000>; 594 clock-frequency = <65000000>;
595 hactive = <1024>; 595 hactive = <1024>;
596 vactive = <768>; 596 vactive = <768>;
597 hback-porch = <220>; 597 hback-porch = <220>;
598 hfront-porch = <40>; 598 hfront-porch = <40>;
599 vback-porch = <21>; 599 vback-porch = <21>;
600 vfront-porch = <7>; 600 vfront-porch = <7>;
601 hsync-len = <60>; 601 hsync-len = <60>;
602 vsync-len = <10>; 602 vsync-len = <10>;
603 }; 603 };
604 }; 604 };
605 }; 605 };
606 }; 606 };
607 607
608 &pwm3 { 608 &pwm3 {
609 pinctrl-names = "default"; 609 pinctrl-names = "default";
610 pinctrl-0 = <&pinctrl_pwm3>; 610 pinctrl-0 = <&pinctrl_pwm3>;
611 status = "okay"; 611 status = "okay";
612 }; 612 };
613 613
614 &pwm4 { 614 &pwm4 {
615 pinctrl-names = "default"; 615 pinctrl-names = "default";
616 pinctrl-0 = <&pinctrl_pwm4>; 616 pinctrl-0 = <&pinctrl_pwm4>;
617 status = "okay"; 617 status = "okay";
618 }; 618 };
619 619
620 &pxp { 620 &pxp {
621 status = "okay"; 621 status = "okay";
622 }; 622 };
623 623
624 &snvs_poweroff { 624 &snvs_poweroff {
625 status = "okay"; 625 status = "okay";
626 }; 626 };
627 627
628 &sai1 { 628 &sai1 {
629 pinctrl-names = "default"; 629 pinctrl-names = "default";
630 pinctrl-0 = <&pinctrl_sai1>; 630 pinctrl-0 = <&pinctrl_sai1>;
631 status = "disabled"; 631 status = "disabled";
632 }; 632 };
633 633
634 &spdif { 634 &spdif {
635 pinctrl-names = "default"; 635 pinctrl-names = "default";
636 pinctrl-0 = <&pinctrl_spdif>; 636 pinctrl-0 = <&pinctrl_spdif>;
637 status = "okay"; 637 status = "okay";
638 }; 638 };
639 639
640 &ssi2 { 640 &ssi2 {
641 assigned-clocks = <&clks IMX6SX_CLK_PLL4>, 641 assigned-clocks = <&clks IMX6SX_CLK_PLL4>,
642 <&clks IMX6SX_PLL4_BYPASS>, 642 <&clks IMX6SX_PLL4_BYPASS>,
643 <&clks IMX6SX_CLK_SSI2_SEL>; 643 <&clks IMX6SX_CLK_SSI2_SEL>;
644 assigned-clock-parents = <&clks IMX6SX_CLK_OSC>, 644 assigned-clock-parents = <&clks IMX6SX_CLK_OSC>,
645 <&clks IMX6SX_CLK_PLL4>, 645 <&clks IMX6SX_CLK_PLL4>,
646 <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>; 646 <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>;
647 assigned-clock-rates = <737280000>, <0>, <0>; 647 assigned-clock-rates = <737280000>, <0>, <0>;
648 status = "okay"; 648 status = "okay";
649 }; 649 };
650 650
651 &uart1 { 651 &uart1 {
652 pinctrl-names = "default"; 652 pinctrl-names = "default";
653 pinctrl-0 = <&pinctrl_uart1>; 653 pinctrl-0 = <&pinctrl_uart1>;
654 status = "okay"; 654 status = "okay";
655 }; 655 };
656 656
657 &uart5 { /* for bluetooth */ 657 &uart5 { /* for bluetooth */
658 pinctrl-names = "default"; 658 pinctrl-names = "default";
659 pinctrl-0 = <&pinctrl_uart5>; 659 pinctrl-0 = <&pinctrl_uart5>;
660 uart-has-rtscts; 660 uart-has-rtscts;
661 status = "okay"; 661 status = "okay";
662 /* for DTE mode, add below change */ 662 /* for DTE mode, add below change */
663 /* fsl,dte-mode;*/ 663 /* fsl,dte-mode;*/
664 /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ 664 /* pinctrl-0 = <&pinctrl_uart5dte_1>; */
665 }; 665 };
666 666
667 &usbotg1 { 667 &usbotg1 {
668 vbus-supply = <&reg_usb_otg1_vbus>; 668 vbus-supply = <&reg_usb_otg1_vbus>;
669 pinctrl-names = "default"; 669 pinctrl-names = "default";
670 pinctrl-0 = <&pinctrl_usb_otg1_id>; 670 pinctrl-0 = <&pinctrl_usb_otg1_id>;
671 srp-disable; 671 srp-disable;
672 hnp-disable; 672 hnp-disable;
673 adp-disable; 673 adp-disable;
674 status = "okay"; 674 status = "okay";
675 }; 675 };
676 676
677 &usbotg2 { 677 &usbotg2 {
678 vbus-supply = <&reg_usb_otg2_vbus>; 678 vbus-supply = <&reg_usb_otg2_vbus>;
679 dr_mode = "host"; 679 dr_mode = "host";
680 status = "okay"; 680 status = "okay";
681 }; 681 };
682 682
683 &usbphy1 { 683 &usbphy1 {
684 fsl,tx-d-cal = <106>; 684 fsl,tx-d-cal = <106>;
685 }; 685 };
686 686
687 &usbphy2 { 687 &usbphy2 {
688 fsl,tx-d-cal = <106>; 688 fsl,tx-d-cal = <106>;
689 }; 689 };
690 690
691 &usdhc2 { 691 &usdhc2 {
692 pinctrl-names = "default"; 692 pinctrl-names = "default";
693 pinctrl-0 = <&pinctrl_usdhc2>; 693 pinctrl-0 = <&pinctrl_usdhc2>;
694 non-removable; 694 non-removable;
695 no-1-8-v; 695 no-1-8-v;
696 keep-power-in-suspend; 696 keep-power-in-suspend;
697 wakeup-source; 697 wakeup-source;
698 status = "okay"; 698 status = "okay";
699 }; 699 };
700 700
701 &usdhc3 { 701 &usdhc3 {
702 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 702 pinctrl-names = "default", "state_100mhz", "state_200mhz";
703 pinctrl-0 = <&pinctrl_usdhc3>; 703 pinctrl-0 = <&pinctrl_usdhc3>;
704 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 704 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
705 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 705 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
706 bus-width = <8>; 706 bus-width = <8>;
707 cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 707 cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
708 wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 708 wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
709 keep-power-in-suspend; 709 keep-power-in-suspend;
710 wakeup-source; 710 wakeup-source;
711 vmmc-supply = <&vcc_sd3>; 711 vmmc-supply = <&vcc_sd3>;
712 status = "okay"; 712 status = "okay";
713 }; 713 };
714 714
715 &usdhc4 { 715 &usdhc4 {
716 pinctrl-names = "default"; 716 pinctrl-names = "default";
717 pinctrl-0 = <&pinctrl_usdhc4>; 717 pinctrl-0 = <&pinctrl_usdhc4>;
718 cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; 718 cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>;
719 wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; 719 wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
720 status = "okay"; 720 status = "okay";
721 }; 721 };
722 722
723 &wdog1 { 723 &wdog1 {
724 pinctrl-names = "default"; 724 pinctrl-names = "default";
725 pinctrl-0 = <&pinctrl_wdog>; 725 pinctrl-0 = <&pinctrl_wdog>;
726 fsl,ext-reset-output; 726 fsl,ext-reset-output;
727 }; 727 };
728 728
729 &iomuxc { 729 &iomuxc {
730 pinctrl-names = "default"; 730 pinctrl-names = "default";
731 pinctrl-0 = <&pinctrl_hog &pinctrl_can_gpios>; 731 pinctrl-0 = <&pinctrl_hog &pinctrl_can_gpios>;
732 732
733 imx6x-sdb { 733 imx6x-sdb {
734 pinctrl_hog: hoggrp { 734 pinctrl_hog: hoggrp {
735 fsl,pins = < 735 fsl,pins = <
736 MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059 736 MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059
737 MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000 737 MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000
738 MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059 738 MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059
739 >; 739 >;
740 }; 740 };
741 741
742 pinctrl_can_gpios: can-gpios { 742 pinctrl_can_gpios: can-gpios {
743 fsl,pins = < 743 fsl,pins = <
744 MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059 744 MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059
745 MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059 745 MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059
746 >; 746 >;
747 }; 747 };
748 748
749 pinctrl_audmux: audmuxgrp { 749 pinctrl_audmux: audmuxgrp {
750 fsl,pins = < 750 fsl,pins = <
751 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 751 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
752 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0 752 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
753 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0 753 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
754 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0 754 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
755 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 755 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
756 >; 756 >;
757 }; 757 };
758 758
759 pinctrl_csi_0: csigrp-0 { 759 pinctrl_csi_0: csigrp-0 {
760 fsl,pins = < 760 fsl,pins = <
761 MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 761 MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0
762 MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 762 MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0
763 MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 763 MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0
764 MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 764 MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0
765 MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 765 MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0
766 MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 766 MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0
767 MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 767 MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0
768 MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 768 MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0
769 MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 769 MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0
770 MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 770 MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0
771 MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 771 MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0
772 MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 772 MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0
773 MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 773 MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0
774 MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 774 MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0
775 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 775 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000
776 MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 776 MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000
777 >; 777 >;
778 }; 778 };
779 779
780 pinctrl_egalax_int: egalax_intgrp { 780 pinctrl_egalax_int: egalax_intgrp {
781 fsl,pins = < 781 fsl,pins = <
782 MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000 782 MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000
783 >; 783 >;
784 }; 784 };
785 785
786 pinctrl_enet1: enet1grp { 786 pinctrl_enet1: enet1grp {
787 fsl,pins = < 787 fsl,pins = <
788 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 788 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
789 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 789 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
790 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 790 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
791 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 791 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
792 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 792 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
793 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 793 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
794 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 794 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
795 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 795 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
796 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 796 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
797 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 797 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
798 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 798 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
799 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 799 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
800 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 800 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
801 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 801 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
802 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 802 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
803 >; 803 >;
804 }; 804 };
805 805
806 pinctrl_enet_3v3: enet3v3grp { 806 pinctrl_enet_3v3: enet3v3grp {
807 fsl,pins = < 807 fsl,pins = <
808 MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000 808 MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
809 >; 809 >;
810 }; 810 };
811 811
812 pinctrl_enet2: enet2grp { 812 pinctrl_enet2: enet2grp {
813 fsl,pins = < 813 fsl,pins = <
814 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 814 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
815 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 815 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
816 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 816 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
817 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 817 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
818 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 818 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
819 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 819 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
820 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 820 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
821 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 821 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
822 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 822 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
823 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 823 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
824 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 824 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
825 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 825 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
826 >; 826 >;
827 }; 827 };
828 828
829 pinctrl_flexcan1: flexcan1grp { 829 pinctrl_flexcan1: flexcan1grp {
830 fsl,pins = < 830 fsl,pins = <
831 MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 831 MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
832 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 832 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
833 >; 833 >;
834 }; 834 };
835 835
836 pinctrl_flexcan2: flexcan2grp { 836 pinctrl_flexcan2: flexcan2grp {
837 fsl,pins = < 837 fsl,pins = <
838 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 838 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
839 MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 839 MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020
840 >; 840 >;
841 }; 841 };
842 842
843 pinctrl_gpio_keys: gpio_keysgrp { 843 pinctrl_gpio_keys: gpio_keysgrp {
844 fsl,pins = < 844 fsl,pins = <
845 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 845 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
846 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059 846 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
847 >; 847 >;
848 }; 848 };
849 849
850 pinctrl_i2c1: i2c1grp { 850 pinctrl_i2c1: i2c1grp {
851 fsl,pins = < 851 fsl,pins = <
852 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 852 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
853 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 853 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
854 >; 854 >;
855 }; 855 };
856 856
857 pinctrl_i2c1_gpio: i2c1grp-gpio { 857 pinctrl_i2c1_gpio: i2c1grp-gpio {
858 fsl,pins = < 858 fsl,pins = <
859 MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x1b8b1 859 MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x1b8b1
860 MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x1b8b1 860 MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x1b8b1
861 >; 861 >;
862 }; 862 };
863 863
864 pinctrl_i2c2: i2c2grp { 864 pinctrl_i2c2: i2c2grp {
865 fsl,pins = < 865 fsl,pins = <
866 MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 866 MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
867 MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 867 MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
868 >; 868 >;
869 }; 869 };
870 870
871 pinctrl_i2c2_gpio: i2c2grp-gpio { 871 pinctrl_i2c2_gpio: i2c2grp-gpio {
872 fsl,pins = < 872 fsl,pins = <
873 MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1 873 MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1
874 MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1 874 MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1
875 >; 875 >;
876 }; 876 };
877 pinctrl_i2c3: i2c3grp { 877 pinctrl_i2c3: i2c3grp {
878 fsl,pins = < 878 fsl,pins = <
879 MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 879 MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
880 MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 880 MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
881 >; 881 >;
882 }; 882 };
883 883
884 pinctrl_i2c3_gpio: i2c3grp-gpio { 884 pinctrl_i2c3_gpio: i2c3grp-gpio {
885 fsl,pins = < 885 fsl,pins = <
886 MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x1b8b1 886 MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x1b8b1
887 MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1 887 MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1
888 >; 888 >;
889 }; 889 };
890 890
891 pinctrl_i2c4: i2c4grp { 891 pinctrl_i2c4: i2c4grp {
892 fsl,pins = < 892 fsl,pins = <
893 MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 893 MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
894 MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 894 MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
895 >; 895 >;
896 }; 896 };
897 897
898 pinctrl_i2c4_gpio: i2c4grp-gpio { 898 pinctrl_i2c4_gpio: i2c4grp-gpio {
899 fsl,pins = < 899 fsl,pins = <
900 MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x1b8b1 900 MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x1b8b1
901 MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x1b8b1 901 MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x1b8b1
902 >; 902 >;
903 }; 903 };
904 904
905 pinctrl_lcd: lcdgrp { 905 pinctrl_lcd: lcdgrp {
906 fsl,pins = < 906 fsl,pins = <
907 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 907 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
908 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 908 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
909 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 909 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
910 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 910 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
911 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 911 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
912 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 912 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
913 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 913 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
914 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 914 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
915 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 915 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
916 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 916 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
917 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 917 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
918 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 918 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
919 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 919 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
920 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 920 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
921 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 921 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
922 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 922 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
923 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 923 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
924 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 924 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
925 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 925 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
926 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 926 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
927 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 927 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
928 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 928 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
929 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 929 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
930 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 930 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
931 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 931 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
932 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 932 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
933 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 933 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
934 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 934 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
935 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 935 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
936 >; 936 >;
937 }; 937 };
938 938
939 pinctrl_mqs: mqsgrp { 939 pinctrl_mqs: mqsgrp {
940 fsl,pins = < 940 fsl,pins = <
941 MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0 941 MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0
942 MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0 942 MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0
943 >; 943 >;
944 }; 944 };
945 945
946 pinctrl_pcie: pciegrp { 946 pinctrl_pcie: pciegrp {
947 fsl,pins = < 947 fsl,pins = <
948 MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0 948 MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
949 >; 949 >;
950 }; 950 };
951 951
952 pinctrl_pcie_reg: pciereggrp { 952 pinctrl_pcie_reg: pciereggrp {
953 fsl,pins = < 953 fsl,pins = <
954 MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0 954 MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0
955 >; 955 >;
956 }; 956 };
957 957
958 pinctrl_peri_3v3: peri3v3grp { 958 pinctrl_peri_3v3: peri3v3grp {
959 fsl,pins = < 959 fsl,pins = <
960 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 960 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
961 >; 961 >;
962 }; 962 };
963 963
964 pinctrl_pwm3: pwm3grp-1 { 964 pinctrl_pwm3: pwm3grp-1 {
965 fsl,pins = < 965 fsl,pins = <
966 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 966 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
967 >; 967 >;
968 }; 968 };
969 969
970 pinctrl_pwm4: pwm4grp-1 { 970 pinctrl_pwm4: pwm4grp-1 {
971 fsl,pins = < 971 fsl,pins = <
972 MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 972 MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
973 >; 973 >;
974 }; 974 };
975 975
976 pinctrl_qspi2: qspi2grp { 976 pinctrl_qspi2: qspi2grp {
977 fsl,pins = < 977 fsl,pins = <
978 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 978 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
979 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1 979 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
980 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1 980 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
981 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1 981 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
982 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1 982 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
983 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1 983 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
984 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1 984 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
985 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1 985 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
986 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1 986 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
987 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1 987 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
988 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1 988 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
989 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1 989 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
990 >; 990 >;
991 }; 991 };
992 992
993 pinctrl_spdif: spdifgrp { 993 pinctrl_spdif: spdifgrp {
994 fsl,pins = < 994 fsl,pins = <
995 MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 995 MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0
996 >; 996 >;
997 }; 997 };
998 998
999 pinctrl_vcc_sd3: vccsd3grp { 999 pinctrl_vcc_sd3: vccsd3grp {
1000 fsl,pins = < 1000 fsl,pins = <
1001 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 1001 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
1002 >; 1002 >;
1003 }; 1003 };
1004 1004
1005 pinctrl_sai1: sai1grp { 1005 pinctrl_sai1: sai1grp {
1006 fsl,pins = < 1006 fsl,pins = <
1007 MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0 1007 MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0
1008 MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0 1008 MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0
1009 MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0 1009 MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0
1010 MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0 1010 MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0
1011 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 1011 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
1012 >; 1012 >;
1013 }; 1013 };
1014 1014
1015 pinctrl_uart1: uart1grp { 1015 pinctrl_uart1: uart1grp {
1016 fsl,pins = < 1016 fsl,pins = <
1017 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 1017 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
1018 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 1018 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
1019 >; 1019 >;
1020 }; 1020 };
1021 1021
1022 pinctrl_uart5: uart5grp { 1022 pinctrl_uart5: uart5grp {
1023 fsl,pins = < 1023 fsl,pins = <
1024 MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 1024 MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
1025 MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 1025 MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
1026 MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 1026 MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
1027 MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 1027 MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
1028 >; 1028 >;
1029 }; 1029 };
1030 1030
1031 pinctrl_uart5dte_1: uart5dtegrp-1 { 1031 pinctrl_uart5dte_1: uart5dtegrp-1 {
1032 fsl,pins = < 1032 fsl,pins = <
1033 MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 1033 MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1
1034 MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 1034 MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1
1035 MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 1035 MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1
1036 MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 1036 MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1
1037 >; 1037 >;
1038 }; 1038 };
1039 1039
1040 pinctrl_usb_otg1: usbotg1grp { 1040 pinctrl_usb_otg1: usbotg1grp {
1041 fsl,pins = < 1041 fsl,pins = <
1042 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 1042 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
1043 >; 1043 >;
1044 }; 1044 };
1045 1045
1046 pinctrl_usb_otg1_id: usbotg1idgrp { 1046 pinctrl_usb_otg1_id: usbotg1idgrp {
1047 fsl,pins = < 1047 fsl,pins = <
1048 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 1048 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
1049 >; 1049 >;
1050 }; 1050 };
1051 1051
1052 pinctrl_usb_otg2: usbot2ggrp { 1052 pinctrl_usb_otg2: usbot2ggrp {
1053 fsl,pins = < 1053 fsl,pins = <
1054 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 1054 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
1055 >; 1055 >;
1056 }; 1056 };
1057 1057
1058 pinctrl_usdhc2: usdhc2grp { 1058 pinctrl_usdhc2: usdhc2grp {
1059 fsl,pins = < 1059 fsl,pins = <
1060 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 1060 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
1061 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 1061 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
1062 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 1062 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
1063 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 1063 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
1064 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 1064 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
1065 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 1065 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
1066 >; 1066 >;
1067 }; 1067 };
1068 1068
1069 pinctrl_usdhc3: usdhc3grp { 1069 pinctrl_usdhc3: usdhc3grp {
1070 fsl,pins = < 1070 fsl,pins = <
1071 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17069 1071 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17069
1072 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071 1072 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071
1073 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17069 1073 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17069
1074 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17069 1074 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17069
1075 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17069 1075 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17069
1076 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17069 1076 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17069
1077 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17069 1077 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17069
1078 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17069 1078 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17069
1079 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17069 1079 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17069
1080 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17069 1080 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17069
1081 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ 1081 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
1082 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ 1082 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
1083 >; 1083 >;
1084 }; 1084 };
1085 1085
1086 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { 1086 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
1087 fsl,pins = < 1087 fsl,pins = <
1088 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 1088 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
1089 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 1089 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
1090 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 1090 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
1091 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 1091 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
1092 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 1092 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
1093 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 1093 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
1094 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 1094 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
1095 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 1095 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
1096 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 1096 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
1097 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 1097 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
1098 >; 1098 >;
1099 }; 1099 };
1100 1100
1101 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { 1101 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
1102 fsl,pins = < 1102 fsl,pins = <
1103 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 1103 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
1104 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 1104 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
1105 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 1105 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
1106 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 1106 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
1107 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 1107 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
1108 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 1108 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
1109 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 1109 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
1110 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 1110 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
1111 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 1111 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
1112 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 1112 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
1113 >; 1113 >;
1114 }; 1114 };
1115 1115
1116 pinctrl_usdhc4: usdhc4grp { 1116 pinctrl_usdhc4: usdhc4grp {
1117 fsl,pins = < 1117 fsl,pins = <
1118 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 1118 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
1119 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 1119 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
1120 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 1120 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
1121 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 1121 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
1122 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 1122 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
1123 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 1123 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
1124 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ 1124 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
1125 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ 1125 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
1126 >; 1126 >;
1127 }; 1127 };
1128 1128
1129 pinctrl_usdhc4_1: usdhc4grp-1 { 1129 pinctrl_usdhc4_1: usdhc4grp-1 {
1130 fsl,pins = < 1130 fsl,pins = <
1131 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 1131 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
1132 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 1132 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
1133 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 1133 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
1134 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 1134 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
1135 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 1135 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
1136 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 1136 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
1137 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 1137 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
1138 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 1138 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
1139 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 1139 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
1140 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 1140 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
1141 >; 1141 >;
1142 }; 1142 };
1143 1143
1144 pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { 1144 pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz {
1145 fsl,pins = < 1145 fsl,pins = <
1146 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 1146 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
1147 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 1147 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
1148 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 1148 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
1149 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 1149 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
1150 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 1150 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
1151 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 1151 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
1152 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 1152 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
1153 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 1153 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
1154 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 1154 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
1155 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 1155 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
1156 >; 1156 >;
1157 }; 1157 };
1158 1158
1159 pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { 1159 pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz {
1160 fsl,pins = < 1160 fsl,pins = <
1161 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 1161 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
1162 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 1162 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
1163 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 1163 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
1164 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 1164 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
1165 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 1165 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
1166 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 1166 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
1167 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 1167 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
1168 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 1168 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
1169 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 1169 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
1170 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 1170 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
1171 >; 1171 >;
1172 }; 1172 };
1173 1173
1174 pinctrl_wdog: wdoggrp { 1174 pinctrl_wdog: wdoggrp {
1175 fsl,pins = < 1175 fsl,pins = <
1176 MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 1176 MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
1177 >; 1177 >;
1178 }; 1178 };
1179 }; 1179 };
1180 }; 1180 };
1181 1181
1182 &vadc { 1182 &vadc {
1183 vadc_in = <0>; 1183 vadc_in = <0>;
1184 csi_id = <1>; 1184 csi_id = <1>;
1185 status = "okay"; 1185 status = "okay";
1186 port { 1186 port {
1187 vadc_ep: endpoint { 1187 vadc_ep: endpoint {
1188 remote-endpoint = <&csi2_ep>; 1188 remote-endpoint = <&csi2_ep>;
1189 }; 1189 };
1190 }; 1190 };
1191 }; 1191 };
1192 1192
arch/arm/dts/imx6ul-14x14-ddr3-arm2.dts
Diff comments   View file @ 4daafb3
1 /* 1 /*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/input/input.h>
12 #include "imx6ul.dtsi" 12 #include "imx6ul.dtsi"
13 13
14 / { 14 / {
15 model = "Freescale i.MX6 UltraLite DDR3 ARM2 Board"; 15 model = "Freescale i.MX6 UltraLite DDR3 ARM2 Board";
16 compatible = "fsl,imx6ul-14x14-ddr3-arm2", "fsl,imx6ul"; 16 compatible = "fsl,imx6ul-14x14-ddr3-arm2", "fsl,imx6ul";
17 17
18 chosen { 18 chosen {
19 stdout-path = &uart1; 19 stdout-path = &uart1;
20 }; 20 };
21 21
22 memory { 22 memory {
23 reg = <0x80000000 0x40000000>; 23 reg = <0x80000000 0x40000000>;
24 }; 24 };
25 25
26 reserved-memory { 26 reserved-memory {
27 #address-cells = <1>; 27 #address-cells = <1>;
28 #size-cells = <1>; 28 #size-cells = <1>;
29 ranges; 29 ranges;
30 30
31 linux,cma { 31 linux,cma {
32 compatible = "shared-dma-pool"; 32 compatible = "shared-dma-pool";
33 reusable; 33 reusable;
34 size = <0x14000000>; 34 size = <0x14000000>;
35 linux,cma-default; 35 linux,cma-default;
36 }; 36 };
37 }; 37 };
38 38
39 pxp_v4l2 { 39 pxp_v4l2 {
40 compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; 40 compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
41 status = "okay"; 41 status = "okay";
42 }; 42 };
43 43
44 regulators { 44 regulators {
45 compatible = "simple-bus"; 45 compatible = "simple-bus";
46 #address-cells = <1>; 46 #address-cells = <1>;
47 #size-cells = <0>; 47 #size-cells = <0>;
48 48
49 reg_sd1_vmmc: sd1_vmmc { 49 reg_sd1_vmmc: sd1_vmmc {
50 compatible = "regulator-fixed"; 50 compatible = "regulator-fixed";
51 regulator-name = "SD1_SPWR"; 51 regulator-name = "SD1_SPWR";
52 regulator-min-microvolt = <3000000>; 52 regulator-min-microvolt = <3000000>;
53 regulator-max-microvolt = <3000000>; 53 regulator-max-microvolt = <3000000>;
54 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 54 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
55 off-on-delay = <20000>; 55 u-boot,off-on-delay-us = <20000>;
56 enable-active-high; 56 enable-active-high;
57 }; 57 };
58 58
59 reg_sd2_vmmc: sd2_vmmc { 59 reg_sd2_vmmc: sd2_vmmc {
60 compatible = "regulator-fixed"; 60 compatible = "regulator-fixed";
61 regulator-name = "SD2_SPWR"; 61 regulator-name = "SD2_SPWR";
62 regulator-min-microvolt = <3000000>; 62 regulator-min-microvolt = <3000000>;
63 regulator-max-microvolt = <3000000>; 63 regulator-max-microvolt = <3000000>;
64 gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; 64 gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
65 off-on-delay = <20000>; 65 u-boot,off-on-delay-us = <20000>;
66 enable-active-high; 66 enable-active-high;
67 }; 67 };
68 68
69 reg_can2_3v3: regulator@0 { 69 reg_can2_3v3: regulator@0 {
70 compatible = "regulator-fixed"; 70 compatible = "regulator-fixed";
71 reg = <0>; 71 reg = <0>;
72 regulator-name = "can2-3v3"; 72 regulator-name = "can2-3v3";
73 regulator-min-microvolt = <3300000>; 73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>; 74 regulator-max-microvolt = <3300000>;
75 gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; 75 gpio = <&gpio1 15 GPIO_ACTIVE_LOW>;
76 }; 76 };
77 77
78 reg_vref_3v3: regulator@1 { 78 reg_vref_3v3: regulator@1 {
79 compatible = "regulator-fixed"; 79 compatible = "regulator-fixed";
80 regulator-name = "vref-3v3"; 80 regulator-name = "vref-3v3";
81 regulator-min-microvolt = <3300000>; 81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>; 82 regulator-max-microvolt = <3300000>;
83 }; 83 };
84 84
85 reg_usb_otg1_vbus: regulator@2 { 85 reg_usb_otg1_vbus: regulator@2 {
86 compatible = "regulator-fixed"; 86 compatible = "regulator-fixed";
87 reg = <2>; 87 reg = <2>;
88 pinctrl-names = "default"; 88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_usb_otg1>; 89 pinctrl-0 = <&pinctrl_usb_otg1>;
90 regulator-name = "usb_otg1_vbus"; 90 regulator-name = "usb_otg1_vbus";
91 regulator-min-microvolt = <5000000>; 91 regulator-min-microvolt = <5000000>;
92 regulator-max-microvolt = <5000000>; 92 regulator-max-microvolt = <5000000>;
93 gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; 93 gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
94 enable-active-high; 94 enable-active-high;
95 }; 95 };
96 }; 96 };
97 }; 97 };
98 98
99 &clks { 99 &clks {
100 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 100 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
101 assigned-clock-rates = <786432000>; 101 assigned-clock-rates = <786432000>;
102 }; 102 };
103 103
104 &cpu0 { 104 &cpu0 {
105 /* 105 /*
106 * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN, 106 * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN,
107 * to align with other platform and use the same cpufreq 107 * to align with other platform and use the same cpufreq
108 * driver, still use the seperated OPP define for arm 108 * driver, still use the seperated OPP define for arm
109 * and soc. 109 * and soc.
110 */ 110 */
111 operating-points = < 111 operating-points = <
112 /* kHz uV */ 112 /* kHz uV */
113 528000 1175000 113 528000 1175000
114 396000 1175000 114 396000 1175000
115 198000 1175000 115 198000 1175000
116 >; 116 >;
117 fsl,soc-operating-points = < 117 fsl,soc-operating-points = <
118 /* KHz uV */ 118 /* KHz uV */
119 528000 1175000 119 528000 1175000
120 396000 1175000 120 396000 1175000
121 198000 1175000 121 198000 1175000
122 >; 122 >;
123 fsl,arm-soc-shared = <1>; 123 fsl,arm-soc-shared = <1>;
124 }; 124 };
125 125
126 &reg_arm { 126 &reg_arm {
127 vin-supply = <&sw1a_reg>; 127 vin-supply = <&sw1a_reg>;
128 regulator-allow-bypass; 128 regulator-allow-bypass;
129 }; 129 };
130 130
131 &reg_soc { 131 &reg_soc {
132 vin-supply = <&sw1a_reg>; 132 vin-supply = <&sw1a_reg>;
133 regulator-allow-bypass; 133 regulator-allow-bypass;
134 }; 134 };
135 135
136 &ecspi1 { 136 &ecspi1 {
137 fsl,spi-num-chipselects = <1>; 137 fsl,spi-num-chipselects = <1>;
138 cs-gpios = <&gpio4 26 0>; 138 cs-gpios = <&gpio4 26 0>;
139 pinctrl-names = "default"; 139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; 140 pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>;
141 status = "okay"; 141 status = "okay";
142 142
143 flash: n25q032@0 { 143 flash: n25q032@0 {
144 #address-cells = <1>; 144 #address-cells = <1>;
145 #size-cells = <1>; 145 #size-cells = <1>;
146 compatible = "st,n25q032", "jedec,spi-nor"; 146 compatible = "st,n25q032", "jedec,spi-nor";
147 spi-max-frequency = <20000000>; 147 spi-max-frequency = <20000000>;
148 reg = <0>; 148 reg = <0>;
149 }; 149 };
150 }; 150 };
151 151
152 &fec1 { 152 &fec1 {
153 pinctrl-names = "default"; 153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_enet1>; 154 pinctrl-0 = <&pinctrl_enet1>;
155 phy-mode = "rmii"; 155 phy-mode = "rmii";
156 phy-handle = <&ethphy0>; 156 phy-handle = <&ethphy0>;
157 status = "okay"; 157 status = "okay";
158 }; 158 };
159 159
160 &fec2 { 160 &fec2 {
161 pinctrl-names = "default"; 161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_enet2>; 162 pinctrl-0 = <&pinctrl_enet2>;
163 phy-mode = "mii"; 163 phy-mode = "mii";
164 phy-handle = <&ethphy1>; 164 phy-handle = <&ethphy1>;
165 status = "okay"; 165 status = "okay";
166 166
167 mdio { 167 mdio {
168 #address-cells = <1>; 168 #address-cells = <1>;
169 #size-cells = <0>; 169 #size-cells = <0>;
170 170
171 ethphy0: ethernet-phy@1 { 171 ethphy0: ethernet-phy@1 {
172 compatible = "ethernet-phy-ieee802.3-c22"; 172 compatible = "ethernet-phy-ieee802.3-c22";
173 reg = <1>; 173 reg = <1>;
174 }; 174 };
175 175
176 ethphy1: ethernet-phy@2 { 176 ethphy1: ethernet-phy@2 {
177 compatible = "ethernet-phy-ieee802.3-c22"; 177 compatible = "ethernet-phy-ieee802.3-c22";
178 reg = <2>; 178 reg = <2>;
179 }; 179 };
180 }; 180 };
181 }; 181 };
182 182
183 &can2 { 183 &can2 {
184 pinctrl-names = "default"; 184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_flexcan2>; 185 pinctrl-0 = <&pinctrl_flexcan2>;
186 xceiver-supply = <&reg_can2_3v3>; 186 xceiver-supply = <&reg_can2_3v3>;
187 status = "disabled"; 187 status = "disabled";
188 }; 188 };
189 189
190 &gpc { 190 &gpc {
191 fsl,cpu_pupscr_sw2iso = <0xf>; 191 fsl,cpu_pupscr_sw2iso = <0xf>;
192 fsl,cpu_pupscr_sw = <0x0>; 192 fsl,cpu_pupscr_sw = <0x0>;
193 fsl,cpu_pdnscr_iso2sw = <0x1>; 193 fsl,cpu_pdnscr_iso2sw = <0x1>;
194 fsl,cpu_pdnscr_iso = <0x1>; 194 fsl,cpu_pdnscr_iso = <0x1>;
195 fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ 195 fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
196 }; 196 };
197 197
198 &gpmi { 198 &gpmi {
199 pinctrl-names = "default"; 199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_gpmi_nand_1>; 200 pinctrl-0 = <&pinctrl_gpmi_nand_1>;
201 status = "disabled"; 201 status = "disabled";
202 nand-on-flash-bbt; 202 nand-on-flash-bbt;
203 }; 203 };
204 204
205 &i2c1 { 205 &i2c1 {
206 clock-frequency = <100000>; 206 clock-frequency = <100000>;
207 pinctrl-names = "default", "gpio"; 207 pinctrl-names = "default", "gpio";
208 pinctrl-0 = <&pinctrl_i2c1>; 208 pinctrl-0 = <&pinctrl_i2c1>;
209 pinctrl-1 = <&pinctrl_i2c1_gpio>; 209 pinctrl-1 = <&pinctrl_i2c1_gpio>;
210 scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 210 scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
211 sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 211 sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
212 status = "okay"; 212 status = "okay";
213 213
214 pmic: pfuze100@08 { 214 pmic: pfuze100@08 {
215 compatible = "fsl,pfuze200"; 215 compatible = "fsl,pfuze200";
216 reg = <0x08>; 216 reg = <0x08>;
217 217
218 regulators { 218 regulators {
219 sw1a_reg: sw1ab { 219 sw1a_reg: sw1ab {
220 regulator-min-microvolt = <300000>; 220 regulator-min-microvolt = <300000>;
221 regulator-max-microvolt = <1875000>; 221 regulator-max-microvolt = <1875000>;
222 regulator-always-on; 222 regulator-always-on;
223 regulator-ramp-delay = <6250>; 223 regulator-ramp-delay = <6250>;
224 }; 224 };
225 225
226 sw2_reg: sw2 { 226 sw2_reg: sw2 {
227 regulator-min-microvolt = <800000>; 227 regulator-min-microvolt = <800000>;
228 regulator-max-microvolt = <3300000>; 228 regulator-max-microvolt = <3300000>;
229 regulator-always-on; 229 regulator-always-on;
230 }; 230 };
231 231
232 sw3a_reg: sw3a { 232 sw3a_reg: sw3a {
233 regulator-min-microvolt = <400000>; 233 regulator-min-microvolt = <400000>;
234 regulator-max-microvolt = <1975000>; 234 regulator-max-microvolt = <1975000>;
235 regulator-always-on; 235 regulator-always-on;
236 }; 236 };
237 237
238 sw3b_reg: sw3b { 238 sw3b_reg: sw3b {
239 regulator-min-microvolt = <800000>; 239 regulator-min-microvolt = <800000>;
240 regulator-max-microvolt = <3300000>; 240 regulator-max-microvolt = <3300000>;
241 regulator-always-on; 241 regulator-always-on;
242 }; 242 };
243 243
244 swbst_reg: swbst { 244 swbst_reg: swbst {
245 regulator-min-microvolt = <5000000>; 245 regulator-min-microvolt = <5000000>;
246 regulator-max-microvolt = <5150000>; 246 regulator-max-microvolt = <5150000>;
247 }; 247 };
248 248
249 snvs_reg: vsnvs { 249 snvs_reg: vsnvs {
250 regulator-min-microvolt = <1000000>; 250 regulator-min-microvolt = <1000000>;
251 regulator-max-microvolt = <3000000>; 251 regulator-max-microvolt = <3000000>;
252 regulator-always-on; 252 regulator-always-on;
253 }; 253 };
254 254
255 vref_reg: vrefddr { 255 vref_reg: vrefddr {
256 regulator-always-on; 256 regulator-always-on;
257 }; 257 };
258 258
259 vgen1_reg: vgen1 { 259 vgen1_reg: vgen1 {
260 regulator-min-microvolt = <800000>; 260 regulator-min-microvolt = <800000>;
261 regulator-max-microvolt = <1550000>; 261 regulator-max-microvolt = <1550000>;
262 }; 262 };
263 263
264 vgen2_reg: vgen2 { 264 vgen2_reg: vgen2 {
265 regulator-min-microvolt = <800000>; 265 regulator-min-microvolt = <800000>;
266 regulator-max-microvolt = <1550000>; 266 regulator-max-microvolt = <1550000>;
267 }; 267 };
268 268
269 vgen3_reg: vgen3 { 269 vgen3_reg: vgen3 {
270 regulator-min-microvolt = <1800000>; 270 regulator-min-microvolt = <1800000>;
271 regulator-max-microvolt = <3300000>; 271 regulator-max-microvolt = <3300000>;
272 }; 272 };
273 273
274 vgen4_reg: vgen4 { 274 vgen4_reg: vgen4 {
275 regulator-min-microvolt = <1800000>; 275 regulator-min-microvolt = <1800000>;
276 regulator-max-microvolt = <3300000>; 276 regulator-max-microvolt = <3300000>;
277 regulator-always-on; 277 regulator-always-on;
278 }; 278 };
279 279
280 vgen5_reg: vgen5 { 280 vgen5_reg: vgen5 {
281 regulator-min-microvolt = <1800000>; 281 regulator-min-microvolt = <1800000>;
282 regulator-max-microvolt = <3300000>; 282 regulator-max-microvolt = <3300000>;
283 regulator-always-on; 283 regulator-always-on;
284 }; 284 };
285 285
286 vgen6_reg: vgen6 { 286 vgen6_reg: vgen6 {
287 regulator-min-microvolt = <1800000>; 287 regulator-min-microvolt = <1800000>;
288 regulator-max-microvolt = <3300000>; 288 regulator-max-microvolt = <3300000>;
289 regulator-always-on; 289 regulator-always-on;
290 }; 290 };
291 }; 291 };
292 }; 292 };
293 }; 293 };
294 294
295 &iomuxc { 295 &iomuxc {
296 pinctrl-names = "default"; 296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_hog &pinctrl_hog1 &pinctrl_hog_sd>; 297 pinctrl-0 = <&pinctrl_hog &pinctrl_hog1 &pinctrl_hog_sd>;
298 298
299 imx6ul-ddr3-arm2 { 299 imx6ul-ddr3-arm2 {
300 pinctrl_hog: hoggrp { 300 pinctrl_hog: hoggrp {
301 fsl,pins = < 301 fsl,pins = <
302 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ 302 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
303 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 /* SD1 WP */ 303 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 /* SD1 WP */
304 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ 304 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
305 MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x17059 /* SD2 CD */ 305 MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x17059 /* SD2 CD */
306 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x17059 /* SD2 WP */ 306 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x17059 /* SD2 WP */
307 >; 307 >;
308 }; 308 };
309 309
310 pinctrl_hog1: hoggrp1 { 310 pinctrl_hog1: hoggrp1 {
311 fsl,pins = < 311 fsl,pins = <
312 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESECT */ 312 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESECT */
313 >; 313 >;
314 }; 314 };
315 315
316 pinctrl_hog_sd: hoggrp_sd { 316 pinctrl_hog_sd: hoggrp_sd {
317 fsl,pins = < 317 fsl,pins = <
318 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ 318 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
319 MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x17059 /* SD2 VSELECT */ 319 MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x17059 /* SD2 VSELECT */
320 >; 320 >;
321 }; 321 };
322 322
323 pinctrl_adc1: adc1grp { 323 pinctrl_adc1: adc1grp {
324 fsl,pins = < 324 fsl,pins = <
325 MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 325 MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0
326 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 326 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
327 >; 327 >;
328 }; 328 };
329 329
330 pinctrl_bt: btgrp { 330 pinctrl_bt: btgrp {
331 fsl,pins = < 331 fsl,pins = <
332 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x80000000 332 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x80000000
333 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x80000000 333 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x80000000
334 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x80000000 334 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x80000000
335 >; 335 >;
336 }; 336 };
337 337
338 pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { 338 pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 {
339 fsl,pins = < 339 fsl,pins = <
340 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 340 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0
341 >; 341 >;
342 }; 342 };
343 343
344 pinctrl_ecspi1_1: ecspi1grp-1 { 344 pinctrl_ecspi1_1: ecspi1grp-1 {
345 fsl,pins = < 345 fsl,pins = <
346 MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x10b0 346 MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x10b0
347 MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x10b0 347 MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x10b0
348 MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x10b0 348 MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x10b0
349 >; 349 >;
350 }; 350 };
351 351
352 pinctrl_enet1: enet1grp { 352 pinctrl_enet1: enet1grp {
353 fsl,pins = < 353 fsl,pins = <
354 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 354 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
355 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 355 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
356 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 356 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
357 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 357 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
358 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 358 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
359 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 359 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
360 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 360 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
361 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8 361 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8
362 >; 362 >;
363 }; 363 };
364 364
365 pinctrl_enet2: enet2grp { 365 pinctrl_enet2: enet2grp {
366 fsl,pins = < 366 fsl,pins = <
367 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 367 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
368 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 368 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
369 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 369 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
370 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 370 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
371 MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x1b0b0 371 MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x1b0b0
372 MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x1b0b0 372 MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x1b0b0
373 MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x4001b0a8 373 MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x4001b0a8
374 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 374 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
375 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 375 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
376 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 376 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
377 MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x1b0b0 377 MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x1b0b0
378 MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x1b0b0 378 MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x1b0b0
379 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 379 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
380 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 380 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
381 MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8 381 MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8
382 MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0 382 MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0
383 MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0 383 MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0
384 >; 384 >;
385 }; 385 };
386 386
387 pinctrl_flexcan2: flexcan2grp{ 387 pinctrl_flexcan2: flexcan2grp{
388 fsl,pins = < 388 fsl,pins = <
389 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 389 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
390 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 390 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
391 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */ 391 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */
392 >; 392 >;
393 }; 393 };
394 394
395 pinctrl_gpmi_nand_1: gpmi-nand-1 { 395 pinctrl_gpmi_nand_1: gpmi-nand-1 {
396 fsl,pins = < 396 fsl,pins = <
397 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 397 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
398 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 398 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
399 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 399 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
400 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 400 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
401 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 401 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
402 MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 402 MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
403 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 403 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
404 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 404 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
405 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 405 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
406 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 406 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
407 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 407 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
408 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 408 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
409 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 409 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
410 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 410 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
411 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 411 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
412 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 412 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
413 >; 413 >;
414 }; 414 };
415 415
416 pinctrl_i2c1: i2c1grp { 416 pinctrl_i2c1: i2c1grp {
417 fsl,pins = < 417 fsl,pins = <
418 MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1 418 MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1
419 MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1 419 MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1
420 >; 420 >;
421 }; 421 };
422 422
423 pinctrl_i2c1_gpio: i2c1grp_gpio { 423 pinctrl_i2c1_gpio: i2c1grp_gpio {
424 fsl,pins = < 424 fsl,pins = <
425 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x1b8b1 425 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x1b8b1
426 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b8b1 426 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b8b1
427 >; 427 >;
428 }; 428 };
429 429
430 pinctrl_i2c4: i2c4grp { 430 pinctrl_i2c4: i2c4grp {
431 fsl,pins = < 431 fsl,pins = <
432 MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0 432 MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0
433 MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0 433 MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0
434 >; 434 >;
435 }; 435 };
436 436
437 pinctrl_lcdif_dat: lcdifdatgrp { 437 pinctrl_lcdif_dat: lcdifdatgrp {
438 fsl,pins = < 438 fsl,pins = <
439 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 439 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
440 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 440 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
441 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 441 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
442 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 442 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
443 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 443 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
444 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 444 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
445 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 445 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
446 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 446 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
447 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 447 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
448 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 448 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
449 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 449 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
450 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 450 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
451 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 451 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
452 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 452 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
453 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 453 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
454 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 454 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
455 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 455 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
456 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 456 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
457 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 457 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
458 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 458 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
459 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 459 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
460 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 460 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
461 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 461 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
462 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 462 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
463 >; 463 >;
464 }; 464 };
465 465
466 pinctrl_lcdif_ctrl: lcdifctrlgrp { 466 pinctrl_lcdif_ctrl: lcdifctrlgrp {
467 fsl,pins = < 467 fsl,pins = <
468 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 468 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
469 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 469 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
470 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 470 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
471 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 471 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
472 MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 472 MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79
473 >; 473 >;
474 }; 474 };
475 475
476 pinctrl_mqs: mqsgrp { 476 pinctrl_mqs: mqsgrp {
477 fsl,pins = < 477 fsl,pins = <
478 MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x11088 478 MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x11088
479 MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x11088 479 MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x11088
480 >; 480 >;
481 }; 481 };
482 482
483 pinctrl_pwm1: pmw1grp { 483 pinctrl_pwm1: pmw1grp {
484 fsl,pins = < 484 fsl,pins = <
485 MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x110b0 485 MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x110b0
486 >; 486 >;
487 }; 487 };
488 488
489 pinctrl_qspi: qspigrp { 489 pinctrl_qspi: qspigrp {
490 fsl,pins = < 490 fsl,pins = <
491 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 491 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
492 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 492 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
493 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 493 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
494 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 494 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
495 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 495 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
496 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 496 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
497 MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1 497 MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1
498 MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1 498 MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1
499 MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1 499 MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1
500 MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1 500 MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1
501 MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1 501 MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1
502 MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1 502 MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1
503 MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1 503 MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1
504 MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1 504 MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1
505 >; 505 >;
506 }; 506 };
507 507
508 pinctrl_sai2: sai2grp { 508 pinctrl_sai2: sai2grp {
509 fsl,pins = < 509 fsl,pins = <
510 MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x1b0b0 510 MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x1b0b0
511 MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x1b0b0 511 MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x1b0b0
512 MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x110b0 512 MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x110b0
513 MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x1f0b8 513 MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x1f0b8
514 MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x1b0b0 514 MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x1b0b0
515 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 515 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059
516 >; 516 >;
517 }; 517 };
518 518
519 pinctrl_spdif: spdifgrp { 519 pinctrl_spdif: spdifgrp {
520 fsl,pins = < 520 fsl,pins = <
521 MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x1b0b0 521 MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x1b0b0
522 MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x1b0b0 522 MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x1b0b0
523 >; 523 >;
524 }; 524 };
525 525
526 pinctrl_tsc: tscgrp { 526 pinctrl_tsc: tscgrp {
527 fsl,pins = < 527 fsl,pins = <
528 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 528 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
529 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 529 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
530 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 530 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
531 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 531 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
532 >; 532 >;
533 }; 533 };
534 534
535 pinctrl_uart1: uart1grp { 535 pinctrl_uart1: uart1grp {
536 fsl,pins = < 536 fsl,pins = <
537 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 537 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
538 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 538 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
539 >; 539 >;
540 }; 540 };
541 541
542 pinctrl_uart2: uart2grp { 542 pinctrl_uart2: uart2grp {
543 fsl,pins = < 543 fsl,pins = <
544 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 544 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
545 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 545 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
546 MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 546 MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
547 MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 547 MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
548 >; 548 >;
549 }; 549 };
550 550
551 pinctrl_uart2dte: uart2dtegrp { 551 pinctrl_uart2dte: uart2dtegrp {
552 fsl,pins = < 552 fsl,pins = <
553 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 553 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
554 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 554 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
555 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 555 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1
556 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 556 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1
557 >; 557 >;
558 }; 558 };
559 559
560 pinctrl_usb_otg1_id: usbotg1idgrp { 560 pinctrl_usb_otg1_id: usbotg1idgrp {
561 fsl,pins = < 561 fsl,pins = <
562 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 562 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
563 >; 563 >;
564 }; 564 };
565 565
566 pinctrl_usb_otg1: usbotg1grp { 566 pinctrl_usb_otg1: usbotg1grp {
567 fsl,pins = < 567 fsl,pins = <
568 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0 568 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0
569 >; 569 >;
570 }; 570 };
571 571
572 pinctrl_usdhc1: usdhc1grp { 572 pinctrl_usdhc1: usdhc1grp {
573 fsl,pins = < 573 fsl,pins = <
574 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 574 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
575 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 575 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
576 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 576 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
577 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 577 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
578 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 578 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
579 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 579 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
580 >; 580 >;
581 }; 581 };
582 582
583 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 583 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
584 fsl,pins = < 584 fsl,pins = <
585 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 585 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
586 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 586 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
587 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 587 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
588 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 588 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
589 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 589 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
590 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 590 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
591 >; 591 >;
592 }; 592 };
593 593
594 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 594 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
595 fsl,pins = < 595 fsl,pins = <
596 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 596 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
597 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 597 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
598 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 598 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
599 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 599 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
600 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 600 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
601 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 601 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
602 >; 602 >;
603 }; 603 };
604 604
605 pinctrl_usdhc1_8bit: usdhc1_8bit_grp { 605 pinctrl_usdhc1_8bit: usdhc1_8bit_grp {
606 fsl,pins = < 606 fsl,pins = <
607 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 607 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
608 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 608 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
609 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 609 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
610 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 610 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
611 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 611 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
612 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 612 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
613 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 613 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
614 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 614 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
615 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 615 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
616 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 616 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
617 >; 617 >;
618 }; 618 };
619 619
620 pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp { 620 pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp {
621 fsl,pins = < 621 fsl,pins = <
622 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 622 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
623 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 623 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
624 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 624 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
625 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 625 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
626 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 626 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
627 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 627 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
628 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9 628 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9
629 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9 629 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9
630 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9 630 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9
631 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9 631 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9
632 >; 632 >;
633 }; 633 };
634 634
635 pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp { 635 pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp {
636 fsl,pins = < 636 fsl,pins = <
637 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 637 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
638 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 638 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
639 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 639 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
640 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 640 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
641 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 641 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
642 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 642 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
643 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9 643 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9
644 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9 644 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9
645 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9 645 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9
646 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9 646 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9
647 >; 647 >;
648 }; 648 };
649 649
650 pinctrl_usdhc2: usdhc2grp { 650 pinctrl_usdhc2: usdhc2grp {
651 fsl,pins = < 651 fsl,pins = <
652 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 652 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
653 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059 653 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059
654 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 654 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
655 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 655 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
656 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 656 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
657 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 657 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
658 >; 658 >;
659 }; 659 };
660 660
661 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 661 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
662 fsl,pins = < 662 fsl,pins = <
663 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170b9 663 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170b9
664 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100b9 664 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100b9
665 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170b9 665 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170b9
666 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170b9 666 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170b9
667 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170b9 667 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170b9
668 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170b9 668 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170b9
669 >; 669 >;
670 }; 670 };
671 671
672 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 672 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
673 fsl,pins = < 673 fsl,pins = <
674 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170f9 674 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170f9
675 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100f9 675 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100f9
676 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170f9 676 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170f9
677 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170f9 677 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170f9
678 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170f9 678 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170f9
679 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170f9 679 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170f9
680 >; 680 >;
681 }; 681 };
682 }; 682 };
683 }; 683 };
684 684
685 &pxp { 685 &pxp {
686 status = "okay"; 686 status = "okay";
687 }; 687 };
688 688
689 &qspi { 689 &qspi {
690 pinctrl-names = "default"; 690 pinctrl-names = "default";
691 pinctrl-0 = <&pinctrl_qspi>; 691 pinctrl-0 = <&pinctrl_qspi>;
692 status = "okay"; 692 status = "okay";
693 fsl,qspi-has-second-chip = <1>; 693 fsl,qspi-has-second-chip = <1>;
694 ddrsmp=<0>; 694 ddrsmp=<0>;
695 695
696 flash0: n25q256a@0 { 696 flash0: n25q256a@0 {
697 #address-cells = <1>; 697 #address-cells = <1>;
698 #size-cells = <1>; 698 #size-cells = <1>;
699 compatible = "micron,n25q256a", "jedec,spi-nor"; 699 compatible = "micron,n25q256a", "jedec,spi-nor";
700 spi-max-frequency = <29000000>; 700 spi-max-frequency = <29000000>;
701 spi-nor,ddr-quad-read-dummy = <6>; 701 spi-nor,ddr-quad-read-dummy = <6>;
702 reg = <0>; 702 reg = <0>;
703 }; 703 };
704 704
705 flash1: n25q256a@1 { 705 flash1: n25q256a@1 {
706 #address-cells = <1>; 706 #address-cells = <1>;
707 #size-cells = <1>; 707 #size-cells = <1>;
708 compatible = "micron,n25q256a", "jedec,spi-nor"; 708 compatible = "micron,n25q256a", "jedec,spi-nor";
709 spi-max-frequency = <29000000>; 709 spi-max-frequency = <29000000>;
710 spi-nor,ddr-quad-read-dummy = <6>; 710 spi-nor,ddr-quad-read-dummy = <6>;
711 reg = <1>; 711 reg = <1>;
712 }; 712 };
713 713
714 flash2: n25q256a@2 { 714 flash2: n25q256a@2 {
715 #address-cells = <1>; 715 #address-cells = <1>;
716 #size-cells = <1>; 716 #size-cells = <1>;
717 compatible = "micron,n25q256a", "jedec,spi-nor"; 717 compatible = "micron,n25q256a", "jedec,spi-nor";
718 spi-max-frequency = <29000000>; 718 spi-max-frequency = <29000000>;
719 spi-nor,ddr-quad-read-dummy = <6>; 719 spi-nor,ddr-quad-read-dummy = <6>;
720 reg = <2>; 720 reg = <2>;
721 }; 721 };
722 722
723 flash3: n25q256a@3 { 723 flash3: n25q256a@3 {
724 #address-cells = <1>; 724 #address-cells = <1>;
725 #size-cells = <1>; 725 #size-cells = <1>;
726 compatible = "micron,n25q256a", "jedec,spi-nor"; 726 compatible = "micron,n25q256a", "jedec,spi-nor";
727 spi-max-frequency = <29000000>; 727 spi-max-frequency = <29000000>;
728 spi-nor,ddr-quad-read-dummy = <6>; 728 spi-nor,ddr-quad-read-dummy = <6>;
729 reg = <3>; 729 reg = <3>;
730 }; 730 };
731 }; 731 };
732 732
733 &uart1 { 733 &uart1 {
734 pinctrl-names = "default"; 734 pinctrl-names = "default";
735 pinctrl-0 = <&pinctrl_uart1>; 735 pinctrl-0 = <&pinctrl_uart1>;
736 status = "okay"; 736 status = "okay";
737 }; 737 };
738 738
739 &uart2 { 739 &uart2 {
740 pinctrl-names = "default"; 740 pinctrl-names = "default";
741 pinctrl-0 = <&pinctrl_uart2 741 pinctrl-0 = <&pinctrl_uart2
742 &pinctrl_bt>; 742 &pinctrl_bt>;
743 fsl,uart-has-rtscts; 743 fsl,uart-has-rtscts;
744 /* for DTE mode, add below change */ 744 /* for DTE mode, add below change */
745 /* fsl,dte-mode; */ 745 /* fsl,dte-mode; */
746 /* pinctrl-0 = <&pinctrl_uart2dte>; */ 746 /* pinctrl-0 = <&pinctrl_uart2dte>; */
747 status = "okay"; 747 status = "okay";
748 }; 748 };
749 749
750 &usbotg1 { 750 &usbotg1 {
751 vbus-supply = <&reg_usb_otg1_vbus>; 751 vbus-supply = <&reg_usb_otg1_vbus>;
752 pinctrl-names = "default"; 752 pinctrl-names = "default";
753 pinctrl-0 = <&pinctrl_usb_otg1_id>; 753 pinctrl-0 = <&pinctrl_usb_otg1_id>;
754 srp-disable; 754 srp-disable;
755 hnp-disable; 755 hnp-disable;
756 adp-disable; 756 adp-disable;
757 status = "okay"; 757 status = "okay";
758 }; 758 };
759 759
760 &usdhc1 { 760 &usdhc1 {
761 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 761 pinctrl-names = "default", "state_100mhz", "state_200mhz";
762 pinctrl-0 = <&pinctrl_usdhc1>; 762 pinctrl-0 = <&pinctrl_usdhc1>;
763 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 763 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
764 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 764 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
765 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 765 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
766 wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; 766 wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
767 keep-power-in-suspend; 767 keep-power-in-suspend;
768 enable-sdio-wakeup; 768 enable-sdio-wakeup;
769 vmmc-supply = <&reg_sd1_vmmc>; 769 vmmc-supply = <&reg_sd1_vmmc>;
770 status = "okay"; 770 status = "okay";
771 }; 771 };
772 772
773 &usdhc2 { 773 &usdhc2 {
774 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 774 pinctrl-names = "default", "state_100mhz", "state_200mhz";
775 pinctrl-0 = <&pinctrl_usdhc2>; 775 pinctrl-0 = <&pinctrl_usdhc2>;
776 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 776 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
777 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 777 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
778 cd-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; 778 cd-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
779 wp-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; 779 wp-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
780 keep-power-in-suspend; 780 keep-power-in-suspend;
781 enable-sdio-wakeup; 781 enable-sdio-wakeup;
782 vmmc-supply = <&reg_sd2_vmmc>; 782 vmmc-supply = <&reg_sd2_vmmc>;
783 status = "okay"; 783 status = "okay";
784 }; 784 };
785 785
arch/arm/dts/imx6ul-14x14-evk.dts
Diff comments   View file @ 4daafb3
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP 4 * Copyright 2017-2018 NXP
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include "imx6ul.dtsi" 9 #include "imx6ul.dtsi"
10 10
11 / { 11 / {
12 model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; 12 model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
13 compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; 13 compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
14 14
15 aliases { 15 aliases {
16 spi5 = &soft_spi; 16 spi5 = &soft_spi;
17 }; 17 };
18 18
19 chosen { 19 chosen {
20 stdout-path = &uart1; 20 stdout-path = &uart1;
21 }; 21 };
22 22
23 memory { 23 memory {
24 reg = <0x80000000 0x20000000>; 24 reg = <0x80000000 0x20000000>;
25 }; 25 };
26 26
27 reserved-memory { 27 reserved-memory {
28 #address-cells = <1>; 28 #address-cells = <1>;
29 #size-cells = <1>; 29 #size-cells = <1>;
30 ranges; 30 ranges;
31 31
32 linux,cma { 32 linux,cma {
33 compatible = "shared-dma-pool"; 33 compatible = "shared-dma-pool";
34 reusable; 34 reusable;
35 size = <0x14000000>; 35 size = <0x14000000>;
36 linux,cma-default; 36 linux,cma-default;
37 }; 37 };
38 }; 38 };
39 39
40 backlight { 40 backlight {
41 compatible = "pwm-backlight"; 41 compatible = "pwm-backlight";
42 pwms = <&pwm1 0 5000000>; 42 pwms = <&pwm1 0 5000000>;
43 brightness-levels = <0 4 8 16 32 64 128 255>; 43 brightness-levels = <0 4 8 16 32 64 128 255>;
44 default-brightness-level = <6>; 44 default-brightness-level = <6>;
45 status = "okay"; 45 status = "okay";
46 }; 46 };
47 47
48 pxp_v4l2 { 48 pxp_v4l2 {
49 compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; 49 compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
50 status = "okay"; 50 status = "okay";
51 }; 51 };
52 52
53 regulators { 53 regulators {
54 compatible = "simple-bus"; 54 compatible = "simple-bus";
55 #address-cells = <1>; 55 #address-cells = <1>;
56 #size-cells = <0>; 56 #size-cells = <0>;
57 57
58 reg_sd1_vmmc: regulator@1 { 58 reg_sd1_vmmc: regulator@1 {
59 compatible = "regulator-fixed"; 59 compatible = "regulator-fixed";
60 regulator-name = "VSD_3V3"; 60 regulator-name = "VSD_3V3";
61 regulator-min-microvolt = <3300000>; 61 regulator-min-microvolt = <3300000>;
62 regulator-max-microvolt = <3300000>; 62 regulator-max-microvolt = <3300000>;
63 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 63 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
64 off-on-delay = <20000>; 64 u-boot,off-on-delay-us = <20000>;
65 enable-active-high; 65 enable-active-high;
66 }; 66 };
67 67
68 reg_can_3v3: regulator@0 { 68 reg_can_3v3: regulator@0 {
69 compatible = "regulator-fixed"; 69 compatible = "regulator-fixed";
70 reg = <0>; 70 reg = <0>;
71 regulator-name = "can-3v3"; 71 regulator-name = "can-3v3";
72 regulator-min-microvolt = <3300000>; 72 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <3300000>; 73 regulator-max-microvolt = <3300000>;
74 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; 74 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
75 }; 75 };
76 76
77 reg_gpio_dvfs: regulator-gpio { 77 reg_gpio_dvfs: regulator-gpio {
78 compatible = "regulator-gpio"; 78 compatible = "regulator-gpio";
79 pinctrl-names = "default"; 79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_dvfs>; 80 pinctrl-0 = <&pinctrl_dvfs>;
81 regulator-min-microvolt = <1300000>; 81 regulator-min-microvolt = <1300000>;
82 regulator-max-microvolt = <1400000>; 82 regulator-max-microvolt = <1400000>;
83 regulator-name = "gpio_dvfs"; 83 regulator-name = "gpio_dvfs";
84 regulator-type = "voltage"; 84 regulator-type = "voltage";
85 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 85 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
86 states = <1300000 0x1 1400000 0x0>; 86 states = <1300000 0x1 1400000 0x0>;
87 }; 87 };
88 }; 88 };
89 89
90 sound: sound { 90 sound: sound {
91 compatible = "fsl,imx6ul-evk-wm8960", 91 compatible = "fsl,imx6ul-evk-wm8960",
92 "fsl,imx-audio-wm8960"; 92 "fsl,imx-audio-wm8960";
93 model = "wm8960-audio"; 93 model = "wm8960-audio";
94 cpu-dai = <&sai2>; 94 cpu-dai = <&sai2>;
95 audio-codec = <&codec>; 95 audio-codec = <&codec>;
96 asrc-controller = <&asrc>; 96 asrc-controller = <&asrc>;
97 codec-master; 97 codec-master;
98 gpr = <&gpr 4 0x100000 0x100000>; 98 gpr = <&gpr 4 0x100000 0x100000>;
99 /* 99 /*
100 * hp-det = <hp-det-pin hp-det-polarity>; 100 * hp-det = <hp-det-pin hp-det-polarity>;
101 * hp-det-pin: JD1 JD2 or JD3 101 * hp-det-pin: JD1 JD2 or JD3
102 * hp-det-polarity = 0: hp detect high for headphone 102 * hp-det-polarity = 0: hp detect high for headphone
103 * hp-det-polarity = 1: hp detect high for speaker 103 * hp-det-polarity = 1: hp detect high for speaker
104 */ 104 */
105 hp-det = <3 0>; 105 hp-det = <3 0>;
106 hp-det-gpios = <&gpio5 4 0>; 106 hp-det-gpios = <&gpio5 4 0>;
107 mic-det-gpios = <&gpio5 4 0>; 107 mic-det-gpios = <&gpio5 4 0>;
108 audio-routing = 108 audio-routing =
109 "Headphone Jack", "HP_L", 109 "Headphone Jack", "HP_L",
110 "Headphone Jack", "HP_R", 110 "Headphone Jack", "HP_R",
111 "Ext Spk", "SPK_LP", 111 "Ext Spk", "SPK_LP",
112 "Ext Spk", "SPK_LN", 112 "Ext Spk", "SPK_LN",
113 "Ext Spk", "SPK_RP", 113 "Ext Spk", "SPK_RP",
114 "Ext Spk", "SPK_RN", 114 "Ext Spk", "SPK_RN",
115 "LINPUT2", "Mic Jack", 115 "LINPUT2", "Mic Jack",
116 "LINPUT3", "Mic Jack", 116 "LINPUT3", "Mic Jack",
117 "RINPUT1", "Main MIC", 117 "RINPUT1", "Main MIC",
118 "RINPUT2", "Main MIC", 118 "RINPUT2", "Main MIC",
119 "Mic Jack", "MICB", 119 "Mic Jack", "MICB",
120 "Main MIC", "MICB", 120 "Main MIC", "MICB",
121 "CPU-Playback", "ASRC-Playback", 121 "CPU-Playback", "ASRC-Playback",
122 "Playback", "CPU-Playback", 122 "Playback", "CPU-Playback",
123 "ASRC-Capture", "CPU-Capture", 123 "ASRC-Capture", "CPU-Capture",
124 "CPU-Capture", "Capture"; 124 "CPU-Capture", "Capture";
125 }; 125 };
126 126
127 soft_spi: soft-spi { 127 soft_spi: soft-spi {
128 compatible = "spi-gpio"; 128 compatible = "spi-gpio";
129 pinctrl-names = "default"; 129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_spi4>; 130 pinctrl-0 = <&pinctrl_spi4>;
131 pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; 131 pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
132 status = "okay"; 132 status = "okay";
133 gpio-sck = <&gpio5 11 0>; 133 gpio-sck = <&gpio5 11 0>;
134 gpio-mosi = <&gpio5 10 0>; 134 gpio-mosi = <&gpio5 10 0>;
135 cs-gpios = <&gpio5 7 0>; 135 cs-gpios = <&gpio5 7 0>;
136 num-chipselects = <1>; 136 num-chipselects = <1>;
137 #address-cells = <1>; 137 #address-cells = <1>;
138 #size-cells = <0>; 138 #size-cells = <0>;
139 139
140 gpio_spi: gpio_spi@0 { 140 gpio_spi: gpio_spi@0 {
141 compatible = "fairchild,74hc595"; 141 compatible = "fairchild,74hc595";
142 gpio-controller; 142 gpio-controller;
143 #gpio-cells = <2>; 143 #gpio-cells = <2>;
144 reg = <0>; 144 reg = <0>;
145 registers-number = <1>; 145 registers-number = <1>;
146 registers-default = /bits/ 8 <0x57>; 146 registers-default = /bits/ 8 <0x57>;
147 spi-max-frequency = <100000>; 147 spi-max-frequency = <100000>;
148 }; 148 };
149 }; 149 };
150 }; 150 };
151 151
152 &cpu0 { 152 &cpu0 {
153 arm-supply = <&reg_arm>; 153 arm-supply = <&reg_arm>;
154 soc-supply = <&reg_soc>; 154 soc-supply = <&reg_soc>;
155 dc-supply = <&reg_gpio_dvfs>; 155 dc-supply = <&reg_gpio_dvfs>;
156 }; 156 };
157 157
158 &clks { 158 &clks {
159 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 159 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
160 assigned-clock-rates = <786432000>; 160 assigned-clock-rates = <786432000>;
161 }; 161 };
162 162
163 &csi { 163 &csi {
164 status = "disabled"; 164 status = "disabled";
165 165
166 port { 166 port {
167 csi1_ep: endpoint { 167 csi1_ep: endpoint {
168 remote-endpoint = <&ov5640_ep>; 168 remote-endpoint = <&ov5640_ep>;
169 }; 169 };
170 }; 170 };
171 }; 171 };
172 172
173 &fec1 { 173 &fec1 {
174 pinctrl-names = "default"; 174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_enet1>; 175 pinctrl-0 = <&pinctrl_enet1>;
176 phy-mode = "rmii"; 176 phy-mode = "rmii";
177 phy-handle = <&ethphy0>; 177 phy-handle = <&ethphy0>;
178 status = "okay"; 178 status = "okay";
179 }; 179 };
180 180
181 &fec2 { 181 &fec2 {
182 pinctrl-names = "default"; 182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_enet2>; 183 pinctrl-0 = <&pinctrl_enet2>;
184 phy-mode = "rmii"; 184 phy-mode = "rmii";
185 phy-handle = <&ethphy1>; 185 phy-handle = <&ethphy1>;
186 status = "okay"; 186 status = "okay";
187 187
188 mdio { 188 mdio {
189 #address-cells = <1>; 189 #address-cells = <1>;
190 #size-cells = <0>; 190 #size-cells = <0>;
191 191
192 ethphy0: ethernet-phy@2 { 192 ethphy0: ethernet-phy@2 {
193 compatible = "ethernet-phy-ieee802.3-c22"; 193 compatible = "ethernet-phy-ieee802.3-c22";
194 reg = <2>; 194 reg = <2>;
195 }; 195 };
196 196
197 ethphy1: ethernet-phy@1 { 197 ethphy1: ethernet-phy@1 {
198 compatible = "ethernet-phy-ieee802.3-c22"; 198 compatible = "ethernet-phy-ieee802.3-c22";
199 reg = <1>; 199 reg = <1>;
200 }; 200 };
201 }; 201 };
202 }; 202 };
203 203
204 &can1 { 204 &can1 {
205 pinctrl-names = "default"; 205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_flexcan1>; 206 pinctrl-0 = <&pinctrl_flexcan1>;
207 xceiver-supply = <&reg_can_3v3>; 207 xceiver-supply = <&reg_can_3v3>;
208 status = "okay"; 208 status = "okay";
209 }; 209 };
210 210
211 &can2 { 211 &can2 {
212 pinctrl-names = "default"; 212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_flexcan2>; 213 pinctrl-0 = <&pinctrl_flexcan2>;
214 xceiver-supply = <&reg_can_3v3>; 214 xceiver-supply = <&reg_can_3v3>;
215 status = "okay"; 215 status = "okay";
216 }; 216 };
217 217
218 &gpc { 218 &gpc {
219 fsl,cpu_pupscr_sw2iso = <0x1>; 219 fsl,cpu_pupscr_sw2iso = <0x1>;
220 fsl,cpu_pupscr_sw = <0x0>; 220 fsl,cpu_pupscr_sw = <0x0>;
221 fsl,cpu_pdnscr_iso2sw = <0x1>; 221 fsl,cpu_pdnscr_iso2sw = <0x1>;
222 fsl,cpu_pdnscr_iso = <0x1>; 222 fsl,cpu_pdnscr_iso = <0x1>;
223 fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ 223 fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
224 }; 224 };
225 225
226 &i2c1 { 226 &i2c1 {
227 clock-frequency = <100000>; 227 clock-frequency = <100000>;
228 pinctrl-names = "default", "gpio"; 228 pinctrl-names = "default", "gpio";
229 pinctrl-0 = <&pinctrl_i2c1>; 229 pinctrl-0 = <&pinctrl_i2c1>;
230 pinctrl-1 = <&pinctrl_i2c1_gpio>; 230 pinctrl-1 = <&pinctrl_i2c1_gpio>;
231 scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; 231 scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
232 sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; 232 sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
233 status = "okay"; 233 status = "okay";
234 234
235 mag3110@0e { 235 mag3110@0e {
236 compatible = "fsl,mag3110"; 236 compatible = "fsl,mag3110";
237 reg = <0x0e>; 237 reg = <0x0e>;
238 position = <2>; 238 position = <2>;
239 }; 239 };
240 240
241 fxls8471@1e { 241 fxls8471@1e {
242 compatible = "fsl,fxls8471"; 242 compatible = "fsl,fxls8471";
243 reg = <0x1e>; 243 reg = <0x1e>;
244 position = <0>; 244 position = <0>;
245 interrupt-parent = <&gpio5>; 245 interrupt-parent = <&gpio5>;
246 interrupts = <0 8>; 246 interrupts = <0 8>;
247 }; 247 };
248 }; 248 };
249 249
250 &i2c2 { 250 &i2c2 {
251 clock_frequency = <100000>; 251 clock_frequency = <100000>;
252 pinctrl-names = "default", "gpio"; 252 pinctrl-names = "default", "gpio";
253 pinctrl-0 = <&pinctrl_i2c2>; 253 pinctrl-0 = <&pinctrl_i2c2>;
254 pinctrl-1 = <&pinctrl_i2c2_gpio>; 254 pinctrl-1 = <&pinctrl_i2c2_gpio>;
255 scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; 255 scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
256 sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; 256 sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
257 status = "okay"; 257 status = "okay";
258 258
259 codec: wm8960@1a { 259 codec: wm8960@1a {
260 compatible = "wlf,wm8960"; 260 compatible = "wlf,wm8960";
261 reg = <0x1a>; 261 reg = <0x1a>;
262 clocks = <&clks IMX6UL_CLK_SAI2>; 262 clocks = <&clks IMX6UL_CLK_SAI2>;
263 clock-names = "mclk"; 263 clock-names = "mclk";
264 wlf,shared-lrclk; 264 wlf,shared-lrclk;
265 }; 265 };
266 266
267 ov5640: ov5640@3c { 267 ov5640: ov5640@3c {
268 compatible = "ovti,ov5640"; 268 compatible = "ovti,ov5640";
269 reg = <0x3c>; 269 reg = <0x3c>;
270 pinctrl-names = "default"; 270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_csi1>; 271 pinctrl-0 = <&pinctrl_csi1>;
272 clocks = <&clks IMX6UL_CLK_CSI>; 272 clocks = <&clks IMX6UL_CLK_CSI>;
273 clock-names = "csi_mclk"; 273 clock-names = "csi_mclk";
274 pwn-gpios = <&gpio_spi 6 1>; 274 pwn-gpios = <&gpio_spi 6 1>;
275 rst-gpios = <&gpio_spi 5 0>; 275 rst-gpios = <&gpio_spi 5 0>;
276 csi_id = <0>; 276 csi_id = <0>;
277 mclk = <24000000>; 277 mclk = <24000000>;
278 mclk_source = <0>; 278 mclk_source = <0>;
279 status = "disabled"; 279 status = "disabled";
280 port { 280 port {
281 ov5640_ep: endpoint { 281 ov5640_ep: endpoint {
282 remote-endpoint = <&csi1_ep>; 282 remote-endpoint = <&csi1_ep>;
283 }; 283 };
284 }; 284 };
285 }; 285 };
286 }; 286 };
287 287
288 &iomuxc { 288 &iomuxc {
289 pinctrl-names = "default"; 289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_hog_1>; 290 pinctrl-0 = <&pinctrl_hog_1>;
291 imx6ul-evk { 291 imx6ul-evk {
292 pinctrl_hog_1: hoggrp-1 { 292 pinctrl_hog_1: hoggrp-1 {
293 fsl,pins = < 293 fsl,pins = <
294 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ 294 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
295 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ 295 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
296 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ 296 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
297 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 297 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000
298 >; 298 >;
299 }; 299 };
300 300
301 pinctrl_csi1: csi1grp { 301 pinctrl_csi1: csi1grp {
302 fsl,pins = < 302 fsl,pins = <
303 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 303 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
304 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 304 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
305 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 305 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
306 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 306 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
307 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 307 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
308 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 308 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
309 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 309 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
310 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 310 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
311 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 311 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
312 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 312 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
313 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 313 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
314 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 314 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
315 >; 315 >;
316 }; 316 };
317 317
318 pinctrl_dvfs: dvfsgrp { 318 pinctrl_dvfs: dvfsgrp {
319 fsl,pins = < 319 fsl,pins = <
320 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 320 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79
321 >; 321 >;
322 }; 322 };
323 323
324 pinctrl_enet1: enet1grp { 324 pinctrl_enet1: enet1grp {
325 fsl,pins = < 325 fsl,pins = <
326 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 326 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
327 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 327 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
328 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 328 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
329 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 329 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
330 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 330 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
331 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 331 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
332 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 332 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
333 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 333 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
334 >; 334 >;
335 }; 335 };
336 336
337 pinctrl_enet2: enet2grp { 337 pinctrl_enet2: enet2grp {
338 fsl,pins = < 338 fsl,pins = <
339 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 339 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
340 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 340 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
341 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 341 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
342 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 342 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
343 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 343 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
344 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 344 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
345 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 345 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
346 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 346 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
347 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 347 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
348 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 348 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
349 >; 349 >;
350 }; 350 };
351 351
352 pinctrl_flexcan1: flexcan1grp{ 352 pinctrl_flexcan1: flexcan1grp{
353 fsl,pins = < 353 fsl,pins = <
354 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 354 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
355 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 355 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
356 >; 356 >;
357 }; 357 };
358 358
359 pinctrl_flexcan2: flexcan2grp{ 359 pinctrl_flexcan2: flexcan2grp{
360 fsl,pins = < 360 fsl,pins = <
361 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 361 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
362 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 362 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
363 >; 363 >;
364 }; 364 };
365 365
366 pinctrl_i2c1: i2c1grp { 366 pinctrl_i2c1: i2c1grp {
367 fsl,pins = < 367 fsl,pins = <
368 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 368 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
369 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 369 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
370 >; 370 >;
371 }; 371 };
372 372
373 pinctrl_i2c1_gpio: i2c1grp_gpio { 373 pinctrl_i2c1_gpio: i2c1grp_gpio {
374 fsl,pins = < 374 fsl,pins = <
375 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 375 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
376 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 376 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
377 >; 377 >;
378 }; 378 };
379 379
380 pinctrl_i2c2: i2c2grp { 380 pinctrl_i2c2: i2c2grp {
381 fsl,pins = < 381 fsl,pins = <
382 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 382 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
383 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 383 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
384 >; 384 >;
385 }; 385 };
386 386
387 pinctrl_i2c2_gpio: i2c2grp_gpio { 387 pinctrl_i2c2_gpio: i2c2grp_gpio {
388 fsl,pins = < 388 fsl,pins = <
389 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 389 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
390 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 390 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
391 >; 391 >;
392 }; 392 };
393 393
394 pinctrl_lcdif_dat: lcdifdatgrp { 394 pinctrl_lcdif_dat: lcdifdatgrp {
395 fsl,pins = < 395 fsl,pins = <
396 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 396 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
397 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 397 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
398 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 398 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
399 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 399 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
400 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 400 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
401 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 401 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
402 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 402 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
403 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 403 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
404 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 404 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
405 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 405 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
406 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 406 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
407 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 407 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
408 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 408 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
409 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 409 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
410 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 410 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
411 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 411 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
412 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 412 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
413 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 413 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
414 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 414 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
415 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 415 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
416 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 416 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
417 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 417 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
418 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 418 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
419 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 419 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
420 >; 420 >;
421 }; 421 };
422 422
423 pinctrl_lcdif_ctrl: lcdifctrlgrp { 423 pinctrl_lcdif_ctrl: lcdifctrlgrp {
424 fsl,pins = < 424 fsl,pins = <
425 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 425 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
426 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 426 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
427 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 427 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
428 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 428 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
429 /* used for lcd reset */ 429 /* used for lcd reset */
430 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 430 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
431 >; 431 >;
432 }; 432 };
433 433
434 pinctrl_pf1550: pf1550 { 434 pinctrl_pf1550: pf1550 {
435 fsl,pins = < 435 fsl,pins = <
436 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x80000000 436 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x80000000
437 >; 437 >;
438 }; 438 };
439 439
440 pinctrl_pwm1: pwm1grp { 440 pinctrl_pwm1: pwm1grp {
441 fsl,pins = < 441 fsl,pins = <
442 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 442 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
443 >; 443 >;
444 }; 444 };
445 445
446 pinctrl_qspi: qspigrp { 446 pinctrl_qspi: qspigrp {
447 fsl,pins = < 447 fsl,pins = <
448 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 448 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
449 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 449 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
450 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 450 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
451 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 451 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
452 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 452 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
453 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 453 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
454 >; 454 >;
455 }; 455 };
456 456
457 pinctrl_sai2: sai2grp { 457 pinctrl_sai2: sai2grp {
458 fsl,pins = < 458 fsl,pins = <
459 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 459 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
460 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 460 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
461 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 461 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
462 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 462 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
463 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 463 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
464 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 464 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
465 >; 465 >;
466 }; 466 };
467 467
468 pinctrl_sim2_1: sim2grp-1 { 468 pinctrl_sim2_1: sim2grp-1 {
469 fsl,pins = < 469 fsl,pins = <
470 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 470 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
471 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x11 471 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x11
472 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb810 472 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb810
473 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb810 473 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb810
474 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb811 474 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb811
475 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 475 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
476 >; 476 >;
477 }; 477 };
478 478
479 pinctrl_spi4: spi4grp { 479 pinctrl_spi4: spi4grp {
480 fsl,pins = < 480 fsl,pins = <
481 MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 481 MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
482 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 482 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
483 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 483 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
484 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 484 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
485 >; 485 >;
486 }; 486 };
487 487
488 pinctrl_tsc: tscgrp { 488 pinctrl_tsc: tscgrp {
489 fsl,pins = < 489 fsl,pins = <
490 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 490 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
491 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 491 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
492 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 492 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
493 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 493 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
494 >; 494 >;
495 }; 495 };
496 496
497 pinctrl_uart1: uart1grp { 497 pinctrl_uart1: uart1grp {
498 fsl,pins = < 498 fsl,pins = <
499 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 499 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
500 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 500 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
501 >; 501 >;
502 }; 502 };
503 503
504 pinctrl_uart2: uart2grp { 504 pinctrl_uart2: uart2grp {
505 fsl,pins = < 505 fsl,pins = <
506 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 506 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
507 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 507 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
508 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 508 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
509 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 509 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
510 >; 510 >;
511 }; 511 };
512 512
513 pinctrl_uart2dte: uart2dtegrp { 513 pinctrl_uart2dte: uart2dtegrp {
514 fsl,pins = < 514 fsl,pins = <
515 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 515 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
516 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 516 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
517 MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 517 MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1
518 MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 518 MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1
519 >; 519 >;
520 }; 520 };
521 521
522 pinctrl_usb_otg1_id: usbotg1idgrp { 522 pinctrl_usb_otg1_id: usbotg1idgrp {
523 fsl,pins = < 523 fsl,pins = <
524 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 524 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
525 >; 525 >;
526 }; 526 };
527 527
528 pinctrl_usdhc1: usdhc1grp { 528 pinctrl_usdhc1: usdhc1grp {
529 fsl,pins = < 529 fsl,pins = <
530 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 530 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
531 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 531 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
532 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 532 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
533 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 533 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
534 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 534 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
535 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 535 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
536 >; 536 >;
537 }; 537 };
538 538
539 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 539 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
540 fsl,pins = < 540 fsl,pins = <
541 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 541 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
542 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 542 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
543 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 543 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
544 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 544 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
545 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 545 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
546 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 546 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
547 >; 547 >;
548 }; 548 };
549 549
550 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 550 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
551 fsl,pins = < 551 fsl,pins = <
552 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 552 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
553 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 553 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
554 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 554 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
555 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 555 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
556 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 556 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
557 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 557 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
558 >; 558 >;
559 }; 559 };
560 560
561 pinctrl_usdhc2: usdhc2grp { 561 pinctrl_usdhc2: usdhc2grp {
562 fsl,pins = < 562 fsl,pins = <
563 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 563 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
564 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 564 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
565 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 565 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
566 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 566 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
567 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 567 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
568 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 568 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
569 >; 569 >;
570 }; 570 };
571 571
572 pinctrl_usdhc2_8bit: usdhc2grp_8bit { 572 pinctrl_usdhc2_8bit: usdhc2grp_8bit {
573 fsl,pins = < 573 fsl,pins = <
574 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 574 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
575 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 575 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
576 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 576 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
577 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 577 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
578 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 578 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
579 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 579 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
580 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 580 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
581 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 581 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
582 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 582 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
583 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 583 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
584 >; 584 >;
585 }; 585 };
586 586
587 pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { 587 pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
588 fsl,pins = < 588 fsl,pins = <
589 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 589 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
590 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 590 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
591 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 591 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
592 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 592 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
593 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 593 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
594 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 594 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
595 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 595 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
596 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 596 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
597 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 597 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
598 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 598 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
599 >; 599 >;
600 }; 600 };
601 601
602 pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { 602 pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
603 fsl,pins = < 603 fsl,pins = <
604 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 604 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
605 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 605 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
606 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 606 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
607 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 607 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
608 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 608 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
609 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 609 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
610 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 610 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
611 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 611 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
612 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 612 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
613 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 613 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
614 >; 614 >;
615 }; 615 };
616 pinctrl_wdog: wdoggrp { 616 pinctrl_wdog: wdoggrp {
617 fsl,pins = < 617 fsl,pins = <
618 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 618 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
619 >; 619 >;
620 }; 620 };
621 }; 621 };
622 }; 622 };
623 623
624 &lcdif { 624 &lcdif {
625 pinctrl-names = "default"; 625 pinctrl-names = "default";
626 pinctrl-0 = <&pinctrl_lcdif_dat 626 pinctrl-0 = <&pinctrl_lcdif_dat
627 &pinctrl_lcdif_ctrl>; 627 &pinctrl_lcdif_ctrl>;
628 display = <&display0>; 628 display = <&display0>;
629 status = "okay"; 629 status = "okay";
630 630
631 display0: display { 631 display0: display {
632 bits-per-pixel = <16>; 632 bits-per-pixel = <16>;
633 bus-width = <24>; 633 bus-width = <24>;
634 634
635 display-timings { 635 display-timings {
636 native-mode = <&timing0>; 636 native-mode = <&timing0>;
637 timing0: timing0 { 637 timing0: timing0 {
638 clock-frequency = <9200000>; 638 clock-frequency = <9200000>;
639 hactive = <480>; 639 hactive = <480>;
640 vactive = <272>; 640 vactive = <272>;
641 hfront-porch = <8>; 641 hfront-porch = <8>;
642 hback-porch = <4>; 642 hback-porch = <4>;
643 hsync-len = <41>; 643 hsync-len = <41>;
644 vback-porch = <2>; 644 vback-porch = <2>;
645 vfront-porch = <4>; 645 vfront-porch = <4>;
646 vsync-len = <10>; 646 vsync-len = <10>;
647 647
648 hsync-active = <0>; 648 hsync-active = <0>;
649 vsync-active = <0>; 649 vsync-active = <0>;
650 de-active = <1>; 650 de-active = <1>;
651 pixelclk-active = <0>; 651 pixelclk-active = <0>;
652 }; 652 };
653 }; 653 };
654 }; 654 };
655 }; 655 };
656 656
657 &pwm1 { 657 &pwm1 {
658 pinctrl-names = "default"; 658 pinctrl-names = "default";
659 pinctrl-0 = <&pinctrl_pwm1>; 659 pinctrl-0 = <&pinctrl_pwm1>;
660 status = "okay"; 660 status = "okay";
661 }; 661 };
662 662
663 &pxp { 663 &pxp {
664 status = "okay"; 664 status = "okay";
665 }; 665 };
666 666
667 &qspi { 667 &qspi {
668 pinctrl-names = "default"; 668 pinctrl-names = "default";
669 pinctrl-0 = <&pinctrl_qspi>; 669 pinctrl-0 = <&pinctrl_qspi>;
670 status = "okay"; 670 status = "okay";
671 ddrsmp=<0>; 671 ddrsmp=<0>;
672 672
673 flash0: n25q256a@0 { 673 flash0: n25q256a@0 {
674 #address-cells = <1>; 674 #address-cells = <1>;
675 #size-cells = <1>; 675 #size-cells = <1>;
676 compatible = "micron,n25q256a", "jedec,spi-nor"; 676 compatible = "micron,n25q256a", "jedec,spi-nor";
677 spi-max-frequency = <29000000>; 677 spi-max-frequency = <29000000>;
678 spi-nor,ddr-quad-read-dummy = <6>; 678 spi-nor,ddr-quad-read-dummy = <6>;
679 reg = <0>; 679 reg = <0>;
680 }; 680 };
681 }; 681 };
682 682
683 &sai2 { 683 &sai2 {
684 pinctrl-names = "default"; 684 pinctrl-names = "default";
685 pinctrl-0 = <&pinctrl_sai2>; 685 pinctrl-0 = <&pinctrl_sai2>;
686 686
687 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, 687 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
688 <&clks IMX6UL_CLK_SAI2>; 688 <&clks IMX6UL_CLK_SAI2>;
689 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 689 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
690 assigned-clock-rates = <0>, <12288000>; 690 assigned-clock-rates = <0>, <12288000>;
691 691
692 status = "okay"; 692 status = "okay";
693 }; 693 };
694 694
695 &sim2 { 695 &sim2 {
696 pinctrl-names = "default"; 696 pinctrl-names = "default";
697 pinctrl-0 = <&pinctrl_sim2_1>; 697 pinctrl-0 = <&pinctrl_sim2_1>;
698 assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>; 698 assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>;
699 assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>; 699 assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>;
700 assigned-clock-rates = <240000000>; 700 assigned-clock-rates = <240000000>;
701 /* GPIO_ACTIVE_HIGH/LOW:sim card voltage control 701 /* GPIO_ACTIVE_HIGH/LOW:sim card voltage control
702 * NCN8025:Vcc = ACTIVE_HIGH?5V:3V 702 * NCN8025:Vcc = ACTIVE_HIGH?5V:3V
703 * TDA8035:Vcc = ACTIVE_HIGH?5V:1.8V 703 * TDA8035:Vcc = ACTIVE_HIGH?5V:1.8V
704 */ 704 */
705 pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; 705 pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
706 port = <1>; 706 port = <1>;
707 sven_low_active; 707 sven_low_active;
708 status = "okay"; 708 status = "okay";
709 }; 709 };
710 710
711 &tsc { 711 &tsc {
712 pinctrl-names = "default"; 712 pinctrl-names = "default";
713 pinctrl-0 = <&pinctrl_tsc>; 713 pinctrl-0 = <&pinctrl_tsc>;
714 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; 714 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
715 measure-delay-time = <0xffff>; 715 measure-delay-time = <0xffff>;
716 pre-charge-time = <0xfff>; 716 pre-charge-time = <0xfff>;
717 status = "okay"; 717 status = "okay";
718 }; 718 };
719 719
720 &uart1 { 720 &uart1 {
721 pinctrl-names = "default"; 721 pinctrl-names = "default";
722 pinctrl-0 = <&pinctrl_uart1>; 722 pinctrl-0 = <&pinctrl_uart1>;
723 status = "okay"; 723 status = "okay";
724 }; 724 };
725 725
726 &uart2 { 726 &uart2 {
727 pinctrl-names = "default"; 727 pinctrl-names = "default";
728 pinctrl-0 = <&pinctrl_uart2>; 728 pinctrl-0 = <&pinctrl_uart2>;
729 fsl,uart-has-rtscts; 729 fsl,uart-has-rtscts;
730 /* for DTE mode, add below change */ 730 /* for DTE mode, add below change */
731 /* fsl,dte-mode; */ 731 /* fsl,dte-mode; */
732 /* pinctrl-0 = <&pinctrl_uart2dte>; */ 732 /* pinctrl-0 = <&pinctrl_uart2dte>; */
733 status = "okay"; 733 status = "okay";
734 }; 734 };
735 735
736 &usbotg1 { 736 &usbotg1 {
737 pinctrl-names = "default"; 737 pinctrl-names = "default";
738 pinctrl-0 = <&pinctrl_usb_otg1_id>; 738 pinctrl-0 = <&pinctrl_usb_otg1_id>;
739 dr_mode = "otg"; 739 dr_mode = "otg";
740 srp-disable; 740 srp-disable;
741 hnp-disable; 741 hnp-disable;
742 adp-disable; 742 adp-disable;
743 status = "okay"; 743 status = "okay";
744 }; 744 };
745 745
746 &usbotg2 { 746 &usbotg2 {
747 dr_mode = "host"; 747 dr_mode = "host";
748 disable-over-current; 748 disable-over-current;
749 status = "okay"; 749 status = "okay";
750 }; 750 };
751 751
752 &usbphy1 { 752 &usbphy1 {
753 tx-d-cal = <0x5>; 753 tx-d-cal = <0x5>;
754 }; 754 };
755 755
756 &usbphy2 { 756 &usbphy2 {
757 tx-d-cal = <0x5>; 757 tx-d-cal = <0x5>;
758 }; 758 };
759 759
760 &usdhc1 { 760 &usdhc1 {
761 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 761 pinctrl-names = "default", "state_100mhz", "state_200mhz";
762 pinctrl-0 = <&pinctrl_usdhc1>; 762 pinctrl-0 = <&pinctrl_usdhc1>;
763 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 763 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
764 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 764 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
765 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 765 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
766 keep-power-in-suspend; 766 keep-power-in-suspend;
767 wakeup-source; 767 wakeup-source;
768 vmmc-supply = <&reg_sd1_vmmc>; 768 vmmc-supply = <&reg_sd1_vmmc>;
769 status = "okay"; 769 status = "okay";
770 }; 770 };
771 771
772 &usdhc2 { 772 &usdhc2 {
773 pinctrl-names = "default"; 773 pinctrl-names = "default";
774 pinctrl-0 = <&pinctrl_usdhc2>; 774 pinctrl-0 = <&pinctrl_usdhc2>;
775 non-removable; 775 non-removable;
776 status = "okay"; 776 status = "okay";
777 }; 777 };
778 778
779 &wdog1 { 779 &wdog1 {
780 pinctrl-names = "default"; 780 pinctrl-names = "default";
781 pinctrl-0 = <&pinctrl_wdog>; 781 pinctrl-0 = <&pinctrl_wdog>;
782 fsl,ext-reset-output; 782 fsl,ext-reset-output;
783 }; 783 };
784 784
arch/arm/dts/imx6ul-14x14-lpddr2-arm2.dts
Diff comments   View file @ 4daafb3
1 /* 1 /*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/input/input.h>
12 #include "imx6ul.dtsi" 12 #include "imx6ul.dtsi"
13 13
14 / { 14 / {
15 model = "Freescale i.MX6 UltraLite 14X14 LPDDR2 ARM2 Board"; 15 model = "Freescale i.MX6 UltraLite 14X14 LPDDR2 ARM2 Board";
16 compatible = "fsl,imx6ul-14x14-lpddr2-arm2", "fsl,imx6ul"; 16 compatible = "fsl,imx6ul-14x14-lpddr2-arm2", "fsl,imx6ul";
17 17
18 chosen { 18 chosen {
19 stdout-path = &uart1; 19 stdout-path = &uart1;
20 }; 20 };
21 21
22 memory { 22 memory {
23 reg = <0x80000000 0x20000000>; 23 reg = <0x80000000 0x20000000>;
24 }; 24 };
25 25
26 reserved-memory { 26 reserved-memory {
27 #address-cells = <1>; 27 #address-cells = <1>;
28 #size-cells = <1>; 28 #size-cells = <1>;
29 ranges; 29 ranges;
30 30
31 linux,cma { 31 linux,cma {
32 compatible = "shared-dma-pool"; 32 compatible = "shared-dma-pool";
33 reusable; 33 reusable;
34 size = <0x14000000>; 34 size = <0x14000000>;
35 linux,cma-default; 35 linux,cma-default;
36 }; 36 };
37 }; 37 };
38 38
39 pxp_v4l2 { 39 pxp_v4l2 {
40 compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; 40 compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
41 status = "okay"; 41 status = "okay";
42 }; 42 };
43 43
44 regulators { 44 regulators {
45 compatible = "simple-bus"; 45 compatible = "simple-bus";
46 #address-cells = <1>; 46 #address-cells = <1>;
47 #size-cells = <0>; 47 #size-cells = <0>;
48 48
49 reg_sd1_vmmc: sd1_vmmc { 49 reg_sd1_vmmc: sd1_vmmc {
50 compatible = "regulator-fixed"; 50 compatible = "regulator-fixed";
51 regulator-name = "SD1_SPWR"; 51 regulator-name = "SD1_SPWR";
52 regulator-min-microvolt = <3000000>; 52 regulator-min-microvolt = <3000000>;
53 regulator-max-microvolt = <3000000>; 53 regulator-max-microvolt = <3000000>;
54 gpio = <&gpio4 11 GPIO_ACTIVE_HIGH>; 54 gpio = <&gpio4 11 GPIO_ACTIVE_HIGH>;
55 off-on-delay = <20000>; 55 u-boot,off-on-delay-us = <20000>;
56 enable-active-high; 56 enable-active-high;
57 }; 57 };
58 58
59 reg_sd2_vmmc: sd2_vmmc { 59 reg_sd2_vmmc: sd2_vmmc {
60 compatible = "regulator-fixed"; 60 compatible = "regulator-fixed";
61 regulator-name = "SD2_SPWR"; 61 regulator-name = "SD2_SPWR";
62 regulator-min-microvolt = <3000000>; 62 regulator-min-microvolt = <3000000>;
63 regulator-max-microvolt = <3000000>; 63 regulator-max-microvolt = <3000000>;
64 gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; 64 gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
65 enable-active-high; 65 enable-active-high;
66 }; 66 };
67 67
68 reg_can1_3v3: regulator@0 { 68 reg_can1_3v3: regulator@0 {
69 compatible = "regulator-fixed"; 69 compatible = "regulator-fixed";
70 reg = <0>; 70 reg = <0>;
71 regulator-name = "can1-3v3"; 71 regulator-name = "can1-3v3";
72 regulator-min-microvolt = <3300000>; 72 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <3300000>; 73 regulator-max-microvolt = <3300000>;
74 gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; 74 gpio = <&gpio1 15 GPIO_ACTIVE_LOW>;
75 }; 75 };
76 76
77 reg_vref_3v3: regulator@1 { 77 reg_vref_3v3: regulator@1 {
78 compatible = "regulator-fixed"; 78 compatible = "regulator-fixed";
79 regulator-name = "vref-3v3"; 79 regulator-name = "vref-3v3";
80 regulator-min-microvolt = <3300000>; 80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>; 81 regulator-max-microvolt = <3300000>;
82 }; 82 };
83 83
84 reg_usb_otg1_vbus: regulator@2 { 84 reg_usb_otg1_vbus: regulator@2 {
85 compatible = "regulator-fixed"; 85 compatible = "regulator-fixed";
86 reg = <2>; 86 reg = <2>;
87 pinctrl-names = "default"; 87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_usb_otg1>; 88 pinctrl-0 = <&pinctrl_usb_otg1>;
89 regulator-name = "usb_otg1_vbus"; 89 regulator-name = "usb_otg1_vbus";
90 regulator-min-microvolt = <5000000>; 90 regulator-min-microvolt = <5000000>;
91 regulator-max-microvolt = <5000000>; 91 regulator-max-microvolt = <5000000>;
92 gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; 92 gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
93 enable-active-high; 93 enable-active-high;
94 }; 94 };
95 }; 95 };
96 }; 96 };
97 97
98 &ecspi2 { 98 &ecspi2 {
99 fsl,spi-num-chipselects = <1>; 99 fsl,spi-num-chipselects = <1>;
100 cs-gpios = <&gpio4 22 0>; 100 cs-gpios = <&gpio4 22 0>;
101 pinctrl-names = "default"; 101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_ecspi2_1 &pinctrl_ecspi2_cs_1>; 102 pinctrl-0 = <&pinctrl_ecspi2_1 &pinctrl_ecspi2_cs_1>;
103 status = "disabled"; 103 status = "disabled";
104 104
105 flash: n25q032@0 { 105 flash: n25q032@0 {
106 #address-cells = <1>; 106 #address-cells = <1>;
107 #size-cells = <1>; 107 #size-cells = <1>;
108 compatible = "st,n25q032"; 108 compatible = "st,n25q032";
109 spi-max-frequency = <20000000>; 109 spi-max-frequency = <20000000>;
110 reg = <0>; 110 reg = <0>;
111 }; 111 };
112 }; 112 };
113 113
114 &cpu0 { 114 &cpu0 {
115 /* 115 /*
116 * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN, 116 * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN,
117 * to align with other platform and use the same cpufreq 117 * to align with other platform and use the same cpufreq
118 * driver, still use the seperated OPP define for arm 118 * driver, still use the seperated OPP define for arm
119 * and soc. 119 * and soc.
120 */ 120 */
121 operating-points = < 121 operating-points = <
122 /* kHz uV */ 122 /* kHz uV */
123 528000 1175000 123 528000 1175000
124 396000 1175000 124 396000 1175000
125 198000 1175000 125 198000 1175000
126 >; 126 >;
127 fsl,soc-operating-points = < 127 fsl,soc-operating-points = <
128 /* KHz uV */ 128 /* KHz uV */
129 528000 1175000 129 528000 1175000
130 396000 1175000 130 396000 1175000
131 198000 1175000 131 198000 1175000
132 >; 132 >;
133 fsl,arm-soc-shared = <1>; 133 fsl,arm-soc-shared = <1>;
134 }; 134 };
135 135
136 &reg_arm { 136 &reg_arm {
137 vin-supply = <&sw1a_reg>; 137 vin-supply = <&sw1a_reg>;
138 regulator-allow-bypass; 138 regulator-allow-bypass;
139 }; 139 };
140 140
141 &reg_soc { 141 &reg_soc {
142 vin-supply = <&sw1a_reg>; 142 vin-supply = <&sw1a_reg>;
143 regulator-allow-bypass; 143 regulator-allow-bypass;
144 }; 144 };
145 145
146 &fec1 { 146 &fec1 {
147 pinctrl-names = "default"; 147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_enet1>; 148 pinctrl-0 = <&pinctrl_enet1>;
149 phy-mode = "mii"; 149 phy-mode = "mii";
150 phy-handle = <&ethphy0>; 150 phy-handle = <&ethphy0>;
151 status = "disabled"; 151 status = "disabled";
152 }; 152 };
153 153
154 &fec2 { 154 &fec2 {
155 pinctrl-names = "default"; 155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_enet2>; 156 pinctrl-0 = <&pinctrl_enet2>;
157 phy-mode = "rmii"; 157 phy-mode = "rmii";
158 phy-handle = <&ethphy1>; 158 phy-handle = <&ethphy1>;
159 status = "okay"; 159 status = "okay";
160 160
161 mdio { 161 mdio {
162 #address-cells = <1>; 162 #address-cells = <1>;
163 #size-cells = <0>; 163 #size-cells = <0>;
164 164
165 ethphy0: ethernet-phy@1 { 165 ethphy0: ethernet-phy@1 {
166 compatible = "ethernet-phy-ieee802.3-c22"; 166 compatible = "ethernet-phy-ieee802.3-c22";
167 reg = <2>; 167 reg = <2>;
168 }; 168 };
169 169
170 ethphy1: ethernet-phy@2 { 170 ethphy1: ethernet-phy@2 {
171 compatible = "ethernet-phy-ieee802.3-c22"; 171 compatible = "ethernet-phy-ieee802.3-c22";
172 reg = <1>; 172 reg = <1>;
173 }; 173 };
174 }; 174 };
175 }; 175 };
176 176
177 &can1 { 177 &can1 {
178 pinctrl-names = "default"; 178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_flexcan1>; 179 pinctrl-0 = <&pinctrl_flexcan1>;
180 xceiver-supply = <&reg_can1_3v3>; 180 xceiver-supply = <&reg_can1_3v3>;
181 status = "disabled"; 181 status = "disabled";
182 }; 182 };
183 183
184 &gpc { 184 &gpc {
185 fsl,cpu_pupscr_sw2iso = <0xf>; 185 fsl,cpu_pupscr_sw2iso = <0xf>;
186 fsl,cpu_pupscr_sw = <0x0>; 186 fsl,cpu_pupscr_sw = <0x0>;
187 fsl,cpu_pdnscr_iso2sw = <0x1>; 187 fsl,cpu_pdnscr_iso2sw = <0x1>;
188 fsl,cpu_pdnscr_iso = <0x1>; 188 fsl,cpu_pdnscr_iso = <0x1>;
189 fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ 189 fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
190 }; 190 };
191 191
192 &gpmi { 192 &gpmi {
193 pinctrl-names = "default"; 193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_gpmi_nand_1>; 194 pinctrl-0 = <&pinctrl_gpmi_nand_1>;
195 status = "disabled"; 195 status = "disabled";
196 nand-on-flash-bbt; 196 nand-on-flash-bbt;
197 }; 197 };
198 198
199 &i2c1 { 199 &i2c1 {
200 clock-frequency = <100000>; 200 clock-frequency = <100000>;
201 pinctrl-names = "default"; 201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_i2c1>; 202 pinctrl-0 = <&pinctrl_i2c1>;
203 status = "okay"; 203 status = "okay";
204 204
205 pmic: pfuze100@08 { 205 pmic: pfuze100@08 {
206 compatible = "fsl,pfuze200"; 206 compatible = "fsl,pfuze200";
207 reg = <0x08>; 207 reg = <0x08>;
208 208
209 regulators { 209 regulators {
210 sw1a_reg: sw1ab { 210 sw1a_reg: sw1ab {
211 regulator-min-microvolt = <300000>; 211 regulator-min-microvolt = <300000>;
212 regulator-max-microvolt = <1875000>; 212 regulator-max-microvolt = <1875000>;
213 regulator-always-on; 213 regulator-always-on;
214 regulator-ramp-delay = <6250>; 214 regulator-ramp-delay = <6250>;
215 }; 215 };
216 216
217 sw2_reg: sw2 { 217 sw2_reg: sw2 {
218 regulator-min-microvolt = <800000>; 218 regulator-min-microvolt = <800000>;
219 regulator-max-microvolt = <3300000>; 219 regulator-max-microvolt = <3300000>;
220 regulator-always-on; 220 regulator-always-on;
221 }; 221 };
222 222
223 sw3a_reg: sw3a { 223 sw3a_reg: sw3a {
224 regulator-min-microvolt = <400000>; 224 regulator-min-microvolt = <400000>;
225 regulator-max-microvolt = <1975000>; 225 regulator-max-microvolt = <1975000>;
226 regulator-always-on; 226 regulator-always-on;
227 }; 227 };
228 228
229 sw3b_reg: sw3b { 229 sw3b_reg: sw3b {
230 regulator-min-microvolt = <400000>; 230 regulator-min-microvolt = <400000>;
231 regulator-max-microvolt = <1975000>; 231 regulator-max-microvolt = <1975000>;
232 regulator-always-on; 232 regulator-always-on;
233 }; 233 };
234 234
235 swbst_reg: swbst { 235 swbst_reg: swbst {
236 regulator-min-microvolt = <5000000>; 236 regulator-min-microvolt = <5000000>;
237 regulator-max-microvolt = <5150000>; 237 regulator-max-microvolt = <5150000>;
238 }; 238 };
239 239
240 snvs_reg: vsnvs { 240 snvs_reg: vsnvs {
241 regulator-min-microvolt = <1000000>; 241 regulator-min-microvolt = <1000000>;
242 regulator-max-microvolt = <3000000>; 242 regulator-max-microvolt = <3000000>;
243 regulator-always-on; 243 regulator-always-on;
244 }; 244 };
245 245
246 vref_reg: vrefddr { 246 vref_reg: vrefddr {
247 regulator-always-on; 247 regulator-always-on;
248 }; 248 };
249 249
250 vgen1_reg: vgen1 { 250 vgen1_reg: vgen1 {
251 regulator-min-microvolt = <800000>; 251 regulator-min-microvolt = <800000>;
252 regulator-max-microvolt = <1550000>; 252 regulator-max-microvolt = <1550000>;
253 }; 253 };
254 254
255 vgen2_reg: vgen2 { 255 vgen2_reg: vgen2 {
256 regulator-min-microvolt = <800000>; 256 regulator-min-microvolt = <800000>;
257 regulator-max-microvolt = <1550000>; 257 regulator-max-microvolt = <1550000>;
258 }; 258 };
259 259
260 vgen3_reg: vgen3 { 260 vgen3_reg: vgen3 {
261 regulator-min-microvolt = <1800000>; 261 regulator-min-microvolt = <1800000>;
262 regulator-max-microvolt = <3300000>; 262 regulator-max-microvolt = <3300000>;
263 }; 263 };
264 264
265 vgen4_reg: vgen4 { 265 vgen4_reg: vgen4 {
266 regulator-min-microvolt = <1800000>; 266 regulator-min-microvolt = <1800000>;
267 regulator-max-microvolt = <3300000>; 267 regulator-max-microvolt = <3300000>;
268 regulator-always-on; 268 regulator-always-on;
269 }; 269 };
270 270
271 vgen5_reg: vgen5 { 271 vgen5_reg: vgen5 {
272 regulator-min-microvolt = <1800000>; 272 regulator-min-microvolt = <1800000>;
273 regulator-max-microvolt = <3300000>; 273 regulator-max-microvolt = <3300000>;
274 regulator-always-on; 274 regulator-always-on;
275 }; 275 };
276 276
277 vgen6_reg: vgen6 { 277 vgen6_reg: vgen6 {
278 regulator-min-microvolt = <1800000>; 278 regulator-min-microvolt = <1800000>;
279 regulator-max-microvolt = <3300000>; 279 regulator-max-microvolt = <3300000>;
280 regulator-always-on; 280 regulator-always-on;
281 }; 281 };
282 }; 282 };
283 }; 283 };
284 }; 284 };
285 285
286 &pxp { 286 &pxp {
287 status = "okay"; 287 status = "okay";
288 }; 288 };
289 289
290 &qspi { 290 &qspi {
291 pinctrl-names = "default"; 291 pinctrl-names = "default";
292 pinctrl-0 = <&pinctrl_qspi>; 292 pinctrl-0 = <&pinctrl_qspi>;
293 status = "disabled"; 293 status = "disabled";
294 fsl,qspi-has-second-chip = <1>; 294 fsl,qspi-has-second-chip = <1>;
295 ddrsmp=<0>; 295 ddrsmp=<0>;
296 296
297 flash0: n25q256a@0 { 297 flash0: n25q256a@0 {
298 #address-cells = <1>; 298 #address-cells = <1>;
299 #size-cells = <1>; 299 #size-cells = <1>;
300 compatible = "micron,n25q256a", "jedec,spi-nor"; 300 compatible = "micron,n25q256a", "jedec,spi-nor";
301 spi-max-frequency = <29000000>; 301 spi-max-frequency = <29000000>;
302 spi-nor,ddr-quad-read-dummy = <6>; 302 spi-nor,ddr-quad-read-dummy = <6>;
303 reg = <0>; 303 reg = <0>;
304 }; 304 };
305 305
306 flash1: n25q256a@1 { 306 flash1: n25q256a@1 {
307 #address-cells = <1>; 307 #address-cells = <1>;
308 #size-cells = <1>; 308 #size-cells = <1>;
309 compatible = "micron,n25q256a", "jedec,spi-nor"; 309 compatible = "micron,n25q256a", "jedec,spi-nor";
310 spi-max-frequency = <29000000>; 310 spi-max-frequency = <29000000>;
311 spi-nor,ddr-quad-read-dummy = <6>; 311 spi-nor,ddr-quad-read-dummy = <6>;
312 reg = <1>; 312 reg = <1>;
313 }; 313 };
314 314
315 flash2: n25q256a@2 { 315 flash2: n25q256a@2 {
316 #address-cells = <1>; 316 #address-cells = <1>;
317 #size-cells = <1>; 317 #size-cells = <1>;
318 compatible = "micron,n25q256a", "jedec,spi-nor"; 318 compatible = "micron,n25q256a", "jedec,spi-nor";
319 spi-max-frequency = <29000000>; 319 spi-max-frequency = <29000000>;
320 spi-nor,ddr-quad-read-dummy = <6>; 320 spi-nor,ddr-quad-read-dummy = <6>;
321 reg = <2>; 321 reg = <2>;
322 }; 322 };
323 323
324 flash3: n25q256a@3 { 324 flash3: n25q256a@3 {
325 #address-cells = <1>; 325 #address-cells = <1>;
326 #size-cells = <1>; 326 #size-cells = <1>;
327 compatible = "micron,n25q256a", "jedec,spi-nor"; 327 compatible = "micron,n25q256a", "jedec,spi-nor";
328 spi-max-frequency = <29000000>; 328 spi-max-frequency = <29000000>;
329 spi-nor,ddr-quad-read-dummy = <6>; 329 spi-nor,ddr-quad-read-dummy = <6>;
330 reg = <3>; 330 reg = <3>;
331 }; 331 };
332 }; 332 };
333 333
334 &uart1 { 334 &uart1 {
335 pinctrl-names = "default"; 335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_uart1>; 336 pinctrl-0 = <&pinctrl_uart1>;
337 status = "okay"; 337 status = "okay";
338 }; 338 };
339 339
340 &usbotg1 { 340 &usbotg1 {
341 vbus-supply = <&reg_usb_otg1_vbus>; 341 vbus-supply = <&reg_usb_otg1_vbus>;
342 pinctrl-names = "default"; 342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_usb_otg1_id>; 343 pinctrl-0 = <&pinctrl_usb_otg1_id>;
344 status = "okay"; 344 status = "okay";
345 }; 345 };
346 346
347 &usdhc1 { 347 &usdhc1 {
348 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 348 pinctrl-names = "default", "state_100mhz", "state_200mhz";
349 pinctrl-0 = <&pinctrl_usdhc1>; 349 pinctrl-0 = <&pinctrl_usdhc1>;
350 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 350 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
351 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 351 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
352 cd-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; 352 cd-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
353 wp-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; 353 wp-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
354 keep-power-in-suspend; 354 keep-power-in-suspend;
355 enable-sdio-wakeup; 355 enable-sdio-wakeup;
356 vmmc-supply = <&reg_sd1_vmmc>; 356 vmmc-supply = <&reg_sd1_vmmc>;
357 status = "okay"; 357 status = "okay";
358 }; 358 };
359 359
360 &usdhc2 { 360 &usdhc2 {
361 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 361 pinctrl-names = "default", "state_100mhz", "state_200mhz";
362 pinctrl-0 = <&pinctrl_usdhc2_8bit>; 362 pinctrl-0 = <&pinctrl_usdhc2_8bit>;
363 pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; 363 pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
364 pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; 364 pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
365 keep-power-in-suspend; 365 keep-power-in-suspend;
366 vmmc-supply = <&reg_sd2_vmmc>; 366 vmmc-supply = <&reg_sd2_vmmc>;
367 bus-width = <8>; 367 bus-width = <8>;
368 non-removable; 368 non-removable;
369 status = "okay"; 369 status = "okay";
370 }; 370 };
371 371
372 &iomuxc { 372 &iomuxc {
373 pinctrl-names = "default"; 373 pinctrl-names = "default";
374 pinctrl-0 = <&pinctrl_hog &pinctrl_hog_nand>; 374 pinctrl-0 = <&pinctrl_hog &pinctrl_hog_nand>;
375 375
376 imx6ul-14x14-lpddr2-arm2 { 376 imx6ul-14x14-lpddr2-arm2 {
377 pinctrl_hog: hoggrp { 377 pinctrl_hog: hoggrp {
378 fsl,pins = < 378 fsl,pins = <
379 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* SD1 CD */ 379 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* SD1 CD */
380 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* SD1 WP */ 380 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* SD1 WP */
381 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ 381 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
382 MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x17059 /* SD2 VSELECT */ 382 MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x17059 /* SD2 VSELECT */
383 >; 383 >;
384 }; 384 };
385 385
386 pinctrl_hog_nand: hoggrp_nand { 386 pinctrl_hog_nand: hoggrp_nand {
387 fsl,pins = < 387 fsl,pins = <
388 MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x17059 /* SD1 RESET */ 388 MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x17059 /* SD1 RESET */
389 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESET */ 389 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESET */
390 >; 390 >;
391 }; 391 };
392 392
393 pinctrl_ecspi2_cs_1: ecspi2_cs_grp-1 { 393 pinctrl_ecspi2_cs_1: ecspi2_cs_grp-1 {
394 fsl,pins = < 394 fsl,pins = <
395 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 395 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0
396 >; 396 >;
397 }; 397 };
398 398
399 pinctrl_ecspi2_1: ecspi2grp-1 { 399 pinctrl_ecspi2_1: ecspi2grp-1 {
400 fsl,pins = < 400 fsl,pins = <
401 MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x10b0 401 MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x10b0
402 MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x10b0 402 MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x10b0
403 MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x10b0 403 MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x10b0
404 >; 404 >;
405 }; 405 };
406 406
407 pinctrl_enet1: enet1grp { 407 pinctrl_enet1: enet1grp {
408 fsl,pins = < 408 fsl,pins = <
409 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 409 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
410 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 410 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
411 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 411 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
412 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 412 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
413 MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x1b0b0 413 MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x1b0b0
414 MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x1b0b0 414 MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x1b0b0
415 MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x4b01b0a8 415 MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x4b01b0a8
416 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 416 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
417 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 417 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
418 MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x1b0b0 418 MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x1b0b0
419 MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x1b0b0 419 MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x1b0b0
420 MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x4b01b0a8 420 MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x4b01b0a8
421 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 421 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
422 MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x1b0b0 422 MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x1b0b0
423 MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x1b0b0 423 MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x1b0b0
424 >; 424 >;
425 }; 425 };
426 426
427 pinctrl_enet2: enet2grp { 427 pinctrl_enet2: enet2grp {
428 fsl,pins = < 428 fsl,pins = <
429 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 429 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
430 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 430 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
431 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 431 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
432 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 432 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
433 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 433 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
434 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8 434 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8
435 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 435 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
436 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 436 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
437 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 437 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
438 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 438 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
439 MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8 439 MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8
440 MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0 440 MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0
441 MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0 441 MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0
442 >; 442 >;
443 }; 443 };
444 444
445 pinctrl_flexcan1: flexcan1grp{ 445 pinctrl_flexcan1: flexcan1grp{
446 fsl,pins = < 446 fsl,pins = <
447 MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 447 MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
448 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 448 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
449 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */ 449 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */
450 >; 450 >;
451 }; 451 };
452 452
453 pinctrl_gpmi_nand_1: gpmi-nand-1 { 453 pinctrl_gpmi_nand_1: gpmi-nand-1 {
454 fsl,pins = < 454 fsl,pins = <
455 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 455 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
456 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 456 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
457 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 457 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
458 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 458 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
459 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 459 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
460 MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 460 MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
461 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 461 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
462 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 462 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
463 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 463 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
464 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 464 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
465 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 465 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
466 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 466 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
467 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 467 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
468 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 468 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
469 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 469 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
470 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 470 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
471 >; 471 >;
472 }; 472 };
473 473
474 pinctrl_i2c2: i2c2grp { 474 pinctrl_i2c2: i2c2grp {
475 fsl,pins = < 475 fsl,pins = <
476 MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0 476 MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0
477 MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0 477 MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0
478 >; 478 >;
479 }; 479 };
480 480
481 pinctrl_lcdif_dat: lcdifdatgrp { 481 pinctrl_lcdif_dat: lcdifdatgrp {
482 fsl,pins = < 482 fsl,pins = <
483 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 483 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
484 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 484 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
485 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 485 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
486 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 486 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
487 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 487 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
488 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 488 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
489 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 489 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
490 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 490 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
491 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 491 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
492 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 492 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
493 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 493 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
494 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 494 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
495 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 495 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
496 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 496 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
497 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 497 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
498 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 498 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
499 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 499 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
500 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 500 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
501 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 501 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
502 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 502 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
503 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 503 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
504 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 504 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
505 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 505 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
506 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 506 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
507 >; 507 >;
508 }; 508 };
509 509
510 pinctrl_lcdif_ctrl: lcdifctrlgrp { 510 pinctrl_lcdif_ctrl: lcdifctrlgrp {
511 fsl,pins = < 511 fsl,pins = <
512 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 512 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
513 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 513 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
514 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 514 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
515 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 515 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
516 MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 516 MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79
517 >; 517 >;
518 }; 518 };
519 519
520 pinctrl_pwm1: pmw1grp { 520 pinctrl_pwm1: pmw1grp {
521 fsl,pins = < 521 fsl,pins = <
522 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0 522 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0
523 >; 523 >;
524 }; 524 };
525 525
526 pinctrl_qspi: qspigrp { 526 pinctrl_qspi: qspigrp {
527 fsl,pins = < 527 fsl,pins = <
528 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 528 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
529 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 529 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
530 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 530 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
531 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 531 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
532 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 532 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
533 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 533 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
534 MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1 534 MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1
535 MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1 535 MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1
536 MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1 536 MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1
537 MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1 537 MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1
538 MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1 538 MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1
539 MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1 539 MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1
540 MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1 540 MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1
541 MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1 541 MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1
542 >; 542 >;
543 }; 543 };
544 544
545 pinctrl_mqs: mqsgrp { 545 pinctrl_mqs: mqsgrp {
546 fsl,pins = < 546 fsl,pins = <
547 MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x11088 547 MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x11088
548 MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x11088 548 MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x11088
549 >; 549 >;
550 }; 550 };
551 551
552 pinctrl_sai1: sai1grp { 552 pinctrl_sai1: sai1grp {
553 fsl,pins = < 553 fsl,pins = <
554 MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b0 554 MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b0
555 MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x1b0b0 555 MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x1b0b0
556 MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x1b0b0 556 MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x1b0b0
557 MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0 557 MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0
558 MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0 558 MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0
559 MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 559 MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0
560 MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 560 MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
561 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 561 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059
562 >; 562 >;
563 }; 563 };
564 564
565 pinctrl_spdif: spdifgrp { 565 pinctrl_spdif: spdifgrp {
566 fsl,pins = < 566 fsl,pins = <
567 MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x1b0b0 567 MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x1b0b0
568 MX6UL_PAD_SD1_CLK__SPDIF_IN 0x1b0b0 568 MX6UL_PAD_SD1_CLK__SPDIF_IN 0x1b0b0
569 >; 569 >;
570 }; 570 };
571 571
572 pinctrl_tsc: tscgrp { 572 pinctrl_tsc: tscgrp {
573 fsl,pins = < 573 fsl,pins = <
574 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 574 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
575 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 575 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
576 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 576 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
577 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 577 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
578 >; 578 >;
579 }; 579 };
580 580
581 pinctrl_adc1: adc1grp { 581 pinctrl_adc1: adc1grp {
582 fsl,pins = < 582 fsl,pins = <
583 MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 583 MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0
584 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 584 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
585 >; 585 >;
586 }; 586 };
587 587
588 pinctrl_i2c1: i2c1grp { 588 pinctrl_i2c1: i2c1grp {
589 fsl,pins = < 589 fsl,pins = <
590 MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1 590 MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1
591 MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1 591 MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1
592 >; 592 >;
593 }; 593 };
594 594
595 pinctrl_uart1: uart1grp { 595 pinctrl_uart1: uart1grp {
596 fsl,pins = < 596 fsl,pins = <
597 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 597 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
598 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 598 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
599 >; 599 >;
600 }; 600 };
601 601
602 pinctrl_uart2: uart2grp { 602 pinctrl_uart2: uart2grp {
603 fsl,pins = < 603 fsl,pins = <
604 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 604 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
605 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 605 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
606 MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 606 MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
607 MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 607 MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
608 >; 608 >;
609 }; 609 };
610 610
611 pinctrl_uart2dte: uart2dtegrp { 611 pinctrl_uart2dte: uart2dtegrp {
612 fsl,pins = < 612 fsl,pins = <
613 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 613 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
614 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 614 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
615 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 615 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1
616 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 616 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1
617 >; 617 >;
618 }; 618 };
619 619
620 pinctrl_usb_otg1_id: usbotg1idgrp { 620 pinctrl_usb_otg1_id: usbotg1idgrp {
621 fsl,pins = < 621 fsl,pins = <
622 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 622 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
623 >; 623 >;
624 }; 624 };
625 625
626 pinctrl_usb_otg1: usbotg1grp { 626 pinctrl_usb_otg1: usbotg1grp {
627 fsl,pins = < 627 fsl,pins = <
628 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0 628 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0
629 >; 629 >;
630 }; 630 };
631 631
632 pinctrl_usdhc1: usdhc1grp { 632 pinctrl_usdhc1: usdhc1grp {
633 fsl,pins = < 633 fsl,pins = <
634 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 634 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
635 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 635 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
636 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 636 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
637 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 637 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
638 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 638 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
639 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 639 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
640 >; 640 >;
641 }; 641 };
642 642
643 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 643 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
644 fsl,pins = < 644 fsl,pins = <
645 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 645 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
646 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 646 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
647 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 647 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
648 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 648 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
649 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 649 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
650 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 650 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
651 >; 651 >;
652 }; 652 };
653 653
654 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 654 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
655 fsl,pins = < 655 fsl,pins = <
656 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 656 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
657 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 657 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
658 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 658 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
659 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 659 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
660 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 660 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
661 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 661 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
662 >; 662 >;
663 }; 663 };
664 664
665 pinctrl_usdhc1_8bit: usdhc1_8bit_grp { 665 pinctrl_usdhc1_8bit: usdhc1_8bit_grp {
666 fsl,pins = < 666 fsl,pins = <
667 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 667 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
668 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 668 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
669 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 669 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
670 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 670 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
671 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 671 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
672 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 672 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
673 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 673 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
674 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 674 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
675 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 675 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
676 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 676 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
677 >; 677 >;
678 }; 678 };
679 679
680 pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp { 680 pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp {
681 fsl,pins = < 681 fsl,pins = <
682 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 682 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
683 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 683 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
684 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 684 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
685 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 685 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
686 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 686 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
687 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 687 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
688 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9 688 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9
689 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9 689 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9
690 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9 690 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9
691 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9 691 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9
692 >; 692 >;
693 }; 693 };
694 694
695 pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp { 695 pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp {
696 fsl,pins = < 696 fsl,pins = <
697 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 697 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
698 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 698 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
699 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 699 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
700 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 700 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
701 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 701 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
702 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 702 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
703 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9 703 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9
704 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9 704 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9
705 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9 705 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9
706 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9 706 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9
707 >; 707 >;
708 }; 708 };
709 709
710 pinctrl_usdhc2: usdhc2grp { 710 pinctrl_usdhc2: usdhc2grp {
711 fsl,pins = < 711 fsl,pins = <
712 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 712 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
713 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 713 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
714 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 714 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
715 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 715 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
716 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 716 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
717 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 717 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
718 >; 718 >;
719 }; 719 };
720 720
721 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 721 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
722 fsl,pins = < 722 fsl,pins = <
723 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 723 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
724 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 724 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
725 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 725 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
726 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 726 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
727 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 727 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
728 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 728 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
729 >; 729 >;
730 }; 730 };
731 731
732 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 732 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
733 fsl,pins = < 733 fsl,pins = <
734 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 734 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
735 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 735 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
736 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 736 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
737 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 737 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
738 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 738 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
739 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 739 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
740 >; 740 >;
741 }; 741 };
742 742
743 pinctrl_usdhc2_8bit: usdhc2_8bit_grp { 743 pinctrl_usdhc2_8bit: usdhc2_8bit_grp {
744 fsl,pins = < 744 fsl,pins = <
745 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 745 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
746 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 746 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
747 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 747 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
748 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 748 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
749 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 749 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
750 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 750 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
751 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 751 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
752 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 752 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
753 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 753 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
754 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 754 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
755 >; 755 >;
756 }; 756 };
757 757
758 pinctrl_usdhc2_8bit_100mhz: usdhc2_8bit_100mhz_grp { 758 pinctrl_usdhc2_8bit_100mhz: usdhc2_8bit_100mhz_grp {
759 fsl,pins = < 759 fsl,pins = <
760 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 760 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
761 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 761 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
762 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 762 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
763 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 763 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
764 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 764 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
765 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 765 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
766 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 766 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
767 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 767 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
768 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 768 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
769 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 769 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
770 >; 770 >;
771 }; 771 };
772 772
773 pinctrl_usdhc2_8bit_200mhz: usdhc2_8bit_200mhz_grp { 773 pinctrl_usdhc2_8bit_200mhz: usdhc2_8bit_200mhz_grp {
774 fsl,pins = < 774 fsl,pins = <
775 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 775 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
776 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 776 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
777 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 777 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
778 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 778 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
779 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 779 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
780 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 780 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
781 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 781 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
782 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 782 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
783 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 783 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
784 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 784 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
785 >; 785 >;
786 }; 786 };
787 }; 787 };
788 }; 788 };
789 789
arch/arm/dts/imx6ul-9x9-evk.dts
Diff comments   View file @ 4daafb3
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP 4 * Copyright 2017-2018 NXP
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include <dt-bindings/input/input.h> 9 #include <dt-bindings/input/input.h>
10 #include "imx6ul.dtsi" 10 #include "imx6ul.dtsi"
11 11
12 / { 12 / {
13 model = "Freescale i.MX6 UltraLite 9x9 EVK Board"; 13 model = "Freescale i.MX6 UltraLite 9x9 EVK Board";
14 compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul"; 14 compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul";
15 15
16 aliases { 16 aliases {
17 spi5 = &soft_spi; 17 spi5 = &soft_spi;
18 }; 18 };
19 19
20 backlight { 20 backlight {
21 compatible = "pwm-backlight"; 21 compatible = "pwm-backlight";
22 pwms = <&pwm1 0 5000000>; 22 pwms = <&pwm1 0 5000000>;
23 brightness-levels = <0 4 8 16 32 64 128 255>; 23 brightness-levels = <0 4 8 16 32 64 128 255>;
24 default-brightness-level = <6>; 24 default-brightness-level = <6>;
25 status = "okay"; 25 status = "okay";
26 }; 26 };
27 27
28 chosen { 28 chosen {
29 stdout-path = &uart1; 29 stdout-path = &uart1;
30 }; 30 };
31 31
32 memory { 32 memory {
33 reg = <0x80000000 0x10000000>; 33 reg = <0x80000000 0x10000000>;
34 }; 34 };
35 35
36 reserved-memory { 36 reserved-memory {
37 #address-cells = <1>; 37 #address-cells = <1>;
38 #size-cells = <1>; 38 #size-cells = <1>;
39 ranges; 39 ranges;
40 40
41 linux,cma { 41 linux,cma {
42 compatible = "shared-dma-pool"; 42 compatible = "shared-dma-pool";
43 reusable; 43 reusable;
44 size = <0x6000000>; 44 size = <0x6000000>;
45 linux,cma-default; 45 linux,cma-default;
46 }; 46 };
47 }; 47 };
48 48
49 pxp_v4l2 { 49 pxp_v4l2 {
50 compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; 50 compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
51 status = "okay"; 51 status = "okay";
52 }; 52 };
53 53
54 regulators { 54 regulators {
55 compatible = "simple-bus"; 55 compatible = "simple-bus";
56 #address-cells = <1>; 56 #address-cells = <1>;
57 #size-cells = <0>; 57 #size-cells = <0>;
58 58
59 reg_can_3v3: regulator@0 { 59 reg_can_3v3: regulator@0 {
60 compatible = "regulator-fixed"; 60 compatible = "regulator-fixed";
61 reg = <0>; 61 reg = <0>;
62 regulator-name = "can-3v3"; 62 regulator-name = "can-3v3";
63 regulator-min-microvolt = <3300000>; 63 regulator-min-microvolt = <3300000>;
64 regulator-max-microvolt = <3300000>; 64 regulator-max-microvolt = <3300000>;
65 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; 65 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
66 }; 66 };
67 67
68 reg_gpio_dvfs: regulator-gpio { 68 reg_gpio_dvfs: regulator-gpio {
69 compatible = "regulator-gpio"; 69 compatible = "regulator-gpio";
70 pinctrl-names = "default"; 70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_dvfs>; 71 pinctrl-0 = <&pinctrl_dvfs>;
72 regulator-min-microvolt = <1300000>; 72 regulator-min-microvolt = <1300000>;
73 regulator-max-microvolt = <1400000>; 73 regulator-max-microvolt = <1400000>;
74 regulator-name = "gpio_dvfs"; 74 regulator-name = "gpio_dvfs";
75 regulator-type = "voltage"; 75 regulator-type = "voltage";
76 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 76 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
77 states = <1300000 0x1 1400000 0x0>; 77 states = <1300000 0x1 1400000 0x0>;
78 }; 78 };
79 79
80 reg_sd1_vmmc: regulator@1 { 80 reg_sd1_vmmc: regulator@1 {
81 compatible = "regulator-fixed"; 81 compatible = "regulator-fixed";
82 regulator-name = "VSD_3V3"; 82 regulator-name = "VSD_3V3";
83 regulator-min-microvolt = <3300000>; 83 regulator-min-microvolt = <3300000>;
84 regulator-max-microvolt = <3300000>; 84 regulator-max-microvolt = <3300000>;
85 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 85 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
86 off-on-delay = <20000>; 86 u-boot,off-on-delay-us = <20000>;
87 enable-active-high; 87 enable-active-high;
88 }; 88 };
89 }; 89 };
90 90
91 sound { 91 sound {
92 compatible = "fsl,imx6ul-evk-wm8960", 92 compatible = "fsl,imx6ul-evk-wm8960",
93 "fsl,imx-audio-wm8960"; 93 "fsl,imx-audio-wm8960";
94 model = "wm8960-audio"; 94 model = "wm8960-audio";
95 cpu-dai = <&sai2>; 95 cpu-dai = <&sai2>;
96 audio-codec = <&codec>; 96 audio-codec = <&codec>;
97 asrc-controller = <&asrc>; 97 asrc-controller = <&asrc>;
98 codec-master; 98 codec-master;
99 gpr = <&gpr 4 0x100000 0x100000>; 99 gpr = <&gpr 4 0x100000 0x100000>;
100 /* 100 /*
101 * hp-det = <hp-det-pin hp-det-polarity>; 101 * hp-det = <hp-det-pin hp-det-polarity>;
102 * hp-det-pin: JD1 JD2 or JD3 102 * hp-det-pin: JD1 JD2 or JD3
103 * hp-det-polarity = 0: hp detect high for headphone 103 * hp-det-polarity = 0: hp detect high for headphone
104 * hp-det-polarity = 1: hp detect high for speaker 104 * hp-det-polarity = 1: hp detect high for speaker
105 */ 105 */
106 hp-det = <3 0>; 106 hp-det = <3 0>;
107 hp-det-gpios = <&gpio5 4 0>; 107 hp-det-gpios = <&gpio5 4 0>;
108 mic-det-gpios = <&gpio5 4 0>; 108 mic-det-gpios = <&gpio5 4 0>;
109 audio-routing = 109 audio-routing =
110 "Headphone Jack", "HP_L", 110 "Headphone Jack", "HP_L",
111 "Headphone Jack", "HP_R", 111 "Headphone Jack", "HP_R",
112 "Ext Spk", "SPK_LP", 112 "Ext Spk", "SPK_LP",
113 "Ext Spk", "SPK_LN", 113 "Ext Spk", "SPK_LN",
114 "Ext Spk", "SPK_RP", 114 "Ext Spk", "SPK_RP",
115 "Ext Spk", "SPK_RN", 115 "Ext Spk", "SPK_RN",
116 "LINPUT2", "Mic Jack", 116 "LINPUT2", "Mic Jack",
117 "LINPUT3", "Mic Jack", 117 "LINPUT3", "Mic Jack",
118 "RINPUT1", "Main MIC", 118 "RINPUT1", "Main MIC",
119 "RINPUT2", "Main MIC", 119 "RINPUT2", "Main MIC",
120 "Mic Jack", "MICB", 120 "Mic Jack", "MICB",
121 "Main MIC", "MICB", 121 "Main MIC", "MICB",
122 "CPU-Playback", "ASRC-Playback", 122 "CPU-Playback", "ASRC-Playback",
123 "Playback", "CPU-Playback", 123 "Playback", "CPU-Playback",
124 "ASRC-Capture", "CPU-Capture", 124 "ASRC-Capture", "CPU-Capture",
125 "CPU-Capture", "Capture"; 125 "CPU-Capture", "Capture";
126 }; 126 };
127 127
128 soft_spi: soft-spi { 128 soft_spi: soft-spi {
129 compatible = "spi-gpio"; 129 compatible = "spi-gpio";
130 pinctrl-names = "default"; 130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_spi4>; 131 pinctrl-0 = <&pinctrl_spi4>;
132 pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; 132 pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
133 status = "okay"; 133 status = "okay";
134 gpio-sck = <&gpio5 11 0>; 134 gpio-sck = <&gpio5 11 0>;
135 gpio-mosi = <&gpio5 10 0>; 135 gpio-mosi = <&gpio5 10 0>;
136 cs-gpios = <&gpio5 7 0>; 136 cs-gpios = <&gpio5 7 0>;
137 num-chipselects = <1>; 137 num-chipselects = <1>;
138 #address-cells = <1>; 138 #address-cells = <1>;
139 #size-cells = <0>; 139 #size-cells = <0>;
140 140
141 gpio_spi: gpio_spi@0 { 141 gpio_spi: gpio_spi@0 {
142 compatible = "fairchild,74hc595"; 142 compatible = "fairchild,74hc595";
143 gpio-controller; 143 gpio-controller;
144 #gpio-cells = <2>; 144 #gpio-cells = <2>;
145 reg = <0>; 145 reg = <0>;
146 registers-number = <1>; 146 registers-number = <1>;
147 registers-default = /bits/ 8 <0x57>; 147 registers-default = /bits/ 8 <0x57>;
148 spi-max-frequency = <100000>; 148 spi-max-frequency = <100000>;
149 }; 149 };
150 }; 150 };
151 }; 151 };
152 152
153 &clks { 153 &clks {
154 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 154 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
155 assigned-clock-rates = <786432000>; 155 assigned-clock-rates = <786432000>;
156 }; 156 };
157 157
158 &cpu0 { 158 &cpu0 {
159 /* 159 /*
160 * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN, 160 * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN,
161 * to align with other platform and use the same cpufreq 161 * to align with other platform and use the same cpufreq
162 * driver, still use the seperated OPP define for arm 162 * driver, still use the seperated OPP define for arm
163 * and soc. 163 * and soc.
164 */ 164 */
165 operating-points = < 165 operating-points = <
166 /* kHz uV */ 166 /* kHz uV */
167 528000 1175000 167 528000 1175000
168 396000 1175000 168 396000 1175000
169 198000 1175000 169 198000 1175000
170 >; 170 >;
171 fsl,soc-operating-points = < 171 fsl,soc-operating-points = <
172 /* KHz uV */ 172 /* KHz uV */
173 528000 1175000 173 528000 1175000
174 396000 1175000 174 396000 1175000
175 198000 1175000 175 198000 1175000
176 >; 176 >;
177 fsl,arm-soc-shared = <1>; 177 fsl,arm-soc-shared = <1>;
178 }; 178 };
179 179
180 &reg_arm { 180 &reg_arm {
181 vin-supply = <&sw1c_reg>; 181 vin-supply = <&sw1c_reg>;
182 regulator-allow-bypass; 182 regulator-allow-bypass;
183 }; 183 };
184 184
185 &reg_soc { 185 &reg_soc {
186 vin-supply = <&sw1c_reg>; 186 vin-supply = <&sw1c_reg>;
187 regulator-allow-bypass; 187 regulator-allow-bypass;
188 }; 188 };
189 189
190 &csi { 190 &csi {
191 status = "disabled"; 191 status = "disabled";
192 192
193 port { 193 port {
194 csi1_ep: endpoint { 194 csi1_ep: endpoint {
195 remote-endpoint = <&ov5640_ep>; 195 remote-endpoint = <&ov5640_ep>;
196 }; 196 };
197 }; 197 };
198 }; 198 };
199 199
200 &fec1 { 200 &fec1 {
201 pinctrl-names = "default"; 201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_enet1>; 202 pinctrl-0 = <&pinctrl_enet1>;
203 phy-mode = "rmii"; 203 phy-mode = "rmii";
204 phy-handle = <&ethphy0>; 204 phy-handle = <&ethphy0>;
205 status = "okay"; 205 status = "okay";
206 }; 206 };
207 207
208 &fec2 { 208 &fec2 {
209 pinctrl-names = "default"; 209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_enet2>; 210 pinctrl-0 = <&pinctrl_enet2>;
211 phy-mode = "rmii"; 211 phy-mode = "rmii";
212 phy-handle = <&ethphy1>; 212 phy-handle = <&ethphy1>;
213 status = "okay"; 213 status = "okay";
214 214
215 mdio { 215 mdio {
216 #address-cells = <1>; 216 #address-cells = <1>;
217 #size-cells = <0>; 217 #size-cells = <0>;
218 218
219 ethphy0: ethernet-phy@2 { 219 ethphy0: ethernet-phy@2 {
220 compatible = "ethernet-phy-ieee802.3-c22"; 220 compatible = "ethernet-phy-ieee802.3-c22";
221 reg = <2>; 221 reg = <2>;
222 }; 222 };
223 223
224 ethphy1: ethernet-phy@1 { 224 ethphy1: ethernet-phy@1 {
225 compatible = "ethernet-phy-ieee802.3-c22"; 225 compatible = "ethernet-phy-ieee802.3-c22";
226 reg = <1>; 226 reg = <1>;
227 }; 227 };
228 }; 228 };
229 }; 229 };
230 230
231 &can1 { 231 &can1 {
232 pinctrl-names = "default"; 232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_flexcan1>; 233 pinctrl-0 = <&pinctrl_flexcan1>;
234 xceiver-supply = <&reg_can_3v3>; 234 xceiver-supply = <&reg_can_3v3>;
235 status = "okay"; 235 status = "okay";
236 }; 236 };
237 237
238 &can2 { 238 &can2 {
239 pinctrl-names = "default"; 239 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_flexcan2>; 240 pinctrl-0 = <&pinctrl_flexcan2>;
241 xceiver-supply = <&reg_can_3v3>; 241 xceiver-supply = <&reg_can_3v3>;
242 status = "okay"; 242 status = "okay";
243 }; 243 };
244 244
245 &gpc { 245 &gpc {
246 fsl,cpu_pupscr_sw2iso = <0xf>; 246 fsl,cpu_pupscr_sw2iso = <0xf>;
247 fsl,cpu_pupscr_sw = <0x0>; 247 fsl,cpu_pupscr_sw = <0x0>;
248 fsl,cpu_pdnscr_iso2sw = <0x1>; 248 fsl,cpu_pdnscr_iso2sw = <0x1>;
249 fsl,cpu_pdnscr_iso = <0x1>; 249 fsl,cpu_pdnscr_iso = <0x1>;
250 fsl,ldo-bypass = <1>; 250 fsl,ldo-bypass = <1>;
251 }; 251 };
252 252
253 &i2c1 { 253 &i2c1 {
254 clock-frequency = <100000>; 254 clock-frequency = <100000>;
255 pinctrl-names = "default", "gpio"; 255 pinctrl-names = "default", "gpio";
256 pinctrl-0 = <&pinctrl_i2c1>; 256 pinctrl-0 = <&pinctrl_i2c1>;
257 pinctrl-1 = <&pinctrl_i2c1_gpio>; 257 pinctrl-1 = <&pinctrl_i2c1_gpio>;
258 scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; 258 scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
259 sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; 259 sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
260 status = "okay"; 260 status = "okay";
261 261
262 pmic: pfuze3000@08 { 262 pmic: pfuze3000@08 {
263 compatible = "fsl,pfuze3000"; 263 compatible = "fsl,pfuze3000";
264 reg = <0x08>; 264 reg = <0x08>;
265 265
266 regulators { 266 regulators {
267 sw1a_reg: sw1a { 267 sw1a_reg: sw1a {
268 regulator-min-microvolt = <700000>; 268 regulator-min-microvolt = <700000>;
269 regulator-max-microvolt = <3300000>; 269 regulator-max-microvolt = <3300000>;
270 regulator-boot-on; 270 regulator-boot-on;
271 regulator-always-on; 271 regulator-always-on;
272 regulator-ramp-delay = <6250>; 272 regulator-ramp-delay = <6250>;
273 }; 273 };
274 274
275 /* use sw1c_reg to align with pfuze100/pfuze200 */ 275 /* use sw1c_reg to align with pfuze100/pfuze200 */
276 sw1c_reg: sw1b { 276 sw1c_reg: sw1b {
277 regulator-min-microvolt = <700000>; 277 regulator-min-microvolt = <700000>;
278 regulator-max-microvolt = <1475000>; 278 regulator-max-microvolt = <1475000>;
279 regulator-boot-on; 279 regulator-boot-on;
280 regulator-always-on; 280 regulator-always-on;
281 regulator-ramp-delay = <6250>; 281 regulator-ramp-delay = <6250>;
282 }; 282 };
283 283
284 sw2_reg: sw2 { 284 sw2_reg: sw2 {
285 regulator-min-microvolt = <2500000>; 285 regulator-min-microvolt = <2500000>;
286 regulator-max-microvolt = <3300000>; 286 regulator-max-microvolt = <3300000>;
287 regulator-boot-on; 287 regulator-boot-on;
288 regulator-always-on; 288 regulator-always-on;
289 }; 289 };
290 290
291 sw3a_reg: sw3 { 291 sw3a_reg: sw3 {
292 regulator-min-microvolt = <900000>; 292 regulator-min-microvolt = <900000>;
293 regulator-max-microvolt = <1650000>; 293 regulator-max-microvolt = <1650000>;
294 regulator-boot-on; 294 regulator-boot-on;
295 regulator-always-on; 295 regulator-always-on;
296 }; 296 };
297 297
298 swbst_reg: swbst { 298 swbst_reg: swbst {
299 regulator-min-microvolt = <5000000>; 299 regulator-min-microvolt = <5000000>;
300 regulator-max-microvolt = <5150000>; 300 regulator-max-microvolt = <5150000>;
301 }; 301 };
302 302
303 snvs_reg: vsnvs { 303 snvs_reg: vsnvs {
304 regulator-min-microvolt = <1000000>; 304 regulator-min-microvolt = <1000000>;
305 regulator-max-microvolt = <3000000>; 305 regulator-max-microvolt = <3000000>;
306 regulator-boot-on; 306 regulator-boot-on;
307 regulator-always-on; 307 regulator-always-on;
308 }; 308 };
309 309
310 vref_reg: vrefddr { 310 vref_reg: vrefddr {
311 regulator-boot-on; 311 regulator-boot-on;
312 regulator-always-on; 312 regulator-always-on;
313 }; 313 };
314 314
315 vgen1_reg: vldo1 { 315 vgen1_reg: vldo1 {
316 regulator-min-microvolt = <1800000>; 316 regulator-min-microvolt = <1800000>;
317 regulator-max-microvolt = <3300000>; 317 regulator-max-microvolt = <3300000>;
318 regulator-always-on; 318 regulator-always-on;
319 }; 319 };
320 320
321 vgen2_reg: vldo2 { 321 vgen2_reg: vldo2 {
322 regulator-min-microvolt = <800000>; 322 regulator-min-microvolt = <800000>;
323 regulator-max-microvolt = <1550000>; 323 regulator-max-microvolt = <1550000>;
324 regulator-always-on; 324 regulator-always-on;
325 }; 325 };
326 326
327 vgen3_reg: vccsd { 327 vgen3_reg: vccsd {
328 regulator-min-microvolt = <2850000>; 328 regulator-min-microvolt = <2850000>;
329 regulator-max-microvolt = <3300000>; 329 regulator-max-microvolt = <3300000>;
330 regulator-always-on; 330 regulator-always-on;
331 }; 331 };
332 332
333 vgen4_reg: v33 { 333 vgen4_reg: v33 {
334 regulator-min-microvolt = <2850000>; 334 regulator-min-microvolt = <2850000>;
335 regulator-max-microvolt = <3300000>; 335 regulator-max-microvolt = <3300000>;
336 regulator-always-on; 336 regulator-always-on;
337 }; 337 };
338 338
339 vgen5_reg: vldo3 { 339 vgen5_reg: vldo3 {
340 regulator-min-microvolt = <1800000>; 340 regulator-min-microvolt = <1800000>;
341 regulator-max-microvolt = <3300000>; 341 regulator-max-microvolt = <3300000>;
342 regulator-always-on; 342 regulator-always-on;
343 }; 343 };
344 344
345 vgen6_reg: vldo4 { 345 vgen6_reg: vldo4 {
346 regulator-min-microvolt = <1800000>; 346 regulator-min-microvolt = <1800000>;
347 regulator-max-microvolt = <3300000>; 347 regulator-max-microvolt = <3300000>;
348 regulator-always-on; 348 regulator-always-on;
349 }; 349 };
350 }; 350 };
351 }; 351 };
352 352
353 mag3110@0e { 353 mag3110@0e {
354 compatible = "fsl,mag3110"; 354 compatible = "fsl,mag3110";
355 reg = <0x0e>; 355 reg = <0x0e>;
356 position = <2>; 356 position = <2>;
357 }; 357 };
358 358
359 fxls8471@1e { 359 fxls8471@1e {
360 compatible = "fsl,fxls8471"; 360 compatible = "fsl,fxls8471";
361 reg = <0x1e>; 361 reg = <0x1e>;
362 position = <0>; 362 position = <0>;
363 interrupt-parent = <&gpio5>; 363 interrupt-parent = <&gpio5>;
364 interrupts = <0 8>; 364 interrupts = <0 8>;
365 }; 365 };
366 }; 366 };
367 367
368 &i2c2 { 368 &i2c2 {
369 clock_frequency = <100000>; 369 clock_frequency = <100000>;
370 pinctrl-names = "default", "gpio"; 370 pinctrl-names = "default", "gpio";
371 pinctrl-0 = <&pinctrl_i2c2>; 371 pinctrl-0 = <&pinctrl_i2c2>;
372 pinctrl-1 = <&pinctrl_i2c2_gpio>; 372 pinctrl-1 = <&pinctrl_i2c2_gpio>;
373 scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; 373 scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
374 sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; 374 sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
375 status = "okay"; 375 status = "okay";
376 376
377 codec: wm8960@1a { 377 codec: wm8960@1a {
378 compatible = "wlf,wm8960"; 378 compatible = "wlf,wm8960";
379 reg = <0x1a>; 379 reg = <0x1a>;
380 clocks = <&clks IMX6UL_CLK_SAI2>; 380 clocks = <&clks IMX6UL_CLK_SAI2>;
381 clock-names = "mclk"; 381 clock-names = "mclk";
382 wlf,shared-lrclk; 382 wlf,shared-lrclk;
383 }; 383 };
384 384
385 ov5640: ov5640@3c { 385 ov5640: ov5640@3c {
386 compatible = "ovti,ov5640"; 386 compatible = "ovti,ov5640";
387 reg = <0x3c>; 387 reg = <0x3c>;
388 pinctrl-names = "default"; 388 pinctrl-names = "default";
389 pinctrl-0 = <&pinctrl_csi1>; 389 pinctrl-0 = <&pinctrl_csi1>;
390 clocks = <&clks IMX6UL_CLK_CSI>; 390 clocks = <&clks IMX6UL_CLK_CSI>;
391 clock-names = "csi_mclk"; 391 clock-names = "csi_mclk";
392 pwn-gpios = <&gpio_spi 6 1>; 392 pwn-gpios = <&gpio_spi 6 1>;
393 rst-gpios = <&gpio_spi 5 0>; 393 rst-gpios = <&gpio_spi 5 0>;
394 csi_id = <0>; 394 csi_id = <0>;
395 mclk = <24000000>; 395 mclk = <24000000>;
396 mclk_source = <0>; 396 mclk_source = <0>;
397 status = "disabled"; 397 status = "disabled";
398 port { 398 port {
399 ov5640_ep: endpoint { 399 ov5640_ep: endpoint {
400 remote-endpoint = <&csi1_ep>; 400 remote-endpoint = <&csi1_ep>;
401 }; 401 };
402 }; 402 };
403 }; 403 };
404 }; 404 };
405 405
406 &iomuxc { 406 &iomuxc {
407 pinctrl-names = "default"; 407 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_hog_1>; 408 pinctrl-0 = <&pinctrl_hog_1>;
409 imx6ul-evk { 409 imx6ul-evk {
410 pinctrl_csi1: csi1grp { 410 pinctrl_csi1: csi1grp {
411 fsl,pins = < 411 fsl,pins = <
412 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 412 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
413 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 413 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
414 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 414 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
415 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 415 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
416 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 416 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
417 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 417 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
418 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 418 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
419 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 419 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
420 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 420 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
421 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 421 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
422 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 422 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
423 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 423 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
424 >; 424 >;
425 }; 425 };
426 426
427 pinctrl_dvfs: dvfsgrp { 427 pinctrl_dvfs: dvfsgrp {
428 fsl,pins = < 428 fsl,pins = <
429 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 429 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79
430 >; 430 >;
431 }; 431 };
432 432
433 pinctrl_enet1: enet1grp { 433 pinctrl_enet1: enet1grp {
434 fsl,pins = < 434 fsl,pins = <
435 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 435 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
436 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 436 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
437 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 437 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
438 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 438 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
439 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 439 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
440 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 440 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
441 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 441 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
442 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 442 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
443 >; 443 >;
444 }; 444 };
445 445
446 pinctrl_enet2: enet2grp { 446 pinctrl_enet2: enet2grp {
447 fsl,pins = < 447 fsl,pins = <
448 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 448 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
449 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 449 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
450 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 450 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
451 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 451 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
452 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 452 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
453 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 453 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
454 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 454 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
455 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 455 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
456 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 456 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
457 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 457 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
458 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 458 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000
459 >; 459 >;
460 }; 460 };
461 461
462 pinctrl_flexcan1: flexcan1grp{ 462 pinctrl_flexcan1: flexcan1grp{
463 fsl,pins = < 463 fsl,pins = <
464 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 464 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
465 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 465 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
466 >; 466 >;
467 }; 467 };
468 468
469 pinctrl_flexcan2: flexcan2grp{ 469 pinctrl_flexcan2: flexcan2grp{
470 fsl,pins = < 470 fsl,pins = <
471 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 471 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
472 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 472 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
473 >; 473 >;
474 }; 474 };
475 475
476 pinctrl_hog_1: hoggrp-1 { 476 pinctrl_hog_1: hoggrp-1 {
477 fsl,pins = < 477 fsl,pins = <
478 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ 478 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
479 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ 479 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
480 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ 480 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
481 >; 481 >;
482 }; 482 };
483 483
484 pinctrl_i2c1: i2c1grp { 484 pinctrl_i2c1: i2c1grp {
485 fsl,pins = < 485 fsl,pins = <
486 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 486 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
487 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 487 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
488 >; 488 >;
489 }; 489 };
490 490
491 pinctrl_i2c1_gpio: i2c1grp_gpio { 491 pinctrl_i2c1_gpio: i2c1grp_gpio {
492 fsl,pins = < 492 fsl,pins = <
493 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 493 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
494 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 494 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
495 >; 495 >;
496 }; 496 };
497 497
498 pinctrl_i2c2: i2c2grp { 498 pinctrl_i2c2: i2c2grp {
499 fsl,pins = < 499 fsl,pins = <
500 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 500 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
501 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 501 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
502 >; 502 >;
503 }; 503 };
504 504
505 pinctrl_i2c2_gpio: i2c2grp_gpio { 505 pinctrl_i2c2_gpio: i2c2grp_gpio {
506 fsl,pins = < 506 fsl,pins = <
507 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 507 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
508 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 508 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
509 >; 509 >;
510 }; 510 };
511 511
512 pinctrl_lcdif_ctrl: lcdifctrlgrp { 512 pinctrl_lcdif_ctrl: lcdifctrlgrp {
513 fsl,pins = < 513 fsl,pins = <
514 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 514 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
515 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 515 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
516 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 516 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
517 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 517 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
518 /* used for lcd reset */ 518 /* used for lcd reset */
519 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 519 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
520 >; 520 >;
521 }; 521 };
522 522
523 pinctrl_lcdif_dat: lcdifdatgrp { 523 pinctrl_lcdif_dat: lcdifdatgrp {
524 fsl,pins = < 524 fsl,pins = <
525 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 525 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
526 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 526 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
527 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 527 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
528 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 528 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
529 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 529 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
530 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 530 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
531 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 531 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
532 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 532 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
533 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 533 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
534 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 534 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
535 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 535 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
536 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 536 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
537 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 537 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
538 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 538 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
539 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 539 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
540 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 540 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
541 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 541 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
542 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 542 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
543 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 543 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
544 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 544 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
545 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 545 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
546 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 546 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
547 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 547 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
548 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 548 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
549 >; 549 >;
550 }; 550 };
551 551
552 pinctrl_pwm1: pwm1grp { 552 pinctrl_pwm1: pwm1grp {
553 fsl,pins = < 553 fsl,pins = <
554 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 554 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
555 >; 555 >;
556 }; 556 };
557 557
558 pinctrl_qspi: qspigrp { 558 pinctrl_qspi: qspigrp {
559 fsl,pins = < 559 fsl,pins = <
560 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 560 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
561 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 561 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
562 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 562 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
563 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 563 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
564 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 564 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
565 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 565 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
566 >; 566 >;
567 }; 567 };
568 568
569 pinctrl_sai2: sai2grp { 569 pinctrl_sai2: sai2grp {
570 fsl,pins = < 570 fsl,pins = <
571 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 571 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
572 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 572 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
573 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 573 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
574 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 574 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
575 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 575 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
576 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 576 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
577 >; 577 >;
578 }; 578 };
579 579
580 pinctrl_sim2_1: sim2grp-1 { 580 pinctrl_sim2_1: sim2grp-1 {
581 fsl,pins = < 581 fsl,pins = <
582 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 582 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
583 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 583 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
584 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 584 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808
585 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 585 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
586 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 586 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
587 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 587 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
588 >; 588 >;
589 }; 589 };
590 590
591 pinctrl_spi4: spi4grp { 591 pinctrl_spi4: spi4grp {
592 fsl,pins = < 592 fsl,pins = <
593 MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 593 MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
594 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 594 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
595 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 595 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
596 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 596 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
597 >; 597 >;
598 }; 598 };
599 599
600 pinctrl_tsc: tscgrp { 600 pinctrl_tsc: tscgrp {
601 fsl,pins = < 601 fsl,pins = <
602 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 602 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
603 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 603 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
604 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 604 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
605 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 605 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
606 >; 606 >;
607 }; 607 };
608 608
609 pinctrl_uart1: uart1grp { 609 pinctrl_uart1: uart1grp {
610 fsl,pins = < 610 fsl,pins = <
611 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 611 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
612 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 612 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
613 >; 613 >;
614 }; 614 };
615 615
616 pinctrl_uart2: uart2grp { 616 pinctrl_uart2: uart2grp {
617 fsl,pins = < 617 fsl,pins = <
618 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 618 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
619 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 619 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
620 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 620 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
621 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 621 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
622 >; 622 >;
623 }; 623 };
624 624
625 pinctrl_uart2dte: uart2dtegrp { 625 pinctrl_uart2dte: uart2dtegrp {
626 fsl,pins = < 626 fsl,pins = <
627 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 627 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
628 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 628 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
629 MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 629 MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1
630 MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 630 MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1
631 >; 631 >;
632 }; 632 };
633 633
634 pinctrl_usb_otg1_id: usbotg1idgrp { 634 pinctrl_usb_otg1_id: usbotg1idgrp {
635 fsl,pins = < 635 fsl,pins = <
636 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 636 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
637 >; 637 >;
638 }; 638 };
639 639
640 pinctrl_usdhc1: usdhc1grp { 640 pinctrl_usdhc1: usdhc1grp {
641 fsl,pins = < 641 fsl,pins = <
642 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 642 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
643 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 643 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
644 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 644 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
645 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 645 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
646 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 646 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
647 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 647 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
648 >; 648 >;
649 }; 649 };
650 650
651 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 651 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
652 fsl,pins = < 652 fsl,pins = <
653 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 653 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
654 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 654 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
655 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 655 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
656 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 656 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
657 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 657 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
658 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 658 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
659 >; 659 >;
660 }; 660 };
661 661
662 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 662 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
663 fsl,pins = < 663 fsl,pins = <
664 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 664 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
665 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 665 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
666 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 666 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
667 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 667 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
668 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 668 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
669 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 669 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
670 >; 670 >;
671 }; 671 };
672 672
673 pinctrl_usdhc2: usdhc2grp { 673 pinctrl_usdhc2: usdhc2grp {
674 fsl,pins = < 674 fsl,pins = <
675 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 675 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
676 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 676 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
677 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 677 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
678 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 678 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
679 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 679 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
680 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 680 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
681 >; 681 >;
682 }; 682 };
683 683
684 pinctrl_wdog: wdoggrp { 684 pinctrl_wdog: wdoggrp {
685 fsl,pins = < 685 fsl,pins = <
686 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 686 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
687 >; 687 >;
688 }; 688 };
689 }; 689 };
690 }; 690 };
691 691
692 &lcdif { 692 &lcdif {
693 pinctrl-names = "default"; 693 pinctrl-names = "default";
694 pinctrl-0 = <&pinctrl_lcdif_dat 694 pinctrl-0 = <&pinctrl_lcdif_dat
695 &pinctrl_lcdif_ctrl>; 695 &pinctrl_lcdif_ctrl>;
696 display = <&display0>; 696 display = <&display0>;
697 status = "okay"; 697 status = "okay";
698 698
699 display0: display { 699 display0: display {
700 bits-per-pixel = <16>; 700 bits-per-pixel = <16>;
701 bus-width = <24>; 701 bus-width = <24>;
702 702
703 display-timings { 703 display-timings {
704 native-mode = <&timing0>; 704 native-mode = <&timing0>;
705 timing0: timing0 { 705 timing0: timing0 {
706 clock-frequency = <9200000>; 706 clock-frequency = <9200000>;
707 hactive = <480>; 707 hactive = <480>;
708 vactive = <272>; 708 vactive = <272>;
709 hfront-porch = <8>; 709 hfront-porch = <8>;
710 hback-porch = <4>; 710 hback-porch = <4>;
711 hsync-len = <41>; 711 hsync-len = <41>;
712 vback-porch = <2>; 712 vback-porch = <2>;
713 vfront-porch = <4>; 713 vfront-porch = <4>;
714 vsync-len = <10>; 714 vsync-len = <10>;
715 715
716 hsync-active = <0>; 716 hsync-active = <0>;
717 vsync-active = <0>; 717 vsync-active = <0>;
718 de-active = <1>; 718 de-active = <1>;
719 pixelclk-active = <0>; 719 pixelclk-active = <0>;
720 }; 720 };
721 }; 721 };
722 }; 722 };
723 }; 723 };
724 724
725 &pwm1 { 725 &pwm1 {
726 pinctrl-names = "default"; 726 pinctrl-names = "default";
727 pinctrl-0 = <&pinctrl_pwm1>; 727 pinctrl-0 = <&pinctrl_pwm1>;
728 status = "okay"; 728 status = "okay";
729 }; 729 };
730 730
731 &pxp { 731 &pxp {
732 status = "okay"; 732 status = "okay";
733 }; 733 };
734 734
735 &qspi { 735 &qspi {
736 pinctrl-names = "default"; 736 pinctrl-names = "default";
737 pinctrl-0 = <&pinctrl_qspi>; 737 pinctrl-0 = <&pinctrl_qspi>;
738 status = "okay"; 738 status = "okay";
739 ddrsmp=<0>; 739 ddrsmp=<0>;
740 740
741 flash0: n25q256a@0 { 741 flash0: n25q256a@0 {
742 #address-cells = <1>; 742 #address-cells = <1>;
743 #size-cells = <1>; 743 #size-cells = <1>;
744 compatible = "micron,n25q256a"; 744 compatible = "micron,n25q256a";
745 spi-max-frequency = <29000000>; 745 spi-max-frequency = <29000000>;
746 spi-nor,ddr-quad-read-dummy = <6>; 746 spi-nor,ddr-quad-read-dummy = <6>;
747 reg = <0>; 747 reg = <0>;
748 }; 748 };
749 }; 749 };
750 750
751 &sai2 { 751 &sai2 {
752 pinctrl-names = "default"; 752 pinctrl-names = "default";
753 pinctrl-0 = <&pinctrl_sai2>; 753 pinctrl-0 = <&pinctrl_sai2>;
754 754
755 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, 755 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
756 <&clks IMX6UL_CLK_SAI2>; 756 <&clks IMX6UL_CLK_SAI2>;
757 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 757 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
758 assigned-clock-rates = <0>, <12288000>; 758 assigned-clock-rates = <0>, <12288000>;
759 759
760 status = "okay"; 760 status = "okay";
761 }; 761 };
762 762
763 &sim2 { 763 &sim2 {
764 pinctrl-names = "default"; 764 pinctrl-names = "default";
765 pinctrl-0 = <&pinctrl_sim2_1>; 765 pinctrl-0 = <&pinctrl_sim2_1>;
766 assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>; 766 assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>;
767 assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>; 767 assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>;
768 assigned-clock-rates = <240000000>; 768 assigned-clock-rates = <240000000>;
769 pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; 769 pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
770 port = <1>; 770 port = <1>;
771 sven_low_active; 771 sven_low_active;
772 status = "okay"; 772 status = "okay";
773 }; 773 };
774 774
775 &tsc { 775 &tsc {
776 pinctrl-names = "default"; 776 pinctrl-names = "default";
777 pinctrl-0 = <&pinctrl_tsc>; 777 pinctrl-0 = <&pinctrl_tsc>;
778 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; 778 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
779 measure_delay_time = <0xffff>; 779 measure_delay_time = <0xffff>;
780 pre_charge_time = <0xfff>; 780 pre_charge_time = <0xfff>;
781 status = "okay"; 781 status = "okay";
782 }; 782 };
783 783
784 &uart1 { 784 &uart1 {
785 pinctrl-names = "default"; 785 pinctrl-names = "default";
786 pinctrl-0 = <&pinctrl_uart1>; 786 pinctrl-0 = <&pinctrl_uart1>;
787 status = "okay"; 787 status = "okay";
788 }; 788 };
789 789
790 &uart2 { 790 &uart2 {
791 pinctrl-names = "default"; 791 pinctrl-names = "default";
792 pinctrl-0 = <&pinctrl_uart2>; 792 pinctrl-0 = <&pinctrl_uart2>;
793 fsl,uart-has-rtscts; 793 fsl,uart-has-rtscts;
794 /* for DTE mode, add below change */ 794 /* for DTE mode, add below change */
795 /* fsl,dte-mode; */ 795 /* fsl,dte-mode; */
796 /* pinctrl-0 = <&pinctrl_uart2dte>; */ 796 /* pinctrl-0 = <&pinctrl_uart2dte>; */
797 status = "okay"; 797 status = "okay";
798 }; 798 };
799 799
800 &usbotg1 { 800 &usbotg1 {
801 pinctrl-names = "default"; 801 pinctrl-names = "default";
802 pinctrl-0 = <&pinctrl_usb_otg1_id>; 802 pinctrl-0 = <&pinctrl_usb_otg1_id>;
803 dr_mode = "otg"; 803 dr_mode = "otg";
804 srp-disable; 804 srp-disable;
805 hnp-disable; 805 hnp-disable;
806 adp-disable; 806 adp-disable;
807 status = "okay"; 807 status = "okay";
808 }; 808 };
809 809
810 &usbotg2 { 810 &usbotg2 {
811 dr_mode = "host"; 811 dr_mode = "host";
812 disable-over-current; 812 disable-over-current;
813 status = "okay"; 813 status = "okay";
814 }; 814 };
815 815
816 &usdhc1 { 816 &usdhc1 {
817 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 817 pinctrl-names = "default", "state_100mhz", "state_200mhz";
818 pinctrl-0 = <&pinctrl_usdhc1>; 818 pinctrl-0 = <&pinctrl_usdhc1>;
819 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 819 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
820 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 820 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
821 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 821 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
822 keep-power-in-suspend; 822 keep-power-in-suspend;
823 enable-sdio-wakeup; 823 enable-sdio-wakeup;
824 vmmc-supply = <&reg_sd1_vmmc>; 824 vmmc-supply = <&reg_sd1_vmmc>;
825 status = "okay"; 825 status = "okay";
826 }; 826 };
827 827
828 &usdhc2 { 828 &usdhc2 {
829 pinctrl-names = "default"; 829 pinctrl-names = "default";
830 pinctrl-0 = <&pinctrl_usdhc2>; 830 pinctrl-0 = <&pinctrl_usdhc2>;
831 no-1-8-v; 831 no-1-8-v;
832 non-removable; 832 non-removable;
833 keep-power-in-suspend; 833 keep-power-in-suspend;
834 enable-sdio-wakeup; 834 enable-sdio-wakeup;
835 status = "okay"; 835 status = "okay";
836 }; 836 };
837 837
838 &wdog1 { 838 &wdog1 {
839 pinctrl-names = "default"; 839 pinctrl-names = "default";
840 pinctrl-0 = <&pinctrl_wdog>; 840 pinctrl-0 = <&pinctrl_wdog>;
841 fsl,ext-reset-output; 841 fsl,ext-reset-output;
842 }; 842 };
843 843
arch/arm/dts/imx6ull-14x14-ddr3-arm2.dts
Diff comments   View file @ 4daafb3
1 /* 1 /*
2 * Copyright (C) 2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/input/input.h>
12 #include "imx6ull.dtsi" 12 #include "imx6ull.dtsi"
13 13
14 / { 14 / {
15 model = "Freescale i.MX6 ULL DDR3 ARM2 Board"; 15 model = "Freescale i.MX6 ULL DDR3 ARM2 Board";
16 compatible = "fsl,imx6ull-ddr3-arm2", "fsl,imx6ull"; 16 compatible = "fsl,imx6ull-ddr3-arm2", "fsl,imx6ull";
17 17
18 chosen { 18 chosen {
19 stdout-path = &uart1; 19 stdout-path = &uart1;
20 }; 20 };
21 21
22 memory { 22 memory {
23 reg = <0x80000000 0x40000000>; 23 reg = <0x80000000 0x40000000>;
24 }; 24 };
25 25
26 backlight { 26 backlight {
27 compatible = "pwm-backlight"; 27 compatible = "pwm-backlight";
28 pwms = <&pwm1 0 5000000>; 28 pwms = <&pwm1 0 5000000>;
29 brightness-levels = <0 4 8 16 32 64 128 255>; 29 brightness-levels = <0 4 8 16 32 64 128 255>;
30 default-brightness-level = <6>; 30 default-brightness-level = <6>;
31 status = "disabled"; 31 status = "disabled";
32 }; 32 };
33 33
34 pxp_v4l2 { 34 pxp_v4l2 {
35 compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; 35 compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
36 status = "okay"; 36 status = "okay";
37 }; 37 };
38 38
39 regulators { 39 regulators {
40 compatible = "simple-bus"; 40 compatible = "simple-bus";
41 #address-cells = <1>; 41 #address-cells = <1>;
42 #size-cells = <0>; 42 #size-cells = <0>;
43 43
44 reg_sd1_vmmc: sd1_vmmc { 44 reg_sd1_vmmc: sd1_vmmc {
45 compatible = "regulator-fixed"; 45 compatible = "regulator-fixed";
46 regulator-name = "SD1_SPWR"; 46 regulator-name = "SD1_SPWR";
47 regulator-min-microvolt = <3000000>; 47 regulator-min-microvolt = <3000000>;
48 regulator-max-microvolt = <3000000>; 48 regulator-max-microvolt = <3000000>;
49 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 49 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
50 off-on-delay = <20000>; 50 u-boot,off-on-delay-us = <20000>;
51 enable-active-high; 51 enable-active-high;
52 }; 52 };
53 53
54 reg_sd2_vmmc: sd2_vmmc { 54 reg_sd2_vmmc: sd2_vmmc {
55 compatible = "regulator-fixed"; 55 compatible = "regulator-fixed";
56 regulator-name = "SD2_SPWR"; 56 regulator-name = "SD2_SPWR";
57 regulator-min-microvolt = <3000000>; 57 regulator-min-microvolt = <3000000>;
58 regulator-max-microvolt = <3000000>; 58 regulator-max-microvolt = <3000000>;
59 gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; 59 gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
60 enable-active-high; 60 enable-active-high;
61 }; 61 };
62 62
63 reg_can2_3v3: regulator@0 { 63 reg_can2_3v3: regulator@0 {
64 compatible = "regulator-fixed"; 64 compatible = "regulator-fixed";
65 reg = <0>; 65 reg = <0>;
66 regulator-name = "can2-3v3"; 66 regulator-name = "can2-3v3";
67 regulator-min-microvolt = <3300000>; 67 regulator-min-microvolt = <3300000>;
68 regulator-max-microvolt = <3300000>; 68 regulator-max-microvolt = <3300000>;
69 gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; 69 gpio = <&gpio1 15 GPIO_ACTIVE_LOW>;
70 }; 70 };
71 71
72 reg_vref_3v3: regulator@1 { 72 reg_vref_3v3: regulator@1 {
73 compatible = "regulator-fixed"; 73 compatible = "regulator-fixed";
74 regulator-name = "vref-3v3"; 74 regulator-name = "vref-3v3";
75 regulator-min-microvolt = <3300000>; 75 regulator-min-microvolt = <3300000>;
76 regulator-max-microvolt = <3300000>; 76 regulator-max-microvolt = <3300000>;
77 }; 77 };
78 78
79 reg_usb_otg1_vbus: regulator@2 { 79 reg_usb_otg1_vbus: regulator@2 {
80 compatible = "regulator-fixed"; 80 compatible = "regulator-fixed";
81 reg = <2>; 81 reg = <2>;
82 pinctrl-names = "default"; 82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_usb_otg1>; 83 pinctrl-0 = <&pinctrl_usb_otg1>;
84 regulator-name = "usb_otg1_vbus"; 84 regulator-name = "usb_otg1_vbus";
85 regulator-min-microvolt = <5000000>; 85 regulator-min-microvolt = <5000000>;
86 regulator-max-microvolt = <5000000>; 86 regulator-max-microvolt = <5000000>;
87 gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; 87 gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
88 enable-active-high; 88 enable-active-high;
89 }; 89 };
90 }; 90 };
91 }; 91 };
92 92
93 &clks { 93 &clks {
94 /* For bringup, comments this. 94 /* For bringup, comments this.
95 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 95 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
96 assigned-clock-rates = <786432000>; 96 assigned-clock-rates = <786432000>;
97 */ 97 */
98 }; 98 };
99 99
100 &cpu0 { 100 &cpu0 {
101 /* 101 /*
102 * on i.MX6ULL, no seperated VDD_ARM_IN and VDD_SOC_IN, 102 * on i.MX6ULL, no seperated VDD_ARM_IN and VDD_SOC_IN,
103 * to align with other platform and use the same cpufreq 103 * to align with other platform and use the same cpufreq
104 * driver, still use the seperated OPP define for arm 104 * driver, still use the seperated OPP define for arm
105 * and soc. 105 * and soc.
106 */ 106 */
107 operating-points = < 107 operating-points = <
108 /* kHz uV */ 108 /* kHz uV */
109 528000 1175000 109 528000 1175000
110 396000 1175000 110 396000 1175000
111 198000 1175000 111 198000 1175000
112 >; 112 >;
113 fsl,soc-operating-points = < 113 fsl,soc-operating-points = <
114 /* KHz uV */ 114 /* KHz uV */
115 528000 1175000 115 528000 1175000
116 396000 1175000 116 396000 1175000
117 198000 1175000 117 198000 1175000
118 >; 118 >;
119 fsl,arm-soc-shared = <1>; 119 fsl,arm-soc-shared = <1>;
120 }; 120 };
121 121
122 &reg_arm { 122 &reg_arm {
123 vin-supply = <&sw1a_reg>; 123 vin-supply = <&sw1a_reg>;
124 regulator-allow-bypass; 124 regulator-allow-bypass;
125 }; 125 };
126 126
127 &reg_soc { 127 &reg_soc {
128 vin-supply = <&sw1a_reg>; 128 vin-supply = <&sw1a_reg>;
129 regulator-allow-bypass; 129 regulator-allow-bypass;
130 }; 130 };
131 131
132 &csi { 132 &csi {
133 status = "okay"; 133 status = "okay";
134 134
135 port { 135 port {
136 csi1_ep: endpoint { 136 csi1_ep: endpoint {
137 remote-endpoint = <&ov5640_ep>; 137 remote-endpoint = <&ov5640_ep>;
138 }; 138 };
139 }; 139 };
140 }; 140 };
141 141
142 &ecspi1 { 142 &ecspi1 {
143 fsl,spi-num-chipselects = <1>; 143 fsl,spi-num-chipselects = <1>;
144 cs-gpios = <&gpio4 26 0>; 144 cs-gpios = <&gpio4 26 0>;
145 pinctrl-names = "default"; 145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; 146 pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>;
147 status = "disabled"; 147 status = "disabled";
148 148
149 flash: n25q032@0 { 149 flash: n25q032@0 {
150 #address-cells = <1>; 150 #address-cells = <1>;
151 #size-cells = <1>; 151 #size-cells = <1>;
152 compatible = "st,n25q032", "jedec,spi-nor"; 152 compatible = "st,n25q032", "jedec,spi-nor";
153 spi-max-frequency = <20000000>; 153 spi-max-frequency = <20000000>;
154 reg = <0>; 154 reg = <0>;
155 }; 155 };
156 }; 156 };
157 157
158 &epdc { 158 &epdc {
159 pinctrl-names = "default"; 159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_epdc0>; 160 pinctrl-0 = <&pinctrl_epdc0>;
161 V3P3-supply = <&V3P3_reg>; 161 V3P3-supply = <&V3P3_reg>;
162 VCOM-supply = <&VCOM_reg>; 162 VCOM-supply = <&VCOM_reg>;
163 DISPLAY-supply = <&DISPLAY_reg>; 163 DISPLAY-supply = <&DISPLAY_reg>;
164 status = "disabled"; 164 status = "disabled";
165 }; 165 };
166 166
167 &fec1 { 167 &fec1 {
168 pinctrl-names = "default"; 168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_enet1>; 169 pinctrl-0 = <&pinctrl_enet1>;
170 phy-mode = "rmii"; 170 phy-mode = "rmii";
171 phy-handle = <&ethphy0>; 171 phy-handle = <&ethphy0>;
172 status = "okay"; 172 status = "okay";
173 }; 173 };
174 174
175 &fec2 { 175 &fec2 {
176 pinctrl-names = "default"; 176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_enet2>; 177 pinctrl-0 = <&pinctrl_enet2>;
178 phy-mode = "mii"; 178 phy-mode = "mii";
179 phy-handle = <&ethphy1>; 179 phy-handle = <&ethphy1>;
180 status = "okay"; 180 status = "okay";
181 181
182 mdio { 182 mdio {
183 #address-cells = <1>; 183 #address-cells = <1>;
184 #size-cells = <0>; 184 #size-cells = <0>;
185 185
186 ethphy0: ethernet-phy@1 { 186 ethphy0: ethernet-phy@1 {
187 compatible = "ethernet-phy-ieee802.3-c22"; 187 compatible = "ethernet-phy-ieee802.3-c22";
188 reg = <1>; 188 reg = <1>;
189 }; 189 };
190 190
191 ethphy1: ethernet-phy@2 { 191 ethphy1: ethernet-phy@2 {
192 compatible = "ethernet-phy-ieee802.3-c22"; 192 compatible = "ethernet-phy-ieee802.3-c22";
193 reg = <2>; 193 reg = <2>;
194 }; 194 };
195 }; 195 };
196 }; 196 };
197 197
198 &flexcan2 { 198 &flexcan2 {
199 pinctrl-names = "default"; 199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_flexcan2>; 200 pinctrl-0 = <&pinctrl_flexcan2>;
201 xceiver-supply = <&reg_can2_3v3>; 201 xceiver-supply = <&reg_can2_3v3>;
202 status = "disabled"; 202 status = "disabled";
203 }; 203 };
204 204
205 &gpc { 205 &gpc {
206 fsl,cpu_pupscr_sw2iso = <0xf>; 206 fsl,cpu_pupscr_sw2iso = <0xf>;
207 fsl,cpu_pupscr_sw = <0x0>; 207 fsl,cpu_pupscr_sw = <0x0>;
208 fsl,cpu_pdnscr_iso2sw = <0x1>; 208 fsl,cpu_pdnscr_iso2sw = <0x1>;
209 fsl,cpu_pdnscr_iso = <0x1>; 209 fsl,cpu_pdnscr_iso = <0x1>;
210 fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ 210 fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
211 }; 211 };
212 212
213 &gpmi { 213 &gpmi {
214 pinctrl-names = "default"; 214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_gpmi_nand_1>; 215 pinctrl-0 = <&pinctrl_gpmi_nand_1>;
216 status = "disabled"; 216 status = "disabled";
217 nand-on-flash-bbt; 217 nand-on-flash-bbt;
218 }; 218 };
219 219
220 &i2c1 { 220 &i2c1 {
221 clock-frequency = <100000>; 221 clock-frequency = <100000>;
222 pinctrl-names = "default", "gpio"; 222 pinctrl-names = "default", "gpio";
223 pinctrl-0 = <&pinctrl_i2c1>; 223 pinctrl-0 = <&pinctrl_i2c1>;
224 pinctrl-1 = <&pinctrl_i2c1_gpio>; 224 pinctrl-1 = <&pinctrl_i2c1_gpio>;
225 scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 225 scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
226 sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 226 sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
227 status = "okay"; 227 status = "okay";
228 228
229 pmic: pfuze100@08 { 229 pmic: pfuze100@08 {
230 compatible = "fsl,pfuze200"; 230 compatible = "fsl,pfuze200";
231 reg = <0x08>; 231 reg = <0x08>;
232 232
233 regulators { 233 regulators {
234 sw1a_reg: sw1ab { 234 sw1a_reg: sw1ab {
235 regulator-min-microvolt = <300000>; 235 regulator-min-microvolt = <300000>;
236 regulator-max-microvolt = <1875000>; 236 regulator-max-microvolt = <1875000>;
237 regulator-always-on; 237 regulator-always-on;
238 regulator-ramp-delay = <6250>; 238 regulator-ramp-delay = <6250>;
239 }; 239 };
240 240
241 sw2_reg: sw2 { 241 sw2_reg: sw2 {
242 regulator-min-microvolt = <800000>; 242 regulator-min-microvolt = <800000>;
243 regulator-max-microvolt = <3300000>; 243 regulator-max-microvolt = <3300000>;
244 regulator-always-on; 244 regulator-always-on;
245 }; 245 };
246 246
247 sw3a_reg: sw3a { 247 sw3a_reg: sw3a {
248 regulator-min-microvolt = <400000>; 248 regulator-min-microvolt = <400000>;
249 regulator-max-microvolt = <1975000>; 249 regulator-max-microvolt = <1975000>;
250 regulator-always-on; 250 regulator-always-on;
251 }; 251 };
252 252
253 sw3b_reg: sw3b { 253 sw3b_reg: sw3b {
254 regulator-min-microvolt = <800000>; 254 regulator-min-microvolt = <800000>;
255 regulator-max-microvolt = <3300000>; 255 regulator-max-microvolt = <3300000>;
256 regulator-always-on; 256 regulator-always-on;
257 }; 257 };
258 258
259 swbst_reg: swbst { 259 swbst_reg: swbst {
260 regulator-min-microvolt = <5000000>; 260 regulator-min-microvolt = <5000000>;
261 regulator-max-microvolt = <5150000>; 261 regulator-max-microvolt = <5150000>;
262 }; 262 };
263 263
264 snvs_reg: vsnvs { 264 snvs_reg: vsnvs {
265 regulator-min-microvolt = <1000000>; 265 regulator-min-microvolt = <1000000>;
266 regulator-max-microvolt = <3000000>; 266 regulator-max-microvolt = <3000000>;
267 regulator-always-on; 267 regulator-always-on;
268 }; 268 };
269 269
270 vref_reg: vrefddr { 270 vref_reg: vrefddr {
271 regulator-always-on; 271 regulator-always-on;
272 }; 272 };
273 273
274 vgen1_reg: vgen1 { 274 vgen1_reg: vgen1 {
275 regulator-min-microvolt = <800000>; 275 regulator-min-microvolt = <800000>;
276 regulator-max-microvolt = <1550000>; 276 regulator-max-microvolt = <1550000>;
277 }; 277 };
278 278
279 vgen2_reg: vgen2 { 279 vgen2_reg: vgen2 {
280 regulator-min-microvolt = <800000>; 280 regulator-min-microvolt = <800000>;
281 regulator-max-microvolt = <1550000>; 281 regulator-max-microvolt = <1550000>;
282 }; 282 };
283 283
284 vgen3_reg: vgen3 { 284 vgen3_reg: vgen3 {
285 regulator-min-microvolt = <1800000>; 285 regulator-min-microvolt = <1800000>;
286 regulator-max-microvolt = <3300000>; 286 regulator-max-microvolt = <3300000>;
287 }; 287 };
288 288
289 vgen4_reg: vgen4 { 289 vgen4_reg: vgen4 {
290 regulator-min-microvolt = <1800000>; 290 regulator-min-microvolt = <1800000>;
291 regulator-max-microvolt = <3300000>; 291 regulator-max-microvolt = <3300000>;
292 regulator-always-on; 292 regulator-always-on;
293 }; 293 };
294 294
295 vgen5_reg: vgen5 { 295 vgen5_reg: vgen5 {
296 regulator-min-microvolt = <1800000>; 296 regulator-min-microvolt = <1800000>;
297 regulator-max-microvolt = <3300000>; 297 regulator-max-microvolt = <3300000>;
298 regulator-always-on; 298 regulator-always-on;
299 }; 299 };
300 300
301 vgen6_reg: vgen6 { 301 vgen6_reg: vgen6 {
302 regulator-min-microvolt = <1800000>; 302 regulator-min-microvolt = <1800000>;
303 regulator-max-microvolt = <3300000>; 303 regulator-max-microvolt = <3300000>;
304 regulator-always-on; 304 regulator-always-on;
305 }; 305 };
306 }; 306 };
307 }; 307 };
308 308
309 309
310 ov5640: ov5640@3c { 310 ov5640: ov5640@3c {
311 compatible = "ovti,ov5640"; 311 compatible = "ovti,ov5640";
312 reg = <0x3c>; 312 reg = <0x3c>;
313 pinctrl-names = "default"; 313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_csi1>; 314 pinctrl-0 = <&pinctrl_csi1>;
315 clocks = <&clks IMX6UL_CLK_CSI>; 315 clocks = <&clks IMX6UL_CLK_CSI>;
316 clock-names = "csi_mclk"; 316 clock-names = "csi_mclk";
317 AVDD-supply = <&vgen3_reg>; /* 2.8v */ 317 AVDD-supply = <&vgen3_reg>; /* 2.8v */
318 DVDD-supply = <&vgen2_reg>; /* 1.5v*/ 318 DVDD-supply = <&vgen2_reg>; /* 1.5v*/
319 pwn-gpios = <&gpio5 8 1>; 319 pwn-gpios = <&gpio5 8 1>;
320 rst-gpios = <&gpio5 7 0>; 320 rst-gpios = <&gpio5 7 0>;
321 csi_id = <0>; 321 csi_id = <0>;
322 mclk = <24000000>; 322 mclk = <24000000>;
323 mclk_source = <0>; 323 mclk_source = <0>;
324 status = "okay"; 324 status = "okay";
325 port { 325 port {
326 ov5640_ep: endpoint { 326 ov5640_ep: endpoint {
327 remote-endpoint = <&csi1_ep>; 327 remote-endpoint = <&csi1_ep>;
328 }; 328 };
329 }; 329 };
330 }; 330 };
331 }; 331 };
332 332
333 &i2c4 { 333 &i2c4 {
334 clock-frequency = <100000>; 334 clock-frequency = <100000>;
335 pinctrl-names = "default", "gpio"; 335 pinctrl-names = "default", "gpio";
336 pinctrl-0 = <&pinctrl_i2c4>; 336 pinctrl-0 = <&pinctrl_i2c4>;
337 pinctrl-1 = <&pinctrl_i2c4_gpio>; 337 pinctrl-1 = <&pinctrl_i2c4_gpio>;
338 scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; 338 scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
339 sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; 339 sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
340 status = "okay"; 340 status = "okay";
341 341
342 max17135: max17135@48 { 342 max17135: max17135@48 {
343 pinctrl-names = "default"; 343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_max17135>; 344 pinctrl-0 = <&pinctrl_max17135>;
345 compatible = "maxim,max17135"; 345 compatible = "maxim,max17135";
346 reg = <0x48>; 346 reg = <0x48>;
347 status = "disabled"; 347 status = "disabled";
348 348
349 vneg_pwrup = <1>; 349 vneg_pwrup = <1>;
350 gvee_pwrup = <2>; 350 gvee_pwrup = <2>;
351 vpos_pwrup = <10>; 351 vpos_pwrup = <10>;
352 gvdd_pwrup = <12>; 352 gvdd_pwrup = <12>;
353 gvdd_pwrdn = <1>; 353 gvdd_pwrdn = <1>;
354 vpos_pwrdn = <2>; 354 vpos_pwrdn = <2>;
355 gvee_pwrdn = <8>; 355 gvee_pwrdn = <8>;
356 vneg_pwrdn = <10>; 356 vneg_pwrdn = <10>;
357 gpio_pmic_pwrgood = <&gpio3 16 0>; 357 gpio_pmic_pwrgood = <&gpio3 16 0>;
358 gpio_pmic_vcom_ctrl = <&gpio3 24 0>; 358 gpio_pmic_vcom_ctrl = <&gpio3 24 0>;
359 gpio_pmic_wakeup = <&gpio3 14 0>; 359 gpio_pmic_wakeup = <&gpio3 14 0>;
360 gpio_pmic_v3p3 = <&gpio3 17 0>; 360 gpio_pmic_v3p3 = <&gpio3 17 0>;
361 gpio_pmic_intr = <&gpio3 13 0>; 361 gpio_pmic_intr = <&gpio3 13 0>;
362 362
363 regulators { 363 regulators {
364 DISPLAY_reg: DISPLAY { 364 DISPLAY_reg: DISPLAY {
365 regulator-name = "DISPLAY"; 365 regulator-name = "DISPLAY";
366 }; 366 };
367 367
368 GVDD_reg: GVDD { 368 GVDD_reg: GVDD {
369 /* 20v */ 369 /* 20v */
370 regulator-name = "GVDD"; 370 regulator-name = "GVDD";
371 }; 371 };
372 372
373 GVEE_reg: GVEE { 373 GVEE_reg: GVEE {
374 /* -22v */ 374 /* -22v */
375 regulator-name = "GVEE"; 375 regulator-name = "GVEE";
376 }; 376 };
377 377
378 HVINN_reg: HVINN { 378 HVINN_reg: HVINN {
379 /* -22v */ 379 /* -22v */
380 regulator-name = "HVINN"; 380 regulator-name = "HVINN";
381 }; 381 };
382 382
383 HVINP_reg: HVINP { 383 HVINP_reg: HVINP {
384 /* 20v */ 384 /* 20v */
385 regulator-name = "HVINP"; 385 regulator-name = "HVINP";
386 }; 386 };
387 387
388 VCOM_reg: VCOM { 388 VCOM_reg: VCOM {
389 regulator-name = "VCOM"; 389 regulator-name = "VCOM";
390 /* Real max: -500000 */ 390 /* Real max: -500000 */
391 regulator-max-microvolt = <4325000>; 391 regulator-max-microvolt = <4325000>;
392 /* Real min: -4325000 */ 392 /* Real min: -4325000 */
393 regulator-min-microvolt = <500000>; 393 regulator-min-microvolt = <500000>;
394 }; 394 };
395 395
396 VNEG_reg: VNEG { 396 VNEG_reg: VNEG {
397 /* -15v */ 397 /* -15v */
398 regulator-name = "VNEG"; 398 regulator-name = "VNEG";
399 }; 399 };
400 400
401 VPOS_reg: VPOS { 401 VPOS_reg: VPOS {
402 /* 15v */ 402 /* 15v */
403 regulator-name = "VPOS"; 403 regulator-name = "VPOS";
404 }; 404 };
405 405
406 V3P3_reg: V3P3 { 406 V3P3_reg: V3P3 {
407 regulator-name = "V3P3"; 407 regulator-name = "V3P3";
408 }; 408 };
409 }; 409 };
410 }; 410 };
411 }; 411 };
412 412
413 &iomuxc { 413 &iomuxc {
414 imx6ul-ddr3-arm2 { 414 imx6ul-ddr3-arm2 {
415 pinctrl_adc1: adc1grp { 415 pinctrl_adc1: adc1grp {
416 fsl,pins = < 416 fsl,pins = <
417 MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 417 MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0
418 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 418 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
419 >; 419 >;
420 }; 420 };
421 421
422 422
423 pinctrl_csi1: csi1grp { 423 pinctrl_csi1: csi1grp {
424 fsl,pins = < 424 fsl,pins = <
425 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 425 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
426 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 426 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
427 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 427 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
428 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 428 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
429 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 429 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
430 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 430 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
431 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 431 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
432 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 432 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
433 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 433 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
434 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 434 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
435 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 435 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
436 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 436 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
437 >; 437 >;
438 }; 438 };
439 439
440 pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { 440 pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 {
441 fsl,pins = < 441 fsl,pins = <
442 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 442 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0
443 >; 443 >;
444 }; 444 };
445 445
446 pinctrl_ecspi1_1: ecspi1grp-1 { 446 pinctrl_ecspi1_1: ecspi1grp-1 {
447 fsl,pins = < 447 fsl,pins = <
448 MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x10b0 448 MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x10b0
449 MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x10b0 449 MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x10b0
450 MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x10b0 450 MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x10b0
451 >; 451 >;
452 }; 452 };
453 453
454 pinctrl_enet1: enet1grp { 454 pinctrl_enet1: enet1grp {
455 fsl,pins = < 455 fsl,pins = <
456 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 456 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
457 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 457 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
458 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 458 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
459 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 459 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
460 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 460 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
461 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 461 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
462 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 462 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
463 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a0 463 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a0
464 >; 464 >;
465 }; 465 };
466 466
467 pinctrl_enet2: enet2grp { 467 pinctrl_enet2: enet2grp {
468 fsl,pins = < 468 fsl,pins = <
469 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b098 469 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b098
470 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 470 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
471 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0 471 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0
472 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0 472 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0
473 MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x1b0a0 473 MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x1b0a0
474 MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x1b0a0 474 MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x1b0a0
475 MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x4001b0a8 475 MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x4001b0a8
476 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 476 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
477 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 477 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
478 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 478 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
479 MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x1b0b0 479 MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x1b0b0
480 MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x1b0b0 480 MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x1b0b0
481 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 481 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
482 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 482 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
483 MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8 483 MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8
484 MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0 484 MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0
485 MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0 485 MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0
486 >; 486 >;
487 }; 487 };
488 488
489 pinctrl_epdc0: epdcgrp0 { 489 pinctrl_epdc0: epdcgrp0 {
490 fsl,pins = < 490 fsl,pins = <
491 MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x10b1 491 MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x10b1
492 MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x10b1 492 MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x10b1
493 MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x10b1 493 MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x10b1
494 MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x10b1 494 MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x10b1
495 MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x10b1 495 MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x10b1
496 MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x10b1 496 MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x10b1
497 MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x10b1 497 MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x10b1
498 MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x10b1 498 MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x10b1
499 MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x10b1 499 MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x10b1
500 MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x10b1 500 MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x10b1
501 MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x10b1 501 MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x10b1
502 MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x10b1 502 MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x10b1
503 MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x10b1 503 MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x10b1
504 MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x10b1 504 MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x10b1
505 MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x10b1 505 MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x10b1
506 MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x10b1 506 MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x10b1
507 MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x10b1 507 MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x10b1
508 MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x10b1 508 MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x10b1
509 MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x10b1 509 MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x10b1
510 MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x10b1 510 MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x10b1
511 MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x10b1 511 MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x10b1
512 MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x10b1 512 MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x10b1
513 MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x10b1 513 MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x10b1
514 MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x10b1 514 MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x10b1
515 MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x10b1 515 MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x10b1
516 >; 516 >;
517 }; 517 };
518 518
519 pinctrl_esai: esaigrp { 519 pinctrl_esai: esaigrp {
520 fsl,pins = < 520 fsl,pins = <
521 MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x1b0b0 521 MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x1b0b0
522 MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x1b0b0 522 MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x1b0b0
523 MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x1b0b0 523 MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x1b0b0
524 MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x1b0b0 524 MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x1b0b0
525 MX6ULL_PAD_CSI_DATA07__ESAI_T0 0x1b0b0 525 MX6ULL_PAD_CSI_DATA07__ESAI_T0 0x1b0b0
526 MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x1b0b0 526 MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x1b0b0
527 MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x1b0b0 527 MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x1b0b0
528 MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x1b0b0 528 MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x1b0b0
529 MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x1b0b0 529 MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x1b0b0
530 MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x1b0b0 530 MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x1b0b0
531 MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x1b0b0 531 MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x1b0b0
532 MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x1b0b0 532 MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x1b0b0
533 >; 533 >;
534 }; 534 };
535 535
536 pinctrl_flexcan2: flexcan2grp{ 536 pinctrl_flexcan2: flexcan2grp{
537 fsl,pins = < 537 fsl,pins = <
538 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 538 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
539 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 539 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
540 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */ 540 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */
541 >; 541 >;
542 }; 542 };
543 543
544 pinctrl_gpmi_nand_1: gpmi-nand-1 { 544 pinctrl_gpmi_nand_1: gpmi-nand-1 {
545 fsl,pins = < 545 fsl,pins = <
546 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 546 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
547 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 547 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
548 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 548 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
549 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 549 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
550 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 550 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
551 MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 551 MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
552 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 552 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
553 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 553 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
554 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 554 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
555 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 555 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
556 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 556 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
557 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 557 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
558 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 558 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
559 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 559 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
560 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 560 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
561 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 561 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
562 >; 562 >;
563 }; 563 };
564 564
565 pinctrl_i2c1: i2c1grp { 565 pinctrl_i2c1: i2c1grp {
566 fsl,pins = < 566 fsl,pins = <
567 MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1 567 MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1
568 MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1 568 MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1
569 >; 569 >;
570 }; 570 };
571 571
572 pinctrl_i2c1_gpio: i2c1grp_gpio { 572 pinctrl_i2c1_gpio: i2c1grp_gpio {
573 fsl,pins = < 573 fsl,pins = <
574 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x1b8b1 574 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x1b8b1
575 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b8b1 575 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b8b1
576 >; 576 >;
577 }; 577 };
578 578
579 pinctrl_i2c4: i2c4grp { 579 pinctrl_i2c4: i2c4grp {
580 fsl,pins = < 580 fsl,pins = <
581 MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0 581 MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0
582 MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0 582 MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0
583 >; 583 >;
584 }; 584 };
585 585
586 pinctrl_i2c4_gpio: i2c4grp_gpio { 586 pinctrl_i2c4_gpio: i2c4grp_gpio {
587 fsl,pins = < 587 fsl,pins = <
588 MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x1b8b0 588 MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x1b8b0
589 MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x1b8b0 589 MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x1b8b0
590 >; 590 >;
591 }; 591 };
592 592
593 pinctrl_lcdif_dat: lcdifdatgrp { 593 pinctrl_lcdif_dat: lcdifdatgrp {
594 fsl,pins = < 594 fsl,pins = <
595 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 595 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
596 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 596 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
597 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 597 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
598 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 598 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
599 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 599 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
600 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 600 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
601 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 601 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
602 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 602 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
603 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 603 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
604 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 604 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
605 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 605 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
606 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 606 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
607 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 607 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
608 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 608 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
609 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 609 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
610 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 610 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
611 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 611 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
612 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 612 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
613 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 613 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
614 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 614 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
615 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 615 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
616 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 616 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
617 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 617 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
618 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 618 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
619 >; 619 >;
620 }; 620 };
621 621
622 pinctrl_lcdif_ctrl: lcdifctrlgrp { 622 pinctrl_lcdif_ctrl: lcdifctrlgrp {
623 fsl,pins = < 623 fsl,pins = <
624 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 624 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
625 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 625 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
626 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 626 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
627 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 627 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
628 MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 628 MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79
629 >; 629 >;
630 }; 630 };
631 631
632 pinctrl_max17135: max17135grp-1 { 632 pinctrl_max17135: max17135grp-1 {
633 fsl,pins = < 633 fsl,pins = <
634 MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x80000000 /* pwrgood */ 634 MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x80000000 /* pwrgood */
635 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x80000000 /* vcom_ctrl */ 635 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x80000000 /* vcom_ctrl */
636 MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x80000000 /* wakeup */ 636 MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x80000000 /* wakeup */
637 MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x80000000 /* v3p3 */ 637 MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x80000000 /* v3p3 */
638 MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x80000000 /* pwr int */ 638 MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x80000000 /* pwr int */
639 >; 639 >;
640 }; 640 };
641 641
642 pinctrl_mqs: mqsgrp { 642 pinctrl_mqs: mqsgrp {
643 fsl,pins = < 643 fsl,pins = <
644 MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x11088 644 MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x11088
645 MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x11088 645 MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x11088
646 >; 646 >;
647 }; 647 };
648 648
649 pinctrl_pwm1: pmw1grp { 649 pinctrl_pwm1: pmw1grp {
650 fsl,pins = < 650 fsl,pins = <
651 MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x110b0 651 MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x110b0
652 >; 652 >;
653 }; 653 };
654 654
655 pinctrl_qspi: qspigrp { 655 pinctrl_qspi: qspigrp {
656 fsl,pins = < 656 fsl,pins = <
657 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 657 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
658 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 658 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
659 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 659 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
660 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 660 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
661 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 661 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
662 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 662 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
663 #ifdef REWORKED_ENABLE_ALL_QSPI 663 #ifdef REWORKED_ENABLE_ALL_QSPI
664 MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1 664 MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1
665 MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1 665 MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1
666 MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1 666 MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1
667 MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1 667 MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1
668 MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1 668 MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1
669 MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1 669 MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1
670 MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1 670 MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1
671 MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1 671 MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1
672 #endif 672 #endif
673 >; 673 >;
674 }; 674 };
675 675
676 pinctrl_sai2: sai2grp { 676 pinctrl_sai2: sai2grp {
677 fsl,pins = < 677 fsl,pins = <
678 MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x1b0b0 678 MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x1b0b0
679 MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x1b0b0 679 MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x1b0b0
680 MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x110b0 680 MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x110b0
681 MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x110b0 681 MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x110b0
682 MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x1b0b0 682 MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x1b0b0
683 >; 683 >;
684 }; 684 };
685 685
686 pinctrl_spdif: spdifgrp { 686 pinctrl_spdif: spdifgrp {
687 fsl,pins = < 687 fsl,pins = <
688 MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x1b0b0 688 MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x1b0b0
689 MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x1b0b0 689 MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x1b0b0
690 >; 690 >;
691 }; 691 };
692 692
693 pinctrl_tsc: tscgrp { 693 pinctrl_tsc: tscgrp {
694 fsl,pins = < 694 fsl,pins = <
695 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 695 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
696 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 696 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
697 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 697 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
698 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 698 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
699 >; 699 >;
700 }; 700 };
701 701
702 pinctrl_uart1: uart1grp { 702 pinctrl_uart1: uart1grp {
703 fsl,pins = < 703 fsl,pins = <
704 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 704 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
705 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 705 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
706 >; 706 >;
707 }; 707 };
708 708
709 pinctrl_uart2: uart2grp { 709 pinctrl_uart2: uart2grp {
710 fsl,pins = < 710 fsl,pins = <
711 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 711 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
712 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 712 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
713 MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 713 MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
714 MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 714 MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
715 >; 715 >;
716 }; 716 };
717 717
718 pinctrl_uart2dte: uart2dtegrp { 718 pinctrl_uart2dte: uart2dtegrp {
719 fsl,pins = < 719 fsl,pins = <
720 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 720 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
721 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 721 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
722 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 722 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1
723 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 723 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1
724 >; 724 >;
725 }; 725 };
726 726
727 pinctrl_usb_otg1_id: usbotg1idgrp { 727 pinctrl_usb_otg1_id: usbotg1idgrp {
728 fsl,pins = < 728 fsl,pins = <
729 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 729 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
730 >; 730 >;
731 }; 731 };
732 732
733 pinctrl_usb_otg1: usbotg1grp { 733 pinctrl_usb_otg1: usbotg1grp {
734 fsl,pins = < 734 fsl,pins = <
735 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0 735 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0
736 >; 736 >;
737 }; 737 };
738 738
739 pinctrl_usdhc1: usdhc1grp { 739 pinctrl_usdhc1: usdhc1grp {
740 fsl,pins = < 740 fsl,pins = <
741 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 741 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
742 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 742 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
743 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 743 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
744 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 744 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
745 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 745 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
746 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 746 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
747 >; 747 >;
748 }; 748 };
749 749
750 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 750 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
751 fsl,pins = < 751 fsl,pins = <
752 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 752 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
753 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 753 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
754 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 754 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
755 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 755 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
756 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 756 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
757 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 757 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
758 >; 758 >;
759 }; 759 };
760 760
761 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 761 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
762 fsl,pins = < 762 fsl,pins = <
763 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 763 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
764 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 764 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
765 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 765 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
766 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 766 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
767 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 767 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
768 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 768 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
769 >; 769 >;
770 }; 770 };
771 771
772 pinctrl_usdhc1_8bit: usdhc1_8bit_grp { 772 pinctrl_usdhc1_8bit: usdhc1_8bit_grp {
773 fsl,pins = < 773 fsl,pins = <
774 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 774 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
775 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 775 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
776 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 776 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
777 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 777 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
778 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 778 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
779 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 779 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
780 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 780 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
781 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 781 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
782 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 782 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
783 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 783 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
784 >; 784 >;
785 }; 785 };
786 786
787 pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp { 787 pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp {
788 fsl,pins = < 788 fsl,pins = <
789 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 789 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
790 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 790 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
791 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 791 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
792 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 792 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
793 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 793 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
794 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 794 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
795 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9 795 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9
796 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9 796 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9
797 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9 797 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9
798 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9 798 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9
799 >; 799 >;
800 }; 800 };
801 801
802 pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp { 802 pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp {
803 fsl,pins = < 803 fsl,pins = <
804 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 804 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
805 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 805 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
806 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 806 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
807 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 807 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
808 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 808 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
809 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 809 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
810 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9 810 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9
811 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9 811 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9
812 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9 812 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9
813 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9 813 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9
814 >; 814 >;
815 }; 815 };
816 816
817 pinctrl_usdhc1_cd_wp: usdhc1_cd_wp_grp { 817 pinctrl_usdhc1_cd_wp: usdhc1_cd_wp_grp {
818 fsl,pins = < 818 fsl,pins = <
819 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ 819 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
820 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 /* SD1 WP */ 820 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 /* SD1 WP */
821 >; 821 >;
822 }; 822 };
823 823
824 pinctrl_usdhc1_rst: usdhc1_rst_grp { 824 pinctrl_usdhc1_rst: usdhc1_rst_grp {
825 fsl,pins = < 825 fsl,pins = <
826 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ 826 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
827 >; 827 >;
828 }; 828 };
829 829
830 pinctrl_usdhc1_vselect: usdhc1_vselect_grp { 830 pinctrl_usdhc1_vselect: usdhc1_vselect_grp {
831 fsl,pins = < 831 fsl,pins = <
832 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ 832 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
833 >; 833 >;
834 }; 834 };
835 835
836 pinctrl_usdhc2: usdhc2grp { 836 pinctrl_usdhc2: usdhc2grp {
837 fsl,pins = < 837 fsl,pins = <
838 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 838 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
839 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 839 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
840 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 840 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
841 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 841 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
842 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 842 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
843 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 843 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
844 >; 844 >;
845 }; 845 };
846 846
847 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 847 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
848 fsl,pins = < 848 fsl,pins = <
849 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 849 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
850 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100a9 850 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100a9
851 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170a9 851 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170a9
852 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170a9 852 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170a9
853 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170a9 853 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170a9
854 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170a9 854 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170a9
855 >; 855 >;
856 }; 856 };
857 857
858 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 858 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
859 fsl,pins = < 859 fsl,pins = <
860 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 860 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
861 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 861 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
862 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 862 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
863 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 863 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
864 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 864 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
865 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 865 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
866 >; 866 >;
867 }; 867 };
868 868
869 pinctrl_usdhc2_rst: usdhc2_rst_grp { 869 pinctrl_usdhc2_rst: usdhc2_rst_grp {
870 fsl,pins = < 870 fsl,pins = <
871 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESET */ 871 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESET */
872 >; 872 >;
873 }; 873 };
874 874
875 pinctrl_wdog: wdoggrp { 875 pinctrl_wdog: wdoggrp {
876 fsl,pins = < 876 fsl,pins = <
877 MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x30b0 877 MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x30b0
878 >; 878 >;
879 }; 879 };
880 }; 880 };
881 }; 881 };
882 882
883 &iomuxc_snvs { 883 &iomuxc_snvs {
884 imx6ul-ddr3-arm2 { 884 imx6ul-ddr3-arm2 {
885 pinctrl_bt: btgrp { 885 pinctrl_bt: btgrp {
886 fsl,pins = < 886 fsl,pins = <
887 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x80000000 887 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x80000000
888 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x80000000 888 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x80000000
889 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x80000000 889 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x80000000
890 >; 890 >;
891 }; 891 };
892 892
893 pinctrl_sai2_hp_det_b: sai2_hp_det_grp { 893 pinctrl_sai2_hp_det_b: sai2_hp_det_grp {
894 fsl,pins = < 894 fsl,pins = <
895 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 895 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059
896 >; 896 >;
897 }; 897 };
898 }; 898 };
899 }; 899 };
900 900
901 &lcdif { 901 &lcdif {
902 pinctrl-names = "default"; 902 pinctrl-names = "default";
903 pinctrl-0 = <&pinctrl_lcdif_dat 903 pinctrl-0 = <&pinctrl_lcdif_dat
904 &pinctrl_lcdif_ctrl>; 904 &pinctrl_lcdif_ctrl>;
905 display = <&display0>; 905 display = <&display0>;
906 status = "disabled"; 906 status = "disabled";
907 907
908 display0: display { 908 display0: display {
909 bits-per-pixel = <16>; 909 bits-per-pixel = <16>;
910 bus-width = <24>; 910 bus-width = <24>;
911 911
912 display-timings { 912 display-timings {
913 native-mode = <&timing0>; 913 native-mode = <&timing0>;
914 timing0: timing0 { 914 timing0: timing0 {
915 clock-frequency = <33500000>; 915 clock-frequency = <33500000>;
916 hactive = <800>; 916 hactive = <800>;
917 vactive = <480>; 917 vactive = <480>;
918 hback-porch = <89>; 918 hback-porch = <89>;
919 hfront-porch = <164>; 919 hfront-porch = <164>;
920 vback-porch = <23>; 920 vback-porch = <23>;
921 vfront-porch = <10>; 921 vfront-porch = <10>;
922 hsync-len = <10>; 922 hsync-len = <10>;
923 vsync-len = <10>; 923 vsync-len = <10>;
924 hsync-active = <0>; 924 hsync-active = <0>;
925 vsync-active = <0>; 925 vsync-active = <0>;
926 de-active = <1>; 926 de-active = <1>;
927 pixelclk-active = <0>; 927 pixelclk-active = <0>;
928 }; 928 };
929 }; 929 };
930 }; 930 };
931 }; 931 };
932 932
933 &pwm1 { 933 &pwm1 {
934 pinctrl-names = "default"; 934 pinctrl-names = "default";
935 pinctrl-0 = <&pinctrl_pwm1>; 935 pinctrl-0 = <&pinctrl_pwm1>;
936 status = "disabled"; 936 status = "disabled";
937 }; 937 };
938 938
939 &pxp { 939 &pxp {
940 status = "okay"; 940 status = "okay";
941 }; 941 };
942 942
943 &qspi { 943 &qspi {
944 pinctrl-names = "default"; 944 pinctrl-names = "default";
945 pinctrl-0 = <&pinctrl_qspi>; 945 pinctrl-0 = <&pinctrl_qspi>;
946 status = "okay"; 946 status = "okay";
947 #ifdef REWORKED_ENABLE_ALL_QSPI 947 #ifdef REWORKED_ENABLE_ALL_QSPI
948 fsl,qspi-has-second-chip = <1>; 948 fsl,qspi-has-second-chip = <1>;
949 #endif 949 #endif
950 ddrsmp=<0>; 950 ddrsmp=<0>;
951 951
952 flash0: n25q256a@0 { 952 flash0: n25q256a@0 {
953 #address-cells = <1>; 953 #address-cells = <1>;
954 #size-cells = <1>; 954 #size-cells = <1>;
955 compatible = "micron,n25q256a", "jedec,spi-nor"; 955 compatible = "micron,n25q256a", "jedec,spi-nor";
956 spi-max-frequency = <29000000>; 956 spi-max-frequency = <29000000>;
957 spi-nor,ddr-quad-read-dummy = <6>; 957 spi-nor,ddr-quad-read-dummy = <6>;
958 reg = <0>; 958 reg = <0>;
959 }; 959 };
960 960
961 #ifdef REWORKED_ENABLE_ALL_QSPI 961 #ifdef REWORKED_ENABLE_ALL_QSPI
962 962
963 flash1: n25q256a@1 { 963 flash1: n25q256a@1 {
964 #address-cells = <1>; 964 #address-cells = <1>;
965 #size-cells = <1>; 965 #size-cells = <1>;
966 compatible = "micron,n25q256a", "jedec,spi-nor"; 966 compatible = "micron,n25q256a", "jedec,spi-nor";
967 spi-max-frequency = <29000000>; 967 spi-max-frequency = <29000000>;
968 spi-nor,ddr-quad-read-dummy = <6>; 968 spi-nor,ddr-quad-read-dummy = <6>;
969 reg = <1>; 969 reg = <1>;
970 }; 970 };
971 971
972 flash2: n25q256a@2 { 972 flash2: n25q256a@2 {
973 #address-cells = <1>; 973 #address-cells = <1>;
974 #size-cells = <1>; 974 #size-cells = <1>;
975 compatible = "micron,n25q256a", "jedec,spi-nor"; 975 compatible = "micron,n25q256a", "jedec,spi-nor";
976 spi-max-frequency = <29000000>; 976 spi-max-frequency = <29000000>;
977 spi-nor,ddr-quad-read-dummy = <6>; 977 spi-nor,ddr-quad-read-dummy = <6>;
978 reg = <2>; 978 reg = <2>;
979 }; 979 };
980 980
981 flash3: n25q256a@3 { 981 flash3: n25q256a@3 {
982 #address-cells = <1>; 982 #address-cells = <1>;
983 #size-cells = <1>; 983 #size-cells = <1>;
984 compatible = "micron,n25q256a", "jedec,spi-nor"; 984 compatible = "micron,n25q256a", "jedec,spi-nor";
985 spi-max-frequency = <29000000>; 985 spi-max-frequency = <29000000>;
986 spi-nor,ddr-quad-read-dummy = <6>; 986 spi-nor,ddr-quad-read-dummy = <6>;
987 reg = <3>; 987 reg = <3>;
988 }; 988 };
989 #endif 989 #endif
990 }; 990 };
991 991
992 &uart1 { 992 &uart1 {
993 pinctrl-names = "default"; 993 pinctrl-names = "default";
994 pinctrl-0 = <&pinctrl_uart1>; 994 pinctrl-0 = <&pinctrl_uart1>;
995 status = "okay"; 995 status = "okay";
996 }; 996 };
997 997
998 &uart2 { 998 &uart2 {
999 pinctrl-names = "default"; 999 pinctrl-names = "default";
1000 pinctrl-0 = <&pinctrl_uart2 1000 pinctrl-0 = <&pinctrl_uart2
1001 &pinctrl_bt>; 1001 &pinctrl_bt>;
1002 fsl,uart-has-rtscts; 1002 fsl,uart-has-rtscts;
1003 /* for DTE mode, add below change */ 1003 /* for DTE mode, add below change */
1004 /* fsl,dte-mode; */ 1004 /* fsl,dte-mode; */
1005 /* pinctrl-0 = <&pinctrl_uart2dte>; */ 1005 /* pinctrl-0 = <&pinctrl_uart2dte>; */
1006 status = "disabled"; 1006 status = "disabled";
1007 }; 1007 };
1008 1008
1009 &usbotg1 { 1009 &usbotg1 {
1010 vbus-supply = <&reg_usb_otg1_vbus>; 1010 vbus-supply = <&reg_usb_otg1_vbus>;
1011 pinctrl-names = "default"; 1011 pinctrl-names = "default";
1012 pinctrl-0 = <&pinctrl_usb_otg1_id>; 1012 pinctrl-0 = <&pinctrl_usb_otg1_id>;
1013 srp-disable; 1013 srp-disable;
1014 hnp-disable; 1014 hnp-disable;
1015 adp-disable; 1015 adp-disable;
1016 status = "okay"; 1016 status = "okay";
1017 }; 1017 };
1018 1018
1019 &usdhc1 { 1019 &usdhc1 {
1020 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 1020 pinctrl-names = "default", "state_100mhz", "state_200mhz";
1021 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>; 1021 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>;
1022 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>; 1022 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>;
1023 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>; 1023 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>;
1024 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 1024 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
1025 wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; 1025 wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
1026 keep-power-in-suspend; 1026 keep-power-in-suspend;
1027 enable-sdio-wakeup; 1027 enable-sdio-wakeup;
1028 vmmc-supply = <&reg_sd1_vmmc>; 1028 vmmc-supply = <&reg_sd1_vmmc>;
1029 status = "okay"; 1029 status = "okay";
1030 }; 1030 };
1031 1031
1032 &usdhc2 { 1032 &usdhc2 {
1033 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 1033 pinctrl-names = "default", "state_100mhz", "state_200mhz";
1034 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_rst>; 1034 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_rst>;
1035 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_rst>; 1035 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_rst>;
1036 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_rst>; 1036 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_rst>;
1037 non-removable; 1037 non-removable;
1038 no-1-8-v; /* VSELECT not connected by default */ 1038 no-1-8-v; /* VSELECT not connected by default */
1039 keep-power-in-suspend; 1039 keep-power-in-suspend;
1040 enable-sdio-wakeup; 1040 enable-sdio-wakeup;
1041 vmmc-supply = <&reg_sd2_vmmc>; 1041 vmmc-supply = <&reg_sd2_vmmc>;
1042 status = "okay"; 1042 status = "okay";
1043 }; 1043 };
1044 1044
1045 &wdog1 { 1045 &wdog1 {
1046 pinctrl-names = "default"; 1046 pinctrl-names = "default";
1047 pinctrl-0 = <&pinctrl_wdog>; 1047 pinctrl-0 = <&pinctrl_wdog>;
1048 fsl,ext-reset-output; 1048 fsl,ext-reset-output;
1049 }; 1049 };
1050 1050
arch/arm/dts/imx6ull-14x14-evk.dts
Diff comments   View file @ 4daafb3
1 /* 1 /*
2 * Copyright (C) 2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include "imx6ull.dtsi" 11 #include "imx6ull.dtsi"
12 12
13 / { 13 / {
14 model = "Freescale i.MX6 ULL 14x14 EVK Board"; 14 model = "Freescale i.MX6 ULL 14x14 EVK Board";
15 compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; 15 compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
16 16
17 aliases { 17 aliases {
18 spi5 = &soft_spi; 18 spi5 = &soft_spi;
19 }; 19 };
20 20
21 chosen { 21 chosen {
22 stdout-path = &uart1; 22 stdout-path = &uart1;
23 }; 23 };
24 24
25 memory { 25 memory {
26 reg = <0x80000000 0x20000000>; 26 reg = <0x80000000 0x20000000>;
27 }; 27 };
28 28
29 reserved-memory { 29 reserved-memory {
30 #address-cells = <1>; 30 #address-cells = <1>;
31 #size-cells = <1>; 31 #size-cells = <1>;
32 ranges; 32 ranges;
33 33
34 linux,cma { 34 linux,cma {
35 compatible = "shared-dma-pool"; 35 compatible = "shared-dma-pool";
36 reusable; 36 reusable;
37 size = <0x14000000>; 37 size = <0x14000000>;
38 linux,cma-default; 38 linux,cma-default;
39 }; 39 };
40 }; 40 };
41 41
42 backlight { 42 backlight {
43 compatible = "pwm-backlight"; 43 compatible = "pwm-backlight";
44 pwms = <&pwm1 0 5000000>; 44 pwms = <&pwm1 0 5000000>;
45 brightness-levels = <0 4 8 16 32 64 128 255>; 45 brightness-levels = <0 4 8 16 32 64 128 255>;
46 default-brightness-level = <6>; 46 default-brightness-level = <6>;
47 status = "okay"; 47 status = "okay";
48 }; 48 };
49 49
50 pxp_v4l2 { 50 pxp_v4l2 {
51 compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; 51 compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
52 status = "okay"; 52 status = "okay";
53 }; 53 };
54 54
55 regulators { 55 regulators {
56 compatible = "simple-bus"; 56 compatible = "simple-bus";
57 #address-cells = <1>; 57 #address-cells = <1>;
58 #size-cells = <0>; 58 #size-cells = <0>;
59 59
60 reg_can_3v3: regulator@0 { 60 reg_can_3v3: regulator@0 {
61 compatible = "regulator-fixed"; 61 compatible = "regulator-fixed";
62 reg = <0>; 62 reg = <0>;
63 regulator-name = "can-3v3"; 63 regulator-name = "can-3v3";
64 regulator-min-microvolt = <3300000>; 64 regulator-min-microvolt = <3300000>;
65 regulator-max-microvolt = <3300000>; 65 regulator-max-microvolt = <3300000>;
66 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; 66 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
67 }; 67 };
68 68
69 reg_sd1_vmmc: regulator@1 { 69 reg_sd1_vmmc: regulator@1 {
70 compatible = "regulator-fixed"; 70 compatible = "regulator-fixed";
71 regulator-name = "VSD_3V3"; 71 regulator-name = "VSD_3V3";
72 regulator-min-microvolt = <3300000>; 72 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <3300000>; 73 regulator-max-microvolt = <3300000>;
74 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 74 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
75 off-on-delay = <20000>; 75 u-boot,off-on-delay-us = <20000>;
76 enable-active-high; 76 enable-active-high;
77 }; 77 };
78 78
79 reg_gpio_dvfs: regulator-gpio { 79 reg_gpio_dvfs: regulator-gpio {
80 compatible = "regulator-gpio"; 80 compatible = "regulator-gpio";
81 pinctrl-names = "default"; 81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_dvfs>; 82 pinctrl-0 = <&pinctrl_dvfs>;
83 regulator-min-microvolt = <1300000>; 83 regulator-min-microvolt = <1300000>;
84 regulator-max-microvolt = <1400000>; 84 regulator-max-microvolt = <1400000>;
85 regulator-name = "gpio_dvfs"; 85 regulator-name = "gpio_dvfs";
86 regulator-type = "voltage"; 86 regulator-type = "voltage";
87 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 87 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
88 states = <1300000 0x1 1400000 0x0>; 88 states = <1300000 0x1 1400000 0x0>;
89 }; 89 };
90 }; 90 };
91 91
92 sound { 92 sound {
93 compatible = "fsl,imx6ul-evk-wm8960", 93 compatible = "fsl,imx6ul-evk-wm8960",
94 "fsl,imx-audio-wm8960"; 94 "fsl,imx-audio-wm8960";
95 model = "wm8960-audio"; 95 model = "wm8960-audio";
96 cpu-dai = <&sai2>; 96 cpu-dai = <&sai2>;
97 audio-codec = <&codec>; 97 audio-codec = <&codec>;
98 asrc-controller = <&asrc>; 98 asrc-controller = <&asrc>;
99 codec-master; 99 codec-master;
100 gpr = <&gpr 4 0x100000 0x100000>; 100 gpr = <&gpr 4 0x100000 0x100000>;
101 /* 101 /*
102 * hp-det = <hp-det-pin hp-det-polarity>; 102 * hp-det = <hp-det-pin hp-det-polarity>;
103 * hp-det-pin: JD1 JD2 or JD3 103 * hp-det-pin: JD1 JD2 or JD3
104 * hp-det-polarity = 0: hp detect high for headphone 104 * hp-det-polarity = 0: hp detect high for headphone
105 * hp-det-polarity = 1: hp detect high for speaker 105 * hp-det-polarity = 1: hp detect high for speaker
106 */ 106 */
107 hp-det = <3 0>; 107 hp-det = <3 0>;
108 hp-det-gpios = <&gpio5 4 0>; 108 hp-det-gpios = <&gpio5 4 0>;
109 mic-det-gpios = <&gpio5 4 0>; 109 mic-det-gpios = <&gpio5 4 0>;
110 audio-routing = 110 audio-routing =
111 "Headphone Jack", "HP_L", 111 "Headphone Jack", "HP_L",
112 "Headphone Jack", "HP_R", 112 "Headphone Jack", "HP_R",
113 "Ext Spk", "SPK_LP", 113 "Ext Spk", "SPK_LP",
114 "Ext Spk", "SPK_LN", 114 "Ext Spk", "SPK_LN",
115 "Ext Spk", "SPK_RP", 115 "Ext Spk", "SPK_RP",
116 "Ext Spk", "SPK_RN", 116 "Ext Spk", "SPK_RN",
117 "LINPUT2", "Mic Jack", 117 "LINPUT2", "Mic Jack",
118 "LINPUT3", "Mic Jack", 118 "LINPUT3", "Mic Jack",
119 "RINPUT1", "Main MIC", 119 "RINPUT1", "Main MIC",
120 "RINPUT2", "Main MIC", 120 "RINPUT2", "Main MIC",
121 "Mic Jack", "MICB", 121 "Mic Jack", "MICB",
122 "Main MIC", "MICB", 122 "Main MIC", "MICB",
123 "CPU-Playback", "ASRC-Playback", 123 "CPU-Playback", "ASRC-Playback",
124 "Playback", "CPU-Playback", 124 "Playback", "CPU-Playback",
125 "ASRC-Capture", "CPU-Capture", 125 "ASRC-Capture", "CPU-Capture",
126 "CPU-Capture", "Capture"; 126 "CPU-Capture", "Capture";
127 }; 127 };
128 128
129 soft_spi: soft-spi { 129 soft_spi: soft-spi {
130 compatible = "spi-gpio"; 130 compatible = "spi-gpio";
131 pinctrl-names = "default"; 131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_spi4>; 132 pinctrl-0 = <&pinctrl_spi4>;
133 pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; 133 pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
134 status = "okay"; 134 status = "okay";
135 gpio-sck = <&gpio5 11 0>; 135 gpio-sck = <&gpio5 11 0>;
136 gpio-mosi = <&gpio5 10 0>; 136 gpio-mosi = <&gpio5 10 0>;
137 cs-gpios = <&gpio5 7 0>; 137 cs-gpios = <&gpio5 7 0>;
138 num-chipselects = <1>; 138 num-chipselects = <1>;
139 #address-cells = <1>; 139 #address-cells = <1>;
140 #size-cells = <0>; 140 #size-cells = <0>;
141 141
142 gpio_spi: gpio_spi@0 { 142 gpio_spi: gpio_spi@0 {
143 compatible = "fairchild,74hc595"; 143 compatible = "fairchild,74hc595";
144 gpio-controller; 144 gpio-controller;
145 #gpio-cells = <2>; 145 #gpio-cells = <2>;
146 reg = <0>; 146 reg = <0>;
147 registers-number = <1>; 147 registers-number = <1>;
148 registers-default = /bits/ 8 <0x57>; 148 registers-default = /bits/ 8 <0x57>;
149 spi-max-frequency = <100000>; 149 spi-max-frequency = <100000>;
150 }; 150 };
151 }; 151 };
152 }; 152 };
153 153
154 &cpu0 { 154 &cpu0 {
155 dc-supply = <&reg_gpio_dvfs>; 155 dc-supply = <&reg_gpio_dvfs>;
156 }; 156 };
157 157
158 &clks { 158 &clks {
159 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 159 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
160 assigned-clock-rates = <786432000>; 160 assigned-clock-rates = <786432000>;
161 }; 161 };
162 162
163 &csi { 163 &csi {
164 status = "okay"; 164 status = "okay";
165 165
166 port { 166 port {
167 csi1_ep: endpoint { 167 csi1_ep: endpoint {
168 remote-endpoint = <&ov5640_ep>; 168 remote-endpoint = <&ov5640_ep>;
169 }; 169 };
170 }; 170 };
171 }; 171 };
172 172
173 &fec1 { 173 &fec1 {
174 pinctrl-names = "default"; 174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_enet1>; 175 pinctrl-0 = <&pinctrl_enet1>;
176 phy-mode = "rmii"; 176 phy-mode = "rmii";
177 phy-handle = <&ethphy0>; 177 phy-handle = <&ethphy0>;
178 status = "okay"; 178 status = "okay";
179 }; 179 };
180 180
181 &fec2 { 181 &fec2 {
182 pinctrl-names = "default"; 182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_enet2>; 183 pinctrl-0 = <&pinctrl_enet2>;
184 phy-mode = "rmii"; 184 phy-mode = "rmii";
185 phy-handle = <&ethphy1>; 185 phy-handle = <&ethphy1>;
186 status = "okay"; 186 status = "okay";
187 187
188 mdio { 188 mdio {
189 #address-cells = <1>; 189 #address-cells = <1>;
190 #size-cells = <0>; 190 #size-cells = <0>;
191 191
192 ethphy0: ethernet-phy@2 { 192 ethphy0: ethernet-phy@2 {
193 compatible = "ethernet-phy-ieee802.3-c22"; 193 compatible = "ethernet-phy-ieee802.3-c22";
194 reg = <2>; 194 reg = <2>;
195 micrel,led-mode = <1>; 195 micrel,led-mode = <1>;
196 clocks = <&clks IMX6UL_CLK_ENET_REF>; 196 clocks = <&clks IMX6UL_CLK_ENET_REF>;
197 clock-names = "rmii-ref"; 197 clock-names = "rmii-ref";
198 }; 198 };
199 199
200 ethphy1: ethernet-phy@1 { 200 ethphy1: ethernet-phy@1 {
201 compatible = "ethernet-phy-ieee802.3-c22"; 201 compatible = "ethernet-phy-ieee802.3-c22";
202 reg = <1>; 202 reg = <1>;
203 micrel,led-mode = <1>; 203 micrel,led-mode = <1>;
204 clocks = <&clks IMX6UL_CLK_ENET2_REF>; 204 clocks = <&clks IMX6UL_CLK_ENET2_REF>;
205 clock-names = "rmii-ref"; 205 clock-names = "rmii-ref";
206 }; 206 };
207 }; 207 };
208 }; 208 };
209 209
210 &flexcan1 { 210 &flexcan1 {
211 pinctrl-names = "default"; 211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_flexcan1>; 212 pinctrl-0 = <&pinctrl_flexcan1>;
213 xceiver-supply = <&reg_can_3v3>; 213 xceiver-supply = <&reg_can_3v3>;
214 status = "okay"; 214 status = "okay";
215 }; 215 };
216 216
217 &flexcan2 { 217 &flexcan2 {
218 pinctrl-names = "default"; 218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_flexcan2>; 219 pinctrl-0 = <&pinctrl_flexcan2>;
220 xceiver-supply = <&reg_can_3v3>; 220 xceiver-supply = <&reg_can_3v3>;
221 status = "okay"; 221 status = "okay";
222 }; 222 };
223 223
224 &gpc { 224 &gpc {
225 fsl,cpu_pupscr_sw2iso = <0xf>; 225 fsl,cpu_pupscr_sw2iso = <0xf>;
226 fsl,cpu_pupscr_sw = <0x0>; 226 fsl,cpu_pupscr_sw = <0x0>;
227 fsl,cpu_pdnscr_iso2sw = <0x1>; 227 fsl,cpu_pdnscr_iso2sw = <0x1>;
228 fsl,cpu_pdnscr_iso = <0x1>; 228 fsl,cpu_pdnscr_iso = <0x1>;
229 fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ 229 fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
230 }; 230 };
231 231
232 &i2c1 { 232 &i2c1 {
233 clock-frequency = <100000>; 233 clock-frequency = <100000>;
234 pinctrl-names = "default", "gpio"; 234 pinctrl-names = "default", "gpio";
235 pinctrl-0 = <&pinctrl_i2c1>; 235 pinctrl-0 = <&pinctrl_i2c1>;
236 pinctrl-1 = <&pinctrl_i2c1_gpio>; 236 pinctrl-1 = <&pinctrl_i2c1_gpio>;
237 scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; 237 scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
238 sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; 238 sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
239 status = "okay"; 239 status = "okay";
240 240
241 mag3110@0e { 241 mag3110@0e {
242 compatible = "fsl,mag3110"; 242 compatible = "fsl,mag3110";
243 reg = <0x0e>; 243 reg = <0x0e>;
244 position = <2>; 244 position = <2>;
245 }; 245 };
246 246
247 fxls8471@1e { 247 fxls8471@1e {
248 compatible = "fsl,fxls8471"; 248 compatible = "fsl,fxls8471";
249 reg = <0x1e>; 249 reg = <0x1e>;
250 position = <0>; 250 position = <0>;
251 interrupt-parent = <&gpio5>; 251 interrupt-parent = <&gpio5>;
252 interrupts = <0 8>; 252 interrupts = <0 8>;
253 }; 253 };
254 }; 254 };
255 255
256 &i2c2 { 256 &i2c2 {
257 clock_frequency = <100000>; 257 clock_frequency = <100000>;
258 pinctrl-names = "default", "gpio"; 258 pinctrl-names = "default", "gpio";
259 pinctrl-0 = <&pinctrl_i2c2>; 259 pinctrl-0 = <&pinctrl_i2c2>;
260 pinctrl-1 = <&pinctrl_i2c2_gpio>; 260 pinctrl-1 = <&pinctrl_i2c2_gpio>;
261 scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; 261 scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
262 sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; 262 sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
263 status = "okay"; 263 status = "okay";
264 264
265 codec: wm8960@1a { 265 codec: wm8960@1a {
266 compatible = "wlf,wm8960"; 266 compatible = "wlf,wm8960";
267 reg = <0x1a>; 267 reg = <0x1a>;
268 clocks = <&clks IMX6UL_CLK_SAI2>; 268 clocks = <&clks IMX6UL_CLK_SAI2>;
269 clock-names = "mclk"; 269 clock-names = "mclk";
270 wlf,shared-lrclk; 270 wlf,shared-lrclk;
271 }; 271 };
272 272
273 ov5640: ov5640@3c { 273 ov5640: ov5640@3c {
274 compatible = "ovti,ov5640"; 274 compatible = "ovti,ov5640";
275 reg = <0x3c>; 275 reg = <0x3c>;
276 pinctrl-names = "default"; 276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_csi1>; 277 pinctrl-0 = <&pinctrl_csi1>;
278 clocks = <&clks IMX6UL_CLK_CSI>; 278 clocks = <&clks IMX6UL_CLK_CSI>;
279 clock-names = "csi_mclk"; 279 clock-names = "csi_mclk";
280 pwn-gpios = <&gpio_spi 6 1>; 280 pwn-gpios = <&gpio_spi 6 1>;
281 rst-gpios = <&gpio_spi 5 0>; 281 rst-gpios = <&gpio_spi 5 0>;
282 csi_id = <0>; 282 csi_id = <0>;
283 mclk = <24000000>; 283 mclk = <24000000>;
284 mclk_source = <0>; 284 mclk_source = <0>;
285 status = "okay"; 285 status = "okay";
286 port { 286 port {
287 ov5640_ep: endpoint { 287 ov5640_ep: endpoint {
288 remote-endpoint = <&csi1_ep>; 288 remote-endpoint = <&csi1_ep>;
289 }; 289 };
290 }; 290 };
291 }; 291 };
292 }; 292 };
293 293
294 &iomuxc { 294 &iomuxc {
295 pinctrl-names = "default"; 295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_hog_1>; 296 pinctrl-0 = <&pinctrl_hog_1>;
297 imx6ul-evk { 297 imx6ul-evk {
298 pinctrl_hog_1: hoggrp-1 { 298 pinctrl_hog_1: hoggrp-1 {
299 fsl,pins = < 299 fsl,pins = <
300 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ 300 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
301 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ 301 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
302 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ 302 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
303 >; 303 >;
304 }; 304 };
305 305
306 pinctrl_csi1: csi1grp { 306 pinctrl_csi1: csi1grp {
307 fsl,pins = < 307 fsl,pins = <
308 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 308 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
309 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 309 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
310 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 310 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
311 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 311 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
312 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 312 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
313 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 313 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
314 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 314 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
315 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 315 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
316 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 316 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
317 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 317 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
318 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 318 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
319 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 319 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
320 >; 320 >;
321 }; 321 };
322 322
323 pinctrl_enet1: enet1grp { 323 pinctrl_enet1: enet1grp {
324 fsl,pins = < 324 fsl,pins = <
325 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 325 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
326 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 326 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
327 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 327 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
328 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 328 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
329 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 329 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
330 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 330 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
331 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 331 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
332 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 332 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
333 >; 333 >;
334 }; 334 };
335 335
336 pinctrl_enet2: enet2grp { 336 pinctrl_enet2: enet2grp {
337 fsl,pins = < 337 fsl,pins = <
338 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 338 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
339 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 339 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
340 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 340 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
341 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 341 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
342 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 342 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
343 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 343 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
344 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 344 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
345 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 345 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
346 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 346 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
347 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 347 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
348 >; 348 >;
349 }; 349 };
350 350
351 pinctrl_flexcan1: flexcan1grp{ 351 pinctrl_flexcan1: flexcan1grp{
352 fsl,pins = < 352 fsl,pins = <
353 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 353 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
354 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 354 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
355 >; 355 >;
356 }; 356 };
357 357
358 pinctrl_flexcan2: flexcan2grp{ 358 pinctrl_flexcan2: flexcan2grp{
359 fsl,pins = < 359 fsl,pins = <
360 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 360 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
361 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 361 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
362 >; 362 >;
363 }; 363 };
364 364
365 pinctrl_i2c1: i2c1grp { 365 pinctrl_i2c1: i2c1grp {
366 fsl,pins = < 366 fsl,pins = <
367 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 367 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
368 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 368 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
369 >; 369 >;
370 }; 370 };
371 371
372 pinctrl_i2c1_gpio: i2c1grp_gpio { 372 pinctrl_i2c1_gpio: i2c1grp_gpio {
373 fsl,pins = < 373 fsl,pins = <
374 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 374 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
375 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 375 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
376 >; 376 >;
377 }; 377 };
378 378
379 pinctrl_i2c2: i2c2grp { 379 pinctrl_i2c2: i2c2grp {
380 fsl,pins = < 380 fsl,pins = <
381 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 381 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
382 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 382 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
383 >; 383 >;
384 }; 384 };
385 385
386 pinctrl_i2c2_gpio: i2c2grp_gpio { 386 pinctrl_i2c2_gpio: i2c2grp_gpio {
387 fsl,pins = < 387 fsl,pins = <
388 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 388 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
389 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 389 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
390 >; 390 >;
391 }; 391 };
392 392
393 pinctrl_lcdif_dat: lcdifdatgrp { 393 pinctrl_lcdif_dat: lcdifdatgrp {
394 fsl,pins = < 394 fsl,pins = <
395 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 395 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
396 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 396 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
397 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 397 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
398 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 398 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
399 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 399 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
400 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 400 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
401 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 401 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
402 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 402 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
403 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 403 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
404 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 404 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
405 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 405 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
406 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 406 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
407 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 407 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
408 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 408 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
409 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 409 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
410 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 410 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
411 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 411 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
412 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 412 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
413 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 413 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
414 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 414 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
415 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 415 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
416 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 416 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
417 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 417 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
418 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 418 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
419 >; 419 >;
420 }; 420 };
421 421
422 pinctrl_lcdif_ctrl: lcdifctrlgrp { 422 pinctrl_lcdif_ctrl: lcdifctrlgrp {
423 fsl,pins = < 423 fsl,pins = <
424 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 424 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
425 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 425 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
426 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 426 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
427 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 427 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
428 >; 428 >;
429 }; 429 };
430 430
431 pinctrl_pwm1: pwm1grp { 431 pinctrl_pwm1: pwm1grp {
432 fsl,pins = < 432 fsl,pins = <
433 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 433 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
434 >; 434 >;
435 }; 435 };
436 436
437 pinctrl_qspi: qspigrp { 437 pinctrl_qspi: qspigrp {
438 fsl,pins = < 438 fsl,pins = <
439 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 439 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
440 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 440 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
441 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 441 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
442 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 442 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
443 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 443 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
444 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 444 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
445 >; 445 >;
446 }; 446 };
447 447
448 pinctrl_sai2: sai2grp { 448 pinctrl_sai2: sai2grp {
449 fsl,pins = < 449 fsl,pins = <
450 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 450 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
451 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 451 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
452 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 452 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
453 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 453 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
454 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 454 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
455 >; 455 >;
456 }; 456 };
457 457
458 pinctrl_tsc: tscgrp { 458 pinctrl_tsc: tscgrp {
459 fsl,pins = < 459 fsl,pins = <
460 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 460 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
461 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 461 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
462 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 462 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
463 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 463 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
464 >; 464 >;
465 }; 465 };
466 466
467 pinctrl_uart1: uart1grp { 467 pinctrl_uart1: uart1grp {
468 fsl,pins = < 468 fsl,pins = <
469 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 469 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
470 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 470 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
471 >; 471 >;
472 }; 472 };
473 473
474 pinctrl_uart2: uart2grp { 474 pinctrl_uart2: uart2grp {
475 fsl,pins = < 475 fsl,pins = <
476 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 476 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
477 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 477 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
478 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 478 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
479 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 479 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
480 >; 480 >;
481 }; 481 };
482 482
483 pinctrl_uart2dte: uart2dtegrp { 483 pinctrl_uart2dte: uart2dtegrp {
484 fsl,pins = < 484 fsl,pins = <
485 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 485 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
486 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 486 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
487 MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 487 MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1
488 MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 488 MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1
489 >; 489 >;
490 }; 490 };
491 491
492 pinctrl_usb_otg1_id: usbotg1idgrp { 492 pinctrl_usb_otg1_id: usbotg1idgrp {
493 fsl,pins = < 493 fsl,pins = <
494 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 494 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
495 >; 495 >;
496 }; 496 };
497 497
498 pinctrl_usdhc1: usdhc1grp { 498 pinctrl_usdhc1: usdhc1grp {
499 fsl,pins = < 499 fsl,pins = <
500 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 500 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
501 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 501 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
502 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 502 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
503 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 503 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
504 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 504 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
505 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 505 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
506 >; 506 >;
507 }; 507 };
508 508
509 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 509 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
510 fsl,pins = < 510 fsl,pins = <
511 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 511 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
512 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 512 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
513 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 513 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
514 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 514 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
515 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 515 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
516 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 516 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
517 >; 517 >;
518 }; 518 };
519 519
520 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 520 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
521 fsl,pins = < 521 fsl,pins = <
522 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 522 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
523 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 523 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
524 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 524 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
525 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 525 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
526 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 526 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
527 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 527 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
528 >; 528 >;
529 }; 529 };
530 530
531 pinctrl_usdhc2: usdhc2grp { 531 pinctrl_usdhc2: usdhc2grp {
532 fsl,pins = < 532 fsl,pins = <
533 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 533 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
534 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 534 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
535 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 535 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
536 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 536 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
537 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 537 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
538 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 538 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
539 >; 539 >;
540 }; 540 };
541 541
542 pinctrl_usdhc2_8bit: usdhc2grp_8bit { 542 pinctrl_usdhc2_8bit: usdhc2grp_8bit {
543 fsl,pins = < 543 fsl,pins = <
544 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 544 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
545 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 545 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
546 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 546 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
547 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 547 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
548 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 548 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
549 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 549 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
550 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 550 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
551 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 551 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
552 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 552 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
553 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 553 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
554 >; 554 >;
555 }; 555 };
556 556
557 pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { 557 pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
558 fsl,pins = < 558 fsl,pins = <
559 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 559 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
560 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 560 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
561 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 561 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
562 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 562 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
563 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 563 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
564 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 564 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
565 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 565 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
566 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 566 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
567 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 567 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
568 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 568 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
569 >; 569 >;
570 }; 570 };
571 571
572 pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { 572 pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
573 fsl,pins = < 573 fsl,pins = <
574 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 574 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
575 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 575 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
576 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 576 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
577 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 577 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
578 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 578 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
579 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 579 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
580 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 580 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
581 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 581 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
582 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 582 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
583 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 583 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
584 >; 584 >;
585 }; 585 };
586 586
587 pinctrl_wdog: wdoggrp { 587 pinctrl_wdog: wdoggrp {
588 fsl,pins = < 588 fsl,pins = <
589 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 589 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
590 >; 590 >;
591 }; 591 };
592 }; 592 };
593 }; 593 };
594 594
595 &iomuxc_snvs { 595 &iomuxc_snvs {
596 pinctrl-names = "default_snvs"; 596 pinctrl-names = "default_snvs";
597 pinctrl-0 = <&pinctrl_hog_2>; 597 pinctrl-0 = <&pinctrl_hog_2>;
598 imx6ul-evk { 598 imx6ul-evk {
599 pinctrl_hog_2: hoggrp-2 { 599 pinctrl_hog_2: hoggrp-2 {
600 fsl,pins = < 600 fsl,pins = <
601 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 601 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000
602 >; 602 >;
603 }; 603 };
604 604
605 pinctrl_dvfs: dvfsgrp { 605 pinctrl_dvfs: dvfsgrp {
606 fsl,pins = < 606 fsl,pins = <
607 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 607 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79
608 >; 608 >;
609 }; 609 };
610 610
611 pinctrl_lcdif_reset: lcdifresetgrp { 611 pinctrl_lcdif_reset: lcdifresetgrp {
612 fsl,pins = < 612 fsl,pins = <
613 /* used for lcd reset */ 613 /* used for lcd reset */
614 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 614 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
615 >; 615 >;
616 }; 616 };
617 617
618 pinctrl_spi4: spi4grp { 618 pinctrl_spi4: spi4grp {
619 fsl,pins = < 619 fsl,pins = <
620 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 620 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
621 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 621 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
622 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 622 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
623 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 623 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
624 >; 624 >;
625 }; 625 };
626 626
627 pinctrl_sai2_hp_det_b: sai2_hp_det_grp { 627 pinctrl_sai2_hp_det_b: sai2_hp_det_grp {
628 fsl,pins = < 628 fsl,pins = <
629 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 629 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
630 >; 630 >;
631 }; 631 };
632 }; 632 };
633 }; 633 };
634 634
635 635
636 &lcdif { 636 &lcdif {
637 pinctrl-names = "default"; 637 pinctrl-names = "default";
638 pinctrl-0 = <&pinctrl_lcdif_dat 638 pinctrl-0 = <&pinctrl_lcdif_dat
639 &pinctrl_lcdif_ctrl 639 &pinctrl_lcdif_ctrl
640 &pinctrl_lcdif_reset>; 640 &pinctrl_lcdif_reset>;
641 display = <&display0>; 641 display = <&display0>;
642 status = "okay"; 642 status = "okay";
643 643
644 display0: display@0 { 644 display0: display@0 {
645 bits-per-pixel = <16>; 645 bits-per-pixel = <16>;
646 bus-width = <24>; 646 bus-width = <24>;
647 647
648 display-timings { 648 display-timings {
649 native-mode = <&timing0>; 649 native-mode = <&timing0>;
650 timing0: timing0 { 650 timing0: timing0 {
651 clock-frequency = <9200000>; 651 clock-frequency = <9200000>;
652 hactive = <480>; 652 hactive = <480>;
653 vactive = <272>; 653 vactive = <272>;
654 hfront-porch = <8>; 654 hfront-porch = <8>;
655 hback-porch = <4>; 655 hback-porch = <4>;
656 hsync-len = <41>; 656 hsync-len = <41>;
657 vback-porch = <2>; 657 vback-porch = <2>;
658 vfront-porch = <4>; 658 vfront-porch = <4>;
659 vsync-len = <10>; 659 vsync-len = <10>;
660 660
661 hsync-active = <0>; 661 hsync-active = <0>;
662 vsync-active = <0>; 662 vsync-active = <0>;
663 de-active = <1>; 663 de-active = <1>;
664 pixelclk-active = <0>; 664 pixelclk-active = <0>;
665 }; 665 };
666 }; 666 };
667 }; 667 };
668 }; 668 };
669 669
670 &pwm1 { 670 &pwm1 {
671 pinctrl-names = "default"; 671 pinctrl-names = "default";
672 pinctrl-0 = <&pinctrl_pwm1>; 672 pinctrl-0 = <&pinctrl_pwm1>;
673 status = "okay"; 673 status = "okay";
674 }; 674 };
675 675
676 &pxp { 676 &pxp {
677 status = "okay"; 677 status = "okay";
678 }; 678 };
679 679
680 &qspi { 680 &qspi {
681 pinctrl-names = "default"; 681 pinctrl-names = "default";
682 pinctrl-0 = <&pinctrl_qspi>; 682 pinctrl-0 = <&pinctrl_qspi>;
683 status = "okay"; 683 status = "okay";
684 ddrsmp=<0>; 684 ddrsmp=<0>;
685 685
686 flash0: n25q256a@0 { 686 flash0: n25q256a@0 {
687 #address-cells = <1>; 687 #address-cells = <1>;
688 #size-cells = <1>; 688 #size-cells = <1>;
689 compatible = "micron,n25q256a", "jedec,spi-nor"; 689 compatible = "micron,n25q256a", "jedec,spi-nor";
690 spi-max-frequency = <29000000>; 690 spi-max-frequency = <29000000>;
691 spi-nor,ddr-quad-read-dummy = <6>; 691 spi-nor,ddr-quad-read-dummy = <6>;
692 reg = <0>; 692 reg = <0>;
693 }; 693 };
694 }; 694 };
695 695
696 &sai2 { 696 &sai2 {
697 pinctrl-names = "default"; 697 pinctrl-names = "default";
698 pinctrl-0 = <&pinctrl_sai2 698 pinctrl-0 = <&pinctrl_sai2
699 &pinctrl_sai2_hp_det_b>; 699 &pinctrl_sai2_hp_det_b>;
700 700
701 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, 701 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
702 <&clks IMX6UL_CLK_SAI2>; 702 <&clks IMX6UL_CLK_SAI2>;
703 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 703 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
704 assigned-clock-rates = <0>, <12288000>; 704 assigned-clock-rates = <0>, <12288000>;
705 705
706 status = "okay"; 706 status = "okay";
707 }; 707 };
708 708
709 &tsc { 709 &tsc {
710 pinctrl-names = "default"; 710 pinctrl-names = "default";
711 pinctrl-0 = <&pinctrl_tsc>; 711 pinctrl-0 = <&pinctrl_tsc>;
712 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; 712 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
713 measure-delay-time = <0xffff>; 713 measure-delay-time = <0xffff>;
714 pre-charge-time = <0xfff>; 714 pre-charge-time = <0xfff>;
715 status = "okay"; 715 status = "okay";
716 }; 716 };
717 717
718 &uart1 { 718 &uart1 {
719 pinctrl-names = "default"; 719 pinctrl-names = "default";
720 pinctrl-0 = <&pinctrl_uart1>; 720 pinctrl-0 = <&pinctrl_uart1>;
721 status = "okay"; 721 status = "okay";
722 }; 722 };
723 723
724 &uart2 { 724 &uart2 {
725 pinctrl-names = "default"; 725 pinctrl-names = "default";
726 pinctrl-0 = <&pinctrl_uart2>; 726 pinctrl-0 = <&pinctrl_uart2>;
727 fsl,uart-has-rtscts; 727 fsl,uart-has-rtscts;
728 /* for DTE mode, add below change */ 728 /* for DTE mode, add below change */
729 /* fsl,dte-mode; */ 729 /* fsl,dte-mode; */
730 /* pinctrl-0 = <&pinctrl_uart2dte>; */ 730 /* pinctrl-0 = <&pinctrl_uart2dte>; */
731 status = "okay"; 731 status = "okay";
732 }; 732 };
733 733
734 &usbotg1 { 734 &usbotg1 {
735 pinctrl-names = "default"; 735 pinctrl-names = "default";
736 pinctrl-0 = <&pinctrl_usb_otg1_id>; 736 pinctrl-0 = <&pinctrl_usb_otg1_id>;
737 dr_mode = "otg"; 737 dr_mode = "otg";
738 srp-disable; 738 srp-disable;
739 hnp-disable; 739 hnp-disable;
740 adp-disable; 740 adp-disable;
741 status = "okay"; 741 status = "okay";
742 }; 742 };
743 743
744 &usbotg2 { 744 &usbotg2 {
745 dr_mode = "host"; 745 dr_mode = "host";
746 disable-over-current; 746 disable-over-current;
747 status = "okay"; 747 status = "okay";
748 }; 748 };
749 749
750 &usbphy1 { 750 &usbphy1 {
751 fsl,tx-d-cal = <106>; 751 fsl,tx-d-cal = <106>;
752 }; 752 };
753 753
754 &usbphy2 { 754 &usbphy2 {
755 fsl,tx-d-cal = <106>; 755 fsl,tx-d-cal = <106>;
756 }; 756 };
757 757
758 &usdhc1 { 758 &usdhc1 {
759 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 759 pinctrl-names = "default", "state_100mhz", "state_200mhz";
760 pinctrl-0 = <&pinctrl_usdhc1>; 760 pinctrl-0 = <&pinctrl_usdhc1>;
761 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 761 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
762 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 762 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
763 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 763 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
764 keep-power-in-suspend; 764 keep-power-in-suspend;
765 enable-sdio-wakeup; 765 enable-sdio-wakeup;
766 vmmc-supply = <&reg_sd1_vmmc>; 766 vmmc-supply = <&reg_sd1_vmmc>;
767 status = "okay"; 767 status = "okay";
768 }; 768 };
769 769
770 &usdhc2 { 770 &usdhc2 {
771 pinctrl-names = "default"; 771 pinctrl-names = "default";
772 pinctrl-0 = <&pinctrl_usdhc2>; 772 pinctrl-0 = <&pinctrl_usdhc2>;
773 non-removable; 773 non-removable;
774 status = "okay"; 774 status = "okay";
775 }; 775 };
776 776
777 &wdog1 { 777 &wdog1 {
778 pinctrl-names = "default"; 778 pinctrl-names = "default";
779 pinctrl-0 = <&pinctrl_wdog>; 779 pinctrl-0 = <&pinctrl_wdog>;
780 fsl,ext-reset-output; 780 fsl,ext-reset-output;
781 }; 781 };
782 782
arch/arm/dts/imx6ull-9x9-evk.dts
Diff comments   View file @ 4daafb3
1 /* 1 /*
2 * Copyright (C) 2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as 6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
8 */ 8 */
9 9
10 /dts-v1/; 10 /dts-v1/;
11 11
12 #include "imx6ull.dtsi" 12 #include "imx6ull.dtsi"
13 13
14 / { 14 / {
15 model = "Freescale i.MX6 ULL 9x9 EVK Board"; 15 model = "Freescale i.MX6 ULL 9x9 EVK Board";
16 compatible = "fsl,imx6ull-9x9-evk", "fsl,imx6ull"; 16 compatible = "fsl,imx6ull-9x9-evk", "fsl,imx6ull";
17 17
18 aliases { 18 aliases {
19 spi5 = &soft_spi; 19 spi5 = &soft_spi;
20 }; 20 };
21 21
22 backlight { 22 backlight {
23 compatible = "pwm-backlight"; 23 compatible = "pwm-backlight";
24 pwms = <&pwm1 0 5000000>; 24 pwms = <&pwm1 0 5000000>;
25 brightness-levels = <0 4 8 16 32 64 128 255>; 25 brightness-levels = <0 4 8 16 32 64 128 255>;
26 default-brightness-level = <6>; 26 default-brightness-level = <6>;
27 status = "okay"; 27 status = "okay";
28 }; 28 };
29 29
30 chosen { 30 chosen {
31 stdout-path = &uart1; 31 stdout-path = &uart1;
32 }; 32 };
33 33
34 memory { 34 memory {
35 reg = <0x80000000 0x10000000>; 35 reg = <0x80000000 0x10000000>;
36 }; 36 };
37 37
38 reserved-memory { 38 reserved-memory {
39 #address-cells = <1>; 39 #address-cells = <1>;
40 #size-cells = <1>; 40 #size-cells = <1>;
41 ranges; 41 ranges;
42 42
43 linux,cma { 43 linux,cma {
44 compatible = "shared-dma-pool"; 44 compatible = "shared-dma-pool";
45 reusable; 45 reusable;
46 size = <0x6000000>; 46 size = <0x6000000>;
47 linux,cma-default; 47 linux,cma-default;
48 }; 48 };
49 }; 49 };
50 50
51 pxp_v4l2 { 51 pxp_v4l2 {
52 compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; 52 compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
53 status = "okay"; 53 status = "okay";
54 }; 54 };
55 55
56 regulators { 56 regulators {
57 compatible = "simple-bus"; 57 compatible = "simple-bus";
58 #address-cells = <1>; 58 #address-cells = <1>;
59 #size-cells = <0>; 59 #size-cells = <0>;
60 60
61 reg_can_3v3: regulator@0 { 61 reg_can_3v3: regulator@0 {
62 compatible = "regulator-fixed"; 62 compatible = "regulator-fixed";
63 reg = <0>; 63 reg = <0>;
64 regulator-name = "can-3v3"; 64 regulator-name = "can-3v3";
65 regulator-min-microvolt = <3300000>; 65 regulator-min-microvolt = <3300000>;
66 regulator-max-microvolt = <3300000>; 66 regulator-max-microvolt = <3300000>;
67 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; 67 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
68 }; 68 };
69 69
70 reg_gpio_dvfs: regulator-gpio { 70 reg_gpio_dvfs: regulator-gpio {
71 compatible = "regulator-gpio"; 71 compatible = "regulator-gpio";
72 pinctrl-names = "default"; 72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_dvfs>; 73 pinctrl-0 = <&pinctrl_dvfs>;
74 regulator-min-microvolt = <1300000>; 74 regulator-min-microvolt = <1300000>;
75 regulator-max-microvolt = <1400000>; 75 regulator-max-microvolt = <1400000>;
76 regulator-name = "gpio_dvfs"; 76 regulator-name = "gpio_dvfs";
77 regulator-type = "voltage"; 77 regulator-type = "voltage";
78 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 78 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
79 states = <1300000 0x1 1400000 0x0>; 79 states = <1300000 0x1 1400000 0x0>;
80 }; 80 };
81 81
82 reg_sd1_vmmc: regulator@1 { 82 reg_sd1_vmmc: regulator@1 {
83 compatible = "regulator-fixed"; 83 compatible = "regulator-fixed";
84 regulator-name = "VSD_3V3"; 84 regulator-name = "VSD_3V3";
85 regulator-min-microvolt = <3300000>; 85 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <3300000>; 86 regulator-max-microvolt = <3300000>;
87 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 87 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
88 off-on-delay = <20000>; 88 u-boot,off-on-delay-us = <20000>;
89 enable-active-high; 89 enable-active-high;
90 }; 90 };
91 }; 91 };
92 92
93 sound { 93 sound {
94 compatible = "fsl,imx6ul-evk-wm8960", 94 compatible = "fsl,imx6ul-evk-wm8960",
95 "fsl,imx-audio-wm8960"; 95 "fsl,imx-audio-wm8960";
96 model = "wm8960-audio"; 96 model = "wm8960-audio";
97 cpu-dai = <&sai2>; 97 cpu-dai = <&sai2>;
98 audio-codec = <&codec>; 98 audio-codec = <&codec>;
99 asrc-controller = <&asrc>; 99 asrc-controller = <&asrc>;
100 codec-master; 100 codec-master;
101 gpr = <&gpr 4 0x100000 0x100000>; 101 gpr = <&gpr 4 0x100000 0x100000>;
102 /* 102 /*
103 * hp-det = <hp-det-pin hp-det-polarity>; 103 * hp-det = <hp-det-pin hp-det-polarity>;
104 * hp-det-pin: JD1 JD2 or JD3 104 * hp-det-pin: JD1 JD2 or JD3
105 * hp-det-polarity = 0: hp detect high for headphone 105 * hp-det-polarity = 0: hp detect high for headphone
106 * hp-det-polarity = 1: hp detect high for speaker 106 * hp-det-polarity = 1: hp detect high for speaker
107 */ 107 */
108 hp-det = <3 0>; 108 hp-det = <3 0>;
109 hp-det-gpios = <&gpio5 4 0>; 109 hp-det-gpios = <&gpio5 4 0>;
110 mic-det-gpios = <&gpio5 4 0>; 110 mic-det-gpios = <&gpio5 4 0>;
111 audio-routing = 111 audio-routing =
112 "Headphone Jack", "HP_L", 112 "Headphone Jack", "HP_L",
113 "Headphone Jack", "HP_R", 113 "Headphone Jack", "HP_R",
114 "Ext Spk", "SPK_LP", 114 "Ext Spk", "SPK_LP",
115 "Ext Spk", "SPK_LN", 115 "Ext Spk", "SPK_LN",
116 "Ext Spk", "SPK_RP", 116 "Ext Spk", "SPK_RP",
117 "Ext Spk", "SPK_RN", 117 "Ext Spk", "SPK_RN",
118 "LINPUT2", "Mic Jack", 118 "LINPUT2", "Mic Jack",
119 "LINPUT3", "Mic Jack", 119 "LINPUT3", "Mic Jack",
120 "RINPUT1", "Main MIC", 120 "RINPUT1", "Main MIC",
121 "RINPUT2", "Main MIC", 121 "RINPUT2", "Main MIC",
122 "Mic Jack", "MICB", 122 "Mic Jack", "MICB",
123 "Main MIC", "MICB", 123 "Main MIC", "MICB",
124 "CPU-Playback", "ASRC-Playback", 124 "CPU-Playback", "ASRC-Playback",
125 "Playback", "CPU-Playback", 125 "Playback", "CPU-Playback",
126 "ASRC-Capture", "CPU-Capture", 126 "ASRC-Capture", "CPU-Capture",
127 "CPU-Capture", "Capture"; 127 "CPU-Capture", "Capture";
128 }; 128 };
129 129
130 soft_spi: soft-spi { 130 soft_spi: soft-spi {
131 compatible = "spi-gpio"; 131 compatible = "spi-gpio";
132 pinctrl-names = "default"; 132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_spi4>; 133 pinctrl-0 = <&pinctrl_spi4>;
134 pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; 134 pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
135 status = "okay"; 135 status = "okay";
136 gpio-sck = <&gpio5 11 0>; 136 gpio-sck = <&gpio5 11 0>;
137 gpio-mosi = <&gpio5 10 0>; 137 gpio-mosi = <&gpio5 10 0>;
138 cs-gpios = <&gpio5 7 0>; 138 cs-gpios = <&gpio5 7 0>;
139 num-chipselects = <1>; 139 num-chipselects = <1>;
140 #address-cells = <1>; 140 #address-cells = <1>;
141 #size-cells = <0>; 141 #size-cells = <0>;
142 142
143 gpio_spi: gpio_spi@0 { 143 gpio_spi: gpio_spi@0 {
144 compatible = "fairchild,74hc595"; 144 compatible = "fairchild,74hc595";
145 gpio-controller; 145 gpio-controller;
146 #gpio-cells = <2>; 146 #gpio-cells = <2>;
147 reg = <0>; 147 reg = <0>;
148 registers-number = <1>; 148 registers-number = <1>;
149 registers-default = /bits/ 8 <0x57>; 149 registers-default = /bits/ 8 <0x57>;
150 spi-max-frequency = <100000>; 150 spi-max-frequency = <100000>;
151 }; 151 };
152 }; 152 };
153 }; 153 };
154 154
155 &clks { 155 &clks {
156 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 156 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
157 assigned-clock-rates = <786432000>; 157 assigned-clock-rates = <786432000>;
158 }; 158 };
159 159
160 &cpu0 { 160 &cpu0 {
161 /* 161 /*
162 * on i.MX6ULL, no seperated VDD_ARM_IN and VDD_SOC_IN, 162 * on i.MX6ULL, no seperated VDD_ARM_IN and VDD_SOC_IN,
163 * to align with other platform and use the same cpufreq 163 * to align with other platform and use the same cpufreq
164 * driver, still use the seperated OPP define for arm 164 * driver, still use the seperated OPP define for arm
165 * and soc. 165 * and soc.
166 */ 166 */
167 operating-points = < 167 operating-points = <
168 /* kHz uV */ 168 /* kHz uV */
169 528000 1175000 169 528000 1175000
170 396000 1175000 170 396000 1175000
171 198000 1175000 171 198000 1175000
172 >; 172 >;
173 fsl,soc-operating-points = < 173 fsl,soc-operating-points = <
174 /* KHz uV */ 174 /* KHz uV */
175 528000 1175000 175 528000 1175000
176 396000 1175000 176 396000 1175000
177 198000 1175000 177 198000 1175000
178 >; 178 >;
179 fsl,arm-soc-shared = <1>; 179 fsl,arm-soc-shared = <1>;
180 }; 180 };
181 181
182 &reg_arm { 182 &reg_arm {
183 vin-supply = <&sw1c_reg>; 183 vin-supply = <&sw1c_reg>;
184 regulator-allow-bypass; 184 regulator-allow-bypass;
185 }; 185 };
186 186
187 &reg_soc { 187 &reg_soc {
188 vin-supply = <&sw1c_reg>; 188 vin-supply = <&sw1c_reg>;
189 regulator-allow-bypass; 189 regulator-allow-bypass;
190 }; 190 };
191 191
192 &csi { 192 &csi {
193 status = "okay"; 193 status = "okay";
194 194
195 port { 195 port {
196 csi1_ep: endpoint { 196 csi1_ep: endpoint {
197 remote-endpoint = <&ov5640_ep>; 197 remote-endpoint = <&ov5640_ep>;
198 }; 198 };
199 }; 199 };
200 }; 200 };
201 201
202 &fec1 { 202 &fec1 {
203 pinctrl-names = "default"; 203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_enet1>; 204 pinctrl-0 = <&pinctrl_enet1>;
205 phy-mode = "rmii"; 205 phy-mode = "rmii";
206 phy-handle = <&ethphy0>; 206 phy-handle = <&ethphy0>;
207 status = "okay"; 207 status = "okay";
208 }; 208 };
209 209
210 &fec2 { 210 &fec2 {
211 pinctrl-names = "default"; 211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_enet2>; 212 pinctrl-0 = <&pinctrl_enet2>;
213 phy-mode = "rmii"; 213 phy-mode = "rmii";
214 phy-handle = <&ethphy1>; 214 phy-handle = <&ethphy1>;
215 status = "okay"; 215 status = "okay";
216 216
217 mdio { 217 mdio {
218 #address-cells = <1>; 218 #address-cells = <1>;
219 #size-cells = <0>; 219 #size-cells = <0>;
220 220
221 ethphy0: ethernet-phy@2 { 221 ethphy0: ethernet-phy@2 {
222 compatible = "ethernet-phy-ieee802.3-c22"; 222 compatible = "ethernet-phy-ieee802.3-c22";
223 reg = <2>; 223 reg = <2>;
224 }; 224 };
225 225
226 ethphy1: ethernet-phy@1 { 226 ethphy1: ethernet-phy@1 {
227 compatible = "ethernet-phy-ieee802.3-c22"; 227 compatible = "ethernet-phy-ieee802.3-c22";
228 reg = <1>; 228 reg = <1>;
229 }; 229 };
230 }; 230 };
231 }; 231 };
232 232
233 &flexcan1 { 233 &flexcan1 {
234 pinctrl-names = "default"; 234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_flexcan1>; 235 pinctrl-0 = <&pinctrl_flexcan1>;
236 xceiver-supply = <&reg_can_3v3>; 236 xceiver-supply = <&reg_can_3v3>;
237 status = "okay"; 237 status = "okay";
238 }; 238 };
239 239
240 &flexcan2 { 240 &flexcan2 {
241 pinctrl-names = "default"; 241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_flexcan2>; 242 pinctrl-0 = <&pinctrl_flexcan2>;
243 xceiver-supply = <&reg_can_3v3>; 243 xceiver-supply = <&reg_can_3v3>;
244 status = "okay"; 244 status = "okay";
245 }; 245 };
246 246
247 &gpc { 247 &gpc {
248 fsl,cpu_pupscr_sw2iso = <0xf>; 248 fsl,cpu_pupscr_sw2iso = <0xf>;
249 fsl,cpu_pupscr_sw = <0x0>; 249 fsl,cpu_pupscr_sw = <0x0>;
250 fsl,cpu_pdnscr_iso2sw = <0x1>; 250 fsl,cpu_pdnscr_iso2sw = <0x1>;
251 fsl,cpu_pdnscr_iso = <0x1>; 251 fsl,cpu_pdnscr_iso = <0x1>;
252 fsl,ldo-bypass = <1>; 252 fsl,ldo-bypass = <1>;
253 }; 253 };
254 254
255 &i2c1 { 255 &i2c1 {
256 clock-frequency = <100000>; 256 clock-frequency = <100000>;
257 pinctrl-names = "default", "gpio"; 257 pinctrl-names = "default", "gpio";
258 pinctrl-0 = <&pinctrl_i2c1>; 258 pinctrl-0 = <&pinctrl_i2c1>;
259 pinctrl-1 = <&pinctrl_i2c1_gpio>; 259 pinctrl-1 = <&pinctrl_i2c1_gpio>;
260 scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; 260 scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
261 sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; 261 sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
262 status = "okay"; 262 status = "okay";
263 263
264 pmic: pfuze3000@08 { 264 pmic: pfuze3000@08 {
265 compatible = "fsl,pfuze3000"; 265 compatible = "fsl,pfuze3000";
266 reg = <0x08>; 266 reg = <0x08>;
267 267
268 regulators { 268 regulators {
269 sw1a_reg: sw1a { 269 sw1a_reg: sw1a {
270 regulator-min-microvolt = <700000>; 270 regulator-min-microvolt = <700000>;
271 regulator-max-microvolt = <3300000>; 271 regulator-max-microvolt = <3300000>;
272 regulator-boot-on; 272 regulator-boot-on;
273 regulator-always-on; 273 regulator-always-on;
274 regulator-ramp-delay = <6250>; 274 regulator-ramp-delay = <6250>;
275 }; 275 };
276 276
277 /* use sw1c_reg to align with pfuze100/pfuze200 */ 277 /* use sw1c_reg to align with pfuze100/pfuze200 */
278 sw1c_reg: sw1b { 278 sw1c_reg: sw1b {
279 regulator-min-microvolt = <700000>; 279 regulator-min-microvolt = <700000>;
280 regulator-max-microvolt = <1475000>; 280 regulator-max-microvolt = <1475000>;
281 regulator-boot-on; 281 regulator-boot-on;
282 regulator-always-on; 282 regulator-always-on;
283 regulator-ramp-delay = <6250>; 283 regulator-ramp-delay = <6250>;
284 }; 284 };
285 285
286 sw2_reg: sw2 { 286 sw2_reg: sw2 {
287 regulator-min-microvolt = <2500000>; 287 regulator-min-microvolt = <2500000>;
288 regulator-max-microvolt = <3300000>; 288 regulator-max-microvolt = <3300000>;
289 regulator-boot-on; 289 regulator-boot-on;
290 regulator-always-on; 290 regulator-always-on;
291 }; 291 };
292 292
293 sw3a_reg: sw3 { 293 sw3a_reg: sw3 {
294 regulator-min-microvolt = <900000>; 294 regulator-min-microvolt = <900000>;
295 regulator-max-microvolt = <1650000>; 295 regulator-max-microvolt = <1650000>;
296 regulator-boot-on; 296 regulator-boot-on;
297 regulator-always-on; 297 regulator-always-on;
298 }; 298 };
299 299
300 swbst_reg: swbst { 300 swbst_reg: swbst {
301 regulator-min-microvolt = <5000000>; 301 regulator-min-microvolt = <5000000>;
302 regulator-max-microvolt = <5150000>; 302 regulator-max-microvolt = <5150000>;
303 }; 303 };
304 304
305 snvs_reg: vsnvs { 305 snvs_reg: vsnvs {
306 regulator-min-microvolt = <1000000>; 306 regulator-min-microvolt = <1000000>;
307 regulator-max-microvolt = <3000000>; 307 regulator-max-microvolt = <3000000>;
308 regulator-boot-on; 308 regulator-boot-on;
309 regulator-always-on; 309 regulator-always-on;
310 }; 310 };
311 311
312 vref_reg: vrefddr { 312 vref_reg: vrefddr {
313 regulator-boot-on; 313 regulator-boot-on;
314 regulator-always-on; 314 regulator-always-on;
315 }; 315 };
316 316
317 vgen1_reg: vldo1 { 317 vgen1_reg: vldo1 {
318 regulator-min-microvolt = <1800000>; 318 regulator-min-microvolt = <1800000>;
319 regulator-max-microvolt = <3300000>; 319 regulator-max-microvolt = <3300000>;
320 regulator-always-on; 320 regulator-always-on;
321 }; 321 };
322 322
323 vgen2_reg: vldo2 { 323 vgen2_reg: vldo2 {
324 regulator-min-microvolt = <800000>; 324 regulator-min-microvolt = <800000>;
325 regulator-max-microvolt = <1550000>; 325 regulator-max-microvolt = <1550000>;
326 regulator-always-on; 326 regulator-always-on;
327 }; 327 };
328 328
329 vgen3_reg: vccsd { 329 vgen3_reg: vccsd {
330 regulator-min-microvolt = <2850000>; 330 regulator-min-microvolt = <2850000>;
331 regulator-max-microvolt = <3300000>; 331 regulator-max-microvolt = <3300000>;
332 regulator-always-on; 332 regulator-always-on;
333 }; 333 };
334 334
335 vgen4_reg: v33 { 335 vgen4_reg: v33 {
336 regulator-min-microvolt = <2850000>; 336 regulator-min-microvolt = <2850000>;
337 regulator-max-microvolt = <3300000>; 337 regulator-max-microvolt = <3300000>;
338 regulator-always-on; 338 regulator-always-on;
339 }; 339 };
340 340
341 vgen5_reg: vldo3 { 341 vgen5_reg: vldo3 {
342 regulator-min-microvolt = <1800000>; 342 regulator-min-microvolt = <1800000>;
343 regulator-max-microvolt = <3300000>; 343 regulator-max-microvolt = <3300000>;
344 regulator-always-on; 344 regulator-always-on;
345 }; 345 };
346 346
347 vgen6_reg: vldo4 { 347 vgen6_reg: vldo4 {
348 regulator-min-microvolt = <1800000>; 348 regulator-min-microvolt = <1800000>;
349 regulator-max-microvolt = <3300000>; 349 regulator-max-microvolt = <3300000>;
350 regulator-always-on; 350 regulator-always-on;
351 }; 351 };
352 }; 352 };
353 }; 353 };
354 354
355 mag3110@0e { 355 mag3110@0e {
356 compatible = "fsl,mag3110"; 356 compatible = "fsl,mag3110";
357 reg = <0x0e>; 357 reg = <0x0e>;
358 position = <2>; 358 position = <2>;
359 }; 359 };
360 360
361 fxls8471@1e { 361 fxls8471@1e {
362 compatible = "fsl,fxls8471"; 362 compatible = "fsl,fxls8471";
363 reg = <0x1e>; 363 reg = <0x1e>;
364 position = <0>; 364 position = <0>;
365 interrupt-parent = <&gpio5>; 365 interrupt-parent = <&gpio5>;
366 interrupts = <0 8>; 366 interrupts = <0 8>;
367 }; 367 };
368 }; 368 };
369 369
370 &i2c2 { 370 &i2c2 {
371 clock_frequency = <100000>; 371 clock_frequency = <100000>;
372 pinctrl-names = "default", "gpio"; 372 pinctrl-names = "default", "gpio";
373 pinctrl-0 = <&pinctrl_i2c2>; 373 pinctrl-0 = <&pinctrl_i2c2>;
374 pinctrl-1 = <&pinctrl_i2c2_gpio>; 374 pinctrl-1 = <&pinctrl_i2c2_gpio>;
375 scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; 375 scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
376 sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; 376 sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
377 status = "okay"; 377 status = "okay";
378 378
379 codec: wm8960@1a { 379 codec: wm8960@1a {
380 compatible = "wlf,wm8960"; 380 compatible = "wlf,wm8960";
381 reg = <0x1a>; 381 reg = <0x1a>;
382 clocks = <&clks IMX6UL_CLK_SAI2>; 382 clocks = <&clks IMX6UL_CLK_SAI2>;
383 clock-names = "mclk"; 383 clock-names = "mclk";
384 wlf,shared-lrclk; 384 wlf,shared-lrclk;
385 }; 385 };
386 386
387 ov5640: ov5640@3c { 387 ov5640: ov5640@3c {
388 compatible = "ovti,ov5640"; 388 compatible = "ovti,ov5640";
389 reg = <0x3c>; 389 reg = <0x3c>;
390 pinctrl-names = "default"; 390 pinctrl-names = "default";
391 pinctrl-0 = <&pinctrl_csi1>; 391 pinctrl-0 = <&pinctrl_csi1>;
392 clocks = <&clks IMX6UL_CLK_CSI>; 392 clocks = <&clks IMX6UL_CLK_CSI>;
393 clock-names = "csi_mclk"; 393 clock-names = "csi_mclk";
394 pwn-gpios = <&gpio_spi 6 1>; 394 pwn-gpios = <&gpio_spi 6 1>;
395 rst-gpios = <&gpio_spi 5 0>; 395 rst-gpios = <&gpio_spi 5 0>;
396 csi_id = <0>; 396 csi_id = <0>;
397 mclk = <24000000>; 397 mclk = <24000000>;
398 mclk_source = <0>; 398 mclk_source = <0>;
399 status = "okay"; 399 status = "okay";
400 port { 400 port {
401 ov5640_ep: endpoint { 401 ov5640_ep: endpoint {
402 remote-endpoint = <&csi1_ep>; 402 remote-endpoint = <&csi1_ep>;
403 }; 403 };
404 }; 404 };
405 }; 405 };
406 }; 406 };
407 407
408 &iomuxc { 408 &iomuxc {
409 pinctrl-names = "default"; 409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_hog_1>; 410 pinctrl-0 = <&pinctrl_hog_1>;
411 imx6ul-evk { 411 imx6ul-evk {
412 pinctrl_csi1: csi1grp { 412 pinctrl_csi1: csi1grp {
413 fsl,pins = < 413 fsl,pins = <
414 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 414 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
415 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 415 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
416 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 416 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
417 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 417 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
418 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 418 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
419 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 419 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
420 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 420 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
421 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 421 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
422 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 422 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
423 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 423 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
424 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 424 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
425 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 425 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
426 >; 426 >;
427 }; 427 };
428 428
429 pinctrl_enet1: enet1grp { 429 pinctrl_enet1: enet1grp {
430 fsl,pins = < 430 fsl,pins = <
431 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 431 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
432 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 432 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
433 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 433 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
434 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 434 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
435 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 435 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
436 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 436 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
437 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 437 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
438 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 438 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
439 >; 439 >;
440 }; 440 };
441 441
442 pinctrl_enet2: enet2grp { 442 pinctrl_enet2: enet2grp {
443 fsl,pins = < 443 fsl,pins = <
444 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 444 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
445 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 445 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
446 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 446 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
447 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 447 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
448 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 448 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
449 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 449 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
450 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 450 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
451 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 451 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
452 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 452 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
453 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 453 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
454 >; 454 >;
455 }; 455 };
456 456
457 pinctrl_flexcan1: flexcan1grp{ 457 pinctrl_flexcan1: flexcan1grp{
458 fsl,pins = < 458 fsl,pins = <
459 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 459 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
460 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 460 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
461 >; 461 >;
462 }; 462 };
463 463
464 pinctrl_flexcan2: flexcan2grp{ 464 pinctrl_flexcan2: flexcan2grp{
465 fsl,pins = < 465 fsl,pins = <
466 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 466 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
467 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 467 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
468 >; 468 >;
469 }; 469 };
470 470
471 pinctrl_hog_1: hoggrp-1 { 471 pinctrl_hog_1: hoggrp-1 {
472 fsl,pins = < 472 fsl,pins = <
473 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ 473 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
474 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ 474 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
475 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ 475 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
476 >; 476 >;
477 }; 477 };
478 478
479 pinctrl_i2c1: i2c1grp { 479 pinctrl_i2c1: i2c1grp {
480 fsl,pins = < 480 fsl,pins = <
481 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 481 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
482 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 482 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
483 >; 483 >;
484 }; 484 };
485 485
486 pinctrl_i2c1_gpio: i2c1grp_gpio { 486 pinctrl_i2c1_gpio: i2c1grp_gpio {
487 fsl,pins = < 487 fsl,pins = <
488 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 488 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
489 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 489 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
490 >; 490 >;
491 }; 491 };
492 492
493 pinctrl_i2c2: i2c2grp { 493 pinctrl_i2c2: i2c2grp {
494 fsl,pins = < 494 fsl,pins = <
495 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 495 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
496 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 496 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
497 >; 497 >;
498 }; 498 };
499 499
500 pinctrl_i2c2_gpio: i2c2grp_gpio { 500 pinctrl_i2c2_gpio: i2c2grp_gpio {
501 fsl,pins = < 501 fsl,pins = <
502 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 502 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
503 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 503 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
504 >; 504 >;
505 }; 505 };
506 506
507 pinctrl_lcdif_ctrl: lcdifctrlgrp { 507 pinctrl_lcdif_ctrl: lcdifctrlgrp {
508 fsl,pins = < 508 fsl,pins = <
509 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 509 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
510 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 510 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
511 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 511 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
512 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 512 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
513 >; 513 >;
514 }; 514 };
515 515
516 pinctrl_lcdif_dat: lcdifdatgrp { 516 pinctrl_lcdif_dat: lcdifdatgrp {
517 fsl,pins = < 517 fsl,pins = <
518 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 518 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
519 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 519 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
520 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 520 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
521 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 521 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
522 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 522 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
523 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 523 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
524 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 524 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
525 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 525 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
526 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 526 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
527 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 527 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
528 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 528 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
529 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 529 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
530 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 530 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
531 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 531 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
532 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 532 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
533 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 533 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
534 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 534 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
535 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 535 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
536 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 536 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
537 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 537 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
538 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 538 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
539 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 539 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
540 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 540 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
541 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 541 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
542 >; 542 >;
543 }; 543 };
544 544
545 pinctrl_pwm1: pwm1grp { 545 pinctrl_pwm1: pwm1grp {
546 fsl,pins = < 546 fsl,pins = <
547 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 547 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
548 >; 548 >;
549 }; 549 };
550 550
551 pinctrl_qspi: qspigrp { 551 pinctrl_qspi: qspigrp {
552 fsl,pins = < 552 fsl,pins = <
553 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 553 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
554 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 554 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
555 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 555 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
556 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 556 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
557 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 557 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
558 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 558 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
559 >; 559 >;
560 }; 560 };
561 561
562 pinctrl_sai2: sai2grp { 562 pinctrl_sai2: sai2grp {
563 fsl,pins = < 563 fsl,pins = <
564 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 564 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
565 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 565 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
566 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 566 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
567 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 567 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
568 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 568 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
569 >; 569 >;
570 }; 570 };
571 571
572 pinctrl_tsc: tscgrp { 572 pinctrl_tsc: tscgrp {
573 fsl,pins = < 573 fsl,pins = <
574 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 574 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
575 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 575 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
576 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 576 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
577 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 577 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
578 >; 578 >;
579 }; 579 };
580 580
581 pinctrl_uart1: uart1grp { 581 pinctrl_uart1: uart1grp {
582 fsl,pins = < 582 fsl,pins = <
583 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 583 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
584 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 584 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
585 >; 585 >;
586 }; 586 };
587 587
588 pinctrl_uart2: uart2grp { 588 pinctrl_uart2: uart2grp {
589 fsl,pins = < 589 fsl,pins = <
590 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 590 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
591 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 591 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
592 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 592 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
593 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 593 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
594 >; 594 >;
595 }; 595 };
596 596
597 pinctrl_uart2dte: uart2dtegrp { 597 pinctrl_uart2dte: uart2dtegrp {
598 fsl,pins = < 598 fsl,pins = <
599 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 599 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
600 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 600 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
601 MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 601 MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1
602 MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 602 MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1
603 >; 603 >;
604 }; 604 };
605 605
606 pinctrl_usb_otg1_id: usbotg1idgrp { 606 pinctrl_usb_otg1_id: usbotg1idgrp {
607 fsl,pins = < 607 fsl,pins = <
608 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 608 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
609 >; 609 >;
610 }; 610 };
611 611
612 pinctrl_usdhc1: usdhc1grp { 612 pinctrl_usdhc1: usdhc1grp {
613 fsl,pins = < 613 fsl,pins = <
614 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 614 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
615 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 615 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
616 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 616 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
617 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 617 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
618 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 618 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
619 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 619 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
620 >; 620 >;
621 }; 621 };
622 622
623 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 623 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
624 fsl,pins = < 624 fsl,pins = <
625 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 625 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
626 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 626 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
627 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 627 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
628 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 628 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
629 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 629 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
630 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 630 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
631 >; 631 >;
632 }; 632 };
633 633
634 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 634 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
635 fsl,pins = < 635 fsl,pins = <
636 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 636 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
637 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 637 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
638 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 638 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
639 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 639 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
640 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 640 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
641 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 641 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
642 >; 642 >;
643 }; 643 };
644 644
645 pinctrl_usdhc2: usdhc2grp { 645 pinctrl_usdhc2: usdhc2grp {
646 fsl,pins = < 646 fsl,pins = <
647 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 647 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
648 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 648 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
649 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 649 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
650 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 650 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
651 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 651 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
652 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 652 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
653 >; 653 >;
654 }; 654 };
655 655
656 pinctrl_wdog: wdoggrp { 656 pinctrl_wdog: wdoggrp {
657 fsl,pins = < 657 fsl,pins = <
658 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 658 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
659 >; 659 >;
660 }; 660 };
661 }; 661 };
662 }; 662 };
663 663
664 &iomuxc_snvs { 664 &iomuxc_snvs {
665 pinctrl-names = "default_snvs"; 665 pinctrl-names = "default_snvs";
666 pinctrl-0 = <&pinctrl_hog_2>; 666 pinctrl-0 = <&pinctrl_hog_2>;
667 imx6ull-evk { 667 imx6ull-evk {
668 pinctrl_hog_2: hoggrp-2 { 668 pinctrl_hog_2: hoggrp-2 {
669 fsl,pins = < 669 fsl,pins = <
670 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 670 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000
671 >; 671 >;
672 }; 672 };
673 673
674 pinctrl_dvfs: dvfsgrp { 674 pinctrl_dvfs: dvfsgrp {
675 fsl,pins = < 675 fsl,pins = <
676 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 676 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79
677 >; 677 >;
678 }; 678 };
679 679
680 pinctrl_lcdif_reset: lcdifresetgrp { 680 pinctrl_lcdif_reset: lcdifresetgrp {
681 fsl,pins = < 681 fsl,pins = <
682 /* used for lcd reset */ 682 /* used for lcd reset */
683 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 683 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
684 >; 684 >;
685 }; 685 };
686 686
687 pinctrl_spi4: spi4grp { 687 pinctrl_spi4: spi4grp {
688 fsl,pins = < 688 fsl,pins = <
689 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 689 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
690 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 690 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
691 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 691 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
692 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 692 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
693 >; 693 >;
694 }; 694 };
695 695
696 pinctrl_sai2_hp_det_b: sai2_hp_det_grp { 696 pinctrl_sai2_hp_det_b: sai2_hp_det_grp {
697 fsl,pins = < 697 fsl,pins = <
698 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 698 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
699 >; 699 >;
700 }; 700 };
701 }; 701 };
702 }; 702 };
703 703
704 &lcdif { 704 &lcdif {
705 pinctrl-names = "default"; 705 pinctrl-names = "default";
706 pinctrl-0 = <&pinctrl_lcdif_dat 706 pinctrl-0 = <&pinctrl_lcdif_dat
707 &pinctrl_lcdif_ctrl 707 &pinctrl_lcdif_ctrl
708 &pinctrl_lcdif_reset>; 708 &pinctrl_lcdif_reset>;
709 display = <&display0>; 709 display = <&display0>;
710 status = "okay"; 710 status = "okay";
711 711
712 display0: display { 712 display0: display {
713 bits-per-pixel = <16>; 713 bits-per-pixel = <16>;
714 bus-width = <24>; 714 bus-width = <24>;
715 715
716 display-timings { 716 display-timings {
717 native-mode = <&timing0>; 717 native-mode = <&timing0>;
718 timing0: timing0 { 718 timing0: timing0 {
719 clock-frequency = <9200000>; 719 clock-frequency = <9200000>;
720 hactive = <480>; 720 hactive = <480>;
721 vactive = <272>; 721 vactive = <272>;
722 hfront-porch = <8>; 722 hfront-porch = <8>;
723 hback-porch = <4>; 723 hback-porch = <4>;
724 hsync-len = <41>; 724 hsync-len = <41>;
725 vback-porch = <2>; 725 vback-porch = <2>;
726 vfront-porch = <4>; 726 vfront-porch = <4>;
727 vsync-len = <10>; 727 vsync-len = <10>;
728 728
729 hsync-active = <0>; 729 hsync-active = <0>;
730 vsync-active = <0>; 730 vsync-active = <0>;
731 de-active = <1>; 731 de-active = <1>;
732 pixelclk-active = <0>; 732 pixelclk-active = <0>;
733 }; 733 };
734 }; 734 };
735 }; 735 };
736 }; 736 };
737 737
738 &pwm1 { 738 &pwm1 {
739 pinctrl-names = "default"; 739 pinctrl-names = "default";
740 pinctrl-0 = <&pinctrl_pwm1>; 740 pinctrl-0 = <&pinctrl_pwm1>;
741 status = "okay"; 741 status = "okay";
742 }; 742 };
743 743
744 &pxp { 744 &pxp {
745 status = "okay"; 745 status = "okay";
746 }; 746 };
747 747
748 &qspi { 748 &qspi {
749 pinctrl-names = "default"; 749 pinctrl-names = "default";
750 pinctrl-0 = <&pinctrl_qspi>; 750 pinctrl-0 = <&pinctrl_qspi>;
751 status = "okay"; 751 status = "okay";
752 ddrsmp=<0>; 752 ddrsmp=<0>;
753 753
754 flash0: n25q256a@0 { 754 flash0: n25q256a@0 {
755 #address-cells = <1>; 755 #address-cells = <1>;
756 #size-cells = <1>; 756 #size-cells = <1>;
757 compatible = "micron,n25q256a", "jedec,spi-nor"; 757 compatible = "micron,n25q256a", "jedec,spi-nor";
758 spi-max-frequency = <29000000>; 758 spi-max-frequency = <29000000>;
759 spi-nor,ddr-quad-read-dummy = <6>; 759 spi-nor,ddr-quad-read-dummy = <6>;
760 reg = <0>; 760 reg = <0>;
761 }; 761 };
762 }; 762 };
763 763
764 &sai2 { 764 &sai2 {
765 pinctrl-names = "default"; 765 pinctrl-names = "default";
766 pinctrl-0 = <&pinctrl_sai2 766 pinctrl-0 = <&pinctrl_sai2
767 &pinctrl_sai2_hp_det_b>; 767 &pinctrl_sai2_hp_det_b>;
768 768
769 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, 769 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
770 <&clks IMX6UL_CLK_SAI2>; 770 <&clks IMX6UL_CLK_SAI2>;
771 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 771 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
772 assigned-clock-rates = <0>, <12288000>; 772 assigned-clock-rates = <0>, <12288000>;
773 773
774 status = "okay"; 774 status = "okay";
775 }; 775 };
776 776
777 &tsc { 777 &tsc {
778 pinctrl-names = "default"; 778 pinctrl-names = "default";
779 pinctrl-0 = <&pinctrl_tsc>; 779 pinctrl-0 = <&pinctrl_tsc>;
780 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; 780 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
781 measure_delay_time = <0xffff>; 781 measure_delay_time = <0xffff>;
782 pre_charge_time = <0xfff>; 782 pre_charge_time = <0xfff>;
783 status = "okay"; 783 status = "okay";
784 }; 784 };
785 785
786 &uart1 { 786 &uart1 {
787 pinctrl-names = "default"; 787 pinctrl-names = "default";
788 pinctrl-0 = <&pinctrl_uart1>; 788 pinctrl-0 = <&pinctrl_uart1>;
789 status = "okay"; 789 status = "okay";
790 }; 790 };
791 791
792 &uart2 { 792 &uart2 {
793 pinctrl-names = "default"; 793 pinctrl-names = "default";
794 pinctrl-0 = <&pinctrl_uart2>; 794 pinctrl-0 = <&pinctrl_uart2>;
795 fsl,uart-has-rtscts; 795 fsl,uart-has-rtscts;
796 /* for DTE mode, add below change */ 796 /* for DTE mode, add below change */
797 /* fsl,dte-mode; */ 797 /* fsl,dte-mode; */
798 /* pinctrl-0 = <&pinctrl_uart2dte>; */ 798 /* pinctrl-0 = <&pinctrl_uart2dte>; */
799 status = "okay"; 799 status = "okay";
800 }; 800 };
801 801
802 &usbotg1 { 802 &usbotg1 {
803 pinctrl-names = "default"; 803 pinctrl-names = "default";
804 pinctrl-0 = <&pinctrl_usb_otg1_id>; 804 pinctrl-0 = <&pinctrl_usb_otg1_id>;
805 dr_mode = "otg"; 805 dr_mode = "otg";
806 srp-disable; 806 srp-disable;
807 hnp-disable; 807 hnp-disable;
808 adp-disable; 808 adp-disable;
809 status = "okay"; 809 status = "okay";
810 }; 810 };
811 811
812 &usbotg2 { 812 &usbotg2 {
813 dr_mode = "host"; 813 dr_mode = "host";
814 disable-over-current; 814 disable-over-current;
815 status = "okay"; 815 status = "okay";
816 }; 816 };
817 817
818 &usdhc1 { 818 &usdhc1 {
819 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 819 pinctrl-names = "default", "state_100mhz", "state_200mhz";
820 pinctrl-0 = <&pinctrl_usdhc1>; 820 pinctrl-0 = <&pinctrl_usdhc1>;
821 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 821 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
822 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 822 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
823 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 823 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
824 keep-power-in-suspend; 824 keep-power-in-suspend;
825 enable-sdio-wakeup; 825 enable-sdio-wakeup;
826 vmmc-supply = <&reg_sd1_vmmc>; 826 vmmc-supply = <&reg_sd1_vmmc>;
827 status = "okay"; 827 status = "okay";
828 }; 828 };
829 829
830 &usdhc2 { 830 &usdhc2 {
831 pinctrl-names = "default"; 831 pinctrl-names = "default";
832 pinctrl-0 = <&pinctrl_usdhc2>; 832 pinctrl-0 = <&pinctrl_usdhc2>;
833 no-1-8-v; 833 no-1-8-v;
834 non-removable; 834 non-removable;
835 keep-power-in-suspend; 835 keep-power-in-suspend;
836 enable-sdio-wakeup; 836 enable-sdio-wakeup;
837 status = "okay"; 837 status = "okay";
838 }; 838 };
839 839
840 &wdog1 { 840 &wdog1 {
841 pinctrl-names = "default"; 841 pinctrl-names = "default";
842 pinctrl-0 = <&pinctrl_wdog>; 842 pinctrl-0 = <&pinctrl_wdog>;
843 fsl,ext-reset-output; 843 fsl,ext-reset-output;
844 }; 844 };
845 845
arch/arm/dts/imx7d-sdb.dts
Diff comments   View file @ 4daafb3
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include "imx7d.dtsi" 8 #include "imx7d.dtsi"
9 9
10 / { 10 / {
11 model = "Freescale i.MX7 SabreSD Board"; 11 model = "Freescale i.MX7 SabreSD Board";
12 compatible = "fsl,imx7d-sdb", "fsl,imx7d"; 12 compatible = "fsl,imx7d-sdb", "fsl,imx7d";
13 13
14 aliases { 14 aliases {
15 spi5 = &soft_spi; 15 spi5 = &soft_spi;
16 }; 16 };
17 17
18 chosen { 18 chosen {
19 stdout-path = &uart1; 19 stdout-path = &uart1;
20 }; 20 };
21 21
22 memory { 22 memory {
23 reg = <0x80000000 0x80000000>; 23 reg = <0x80000000 0x80000000>;
24 }; 24 };
25 25
26 modem_reset: modem-reset { 26 modem_reset: modem-reset {
27 compatible = "gpio-reset"; 27 compatible = "gpio-reset";
28 reset-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; 28 reset-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
29 reset-delay-us = <1000>; 29 reset-delay-us = <1000>;
30 #reset-cells = <0>; 30 #reset-cells = <0>;
31 }; 31 };
32 32
33 soft_spi: soft-spi { 33 soft_spi: soft-spi {
34 compatible = "spi-gpio"; 34 compatible = "spi-gpio";
35 pinctrl-names = "default"; 35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_spi4>; 36 pinctrl-0 = <&pinctrl_spi4>;
37 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; 37 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
38 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; 38 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
39 cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; 39 cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
40 num-chipselects = <1>; 40 num-chipselects = <1>;
41 #address-cells = <1>; 41 #address-cells = <1>;
42 #size-cells = <0>; 42 #size-cells = <0>;
43 43
44 extended_io: gpio-expander@0 { 44 extended_io: gpio-expander@0 {
45 compatible = "fairchild,74hc595"; 45 compatible = "fairchild,74hc595";
46 gpio-controller; 46 gpio-controller;
47 #gpio-cells = <2>; 47 #gpio-cells = <2>;
48 reg = <0>; 48 reg = <0>;
49 registers-number = <1>; 49 registers-number = <1>;
50 registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/ 50 registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/
51 spi-max-frequency = <100000>; 51 spi-max-frequency = <100000>;
52 }; 52 };
53 }; 53 };
54 54
55 reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 55 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
56 compatible = "regulator-fixed"; 56 compatible = "regulator-fixed";
57 regulator-name = "usb_otg1_vbus"; 57 regulator-name = "usb_otg1_vbus";
58 regulator-min-microvolt = <5000000>; 58 regulator-min-microvolt = <5000000>;
59 regulator-max-microvolt = <5000000>; 59 regulator-max-microvolt = <5000000>;
60 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 60 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
61 enable-active-high; 61 enable-active-high;
62 }; 62 };
63 63
64 reg_usb_otg2_vbus: regulator-usb-otg2-vbus { 64 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
65 compatible = "regulator-fixed"; 65 compatible = "regulator-fixed";
66 regulator-name = "usb_otg2_vbus"; 66 regulator-name = "usb_otg2_vbus";
67 regulator-min-microvolt = <5000000>; 67 regulator-min-microvolt = <5000000>;
68 regulator-max-microvolt = <5000000>; 68 regulator-max-microvolt = <5000000>;
69 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 69 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
70 enable-active-high; 70 enable-active-high;
71 }; 71 };
72 72
73 reg_vref_1v8: regulator-vref-1v8 { 73 reg_vref_1v8: regulator-vref-1v8 {
74 compatible = "regulator-fixed"; 74 compatible = "regulator-fixed";
75 regulator-name = "vref-1v8"; 75 regulator-name = "vref-1v8";
76 regulator-min-microvolt = <1800000>; 76 regulator-min-microvolt = <1800000>;
77 regulator-max-microvolt = <1800000>; 77 regulator-max-microvolt = <1800000>;
78 }; 78 };
79 79
80 reg_can2_3v3: regulator-can2-3v3 { 80 reg_can2_3v3: regulator-can2-3v3 {
81 compatible = "regulator-fixed"; 81 compatible = "regulator-fixed";
82 regulator-name = "can2-3v3"; 82 regulator-name = "can2-3v3";
83 pinctrl-names = "default"; 83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_flexcan2_reg>; 84 pinctrl-0 = <&pinctrl_flexcan2_reg>;
85 regulator-min-microvolt = <3300000>; 85 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <3300000>; 86 regulator-max-microvolt = <3300000>;
87 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; 87 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
88 }; 88 };
89 89
90 reg_sd1_vmmc: regulator-sd1-vmmc { 90 reg_sd1_vmmc: regulator-sd1-vmmc {
91 compatible = "regulator-fixed"; 91 compatible = "regulator-fixed";
92 regulator-name = "VDD_SD1"; 92 regulator-name = "VDD_SD1";
93 regulator-min-microvolt = <3300000>; 93 regulator-min-microvolt = <3300000>;
94 regulator-max-microvolt = <3300000>; 94 regulator-max-microvolt = <3300000>;
95 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; 95 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
96 startup-delay-us = <200000>; 96 startup-delay-us = <200000>;
97 off-on-delay = <20000>; 97 u-boot,off-on-delay-us = <20000>;
98 enable-active-high; 98 enable-active-high;
99 }; 99 };
100 100
101 backlight { 101 backlight {
102 compatible = "pwm-backlight"; 102 compatible = "pwm-backlight";
103 pwms = <&pwm1 0 5000000 0>; 103 pwms = <&pwm1 0 5000000 0>;
104 brightness-levels = <0 4 8 16 32 64 128 255>; 104 brightness-levels = <0 4 8 16 32 64 128 255>;
105 default-brightness-level = <6>; 105 default-brightness-level = <6>;
106 status = "okay"; 106 status = "okay";
107 }; 107 };
108 108
109 pxp_v4l2_out { 109 pxp_v4l2_out {
110 compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; 110 compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
111 status = "okay"; 111 status = "okay";
112 }; 112 };
113 113
114 sound { 114 sound {
115 compatible = "fsl,imx7d-evk-wm8960", 115 compatible = "fsl,imx7d-evk-wm8960",
116 "fsl,imx-audio-wm8960"; 116 "fsl,imx-audio-wm8960";
117 model = "wm8960-audio"; 117 model = "wm8960-audio";
118 cpu-dai = <&sai1>; 118 cpu-dai = <&sai1>;
119 audio-codec = <&codec>; 119 audio-codec = <&codec>;
120 codec-master; 120 codec-master;
121 /* JD2: hp detect high for headphone*/ 121 /* JD2: hp detect high for headphone*/
122 hp-det = <2 0>; 122 hp-det = <2 0>;
123 hp-det-gpios = <&gpio2 28 0>; 123 hp-det-gpios = <&gpio2 28 0>;
124 audio-routing = 124 audio-routing =
125 "Headphone Jack", "HP_L", 125 "Headphone Jack", "HP_L",
126 "Headphone Jack", "HP_R", 126 "Headphone Jack", "HP_R",
127 "Ext Spk", "SPK_LP", 127 "Ext Spk", "SPK_LP",
128 "Ext Spk", "SPK_LN", 128 "Ext Spk", "SPK_LN",
129 "Ext Spk", "SPK_RP", 129 "Ext Spk", "SPK_RP",
130 "Ext Spk", "SPK_RN", 130 "Ext Spk", "SPK_RN",
131 "LINPUT1", "Main MIC", 131 "LINPUT1", "Main MIC",
132 "Main MIC", "MICB"; 132 "Main MIC", "MICB";
133 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, 133 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
134 <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; 134 <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
135 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 135 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
136 assigned-clock-rates = <0>, <12288000>; 136 assigned-clock-rates = <0>, <12288000>;
137 }; 137 };
138 138
139 sound-hdmi { 139 sound-hdmi {
140 compatible = "fsl,imx7d-sdb-sii902x", 140 compatible = "fsl,imx7d-sdb-sii902x",
141 "fsl,imx-audio-sii902x"; 141 "fsl,imx-audio-sii902x";
142 model = "sii902x-audio"; 142 model = "sii902x-audio";
143 cpu-dai = <&sai3>; 143 cpu-dai = <&sai3>;
144 hdmi-controler = <&sii902x>; 144 hdmi-controler = <&sii902x>;
145 }; 145 };
146 146
147 usdhc2_pwrseq: usdhc2_pwrseq { 147 usdhc2_pwrseq: usdhc2_pwrseq {
148 compatible = "mmc-pwrseq-simple"; 148 compatible = "mmc-pwrseq-simple";
149 pinctrl-names = "default"; 149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_brcm_reg>; 150 pinctrl-0 = <&pinctrl_brcm_reg>;
151 reset-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; 151 reset-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
152 }; 152 };
153 }; 153 };
154 154
155 &adc1 { 155 &adc1 {
156 vref-supply = <&reg_vref_1v8>; 156 vref-supply = <&reg_vref_1v8>;
157 status = "okay"; 157 status = "okay";
158 }; 158 };
159 159
160 &adc2 { 160 &adc2 {
161 vref-supply = <&reg_vref_1v8>; 161 vref-supply = <&reg_vref_1v8>;
162 status = "okay"; 162 status = "okay";
163 }; 163 };
164 164
165 &cpu0 { 165 &cpu0 {
166 arm-supply = <&sw1a_reg>; 166 arm-supply = <&sw1a_reg>;
167 }; 167 };
168 168
169 &ecspi3 { 169 &ecspi3 {
170 fsl,spi-num-chipselects = <1>; 170 fsl,spi-num-chipselects = <1>;
171 pinctrl-names = "default"; 171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; 172 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
173 cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; 173 cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
174 status = "okay"; 174 status = "okay";
175 175
176 tsc2046@0 { 176 tsc2046@0 {
177 compatible = "ti,tsc2046"; 177 compatible = "ti,tsc2046";
178 reg = <0>; 178 reg = <0>;
179 spi-max-frequency = <1000000>; 179 spi-max-frequency = <1000000>;
180 pinctrl-names ="default"; 180 pinctrl-names ="default";
181 pinctrl-0 = <&pinctrl_tsc2046_pendown>; 181 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
182 interrupt-parent = <&gpio2>; 182 interrupt-parent = <&gpio2>;
183 interrupts = <29 0>; 183 interrupts = <29 0>;
184 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; 184 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
185 ti,x-min = /bits/ 16 <0>; 185 ti,x-min = /bits/ 16 <0>;
186 ti,x-max = /bits/ 16 <0>; 186 ti,x-max = /bits/ 16 <0>;
187 ti,y-min = /bits/ 16 <0>; 187 ti,y-min = /bits/ 16 <0>;
188 ti,y-max = /bits/ 16 <0>; 188 ti,y-max = /bits/ 16 <0>;
189 ti,pressure-max = /bits/ 16 <0>; 189 ti,pressure-max = /bits/ 16 <0>;
190 ti,x-plate-ohms = /bits/ 16 <400>; 190 ti,x-plate-ohms = /bits/ 16 <400>;
191 wakeup-source; 191 wakeup-source;
192 }; 192 };
193 }; 193 };
194 194
195 &clks { 195 &clks {
196 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 196 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
197 assigned-clock-rates = <884736000>; 197 assigned-clock-rates = <884736000>;
198 }; 198 };
199 199
200 &csi1 { 200 &csi1 {
201 csi-mux-mipi = <&gpr 0x14 4>; 201 csi-mux-mipi = <&gpr 0x14 4>;
202 fsl,mipi-mode; 202 fsl,mipi-mode;
203 status = "okay"; 203 status = "okay";
204 204
205 port { 205 port {
206 csi_ep: endpoint { 206 csi_ep: endpoint {
207 remote-endpoint = <&csi_mipi_ep>; 207 remote-endpoint = <&csi_mipi_ep>;
208 }; 208 };
209 }; 209 };
210 }; 210 };
211 211
212 &epdc { 212 &epdc {
213 pinctrl-names = "default"; 213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_epdc0 &pinctrl_enet2_epdc0_en>; 214 pinctrl-0 = <&pinctrl_epdc0 &pinctrl_enet2_epdc0_en>;
215 V3P3-supply = <&V3P3_reg>; 215 V3P3-supply = <&V3P3_reg>;
216 VCOM-supply = <&VCOM_reg>; 216 VCOM-supply = <&VCOM_reg>;
217 DISPLAY-supply = <&DISPLAY_reg>; 217 DISPLAY-supply = <&DISPLAY_reg>;
218 en-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 218 en-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
219 status = "disabled"; 219 status = "disabled";
220 }; 220 };
221 221
222 &epxp { 222 &epxp {
223 status = "okay"; 223 status = "okay";
224 }; 224 };
225 225
226 &fec1 { 226 &fec1 {
227 pinctrl-names = "default"; 227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_enet1>; 228 pinctrl-0 = <&pinctrl_enet1>;
229 assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, 229 assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>,
230 <&clks IMX7D_ENET_AXI_ROOT_SRC>, 230 <&clks IMX7D_ENET_AXI_ROOT_SRC>,
231 <&clks IMX7D_ENET1_TIME_ROOT_SRC>, 231 <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
232 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 232 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
233 <&clks IMX7D_ENET_AXI_ROOT_CLK>; 233 <&clks IMX7D_ENET_AXI_ROOT_CLK>;
234 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, 234 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>,
235 <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, 235 <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
236 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 236 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
237 assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; 237 assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>;
238 phy-mode = "rgmii"; 238 phy-mode = "rgmii";
239 phy-handle = <&ethphy0>; 239 phy-handle = <&ethphy0>;
240 fsl,magic-packet; 240 fsl,magic-packet;
241 phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>; 241 phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
242 status = "okay"; 242 status = "okay";
243 243
244 mdio { 244 mdio {
245 #address-cells = <1>; 245 #address-cells = <1>;
246 #size-cells = <0>; 246 #size-cells = <0>;
247 247
248 ethphy0: ethernet-phy@0 { 248 ethphy0: ethernet-phy@0 {
249 compatible = "ethernet-phy-ieee802.3-c22"; 249 compatible = "ethernet-phy-ieee802.3-c22";
250 reg = <0>; 250 reg = <0>;
251 }; 251 };
252 252
253 ethphy1: ethernet-phy@1 { 253 ethphy1: ethernet-phy@1 {
254 compatible = "ethernet-phy-ieee802.3-c22"; 254 compatible = "ethernet-phy-ieee802.3-c22";
255 reg = <1>; 255 reg = <1>;
256 }; 256 };
257 }; 257 };
258 }; 258 };
259 259
260 &fec2 { 260 &fec2 {
261 pinctrl-names = "default"; 261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_epdc0_en>; 262 pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_epdc0_en>;
263 pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 263 pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
264 assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, 264 assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>,
265 <&clks IMX7D_ENET_AXI_ROOT_SRC>, 265 <&clks IMX7D_ENET_AXI_ROOT_SRC>,
266 <&clks IMX7D_ENET2_TIME_ROOT_SRC>, 266 <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
267 <&clks IMX7D_ENET2_TIME_ROOT_CLK>, 267 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
268 <&clks IMX7D_ENET_AXI_ROOT_CLK>; 268 <&clks IMX7D_ENET_AXI_ROOT_CLK>;
269 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, 269 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>,
270 <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, 270 <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
271 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 271 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
272 assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; 272 assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>;
273 phy-mode = "rgmii"; 273 phy-mode = "rgmii";
274 phy-handle = <&ethphy1>; 274 phy-handle = <&ethphy1>;
275 fsl,magic-packet; 275 fsl,magic-packet;
276 status = "okay"; 276 status = "okay";
277 }; 277 };
278 278
279 &flexcan2 { 279 &flexcan2 {
280 pinctrl-names = "default"; 280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_flexcan2>; 281 pinctrl-0 = <&pinctrl_flexcan2>;
282 xceiver-supply = <&reg_can2_3v3>; 282 xceiver-supply = <&reg_can2_3v3>;
283 status = "okay"; 283 status = "okay";
284 }; 284 };
285 285
286 &mipi_csi { 286 &mipi_csi {
287 clock-frequency = <240000000>; 287 clock-frequency = <240000000>;
288 status = "okay"; 288 status = "okay";
289 port { 289 port {
290 mipi_sensor_ep: endpoint1 { 290 mipi_sensor_ep: endpoint1 {
291 remote-endpoint = <&ov5640_mipi_ep>; 291 remote-endpoint = <&ov5640_mipi_ep>;
292 data-lanes = <2>; 292 data-lanes = <2>;
293 csis-hs-settle = <13>; 293 csis-hs-settle = <13>;
294 csis-clk-settle = <2>; 294 csis-clk-settle = <2>;
295 csis-wclk; 295 csis-wclk;
296 }; 296 };
297 297
298 csi_mipi_ep: endpoint2 { 298 csi_mipi_ep: endpoint2 {
299 remote-endpoint = <&csi_ep>; 299 remote-endpoint = <&csi_ep>;
300 }; 300 };
301 }; 301 };
302 }; 302 };
303 303
304 &i2c1 { 304 &i2c1 {
305 clock-frequency = <100000>; 305 clock-frequency = <100000>;
306 pinctrl-names = "default", "gpio"; 306 pinctrl-names = "default", "gpio";
307 pinctrl-0 = <&pinctrl_i2c1>; 307 pinctrl-0 = <&pinctrl_i2c1>;
308 pinctrl-1 = <&pinctrl_i2c1_gpio>; 308 pinctrl-1 = <&pinctrl_i2c1_gpio>;
309 scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; 309 scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
310 sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; 310 sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
311 status = "okay"; 311 status = "okay";
312 312
313 pmic: pfuze3000@08 { 313 pmic: pfuze3000@08 {
314 compatible = "fsl,pfuze3000"; 314 compatible = "fsl,pfuze3000";
315 reg = <0x08>; 315 reg = <0x08>;
316 316
317 regulators { 317 regulators {
318 sw1a_reg: sw1a { 318 sw1a_reg: sw1a {
319 regulator-min-microvolt = <700000>; 319 regulator-min-microvolt = <700000>;
320 regulator-max-microvolt = <3300000>; 320 regulator-max-microvolt = <3300000>;
321 regulator-boot-on; 321 regulator-boot-on;
322 regulator-always-on; 322 regulator-always-on;
323 regulator-ramp-delay = <6250>; 323 regulator-ramp-delay = <6250>;
324 }; 324 };
325 325
326 /* use sw1c_reg to align with pfuze100/pfuze200 */ 326 /* use sw1c_reg to align with pfuze100/pfuze200 */
327 sw1c_reg: sw1b { 327 sw1c_reg: sw1b {
328 regulator-min-microvolt = <700000>; 328 regulator-min-microvolt = <700000>;
329 regulator-max-microvolt = <1475000>; 329 regulator-max-microvolt = <1475000>;
330 regulator-boot-on; 330 regulator-boot-on;
331 regulator-always-on; 331 regulator-always-on;
332 regulator-ramp-delay = <6250>; 332 regulator-ramp-delay = <6250>;
333 }; 333 };
334 334
335 sw2_reg: sw2 { 335 sw2_reg: sw2 {
336 regulator-min-microvolt = <1500000>; 336 regulator-min-microvolt = <1500000>;
337 regulator-max-microvolt = <1850000>; 337 regulator-max-microvolt = <1850000>;
338 regulator-boot-on; 338 regulator-boot-on;
339 regulator-always-on; 339 regulator-always-on;
340 }; 340 };
341 341
342 sw3a_reg: sw3 { 342 sw3a_reg: sw3 {
343 regulator-min-microvolt = <900000>; 343 regulator-min-microvolt = <900000>;
344 regulator-max-microvolt = <1650000>; 344 regulator-max-microvolt = <1650000>;
345 regulator-boot-on; 345 regulator-boot-on;
346 regulator-always-on; 346 regulator-always-on;
347 }; 347 };
348 348
349 swbst_reg: swbst { 349 swbst_reg: swbst {
350 regulator-min-microvolt = <5000000>; 350 regulator-min-microvolt = <5000000>;
351 regulator-max-microvolt = <5150000>; 351 regulator-max-microvolt = <5150000>;
352 }; 352 };
353 353
354 snvs_reg: vsnvs { 354 snvs_reg: vsnvs {
355 regulator-min-microvolt = <1000000>; 355 regulator-min-microvolt = <1000000>;
356 regulator-max-microvolt = <3000000>; 356 regulator-max-microvolt = <3000000>;
357 regulator-boot-on; 357 regulator-boot-on;
358 regulator-always-on; 358 regulator-always-on;
359 }; 359 };
360 360
361 vref_reg: vrefddr { 361 vref_reg: vrefddr {
362 regulator-boot-on; 362 regulator-boot-on;
363 regulator-always-on; 363 regulator-always-on;
364 }; 364 };
365 365
366 vgen1_reg: vldo1 { 366 vgen1_reg: vldo1 {
367 regulator-min-microvolt = <1800000>; 367 regulator-min-microvolt = <1800000>;
368 regulator-max-microvolt = <3300000>; 368 regulator-max-microvolt = <3300000>;
369 regulator-always-on; 369 regulator-always-on;
370 }; 370 };
371 371
372 vgen2_reg: vldo2 { 372 vgen2_reg: vldo2 {
373 regulator-min-microvolt = <800000>; 373 regulator-min-microvolt = <800000>;
374 regulator-max-microvolt = <1550000>; 374 regulator-max-microvolt = <1550000>;
375 }; 375 };
376 376
377 vgen3_reg: vccsd { 377 vgen3_reg: vccsd {
378 regulator-min-microvolt = <2850000>; 378 regulator-min-microvolt = <2850000>;
379 regulator-max-microvolt = <3300000>; 379 regulator-max-microvolt = <3300000>;
380 regulator-always-on; 380 regulator-always-on;
381 }; 381 };
382 382
383 vgen4_reg: v33 { 383 vgen4_reg: v33 {
384 regulator-min-microvolt = <2850000>; 384 regulator-min-microvolt = <2850000>;
385 regulator-max-microvolt = <3300000>; 385 regulator-max-microvolt = <3300000>;
386 regulator-always-on; 386 regulator-always-on;
387 }; 387 };
388 388
389 vgen5_reg: vldo3 { 389 vgen5_reg: vldo3 {
390 regulator-min-microvolt = <1800000>; 390 regulator-min-microvolt = <1800000>;
391 regulator-max-microvolt = <3300000>; 391 regulator-max-microvolt = <3300000>;
392 regulator-always-on; 392 regulator-always-on;
393 }; 393 };
394 394
395 vgen6_reg: vldo4 { 395 vgen6_reg: vldo4 {
396 regulator-min-microvolt = <2800000>; 396 regulator-min-microvolt = <2800000>;
397 regulator-max-microvolt = <2800000>; 397 regulator-max-microvolt = <2800000>;
398 regulator-always-on; 398 regulator-always-on;
399 }; 399 };
400 }; 400 };
401 }; 401 };
402 }; 402 };
403 403
404 &i2c2 { 404 &i2c2 {
405 clock-frequency = <100000>; 405 clock-frequency = <100000>;
406 pinctrl-names = "default", "gpio"; 406 pinctrl-names = "default", "gpio";
407 pinctrl-0 = <&pinctrl_i2c2>; 407 pinctrl-0 = <&pinctrl_i2c2>;
408 pinctrl-1 = <&pinctrl_i2c2_gpio>; 408 pinctrl-1 = <&pinctrl_i2c2_gpio>;
409 scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; 409 scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
410 sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; 410 sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
411 status = "okay"; 411 status = "okay";
412 412
413 fxas2100x@20 { 413 fxas2100x@20 {
414 compatible = "fsl,fxas2100x"; 414 compatible = "fsl,fxas2100x";
415 reg = <0x20>; 415 reg = <0x20>;
416 }; 416 };
417 417
418 fxos8700@1e { 418 fxos8700@1e {
419 compatible = "fsl,fxos8700"; 419 compatible = "fsl,fxos8700";
420 reg = <0x1e>; 420 reg = <0x1e>;
421 }; 421 };
422 422
423 mpl3115@60 { 423 mpl3115@60 {
424 compatible = "fsl,mpl3115"; 424 compatible = "fsl,mpl3115";
425 reg = <0x60>; 425 reg = <0x60>;
426 }; 426 };
427 }; 427 };
428 428
429 &i2c3 { 429 &i2c3 {
430 clock-frequency = <100000>; 430 clock-frequency = <100000>;
431 pinctrl-names = "default", "gpio"; 431 pinctrl-names = "default", "gpio";
432 pinctrl-0 = <&pinctrl_i2c3>; 432 pinctrl-0 = <&pinctrl_i2c3>;
433 pinctrl-1 = <&pinctrl_i2c3_gpio>; 433 pinctrl-1 = <&pinctrl_i2c3_gpio>;
434 scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; 434 scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
435 sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; 435 sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
436 status = "okay"; 436 status = "okay";
437 sii902x: sii902x@39 { 437 sii902x: sii902x@39 {
438 compatible = "SiI,sii902x"; 438 compatible = "SiI,sii902x";
439 pinctrl-names = "default"; 439 pinctrl-names = "default";
440 pinctrl-0 = <&pinctrl_sii902x>; 440 pinctrl-0 = <&pinctrl_sii902x>;
441 interrupt-parent = <&gpio2>; 441 interrupt-parent = <&gpio2>;
442 interrupts = <13 IRQ_TYPE_EDGE_FALLING>; 442 interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
443 mode_str ="1280x720M@60"; 443 mode_str ="1280x720M@60";
444 bits-per-pixel = <16>; 444 bits-per-pixel = <16>;
445 reg = <0x39>; 445 reg = <0x39>;
446 status = "okay"; 446 status = "okay";
447 }; 447 };
448 448
449 max17135: max17135@48 { 449 max17135: max17135@48 {
450 pinctrl-names = "default"; 450 pinctrl-names = "default";
451 pinctrl-0 = <&pinctrl_max17135>; 451 pinctrl-0 = <&pinctrl_max17135>;
452 compatible = "maxim,max17135"; 452 compatible = "maxim,max17135";
453 reg = <0x48>; 453 reg = <0x48>;
454 status = "disabled"; 454 status = "disabled";
455 455
456 vneg_pwrup = <1>; 456 vneg_pwrup = <1>;
457 gvee_pwrup = <2>; 457 gvee_pwrup = <2>;
458 vpos_pwrup = <10>; 458 vpos_pwrup = <10>;
459 gvdd_pwrup = <12>; 459 gvdd_pwrup = <12>;
460 gvdd_pwrdn = <1>; 460 gvdd_pwrdn = <1>;
461 vpos_pwrdn = <2>; 461 vpos_pwrdn = <2>;
462 gvee_pwrdn = <8>; 462 gvee_pwrdn = <8>;
463 vneg_pwrdn = <10>; 463 vneg_pwrdn = <10>;
464 gpio_pmic_pwrgood = <&gpio2 31 0>; 464 gpio_pmic_pwrgood = <&gpio2 31 0>;
465 gpio_pmic_vcom_ctrl = <&gpio4 14 0>; 465 gpio_pmic_vcom_ctrl = <&gpio4 14 0>;
466 gpio_pmic_wakeup = <&gpio2 23 0>; 466 gpio_pmic_wakeup = <&gpio2 23 0>;
467 gpio_pmic_v3p3 = <&gpio2 30 0>; 467 gpio_pmic_v3p3 = <&gpio2 30 0>;
468 gpio_pmic_intr = <&gpio2 22 0>; 468 gpio_pmic_intr = <&gpio2 22 0>;
469 469
470 regulators { 470 regulators {
471 DISPLAY_reg: DISPLAY { 471 DISPLAY_reg: DISPLAY {
472 regulator-name = "DISPLAY"; 472 regulator-name = "DISPLAY";
473 }; 473 };
474 474
475 GVDD_reg: GVDD { 475 GVDD_reg: GVDD {
476 /* 20v */ 476 /* 20v */
477 regulator-name = "GVDD"; 477 regulator-name = "GVDD";
478 }; 478 };
479 479
480 GVEE_reg: GVEE { 480 GVEE_reg: GVEE {
481 /* -22v */ 481 /* -22v */
482 regulator-name = "GVEE"; 482 regulator-name = "GVEE";
483 }; 483 };
484 484
485 HVINN_reg: HVINN { 485 HVINN_reg: HVINN {
486 /* -22v */ 486 /* -22v */
487 regulator-name = "HVINN"; 487 regulator-name = "HVINN";
488 }; 488 };
489 489
490 HVINP_reg: HVINP { 490 HVINP_reg: HVINP {
491 /* 20v */ 491 /* 20v */
492 regulator-name = "HVINP"; 492 regulator-name = "HVINP";
493 }; 493 };
494 494
495 VCOM_reg: VCOM { 495 VCOM_reg: VCOM {
496 regulator-name = "VCOM"; 496 regulator-name = "VCOM";
497 /* Real max value: -500000 */ 497 /* Real max value: -500000 */
498 regulator-max-microvolt = <4325000>; 498 regulator-max-microvolt = <4325000>;
499 /* Real min value: -4325000 */ 499 /* Real min value: -4325000 */
500 regulator-min-microvolt = <500000>; 500 regulator-min-microvolt = <500000>;
501 }; 501 };
502 502
503 VNEG_reg: VNEG { 503 VNEG_reg: VNEG {
504 /* -15v */ 504 /* -15v */
505 regulator-name = "VNEG"; 505 regulator-name = "VNEG";
506 }; 506 };
507 507
508 VPOS_reg: VPOS { 508 VPOS_reg: VPOS {
509 /* 15v */ 509 /* 15v */
510 regulator-name = "VPOS"; 510 regulator-name = "VPOS";
511 }; 511 };
512 512
513 V3P3_reg: V3P3 { 513 V3P3_reg: V3P3 {
514 regulator-name = "V3P3"; 514 regulator-name = "V3P3";
515 }; 515 };
516 }; 516 };
517 }; 517 };
518 }; 518 };
519 519
520 &i2c4 { 520 &i2c4 {
521 clock-frequency = <100000>; 521 clock-frequency = <100000>;
522 pinctrl-names = "default", "gpio"; 522 pinctrl-names = "default", "gpio";
523 pinctrl-0 = <&pinctrl_i2c4>; 523 pinctrl-0 = <&pinctrl_i2c4>;
524 pinctrl-1 = <&pinctrl_i2c4_gpio>; 524 pinctrl-1 = <&pinctrl_i2c4_gpio>;
525 scl-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; 525 scl-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
526 sda-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; 526 sda-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>;
527 status = "okay"; 527 status = "okay";
528 528
529 codec: wm8960@1a { 529 codec: wm8960@1a {
530 compatible = "wlf,wm8960"; 530 compatible = "wlf,wm8960";
531 reg = <0x1a>; 531 reg = <0x1a>;
532 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; 532 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
533 clock-names = "mclk"; 533 clock-names = "mclk";
534 wlf,shared-lrclk; 534 wlf,shared-lrclk;
535 }; 535 };
536 536
537 ov5640_mipi: ov5640_mipi@3c { 537 ov5640_mipi: ov5640_mipi@3c {
538 compatible = "ovti,ov5640_mipi"; 538 compatible = "ovti,ov5640_mipi";
539 reg = <0x3c>; 539 reg = <0x3c>;
540 clocks = <&clks IMX7D_CLK_DUMMY>; 540 clocks = <&clks IMX7D_CLK_DUMMY>;
541 clock-names = "csi_mclk"; 541 clock-names = "csi_mclk";
542 csi_id = <0>; 542 csi_id = <0>;
543 pwn-gpios = <&extended_io 6 GPIO_ACTIVE_HIGH>; 543 pwn-gpios = <&extended_io 6 GPIO_ACTIVE_HIGH>;
544 AVDD-supply = <&vgen6_reg>; 544 AVDD-supply = <&vgen6_reg>;
545 mclk = <24000000>; 545 mclk = <24000000>;
546 mclk_source = <0>; 546 mclk_source = <0>;
547 port { 547 port {
548 ov5640_mipi_ep: endpoint { 548 ov5640_mipi_ep: endpoint {
549 remote-endpoint = <&mipi_sensor_ep>; 549 remote-endpoint = <&mipi_sensor_ep>;
550 }; 550 };
551 }; 551 };
552 }; 552 };
553 }; 553 };
554 554
555 &lcdif { 555 &lcdif {
556 pinctrl-names = "default"; 556 pinctrl-names = "default";
557 pinctrl-0 = <&pinctrl_lcdif>; 557 pinctrl-0 = <&pinctrl_lcdif>;
558 enable-gpio = <&extended_io 7 GPIO_ACTIVE_LOW>; 558 enable-gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
559 display = <&display0>; 559 display = <&display0>;
560 status = "okay"; 560 status = "okay";
561 561
562 display0: display { 562 display0: display {
563 bits-per-pixel = <16>; 563 bits-per-pixel = <16>;
564 bus-width = <24>; 564 bus-width = <24>;
565 565
566 display-timings { 566 display-timings {
567 native-mode = <&timing0>; 567 native-mode = <&timing0>;
568 568
569 timing0: timing0 { 569 timing0: timing0 {
570 clock-frequency = <9200000>; 570 clock-frequency = <9200000>;
571 hactive = <480>; 571 hactive = <480>;
572 vactive = <272>; 572 vactive = <272>;
573 hfront-porch = <8>; 573 hfront-porch = <8>;
574 hback-porch = <4>; 574 hback-porch = <4>;
575 hsync-len = <41>; 575 hsync-len = <41>;
576 vback-porch = <2>; 576 vback-porch = <2>;
577 vfront-porch = <4>; 577 vfront-porch = <4>;
578 vsync-len = <10>; 578 vsync-len = <10>;
579 hsync-active = <0>; 579 hsync-active = <0>;
580 vsync-active = <0>; 580 vsync-active = <0>;
581 de-active = <1>; 581 de-active = <1>;
582 pixelclk-active = <0>; 582 pixelclk-active = <0>;
583 }; 583 };
584 }; 584 };
585 }; 585 };
586 }; 586 };
587 587
588 &sai1 { 588 &sai1 {
589 pinctrl-names = "default"; 589 pinctrl-names = "default";
590 pinctrl-0 = <&pinctrl_sai1>; 590 pinctrl-0 = <&pinctrl_sai1>;
591 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, 591 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
592 <&clks IMX7D_SAI1_ROOT_CLK>; 592 <&clks IMX7D_SAI1_ROOT_CLK>;
593 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 593 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
594 assigned-clock-rates = <0>, <36864000>; 594 assigned-clock-rates = <0>, <36864000>;
595 status = "okay"; 595 status = "okay";
596 }; 596 };
597 597
598 &sai3 { 598 &sai3 {
599 pinctrl-names = "default"; 599 pinctrl-names = "default";
600 pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>; 600 pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>;
601 assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, 601 assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
602 <&clks IMX7D_SAI3_ROOT_CLK>; 602 <&clks IMX7D_SAI3_ROOT_CLK>;
603 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 603 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
604 assigned-clock-rates = <0>, <36864000>; 604 assigned-clock-rates = <0>, <36864000>;
605 status = "okay"; 605 status = "okay";
606 }; 606 };
607 607
608 &sdma { 608 &sdma {
609 status = "okay"; 609 status = "okay";
610 }; 610 };
611 611
612 &pwm1 { 612 &pwm1 {
613 pinctrl-names = "default"; 613 pinctrl-names = "default";
614 pinctrl-0 = <&pinctrl_pwm1>; 614 pinctrl-0 = <&pinctrl_pwm1>;
615 status = "okay"; 615 status = "okay";
616 }; 616 };
617 617
618 &pcie { 618 &pcie {
619 pinctrl-names = "default"; 619 pinctrl-names = "default";
620 reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; 620 reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
621 disable-gpio = <&extended_io 0 GPIO_ACTIVE_LOW>; 621 disable-gpio = <&extended_io 0 GPIO_ACTIVE_LOW>;
622 status = "okay"; 622 status = "okay";
623 }; 623 };
624 624
625 &iomuxc_lpsr { 625 &iomuxc_lpsr {
626 pinctrl-names = "default"; 626 pinctrl-names = "default";
627 pinctrl-0 = <&pinctrl_hog_2 &pinctrl_usbotg2_pwr_2>; 627 pinctrl-0 = <&pinctrl_hog_2 &pinctrl_usbotg2_pwr_2>;
628 628
629 imx7d-sdb { 629 imx7d-sdb {
630 pinctrl_hog_2: hoggrp-2 { 630 pinctrl_hog_2: hoggrp-2 {
631 fsl,pins = < 631 fsl,pins = <
632 MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 632 MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14
633 >; 633 >;
634 }; 634 };
635 635
636 pinctrl_pwm1: pwm1grp { 636 pinctrl_pwm1: pwm1grp {
637 fsl,pins = < 637 fsl,pins = <
638 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 638 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30
639 >; 639 >;
640 }; 640 };
641 641
642 pinctrl_usbotg2_pwr_2: usbotg2-2 { 642 pinctrl_usbotg2_pwr_2: usbotg2-2 {
643 fsl,pins = < 643 fsl,pins = <
644 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 644 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
645 >; 645 >;
646 }; 646 };
647 647
648 pinctrl_enet2_epdc0_en: enet2_epdc0_grp { 648 pinctrl_enet2_epdc0_en: enet2_epdc0_grp {
649 fsl,pins = < 649 fsl,pins = <
650 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x80000000 650 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x80000000
651 >; 651 >;
652 }; 652 };
653 653
654 pinctrl_sai3_mclk: sai3grp_mclk { 654 pinctrl_sai3_mclk: sai3grp_mclk {
655 fsl,pins = < 655 fsl,pins = <
656 MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f 656 MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f
657 >; 657 >;
658 }; 658 };
659 }; 659 };
660 }; 660 };
661 661
662 &sim1 { 662 &sim1 {
663 pinctrl-names = "default"; 663 pinctrl-names = "default";
664 pinctrl-0 = <&pinctrl_sim1_1>; 664 pinctrl-0 = <&pinctrl_sim1_1>;
665 port = <0>; 665 port = <0>;
666 sven_low_active; 666 sven_low_active;
667 status = "okay"; 667 status = "okay";
668 }; 668 };
669 669
670 670
671 &uart1 { 671 &uart1 {
672 pinctrl-names = "default"; 672 pinctrl-names = "default";
673 pinctrl-0 = <&pinctrl_uart1>; 673 pinctrl-0 = <&pinctrl_uart1>;
674 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; 674 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
675 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 675 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
676 status = "okay"; 676 status = "okay";
677 }; 677 };
678 678
679 &uart5 { 679 &uart5 {
680 pinctrl-names = "default"; 680 pinctrl-names = "default";
681 pinctrl-0 = <&pinctrl_uart5>; 681 pinctrl-0 = <&pinctrl_uart5>;
682 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; 682 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
683 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 683 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
684 /* for DTE mode, add below change */ 684 /* for DTE mode, add below change */
685 /* fsl,dte-mode; */ 685 /* fsl,dte-mode; */
686 /* pinctrl-0 = <&pinctrl_uart5dte>; */ 686 /* pinctrl-0 = <&pinctrl_uart5dte>; */
687 status = "okay"; 687 status = "okay";
688 }; 688 };
689 689
690 &uart6 { 690 &uart6 {
691 pinctrl-names = "default"; 691 pinctrl-names = "default";
692 pinctrl-0 = <&pinctrl_uart6>; 692 pinctrl-0 = <&pinctrl_uart6>;
693 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; 693 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
694 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 694 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
695 uart-has-rtscts; 695 uart-has-rtscts;
696 resets = <&modem_reset>; 696 resets = <&modem_reset>;
697 status = "okay"; 697 status = "okay";
698 }; 698 };
699 699
700 &usbotg1 { 700 &usbotg1 {
701 vbus-supply = <&reg_usb_otg1_vbus>; 701 vbus-supply = <&reg_usb_otg1_vbus>;
702 srp-disable; 702 srp-disable;
703 hnp-disable; 703 hnp-disable;
704 adp-disable; 704 adp-disable;
705 status = "okay"; 705 status = "okay";
706 }; 706 };
707 707
708 &usbotg2 { 708 &usbotg2 {
709 vbus-supply = <&reg_usb_otg2_vbus>; 709 vbus-supply = <&reg_usb_otg2_vbus>;
710 dr_mode = "host"; 710 dr_mode = "host";
711 status = "okay"; 711 status = "okay";
712 }; 712 };
713 713
714 &usdhc1 { 714 &usdhc1 {
715 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 715 pinctrl-names = "default", "state_100mhz", "state_200mhz";
716 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; 716 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
717 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; 717 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
718 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; 718 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
719 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 719 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
720 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 720 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
721 wakeup-source; 721 wakeup-source;
722 vmmc-supply = <&reg_sd1_vmmc>; 722 vmmc-supply = <&reg_sd1_vmmc>;
723 enable-sdio-wakeup; 723 enable-sdio-wakeup;
724 keep-power-in-suspend; 724 keep-power-in-suspend;
725 status = "okay"; 725 status = "okay";
726 }; 726 };
727 727
728 &usdhc2 { 728 &usdhc2 {
729 #address-cells = <1>; 729 #address-cells = <1>;
730 #size-cells = <0>; 730 #size-cells = <0>;
731 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 731 pinctrl-names = "default", "state_100mhz", "state_200mhz";
732 pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi>; 732 pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi>;
733 pinctrl-1 = <&pinctrl_usdhc2_100mhz &pinctrl_wifi>; 733 pinctrl-1 = <&pinctrl_usdhc2_100mhz &pinctrl_wifi>;
734 pinctrl-2 = <&pinctrl_usdhc2_200mhz &pinctrl_wifi>; 734 pinctrl-2 = <&pinctrl_usdhc2_200mhz &pinctrl_wifi>;
735 wakeup-source; 735 wakeup-source;
736 keep-power-in-suspend; 736 keep-power-in-suspend;
737 non-removable; 737 non-removable;
738 mmc-pwrseq = <&usdhc2_pwrseq>; 738 mmc-pwrseq = <&usdhc2_pwrseq>;
739 fsl,tuning-step = <2>; 739 fsl,tuning-step = <2>;
740 pm-ignore-notify; 740 pm-ignore-notify;
741 cap-power-off-card; 741 cap-power-off-card;
742 status = "disabled"; 742 status = "disabled";
743 743
744 brcmf: bcrmf@1 { 744 brcmf: bcrmf@1 {
745 reg = <1>; 745 reg = <1>;
746 compatible = "brcm,bcm4329-fmac"; 746 compatible = "brcm,bcm4329-fmac";
747 }; 747 };
748 }; 748 };
749 749
750 &usdhc3 { 750 &usdhc3 {
751 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 751 pinctrl-names = "default", "state_100mhz", "state_200mhz";
752 pinctrl-0 = <&pinctrl_usdhc3>; 752 pinctrl-0 = <&pinctrl_usdhc3>;
753 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 753 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
754 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 754 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
755 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; 755 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
756 assigned-clock-rates = <400000000>; 756 assigned-clock-rates = <400000000>;
757 bus-width = <8>; 757 bus-width = <8>;
758 non-removable; 758 non-removable;
759 status = "okay"; 759 status = "okay";
760 }; 760 };
761 761
762 &wdog1 { 762 &wdog1 {
763 pinctrl-names = "default"; 763 pinctrl-names = "default";
764 pinctrl-0 = <&pinctrl_wdog>; 764 pinctrl-0 = <&pinctrl_wdog>;
765 fsl,ext-reset-output; 765 fsl,ext-reset-output;
766 }; 766 };
767 767
768 &gpmi { 768 &gpmi {
769 pinctrl-names = "default"; 769 pinctrl-names = "default";
770 pinctrl-0 = <&pinctrl_gpmi_nand_1>; 770 pinctrl-0 = <&pinctrl_gpmi_nand_1>;
771 status = "disabled"; 771 status = "disabled";
772 nand-on-flash-bbt; 772 nand-on-flash-bbt;
773 }; 773 };
774 774
775 &iomuxc { 775 &iomuxc {
776 pinctrl-names = "default"; 776 pinctrl-names = "default";
777 pinctrl-0 = <&pinctrl_hog_1>; 777 pinctrl-0 = <&pinctrl_hog_1>;
778 778
779 imx7d-sdb { 779 imx7d-sdb {
780 pinctrl_brcm_reg: brcmreggrp { 780 pinctrl_brcm_reg: brcmreggrp {
781 fsl,pins = < 781 fsl,pins = <
782 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 782 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14
783 >; 783 >;
784 }; 784 };
785 785
786 pinctrl_epdc_elan_touch: epdc_elan_touch_grp { 786 pinctrl_epdc_elan_touch: epdc_elan_touch_grp {
787 fsl,pins = < 787 fsl,pins = <
788 MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x59 788 MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x59
789 MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b 789 MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b
790 MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x80000000 790 MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x80000000
791 >; 791 >;
792 }; 792 };
793 793
794 pinctrl_hog_1: hoggrp-1 { 794 pinctrl_hog_1: hoggrp-1 {
795 fsl,pins = < 795 fsl,pins = <
796 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */ 796 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */
797 >; 797 >;
798 }; 798 };
799 799
800 pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp { 800 pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp {
801 fsl,pins = < 801 fsl,pins = <
802 MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b 802 MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b
803 >; 803 >;
804 }; 804 };
805 805
806 pinctrl_ecspi3: ecspi3grp { 806 pinctrl_ecspi3: ecspi3grp {
807 fsl,pins = < 807 fsl,pins = <
808 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 808 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2
809 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 809 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2
810 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 810 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2
811 >; 811 >;
812 }; 812 };
813 813
814 pinctrl_ecspi3_cs: ecspi3_cs_grp { 814 pinctrl_ecspi3_cs: ecspi3_cs_grp {
815 fsl,pins = < 815 fsl,pins = <
816 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x80000000 816 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x80000000
817 >; 817 >;
818 }; 818 };
819 819
820 pinctrl_enet1: enet1grp { 820 pinctrl_enet1: enet1grp {
821 fsl,pins = < 821 fsl,pins = <
822 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 822 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
823 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 823 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
824 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 824 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
825 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 825 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
826 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 826 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
827 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 827 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
828 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 828 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
829 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 829 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
830 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 830 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
831 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 831 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
832 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 832 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
833 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 833 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
834 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 834 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
835 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 835 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
836 >; 836 >;
837 }; 837 };
838 838
839 pinctrl_enet2: enet2grp { 839 pinctrl_enet2: enet2grp {
840 fsl,pins = < 840 fsl,pins = <
841 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 841 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
842 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 842 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
843 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 843 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
844 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 844 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
845 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 845 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
846 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 846 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
847 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 847 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
848 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 848 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
849 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 849 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
850 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 850 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
851 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 851 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
852 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 852 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
853 >; 853 >;
854 }; 854 };
855 855
856 pinctrl_flexcan2: flexcan2grp { 856 pinctrl_flexcan2: flexcan2grp {
857 fsl,pins = < 857 fsl,pins = <
858 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 858 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
859 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 859 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
860 >; 860 >;
861 }; 861 };
862 862
863 pinctrl_flexcan2_reg: flexcan2reggrp { 863 pinctrl_flexcan2_reg: flexcan2reggrp {
864 fsl,pins = < 864 fsl,pins = <
865 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ 865 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */
866 >; 866 >;
867 }; 867 };
868 868
869 pinctrl_epdc0: epdcgrp0 { 869 pinctrl_epdc0: epdcgrp0 {
870 fsl,pins = < 870 fsl,pins = <
871 MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2 871 MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2
872 MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2 872 MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2
873 MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2 873 MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2
874 MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2 874 MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2
875 MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2 875 MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2
876 MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2 876 MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2
877 MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2 877 MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2
878 MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2 878 MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2
879 MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2 879 MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2
880 MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2 880 MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2
881 MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2 881 MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2
882 MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2 882 MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2
883 MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2 883 MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2
884 MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2 884 MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2
885 MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2 885 MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2
886 MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2 886 MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2
887 MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2 887 MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2
888 MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2 888 MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2
889 MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2 889 MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2
890 MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2 890 MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2
891 MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2 891 MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2
892 MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2 892 MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2
893 MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2 893 MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2
894 MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2 894 MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2
895 MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2 895 MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2
896 MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2 896 MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2
897 >; 897 >;
898 }; 898 };
899 899
900 pinctrl_gpmi_nand_1: gpmi-nand-1 { 900 pinctrl_gpmi_nand_1: gpmi-nand-1 {
901 fsl,pins = < 901 fsl,pins = <
902 MX7D_PAD_SD3_CLK__NAND_CLE 0x71 902 MX7D_PAD_SD3_CLK__NAND_CLE 0x71
903 MX7D_PAD_SD3_CMD__NAND_ALE 0x71 903 MX7D_PAD_SD3_CMD__NAND_ALE 0x71
904 MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71 904 MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71
905 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 905 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
906 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 906 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71
907 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 907 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
908 MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 908 MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
909 MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 909 MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
910 MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 910 MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71
911 MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 911 MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71
912 MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 912 MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71
913 MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 913 MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71
914 MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 914 MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71
915 MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 915 MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71
916 MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 916 MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71
917 MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 917 MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
918 918
919 >; 919 >;
920 }; 920 };
921 921
922 pinctrl_i2c1: i2c1grp { 922 pinctrl_i2c1: i2c1grp {
923 fsl,pins = < 923 fsl,pins = <
924 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f 924 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
925 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f 925 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
926 >; 926 >;
927 }; 927 };
928 928
929 pinctrl_i2c1_gpio: i2c1grp_gpio { 929 pinctrl_i2c1_gpio: i2c1grp_gpio {
930 fsl,pins = < 930 fsl,pins = <
931 MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x7f 931 MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x7f
932 MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x7f 932 MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x7f
933 >; 933 >;
934 }; 934 };
935 935
936 pinctrl_i2c2: i2c2grp { 936 pinctrl_i2c2: i2c2grp {
937 fsl,pins = < 937 fsl,pins = <
938 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f 938 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
939 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f 939 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
940 >; 940 >;
941 }; 941 };
942 942
943 pinctrl_i2c2_gpio: i2c2grp_gpio { 943 pinctrl_i2c2_gpio: i2c2grp_gpio {
944 fsl,pins = < 944 fsl,pins = <
945 MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x7f 945 MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x7f
946 MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x7f 946 MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x7f
947 >; 947 >;
948 }; 948 };
949 949
950 pinctrl_i2c3: i2c3grp { 950 pinctrl_i2c3: i2c3grp {
951 fsl,pins = < 951 fsl,pins = <
952 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f 952 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
953 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f 953 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
954 >; 954 >;
955 }; 955 };
956 956
957 pinctrl_i2c3_gpio: i2c3grp_gpio { 957 pinctrl_i2c3_gpio: i2c3grp_gpio {
958 fsl,pins = < 958 fsl,pins = <
959 MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x7f 959 MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x7f
960 MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x7f 960 MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x7f
961 >; 961 >;
962 }; 962 };
963 963
964 pinctrl_i2c4: i2c4grp { 964 pinctrl_i2c4: i2c4grp {
965 fsl,pins = < 965 fsl,pins = <
966 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f 966 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
967 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f 967 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
968 >; 968 >;
969 }; 969 };
970 970
971 pinctrl_i2c4_gpio: i2c4grp_gpio { 971 pinctrl_i2c4_gpio: i2c4grp_gpio {
972 fsl,pins = < 972 fsl,pins = <
973 MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x7f 973 MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x7f
974 MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x7f 974 MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x7f
975 >; 975 >;
976 }; 976 };
977 977
978 pinctrl_lcdif: lcdifgrp { 978 pinctrl_lcdif: lcdifgrp {
979 fsl,pins = < 979 fsl,pins = <
980 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 980 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
981 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 981 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
982 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 982 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
983 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 983 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
984 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 984 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
985 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 985 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
986 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 986 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
987 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 987 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
988 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 988 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
989 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 989 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
990 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 990 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
991 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 991 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
992 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 992 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
993 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 993 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
994 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 994 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
995 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 995 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
996 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 996 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
997 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 997 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
998 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 998 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
999 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 999 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
1000 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 1000 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
1001 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 1001 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
1002 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 1002 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
1003 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 1003 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
1004 MX7D_PAD_LCD_CLK__LCD_CLK 0x79 1004 MX7D_PAD_LCD_CLK__LCD_CLK 0x79
1005 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 1005 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
1006 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 1006 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
1007 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 1007 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
1008 MX7D_PAD_LCD_RESET__LCD_RESET 0x79 1008 MX7D_PAD_LCD_RESET__LCD_RESET 0x79
1009 >; 1009 >;
1010 }; 1010 };
1011 1011
1012 pinctrl_max17135: max17135grp-1 { 1012 pinctrl_max17135: max17135grp-1 {
1013 fsl,pins = < 1013 fsl,pins = <
1014 MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 /* pwrgood */ 1014 MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 /* pwrgood */
1015 MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 /* vcom_ctrl */ 1015 MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 /* vcom_ctrl */
1016 MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x80000000 /* wakeup */ 1016 MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x80000000 /* wakeup */
1017 MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x80000000 /* v3p3 */ 1017 MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x80000000 /* v3p3 */
1018 MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x80000000 /* pwr int */ 1018 MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x80000000 /* pwr int */
1019 >; 1019 >;
1020 }; 1020 };
1021 1021
1022 pinctrl_sai1: sai1grp { 1022 pinctrl_sai1: sai1grp {
1023 fsl,pins = < 1023 fsl,pins = <
1024 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f 1024 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
1025 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f 1025 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
1026 MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f 1026 MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
1027 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 1027 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
1028 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f 1028 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
1029 >; 1029 >;
1030 }; 1030 };
1031 1031
1032 pinctrl_sai2: sai2grp { 1032 pinctrl_sai2: sai2grp {
1033 fsl,pins = < 1033 fsl,pins = <
1034 MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f 1034 MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f
1035 MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f 1035 MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f
1036 MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 1036 MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30
1037 MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f 1037 MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f
1038 >; 1038 >;
1039 }; 1039 };
1040 1040
1041 pinctrl_sai3: sai3grp { 1041 pinctrl_sai3: sai3grp {
1042 fsl,pins = < 1042 fsl,pins = <
1043 MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f 1043 MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f
1044 MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f 1044 MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f
1045 MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 1045 MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30
1046 >; 1046 >;
1047 }; 1047 };
1048 1048
1049 pinctrl_spi4: spi4grp { 1049 pinctrl_spi4: spi4grp {
1050 fsl,pins = < 1050 fsl,pins = <
1051 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 1051 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
1052 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 1052 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
1053 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 1053 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
1054 >; 1054 >;
1055 }; 1055 };
1056 1056
1057 pinctrl_tsc2046_pendown: tsc2046_pendown { 1057 pinctrl_tsc2046_pendown: tsc2046_pendown {
1058 fsl,pins = < 1058 fsl,pins = <
1059 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 1059 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59
1060 >; 1060 >;
1061 }; 1061 };
1062 1062
1063 1063
1064 pinctrl_sii902x: hdmigrp-1 { 1064 pinctrl_sii902x: hdmigrp-1 {
1065 fsl,pins = < 1065 fsl,pins = <
1066 MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59 1066 MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59
1067 >; 1067 >;
1068 }; 1068 };
1069 1069
1070 pinctrl_sim1_1: sim1grp-1 { 1070 pinctrl_sim1_1: sim1grp-1 {
1071 fsl,pins = < 1071 fsl,pins = <
1072 MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x77 1072 MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x77
1073 MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x77 1073 MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x77
1074 MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x77 1074 MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x77
1075 MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x73 1075 MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x73
1076 MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x73 1076 MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x73
1077 >; 1077 >;
1078 }; 1078 };
1079 1079
1080 pinctrl_uart1: uart1grp { 1080 pinctrl_uart1: uart1grp {
1081 fsl,pins = < 1081 fsl,pins = <
1082 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 1082 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
1083 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 1083 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
1084 >; 1084 >;
1085 }; 1085 };
1086 1086
1087 pinctrl_uart5: uart5grp { 1087 pinctrl_uart5: uart5grp {
1088 fsl,pins = < 1088 fsl,pins = <
1089 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 1089 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79
1090 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 1090 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79
1091 >; 1091 >;
1092 }; 1092 };
1093 1093
1094 pinctrl_uart5dte: uart5dtegrp { 1094 pinctrl_uart5dte: uart5dtegrp {
1095 fsl,pins = < 1095 fsl,pins = <
1096 MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79 1096 MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79
1097 MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79 1097 MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79
1098 >; 1098 >;
1099 }; 1099 };
1100 1100
1101 pinctrl_uart6: uart6grp { 1101 pinctrl_uart6: uart6grp {
1102 fsl,pins = < 1102 fsl,pins = <
1103 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 1103 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
1104 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 1104 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
1105 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 1105 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
1106 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 1106 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
1107 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x19 /* BT_REG_ON */ 1107 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x19 /* BT_REG_ON */
1108 >; 1108 >;
1109 }; 1109 };
1110 1110
1111 pinctrl_usdhc1_gpio: usdhc1_gpiogrp { 1111 pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
1112 fsl,pins = < 1112 fsl,pins = <
1113 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ 1113 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
1114 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ 1114 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
1115 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ 1115 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
1116 MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ 1116 MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
1117 >; 1117 >;
1118 }; 1118 };
1119 1119
1120 pinctrl_usbotg2_pwr_1: usbotg2-1 { 1120 pinctrl_usbotg2_pwr_1: usbotg2-1 {
1121 fsl,pins = < 1121 fsl,pins = <
1122 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 1122 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
1123 >; 1123 >;
1124 }; 1124 };
1125 1125
1126 pinctrl_usdhc1: usdhc1grp { 1126 pinctrl_usdhc1: usdhc1grp {
1127 fsl,pins = < 1127 fsl,pins = <
1128 MX7D_PAD_SD1_CMD__SD1_CMD 0x59 1128 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
1129 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 1129 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
1130 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 1130 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
1131 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 1131 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
1132 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 1132 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
1133 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 1133 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
1134 >; 1134 >;
1135 }; 1135 };
1136 1136
1137 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { 1137 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
1138 fsl,pins = < 1138 fsl,pins = <
1139 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a 1139 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
1140 MX7D_PAD_SD1_CLK__SD1_CLK 0x1a 1140 MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
1141 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a 1141 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
1142 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a 1142 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
1143 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a 1143 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
1144 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a 1144 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
1145 >; 1145 >;
1146 }; 1146 };
1147 1147
1148 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { 1148 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
1149 fsl,pins = < 1149 fsl,pins = <
1150 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b 1150 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
1151 MX7D_PAD_SD1_CLK__SD1_CLK 0x1b 1151 MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
1152 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b 1152 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
1153 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b 1153 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
1154 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b 1154 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
1155 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b 1155 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
1156 >; 1156 >;
1157 }; 1157 };
1158 1158
1159 pinctrl_usdhc2: usdhc2grp { 1159 pinctrl_usdhc2: usdhc2grp {
1160 fsl,pins = < 1160 fsl,pins = <
1161 MX7D_PAD_SD2_CMD__SD2_CMD 0x59 1161 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
1162 MX7D_PAD_SD2_CLK__SD2_CLK 0x19 1162 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
1163 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 1163 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
1164 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 1164 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
1165 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 1165 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
1166 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 1166 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
1167 >; 1167 >;
1168 }; 1168 };
1169 1169
1170 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { 1170 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
1171 fsl,pins = < 1171 fsl,pins = <
1172 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a 1172 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
1173 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a 1173 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
1174 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a 1174 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
1175 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a 1175 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
1176 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a 1176 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
1177 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a 1177 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
1178 >; 1178 >;
1179 }; 1179 };
1180 1180
1181 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { 1181 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
1182 fsl,pins = < 1182 fsl,pins = <
1183 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b 1183 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
1184 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b 1184 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
1185 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b 1185 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
1186 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b 1186 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
1187 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b 1187 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
1188 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b 1188 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
1189 >; 1189 >;
1190 }; 1190 };
1191 1191
1192 pinctrl_usdhc3: usdhc3grp { 1192 pinctrl_usdhc3: usdhc3grp {
1193 fsl,pins = < 1193 fsl,pins = <
1194 MX7D_PAD_SD3_CMD__SD3_CMD 0x59 1194 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
1195 MX7D_PAD_SD3_CLK__SD3_CLK 0x19 1195 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
1196 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 1196 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
1197 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 1197 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
1198 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 1198 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
1199 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 1199 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
1200 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 1200 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
1201 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 1201 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
1202 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 1202 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
1203 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 1203 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
1204 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 1204 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
1205 >; 1205 >;
1206 }; 1206 };
1207 1207
1208 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { 1208 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
1209 fsl,pins = < 1209 fsl,pins = <
1210 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a 1210 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
1211 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a 1211 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
1212 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a 1212 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
1213 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a 1213 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
1214 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a 1214 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
1215 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a 1215 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
1216 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a 1216 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
1217 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a 1217 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
1218 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a 1218 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
1219 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a 1219 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
1220 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a 1220 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
1221 >; 1221 >;
1222 }; 1222 };
1223 1223
1224 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { 1224 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
1225 fsl,pins = < 1225 fsl,pins = <
1226 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b 1226 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
1227 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b 1227 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
1228 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b 1228 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
1229 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b 1229 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
1230 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b 1230 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
1231 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b 1231 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
1232 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b 1232 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
1233 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b 1233 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
1234 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b 1234 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
1235 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b 1235 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
1236 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b 1236 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
1237 >; 1237 >;
1238 }; 1238 };
1239 1239
1240 pinctrl_wifi: wifigrp { 1240 pinctrl_wifi: wifigrp {
1241 fsl,pins = < 1241 fsl,pins = <
1242 MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */ 1242 MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */
1243 >; 1243 >;
1244 }; 1244 };
1245 }; 1245 };
1246 }; 1246 };
1247 1247
1248 &iomuxc_lpsr { 1248 &iomuxc_lpsr {
1249 pinctrl_wdog: wdoggrp { 1249 pinctrl_wdog: wdoggrp {
1250 fsl,pins = < 1250 fsl,pins = <
1251 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 1251 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
1252 >; 1252 >;
1253 }; 1253 };
1254 1254
1255 pinctrl_backlight: backlightgrp { 1255 pinctrl_backlight: backlightgrp {
1256 fsl,pins = < 1256 fsl,pins = <
1257 MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x110b0 1257 MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x110b0
1258 >; 1258 >;
1259 }; 1259 };
1260 }; 1260 };
1261 1261