Eric Lee / smarc-uboot

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Commit 4efe52bf23c96cee7052273bd8549caee4d0fdc2

Authored by Thierry Reding
Committed by Tom Rini
1 parent 042b83d4c5
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

pci: Honour pci_skip_dev() 

When enumerating devices, honour the pci_skip_dev() function. This can
be used by PCI controller drivers to restrict which devices will be
probed.

This is required by the NVIDIA Tegra PCIe controller driver, which will
fail with a data abort exception if an access is attempted to a device
number larger than 0 outside of bus 0. pci_skip_dev() is therefore
implemented to prevent any such accesses.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 3 changed files with 7 additions and 0 deletions Inline Diff

1 /* 1 /*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de> 3 * Andreas Heppel <aheppel@sysgo.de>
4 * 4 *
5 * (C) Copyright 2002 5 * (C) Copyright 2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. 7 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
8 * 8 *
9 * SPDX-License-Identifier: GPL-2.0+ 9 * SPDX-License-Identifier: GPL-2.0+
10 */ 10 */
11 11
12 /* 12 /*
13 * PCI routines 13 * PCI routines
14 */ 14 */
15 15
16 #include <common.h> 16 #include <common.h>
17 #include <bootretry.h> 17 #include <bootretry.h>
18 #include <cli.h> 18 #include <cli.h>
19 #include <command.h> 19 #include <command.h>
20 #include <asm/processor.h> 20 #include <asm/processor.h>
21 #include <asm/io.h> 21 #include <asm/io.h>
22 #include <pci.h> 22 #include <pci.h>
23 23
24 /* 24 /*
25 * Follows routines for the output of infos about devices on PCI bus. 25 * Follows routines for the output of infos about devices on PCI bus.
26 */ 26 */
27 27
28 void pci_header_show(pci_dev_t dev); 28 void pci_header_show(pci_dev_t dev);
29 void pci_header_show_brief(pci_dev_t dev); 29 void pci_header_show_brief(pci_dev_t dev);
30 30
31 /* 31 /*
32 * Subroutine: pciinfo 32 * Subroutine: pciinfo
33 * 33 *
34 * Description: Show information about devices on PCI bus. 34 * Description: Show information about devices on PCI bus.
35 * Depending on the define CONFIG_SYS_SHORT_PCI_LISTING 35 * Depending on the define CONFIG_SYS_SHORT_PCI_LISTING
36 * the output will be more or less exhaustive. 36 * the output will be more or less exhaustive.
37 * 37 *
38 * Inputs: bus_no the number of the bus to be scanned. 38 * Inputs: bus_no the number of the bus to be scanned.
39 * 39 *
40 * Return: None 40 * Return: None
41 * 41 *
42 */ 42 */
43 void pciinfo(int BusNum, int ShortPCIListing) 43 void pciinfo(int BusNum, int ShortPCIListing)
44 { 44 {
45 struct pci_controller *hose = pci_bus_to_hose(BusNum); 45 struct pci_controller *hose = pci_bus_to_hose(BusNum);
46 int Device; 46 int Device;
47 int Function; 47 int Function;
48 unsigned char HeaderType; 48 unsigned char HeaderType;
49 unsigned short VendorID; 49 unsigned short VendorID;
50 pci_dev_t dev; 50 pci_dev_t dev;
51 51
52 if (!hose) 52 if (!hose)
53 return; 53 return;
54 54
55 printf("Scanning PCI devices on bus %d\n", BusNum); 55 printf("Scanning PCI devices on bus %d\n", BusNum);
56 56
57 if (ShortPCIListing) { 57 if (ShortPCIListing) {
58 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n"); 58 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
59 printf("_____________________________________________________________\n"); 59 printf("_____________________________________________________________\n");
60 } 60 }
61 61
62 for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) { 62 for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
63 HeaderType = 0; 63 HeaderType = 0;
64 VendorID = 0; 64 VendorID = 0;
65 for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) { 65 for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
66 /* 66 /*
67 * If this is not a multi-function device, we skip the rest. 67 * If this is not a multi-function device, we skip the rest.
68 */ 68 */
69 if (Function && !(HeaderType & 0x80)) 69 if (Function && !(HeaderType & 0x80))
70 break; 70 break;
71 71
72 dev = PCI_BDF(BusNum, Device, Function); 72 dev = PCI_BDF(BusNum, Device, Function);
73 73
74 if (pci_skip_dev(hose, dev))
75 continue;
76
74 pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID); 77 pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
75 if ((VendorID == 0xFFFF) || (VendorID == 0x0000)) 78 if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
76 continue; 79 continue;
77 80
78 if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType); 81 if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
79 82
80 if (ShortPCIListing) 83 if (ShortPCIListing)
81 { 84 {
82 printf("%02x.%02x.%02x ", BusNum, Device, Function); 85 printf("%02x.%02x.%02x ", BusNum, Device, Function);
83 pci_header_show_brief(dev); 86 pci_header_show_brief(dev);
84 } 87 }
85 else 88 else
86 { 89 {
87 printf("\nFound PCI device %02x.%02x.%02x:\n", 90 printf("\nFound PCI device %02x.%02x.%02x:\n",
88 BusNum, Device, Function); 91 BusNum, Device, Function);
89 pci_header_show(dev); 92 pci_header_show(dev);
90 } 93 }
91 } 94 }
92 } 95 }
93 } 96 }
94 97
95 98
96 /* 99 /*
97 * Subroutine: pci_header_show_brief 100 * Subroutine: pci_header_show_brief
98 * 101 *
99 * Description: Reads and prints the header of the 102 * Description: Reads and prints the header of the
100 * specified PCI device in short form. 103 * specified PCI device in short form.
101 * 104 *
102 * Inputs: dev Bus+Device+Function number 105 * Inputs: dev Bus+Device+Function number
103 * 106 *
104 * Return: None 107 * Return: None
105 * 108 *
106 */ 109 */
107 void pci_header_show_brief(pci_dev_t dev) 110 void pci_header_show_brief(pci_dev_t dev)
108 { 111 {
109 u16 vendor, device; 112 u16 vendor, device;
110 u8 class, subclass; 113 u8 class, subclass;
111 114
112 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); 115 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
113 pci_read_config_word(dev, PCI_DEVICE_ID, &device); 116 pci_read_config_word(dev, PCI_DEVICE_ID, &device);
114 pci_read_config_byte(dev, PCI_CLASS_CODE, &class); 117 pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
115 pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass); 118 pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
116 119
117 printf("0x%.4x 0x%.4x %-23s 0x%.2x\n", 120 printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
118 vendor, device, 121 vendor, device,
119 pci_class_str(class), subclass); 122 pci_class_str(class), subclass);
120 } 123 }
121 124
122 /* 125 /*
123 * Subroutine: PCI_Header_Show 126 * Subroutine: PCI_Header_Show
124 * 127 *
125 * Description: Reads the header of the specified PCI device. 128 * Description: Reads the header of the specified PCI device.
126 * 129 *
127 * Inputs: BusDevFunc Bus+Device+Function number 130 * Inputs: BusDevFunc Bus+Device+Function number
128 * 131 *
129 * Return: None 132 * Return: None
130 * 133 *
131 */ 134 */
132 void pci_header_show(pci_dev_t dev) 135 void pci_header_show(pci_dev_t dev)
133 { 136 {
134 u8 _byte, header_type; 137 u8 _byte, header_type;
135 u16 _word; 138 u16 _word;
136 u32 _dword; 139 u32 _dword;
137 140
138 #define PRINT(msg, type, reg) \ 141 #define PRINT(msg, type, reg) \
139 pci_read_config_##type(dev, reg, &_##type); \ 142 pci_read_config_##type(dev, reg, &_##type); \
140 printf(msg, _##type) 143 printf(msg, _##type)
141 144
142 #define PRINT2(msg, type, reg, func) \ 145 #define PRINT2(msg, type, reg, func) \
143 pci_read_config_##type(dev, reg, &_##type); \ 146 pci_read_config_##type(dev, reg, &_##type); \
144 printf(msg, _##type, func(_##type)) 147 printf(msg, _##type, func(_##type))
145 148
146 pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type); 149 pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
147 150
148 PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID); 151 PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
149 PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID); 152 PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
150 PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND); 153 PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
151 PRINT (" status register = 0x%.4x\n", word, PCI_STATUS); 154 PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
152 PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID); 155 PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
153 PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE, 156 PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
154 pci_class_str); 157 pci_class_str);
155 PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE); 158 PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
156 PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG); 159 PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
157 PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE); 160 PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
158 PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER); 161 PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
159 PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE); 162 PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
160 PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST); 163 PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
161 PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0); 164 PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
162 165
163 switch (header_type & 0x03) { 166 switch (header_type & 0x03) {
164 case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */ 167 case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
165 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1); 168 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
166 PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2); 169 PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
167 PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3); 170 PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
168 PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4); 171 PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
169 PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5); 172 PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
170 PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS); 173 PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
171 PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID); 174 PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
172 PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID); 175 PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
173 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS); 176 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
174 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE); 177 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
175 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN); 178 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
176 PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT); 179 PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
177 PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT); 180 PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
178 break; 181 break;
179 182
180 case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */ 183 case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
181 184
182 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1); 185 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
183 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS); 186 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
184 PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS); 187 PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
185 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS); 188 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
186 PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER); 189 PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
187 PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE); 190 PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
188 PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT); 191 PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
189 PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS); 192 PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
190 PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE); 193 PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
191 PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT); 194 PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
192 PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE); 195 PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
193 PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT); 196 PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
194 PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32); 197 PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
195 PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32); 198 PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
196 PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16); 199 PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
197 PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16); 200 PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
198 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1); 201 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
199 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE); 202 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
200 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN); 203 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
201 PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL); 204 PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
202 break; 205 break;
203 206
204 case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */ 207 case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
205 208
206 PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST); 209 PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
207 PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS); 210 PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
208 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS); 211 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
209 PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS); 212 PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
210 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS); 213 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
211 PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER); 214 PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
212 PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0); 215 PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
213 PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0); 216 PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
214 PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1); 217 PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
215 PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1); 218 PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
216 PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0); 219 PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
217 PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI); 220 PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
218 PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0); 221 PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
219 PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI); 222 PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
220 PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1); 223 PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
221 PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI); 224 PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
222 PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1); 225 PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
223 PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI); 226 PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
224 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE); 227 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
225 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN); 228 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
226 PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL); 229 PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
227 PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID); 230 PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
228 PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID); 231 PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
229 PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE); 232 PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
230 break; 233 break;
231 234
232 default: 235 default:
233 printf("unknown header\n"); 236 printf("unknown header\n");
234 break; 237 break;
235 } 238 }
236 239
237 #undef PRINT 240 #undef PRINT
238 #undef PRINT2 241 #undef PRINT2
239 } 242 }
240 243
241 /* Convert the "bus.device.function" identifier into a number. 244 /* Convert the "bus.device.function" identifier into a number.
242 */ 245 */
243 static pci_dev_t get_pci_dev(char* name) 246 static pci_dev_t get_pci_dev(char* name)
244 { 247 {
245 char cnum[12]; 248 char cnum[12];
246 int len, i, iold, n; 249 int len, i, iold, n;
247 int bdfs[3] = {0,0,0}; 250 int bdfs[3] = {0,0,0};
248 251
249 len = strlen(name); 252 len = strlen(name);
250 if (len > 8) 253 if (len > 8)
251 return -1; 254 return -1;
252 for (i = 0, iold = 0, n = 0; i < len; i++) { 255 for (i = 0, iold = 0, n = 0; i < len; i++) {
253 if (name[i] == '.') { 256 if (name[i] == '.') {
254 memcpy(cnum, &name[iold], i - iold); 257 memcpy(cnum, &name[iold], i - iold);
255 cnum[i - iold] = '\0'; 258 cnum[i - iold] = '\0';
256 bdfs[n++] = simple_strtoul(cnum, NULL, 16); 259 bdfs[n++] = simple_strtoul(cnum, NULL, 16);
257 iold = i + 1; 260 iold = i + 1;
258 } 261 }
259 } 262 }
260 strcpy(cnum, &name[iold]); 263 strcpy(cnum, &name[iold]);
261 if (n == 0) 264 if (n == 0)
262 n = 1; 265 n = 1;
263 bdfs[n] = simple_strtoul(cnum, NULL, 16); 266 bdfs[n] = simple_strtoul(cnum, NULL, 16);
264 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]); 267 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
265 } 268 }
266 269
267 static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length) 270 static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
268 { 271 {
269 #define DISP_LINE_LEN 16 272 #define DISP_LINE_LEN 16
270 ulong i, nbytes, linebytes; 273 ulong i, nbytes, linebytes;
271 int rc = 0; 274 int rc = 0;
272 275
273 if (length == 0) 276 if (length == 0)
274 length = 0x40 / size; /* Standard PCI configuration space */ 277 length = 0x40 / size; /* Standard PCI configuration space */
275 278
276 /* Print the lines. 279 /* Print the lines.
277 * once, and all accesses are with the specified bus width. 280 * once, and all accesses are with the specified bus width.
278 */ 281 */
279 nbytes = length * size; 282 nbytes = length * size;
280 do { 283 do {
281 uint val4; 284 uint val4;
282 ushort val2; 285 ushort val2;
283 u_char val1; 286 u_char val1;
284 287
285 printf("%08lx:", addr); 288 printf("%08lx:", addr);
286 linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes; 289 linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
287 for (i=0; i<linebytes; i+= size) { 290 for (i=0; i<linebytes; i+= size) {
288 if (size == 4) { 291 if (size == 4) {
289 pci_read_config_dword(bdf, addr, &val4); 292 pci_read_config_dword(bdf, addr, &val4);
290 printf(" %08x", val4); 293 printf(" %08x", val4);
291 } else if (size == 2) { 294 } else if (size == 2) {
292 pci_read_config_word(bdf, addr, &val2); 295 pci_read_config_word(bdf, addr, &val2);
293 printf(" %04x", val2); 296 printf(" %04x", val2);
294 } else { 297 } else {
295 pci_read_config_byte(bdf, addr, &val1); 298 pci_read_config_byte(bdf, addr, &val1);
296 printf(" %02x", val1); 299 printf(" %02x", val1);
297 } 300 }
298 addr += size; 301 addr += size;
299 } 302 }
300 printf("\n"); 303 printf("\n");
301 nbytes -= linebytes; 304 nbytes -= linebytes;
302 if (ctrlc()) { 305 if (ctrlc()) {
303 rc = 1; 306 rc = 1;
304 break; 307 break;
305 } 308 }
306 } while (nbytes > 0); 309 } while (nbytes > 0);
307 310
308 return (rc); 311 return (rc);
309 } 312 }
310 313
311 static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value) 314 static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
312 { 315 {
313 if (size == 4) { 316 if (size == 4) {
314 pci_write_config_dword(bdf, addr, value); 317 pci_write_config_dword(bdf, addr, value);
315 } 318 }
316 else if (size == 2) { 319 else if (size == 2) {
317 ushort val = value & 0xffff; 320 ushort val = value & 0xffff;
318 pci_write_config_word(bdf, addr, val); 321 pci_write_config_word(bdf, addr, val);
319 } 322 }
320 else { 323 else {
321 u_char val = value & 0xff; 324 u_char val = value & 0xff;
322 pci_write_config_byte(bdf, addr, val); 325 pci_write_config_byte(bdf, addr, val);
323 } 326 }
324 return 0; 327 return 0;
325 } 328 }
326 329
327 static int 330 static int
328 pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag) 331 pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
329 { 332 {
330 ulong i; 333 ulong i;
331 int nbytes; 334 int nbytes;
332 uint val4; 335 uint val4;
333 ushort val2; 336 ushort val2;
334 u_char val1; 337 u_char val1;
335 338
336 /* Print the address, followed by value. Then accept input for 339 /* Print the address, followed by value. Then accept input for
337 * the next value. A non-converted value exits. 340 * the next value. A non-converted value exits.
338 */ 341 */
339 do { 342 do {
340 printf("%08lx:", addr); 343 printf("%08lx:", addr);
341 if (size == 4) { 344 if (size == 4) {
342 pci_read_config_dword(bdf, addr, &val4); 345 pci_read_config_dword(bdf, addr, &val4);
343 printf(" %08x", val4); 346 printf(" %08x", val4);
344 } 347 }
345 else if (size == 2) { 348 else if (size == 2) {
346 pci_read_config_word(bdf, addr, &val2); 349 pci_read_config_word(bdf, addr, &val2);
347 printf(" %04x", val2); 350 printf(" %04x", val2);
348 } 351 }
349 else { 352 else {
350 pci_read_config_byte(bdf, addr, &val1); 353 pci_read_config_byte(bdf, addr, &val1);
351 printf(" %02x", val1); 354 printf(" %02x", val1);
352 } 355 }
353 356
354 nbytes = cli_readline(" ? "); 357 nbytes = cli_readline(" ? ");
355 if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) { 358 if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
356 /* <CR> pressed as only input, don't modify current 359 /* <CR> pressed as only input, don't modify current
357 * location and move to next. "-" pressed will go back. 360 * location and move to next. "-" pressed will go back.
358 */ 361 */
359 if (incrflag) 362 if (incrflag)
360 addr += nbytes ? -size : size; 363 addr += nbytes ? -size : size;
361 nbytes = 1; 364 nbytes = 1;
362 /* good enough to not time out */ 365 /* good enough to not time out */
363 bootretry_reset_cmd_timeout(); 366 bootretry_reset_cmd_timeout();
364 } 367 }
365 #ifdef CONFIG_BOOT_RETRY_TIME 368 #ifdef CONFIG_BOOT_RETRY_TIME
366 else if (nbytes == -2) { 369 else if (nbytes == -2) {
367 break; /* timed out, exit the command */ 370 break; /* timed out, exit the command */
368 } 371 }
369 #endif 372 #endif
370 else { 373 else {
371 char *endp; 374 char *endp;
372 i = simple_strtoul(console_buffer, &endp, 16); 375 i = simple_strtoul(console_buffer, &endp, 16);
373 nbytes = endp - console_buffer; 376 nbytes = endp - console_buffer;
374 if (nbytes) { 377 if (nbytes) {
375 /* good enough to not time out 378 /* good enough to not time out
376 */ 379 */
377 bootretry_reset_cmd_timeout(); 380 bootretry_reset_cmd_timeout();
378 pci_cfg_write (bdf, addr, size, i); 381 pci_cfg_write (bdf, addr, size, i);
379 if (incrflag) 382 if (incrflag)
380 addr += size; 383 addr += size;
381 } 384 }
382 } 385 }
383 } while (nbytes); 386 } while (nbytes);
384 387
385 return 0; 388 return 0;
386 } 389 }
387 390
388 /* PCI Configuration Space access commands 391 /* PCI Configuration Space access commands
389 * 392 *
390 * Syntax: 393 * Syntax:
391 * pci display[.b, .w, .l] bus.device.function} [addr] [len] 394 * pci display[.b, .w, .l] bus.device.function} [addr] [len]
392 * pci next[.b, .w, .l] bus.device.function [addr] 395 * pci next[.b, .w, .l] bus.device.function [addr]
393 * pci modify[.b, .w, .l] bus.device.function [addr] 396 * pci modify[.b, .w, .l] bus.device.function [addr]
394 * pci write[.b, .w, .l] bus.device.function addr value 397 * pci write[.b, .w, .l] bus.device.function addr value
395 */ 398 */
396 static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 399 static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
397 { 400 {
398 ulong addr = 0, value = 0, size = 0; 401 ulong addr = 0, value = 0, size = 0;
399 pci_dev_t bdf = 0; 402 pci_dev_t bdf = 0;
400 char cmd = 's'; 403 char cmd = 's';
401 404
402 if (argc > 1) 405 if (argc > 1)
403 cmd = argv[1][0]; 406 cmd = argv[1][0];
404 407
405 switch (cmd) { 408 switch (cmd) {
406 case 'd': /* display */ 409 case 'd': /* display */
407 case 'n': /* next */ 410 case 'n': /* next */
408 case 'm': /* modify */ 411 case 'm': /* modify */
409 case 'w': /* write */ 412 case 'w': /* write */
410 /* Check for a size specification. */ 413 /* Check for a size specification. */
411 size = cmd_get_data_size(argv[1], 4); 414 size = cmd_get_data_size(argv[1], 4);
412 if (argc > 3) 415 if (argc > 3)
413 addr = simple_strtoul(argv[3], NULL, 16); 416 addr = simple_strtoul(argv[3], NULL, 16);
414 if (argc > 4) 417 if (argc > 4)
415 value = simple_strtoul(argv[4], NULL, 16); 418 value = simple_strtoul(argv[4], NULL, 16);
416 case 'h': /* header */ 419 case 'h': /* header */
417 if (argc < 3) 420 if (argc < 3)
418 goto usage; 421 goto usage;
419 if ((bdf = get_pci_dev(argv[2])) == -1) 422 if ((bdf = get_pci_dev(argv[2])) == -1)
420 return 1; 423 return 1;
421 break; 424 break;
422 #ifdef CONFIG_CMD_PCI_ENUM 425 #ifdef CONFIG_CMD_PCI_ENUM
423 case 'e': 426 case 'e':
424 break; 427 break;
425 #endif 428 #endif
426 default: /* scan bus */ 429 default: /* scan bus */
427 value = 1; /* short listing */ 430 value = 1; /* short listing */
428 bdf = 0; /* bus number */ 431 bdf = 0; /* bus number */
429 if (argc > 1) { 432 if (argc > 1) {
430 if (argv[argc-1][0] == 'l') { 433 if (argv[argc-1][0] == 'l') {
431 value = 0; 434 value = 0;
432 argc--; 435 argc--;
433 } 436 }
434 if (argc > 1) 437 if (argc > 1)
435 bdf = simple_strtoul(argv[1], NULL, 16); 438 bdf = simple_strtoul(argv[1], NULL, 16);
436 } 439 }
437 pciinfo(bdf, value); 440 pciinfo(bdf, value);
438 return 0; 441 return 0;
439 } 442 }
440 443
441 switch (argv[1][0]) { 444 switch (argv[1][0]) {
442 case 'h': /* header */ 445 case 'h': /* header */
443 pci_header_show(bdf); 446 pci_header_show(bdf);
444 return 0; 447 return 0;
445 case 'd': /* display */ 448 case 'd': /* display */
446 return pci_cfg_display(bdf, addr, size, value); 449 return pci_cfg_display(bdf, addr, size, value);
447 #ifdef CONFIG_CMD_PCI_ENUM 450 #ifdef CONFIG_CMD_PCI_ENUM
448 case 'e': 451 case 'e':
449 pci_init(); 452 pci_init();
450 return 0; 453 return 0;
451 #endif 454 #endif
452 case 'n': /* next */ 455 case 'n': /* next */
453 if (argc < 4) 456 if (argc < 4)
454 goto usage; 457 goto usage;
455 return pci_cfg_modify(bdf, addr, size, value, 0); 458 return pci_cfg_modify(bdf, addr, size, value, 0);
456 case 'm': /* modify */ 459 case 'm': /* modify */
457 if (argc < 4) 460 if (argc < 4)
458 goto usage; 461 goto usage;
459 return pci_cfg_modify(bdf, addr, size, value, 1); 462 return pci_cfg_modify(bdf, addr, size, value, 1);
460 case 'w': /* write */ 463 case 'w': /* write */
461 if (argc < 5) 464 if (argc < 5)
462 goto usage; 465 goto usage;
463 return pci_cfg_write(bdf, addr, size, value); 466 return pci_cfg_write(bdf, addr, size, value);
464 } 467 }
465 468
466 return 1; 469 return 1;
467 usage: 470 usage:
468 return CMD_RET_USAGE; 471 return CMD_RET_USAGE;
469 } 472 }
470 473
471 /***************************************************/ 474 /***************************************************/
472 475
473 #ifdef CONFIG_SYS_LONGHELP 476 #ifdef CONFIG_SYS_LONGHELP
474 static char pci_help_text[] = 477 static char pci_help_text[] =
475 "[bus] [long]\n" 478 "[bus] [long]\n"
476 " - short or long list of PCI devices on bus 'bus'\n" 479 " - short or long list of PCI devices on bus 'bus'\n"
477 #ifdef CONFIG_CMD_PCI_ENUM 480 #ifdef CONFIG_CMD_PCI_ENUM
478 "pci enum\n" 481 "pci enum\n"
479 " - re-enumerate PCI buses\n" 482 " - re-enumerate PCI buses\n"
480 #endif 483 #endif
481 "pci header b.d.f\n" 484 "pci header b.d.f\n"
482 " - show header of PCI device 'bus.device.function'\n" 485 " - show header of PCI device 'bus.device.function'\n"
483 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n" 486 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
484 " - display PCI configuration space (CFG)\n" 487 " - display PCI configuration space (CFG)\n"
485 "pci next[.b, .w, .l] b.d.f address\n" 488 "pci next[.b, .w, .l] b.d.f address\n"
486 " - modify, read and keep CFG address\n" 489 " - modify, read and keep CFG address\n"
487 "pci modify[.b, .w, .l] b.d.f address\n" 490 "pci modify[.b, .w, .l] b.d.f address\n"
488 " - modify, auto increment CFG address\n" 491 " - modify, auto increment CFG address\n"
489 "pci write[.b, .w, .l] b.d.f address value\n" 492 "pci write[.b, .w, .l] b.d.f address value\n"
490 " - write to CFG address"; 493 " - write to CFG address";
491 #endif 494 #endif
492 495
493 U_BOOT_CMD( 496 U_BOOT_CMD(
494 pci, 5, 1, do_pci, 497 pci, 5, 1, do_pci,
495 "list and access PCI Configuration Space", pci_help_text 498 "list and access PCI Configuration Space", pci_help_text
496 ); 499 );
497 500
1 /* 1 /*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de> 3 * Andreas Heppel <aheppel@sysgo.de>
4 * 4 *
5 * (C) Copyright 2002, 2003 5 * (C) Copyright 2002, 2003
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * 7 *
8 * SPDX-License-Identifier: GPL-2.0+ 8 * SPDX-License-Identifier: GPL-2.0+
9 */ 9 */
10 10
11 /* 11 /*
12 * PCI routines 12 * PCI routines
13 */ 13 */
14 14
15 #include <common.h> 15 #include <common.h>
16 16
17 #include <command.h> 17 #include <command.h>
18 #include <asm/processor.h> 18 #include <asm/processor.h>
19 #include <asm/io.h> 19 #include <asm/io.h>
20 #include <pci.h> 20 #include <pci.h>
21 21
22 #define PCI_HOSE_OP(rw, size, type) \ 22 #define PCI_HOSE_OP(rw, size, type) \
23 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \ 23 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
24 pci_dev_t dev, \ 24 pci_dev_t dev, \
25 int offset, type value) \ 25 int offset, type value) \
26 { \ 26 { \
27 return hose->rw##_##size(hose, dev, offset, value); \ 27 return hose->rw##_##size(hose, dev, offset, value); \
28 } 28 }
29 29
30 PCI_HOSE_OP(read, byte, u8 *) 30 PCI_HOSE_OP(read, byte, u8 *)
31 PCI_HOSE_OP(read, word, u16 *) 31 PCI_HOSE_OP(read, word, u16 *)
32 PCI_HOSE_OP(read, dword, u32 *) 32 PCI_HOSE_OP(read, dword, u32 *)
33 PCI_HOSE_OP(write, byte, u8) 33 PCI_HOSE_OP(write, byte, u8)
34 PCI_HOSE_OP(write, word, u16) 34 PCI_HOSE_OP(write, word, u16)
35 PCI_HOSE_OP(write, dword, u32) 35 PCI_HOSE_OP(write, dword, u32)
36 36
37 #define PCI_OP(rw, size, type, error_code) \ 37 #define PCI_OP(rw, size, type, error_code) \
38 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \ 38 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
39 { \ 39 { \
40 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \ 40 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
41 \ 41 \
42 if (!hose) \ 42 if (!hose) \
43 { \ 43 { \
44 error_code; \ 44 error_code; \
45 return -1; \ 45 return -1; \
46 } \ 46 } \
47 \ 47 \
48 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \ 48 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
49 } 49 }
50 50
51 PCI_OP(read, byte, u8 *, *value = 0xff) 51 PCI_OP(read, byte, u8 *, *value = 0xff)
52 PCI_OP(read, word, u16 *, *value = 0xffff) 52 PCI_OP(read, word, u16 *, *value = 0xffff)
53 PCI_OP(read, dword, u32 *, *value = 0xffffffff) 53 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
54 PCI_OP(write, byte, u8, ) 54 PCI_OP(write, byte, u8, )
55 PCI_OP(write, word, u16, ) 55 PCI_OP(write, word, u16, )
56 PCI_OP(write, dword, u32, ) 56 PCI_OP(write, dword, u32, )
57 57
58 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \ 58 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
59 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\ 59 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
60 pci_dev_t dev, \ 60 pci_dev_t dev, \
61 int offset, type val) \ 61 int offset, type val) \
62 { \ 62 { \
63 u32 val32; \ 63 u32 val32; \
64 \ 64 \
65 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \ 65 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
66 *val = -1; \ 66 *val = -1; \
67 return -1; \ 67 return -1; \
68 } \ 68 } \
69 \ 69 \
70 *val = (val32 >> ((offset & (int)off_mask) * 8)); \ 70 *val = (val32 >> ((offset & (int)off_mask) * 8)); \
71 \ 71 \
72 return 0; \ 72 return 0; \
73 } 73 }
74 74
75 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \ 75 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
76 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\ 76 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
77 pci_dev_t dev, \ 77 pci_dev_t dev, \
78 int offset, type val) \ 78 int offset, type val) \
79 { \ 79 { \
80 u32 val32, mask, ldata, shift; \ 80 u32 val32, mask, ldata, shift; \
81 \ 81 \
82 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\ 82 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
83 return -1; \ 83 return -1; \
84 \ 84 \
85 shift = ((offset & (int)off_mask) * 8); \ 85 shift = ((offset & (int)off_mask) * 8); \
86 ldata = (((unsigned long)val) & val_mask) << shift; \ 86 ldata = (((unsigned long)val) & val_mask) << shift; \
87 mask = val_mask << shift; \ 87 mask = val_mask << shift; \
88 val32 = (val32 & ~mask) | ldata; \ 88 val32 = (val32 & ~mask) | ldata; \
89 \ 89 \
90 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\ 90 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
91 return -1; \ 91 return -1; \
92 \ 92 \
93 return 0; \ 93 return 0; \
94 } 94 }
95 95
96 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03) 96 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
97 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02) 97 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
98 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff) 98 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
99 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff) 99 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
100 100
101 /* Get a virtual address associated with a BAR region */ 101 /* Get a virtual address associated with a BAR region */
102 void *pci_map_bar(pci_dev_t pdev, int bar, int flags) 102 void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
103 { 103 {
104 pci_addr_t pci_bus_addr; 104 pci_addr_t pci_bus_addr;
105 u32 bar_response; 105 u32 bar_response;
106 106
107 /* read BAR address */ 107 /* read BAR address */
108 pci_read_config_dword(pdev, bar, &bar_response); 108 pci_read_config_dword(pdev, bar, &bar_response);
109 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf); 109 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
110 110
111 /* 111 /*
112 * Pass "0" as the length argument to pci_bus_to_virt. The arg 112 * Pass "0" as the length argument to pci_bus_to_virt. The arg
113 * isn't actualy used on any platform because u-boot assumes a static 113 * isn't actualy used on any platform because u-boot assumes a static
114 * linear mapping. In the future, this could read the BAR size 114 * linear mapping. In the future, this could read the BAR size
115 * and pass that as the size if needed. 115 * and pass that as the size if needed.
116 */ 116 */
117 return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE); 117 return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
118 } 118 }
119 119
120 /* 120 /*
121 * 121 *
122 */ 122 */
123 123
124 static struct pci_controller* hose_head; 124 static struct pci_controller* hose_head;
125 125
126 void pci_register_hose(struct pci_controller* hose) 126 void pci_register_hose(struct pci_controller* hose)
127 { 127 {
128 struct pci_controller **phose = &hose_head; 128 struct pci_controller **phose = &hose_head;
129 129
130 while(*phose) 130 while(*phose)
131 phose = &(*phose)->next; 131 phose = &(*phose)->next;
132 132
133 hose->next = NULL; 133 hose->next = NULL;
134 134
135 *phose = hose; 135 *phose = hose;
136 } 136 }
137 137
138 struct pci_controller *pci_bus_to_hose(int bus) 138 struct pci_controller *pci_bus_to_hose(int bus)
139 { 139 {
140 struct pci_controller *hose; 140 struct pci_controller *hose;
141 141
142 for (hose = hose_head; hose; hose = hose->next) { 142 for (hose = hose_head; hose; hose = hose->next) {
143 if (bus >= hose->first_busno && bus <= hose->last_busno) 143 if (bus >= hose->first_busno && bus <= hose->last_busno)
144 return hose; 144 return hose;
145 } 145 }
146 146
147 printf("pci_bus_to_hose() failed\n"); 147 printf("pci_bus_to_hose() failed\n");
148 return NULL; 148 return NULL;
149 } 149 }
150 150
151 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr) 151 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
152 { 152 {
153 struct pci_controller *hose; 153 struct pci_controller *hose;
154 154
155 for (hose = hose_head; hose; hose = hose->next) { 155 for (hose = hose_head; hose; hose = hose->next) {
156 if (hose->cfg_addr == cfg_addr) 156 if (hose->cfg_addr == cfg_addr)
157 return hose; 157 return hose;
158 } 158 }
159 159
160 return NULL; 160 return NULL;
161 } 161 }
162 162
163 int pci_last_busno(void) 163 int pci_last_busno(void)
164 { 164 {
165 struct pci_controller *hose = hose_head; 165 struct pci_controller *hose = hose_head;
166 166
167 if (!hose) 167 if (!hose)
168 return -1; 168 return -1;
169 169
170 while (hose->next) 170 while (hose->next)
171 hose = hose->next; 171 hose = hose->next;
172 172
173 return hose->last_busno; 173 return hose->last_busno;
174 } 174 }
175 175
176 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) 176 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
177 { 177 {
178 struct pci_controller * hose; 178 struct pci_controller * hose;
179 u16 vendor, device; 179 u16 vendor, device;
180 u8 header_type; 180 u8 header_type;
181 pci_dev_t bdf; 181 pci_dev_t bdf;
182 int i, bus, found_multi = 0; 182 int i, bus, found_multi = 0;
183 183
184 for (hose = hose_head; hose; hose = hose->next) { 184 for (hose = hose_head; hose; hose = hose->next) {
185 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 185 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
186 for (bus = hose->last_busno; bus >= hose->first_busno; bus--) 186 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
187 #else 187 #else
188 for (bus = hose->first_busno; bus <= hose->last_busno; bus++) 188 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
189 #endif 189 #endif
190 for (bdf = PCI_BDF(bus, 0, 0); 190 for (bdf = PCI_BDF(bus, 0, 0);
191 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX) 191 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
192 bdf < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1, 192 bdf < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
193 PCI_MAX_PCI_FUNCTIONS - 1); 193 PCI_MAX_PCI_FUNCTIONS - 1);
194 #else 194 #else
195 bdf < PCI_BDF(bus + 1, 0, 0); 195 bdf < PCI_BDF(bus + 1, 0, 0);
196 #endif 196 #endif
197 bdf += PCI_BDF(0, 0, 1)) { 197 bdf += PCI_BDF(0, 0, 1)) {
198 if (pci_skip_dev(hose, bdf))
199 continue;
200
198 if (!PCI_FUNC(bdf)) { 201 if (!PCI_FUNC(bdf)) {
199 pci_read_config_byte(bdf, 202 pci_read_config_byte(bdf,
200 PCI_HEADER_TYPE, 203 PCI_HEADER_TYPE,
201 &header_type); 204 &header_type);
202 205
203 found_multi = header_type & 0x80; 206 found_multi = header_type & 0x80;
204 } else { 207 } else {
205 if (!found_multi) 208 if (!found_multi)
206 continue; 209 continue;
207 } 210 }
208 211
209 pci_read_config_word(bdf, 212 pci_read_config_word(bdf,
210 PCI_VENDOR_ID, 213 PCI_VENDOR_ID,
211 &vendor); 214 &vendor);
212 pci_read_config_word(bdf, 215 pci_read_config_word(bdf,
213 PCI_DEVICE_ID, 216 PCI_DEVICE_ID,
214 &device); 217 &device);
215 218
216 for (i = 0; ids[i].vendor != 0; i++) { 219 for (i = 0; ids[i].vendor != 0; i++) {
217 if (vendor == ids[i].vendor && 220 if (vendor == ids[i].vendor &&
218 device == ids[i].device) { 221 device == ids[i].device) {
219 if (index <= 0) 222 if (index <= 0)
220 return bdf; 223 return bdf;
221 224
222 index--; 225 index--;
223 } 226 }
224 } 227 }
225 } 228 }
226 } 229 }
227 230
228 return -1; 231 return -1;
229 } 232 }
230 233
231 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index) 234 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
232 { 235 {
233 static struct pci_device_id ids[2] = {{}, {0, 0}}; 236 static struct pci_device_id ids[2] = {{}, {0, 0}};
234 237
235 ids[0].vendor = vendor; 238 ids[0].vendor = vendor;
236 ids[0].device = device; 239 ids[0].device = device;
237 240
238 return pci_find_devices(ids, index); 241 return pci_find_devices(ids, index);
239 } 242 }
240 243
241 /* 244 /*
242 * 245 *
243 */ 246 */
244 247
245 int __pci_hose_phys_to_bus(struct pci_controller *hose, 248 int __pci_hose_phys_to_bus(struct pci_controller *hose,
246 phys_addr_t phys_addr, 249 phys_addr_t phys_addr,
247 unsigned long flags, 250 unsigned long flags,
248 unsigned long skip_mask, 251 unsigned long skip_mask,
249 pci_addr_t *ba) 252 pci_addr_t *ba)
250 { 253 {
251 struct pci_region *res; 254 struct pci_region *res;
252 pci_addr_t bus_addr; 255 pci_addr_t bus_addr;
253 int i; 256 int i;
254 257
255 for (i = 0; i < hose->region_count; i++) { 258 for (i = 0; i < hose->region_count; i++) {
256 res = &hose->regions[i]; 259 res = &hose->regions[i];
257 260
258 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) 261 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
259 continue; 262 continue;
260 263
261 if (res->flags & skip_mask) 264 if (res->flags & skip_mask)
262 continue; 265 continue;
263 266
264 bus_addr = phys_addr - res->phys_start + res->bus_start; 267 bus_addr = phys_addr - res->phys_start + res->bus_start;
265 268
266 if (bus_addr >= res->bus_start && 269 if (bus_addr >= res->bus_start &&
267 bus_addr < res->bus_start + res->size) { 270 bus_addr < res->bus_start + res->size) {
268 *ba = bus_addr; 271 *ba = bus_addr;
269 return 0; 272 return 0;
270 } 273 }
271 } 274 }
272 275
273 return 1; 276 return 1;
274 } 277 }
275 278
276 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose, 279 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
277 phys_addr_t phys_addr, 280 phys_addr_t phys_addr,
278 unsigned long flags) 281 unsigned long flags)
279 { 282 {
280 pci_addr_t bus_addr = 0; 283 pci_addr_t bus_addr = 0;
281 int ret; 284 int ret;
282 285
283 if (!hose) { 286 if (!hose) {
284 puts("pci_hose_phys_to_bus: invalid hose\n"); 287 puts("pci_hose_phys_to_bus: invalid hose\n");
285 return bus_addr; 288 return bus_addr;
286 } 289 }
287 290
288 /* 291 /*
289 * if PCI_REGION_MEM is set we do a two pass search with preference 292 * if PCI_REGION_MEM is set we do a two pass search with preference
290 * on matches that don't have PCI_REGION_SYS_MEMORY set 293 * on matches that don't have PCI_REGION_SYS_MEMORY set
291 */ 294 */
292 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) { 295 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
293 ret = __pci_hose_phys_to_bus(hose, phys_addr, 296 ret = __pci_hose_phys_to_bus(hose, phys_addr,
294 flags, PCI_REGION_SYS_MEMORY, &bus_addr); 297 flags, PCI_REGION_SYS_MEMORY, &bus_addr);
295 if (!ret) 298 if (!ret)
296 return bus_addr; 299 return bus_addr;
297 } 300 }
298 301
299 ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr); 302 ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
300 303
301 if (ret) 304 if (ret)
302 puts("pci_hose_phys_to_bus: invalid physical address\n"); 305 puts("pci_hose_phys_to_bus: invalid physical address\n");
303 306
304 return bus_addr; 307 return bus_addr;
305 } 308 }
306 309
307 int __pci_hose_bus_to_phys(struct pci_controller *hose, 310 int __pci_hose_bus_to_phys(struct pci_controller *hose,
308 pci_addr_t bus_addr, 311 pci_addr_t bus_addr,
309 unsigned long flags, 312 unsigned long flags,
310 unsigned long skip_mask, 313 unsigned long skip_mask,
311 phys_addr_t *pa) 314 phys_addr_t *pa)
312 { 315 {
313 struct pci_region *res; 316 struct pci_region *res;
314 int i; 317 int i;
315 318
316 for (i = 0; i < hose->region_count; i++) { 319 for (i = 0; i < hose->region_count; i++) {
317 res = &hose->regions[i]; 320 res = &hose->regions[i];
318 321
319 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) 322 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
320 continue; 323 continue;
321 324
322 if (res->flags & skip_mask) 325 if (res->flags & skip_mask)
323 continue; 326 continue;
324 327
325 if (bus_addr >= res->bus_start && 328 if (bus_addr >= res->bus_start &&
326 (bus_addr - res->bus_start) < res->size) { 329 (bus_addr - res->bus_start) < res->size) {
327 *pa = (bus_addr - res->bus_start + res->phys_start); 330 *pa = (bus_addr - res->bus_start + res->phys_start);
328 return 0; 331 return 0;
329 } 332 }
330 } 333 }
331 334
332 return 1; 335 return 1;
333 } 336 }
334 337
335 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, 338 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
336 pci_addr_t bus_addr, 339 pci_addr_t bus_addr,
337 unsigned long flags) 340 unsigned long flags)
338 { 341 {
339 phys_addr_t phys_addr = 0; 342 phys_addr_t phys_addr = 0;
340 int ret; 343 int ret;
341 344
342 if (!hose) { 345 if (!hose) {
343 puts("pci_hose_bus_to_phys: invalid hose\n"); 346 puts("pci_hose_bus_to_phys: invalid hose\n");
344 return phys_addr; 347 return phys_addr;
345 } 348 }
346 349
347 /* 350 /*
348 * if PCI_REGION_MEM is set we do a two pass search with preference 351 * if PCI_REGION_MEM is set we do a two pass search with preference
349 * on matches that don't have PCI_REGION_SYS_MEMORY set 352 * on matches that don't have PCI_REGION_SYS_MEMORY set
350 */ 353 */
351 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) { 354 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
352 ret = __pci_hose_bus_to_phys(hose, bus_addr, 355 ret = __pci_hose_bus_to_phys(hose, bus_addr,
353 flags, PCI_REGION_SYS_MEMORY, &phys_addr); 356 flags, PCI_REGION_SYS_MEMORY, &phys_addr);
354 if (!ret) 357 if (!ret)
355 return phys_addr; 358 return phys_addr;
356 } 359 }
357 360
358 ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr); 361 ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
359 362
360 if (ret) 363 if (ret)
361 puts("pci_hose_bus_to_phys: invalid physical address\n"); 364 puts("pci_hose_bus_to_phys: invalid physical address\n");
362 365
363 return phys_addr; 366 return phys_addr;
364 } 367 }
365 368
366 /* 369 /*
367 * 370 *
368 */ 371 */
369 372
370 int pci_hose_config_device(struct pci_controller *hose, 373 int pci_hose_config_device(struct pci_controller *hose,
371 pci_dev_t dev, 374 pci_dev_t dev,
372 unsigned long io, 375 unsigned long io,
373 pci_addr_t mem, 376 pci_addr_t mem,
374 unsigned long command) 377 unsigned long command)
375 { 378 {
376 u32 bar_response; 379 u32 bar_response;
377 unsigned int old_command; 380 unsigned int old_command;
378 pci_addr_t bar_value; 381 pci_addr_t bar_value;
379 pci_size_t bar_size; 382 pci_size_t bar_size;
380 unsigned char pin; 383 unsigned char pin;
381 int bar, found_mem64; 384 int bar, found_mem64;
382 385
383 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io, 386 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
384 (u64)mem, command); 387 (u64)mem, command);
385 388
386 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0); 389 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
387 390
388 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) { 391 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
389 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); 392 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
390 pci_hose_read_config_dword(hose, dev, bar, &bar_response); 393 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
391 394
392 if (!bar_response) 395 if (!bar_response)
393 continue; 396 continue;
394 397
395 found_mem64 = 0; 398 found_mem64 = 0;
396 399
397 /* Check the BAR type and set our address mask */ 400 /* Check the BAR type and set our address mask */
398 if (bar_response & PCI_BASE_ADDRESS_SPACE) { 401 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
399 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; 402 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
400 /* round up region base address to a multiple of size */ 403 /* round up region base address to a multiple of size */
401 io = ((io - 1) | (bar_size - 1)) + 1; 404 io = ((io - 1) | (bar_size - 1)) + 1;
402 bar_value = io; 405 bar_value = io;
403 /* compute new region base address */ 406 /* compute new region base address */
404 io = io + bar_size; 407 io = io + bar_size;
405 } else { 408 } else {
406 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 409 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
407 PCI_BASE_ADDRESS_MEM_TYPE_64) { 410 PCI_BASE_ADDRESS_MEM_TYPE_64) {
408 u32 bar_response_upper; 411 u32 bar_response_upper;
409 u64 bar64; 412 u64 bar64;
410 pci_hose_write_config_dword(hose, dev, bar + 4, 413 pci_hose_write_config_dword(hose, dev, bar + 4,
411 0xffffffff); 414 0xffffffff);
412 pci_hose_read_config_dword(hose, dev, bar + 4, 415 pci_hose_read_config_dword(hose, dev, bar + 4,
413 &bar_response_upper); 416 &bar_response_upper);
414 417
415 bar64 = ((u64)bar_response_upper << 32) | bar_response; 418 bar64 = ((u64)bar_response_upper << 32) | bar_response;
416 419
417 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1; 420 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
418 found_mem64 = 1; 421 found_mem64 = 1;
419 } else { 422 } else {
420 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1); 423 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
421 } 424 }
422 425
423 /* round up region base address to multiple of size */ 426 /* round up region base address to multiple of size */
424 mem = ((mem - 1) | (bar_size - 1)) + 1; 427 mem = ((mem - 1) | (bar_size - 1)) + 1;
425 bar_value = mem; 428 bar_value = mem;
426 /* compute new region base address */ 429 /* compute new region base address */
427 mem = mem + bar_size; 430 mem = mem + bar_size;
428 } 431 }
429 432
430 /* Write it out and update our limit */ 433 /* Write it out and update our limit */
431 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value); 434 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
432 435
433 if (found_mem64) { 436 if (found_mem64) {
434 bar += 4; 437 bar += 4;
435 #ifdef CONFIG_SYS_PCI_64BIT 438 #ifdef CONFIG_SYS_PCI_64BIT
436 pci_hose_write_config_dword(hose, dev, bar, 439 pci_hose_write_config_dword(hose, dev, bar,
437 (u32)(bar_value >> 32)); 440 (u32)(bar_value >> 32));
438 #else 441 #else
439 pci_hose_write_config_dword(hose, dev, bar, 0x00000000); 442 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
440 #endif 443 #endif
441 } 444 }
442 } 445 }
443 446
444 /* Configure Cache Line Size Register */ 447 /* Configure Cache Line Size Register */
445 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 448 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
446 449
447 /* Configure Latency Timer */ 450 /* Configure Latency Timer */
448 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 451 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
449 452
450 /* Disable interrupt line, if device says it wants to use interrupts */ 453 /* Disable interrupt line, if device says it wants to use interrupts */
451 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); 454 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
452 if (pin != 0) { 455 if (pin != 0) {
453 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff); 456 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff);
454 } 457 }
455 458
456 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command); 459 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
457 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 460 pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
458 (old_command & 0xffff0000) | command); 461 (old_command & 0xffff0000) | command);
459 462
460 return 0; 463 return 0;
461 } 464 }
462 465
463 /* 466 /*
464 * 467 *
465 */ 468 */
466 469
467 struct pci_config_table *pci_find_config(struct pci_controller *hose, 470 struct pci_config_table *pci_find_config(struct pci_controller *hose,
468 unsigned short class, 471 unsigned short class,
469 unsigned int vendor, 472 unsigned int vendor,
470 unsigned int device, 473 unsigned int device,
471 unsigned int bus, 474 unsigned int bus,
472 unsigned int dev, 475 unsigned int dev,
473 unsigned int func) 476 unsigned int func)
474 { 477 {
475 struct pci_config_table *table; 478 struct pci_config_table *table;
476 479
477 for (table = hose->config_table; table && table->vendor; table++) { 480 for (table = hose->config_table; table && table->vendor; table++) {
478 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) && 481 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
479 (table->device == PCI_ANY_ID || table->device == device) && 482 (table->device == PCI_ANY_ID || table->device == device) &&
480 (table->class == PCI_ANY_ID || table->class == class) && 483 (table->class == PCI_ANY_ID || table->class == class) &&
481 (table->bus == PCI_ANY_ID || table->bus == bus) && 484 (table->bus == PCI_ANY_ID || table->bus == bus) &&
482 (table->dev == PCI_ANY_ID || table->dev == dev) && 485 (table->dev == PCI_ANY_ID || table->dev == dev) &&
483 (table->func == PCI_ANY_ID || table->func == func)) { 486 (table->func == PCI_ANY_ID || table->func == func)) {
484 return table; 487 return table;
485 } 488 }
486 } 489 }
487 490
488 return NULL; 491 return NULL;
489 } 492 }
490 493
491 void pci_cfgfunc_config_device(struct pci_controller *hose, 494 void pci_cfgfunc_config_device(struct pci_controller *hose,
492 pci_dev_t dev, 495 pci_dev_t dev,
493 struct pci_config_table *entry) 496 struct pci_config_table *entry)
494 { 497 {
495 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], 498 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
496 entry->priv[2]); 499 entry->priv[2]);
497 } 500 }
498 501
499 void pci_cfgfunc_do_nothing(struct pci_controller *hose, 502 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
500 pci_dev_t dev, struct pci_config_table *entry) 503 pci_dev_t dev, struct pci_config_table *entry)
501 { 504 {
502 } 505 }
503 506
504 /* 507 /*
505 * HJF: Changed this to return int. I think this is required 508 * HJF: Changed this to return int. I think this is required
506 * to get the correct result when scanning bridges 509 * to get the correct result when scanning bridges
507 */ 510 */
508 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 511 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
509 512
510 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW) 513 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
511 const char * pci_class_str(u8 class) 514 const char * pci_class_str(u8 class)
512 { 515 {
513 switch (class) { 516 switch (class) {
514 case PCI_CLASS_NOT_DEFINED: 517 case PCI_CLASS_NOT_DEFINED:
515 return "Build before PCI Rev2.0"; 518 return "Build before PCI Rev2.0";
516 break; 519 break;
517 case PCI_BASE_CLASS_STORAGE: 520 case PCI_BASE_CLASS_STORAGE:
518 return "Mass storage controller"; 521 return "Mass storage controller";
519 break; 522 break;
520 case PCI_BASE_CLASS_NETWORK: 523 case PCI_BASE_CLASS_NETWORK:
521 return "Network controller"; 524 return "Network controller";
522 break; 525 break;
523 case PCI_BASE_CLASS_DISPLAY: 526 case PCI_BASE_CLASS_DISPLAY:
524 return "Display controller"; 527 return "Display controller";
525 break; 528 break;
526 case PCI_BASE_CLASS_MULTIMEDIA: 529 case PCI_BASE_CLASS_MULTIMEDIA:
527 return "Multimedia device"; 530 return "Multimedia device";
528 break; 531 break;
529 case PCI_BASE_CLASS_MEMORY: 532 case PCI_BASE_CLASS_MEMORY:
530 return "Memory controller"; 533 return "Memory controller";
531 break; 534 break;
532 case PCI_BASE_CLASS_BRIDGE: 535 case PCI_BASE_CLASS_BRIDGE:
533 return "Bridge device"; 536 return "Bridge device";
534 break; 537 break;
535 case PCI_BASE_CLASS_COMMUNICATION: 538 case PCI_BASE_CLASS_COMMUNICATION:
536 return "Simple comm. controller"; 539 return "Simple comm. controller";
537 break; 540 break;
538 case PCI_BASE_CLASS_SYSTEM: 541 case PCI_BASE_CLASS_SYSTEM:
539 return "Base system peripheral"; 542 return "Base system peripheral";
540 break; 543 break;
541 case PCI_BASE_CLASS_INPUT: 544 case PCI_BASE_CLASS_INPUT:
542 return "Input device"; 545 return "Input device";
543 break; 546 break;
544 case PCI_BASE_CLASS_DOCKING: 547 case PCI_BASE_CLASS_DOCKING:
545 return "Docking station"; 548 return "Docking station";
546 break; 549 break;
547 case PCI_BASE_CLASS_PROCESSOR: 550 case PCI_BASE_CLASS_PROCESSOR:
548 return "Processor"; 551 return "Processor";
549 break; 552 break;
550 case PCI_BASE_CLASS_SERIAL: 553 case PCI_BASE_CLASS_SERIAL:
551 return "Serial bus controller"; 554 return "Serial bus controller";
552 break; 555 break;
553 case PCI_BASE_CLASS_INTELLIGENT: 556 case PCI_BASE_CLASS_INTELLIGENT:
554 return "Intelligent controller"; 557 return "Intelligent controller";
555 break; 558 break;
556 case PCI_BASE_CLASS_SATELLITE: 559 case PCI_BASE_CLASS_SATELLITE:
557 return "Satellite controller"; 560 return "Satellite controller";
558 break; 561 break;
559 case PCI_BASE_CLASS_CRYPT: 562 case PCI_BASE_CLASS_CRYPT:
560 return "Cryptographic device"; 563 return "Cryptographic device";
561 break; 564 break;
562 case PCI_BASE_CLASS_SIGNAL_PROCESSING: 565 case PCI_BASE_CLASS_SIGNAL_PROCESSING:
563 return "DSP"; 566 return "DSP";
564 break; 567 break;
565 case PCI_CLASS_OTHERS: 568 case PCI_CLASS_OTHERS:
566 return "Does not fit any class"; 569 return "Does not fit any class";
567 break; 570 break;
568 default: 571 default:
569 return "???"; 572 return "???";
570 break; 573 break;
571 }; 574 };
572 } 575 }
573 #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */ 576 #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
574 577
575 __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) 578 __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
576 { 579 {
577 /* 580 /*
578 * Check if pci device should be skipped in configuration 581 * Check if pci device should be skipped in configuration
579 */ 582 */
580 if (dev == PCI_BDF(hose->first_busno, 0, 0)) { 583 if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
581 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */ 584 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
582 /* 585 /*
583 * Only skip configuration if "pciconfighost" is not set 586 * Only skip configuration if "pciconfighost" is not set
584 */ 587 */
585 if (getenv("pciconfighost") == NULL) 588 if (getenv("pciconfighost") == NULL)
586 return 1; 589 return 1;
587 #else 590 #else
588 return 1; 591 return 1;
589 #endif 592 #endif
590 } 593 }
591 594
592 return 0; 595 return 0;
593 } 596 }
594 597
595 #ifdef CONFIG_PCI_SCAN_SHOW 598 #ifdef CONFIG_PCI_SCAN_SHOW
596 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) 599 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
597 { 600 {
598 if (dev == PCI_BDF(hose->first_busno, 0, 0)) 601 if (dev == PCI_BDF(hose->first_busno, 0, 0))
599 return 0; 602 return 0;
600 603
601 return 1; 604 return 1;
602 } 605 }
603 #endif /* CONFIG_PCI_SCAN_SHOW */ 606 #endif /* CONFIG_PCI_SCAN_SHOW */
604 607
605 int pci_hose_scan_bus(struct pci_controller *hose, int bus) 608 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
606 { 609 {
607 unsigned int sub_bus, found_multi = 0; 610 unsigned int sub_bus, found_multi = 0;
608 unsigned short vendor, device, class; 611 unsigned short vendor, device, class;
609 unsigned char header_type; 612 unsigned char header_type;
610 #ifndef CONFIG_PCI_PNP 613 #ifndef CONFIG_PCI_PNP
611 struct pci_config_table *cfg; 614 struct pci_config_table *cfg;
612 #endif 615 #endif
613 pci_dev_t dev; 616 pci_dev_t dev;
614 #ifdef CONFIG_PCI_SCAN_SHOW 617 #ifdef CONFIG_PCI_SCAN_SHOW
615 static int indent = 0; 618 static int indent = 0;
616 #endif 619 #endif
617 620
618 sub_bus = bus; 621 sub_bus = bus;
619 622
620 for (dev = PCI_BDF(bus,0,0); 623 for (dev = PCI_BDF(bus,0,0);
621 dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1, 624 dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
622 PCI_MAX_PCI_FUNCTIONS - 1); 625 PCI_MAX_PCI_FUNCTIONS - 1);
623 dev += PCI_BDF(0, 0, 1)) { 626 dev += PCI_BDF(0, 0, 1)) {
624 627
625 if (pci_skip_dev(hose, dev)) 628 if (pci_skip_dev(hose, dev))
626 continue; 629 continue;
627 630
628 if (PCI_FUNC(dev) && !found_multi) 631 if (PCI_FUNC(dev) && !found_multi)
629 continue; 632 continue;
630 633
631 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); 634 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
632 635
633 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor); 636 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
634 637
635 if (vendor == 0xffff || vendor == 0x0000) 638 if (vendor == 0xffff || vendor == 0x0000)
636 continue; 639 continue;
637 640
638 if (!PCI_FUNC(dev)) 641 if (!PCI_FUNC(dev))
639 found_multi = header_type & 0x80; 642 found_multi = header_type & 0x80;
640 643
641 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n", 644 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
642 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); 645 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
643 646
644 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device); 647 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
645 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); 648 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
646 649
647 #ifdef CONFIG_PCI_FIXUP_DEV 650 #ifdef CONFIG_PCI_FIXUP_DEV
648 board_pci_fixup_dev(hose, dev, vendor, device, class); 651 board_pci_fixup_dev(hose, dev, vendor, device, class);
649 #endif 652 #endif
650 653
651 #ifdef CONFIG_PCI_SCAN_SHOW 654 #ifdef CONFIG_PCI_SCAN_SHOW
652 indent++; 655 indent++;
653 656
654 /* Print leading space, including bus indentation */ 657 /* Print leading space, including bus indentation */
655 printf("%*c", indent + 1, ' '); 658 printf("%*c", indent + 1, ' ');
656 659
657 if (pci_print_dev(hose, dev)) { 660 if (pci_print_dev(hose, dev)) {
658 printf("%02x:%02x.%-*x - %04x:%04x - %s\n", 661 printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
659 PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev), 662 PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
660 vendor, device, pci_class_str(class >> 8)); 663 vendor, device, pci_class_str(class >> 8));
661 } 664 }
662 #endif 665 #endif
663 666
664 #ifdef CONFIG_PCI_PNP 667 #ifdef CONFIG_PCI_PNP
665 sub_bus = max((unsigned int)pciauto_config_device(hose, dev), 668 sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
666 sub_bus); 669 sub_bus);
667 #else 670 #else
668 cfg = pci_find_config(hose, class, vendor, device, 671 cfg = pci_find_config(hose, class, vendor, device,
669 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); 672 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
670 if (cfg) { 673 if (cfg) {
671 cfg->config_device(hose, dev, cfg); 674 cfg->config_device(hose, dev, cfg);
672 sub_bus = max(sub_bus, 675 sub_bus = max(sub_bus,
673 (unsigned int)hose->current_busno); 676 (unsigned int)hose->current_busno);
674 } 677 }
675 #endif 678 #endif
676 679
677 #ifdef CONFIG_PCI_SCAN_SHOW 680 #ifdef CONFIG_PCI_SCAN_SHOW
678 indent--; 681 indent--;
679 #endif 682 #endif
680 683
681 if (hose->fixup_irq) 684 if (hose->fixup_irq)
682 hose->fixup_irq(hose, dev); 685 hose->fixup_irq(hose, dev);
683 } 686 }
684 687
685 return sub_bus; 688 return sub_bus;
686 } 689 }
687 690
688 int pci_hose_scan(struct pci_controller *hose) 691 int pci_hose_scan(struct pci_controller *hose)
689 { 692 {
690 #if defined(CONFIG_PCI_BOOTDELAY) 693 #if defined(CONFIG_PCI_BOOTDELAY)
691 static int pcidelay_done; 694 static int pcidelay_done;
692 char *s; 695 char *s;
693 int i; 696 int i;
694 697
695 if (!pcidelay_done) { 698 if (!pcidelay_done) {
696 /* wait "pcidelay" ms (if defined)... */ 699 /* wait "pcidelay" ms (if defined)... */
697 s = getenv("pcidelay"); 700 s = getenv("pcidelay");
698 if (s) { 701 if (s) {
699 int val = simple_strtoul(s, NULL, 10); 702 int val = simple_strtoul(s, NULL, 10);
700 for (i = 0; i < val; i++) 703 for (i = 0; i < val; i++)
701 udelay(1000); 704 udelay(1000);
702 } 705 }
703 pcidelay_done = 1; 706 pcidelay_done = 1;
704 } 707 }
705 #endif /* CONFIG_PCI_BOOTDELAY */ 708 #endif /* CONFIG_PCI_BOOTDELAY */
706 709
707 /* 710 /*
708 * Start scan at current_busno. 711 * Start scan at current_busno.
709 * PCIe will start scan at first_busno+1. 712 * PCIe will start scan at first_busno+1.
710 */ 713 */
711 /* For legacy support, ensure current >= first */ 714 /* For legacy support, ensure current >= first */
712 if (hose->first_busno > hose->current_busno) 715 if (hose->first_busno > hose->current_busno)
713 hose->current_busno = hose->first_busno; 716 hose->current_busno = hose->first_busno;
714 #ifdef CONFIG_PCI_PNP 717 #ifdef CONFIG_PCI_PNP
715 pciauto_config_init(hose); 718 pciauto_config_init(hose);
716 #endif 719 #endif
717 return pci_hose_scan_bus(hose, hose->current_busno); 720 return pci_hose_scan_bus(hose, hose->current_busno);
718 } 721 }
719 722
720 void pci_init(void) 723 void pci_init(void)
721 { 724 {
722 hose_head = NULL; 725 hose_head = NULL;
723 726
724 /* now call board specific pci_init()... */ 727 /* now call board specific pci_init()... */
725 pci_init_board(); 728 pci_init_board();
726 } 729 }
727 730
728 /* Returns the address of the requested capability structure within the 731 /* Returns the address of the requested capability structure within the
729 * device's PCI configuration space or 0 in case the device does not 732 * device's PCI configuration space or 0 in case the device does not
730 * support it. 733 * support it.
731 * */ 734 * */
732 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, 735 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
733 int cap) 736 int cap)
734 { 737 {
735 int pos; 738 int pos;
736 u8 hdr_type; 739 u8 hdr_type;
737 740
738 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type); 741 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
739 742
740 pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F); 743 pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
741 744
742 if (pos) 745 if (pos)
743 pos = pci_find_cap(hose, dev, pos, cap); 746 pos = pci_find_cap(hose, dev, pos, cap);
744 747
745 return pos; 748 return pos;
746 } 749 }
747 750
748 /* Find the header pointer to the Capabilities*/ 751 /* Find the header pointer to the Capabilities*/
749 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, 752 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
750 u8 hdr_type) 753 u8 hdr_type)
751 { 754 {
752 u16 status; 755 u16 status;
753 756
754 pci_hose_read_config_word(hose, dev, PCI_STATUS, &status); 757 pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
755 758
756 if (!(status & PCI_STATUS_CAP_LIST)) 759 if (!(status & PCI_STATUS_CAP_LIST))
757 return 0; 760 return 0;
758 761
759 switch (hdr_type) { 762 switch (hdr_type) {
760 case PCI_HEADER_TYPE_NORMAL: 763 case PCI_HEADER_TYPE_NORMAL:
761 case PCI_HEADER_TYPE_BRIDGE: 764 case PCI_HEADER_TYPE_BRIDGE:
762 return PCI_CAPABILITY_LIST; 765 return PCI_CAPABILITY_LIST;
763 case PCI_HEADER_TYPE_CARDBUS: 766 case PCI_HEADER_TYPE_CARDBUS:
764 return PCI_CB_CAPABILITY_LIST; 767 return PCI_CB_CAPABILITY_LIST;
765 default: 768 default:
766 return 0; 769 return 0;
767 } 770 }
768 } 771 }
769 772
770 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap) 773 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
771 { 774 {
772 int ttl = PCI_FIND_CAP_TTL; 775 int ttl = PCI_FIND_CAP_TTL;
773 u8 id; 776 u8 id;
774 u8 next_pos; 777 u8 next_pos;
775 778
776 while (ttl--) { 779 while (ttl--) {
777 pci_hose_read_config_byte(hose, dev, pos, &next_pos); 780 pci_hose_read_config_byte(hose, dev, pos, &next_pos);
778 if (next_pos < CAP_START_POS) 781 if (next_pos < CAP_START_POS)
779 break; 782 break;
780 next_pos &= ~3; 783 next_pos &= ~3;
781 pos = (int) next_pos; 784 pos = (int) next_pos;
782 pci_hose_read_config_byte(hose, dev, 785 pci_hose_read_config_byte(hose, dev,
783 pos + PCI_CAP_LIST_ID, &id); 786 pos + PCI_CAP_LIST_ID, &id);
784 if (id == 0xff) 787 if (id == 0xff)
785 break; 788 break;
786 if (id == cap) 789 if (id == cap)
787 return pos; 790 return pos;
788 pos += PCI_CAP_LIST_NEXT; 791 pos += PCI_CAP_LIST_NEXT;
789 } 792 }
790 return 0; 793 return 0;
791 } 794 }
792 795
1 /* 1 /*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de> 3 * Andreas Heppel <aheppel@sysgo.de>
4 * 4 *
5 * (C) Copyright 2002 5 * (C) Copyright 2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * 7 *
8 * SPDX-License-Identifier: GPL-2.0+ 8 * SPDX-License-Identifier: GPL-2.0+
9 */ 9 */
10 10
11 #ifndef _PCI_H 11 #ifndef _PCI_H
12 #define _PCI_H 12 #define _PCI_H
13 13
14 /* 14 /*
15 * Under PCI, each device has 256 bytes of configuration address space, 15 * Under PCI, each device has 256 bytes of configuration address space,
16 * of which the first 64 bytes are standardized as follows: 16 * of which the first 64 bytes are standardized as follows:
17 */ 17 */
18 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 18 #define PCI_VENDOR_ID 0x00 /* 16 bits */
19 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 19 #define PCI_DEVICE_ID 0x02 /* 16 bits */
20 #define PCI_COMMAND 0x04 /* 16 bits */ 20 #define PCI_COMMAND 0x04 /* 16 bits */
21 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 21 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
22 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 22 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
23 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 23 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
24 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 24 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
25 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 25 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
26 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 26 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
27 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 27 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
28 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 28 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
29 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 29 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
30 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 30 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
31 31
32 #define PCI_STATUS 0x06 /* 16 bits */ 32 #define PCI_STATUS 0x06 /* 16 bits */
33 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 33 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
34 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 34 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
35 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 35 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
36 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 36 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
37 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 37 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
38 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 38 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
39 #define PCI_STATUS_DEVSEL_FAST 0x000 39 #define PCI_STATUS_DEVSEL_FAST 0x000
40 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 40 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
41 #define PCI_STATUS_DEVSEL_SLOW 0x400 41 #define PCI_STATUS_DEVSEL_SLOW 0x400
42 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 42 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
43 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 43 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
44 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 44 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
45 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 45 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
46 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 46 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
47 47
48 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 48 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
49 revision */ 49 revision */
50 #define PCI_REVISION_ID 0x08 /* Revision ID */ 50 #define PCI_REVISION_ID 0x08 /* Revision ID */
51 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 51 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
52 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 52 #define PCI_CLASS_DEVICE 0x0a /* Device class */
53 #define PCI_CLASS_CODE 0x0b /* Device class code */ 53 #define PCI_CLASS_CODE 0x0b /* Device class code */
54 #define PCI_CLASS_CODE_TOO_OLD 0x00 54 #define PCI_CLASS_CODE_TOO_OLD 0x00
55 #define PCI_CLASS_CODE_STORAGE 0x01 55 #define PCI_CLASS_CODE_STORAGE 0x01
56 #define PCI_CLASS_CODE_NETWORK 0x02 56 #define PCI_CLASS_CODE_NETWORK 0x02
57 #define PCI_CLASS_CODE_DISPLAY 0x03 57 #define PCI_CLASS_CODE_DISPLAY 0x03
58 #define PCI_CLASS_CODE_MULTIMEDIA 0x04 58 #define PCI_CLASS_CODE_MULTIMEDIA 0x04
59 #define PCI_CLASS_CODE_MEMORY 0x05 59 #define PCI_CLASS_CODE_MEMORY 0x05
60 #define PCI_CLASS_CODE_BRIDGE 0x06 60 #define PCI_CLASS_CODE_BRIDGE 0x06
61 #define PCI_CLASS_CODE_COMM 0x07 61 #define PCI_CLASS_CODE_COMM 0x07
62 #define PCI_CLASS_CODE_PERIPHERAL 0x08 62 #define PCI_CLASS_CODE_PERIPHERAL 0x08
63 #define PCI_CLASS_CODE_INPUT 0x09 63 #define PCI_CLASS_CODE_INPUT 0x09
64 #define PCI_CLASS_CODE_DOCKING 0x0A 64 #define PCI_CLASS_CODE_DOCKING 0x0A
65 #define PCI_CLASS_CODE_PROCESSOR 0x0B 65 #define PCI_CLASS_CODE_PROCESSOR 0x0B
66 #define PCI_CLASS_CODE_SERIAL 0x0C 66 #define PCI_CLASS_CODE_SERIAL 0x0C
67 #define PCI_CLASS_CODE_WIRELESS 0x0D 67 #define PCI_CLASS_CODE_WIRELESS 0x0D
68 #define PCI_CLASS_CODE_I2O 0x0E 68 #define PCI_CLASS_CODE_I2O 0x0E
69 #define PCI_CLASS_CODE_SATELLITE 0x0F 69 #define PCI_CLASS_CODE_SATELLITE 0x0F
70 #define PCI_CLASS_CODE_CRYPTO 0x10 70 #define PCI_CLASS_CODE_CRYPTO 0x10
71 #define PCI_CLASS_CODE_DATA 0x11 71 #define PCI_CLASS_CODE_DATA 0x11
72 /* Base Class 0x12 - 0xFE is reserved */ 72 /* Base Class 0x12 - 0xFE is reserved */
73 #define PCI_CLASS_CODE_OTHER 0xFF 73 #define PCI_CLASS_CODE_OTHER 0xFF
74 74
75 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */ 75 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
76 #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00 76 #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00
77 #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01 77 #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01
78 #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00 78 #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00
79 #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01 79 #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01
80 #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02 80 #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02
81 #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03 81 #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03
82 #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04 82 #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04
83 #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05 83 #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05
84 #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06 84 #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06
85 #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07 85 #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07
86 #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80 86 #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80
87 #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00 87 #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00
88 #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01 88 #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01
89 #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02 89 #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02
90 #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03 90 #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03
91 #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04 91 #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04
92 #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05 92 #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05
93 #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06 93 #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06
94 #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80 94 #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80
95 #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00 95 #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00
96 #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01 96 #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01
97 #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02 97 #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02
98 #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80 98 #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80
99 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00 99 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00
100 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01 100 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01
101 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02 101 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02
102 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80 102 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80
103 #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00 103 #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00
104 #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01 104 #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01
105 #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80 105 #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80
106 #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00 106 #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00
107 #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01 107 #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01
108 #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02 108 #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02
109 #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03 109 #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03
110 #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04 110 #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04
111 #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05 111 #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05
112 #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06 112 #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06
113 #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07 113 #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07
114 #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08 114 #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08
115 #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09 115 #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09
116 #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A 116 #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A
117 #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80 117 #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80
118 #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00 118 #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00
119 #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01 119 #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01
120 #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02 120 #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02
121 #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03 121 #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03
122 #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04 122 #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04
123 #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05 123 #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05
124 #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80 124 #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80
125 #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00 125 #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00
126 #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01 126 #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01
127 #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02 127 #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02
128 #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03 128 #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03
129 #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04 129 #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04
130 #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05 130 #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05
131 #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80 131 #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80
132 #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00 132 #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00
133 #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01 133 #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01
134 #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02 134 #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02
135 #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03 135 #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03
136 #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04 136 #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04
137 #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80 137 #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80
138 #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00 138 #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00
139 #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80 139 #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80
140 #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00 140 #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00
141 #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01 141 #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01
142 #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02 142 #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02
143 #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10 143 #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10
144 #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20 144 #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20
145 #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30 145 #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30
146 #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40 146 #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40
147 #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00 147 #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00
148 #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01 148 #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01
149 #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02 149 #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02
150 #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03 150 #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03
151 #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04 151 #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04
152 #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05 152 #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05
153 #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06 153 #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06
154 #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07 154 #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07
155 #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08 155 #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08
156 #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09 156 #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09
157 #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00 157 #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00
158 #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01 158 #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01
159 #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10 159 #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10
160 #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11 160 #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11
161 #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12 161 #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12
162 #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20 162 #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20
163 #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21 163 #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21
164 #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80 164 #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80
165 #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00 165 #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00
166 #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01 166 #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01
167 #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02 167 #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02
168 #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03 168 #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03
169 #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04 169 #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04
170 #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00 170 #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00
171 #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10 171 #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
172 #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80 172 #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80
173 #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00 173 #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00
174 #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01 174 #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01
175 #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10 175 #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10
176 #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20 176 #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20
177 #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80 177 #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80
178 178
179 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 179 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
180 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 180 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
181 #define PCI_HEADER_TYPE 0x0e /* 8 bits */ 181 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
182 #define PCI_HEADER_TYPE_NORMAL 0 182 #define PCI_HEADER_TYPE_NORMAL 0
183 #define PCI_HEADER_TYPE_BRIDGE 1 183 #define PCI_HEADER_TYPE_BRIDGE 1
184 #define PCI_HEADER_TYPE_CARDBUS 2 184 #define PCI_HEADER_TYPE_CARDBUS 2
185 185
186 #define PCI_BIST 0x0f /* 8 bits */ 186 #define PCI_BIST 0x0f /* 8 bits */
187 #define PCI_BIST_CODE_MASK 0x0f /* Return result */ 187 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
188 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 188 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
189 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 189 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
190 190
191 /* 191 /*
192 * Base addresses specify locations in memory or I/O space. 192 * Base addresses specify locations in memory or I/O space.
193 * Decoded size can be determined by writing a value of 193 * Decoded size can be determined by writing a value of
194 * 0xffffffff to the register, and reading it back. Only 194 * 0xffffffff to the register, and reading it back. Only
195 * 1 bits are decoded. 195 * 1 bits are decoded.
196 */ 196 */
197 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 197 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
198 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 198 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
199 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 199 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
200 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 200 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
201 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 201 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
202 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 202 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
203 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 203 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
204 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 204 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
205 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 205 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
206 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 206 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
207 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 207 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
208 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 208 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
209 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 209 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
210 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 210 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
211 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL) 211 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
212 #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL) 212 #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
213 /* bit 1 is reserved if address_space = 1 */ 213 /* bit 1 is reserved if address_space = 1 */
214 214
215 /* Header type 0 (normal devices) */ 215 /* Header type 0 (normal devices) */
216 #define PCI_CARDBUS_CIS 0x28 216 #define PCI_CARDBUS_CIS 0x28
217 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 217 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
218 #define PCI_SUBSYSTEM_ID 0x2e 218 #define PCI_SUBSYSTEM_ID 0x2e
219 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 219 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
220 #define PCI_ROM_ADDRESS_ENABLE 0x01 220 #define PCI_ROM_ADDRESS_ENABLE 0x01
221 #define PCI_ROM_ADDRESS_MASK (~0x7ffULL) 221 #define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
222 222
223 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 223 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
224 224
225 /* 0x35-0x3b are reserved */ 225 /* 0x35-0x3b are reserved */
226 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 226 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
227 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 227 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
228 #define PCI_MIN_GNT 0x3e /* 8 bits */ 228 #define PCI_MIN_GNT 0x3e /* 8 bits */
229 #define PCI_MAX_LAT 0x3f /* 8 bits */ 229 #define PCI_MAX_LAT 0x3f /* 8 bits */
230 230
231 /* Header type 1 (PCI-to-PCI bridges) */ 231 /* Header type 1 (PCI-to-PCI bridges) */
232 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 232 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
233 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 233 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
234 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 234 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
235 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 235 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
236 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 236 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
237 #define PCI_IO_LIMIT 0x1d 237 #define PCI_IO_LIMIT 0x1d
238 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ 238 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
239 #define PCI_IO_RANGE_TYPE_16 0x00 239 #define PCI_IO_RANGE_TYPE_16 0x00
240 #define PCI_IO_RANGE_TYPE_32 0x01 240 #define PCI_IO_RANGE_TYPE_32 0x01
241 #define PCI_IO_RANGE_MASK ~0x0f 241 #define PCI_IO_RANGE_MASK ~0x0f
242 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 242 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
243 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 243 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
244 #define PCI_MEMORY_LIMIT 0x22 244 #define PCI_MEMORY_LIMIT 0x22
245 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f 245 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
246 #define PCI_MEMORY_RANGE_MASK ~0x0f 246 #define PCI_MEMORY_RANGE_MASK ~0x0f
247 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 247 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
248 #define PCI_PREF_MEMORY_LIMIT 0x26 248 #define PCI_PREF_MEMORY_LIMIT 0x26
249 #define PCI_PREF_RANGE_TYPE_MASK 0x0f 249 #define PCI_PREF_RANGE_TYPE_MASK 0x0f
250 #define PCI_PREF_RANGE_TYPE_32 0x00 250 #define PCI_PREF_RANGE_TYPE_32 0x00
251 #define PCI_PREF_RANGE_TYPE_64 0x01 251 #define PCI_PREF_RANGE_TYPE_64 0x01
252 #define PCI_PREF_RANGE_MASK ~0x0f 252 #define PCI_PREF_RANGE_MASK ~0x0f
253 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 253 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
254 #define PCI_PREF_LIMIT_UPPER32 0x2c 254 #define PCI_PREF_LIMIT_UPPER32 0x2c
255 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 255 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
256 #define PCI_IO_LIMIT_UPPER16 0x32 256 #define PCI_IO_LIMIT_UPPER16 0x32
257 /* 0x34 same as for htype 0 */ 257 /* 0x34 same as for htype 0 */
258 /* 0x35-0x3b is reserved */ 258 /* 0x35-0x3b is reserved */
259 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 259 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
260 /* 0x3c-0x3d are same as for htype 0 */ 260 /* 0x3c-0x3d are same as for htype 0 */
261 #define PCI_BRIDGE_CONTROL 0x3e 261 #define PCI_BRIDGE_CONTROL 0x3e
262 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 262 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
263 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 263 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
264 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 264 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
265 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 265 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
266 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 266 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
267 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 267 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
268 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 268 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
269 269
270 /* From 440ep */ 270 /* From 440ep */
271 #define PCI_ERREN 0x48 /* Error Enable */ 271 #define PCI_ERREN 0x48 /* Error Enable */
272 #define PCI_ERRSTS 0x49 /* Error Status */ 272 #define PCI_ERRSTS 0x49 /* Error Status */
273 #define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */ 273 #define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */
274 #define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */ 274 #define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */
275 #define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */ 275 #define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */
276 #define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */ 276 #define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */
277 #define PCI_CAPID 0x58 /* Capability Identifier */ 277 #define PCI_CAPID 0x58 /* Capability Identifier */
278 #define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */ 278 #define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */
279 #define PCI_PMC 0x5A /* Power Management Capabilities */ 279 #define PCI_PMC 0x5A /* Power Management Capabilities */
280 #define PCI_PMCSR 0x5C /* Power Management Control Status */ 280 #define PCI_PMCSR 0x5C /* Power Management Control Status */
281 #define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */ 281 #define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */
282 #define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */ 282 #define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */
283 #define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */ 283 #define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */
284 284
285 /* Header type 2 (CardBus bridges) */ 285 /* Header type 2 (CardBus bridges) */
286 #define PCI_CB_CAPABILITY_LIST 0x14 286 #define PCI_CB_CAPABILITY_LIST 0x14
287 /* 0x15 reserved */ 287 /* 0x15 reserved */
288 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 288 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
289 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 289 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
290 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 290 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
291 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 291 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
292 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 292 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
293 #define PCI_CB_MEMORY_BASE_0 0x1c 293 #define PCI_CB_MEMORY_BASE_0 0x1c
294 #define PCI_CB_MEMORY_LIMIT_0 0x20 294 #define PCI_CB_MEMORY_LIMIT_0 0x20
295 #define PCI_CB_MEMORY_BASE_1 0x24 295 #define PCI_CB_MEMORY_BASE_1 0x24
296 #define PCI_CB_MEMORY_LIMIT_1 0x28 296 #define PCI_CB_MEMORY_LIMIT_1 0x28
297 #define PCI_CB_IO_BASE_0 0x2c 297 #define PCI_CB_IO_BASE_0 0x2c
298 #define PCI_CB_IO_BASE_0_HI 0x2e 298 #define PCI_CB_IO_BASE_0_HI 0x2e
299 #define PCI_CB_IO_LIMIT_0 0x30 299 #define PCI_CB_IO_LIMIT_0 0x30
300 #define PCI_CB_IO_LIMIT_0_HI 0x32 300 #define PCI_CB_IO_LIMIT_0_HI 0x32
301 #define PCI_CB_IO_BASE_1 0x34 301 #define PCI_CB_IO_BASE_1 0x34
302 #define PCI_CB_IO_BASE_1_HI 0x36 302 #define PCI_CB_IO_BASE_1_HI 0x36
303 #define PCI_CB_IO_LIMIT_1 0x38 303 #define PCI_CB_IO_LIMIT_1 0x38
304 #define PCI_CB_IO_LIMIT_1_HI 0x3a 304 #define PCI_CB_IO_LIMIT_1_HI 0x3a
305 #define PCI_CB_IO_RANGE_MASK ~0x03 305 #define PCI_CB_IO_RANGE_MASK ~0x03
306 /* 0x3c-0x3d are same as for htype 0 */ 306 /* 0x3c-0x3d are same as for htype 0 */
307 #define PCI_CB_BRIDGE_CONTROL 0x3e 307 #define PCI_CB_BRIDGE_CONTROL 0x3e
308 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 308 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
309 #define PCI_CB_BRIDGE_CTL_SERR 0x02 309 #define PCI_CB_BRIDGE_CTL_SERR 0x02
310 #define PCI_CB_BRIDGE_CTL_ISA 0x04 310 #define PCI_CB_BRIDGE_CTL_ISA 0x04
311 #define PCI_CB_BRIDGE_CTL_VGA 0x08 311 #define PCI_CB_BRIDGE_CTL_VGA 0x08
312 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 312 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
313 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 313 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
314 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 314 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
315 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 315 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
316 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 316 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
317 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 317 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
318 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 318 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
319 #define PCI_CB_SUBSYSTEM_ID 0x42 319 #define PCI_CB_SUBSYSTEM_ID 0x42
320 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 320 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
321 /* 0x48-0x7f reserved */ 321 /* 0x48-0x7f reserved */
322 322
323 /* Capability lists */ 323 /* Capability lists */
324 324
325 #define PCI_CAP_LIST_ID 0 /* Capability ID */ 325 #define PCI_CAP_LIST_ID 0 /* Capability ID */
326 #define PCI_CAP_ID_PM 0x01 /* Power Management */ 326 #define PCI_CAP_ID_PM 0x01 /* Power Management */
327 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 327 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
328 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 328 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
329 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 329 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
330 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 330 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
331 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 331 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
332 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 332 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
333 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 333 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
334 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 334 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
335 #define PCI_CAP_SIZEOF 4 335 #define PCI_CAP_SIZEOF 4
336 336
337 /* Power Management Registers */ 337 /* Power Management Registers */
338 338
339 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 339 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
340 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 340 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
341 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ 341 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
342 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 342 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
343 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 343 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
344 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 344 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
345 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 345 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
346 #define PCI_PM_CTRL 4 /* PM control and status register */ 346 #define PCI_PM_CTRL 4 /* PM control and status register */
347 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 347 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
348 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 348 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
349 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 349 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
350 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 350 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
351 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 351 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
352 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 352 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
353 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 353 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
354 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 354 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
355 #define PCI_PM_DATA_REGISTER 7 /* (??) */ 355 #define PCI_PM_DATA_REGISTER 7 /* (??) */
356 #define PCI_PM_SIZEOF 8 356 #define PCI_PM_SIZEOF 8
357 357
358 /* AGP registers */ 358 /* AGP registers */
359 359
360 #define PCI_AGP_VERSION 2 /* BCD version number */ 360 #define PCI_AGP_VERSION 2 /* BCD version number */
361 #define PCI_AGP_RFU 3 /* Rest of capability flags */ 361 #define PCI_AGP_RFU 3 /* Rest of capability flags */
362 #define PCI_AGP_STATUS 4 /* Status register */ 362 #define PCI_AGP_STATUS 4 /* Status register */
363 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 363 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
364 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 364 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
365 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 365 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
366 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 366 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
367 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 367 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
368 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 368 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
369 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 369 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
370 #define PCI_AGP_COMMAND 8 /* Control register */ 370 #define PCI_AGP_COMMAND 8 /* Control register */
371 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 371 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
372 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 372 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
373 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 373 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
374 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 374 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
375 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 375 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
376 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 376 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
377 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ 377 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
378 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ 378 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
379 #define PCI_AGP_SIZEOF 12 379 #define PCI_AGP_SIZEOF 12
380 380
381 /* PCI-X registers */ 381 /* PCI-X registers */
382 382
383 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ 383 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
384 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ 384 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
385 #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ 385 #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
386 #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ 386 #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
387 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 387 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
388 388
389 389
390 /* Slot Identification */ 390 /* Slot Identification */
391 391
392 #define PCI_SID_ESR 2 /* Expansion Slot Register */ 392 #define PCI_SID_ESR 2 /* Expansion Slot Register */
393 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 393 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
394 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 394 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
395 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 395 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
396 396
397 /* Message Signalled Interrupts registers */ 397 /* Message Signalled Interrupts registers */
398 398
399 #define PCI_MSI_FLAGS 2 /* Various flags */ 399 #define PCI_MSI_FLAGS 2 /* Various flags */
400 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ 400 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
401 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ 401 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
402 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ 402 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
403 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ 403 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
404 #define PCI_MSI_RFU 3 /* Rest of capability flags */ 404 #define PCI_MSI_RFU 3 /* Rest of capability flags */
405 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 405 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
406 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 406 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
407 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 407 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
408 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 408 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
409 409
410 #define PCI_MAX_PCI_DEVICES 32 410 #define PCI_MAX_PCI_DEVICES 32
411 #define PCI_MAX_PCI_FUNCTIONS 8 411 #define PCI_MAX_PCI_FUNCTIONS 8
412 412
413 #define PCI_FIND_CAP_TTL 0x48 413 #define PCI_FIND_CAP_TTL 0x48
414 #define CAP_START_POS 0x40 414 #define CAP_START_POS 0x40
415 415
416 /* Include the ID list */ 416 /* Include the ID list */
417 417
418 #include <pci_ids.h> 418 #include <pci_ids.h>
419 419
420 #ifndef __ASSEMBLY__ 420 #ifndef __ASSEMBLY__
421 421
422 #ifdef CONFIG_SYS_PCI_64BIT 422 #ifdef CONFIG_SYS_PCI_64BIT
423 typedef u64 pci_addr_t; 423 typedef u64 pci_addr_t;
424 typedef u64 pci_size_t; 424 typedef u64 pci_size_t;
425 #else 425 #else
426 typedef u32 pci_addr_t; 426 typedef u32 pci_addr_t;
427 typedef u32 pci_size_t; 427 typedef u32 pci_size_t;
428 #endif 428 #endif
429 429
430 struct pci_region { 430 struct pci_region {
431 pci_addr_t bus_start; /* Start on the bus */ 431 pci_addr_t bus_start; /* Start on the bus */
432 phys_addr_t phys_start; /* Start in physical address space */ 432 phys_addr_t phys_start; /* Start in physical address space */
433 pci_size_t size; /* Size */ 433 pci_size_t size; /* Size */
434 unsigned long flags; /* Resource flags */ 434 unsigned long flags; /* Resource flags */
435 435
436 pci_addr_t bus_lower; 436 pci_addr_t bus_lower;
437 }; 437 };
438 438
439 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */ 439 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */
440 #define PCI_REGION_IO 0x00000001 /* PCI IO space */ 440 #define PCI_REGION_IO 0x00000001 /* PCI IO space */
441 #define PCI_REGION_TYPE 0x00000001 441 #define PCI_REGION_TYPE 0x00000001
442 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */ 442 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
443 443
444 #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */ 444 #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */
445 #define PCI_REGION_RO 0x00000200 /* Read-only memory */ 445 #define PCI_REGION_RO 0x00000200 /* Read-only memory */
446 446
447 static inline void pci_set_region(struct pci_region *reg, 447 static inline void pci_set_region(struct pci_region *reg,
448 pci_addr_t bus_start, 448 pci_addr_t bus_start,
449 phys_addr_t phys_start, 449 phys_addr_t phys_start,
450 pci_size_t size, 450 pci_size_t size,
451 unsigned long flags) { 451 unsigned long flags) {
452 reg->bus_start = bus_start; 452 reg->bus_start = bus_start;
453 reg->phys_start = phys_start; 453 reg->phys_start = phys_start;
454 reg->size = size; 454 reg->size = size;
455 reg->flags = flags; 455 reg->flags = flags;
456 } 456 }
457 457
458 typedef int pci_dev_t; 458 typedef int pci_dev_t;
459 459
460 #define PCI_BUS(d) (((d) >> 16) & 0xff) 460 #define PCI_BUS(d) (((d) >> 16) & 0xff)
461 #define PCI_DEV(d) (((d) >> 11) & 0x1f) 461 #define PCI_DEV(d) (((d) >> 11) & 0x1f)
462 #define PCI_FUNC(d) (((d) >> 8) & 0x7) 462 #define PCI_FUNC(d) (((d) >> 8) & 0x7)
463 #define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8) 463 #define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8)
464 464
465 #define PCI_ANY_ID (~0) 465 #define PCI_ANY_ID (~0)
466 466
467 struct pci_device_id { 467 struct pci_device_id {
468 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 468 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
469 }; 469 };
470 470
471 struct pci_controller; 471 struct pci_controller;
472 472
473 struct pci_config_table { 473 struct pci_config_table {
474 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 474 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
475 unsigned int class; /* Class ID, or PCI_ANY_ID */ 475 unsigned int class; /* Class ID, or PCI_ANY_ID */
476 unsigned int bus; /* Bus number, or PCI_ANY_ID */ 476 unsigned int bus; /* Bus number, or PCI_ANY_ID */
477 unsigned int dev; /* Device number, or PCI_ANY_ID */ 477 unsigned int dev; /* Device number, or PCI_ANY_ID */
478 unsigned int func; /* Function number, or PCI_ANY_ID */ 478 unsigned int func; /* Function number, or PCI_ANY_ID */
479 479
480 void (*config_device)(struct pci_controller* hose, pci_dev_t dev, 480 void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
481 struct pci_config_table *); 481 struct pci_config_table *);
482 unsigned long priv[3]; 482 unsigned long priv[3];
483 }; 483 };
484 484
485 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, 485 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
486 struct pci_config_table *); 486 struct pci_config_table *);
487 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, 487 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
488 struct pci_config_table *); 488 struct pci_config_table *);
489 489
490 #define MAX_PCI_REGIONS 7 490 #define MAX_PCI_REGIONS 7
491 491
492 #define INDIRECT_TYPE_NO_PCIE_LINK 1 492 #define INDIRECT_TYPE_NO_PCIE_LINK 1
493 493
494 /* 494 /*
495 * Structure of a PCI controller (host bridge) 495 * Structure of a PCI controller (host bridge)
496 */ 496 */
497 struct pci_controller { 497 struct pci_controller {
498 struct pci_controller *next; 498 struct pci_controller *next;
499 499
500 int first_busno; 500 int first_busno;
501 int last_busno; 501 int last_busno;
502 502
503 volatile unsigned int *cfg_addr; 503 volatile unsigned int *cfg_addr;
504 volatile unsigned char *cfg_data; 504 volatile unsigned char *cfg_data;
505 505
506 int indirect_type; 506 int indirect_type;
507 507
508 struct pci_region regions[MAX_PCI_REGIONS]; 508 struct pci_region regions[MAX_PCI_REGIONS];
509 int region_count; 509 int region_count;
510 510
511 struct pci_config_table *config_table; 511 struct pci_config_table *config_table;
512 512
513 void (*fixup_irq)(struct pci_controller *, pci_dev_t); 513 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
514 514
515 /* Low-level architecture-dependent routines */ 515 /* Low-level architecture-dependent routines */
516 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *); 516 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
517 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *); 517 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
518 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *); 518 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
519 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8); 519 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
520 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16); 520 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
521 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); 521 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
522 522
523 /* Used by auto config */ 523 /* Used by auto config */
524 struct pci_region *pci_mem, *pci_io, *pci_prefetch; 524 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
525 525
526 /* Used by ppc405 autoconfig*/ 526 /* Used by ppc405 autoconfig*/
527 struct pci_region *pci_fb; 527 struct pci_region *pci_fb;
528 int current_busno; 528 int current_busno;
529 529
530 void *priv_data; 530 void *priv_data;
531 }; 531 };
532 532
533 static inline void pci_set_ops(struct pci_controller *hose, 533 static inline void pci_set_ops(struct pci_controller *hose,
534 int (*read_byte)(struct pci_controller*, 534 int (*read_byte)(struct pci_controller*,
535 pci_dev_t, int where, u8 *), 535 pci_dev_t, int where, u8 *),
536 int (*read_word)(struct pci_controller*, 536 int (*read_word)(struct pci_controller*,
537 pci_dev_t, int where, u16 *), 537 pci_dev_t, int where, u16 *),
538 int (*read_dword)(struct pci_controller*, 538 int (*read_dword)(struct pci_controller*,
539 pci_dev_t, int where, u32 *), 539 pci_dev_t, int where, u32 *),
540 int (*write_byte)(struct pci_controller*, 540 int (*write_byte)(struct pci_controller*,
541 pci_dev_t, int where, u8), 541 pci_dev_t, int where, u8),
542 int (*write_word)(struct pci_controller*, 542 int (*write_word)(struct pci_controller*,
543 pci_dev_t, int where, u16), 543 pci_dev_t, int where, u16),
544 int (*write_dword)(struct pci_controller*, 544 int (*write_dword)(struct pci_controller*,
545 pci_dev_t, int where, u32)) { 545 pci_dev_t, int where, u32)) {
546 hose->read_byte = read_byte; 546 hose->read_byte = read_byte;
547 hose->read_word = read_word; 547 hose->read_word = read_word;
548 hose->read_dword = read_dword; 548 hose->read_dword = read_dword;
549 hose->write_byte = write_byte; 549 hose->write_byte = write_byte;
550 hose->write_word = write_word; 550 hose->write_word = write_word;
551 hose->write_dword = write_dword; 551 hose->write_dword = write_dword;
552 } 552 }
553 553
554 #ifdef CONFIG_PCI_INDIRECT_BRIDGE 554 #ifdef CONFIG_PCI_INDIRECT_BRIDGE
555 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); 555 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
556 #endif 556 #endif
557 557
558 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, 558 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
559 pci_addr_t addr, unsigned long flags); 559 pci_addr_t addr, unsigned long flags);
560 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, 560 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
561 phys_addr_t addr, unsigned long flags); 561 phys_addr_t addr, unsigned long flags);
562 562
563 #define pci_phys_to_bus(dev, addr, flags) \ 563 #define pci_phys_to_bus(dev, addr, flags) \
564 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 564 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
565 #define pci_bus_to_phys(dev, addr, flags) \ 565 #define pci_bus_to_phys(dev, addr, flags) \
566 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 566 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
567 567
568 #define pci_virt_to_bus(dev, addr, flags) \ 568 #define pci_virt_to_bus(dev, addr, flags) \
569 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \ 569 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
570 (virt_to_phys(addr)), (flags)) 570 (virt_to_phys(addr)), (flags))
571 #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 571 #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
572 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \ 572 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
573 (addr), (flags)), \ 573 (addr), (flags)), \
574 (len), (map_flags)) 574 (len), (map_flags))
575 575
576 #define pci_phys_to_mem(dev, addr) \ 576 #define pci_phys_to_mem(dev, addr) \
577 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 577 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
578 #define pci_mem_to_phys(dev, addr) \ 578 #define pci_mem_to_phys(dev, addr) \
579 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 579 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
580 #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 580 #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
581 #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 581 #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
582 582
583 #define pci_virt_to_mem(dev, addr) \ 583 #define pci_virt_to_mem(dev, addr) \
584 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 584 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
585 #define pci_mem_to_virt(dev, addr, len, map_flags) \ 585 #define pci_mem_to_virt(dev, addr, len, map_flags) \
586 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 586 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
587 #define pci_virt_to_io(dev, addr) \ 587 #define pci_virt_to_io(dev, addr) \
588 pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 588 pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
589 #define pci_io_to_virt(dev, addr, len, map_flags) \ 589 #define pci_io_to_virt(dev, addr, len, map_flags) \
590 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 590 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
591 591
592 extern int pci_hose_read_config_byte(struct pci_controller *hose, 592 extern int pci_hose_read_config_byte(struct pci_controller *hose,
593 pci_dev_t dev, int where, u8 *val); 593 pci_dev_t dev, int where, u8 *val);
594 extern int pci_hose_read_config_word(struct pci_controller *hose, 594 extern int pci_hose_read_config_word(struct pci_controller *hose,
595 pci_dev_t dev, int where, u16 *val); 595 pci_dev_t dev, int where, u16 *val);
596 extern int pci_hose_read_config_dword(struct pci_controller *hose, 596 extern int pci_hose_read_config_dword(struct pci_controller *hose,
597 pci_dev_t dev, int where, u32 *val); 597 pci_dev_t dev, int where, u32 *val);
598 extern int pci_hose_write_config_byte(struct pci_controller *hose, 598 extern int pci_hose_write_config_byte(struct pci_controller *hose,
599 pci_dev_t dev, int where, u8 val); 599 pci_dev_t dev, int where, u8 val);
600 extern int pci_hose_write_config_word(struct pci_controller *hose, 600 extern int pci_hose_write_config_word(struct pci_controller *hose,
601 pci_dev_t dev, int where, u16 val); 601 pci_dev_t dev, int where, u16 val);
602 extern int pci_hose_write_config_dword(struct pci_controller *hose, 602 extern int pci_hose_write_config_dword(struct pci_controller *hose,
603 pci_dev_t dev, int where, u32 val); 603 pci_dev_t dev, int where, u32 val);
604 604
605 extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); 605 extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
606 extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val); 606 extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
607 extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val); 607 extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
608 extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val); 608 extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
609 extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); 609 extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
610 extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); 610 extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
611 611
612 extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, 612 extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
613 pci_dev_t dev, int where, u8 *val); 613 pci_dev_t dev, int where, u8 *val);
614 extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, 614 extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
615 pci_dev_t dev, int where, u16 *val); 615 pci_dev_t dev, int where, u16 *val);
616 extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose, 616 extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
617 pci_dev_t dev, int where, u8 val); 617 pci_dev_t dev, int where, u8 val);
618 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, 618 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
619 pci_dev_t dev, int where, u16 val); 619 pci_dev_t dev, int where, u16 val);
620 620
621 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); 621 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
622 extern void pci_register_hose(struct pci_controller* hose); 622 extern void pci_register_hose(struct pci_controller* hose);
623 extern struct pci_controller* pci_bus_to_hose(int bus); 623 extern struct pci_controller* pci_bus_to_hose(int bus);
624 extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); 624 extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
625 625
626 extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
626 extern int pci_hose_scan(struct pci_controller *hose); 627 extern int pci_hose_scan(struct pci_controller *hose);
627 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); 628 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
628 629
629 extern void pciauto_region_init(struct pci_region* res); 630 extern void pciauto_region_init(struct pci_region* res);
630 extern void pciauto_region_align(struct pci_region *res, pci_size_t size); 631 extern void pciauto_region_align(struct pci_region *res, pci_size_t size);
631 extern int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar); 632 extern int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar);
632 extern void pciauto_setup_device(struct pci_controller *hose, 633 extern void pciauto_setup_device(struct pci_controller *hose,
633 pci_dev_t dev, int bars_num, 634 pci_dev_t dev, int bars_num,
634 struct pci_region *mem, 635 struct pci_region *mem,
635 struct pci_region *prefetch, 636 struct pci_region *prefetch,
636 struct pci_region *io); 637 struct pci_region *io);
637 extern void pciauto_prescan_setup_bridge(struct pci_controller *hose, 638 extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
638 pci_dev_t dev, int sub_bus); 639 pci_dev_t dev, int sub_bus);
639 extern void pciauto_postscan_setup_bridge(struct pci_controller *hose, 640 extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
640 pci_dev_t dev, int sub_bus); 641 pci_dev_t dev, int sub_bus);
641 extern void pciauto_config_init(struct pci_controller *hose); 642 extern void pciauto_config_init(struct pci_controller *hose);
642 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 643 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
643 644
644 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); 645 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
645 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); 646 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
646 extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code, 647 extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
647 int wanted_prog_if, int index); 648 int wanted_prog_if, int index);
648 649
649 extern int pci_hose_config_device(struct pci_controller *hose, 650 extern int pci_hose_config_device(struct pci_controller *hose,
650 pci_dev_t dev, 651 pci_dev_t dev,
651 unsigned long io, 652 unsigned long io,
652 pci_addr_t mem, 653 pci_addr_t mem,
653 unsigned long command); 654 unsigned long command);
654 655
655 extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, 656 extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
656 int cap); 657 int cap);
657 extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, 658 extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
658 u8 hdr_type); 659 u8 hdr_type);
659 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, 660 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
660 int cap); 661 int cap);
661 662
662 #ifdef CONFIG_PCI_FIXUP_DEV 663 #ifdef CONFIG_PCI_FIXUP_DEV
663 extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, 664 extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
664 unsigned short vendor, 665 unsigned short vendor,
665 unsigned short device, 666 unsigned short device,
666 unsigned short class); 667 unsigned short class);
667 #endif 668 #endif
668 669
669 const char * pci_class_str(u8 class); 670 const char * pci_class_str(u8 class);
670 int pci_last_busno(void); 671 int pci_last_busno(void);
671 672
672 #ifdef CONFIG_MPC824X 673 #ifdef CONFIG_MPC824X
673 extern void pci_mpc824x_init (struct pci_controller *hose); 674 extern void pci_mpc824x_init (struct pci_controller *hose);
674 #endif 675 #endif
675 676
676 #ifdef CONFIG_MPC85xx 677 #ifdef CONFIG_MPC85xx
677 extern void pci_mpc85xx_init (struct pci_controller *hose); 678 extern void pci_mpc85xx_init (struct pci_controller *hose);
678 #endif 679 #endif
679 680
680 #endif /* __ASSEMBLY__ */ 681 #endif /* __ASSEMBLY__ */
681 #endif /* _PCI_H */ 682 #endif /* _PCI_H */
682 683