Eric Lee / smarc-uboot

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Commit 53644801c560db5f7f98e7ef9a0c7a6ad559375f

Authored by Eric Lee
1 parent cb67adbef5
Exists in smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga and in 1 other branch smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga

Fix Ethernet PHY address

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

arch/arm/dts/fsl-smarcimx8mq.dts
Diff comments   View file @ 5364480
1 /* 1 /*
2 * Copyright (C) 2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 * 4 *
5 * This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2 7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version. 8 * of the License, or (at your option) any later version.
9 * 9 *
10 * This program is distributed in the hope that it will be useful, 10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 15
16 /dts-v1/; 16 /dts-v1/;
17 17
18 /* First 128KB is for PSCI ATF. */ 18 /* First 128KB is for PSCI ATF. */
19 /memreserve/ 0x40000000 0x00020000; 19 /memreserve/ 0x40000000 0x00020000;
20 20
21 #include "fsl-imx8mq.dtsi" 21 #include "fsl-imx8mq.dtsi"
22 22
23 / { 23 / {
24 model = "Embedian SMARC-iMX8M Computer on Module"; 24 model = "Embedian SMARC-iMX8M Computer on Module";
25 compatible = "embedian,imx8mq-smarcimx8m", "fsl,imx8mq"; 25 compatible = "embedian,imx8mq-smarcimx8m", "fsl,imx8mq";
26 26
27 regulators { 27 regulators {
28 compatible = "simple-bus"; 28 compatible = "simple-bus";
29 #address-cells = <1>; 29 #address-cells = <1>;
30 #size-cells = <0>; 30 #size-cells = <0>;
31 31
32 reg_usdhc2_vmmc: usdhc2_vmmc { 32 reg_usdhc2_vmmc: usdhc2_vmmc {
33 compatible = "regulator-fixed"; 33 compatible = "regulator-fixed";
34 regulator-name = "VSD_3V3"; 34 regulator-name = "VSD_3V3";
35 regulator-min-microvolt = <3300000>; 35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>; 36 regulator-max-microvolt = <3300000>;
37 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 37 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
38 enable-active-high; 38 enable-active-high;
39 }; 39 };
40 }; 40 };
41 41
42 backlight: backlight { 42 backlight: backlight {
43 compatible = "pwm-backlight"; 43 compatible = "pwm-backlight";
44 pwms = <&pwm1 0 1000000 0>; 44 pwms = <&pwm1 0 1000000 0>;
45 brightness-levels = < 0 1 2 3 4 5 6 7 8 9 45 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
46 10 11 12 13 14 15 16 17 18 19 46 10 11 12 13 14 15 16 17 18 19
47 20 21 22 23 24 25 26 27 28 29 47 20 21 22 23 24 25 26 27 28 29
48 30 31 32 33 34 35 36 37 38 39 48 30 31 32 33 34 35 36 37 38 39
49 40 41 42 43 44 45 46 47 48 49 49 40 41 42 43 44 45 46 47 48 49
50 50 51 52 53 54 55 56 57 58 59 50 50 51 52 53 54 55 56 57 58 59
51 60 61 62 63 64 65 66 67 68 69 51 60 61 62 63 64 65 66 67 68 69
52 70 71 72 73 74 75 76 77 78 79 52 70 71 72 73 74 75 76 77 78 79
53 80 81 82 83 84 85 86 87 88 89 53 80 81 82 83 84 85 86 87 88 89
54 90 91 92 93 94 95 96 97 98 99 54 90 91 92 93 94 95 96 97 98 99
55 100>; 55 100>;
56 default-brightness-level = <80>; 56 default-brightness-level = <80>;
57 status = "disabled"; 57 status = "disabled";
58 }; 58 };
59 }; 59 };
60 60
61 &iomuxc { 61 &iomuxc {
62 pinctrl-names = "default"; 62 pinctrl-names = "default";
63 63
64 smarc-imx8mq { 64 smarc-imx8mq {
65 pinctrl_fec1: fec1grp { 65 pinctrl_fec1: fec1grp {
66 fsl,pins = < 66 fsl,pins = <
67 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 67 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
68 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 68 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
69 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 69 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
70 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 70 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
71 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 71 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
72 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 72 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
73 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 73 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
74 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 74 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
75 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 75 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
76 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 76 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
77 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 77 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
78 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 78 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
79 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 79 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
80 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 80 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
81 >; 81 >;
82 }; 82 };
83 83
84 pinctrl_i2c1: i2c1grp { 84 pinctrl_i2c1: i2c1grp {
85 fsl,pins = < 85 fsl,pins = <
86 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f 86 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
87 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f 87 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
88 >; 88 >;
89 }; 89 };
90 90
91 pinctrl_i2c2: i2c2grp { 91 pinctrl_i2c2: i2c2grp {
92 fsl,pins = < 92 fsl,pins = <
93 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f 93 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
94 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f 94 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
95 >; 95 >;
96 }; 96 };
97 97
98 pinctrl_i2c3: i2c3grp { 98 pinctrl_i2c3: i2c3grp {
99 fsl,pins = < 99 fsl,pins = <
100 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f 100 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
101 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f 101 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
102 >; 102 >;
103 }; 103 };
104 104
105 pinctrl_i2c4: i2c4grp { 105 pinctrl_i2c4: i2c4grp {
106 fsl,pins = < 106 fsl,pins = <
107 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f 107 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
108 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f 108 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
109 >; 109 >;
110 }; 110 };
111 111
112 112
113 pinctrl_pcie0: pcie0grp { 113 pinctrl_pcie0: pcie0grp {
114 fsl,pins = < 114 fsl,pins = <
115 MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x16 115 MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x16
116 >; 116 >;
117 }; 117 };
118 118
119 pinctrl_pcie1: pcie1grp { 119 pinctrl_pcie1: pcie1grp {
120 fsl,pins = < 120 fsl,pins = <
121 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x16 121 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x16
122 >; 122 >;
123 }; 123 };
124 124
125 pinctrl_pwm1: pwm1grp { 125 pinctrl_pwm1: pwm1grp {
126 fsl,pins = < 126 fsl,pins = <
127 MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16 127 MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16
128 >; 128 >;
129 }; 129 };
130 130
131 pinctrl_qspi: qspigrp { 131 pinctrl_qspi: qspigrp {
132 fsl,pins = < 132 fsl,pins = <
133 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 133 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
134 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 134 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
135 MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82 135 MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82
136 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 136 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
137 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 137 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
138 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 138 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
139 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 139 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
140 140
141 >; 141 >;
142 }; 142 };
143 143
144 pinctrl_uart1: uart1grp { 144 pinctrl_uart1: uart1grp {
145 fsl,pins = < 145 fsl,pins = <
146 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 146 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79
147 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 147 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79
148 >; 148 >;
149 }; 149 };
150 150
151 pinctrl_uart2: uart2grp { 151 pinctrl_uart2: uart2grp {
152 fsl,pins = < 152 fsl,pins = <
153 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x79 153 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x79
154 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x79 154 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x79
155 MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x19 /* RTS */ 155 MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x19 /* RTS */
156 MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 /* CTS */ 156 MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 /* CTS */
157 157
158 >; 158 >;
159 }; 159 };
160 160
161 pinctrl_uart3: uart3grp { 161 pinctrl_uart3: uart3grp {
162 fsl,pins = < 162 fsl,pins = <
163 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79 163 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79
164 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79 164 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79
165 >; 165 >;
166 }; 166 };
167 167
168 pinctrl_uart4: uart4grp { 168 pinctrl_uart4: uart4grp {
169 fsl,pins = < 169 fsl,pins = <
170 MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x79 170 MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x79
171 MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x79 171 MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x79
172 >; 172 >;
173 }; 173 };
174 174
175 pinctrl_usdhc1: usdhc1grp { 175 pinctrl_usdhc1: usdhc1grp {
176 fsl,pins = < 176 fsl,pins = <
177 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 177 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
178 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 178 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
179 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 179 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
180 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 180 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
181 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 181 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
182 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 182 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
183 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 183 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
184 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 184 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
185 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 185 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
186 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 186 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
187 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 187 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
188 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 188 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
189 >; 189 >;
190 }; 190 };
191 191
192 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 192 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
193 fsl,pins = < 193 fsl,pins = <
194 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d 194 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
195 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd 195 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
196 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd 196 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
197 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd 197 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
198 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd 198 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
199 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd 199 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
200 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd 200 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
201 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd 201 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
202 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd 202 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
203 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd 203 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
204 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d 204 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
205 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 205 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
206 >; 206 >;
207 }; 207 };
208 208
209 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 209 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
210 fsl,pins = < 210 fsl,pins = <
211 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f 211 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
212 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf 212 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
213 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf 213 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
214 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf 214 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
215 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf 215 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
216 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf 216 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
217 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf 217 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
218 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf 218 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
219 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf 219 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
220 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf 220 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
221 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f 221 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
222 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 222 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
223 >; 223 >;
224 }; 224 };
225 225
226 pinctrl_usdhc2_gpio: usdhc2grpgpio { 226 pinctrl_usdhc2_gpio: usdhc2grpgpio {
227 fsl,pins = < 227 fsl,pins = <
228 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x41 228 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x41
229 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 229 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
230 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 230 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
231 >; 231 >;
232 }; 232 };
233 233
234 pinctrl_usdhc2: usdhc2grp { 234 pinctrl_usdhc2: usdhc2grp {
235 fsl,pins = < 235 fsl,pins = <
236 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 236 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
237 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 237 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
238 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 238 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
239 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 239 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
240 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 240 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
241 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 241 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
242 >; 242 >;
243 }; 243 };
244 244
245 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 245 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
246 fsl,pins = < 246 fsl,pins = <
247 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d 247 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
248 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd 248 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
249 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd 249 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
250 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd 250 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
251 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd 251 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
252 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd 252 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
253 >; 253 >;
254 }; 254 };
255 255
256 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 256 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
257 fsl,pins = < 257 fsl,pins = <
258 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f 258 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
259 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf 259 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
260 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf 260 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
261 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf 261 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
262 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf 262 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
263 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf 263 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
264 >; 264 >;
265 }; 265 };
266 266
267 pinctrl_sai2: sai2grp { 267 pinctrl_sai2: sai2grp {
268 fsl,pins = < 268 fsl,pins = <
269 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 269 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
270 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 270 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
271 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 271 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
272 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 272 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
273 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 273 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
274 >; 274 >;
275 }; 275 };
276 276
277 pinctrl_wdog: wdoggrp { 277 pinctrl_wdog: wdoggrp {
278 fsl,pins = < 278 fsl,pins = <
279 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 279 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
280 >; 280 >;
281 }; 281 };
282 }; 282 };
283 }; 283 };
284 284
285 &fec1 { 285 &fec1 {
286 pinctrl-names = "default"; 286 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_fec1>; 287 pinctrl-0 = <&pinctrl_fec1>;
288 phy-mode = "rgmii-id"; 288 phy-mode = "rgmii-id";
289 phy-handle = <&ethphy0>; 289 phy-handle = <&ethphy0>;
290 fsl,magic-packet; 290 fsl,magic-packet;
291 interrupt-parent = <&gpio1>; 291 interrupt-parent = <&gpio1>;
292 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 292 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
293 status = "okay"; 293 status = "okay";
294 294
295 mdio { 295 mdio {
296 #address-cells = <1>; 296 #address-cells = <1>;
297 #size-cells = <0>; 297 #size-cells = <0>;
298 298
299 ethphy0: ethernet-phy@0 { 299 ethphy0: ethernet-phy@0 {
300 compatible = "ethernet-phy-ieee802.3-c22"; 300 compatible = "ethernet-phy-ieee802.3-c22";
301 reg = <0>; 301 reg = <6>;
302 at803x,led-act-blind-workaround; 302 at803x,led-act-blind-workaround;
303 at803x,eee-disabled; 303 at803x,eee-disabled;
304 }; 304 };
305 }; 305 };
306 }; 306 };
307 307
308 &i2c1 { 308 &i2c1 {
309 clock-frequency = <100000>; 309 clock-frequency = <100000>;
310 pinctrl-names = "default"; 310 pinctrl-names = "default";
311 pinctrl-0 = <&pinctrl_i2c1>; 311 pinctrl-0 = <&pinctrl_i2c1>;
312 status = "okay"; 312 status = "okay";
313 313
314 pmic: pfuze100@08 { 314 pmic: pfuze100@08 {
315 compatible = "fsl,pfuze100"; 315 compatible = "fsl,pfuze100";
316 reg = <0x08>; 316 reg = <0x08>;
317 317
318 regulators { 318 regulators {
319 sw1a_reg: sw1ab { 319 sw1a_reg: sw1ab {
320 regulator-min-microvolt = <300000>; 320 regulator-min-microvolt = <300000>;
321 regulator-max-microvolt = <1875000>; 321 regulator-max-microvolt = <1875000>;
322 regulator-always-on; 322 regulator-always-on;
323 }; 323 };
324 324
325 sw1c_reg: sw1c { 325 sw1c_reg: sw1c {
326 regulator-min-microvolt = <300000>; 326 regulator-min-microvolt = <300000>;
327 regulator-max-microvolt = <1875000>; 327 regulator-max-microvolt = <1875000>;
328 regulator-always-on; 328 regulator-always-on;
329 }; 329 };
330 330
331 sw2_reg: sw2 { 331 sw2_reg: sw2 {
332 regulator-min-microvolt = <800000>; 332 regulator-min-microvolt = <800000>;
333 regulator-max-microvolt = <3300000>; 333 regulator-max-microvolt = <3300000>;
334 regulator-always-on; 334 regulator-always-on;
335 }; 335 };
336 336
337 sw3a_reg: sw3ab { 337 sw3a_reg: sw3ab {
338 regulator-min-microvolt = <400000>; 338 regulator-min-microvolt = <400000>;
339 regulator-max-microvolt = <1975000>; 339 regulator-max-microvolt = <1975000>;
340 regulator-always-on; 340 regulator-always-on;
341 }; 341 };
342 342
343 sw4_reg: sw4 { 343 sw4_reg: sw4 {
344 regulator-min-microvolt = <800000>; 344 regulator-min-microvolt = <800000>;
345 regulator-max-microvolt = <3300000>; 345 regulator-max-microvolt = <3300000>;
346 regulator-always-on; 346 regulator-always-on;
347 }; 347 };
348 348
349 swbst_reg: swbst { 349 swbst_reg: swbst {
350 regulator-min-microvolt = <5000000>; 350 regulator-min-microvolt = <5000000>;
351 regulator-max-microvolt = <5150000>; 351 regulator-max-microvolt = <5150000>;
352 }; 352 };
353 353
354 snvs_reg: vsnvs { 354 snvs_reg: vsnvs {
355 regulator-min-microvolt = <1000000>; 355 regulator-min-microvolt = <1000000>;
356 regulator-max-microvolt = <3000000>; 356 regulator-max-microvolt = <3000000>;
357 regulator-always-on; 357 regulator-always-on;
358 }; 358 };
359 359
360 vref_reg: vrefddr { 360 vref_reg: vrefddr {
361 regulator-always-on; 361 regulator-always-on;
362 }; 362 };
363 363
364 vgen1_reg: vgen1 { 364 vgen1_reg: vgen1 {
365 regulator-min-microvolt = <800000>; 365 regulator-min-microvolt = <800000>;
366 regulator-max-microvolt = <1550000>; 366 regulator-max-microvolt = <1550000>;
367 }; 367 };
368 368
369 vgen2_reg: vgen2 { 369 vgen2_reg: vgen2 {
370 regulator-min-microvolt = <800000>; 370 regulator-min-microvolt = <800000>;
371 regulator-max-microvolt = <1550000>; 371 regulator-max-microvolt = <1550000>;
372 regulator-always-on; 372 regulator-always-on;
373 }; 373 };
374 374
375 vgen3_reg: vgen3 { 375 vgen3_reg: vgen3 {
376 regulator-min-microvolt = <1800000>; 376 regulator-min-microvolt = <1800000>;
377 regulator-max-microvolt = <3300000>; 377 regulator-max-microvolt = <3300000>;
378 regulator-always-on; 378 regulator-always-on;
379 }; 379 };
380 380
381 vgen4_reg: vgen4 { 381 vgen4_reg: vgen4 {
382 regulator-min-microvolt = <1800000>; 382 regulator-min-microvolt = <1800000>;
383 regulator-max-microvolt = <3300000>; 383 regulator-max-microvolt = <3300000>;
384 regulator-always-on; 384 regulator-always-on;
385 }; 385 };
386 386
387 vgen5_reg: vgen5 { 387 vgen5_reg: vgen5 {
388 regulator-min-microvolt = <1800000>; 388 regulator-min-microvolt = <1800000>;
389 regulator-max-microvolt = <3300000>; 389 regulator-max-microvolt = <3300000>;
390 regulator-always-on; 390 regulator-always-on;
391 }; 391 };
392 392
393 vgen6_reg: vgen6 { 393 vgen6_reg: vgen6 {
394 regulator-min-microvolt = <1800000>; 394 regulator-min-microvolt = <1800000>;
395 regulator-max-microvolt = <3300000>; 395 regulator-max-microvolt = <3300000>;
396 regulator-always-on; 396 regulator-always-on;
397 }; 397 };
398 }; 398 };
399 }; 399 };
400 400
401 s35390a: s35390a@30 { 401 s35390a: s35390a@30 {
402 compatible = "s35390a"; 402 compatible = "s35390a";
403 reg = <0x30>; 403 reg = <0x30>;
404 }; 404 };
405 405
406 cape_eeprom0: cape_eeprom@57 { 406 cape_eeprom0: cape_eeprom@57 {
407 compatible = "at,24c256"; 407 compatible = "at,24c256";
408 reg = <0x57>; 408 reg = <0x57>;
409 }; 409 };
410 }; 410 };
411 411
412 &i2c2 { 412 &i2c2 {
413 clock-frequency = <100000>; 413 clock-frequency = <100000>;
414 pinctrl-names = "default"; 414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_i2c2>; 415 pinctrl-0 = <&pinctrl_i2c2>;
416 status = "okay"; 416 status = "okay";
417 417
418 baseboard_eeprom: baseboard_eeprom@50 { 418 baseboard_eeprom: baseboard_eeprom@50 {
419 compatible = "at,24c256"; 419 compatible = "at,24c256";
420 reg = <0x50>; 420 reg = <0x50>;
421 }; 421 };
422 422
423 dsi_lvds_bridge: sn65dsi84@2c { 423 dsi_lvds_bridge: sn65dsi84@2c {
424 status = "disabled"; 424 status = "disabled";
425 reg = <0x2c>; 425 reg = <0x2c>;
426 compatible = "ti,sn65dsi84"; 426 compatible = "ti,sn65dsi84";
427 enable-gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; 427 enable-gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>;
428 interrupt-parent = <&gpio4>; 428 interrupt-parent = <&gpio4>;
429 interrupts = <4 IRQ_TYPE_EDGE_FALLING>; 429 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
430 430
431 /* AUO G070VW01 7-inch 800x480 LVDS Display */ 431 /* AUO G070VW01 7-inch 800x480 LVDS Display */
432 sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 432 sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
433 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 433 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
434 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 434 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
435 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 435 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
436 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 436 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
437 0x3C 0x3D 0x3E 0xE0 0x0D>; 437 0x3C 0x3D 0x3E 0xE0 0x0D>;
438 438
439 sn65dsi84,values = < 0x00 0x01 0x10 0x00 0x26 0x00 0x13 0x00 439 sn65dsi84,values = < 0x00 0x01 0x10 0x00 0x26 0x00 0x13 0x00
440 0x78 0x00 0x03 0x00 0x20 0x03 0x00 0x00 440 0x78 0x00 0x03 0x00 0x20 0x03 0x00 0x00
441 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00 441 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
442 0x80 0x00 0x00 0x00 0x0e 0x00 0x00 0x00 442 0x80 0x00 0x00 0x00 0x0e 0x00 0x00 0x00
443 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 443 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00
444 0x00 0x00 0x00 0x01 0x01>; 444 0x00 0x00 0x00 0x01 0x01>;
445 445
446 /* AUO G185XW01 18.5-inch 1366x768 LVDS Display */ 446 /* AUO G185XW01 18.5-inch 1366x768 LVDS Display */
447 /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 447 /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
448 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 448 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
449 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 449 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
450 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 450 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
451 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 451 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
452 0x3C 0x3D 0x3E 0xE0 0x0D>; 452 0x3C 0x3D 0x3E 0xE0 0x0D>;
453 453
454 sn65dsi84,values = < 0x00 0x05 0x10 0x00 0x26 0x00 0x2E 0x00 454 sn65dsi84,values = < 0x00 0x05 0x10 0x00 0x26 0x00 0x2E 0x00
455 0x78 0x00 0x03 0x00 0x56 0x05 0x00 0x00 455 0x78 0x00 0x03 0x00 0x56 0x05 0x00 0x00
456 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00 456 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
457 0x78 0x00 0x00 0x00 0x12 0x00 0x00 0x00 457 0x78 0x00 0x00 0x00 0x12 0x00 0x00 0x00
458 0x3C 0x00 0x00 0x00 0x00 0x00 0x00 0x00 458 0x3C 0x00 0x00 0x00 0x00 0x00 0x00 0x00
459 0x00 0x00 0x00 0x01 0x01>;*/ 459 0x00 0x00 0x00 0x01 0x01>;*/
460 460
461 /* AUO G240HW01 V0 24-inch 1920x1080 LVDS Display */ 461 /* AUO G240HW01 V0 24-inch 1920x1080 LVDS Display */
462 /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 462 /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
463 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 463 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
464 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 464 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
465 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 465 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
466 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 466 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
467 0x3C 0x3D 0x3E 0xE0 0x0D>; 467 0x3C 0x3D 0x3E 0xE0 0x0D>;
468 468
469 sn65dsi84,values = < 0x00 0x05 0x20 0x00 0x26 0x00 0x4E 0x00 469 sn65dsi84,values = < 0x00 0x05 0x20 0x00 0x26 0x00 0x4E 0x00
470 0x6C 0x00 0x03 0x00 0x80 0x07 0x00 0x00 470 0x6C 0x00 0x03 0x00 0x80 0x07 0x00 0x00
471 0x00 0x00 0x00 0x00 0xC3 0x00 0x00 0x00 471 0x00 0x00 0x00 0x00 0xC3 0x00 0x00 0x00
472 0x32 0x00 0x00 0x00 0x14 0x00 0x00 0x00 472 0x32 0x00 0x00 0x00 0x14 0x00 0x00 0x00
473 0x19 0x00 0x00 0x00 0x00 0x00 0x00 0x00 473 0x19 0x00 0x00 0x00 0x00 0x00 0x00 0x00
474 0x00 0x00 0x00 0x01 0x01>;*/ 474 0x00 0x00 0x00 0x01 0x01>;*/
475 }; 475 };
476 }; 476 };
477 477
478 &i2c3 { 478 &i2c3 {
479 clock-frequency = <100000>; 479 clock-frequency = <100000>;
480 pinctrl-names = "default"; 480 pinctrl-names = "default";
481 pinctrl-0 = <&pinctrl_i2c3>; 481 pinctrl-0 = <&pinctrl_i2c3>;
482 status = "okay"; 482 status = "okay";
483 }; 483 };
484 484
485 &i2c4 { 485 &i2c4 {
486 clock-frequency = <100000>; 486 clock-frequency = <100000>;
487 pinctrl-names = "default"; 487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_i2c4>; 488 pinctrl-0 = <&pinctrl_i2c4>;
489 status = "okay"; 489 status = "okay";
490 }; 490 };
491 491
492 &pcie0{ 492 &pcie0{
493 pinctrl-names = "default"; 493 pinctrl-names = "default";
494 pinctrl-0 = <&pinctrl_pcie0>; 494 pinctrl-0 = <&pinctrl_pcie0>;
495 reset-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>; 495 reset-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>;
496 status = "okay"; 496 status = "okay";
497 }; 497 };
498 498
499 &pcie1{ 499 &pcie1{
500 pinctrl-names = "default"; 500 pinctrl-names = "default";
501 pinctrl-0 = <&pinctrl_pcie1>; 501 pinctrl-0 = <&pinctrl_pcie1>;
502 reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; 502 reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>;
503 status = "okay"; 503 status = "okay";
504 }; 504 };
505 505
506 &pwm1 { 506 &pwm1 {
507 pinctrl-names = "default"; 507 pinctrl-names = "default";
508 pinctrl-0 = <&pinctrl_pwm1>; 508 pinctrl-0 = <&pinctrl_pwm1>;
509 status = "okay"; 509 status = "okay";
510 }; 510 };
511 511
512 &uart1 { /* console */ 512 &uart1 { /* console */
513 pinctrl-names = "default"; 513 pinctrl-names = "default";
514 pinctrl-0 = <&pinctrl_uart1>; 514 pinctrl-0 = <&pinctrl_uart1>;
515 assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; 515 assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
516 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; 516 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
517 status = "okay"; 517 status = "okay";
518 }; 518 };
519 519
520 &lcdif { 520 &lcdif {
521 status = "okay"; 521 status = "okay";
522 disp-dev = "mipi_dsi_northwest"; 522 disp-dev = "mipi_dsi_northwest";
523 display = <&display0>; 523 display = <&display0>;
524 524
525 display0: display@0 { 525 display0: display@0 {
526 bits-per-pixel = <24>; 526 bits-per-pixel = <24>;
527 bus-width = <24>; 527 bus-width = <24>;
528 528
529 display-timings { 529 display-timings {
530 native-mode = <&timing0>; 530 native-mode = <&timing0>;
531 timing0: timing0 { 531 timing0: timing0 {
532 clock-frequency = <9200000>; 532 clock-frequency = <9200000>;
533 hactive = <480>; 533 hactive = <480>;
534 vactive = <272>; 534 vactive = <272>;
535 hfront-porch = <8>; 535 hfront-porch = <8>;
536 hback-porch = <4>; 536 hback-porch = <4>;
537 hsync-len = <41>; 537 hsync-len = <41>;
538 vback-porch = <2>; 538 vback-porch = <2>;
539 vfront-porch = <4>; 539 vfront-porch = <4>;
540 vsync-len = <10>; 540 vsync-len = <10>;
541 541
542 hsync-active = <0>; 542 hsync-active = <0>;
543 vsync-active = <0>; 543 vsync-active = <0>;
544 de-active = <1>; 544 de-active = <1>;
545 pixelclk-active = <0>; 545 pixelclk-active = <0>;
546 }; 546 };
547 }; 547 };
548 }; 548 };
549 port@0 { 549 port@0 {
550 lcdif_mipi_dsi: mipi-dsi-endpoint { 550 lcdif_mipi_dsi: mipi-dsi-endpoint {
551 remote-endpoint = <&mipi_dsi_in>; 551 remote-endpoint = <&mipi_dsi_in>;
552 }; 552 };
553 }; 553 };
554 }; 554 };
555 555
556 &qspi { 556 &qspi {
557 pinctrl-names = "default"; 557 pinctrl-names = "default";
558 pinctrl-0 = <&pinctrl_qspi>; 558 pinctrl-0 = <&pinctrl_qspi>;
559 status = "okay"; 559 status = "okay";
560 }; 560 };
561 561
562 &mipi_dsi { 562 &mipi_dsi {
563 reset = <&src>; 563 reset = <&src>;
564 mux-sel = <&gpr>; /* lcdif or dcss */ 564 mux-sel = <&gpr>; /* lcdif or dcss */
565 status = "okay"; 565 status = "okay";
566 566
567 port@1 { 567 port@1 {
568 mipi_dsi_in: endpoint { 568 mipi_dsi_in: endpoint {
569 remote-endpoint = <&lcdif_mipi_dsi>; 569 remote-endpoint = <&lcdif_mipi_dsi>;
570 }; 570 };
571 }; 571 };
572 }; 572 };
573 573
574 &uart2 { 574 &uart2 {
575 pinctrl-names = "default"; 575 pinctrl-names = "default";
576 pinctrl-0 = <&pinctrl_uart2>; 576 pinctrl-0 = <&pinctrl_uart2>;
577 assigned-clocks = <&clk IMX8MQ_CLK_UART2_SRC>; 577 assigned-clocks = <&clk IMX8MQ_CLK_UART2_SRC>;
578 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; 578 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
579 fsl,uart-has-rtscts; 579 fsl,uart-has-rtscts;
580 status = "okay"; 580 status = "okay";
581 }; 581 };
582 582
583 &uart3 { 583 &uart3 {
584 pinctrl-names = "default"; 584 pinctrl-names = "default";
585 pinctrl-0 = <&pinctrl_uart3>; 585 pinctrl-0 = <&pinctrl_uart3>;
586 assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>; 586 assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
587 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; 587 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
588 status = "okay"; 588 status = "okay";
589 }; 589 };
590 590
591 &uart4 { 591 &uart4 {
592 pinctrl-names = "default"; 592 pinctrl-names = "default";
593 pinctrl-0 = <&pinctrl_uart4>; 593 pinctrl-0 = <&pinctrl_uart4>;
594 assigned-clocks = <&clk IMX8MQ_CLK_UART4_SRC>; 594 assigned-clocks = <&clk IMX8MQ_CLK_UART4_SRC>;
595 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; 595 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
596 fsl,uart-has-rtscts; 596 fsl,uart-has-rtscts;
597 status = "okay"; 597 status = "okay";
598 }; 598 };
599 599
600 &usdhc1 { 600 &usdhc1 {
601 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 601 pinctrl-names = "default", "state_100mhz", "state_200mhz";
602 pinctrl-0 = <&pinctrl_usdhc1>; 602 pinctrl-0 = <&pinctrl_usdhc1>;
603 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 603 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
604 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 604 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
605 bus-width = <8>; 605 bus-width = <8>;
606 non-removable; 606 non-removable;
607 status = "okay"; 607 status = "okay";
608 }; 608 };
609 609
610 &usdhc2 { 610 &usdhc2 {
611 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 611 pinctrl-names = "default", "state_100mhz", "state_200mhz";
612 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 612 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
613 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 613 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
614 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 614 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
615 bus-width = <4>; 615 bus-width = <4>;
616 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 616 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
617 vmmc-supply = <&reg_usdhc2_vmmc>; 617 vmmc-supply = <&reg_usdhc2_vmmc>;
618 status = "okay"; 618 status = "okay";
619 }; 619 };
620 620
621 &usb3_phy0 { 621 &usb3_phy0 {
622 status = "okay"; 622 status = "okay";
623 }; 623 };
624 624
625 &usb3_0 { 625 &usb3_0 {
626 status = "okay"; 626 status = "okay";
627 }; 627 };
628 628
629 &usb_dwc3_0 { 629 &usb_dwc3_0 {
630 status = "okay"; 630 status = "okay";
631 dr_mode = "peripheral"; 631 dr_mode = "peripheral";
632 }; 632 };
633 633
634 &usb3_phy1 { 634 &usb3_phy1 {
635 status = "okay"; 635 status = "okay";
636 }; 636 };
637 637
638 &usb3_1 { 638 &usb3_1 {
639 status = "disabled"; 639 status = "disabled";
640 }; 640 };
641 641
642 &usb_dwc3_1 { 642 &usb_dwc3_1 {
643 status = "okay"; 643 status = "okay";
644 dr_mode = "host"; 644 dr_mode = "host";
645 }; 645 };
646 646
647 &sai2 { 647 &sai2 {
648 pinctrl-names = "default"; 648 pinctrl-names = "default";
649 pinctrl-0 = <&pinctrl_sai2>; 649 pinctrl-0 = <&pinctrl_sai2>;
650 assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>, 650 assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>,
651 <&clk IMX8MQ_AUDIO_PLL1>, 651 <&clk IMX8MQ_AUDIO_PLL1>,
652 <&clk IMX8MQ_CLK_SAI2_PRE_DIV>, 652 <&clk IMX8MQ_CLK_SAI2_PRE_DIV>,
653 <&clk IMX8MQ_CLK_SAI2_DIV>; 653 <&clk IMX8MQ_CLK_SAI2_DIV>;
654 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 654 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
655 assigned-clock-rates = <0>, <786432000>, <98306000>, <24576000>; 655 assigned-clock-rates = <0>, <786432000>, <98306000>, <24576000>;
656 status = "okay"; 656 status = "okay";
657 }; 657 };
658 658
659 &gpu { 659 &gpu {
660 status = "okay"; 660 status = "okay";
661 }; 661 };
662 662
663 &vpu { 663 &vpu {
664 status = "okay"; 664 status = "okay";
665 }; 665 };
666 666
667 &wdog1 { 667 &wdog1 {
668 pinctrl-names = "default"; 668 pinctrl-names = "default";
669 pinctrl-0 = <&pinctrl_wdog>; 669 pinctrl-0 = <&pinctrl_wdog>;
670 fsl,ext-reset-output; 670 fsl,ext-reset-output;
671 status = "okay"; 671 status = "okay";
672 }; 672 };
673 673