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Commit 572045b6e7dd510999e9649c0d94fead1b29f1b7

Authored by Philipp Tomsich
Committed by Simon Glass
1 parent c5f99c654e
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

rockchip: dts: rk3399-puma: Add DDR3-1600 timings and use for Puma 

With the validation done for DDR3-1600 (i.e. 800 MHz bus clock), we
add the timings (rk3399-sdram-ddr3-1600.dtsi) and change rk3399-puma.dts
to use these by default.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Drop blank line at end of file:
Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 2 changed files with 1541 additions and 1 deletions Inline Diff

arch/arm/dts/rk3399-puma.dts
Diff comments   View file @ 572045b
1 /* 1 /*
2 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH 2 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ X11 4 * SPDX-License-Identifier: GPL-2.0+ X11
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 #include <dt-bindings/pwm/pwm.h> 8 #include <dt-bindings/pwm/pwm.h>
9 #include "rk3399.dtsi" 9 #include "rk3399.dtsi"
10 #include "rk3399-sdram-ddr3-1333.dtsi" 10 #include "rk3399-sdram-ddr3-1600.dtsi"
11 11
12 / { 12 / {
13 model = "Theobroma Systems RK3399-Q7 SoM"; 13 model = "Theobroma Systems RK3399-Q7 SoM";
14 compatible = "tsd,puma", "rockchip,rk3399"; 14 compatible = "tsd,puma", "rockchip,rk3399";
15
16 config {
17 u-boot,spl-payload-offset = <204800>;
18 };
15 19
16 chosen { 20 chosen {
17 stdout-path = "serial0:115200n8"; 21 stdout-path = "serial0:115200n8";
18 u-boot,spl-boot-order = &spiflash, &sdhci, &sdmmc; 22 u-boot,spl-boot-order = &spiflash, &sdhci, &sdmmc;
19 }; 23 };
20 24
21 aliases { 25 aliases {
22 spi0 = &spi1; 26 spi0 = &spi1;
23 spi1 = &spi5; 27 spi1 = &spi5;
24 }; 28 };
25 29
26 vdd_center: vdd-center { 30 vdd_center: vdd-center {
27 compatible = "pwm-regulator"; 31 compatible = "pwm-regulator";
28 pwms = <&pwm3 0 25000 0>; 32 pwms = <&pwm3 0 25000 0>;
29 regulator-name = "vdd_center"; 33 regulator-name = "vdd_center";
30 regulator-min-microvolt = <800000>; 34 regulator-min-microvolt = <800000>;
31 regulator-max-microvolt = <1400000>; 35 regulator-max-microvolt = <1400000>;
32 regulator-init-microvolt = <950000>; 36 regulator-init-microvolt = <950000>;
33 regulator-always-on; 37 regulator-always-on;
34 regulator-boot-on; 38 regulator-boot-on;
35 status = "okay"; 39 status = "okay";
36 }; 40 };
37 41
38 vcc3v3_sys: vcc3v3-sys { 42 vcc3v3_sys: vcc3v3-sys {
39 compatible = "regulator-fixed"; 43 compatible = "regulator-fixed";
40 regulator-name = "vcc3v3_sys"; 44 regulator-name = "vcc3v3_sys";
41 regulator-always-on; 45 regulator-always-on;
42 regulator-boot-on; 46 regulator-boot-on;
43 regulator-min-microvolt = <3300000>; 47 regulator-min-microvolt = <3300000>;
44 regulator-max-microvolt = <3300000>; 48 regulator-max-microvolt = <3300000>;
45 }; 49 };
46 50
47 vcc_phy: vcc-phy-regulator { 51 vcc_phy: vcc-phy-regulator {
48 compatible = "regulator-fixed"; 52 compatible = "regulator-fixed";
49 regulator-name = "vcc_phy"; 53 regulator-name = "vcc_phy";
50 regulator-always-on; 54 regulator-always-on;
51 regulator-boot-on; 55 regulator-boot-on;
52 }; 56 };
53 57
54 vcc5v0_host: vcc5v0-host-en { 58 vcc5v0_host: vcc5v0-host-en {
55 compatible = "regulator-fixed"; 59 compatible = "regulator-fixed";
56 regulator-name = "vcc5v0_host"; 60 regulator-name = "vcc5v0_host";
57 gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; 61 gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
58 }; 62 };
59 63
60 clkin_gmac: external-gmac-clock { 64 clkin_gmac: external-gmac-clock {
61 compatible = "fixed-clock"; 65 compatible = "fixed-clock";
62 clock-frequency = <125000000>; 66 clock-frequency = <125000000>;
63 clock-output-names = "clkin_gmac"; 67 clock-output-names = "clkin_gmac";
64 #clock-cells = <0>; 68 #clock-cells = <0>;
65 }; 69 };
66 70
67 vcc_phy: vcc-phy-regulator { 71 vcc_phy: vcc-phy-regulator {
68 compatible = "regulator-fixed"; 72 compatible = "regulator-fixed";
69 regulator-name = "vcc_phy"; 73 regulator-name = "vcc_phy";
70 regulator-always-on; 74 regulator-always-on;
71 regulator-boot-on; 75 regulator-boot-on;
72 }; 76 };
73 }; 77 };
74 78
75 &emmc_phy { 79 &emmc_phy {
76 status = "okay"; 80 status = "okay";
77 }; 81 };
78 82
79 &pwm0 { 83 &pwm0 {
80 status = "okay"; 84 status = "okay";
81 }; 85 };
82 86
83 &pwm2 { 87 &pwm2 {
84 status = "okay"; 88 status = "okay";
85 }; 89 };
86 90
87 &pwm3 { 91 &pwm3 {
88 status = "okay"; 92 status = "okay";
89 }; 93 };
90 94
91 &sdmmc { 95 &sdmmc {
92 u-boot,dm-pre-reloc; 96 u-boot,dm-pre-reloc;
93 bus-width = <4>; 97 bus-width = <4>;
94 status = "okay"; 98 status = "okay";
95 }; 99 };
96 100
97 &sdhci { 101 &sdhci {
98 bus-width = <8>; 102 bus-width = <8>;
99 mmc-hs400-1_8v; 103 mmc-hs400-1_8v;
100 mmc-hs400-enhanced-strobe; 104 mmc-hs400-enhanced-strobe;
101 non-removable; 105 non-removable;
102 status = "okay"; 106 status = "okay";
103 }; 107 };
104 108
105 &uart0 { 109 &uart0 {
106 status = "okay"; 110 status = "okay";
107 }; 111 };
108 112
109 &uart2 { 113 &uart2 {
110 status = "okay"; 114 status = "okay";
111 }; 115 };
112 116
113 &usb_host0_ehci { 117 &usb_host0_ehci {
114 status = "okay"; 118 status = "okay";
115 }; 119 };
116 120
117 &usb_host0_ohci { 121 &usb_host0_ohci {
118 status = "okay"; 122 status = "okay";
119 }; 123 };
120 124
121 &dwc3_typec0 { 125 &dwc3_typec0 {
122 status = "okay"; 126 status = "okay";
123 }; 127 };
124 128
125 &usb_host1_ehci { 129 &usb_host1_ehci {
126 status = "okay"; 130 status = "okay";
127 }; 131 };
128 132
129 &usb_host1_ohci { 133 &usb_host1_ohci {
130 status = "okay"; 134 status = "okay";
131 }; 135 };
132 136
133 &dwc3_typec1 { 137 &dwc3_typec1 {
134 status = "okay"; 138 status = "okay";
135 }; 139 };
136 140
137 &pinctrl { 141 &pinctrl {
138 pmic { 142 pmic {
139 pmic_int_l: pmic-int-l { 143 pmic_int_l: pmic-int-l {
140 rockchip,pins = 144 rockchip,pins =
141 <1 21 RK_FUNC_GPIO &pcfg_pull_up>; 145 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
142 }; 146 };
143 147
144 pmic_dvs2: pmic-dvs2 { 148 pmic_dvs2: pmic-dvs2 {
145 rockchip,pins = 149 rockchip,pins =
146 <1 18 RK_FUNC_GPIO &pcfg_pull_down>; 150 <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
147 }; 151 };
148 }; 152 };
149 }; 153 };
150 154
151 &gmac { 155 &gmac {
152 phy-supply = <&vcc_phy>; 156 phy-supply = <&vcc_phy>;
153 phy-mode = "rgmii"; 157 phy-mode = "rgmii";
154 clock_in_out = "input"; 158 clock_in_out = "input";
155 snps,reset-gpio = <&gpio3 16 GPIO_ACTIVE_LOW>; 159 snps,reset-gpio = <&gpio3 16 GPIO_ACTIVE_LOW>;
156 snps,reset-active-low; 160 snps,reset-active-low;
157 snps,reset-delays-us = <0 10000 50000>; 161 snps,reset-delays-us = <0 10000 50000>;
158 assigned-clocks = <&cru SCLK_RMII_SRC>; 162 assigned-clocks = <&cru SCLK_RMII_SRC>;
159 assigned-clock-parents = <&clkin_gmac>; 163 assigned-clock-parents = <&clkin_gmac>;
160 pinctrl-names = "default"; 164 pinctrl-names = "default";
161 pinctrl-0 = <&rgmii_pins>; 165 pinctrl-0 = <&rgmii_pins>;
162 tx_delay = <0x10>; 166 tx_delay = <0x10>;
163 rx_delay = <0x10>; 167 rx_delay = <0x10>;
164 status = "okay"; 168 status = "okay";
165 }; 169 };
166 170
167 &spi1 { 171 &spi1 {
168 u-boot,dm-pre-reloc; 172 u-boot,dm-pre-reloc;
169 173
170 status = "okay"; 174 status = "okay";
171 175
172 #address-cells = <1>; 176 #address-cells = <1>;
173 #size-cells = <0>; 177 #size-cells = <0>;
174 178
175 spiflash: w25q32dw@0 { 179 spiflash: w25q32dw@0 {
176 u-boot,dm-pre-reloc; 180 u-boot,dm-pre-reloc;
177 181
178 compatible = "spi-flash"; 182 compatible = "spi-flash";
179 reg = <0>; 183 reg = <0>;
180 spi-max-frequency = <5000000>; 184 spi-max-frequency = <5000000>;
181 spi-cpol; 185 spi-cpol;
182 spi-cpha; 186 spi-cpha;
183 }; 187 };
184 }; 188 };
185 189
186 &spi5 { 190 &spi5 {
187 status = "okay"; 191 status = "okay";
188 }; 192 };
189 193
arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi
Diff comments   View file @ 572045b
File was created 1 /*
2 * (C) 2017 Theobroma Systems Design und Consulting GmbH
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 &dmc {
8 rockchip,sdram-params = <
9 0x1
10 0xa
11 0x3
12 0x2
13 0x1
14 0x0
15 0xf
16 0xf
17 1
18 0x80151015
19 0x14040902
20 0x00000002
21 0x00006346
22 0x0000004c
23 0x00000000
24 0x1
25 0xa
26 0x3
27 0x2
28 0x1
29 0x0
30 0xf
31 0xf
32 1
33 0x80151015
34 0x14040902
35 0x00000002
36 0x00006346
37 0x0000004c
38 0x00000000
39 800
40 3
41 2
42 9
43 1
44 0x00000600
45 0x00000000
46 0x00000000
47 0x00000000
48 0x00000000
49 0x00000008
50 0x00000000
51 0x00000000
52 0x00000000
53 0x00000008
54 0x00000000
55 0x00000000
56 0x00000000
57 0x00000008
58 0x00000000
59 0x00000000
60 0x01000000
61 0x00000000
62 0x00000101
63 0x00020100
64 0x00027100
65 0x00061a80
66 0x02000200
67 0x08160200
68 0x00081600
69 0x04000816
70 0x26050004
71 0x1c0b061c
72 0x1c260500
73 0x001c0b06
74 0x061c2605
75 0x06001c0b
76 0x00000c04
77 0x0400db60
78 0x0c040605
79 0x0400db60
80 0x0c040605
81 0x0400db60
82 0x02030005
83 0x0b0c0b00
84 0x000c0b0c
85 0x14000a0a
86 0x00000a0a
87 0x00010000
88 0x03171717
89 0x000b0b0b
90 0x00000000
91 0x03010000
92 0x18580118
93 0x18580118
94 0x18580118
95 0x00000000
96 0x00050005
97 0x00140005
98 0x00140014
99 0x00000000
100 0x00000000
101 0x00000000
102 0x00000000
103 0x02000000
104 0x02000120
105 0x02000120
106 0x00000120
107 0x00000000
108 0x00000000
109 0x00000000
110 0x00000000
111 0x00000000
112 0x00000000
113 0x00000301
114 0x00000001
115 0x00000000
116 0x00000000
117 0x01000000
118 0x80104002
119 0x00040003
120 0x00040005
121 0x00030000
122 0x00050004
123 0x00000004
124 0x00040003
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128 0x30b06160
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236 0x01000f0f
237 0x00000000
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240 0x00000c03
241 0x00000000
242 0x00000000
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245 0x00000001
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247 0x00000000
248 0x00000000
249 0x00000000
250 0x00000000
251 0x00000000
252 0x00000000
253 0x00000000
254 0x00000000
255 0x00010000
256 0x07070702
257 0x01010606
258 0x00000001
259 0x03030300
260 0x03080808
261 0x03050303
262 0x03050303
263 0x00050303
264 0x00020202
265 0x00000000
266 0x00000000
267 0x00000000
268 0x00000000
269 0x0d000001
270 0x00010028
271 0x00010000
272 0x00000003
273 0x00000000
274 0x00000000
275 0x00000000
276 0x00000000
277 0x00000000
278 0x00000000
279 0x00000000
280 0x00000000
281 0x00010100
282 0x01000000
283 0x00000001
284 0x00000303
285 0x00000000
286 0x00000000
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288 0x00000000
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297 0x00000000
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299 0x00000000
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301 0x000aaaaa
302 0x000aa955
303 0x00055555
304 0x000b3133
305 0x0004cd33
306 0x0004cecc
307 0x000b32cc
308 0x00010300
309 0x03000100
310 0x00000000
311 0x00000000
312 0x00000000
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314 0x00000000
315 0x00000000
316 0x00000000
317 0x00000000
318 0x00ffff00
319 0x15150000
320 0x08000015
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322 0x00000200
323 0x00000200
324 0x00000200
325 0x00000200
326 0x000030b0
327 0x0001e6e0
328 0x30b00709
329 0x00000200
330 0x00000200
331 0x00000200
332 0x00000200
333 0x000030b0
334 0x0001e6e0
335 0x30b00709
336 0x00000200
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338 0x00000200
339 0x00000200
340 0x000030b0
341 0x0001e6e0
342 0x02020709
343 0x03030202
344 0x00000014
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347 0x00001403
348 0x00000000
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350 0x00000000
351 0x00030000
352 0x00060018
353 0x00060018
354 0x00060018
355 0x00000000
356 0x00000000
357 0x01000000
358 0x02060206
359 0x00050206
360 0x00000000
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367 0x00000000
368 0x01000100
369 0x01010101
370 0x01000101
371 0x01000100
372 0x00010001
373 0x00010002
374 0x00020100
375 0x00000002
376 0x00000600
377 0x00000000
378 0x00006160
379 0x000030b0
380 0x00006160
381 0x000030b0
382 0x00006160
383 0x30b030b0
384 0x00000200
385 0x00000200
386 0x00000200
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398 0x00010000
399 0x00000007
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405 0x3c010000
406 0x1dc0ffff
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408 0x1dc0ffff
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410 0x1dc7ffff
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412 0x00000000
413 0x3c000000
414 0x00000000
415 0x3c000000
416 0x00000000
417 0x03000101
418 0x00242424
419 0x08160008
420 0x00081600
421 0x00000016
422 0x18580118
423 0x18580118
424 0x18580118
425 0x00000500
426 0x00000000
427 0x00000000
428 0x00000000
429 0x00000000
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463 0x55555a5a
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469 0x00030000
470 0x17030000
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510 0x4d000000
511 0x0000424d
512 0x00000018
513 0x004d4d00
514 0x00180042
515 0x4d000000
516 0x0042004d
517 0x00000018
518 0x004d4d00
519 0x00180042
520 0x4d000000
521 0x0000424d
522 0x00000018
523 0x004d4d00
524 0x00180042
525 0x4d000000
526 0x0000424d
527 0x00000018
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529 0x00180042
530 0x4d000000
531 0x0000004d
532 0x00c800c8
533 0x060400c8
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535 0x1c00d92e
536 0x08042000
537 0x0b0b060c
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550 0x00000000
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560 0x00000000
561 0x00000000
562 0x01000300
563 0x0030b000
564 0x0001e6e0
565 0x000030b0
566 0x0001e6e0
567 0x000030b0
568 0x0001e6e0
569 0x08000000
570 0x00000100
571 0x00000000
572 0x00000000
573 0x00000000
574 0x00000000
575 0x00000001
576 0x76543210
577 0x0004c008
578 0x00000099
579 0x00000000
580 0x00000000
581 0x00010000
582 0x01665555
583 0x00665555
584 0x00010f00
585 0x05010200
586 0x00000001
587 0x001700c0
588 0x00cc0001
589 0x00000066
590 0x00000000
591 0x00000000
592 0x00000000
593 0x00000000
594 0x00000000
595 0x00000000
596 0x00000000
597 0x00000000
598 0x04080000
599 0x04080400
600 0x08000000
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1536 };
1537