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Commit 5769f671a9e5b21ed38cc98618235dac899bd401

Authored by Eric Lee 2019-11-15 18:56:15 +0800

1 parent 89054a546f

Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 3 other branches

Minor bugs fixed

Showing 18 changed files with 40 additions and 43 deletions Inline Diff

board/embedian/smarcfimx6/smarcfimx6.c
configs/smarcfimx6_dl_1g_ser0_android_defconfig
configs/smarcfimx6_dl_1g_ser0_defconfig
configs/smarcfimx6_dl_1g_ser1_android_defconfig
configs/smarcfimx6_dl_1g_ser1_defconfig
configs/smarcfimx6_dl_1g_ser2_android_defconfig
configs/smarcfimx6_dl_1g_ser2_defconfig
configs/smarcfimx6_dl_1g_ser3_android_defconfig
configs/smarcfimx6_dl_1g_ser3_defconfig
configs/smarcfimx6_solo_ser0_android_defconfig
configs/smarcfimx6_solo_ser0_defconfig
configs/smarcfimx6_solo_ser1_android_defconfig
configs/smarcfimx6_solo_ser1_defconfig
configs/smarcfimx6_solo_ser2_android_defconfig
configs/smarcfimx6_solo_ser2_defconfig
configs/smarcfimx6_solo_ser3_android_defconfig
configs/smarcfimx6_solo_ser3_defconfig
include/configs/smarcfimx6_common.h

board/embedian/smarcfimx6/smarcfimx6.c

Diff comments View file @ 5769f67

1	/*	1	/*
2	* Copyright (C) 2012-2016 Freescale Semiconductor, Inc.	2	* Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
3	* Copyright 2017-2018 NXP	3	* Copyright 2017-2018 NXP
4	*	4	*
5	* Author: Fabio Estevam <fabio.estevam@freescale.com>	5	* Author: Fabio Estevam <fabio.estevam@freescale.com>
6	*	6	*
7	* SPDX-License-Identifier: GPL-2.0+	7	* SPDX-License-Identifier: GPL-2.0+
8	*/	8	*/
9		9
10	#include <asm/arch/clock.h>	10	#include <asm/arch/clock.h>
11	#include <asm/arch/imx-regs.h>	11	#include <asm/arch/imx-regs.h>
12	#include <asm/arch/iomux.h>	12	#include <asm/arch/iomux.h>
13	#include <asm/arch/mx6-pins.h>	13	#include <asm/arch/mx6-pins.h>
14	#include <asm/mach-imx/spi.h>	14	#include <asm/mach-imx/spi.h>
15	#include <linux/errno.h>	15	#include <linux/errno.h>
16	#include <asm/gpio.h>	16	#include <asm/gpio.h>
17	#include <asm/mach-imx/mxc_i2c.h>	17	#include <asm/mach-imx/mxc_i2c.h>
18	#include <asm/mach-imx/iomux-v3.h>	18	#include <asm/mach-imx/iomux-v3.h>
19	#include <asm/mach-imx/boot_mode.h>	19	#include <asm/mach-imx/boot_mode.h>
20	#include <asm/mach-imx/video.h>	20	#include <asm/mach-imx/video.h>
21	#include <mmc.h>	21	#include <mmc.h>
22	#include <fsl_esdhc.h>	22	#include <fsl_esdhc.h>
23	#include <miiphy.h>	23	#include <miiphy.h>
24	#include <netdev.h>	24	#include <netdev.h>
25	#include <asm/arch/mxc_hdmi.h>	25	#include <asm/arch/mxc_hdmi.h>
26	#include <asm/arch/crm_regs.h>	26	#include <asm/arch/crm_regs.h>
27	#include <asm/io.h>	27	#include <asm/io.h>
28	#include <asm/arch/sys_proto.h>	28	#include <asm/arch/sys_proto.h>
29	#include <pwm.h>	29	#include <pwm.h>
30	#include <i2c.h>	30	#include <i2c.h>
31	#include <input.h>	31	#include <input.h>
32	#include <usb.h>	32	#include <usb.h>
33	#include <usb/ehci-ci.h>	33	#include <usb/ehci-ci.h>
34	#include <asm/arch/mx6-ddr.h>	34	#include <asm/arch/mx6-ddr.h>
35	#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)	35	#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
36	#include <lcd.h>	36	#include <lcd.h>
37	#include <mxc_epdc_fb.h>	37	#include <mxc_epdc_fb.h>
38	#endif	38	#endif
39	#ifdef CONFIG_SATA	39	#ifdef CONFIG_SATA
40	#include <asm/mach-imx/sata.h>	40	#include <asm/mach-imx/sata.h>
41	#endif	41	#endif
42	#ifdef CONFIG_FSL_FASTBOOT	42	#ifdef CONFIG_FSL_FASTBOOT
43	#include <fsl_fastboot.h>	43	#include <fsl_fastboot.h>
44	#ifdef CONFIG_ANDROID_RECOVERY	44	#ifdef CONFIG_ANDROID_RECOVERY
45	#include <recovery.h>	45	#include <recovery.h>
46	#endif	46	#endif
47	#endif /CONFIG_FSL_FASTBOOT/	47	#endif /CONFIG_FSL_FASTBOOT/
48		48
49	DECLARE_GLOBAL_DATA_PTR;	49	DECLARE_GLOBAL_DATA_PTR;
50		50
51	#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \	51	#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
52	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \	52	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
53	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)	53	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
54		54
55	#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| \	55	#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| \
56	PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_80ohm \| \	56	PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_80ohm \| \
57	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)	57	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
58		58
59	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \	59	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
60	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)	60	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
61		61
62	#define SPI_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_SPEED_MED \| \	62	#define SPI_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_SPEED_MED \| \
63	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST)	63	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST)
64		64
65	#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP \| \	65	#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP \| \
66	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \	66	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
67	PAD_CTL_SRE_SLOW)	67	PAD_CTL_SRE_SLOW)
68		68
69	#define I2C_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \	69	#define I2C_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
70	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \	70	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
71	PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \	71	PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
72	PAD_CTL_ODE \| PAD_CTL_SRE_FAST)	72	PAD_CTL_ODE \| PAD_CTL_SRE_FAST)
73		73
74	#define LCD_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_SPEED_HIGH \| \	74	#define LCD_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_SPEED_HIGH \| \
75	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST)	75	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST)
76		76
77	#define EPDC_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_SPEED_MED \| \	77	#define EPDC_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_SPEED_MED \| \
78	PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)	78	PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
79		79
80	#define OTG_ID_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \	80	#define OTG_ID_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
81	PAD_CTL_PUS_47K_UP \| PAD_CTL_SPEED_LOW \| \	81	PAD_CTL_PUS_47K_UP \| PAD_CTL_SPEED_LOW \| \
82	PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)	82	PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
83		83
84		84
85	#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP \| \	85	#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP \| \
86	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \	86	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
87	PAD_CTL_SRE_SLOW)	87	PAD_CTL_SRE_SLOW)
88		88
89	#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)	89	#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
90		90
91	#define DISP0_PWR_EN IMX_GPIO_NR(1, 02)	91	#define DISP0_PWR_EN IMX_GPIO_NR(1, 02)
92		92
93	#define OUTPUT_40OHM (PAD_CTL_SPEED_MED\|PAD_CTL_DSE_40ohm)	93	#define OUTPUT_40OHM (PAD_CTL_SPEED_MED\|PAD_CTL_DSE_40ohm)
94		94
95	int dram_init(void)	95	int dram_init(void)
96	{	96	{
97	gd->ram_size = imx_ddr_size();	97	gd->ram_size = imx_ddr_size();
98	return 0;	98	return 0;
99	}	99	}
100		100
101	/* SER0/UART1 */	101	/* SER0/UART1 */
102	iomux_v3_cfg_t const uart1_pads[] = {	102	iomux_v3_cfg_t const uart1_pads[] = {
103	IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),	103	IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
104	IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),	104	IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
105	IOMUX_PADS(PAD_EIM_D20__UART1_CTS_B \| MUX_PAD_CTRL(UART_PAD_CTRL)),	105	IOMUX_PADS(PAD_EIM_D20__UART1_CTS_B \| MUX_PAD_CTRL(UART_PAD_CTRL)),
106	IOMUX_PADS(PAD_EIM_D19__UART1_RTS_B \| MUX_PAD_CTRL(UART_PAD_CTRL)),	106	IOMUX_PADS(PAD_EIM_D19__UART1_RTS_B \| MUX_PAD_CTRL(UART_PAD_CTRL)),
107	};	107	};
108		108
109	/* SER1/UART2 */	109	/* SER1/UART2 */
110	iomux_v3_cfg_t const uart2_pads[] = {	110	iomux_v3_cfg_t const uart2_pads[] = {
111	IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),	111	IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
112	IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),	112	IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
113	};	113	};
114		114
115	/* SER2/UART4 */	115	/* SER2/UART4 */
116	iomux_v3_cfg_t const uart4_pads[] = {	116	iomux_v3_cfg_t const uart4_pads[] = {
117	IOMUX_PADS(PAD_CSI0_DAT12__UART4_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),	117	IOMUX_PADS(PAD_CSI0_DAT12__UART4_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
118	IOMUX_PADS(PAD_CSI0_DAT13__UART4_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),	118	IOMUX_PADS(PAD_CSI0_DAT13__UART4_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
119	IOMUX_PADS(PAD_CSI0_DAT16__UART4_CTS_B \| MUX_PAD_CTRL(UART_PAD_CTRL)),	119	IOMUX_PADS(PAD_CSI0_DAT16__UART4_CTS_B \| MUX_PAD_CTRL(UART_PAD_CTRL)),
120	IOMUX_PADS(PAD_CSI0_DAT17__UART4_RTS_B \| MUX_PAD_CTRL(UART_PAD_CTRL)),	120	IOMUX_PADS(PAD_CSI0_DAT17__UART4_RTS_B \| MUX_PAD_CTRL(UART_PAD_CTRL)),
121	};	121	};
122		122
123	/* SER3/UART5 Default Debug Port */	123	/* SER3/UART5 Default Debug Port */
124	iomux_v3_cfg_t const uart5_pads[] = {	124	iomux_v3_cfg_t const uart5_pads[] = {
125	IOMUX_PADS(PAD_CSI0_DAT14__UART5_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),	125	IOMUX_PADS(PAD_CSI0_DAT14__UART5_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
126	IOMUX_PADS(PAD_CSI0_DAT15__UART5_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),	126	IOMUX_PADS(PAD_CSI0_DAT15__UART5_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
127	};	127	};
128		128
129	iomux_v3_cfg_t const wdt_pads[] = {	129	iomux_v3_cfg_t const wdt_pads[] = {
130	IOMUX_PADS(PAD_EIM_D16__GPIO3_IO16 \| MUX_PAD_CTRL(NO_PAD_CTRL)),	130	IOMUX_PADS(PAD_EIM_D16__GPIO3_IO16 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
131	};	131	};
132		132
133	iomux_v3_cfg_t const reset_out_pads[] = {	133	iomux_v3_cfg_t const reset_out_pads[] = {
134	IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 \| MUX_PAD_CTRL(NO_PAD_CTRL)),	134	IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
135	};	135	};
136		136
137	static iomux_v3_cfg_t const enet_pads[] = {	137	static iomux_v3_cfg_t const enet_pads[] = {
138	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL)),	138	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
139	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),	139	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
140	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),	140	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
141	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),	141	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
142	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),	142	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
143	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),	143	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
144	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),	144	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
145	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL)),	145	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
146	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK \| MUX_PAD_CTRL(ENET_PAD_CTRL)),	146	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
147	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),	147	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
148	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),	148	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
149	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),	149	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
150	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),	150	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
151	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),	151	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
152	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL)),	152	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
153	};	153	};
154		154
155	static void setup_iomux_enet(void)	155	static void setup_iomux_enet(void)
156	{	156	{
157	SETUP_IOMUX_PADS(enet_pads);	157	SETUP_IOMUX_PADS(enet_pads);
158	gpio_request(IMX_GPIO_NR(4, 11), "ETH0_IRQ");	158	gpio_request(IMX_GPIO_NR(4, 11), "ETH0_IRQ");
159	gpio_direction_input(IMX_GPIO_NR(4, 11));	159	gpio_direction_input(IMX_GPIO_NR(4, 11));
160	}	160	}
161		161
162	/* SDIO */	162	/* SDIO */
163	static iomux_v3_cfg_t const usdhc2_pads[] = {	163	static iomux_v3_cfg_t const usdhc2_pads[] = {
164	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	164	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
165	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	165	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
166	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	166	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
167	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	167	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
168	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	168	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
169	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	169	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
170	IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */	170	IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
171	IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* WP */	171	IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* WP */
172	IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* SDIO_PWR_EN */	172	IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* SDIO_PWR_EN */
173	};	173	};
174		174
175	/* SDMMC */	175	/* SDMMC */
176	iomux_v3_cfg_t const usdhc3_pads[] = {	176	iomux_v3_cfg_t const usdhc3_pads[] = {
177	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	177	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
178	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	178	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
179	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	179	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
180	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	180	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
181	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	181	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
182	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	182	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
183	IOMUX_PADS(PAD_SD3_RST__SD3_RESET \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	183	IOMUX_PADS(PAD_SD3_RST__SD3_RESET \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
184	};	184	};
185		185
186	/* eMMC */	186	/* eMMC */
187	static iomux_v3_cfg_t const usdhc4_pads[] = {	187	static iomux_v3_cfg_t const usdhc4_pads[] = {
188	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	188	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
189	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	189	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
190	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	190	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
191	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	191	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
192	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	192	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
193	IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	193	IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
194	IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	194	IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
195	IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	195	IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
196	IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	196	IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
197	IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),	197	IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
198	};	198	};
199		199
200	#ifdef CONFIG_MXC_SPI	200	#ifdef CONFIG_MXC_SPI
201	/* SPI0 */	201	/* SPI0 */
202	iomux_v3_cfg_t const ecspi2_pads[] = {	202	iomux_v3_cfg_t const ecspi2_pads[] = {
203	IOMUX_PADS(PAD_CSI0_DAT8__ECSPI2_SCLK \| MUX_PAD_CTRL(SPI_PAD_CTRL)),	203	IOMUX_PADS(PAD_CSI0_DAT8__ECSPI2_SCLK \| MUX_PAD_CTRL(SPI_PAD_CTRL)),
204	IOMUX_PADS(PAD_CSI0_DAT10__ECSPI2_MISO \| MUX_PAD_CTRL(SPI_PAD_CTRL)),	204	IOMUX_PADS(PAD_CSI0_DAT10__ECSPI2_MISO \| MUX_PAD_CTRL(SPI_PAD_CTRL)),
205	IOMUX_PADS(PAD_CSI0_DAT9__ECSPI2_MOSI \| MUX_PAD_CTRL(SPI_PAD_CTRL)),	205	IOMUX_PADS(PAD_CSI0_DAT9__ECSPI2_MOSI \| MUX_PAD_CTRL(SPI_PAD_CTRL)),
206	IOMUX_PADS(PAD_CSI0_DAT11__GPIO5_IO29 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /SS0#/	206	IOMUX_PADS(PAD_CSI0_DAT11__GPIO5_IO29 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /SS0#/
207	IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /SS2#/	207	IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /SS2#/
208	IOMUX_PADS(PAD_EIM_D25__GPIO3_IO25 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /SS3#/	208	IOMUX_PADS(PAD_EIM_D25__GPIO3_IO25 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /SS3#/
209	};	209	};
210		210
211	static void setup_spinor(void)	211	static void setup_spinor(void)
212	{	212	{
213	SETUP_IOMUX_PADS(ecspi2_pads);	213	SETUP_IOMUX_PADS(ecspi2_pads);
214	gpio_request(IMX_GPIO_NR(5, 29), "ECSPI2 SS0");	214	gpio_request(IMX_GPIO_NR(5, 29), "ECSPI2 SS0");
215	gpio_request(IMX_GPIO_NR(3, 24), "ECSPI2 SS2");	215	gpio_request(IMX_GPIO_NR(3, 24), "ECSPI2 SS2");
216	gpio_request(IMX_GPIO_NR(3, 25), "ECSPI2 SS3");	216	gpio_request(IMX_GPIO_NR(3, 25), "ECSPI2 SS3");
217	}	217	}
218		218
219	int board_spi_cs_gpio(unsigned bus, unsigned cs)	219	int board_spi_cs_gpio(unsigned bus, unsigned cs)
220	{	220	{
221	return (bus == 1 && cs == 0) ? (IMX_GPIO_NR(5, 29)) : -1;	221	return (bus == 1 && cs == 0) ? (IMX_GPIO_NR(5, 29)) : -1;
222	return (bus == 1 && cs == 2) ? (IMX_GPIO_NR(3, 24)) : -1;	222	return (bus == 1 && cs == 2) ? (IMX_GPIO_NR(3, 24)) : -1;
223	return (bus == 1 && cs == 3) ? (IMX_GPIO_NR(3, 25)) : -1;	223	return (bus == 1 && cs == 3) ? (IMX_GPIO_NR(3, 25)) : -1;
224	}	224	}
225	#endif	225	#endif
226		226
227	/* SPI1 */	227	/* SPI1 */
228	iomux_v3_cfg_t const ecspi1_pads[] = {	228	iomux_v3_cfg_t const ecspi1_pads[] = {
229	IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK \| MUX_PAD_CTRL(SPI_PAD_CTRL)),	229	IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK \| MUX_PAD_CTRL(SPI_PAD_CTRL)),
230	IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO \| MUX_PAD_CTRL(SPI_PAD_CTRL)),	230	IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO \| MUX_PAD_CTRL(SPI_PAD_CTRL)),
231	IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI \| MUX_PAD_CTRL(SPI_PAD_CTRL)),	231	IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI \| MUX_PAD_CTRL(SPI_PAD_CTRL)),
232	IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /SS0#/	232	IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /SS0#/
233	IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /SS1#/	233	IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /SS1#/
234	};	234	};
235		235
236	static iomux_v3_cfg_t const rgb_pads[] = {	236	static iomux_v3_cfg_t const rgb_pads[] = {
237	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	237	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
238	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	238	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
239	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	239	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
240	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	240	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
241	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 \| MUX_PAD_CTRL(LCD_PAD_CTRL)), /* DISP0_DRDY */	241	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 \| MUX_PAD_CTRL(LCD_PAD_CTRL)), /* DISP0_DRDY */
242	IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	242	IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
243	IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	243	IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
244	IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	244	IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
245	IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	245	IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
246	IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	246	IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
247	IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	247	IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
248	IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	248	IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
249	IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	249	IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
250	IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	250	IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
251	IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	251	IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
252	IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	252	IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
253	IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	253	IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
254	IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	254	IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
255	IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	255	IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
256	IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	256	IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
257	IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	257	IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
258	IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	258	IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
259	IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	259	IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
260	IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	260	IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
261	IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	261	IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
262	IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	262	IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
263	IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	263	IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
264	IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),	264	IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 \| MUX_PAD_CTRL(LCD_PAD_CTRL)),
265	/* LCD VDD Enable(for parallel LCD): S133 */	265	/* LCD VDD Enable(for parallel LCD): S133 */
266	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 \| MUX_PAD_CTRL(NO_PAD_CTRL)),	266	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
267	};	267	};
268		268
269	static iomux_v3_cfg_t const backlight_pads[] = {	269	static iomux_v3_cfg_t const backlight_pads[] = {
270	/* Backlight Enable for RGB: S127 */	270	/* Backlight Enable for RGB: S127 */
271	#define BACKLIGHT_EN IMX_GPIO_NR(1, 00)	271	#define BACKLIGHT_EN IMX_GPIO_NR(1, 00)
272	IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 \| MUX_PAD_CTRL(NO_PAD_CTRL)),	272	IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
273	/* PWM Backlight Control: S141 */	273	/* PWM Backlight Control: S141 */
274	IOMUX_PADS(PAD_GPIO_1__PWM2_OUT \| MUX_PAD_CTRL(NO_PAD_CTRL)),	274	IOMUX_PADS(PAD_GPIO_1__PWM2_OUT \| MUX_PAD_CTRL(NO_PAD_CTRL)),
275	};	275	};
276		276
277	static void enable_backlight(void)	277	static void enable_backlight(void)
278	{	278	{
279	SETUP_IOMUX_PADS(backlight_pads);	279	SETUP_IOMUX_PADS(backlight_pads);
280	gpio_request(DISP0_PWR_EN, "Display Power Enable");	280	gpio_request(DISP0_PWR_EN, "Display Power Enable");
281	gpio_direction_output(DISP0_PWR_EN, 1);	281	gpio_direction_output(DISP0_PWR_EN, 1);
282	/* enable backlight PWM 2 */	282	/* enable backlight PWM 2 */
283	if (pwm_init(1, 0, 0))	283	if (pwm_init(1, 0, 0))
284	goto error;	284	goto error;
285	/* duty cycle 500ns, period: 3000ns */	285	/* duty cycle 500ns, period: 3000ns */
286	if (pwm_config(1, 1000, 3000))	286	if (pwm_config(1, 1000, 3000))
287	goto error;	287	goto error;
288	if (pwm_enable(1))	288	if (pwm_enable(1))
289	goto error;	289	goto error;
290	return;	290	return;
291		291
292	error:	292	error:
293	puts("error init pwm for backlight\n");	293	puts("error init pwm for backlight\n");
294	return;	294	return;
295	}	295	}
296		296
297	static void enable_rgb(struct display_info_t const *dev)	297	static void enable_rgb(struct display_info_t const *dev)
298	{	298	{
299	SETUP_IOMUX_PADS(rgb_pads);	299	SETUP_IOMUX_PADS(rgb_pads);
300		300
301	gpio_request(DISP0_PWR_EN, "Display Power Enable");	301	gpio_request(DISP0_PWR_EN, "Display Power Enable");
302	gpio_direction_output(DISP0_PWR_EN, 1);	302	gpio_direction_output(DISP0_PWR_EN, 1);
303	enable_backlight();	303	enable_backlight();
304	}	304	}
305		305
306	static void enable_lvds(struct display_info_t const *dev)	306	static void enable_lvds(struct display_info_t const *dev)
307	{	307	{
308	struct iomuxc iomux = (struct iomuxc )	308	struct iomuxc iomux = (struct iomuxc )
309	IOMUXC_BASE_ADDR;	309	IOMUXC_BASE_ADDR;
310	u32 reg = readl(&iomux->gpr[2]);	310	u32 reg = readl(&iomux->gpr[2]);
311	reg \|= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;	311	reg \|= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
312	writel(reg, &iomux->gpr[2]);	312	writel(reg, &iomux->gpr[2]);
313		313
314	enable_backlight();	314	enable_backlight();
315	}	315	}
316		316
317	#ifdef CONFIG_SYS_I2C	317	#ifdef CONFIG_SYS_I2C
318	/I2C1 I2C_PM/	318	/I2C1 I2C_PM/
319	struct i2c_pads_info i2c_pad_info1 = {	319	struct i2c_pads_info i2c_pad_info1 = {
320	.scl = {	320	.scl = {
321	.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL \| I2C_PAD,	321	.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL \| I2C_PAD,
322	.gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 \| I2C_PAD,	322	.gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 \| I2C_PAD,
323	.gp = IMX_GPIO_NR(3, 21)	323	.gp = IMX_GPIO_NR(3, 21)
324	},	324	},
325	.sda = {	325	.sda = {
326	.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA \| I2C_PAD,	326	.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA \| I2C_PAD,
327	.gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 \| I2C_PAD,	327	.gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 \| I2C_PAD,
328	.gp = IMX_GPIO_NR(3, 28)	328	.gp = IMX_GPIO_NR(3, 28)
329	}	329	}
330	};	330	};
331		331
332	/* I2C2 HDMI */	332	/* I2C2 HDMI */
333	struct i2c_pads_info i2c_pad_info2 = {	333	struct i2c_pads_info i2c_pad_info2 = {
334	.scl = {	334	.scl = {
335	.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL \| I2C_PAD,	335	.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL \| I2C_PAD,
336	.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 \| I2C_PAD,	336	.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 \| I2C_PAD,
337	.gp = IMX_GPIO_NR(4, 12)	337	.gp = IMX_GPIO_NR(4, 12)
338	},	338	},
339	.sda = {	339	.sda = {
340	.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA \| I2C_PAD,	340	.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA \| I2C_PAD,
341	.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 \| I2C_PAD,	341	.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 \| I2C_PAD,
342	.gp = IMX_GPIO_NR(4, 13)	342	.gp = IMX_GPIO_NR(4, 13)
343	}	343	}
344	};	344	};
345		345
346	/* I2C3 TCA9546APWR */	346	/* I2C3 TCA9546APWR */
347	struct i2c_pads_info i2c_pad_info3 = {	347	struct i2c_pads_info i2c_pad_info3 = {
348	.scl = {	348	.scl = {
349	.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL \| I2C_PAD,	349	.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL \| I2C_PAD,
350	.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 \| I2C_PAD,	350	.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 \| I2C_PAD,
351	.gp = IMX_GPIO_NR(3, 17)	351	.gp = IMX_GPIO_NR(3, 17)
352	},	352	},
353	.sda = {	353	.sda = {
354	.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA \| I2C_PAD,	354	.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA \| I2C_PAD,
355	.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 \| I2C_PAD,	355	.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 \| I2C_PAD,
356	.gp = IMX_GPIO_NR(3, 18)	356	.gp = IMX_GPIO_NR(3, 18)
357	}	357	}
358	};	358	};
359	#endif	359	#endif
360		360
361	#ifdef CONFIG_PCIE_IMX	361	#ifdef CONFIG_PCIE_IMX
362	iomux_v3_cfg_t const pcie_pads[] = {	362	iomux_v3_cfg_t const pcie_pads[] = {
363	IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* PCIe Present */	363	IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* PCIe Present */
364	IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* PCIe_WAKE# */	364	IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* PCIe_WAKE# */
365	IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */	365	IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */
366	IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* PCIe Clock Request */	366	IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* PCIe Clock Request */
367	};	367	};
368		368
369	static void setup_pcie(void)	369	static void setup_pcie(void)
370	{	370	{
371	SETUP_IOMUX_PADS(pcie_pads);	371	SETUP_IOMUX_PADS(pcie_pads);
372	gpio_request(IMX_GPIO_NR(1, 16), "PCIE_A_CLK_REQ");	372	gpio_request(IMX_GPIO_NR(1, 16), "PCIE_A_CLK_REQ");
373	gpio_direction_input(IMX_GPIO_NR(1, 16));	373	gpio_direction_input(IMX_GPIO_NR(1, 16));
374	gpio_request(IMX_GPIO_NR(1, 17), "PCIE_A_PRSNT");	374	gpio_request(IMX_GPIO_NR(1, 17), "PCIE_A_PRSNT");
375	gpio_direction_input(IMX_GPIO_NR(1, 17));	375	gpio_direction_input(IMX_GPIO_NR(1, 17));
376	gpio_request(IMX_GPIO_NR(1, 19), "PCIE_A_WAKE");	376	gpio_request(IMX_GPIO_NR(1, 19), "PCIE_A_WAKE");
377	gpio_direction_input(IMX_GPIO_NR(1, 19));	377	gpio_direction_input(IMX_GPIO_NR(1, 19));
378	gpio_request(IMX_GPIO_NR(1, 20), "PCIE_RST#");	378	gpio_request(IMX_GPIO_NR(1, 20), "PCIE_RST#");
379	gpio_direction_output(IMX_GPIO_NR(1, 20), 0);	379	gpio_direction_output(IMX_GPIO_NR(1, 20), 0);
380	udelay(500);	380	udelay(500);
381	gpio_direction_output(IMX_GPIO_NR(1, 20), 1);	381	gpio_direction_output(IMX_GPIO_NR(1, 20), 1);
382	}	382	}
383	#endif	383	#endif
384		384
385	iomux_v3_cfg_t const di0_pads[] = {	385	iomux_v3_cfg_t const di0_pads[] = {
386	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */	386	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */
387	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* DISP0_HSYNC */	387	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* DISP0_HSYNC */
388	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* DISP0_VSYNC */	388	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* DISP0_VSYNC */
389	};	389	};
390		390
391	/* CAN0/FLEXCAN1 */	391	/* CAN0/FLEXCAN1 */
392	iomux_v3_cfg_t const flexcan1_pads[] = {	392	iomux_v3_cfg_t const flexcan1_pads[] = {
393		393
394	IOMUX_PADS(PAD_GPIO_7__FLEXCAN1_TX \| MUX_PAD_CTRL(WEAK_PULLUP)),	394	IOMUX_PADS(PAD_GPIO_7__FLEXCAN1_TX \| MUX_PAD_CTRL(WEAK_PULLUP)),
395	IOMUX_PADS(PAD_GPIO_8__FLEXCAN1_RX \| MUX_PAD_CTRL(WEAK_PULLUP)),	395	IOMUX_PADS(PAD_GPIO_8__FLEXCAN1_RX \| MUX_PAD_CTRL(WEAK_PULLUP)),
396	};	396	};
397		397
398	/* CAN1/FLEXCAN2 */	398	/* CAN1/FLEXCAN2 */
399	iomux_v3_cfg_t const flexcan2_pads[] = {	399	iomux_v3_cfg_t const flexcan2_pads[] = {
400	IOMUX_PADS(PAD_KEY_COL4__FLEXCAN2_TX \| MUX_PAD_CTRL(WEAK_PULLUP)),	400	IOMUX_PADS(PAD_KEY_COL4__FLEXCAN2_TX \| MUX_PAD_CTRL(WEAK_PULLUP)),
401	IOMUX_PADS(PAD_KEY_ROW4__FLEXCAN2_RX \| MUX_PAD_CTRL(WEAK_PULLUP)),	401	IOMUX_PADS(PAD_KEY_ROW4__FLEXCAN2_RX \| MUX_PAD_CTRL(WEAK_PULLUP)),
402	};	402	};
403		403
404	/* GPIOs */	404	/* GPIOs */
405	iomux_v3_cfg_t const gpios_pads[] = {	405	iomux_v3_cfg_t const gpios_pads[] = {
406	IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO0 */	406	IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO0 */
407	IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO1 */	407	IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO1 */
408	IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO2 */	408	IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO2 */
409	IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO3 */	409	IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO3 */
410	IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO4 */	410	IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO4 */
411	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO6 */	411	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO6 */
412	IOMUX_PADS(PAD_NANDF_CLE__GPIO6_IO07 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO7 */	412	IOMUX_PADS(PAD_NANDF_CLE__GPIO6_IO07 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO7 */
413	IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO8 */	413	IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO8 */
414	IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO9 */	414	IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO9 */
415	IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO10 */	415	IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO10 */
416	IOMUX_PADS(PAD_NANDF_ALE__GPIO6_IO08 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO11 */	416	IOMUX_PADS(PAD_NANDF_ALE__GPIO6_IO08 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* GPIO11 */
417	};	417	};
418		418
419	/* Misc. pins */	419	/* Misc. pins */
420	static iomux_v3_cfg_t const misc_pads[] = {	420	static iomux_v3_cfg_t const misc_pads[] = {
421	IOMUX_PADS(PAD_EIM_CS0__GPIO2_IO23 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* SLEEP# */	421	IOMUX_PADS(PAD_EIM_CS0__GPIO2_IO23 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* SLEEP# */
422	IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* CHARGER_PRSNT# */	422	IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* CHARGER_PRSNT# */
423	IOMUX_PADS(PAD_EIM_CS1__GPIO2_IO24 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* CHARGING# */	423	IOMUX_PADS(PAD_EIM_CS1__GPIO2_IO24 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* CHARGING# */
424	IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* CARRIER_STBY# */	424	IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* CARRIER_STBY# */
425	IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* BATLOW# */	425	IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 \| MUX_PAD_CTRL(WEAK_PULLUP)), /* BATLOW# */
426	};	426	};
427		427
428	static void setup_iomux_uart1(void)	428	static void setup_iomux_uart1(void)
429	{	429	{
430	SETUP_IOMUX_PADS(uart1_pads);	430	SETUP_IOMUX_PADS(uart1_pads);
431	}	431	}
432		432
433	static void setup_iomux_uart2(void)	433	static void setup_iomux_uart2(void)
434	{	434	{
435	SETUP_IOMUX_PADS(uart2_pads);	435	SETUP_IOMUX_PADS(uart2_pads);
436	}	436	}
437		437
438	static void setup_iomux_uart4(void)	438	static void setup_iomux_uart4(void)
439	{	439	{
440	SETUP_IOMUX_PADS(uart4_pads);	440	SETUP_IOMUX_PADS(uart4_pads);
441	}	441	}
442		442
443	static void setup_iomux_uart5(void)	443	static void setup_iomux_uart5(void)
444	{	444	{
445	SETUP_IOMUX_PADS(uart5_pads);	445	SETUP_IOMUX_PADS(uart5_pads);
446	}	446	}
447		447
448	static void setup_iomux_wdt(void)	448	static void setup_iomux_wdt(void)
449	{	449	{
450	SETUP_IOMUX_PADS(wdt_pads);	450	SETUP_IOMUX_PADS(wdt_pads);
451	/* Set HW_WDT as Output High*/	451	/* Set HW_WDT as Output High*/
452	gpio_request(IMX_GPIO_NR(3, 16), "WDT_ENABLE");	452	gpio_request(IMX_GPIO_NR(3, 16), "WDT_ENABLE");
453	gpio_direction_output(IMX_GPIO_NR(3, 16) , 1);	453	gpio_direction_output(IMX_GPIO_NR(3, 16) , 1);
454	}	454	}
455		455
456	static void setup_iomux_reset_out(void)	456	static void setup_iomux_reset_out(void)
457	{	457	{
458	SETUP_IOMUX_PADS(reset_out_pads);	458	SETUP_IOMUX_PADS(reset_out_pads);
459	/* Set CPU RESET_OUT as Output */	459	/* Set CPU RESET_OUT as Output */
460	gpio_request(IMX_GPIO_NR(6, 16), "CPU_RESET");	460	gpio_request(IMX_GPIO_NR(6, 16), "CPU_RESET");
461	gpio_direction_output(IMX_GPIO_NR(6, 16) , 0);	461	gpio_direction_output(IMX_GPIO_NR(6, 16) , 0);
462	}	462	}
463		463
464	static void setup_spi1(void)	464	static void setup_spi1(void)
465	{	465	{
466	SETUP_IOMUX_PADS(ecspi1_pads);	466	SETUP_IOMUX_PADS(ecspi1_pads);
467	gpio_request(IMX_GPIO_NR(4, 9), "EXSPI1_SS0");	467	gpio_request(IMX_GPIO_NR(4, 9), "EXSPI1_SS0");
468	gpio_request(IMX_GPIO_NR(4, 10), "ECSPI1_SS1");	468	gpio_request(IMX_GPIO_NR(4, 10), "ECSPI1_SS1");
469	}	469	}
470		470
471	int board_spi1_cs_gpio(unsigned bus, unsigned cs)	471	int board_spi1_cs_gpio(unsigned bus, unsigned cs)
472	{	472	{
473	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;	473	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
474	return (bus == 0 && cs == 1) ? (IMX_GPIO_NR(4, 10)) : -1;	474	return (bus == 0 && cs == 1) ? (IMX_GPIO_NR(4, 10)) : -1;
475	}	475	}
476		476
477	static void setup_flexcan1(void)	477	static void setup_flexcan1(void)
478	{	478	{
479	SETUP_IOMUX_PADS(flexcan1_pads);	479	SETUP_IOMUX_PADS(flexcan1_pads);
480	}	480	}
481		481
482	static void setup_flexcan2(void)	482	static void setup_flexcan2(void)
483	{	483	{
484	SETUP_IOMUX_PADS(flexcan2_pads);	484	SETUP_IOMUX_PADS(flexcan2_pads);
485	}	485	}
486		486
487	static void setup_gpios(void)	487	static void setup_gpios(void)
488	{	488	{
489	SETUP_IOMUX_PADS(gpios_pads);	489	SETUP_IOMUX_PADS(gpios_pads);
490	gpio_request(IMX_GPIO_NR(6, 11), "GPIO0");	490	gpio_request(IMX_GPIO_NR(6, 11), "GPIO0");
491	gpio_direction_output(IMX_GPIO_NR(6, 11), 0);	491	gpio_direction_output(IMX_GPIO_NR(6, 11), 0);
492	gpio_request(IMX_GPIO_NR(2, 02), "GPIO1");	492	gpio_request(IMX_GPIO_NR(2, 02), "GPIO1");
493	gpio_direction_output(IMX_GPIO_NR(2, 02), 0);	493	gpio_direction_output(IMX_GPIO_NR(2, 02), 0);
494	gpio_request(IMX_GPIO_NR(2, 06), "GPIO2");	494	gpio_request(IMX_GPIO_NR(2, 06), "GPIO2");
495	gpio_direction_output(IMX_GPIO_NR(2, 06), 0);	495	gpio_direction_output(IMX_GPIO_NR(2, 06), 0);
496	gpio_request(IMX_GPIO_NR(2, 03), "GPIO3");	496	gpio_request(IMX_GPIO_NR(2, 03), "GPIO3");
497	gpio_direction_output(IMX_GPIO_NR(2, 03), 0);	497	gpio_direction_output(IMX_GPIO_NR(2, 03), 0);
498	gpio_request(IMX_GPIO_NR(2, 07), "GPIO4");	498	gpio_request(IMX_GPIO_NR(2, 07), "GPIO4");
499	gpio_direction_output(IMX_GPIO_NR(2, 07), 0);	499	gpio_direction_output(IMX_GPIO_NR(2, 07), 0);
500	gpio_request(IMX_GPIO_NR(6, 14), "GPIO6");	500	gpio_request(IMX_GPIO_NR(6, 14), "GPIO6");
501	gpio_direction_input(IMX_GPIO_NR(6, 14));	501	gpio_direction_input(IMX_GPIO_NR(6, 14));
502	gpio_request(IMX_GPIO_NR(6, 07), "GPIO7");	502	gpio_request(IMX_GPIO_NR(6, 07), "GPIO7");
503	gpio_direction_input(IMX_GPIO_NR(6, 07));	503	gpio_direction_input(IMX_GPIO_NR(6, 07));
504	gpio_request(IMX_GPIO_NR(2, 04), "GPIO8");	504	gpio_request(IMX_GPIO_NR(2, 04), "GPIO8");
505	gpio_direction_input(IMX_GPIO_NR(2, 04));	505	gpio_direction_input(IMX_GPIO_NR(2, 04));
506	gpio_request(IMX_GPIO_NR(2, 00), "GPIO9");	506	gpio_request(IMX_GPIO_NR(2, 00), "GPIO9");
507	gpio_direction_input(IMX_GPIO_NR(2, 00));	507	gpio_direction_input(IMX_GPIO_NR(2, 00));
508	gpio_request(IMX_GPIO_NR(2, 05), "GPIO10");	508	gpio_request(IMX_GPIO_NR(2, 05), "GPIO10");
509	gpio_direction_input(IMX_GPIO_NR(2, 05));	509	gpio_direction_input(IMX_GPIO_NR(2, 05));
510	gpio_request(IMX_GPIO_NR(6, 8), "GPIO11");	510	gpio_request(IMX_GPIO_NR(6, 8), "GPIO11");
511	gpio_direction_input(IMX_GPIO_NR(6, 8));	511	gpio_direction_input(IMX_GPIO_NR(6, 8));
512	}	512	}
513		513
514	static void setup_misc(void)	514	static void setup_misc(void)
515	{	515	{
516	SETUP_IOMUX_PADS(misc_pads);	516	SETUP_IOMUX_PADS(misc_pads);
517	gpio_request(IMX_GPIO_NR(2, 23), "SLEEP#");	517	gpio_request(IMX_GPIO_NR(2, 23), "SLEEP#");
518	gpio_direction_input(IMX_GPIO_NR(2, 23));	518	gpio_direction_input(IMX_GPIO_NR(2, 23));
519	gpio_request(IMX_GPIO_NR(2, 24), "CHARGING#");	519	gpio_request(IMX_GPIO_NR(2, 24), "CHARGING#");
520	gpio_direction_input(IMX_GPIO_NR(2, 24));	520	gpio_direction_input(IMX_GPIO_NR(2, 24));
521	gpio_request(IMX_GPIO_NR(3, 22), "CHARGER_PRSNT#");	521	gpio_request(IMX_GPIO_NR(3, 22), "CHARGER_PRSNT#");
522	gpio_direction_input(IMX_GPIO_NR(3, 22));	522	gpio_direction_input(IMX_GPIO_NR(3, 22));
523	gpio_request(IMX_GPIO_NR(3, 29), "BATLOW#");	523	gpio_request(IMX_GPIO_NR(3, 29), "BATLOW#");
524	gpio_direction_input(IMX_GPIO_NR(3, 29));	524	gpio_direction_input(IMX_GPIO_NR(3, 29));
525	gpio_request(IMX_GPIO_NR(7, 13), "CARRIER_STBY#");	525	gpio_request(IMX_GPIO_NR(7, 13), "CARRIER_STBY#");
526	gpio_direction_output(IMX_GPIO_NR(7, 13), 1);	526	gpio_direction_output(IMX_GPIO_NR(7, 13), 1);
527	}	527	}
528		528
529	#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)	529	#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
530	static iomux_v3_cfg_t const epdc_enable_pads[] = {	530	static iomux_v3_cfg_t const epdc_enable_pads[] = {
531	IOMUX_PADS(PAD_EIM_A16__EPDC_DATA00 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	531	IOMUX_PADS(PAD_EIM_A16__EPDC_DATA00 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
532	IOMUX_PADS(PAD_EIM_DA10__EPDC_DATA01 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	532	IOMUX_PADS(PAD_EIM_DA10__EPDC_DATA01 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
533	IOMUX_PADS(PAD_EIM_DA12__EPDC_DATA02 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	533	IOMUX_PADS(PAD_EIM_DA12__EPDC_DATA02 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
534	IOMUX_PADS(PAD_EIM_DA11__EPDC_DATA03 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	534	IOMUX_PADS(PAD_EIM_DA11__EPDC_DATA03 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
535	IOMUX_PADS(PAD_EIM_LBA__EPDC_DATA04 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	535	IOMUX_PADS(PAD_EIM_LBA__EPDC_DATA04 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
536	IOMUX_PADS(PAD_EIM_EB2__EPDC_DATA05 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	536	IOMUX_PADS(PAD_EIM_EB2__EPDC_DATA05 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
537	IOMUX_PADS(PAD_EIM_CS0__EPDC_DATA06 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	537	IOMUX_PADS(PAD_EIM_CS0__EPDC_DATA06 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
538	IOMUX_PADS(PAD_EIM_RW__EPDC_DATA07 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	538	IOMUX_PADS(PAD_EIM_RW__EPDC_DATA07 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
539	IOMUX_PADS(PAD_EIM_A21__EPDC_GDCLK \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	539	IOMUX_PADS(PAD_EIM_A21__EPDC_GDCLK \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
540	IOMUX_PADS(PAD_EIM_A22__EPDC_GDSP \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	540	IOMUX_PADS(PAD_EIM_A22__EPDC_GDSP \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
541	IOMUX_PADS(PAD_EIM_A23__EPDC_GDOE \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	541	IOMUX_PADS(PAD_EIM_A23__EPDC_GDOE \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
542	IOMUX_PADS(PAD_EIM_A24__EPDC_GDRL \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	542	IOMUX_PADS(PAD_EIM_A24__EPDC_GDRL \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
543	IOMUX_PADS(PAD_EIM_D31__EPDC_SDCLK_P \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	543	IOMUX_PADS(PAD_EIM_D31__EPDC_SDCLK_P \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
544	IOMUX_PADS(PAD_EIM_D27__EPDC_SDOE \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	544	IOMUX_PADS(PAD_EIM_D27__EPDC_SDOE \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
545	IOMUX_PADS(PAD_EIM_DA1__EPDC_SDLE \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	545	IOMUX_PADS(PAD_EIM_DA1__EPDC_SDLE \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
546	IOMUX_PADS(PAD_EIM_EB1__EPDC_SDSHR \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	546	IOMUX_PADS(PAD_EIM_EB1__EPDC_SDSHR \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
547	IOMUX_PADS(PAD_EIM_DA2__EPDC_BDR0 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	547	IOMUX_PADS(PAD_EIM_DA2__EPDC_BDR0 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
548	IOMUX_PADS(PAD_EIM_DA4__EPDC_SDCE0 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	548	IOMUX_PADS(PAD_EIM_DA4__EPDC_SDCE0 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
549	IOMUX_PADS(PAD_EIM_DA5__EPDC_SDCE1 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	549	IOMUX_PADS(PAD_EIM_DA5__EPDC_SDCE1 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
550	IOMUX_PADS(PAD_EIM_DA6__EPDC_SDCE2 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	550	IOMUX_PADS(PAD_EIM_DA6__EPDC_SDCE2 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
551	};	551	};
552		552
553	static iomux_v3_cfg_t const epdc_disable_pads[] = {	553	static iomux_v3_cfg_t const epdc_disable_pads[] = {
554	IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22),	554	IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22),
555	IOMUX_PADS(PAD_EIM_DA10__GPIO3_IO10),	555	IOMUX_PADS(PAD_EIM_DA10__GPIO3_IO10),
556	IOMUX_PADS(PAD_EIM_DA12__GPIO3_IO12),	556	IOMUX_PADS(PAD_EIM_DA12__GPIO3_IO12),
557	IOMUX_PADS(PAD_EIM_DA11__GPIO3_IO11),	557	IOMUX_PADS(PAD_EIM_DA11__GPIO3_IO11),
558	IOMUX_PADS(PAD_EIM_LBA__GPIO2_IO27),	558	IOMUX_PADS(PAD_EIM_LBA__GPIO2_IO27),
559	IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30),	559	IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30),
560	IOMUX_PADS(PAD_EIM_CS0__GPIO2_IO23),	560	IOMUX_PADS(PAD_EIM_CS0__GPIO2_IO23),
561	IOMUX_PADS(PAD_EIM_RW__GPIO2_IO26),	561	IOMUX_PADS(PAD_EIM_RW__GPIO2_IO26),
562	IOMUX_PADS(PAD_EIM_A21__GPIO2_IO17),	562	IOMUX_PADS(PAD_EIM_A21__GPIO2_IO17),
563	IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16),	563	IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16),
564	IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06),	564	IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06),
565	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04),	565	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04),
566	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31),	566	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31),
567	IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27),	567	IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27),
568	IOMUX_PADS(PAD_EIM_DA1__GPIO3_IO01),	568	IOMUX_PADS(PAD_EIM_DA1__GPIO3_IO01),
569	IOMUX_PADS(PAD_EIM_EB1__GPIO2_IO29),	569	IOMUX_PADS(PAD_EIM_EB1__GPIO2_IO29),
570	IOMUX_PADS(PAD_EIM_DA2__GPIO3_IO02),	570	IOMUX_PADS(PAD_EIM_DA2__GPIO3_IO02),
571	IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04),	571	IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04),
572	IOMUX_PADS(PAD_EIM_DA5__GPIO3_IO05),	572	IOMUX_PADS(PAD_EIM_DA5__GPIO3_IO05),
573	IOMUX_PADS(PAD_EIM_DA6__GPIO3_IO06),	573	IOMUX_PADS(PAD_EIM_DA6__GPIO3_IO06),
574	};	574	};
575	#endif	575	#endif
576		576
577	#ifdef CONFIG_FSL_ESDHC	577	#ifdef CONFIG_FSL_ESDHC
578	struct fsl_esdhc_cfg usdhc_cfg[3] = {	578	struct fsl_esdhc_cfg usdhc_cfg[3] = {
579	{USDHC2_BASE_ADDR},	579	{USDHC2_BASE_ADDR},
580	{USDHC3_BASE_ADDR},	580	{USDHC3_BASE_ADDR},
581	{USDHC4_BASE_ADDR},	581	{USDHC4_BASE_ADDR},
582	};	582	};
583		583
584	#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 28)	584	#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 28)
585		585
586	int board_mmc_get_env_dev(int devno)	586	int board_mmc_get_env_dev(int devno)
587	{	587	{
588	return devno - 1;	588	return devno - 1;
589	}	589	}
590		590
591	int mmc_map_to_kernel_blk(int devno)	591	int mmc_map_to_kernel_blk(int devno)
592	{	592	{
593	return devno + 1;	593	return devno + 1;
594	}	594	}
595		595
596	int board_mmc_getcd(struct mmc *mmc)	596	int board_mmc_getcd(struct mmc *mmc)
597	{	597	{
598	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;	598	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
599	int ret = 0;	599	int ret = 0;
600		600
601	switch (cfg->esdhc_base) {	601	switch (cfg->esdhc_base) {
602	case USDHC2_BASE_ADDR:	602	case USDHC2_BASE_ADDR:
603	ret = !gpio_get_value(USDHC2_CD_GPIO);	603	ret = !gpio_get_value(USDHC2_CD_GPIO);
604	break;	604	break;
605	case USDHC3_BASE_ADDR:	605	case USDHC3_BASE_ADDR:
606	/ret = !gpio_get_value(USDHC3_CD_GPIO);/	606	/ret = !gpio_get_value(USDHC3_CD_GPIO);/
607	break;	607	break;
608	case USDHC4_BASE_ADDR:	608	case USDHC4_BASE_ADDR:
609	ret = 1; /* eMMC/uSDHC4 is always present */	609	ret = 1; /* eMMC/uSDHC4 is always present */
610	break;	610	break;
611	}	611	}
612		612
613	return ret;	613	return ret;
614	}	614	}
615		615
616	int board_mmc_init(bd_t *bis)	616	int board_mmc_init(bd_t *bis)
617	{	617	{
618	#ifndef CONFIG_SPL_BUILD	618	#ifndef CONFIG_SPL_BUILD
619	int ret;	619	int ret;
620	int i;	620	int i;
621		621
622	/*	622	/*
623	* According to the board_mmc_init() the following map is done:	623	* According to the board_mmc_init() the following map is done:
624	* (U-Boot device node) (Physical Port)	624	* (U-Boot device node) (Physical Port)
625	* mmc0 SDIO	625	* mmc0 SDIO
626	* mmc1 SDMMC	626	* mmc1 SDMMC
627	* mmc2 eMMC	627	* mmc2 eMMC
628	*/	628	*/
629	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {	629	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
630	switch (i) {	630	switch (i) {
631	case 0:	631	case 0:
632	SETUP_IOMUX_PADS(usdhc2_pads);	632	SETUP_IOMUX_PADS(usdhc2_pads);
633	gpio_request(USDHC2_CD_GPIO, "USDHC2 CD");	633	gpio_request(USDHC2_CD_GPIO, "USDHC2 CD");
634	gpio_direction_input(USDHC2_CD_GPIO);	634	gpio_direction_input(USDHC2_CD_GPIO);
635	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);	635	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
636	break;	636	break;
637	case 1:	637	case 1:
638	SETUP_IOMUX_PADS(usdhc3_pads);	638	SETUP_IOMUX_PADS(usdhc3_pads);
639	/*gpio_request(USDHC3_CD_GPIO, "USDHC3 CD");	639	/*gpio_request(USDHC3_CD_GPIO, "USDHC3 CD");
640	gpio_direction_input(USDHC3_CD_GPIO);*/	640	gpio_direction_input(USDHC3_CD_GPIO);*/
641	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);	641	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
642	break;	642	break;
643	case 2:	643	case 2:
644	SETUP_IOMUX_PADS(usdhc4_pads);	644	SETUP_IOMUX_PADS(usdhc4_pads);
645	usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);	645	usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
646	break;	646	break;
647	default:	647	default:
648	printf("Warning: you configured more USDHC controllers"	648	printf("Warning: you configured more USDHC controllers"
649	"(%d) then supported by the board (%d)\n",	649	"(%d) then supported by the board (%d)\n",
650	i + 1, CONFIG_SYS_FSL_USDHC_NUM);	650	i + 1, CONFIG_SYS_FSL_USDHC_NUM);
651	return -EINVAL;	651	return -EINVAL;
652	}	652	}
653		653
654	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);	654	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
655	if (ret)	655	if (ret)
656	return ret;	656	return ret;
657	}	657	}
658		658
659	return 0;	659	return 0;
660	#else	660	#else
661	struct src psrc = (struct src )SRC_BASE_ADDR;	661	struct src psrc = (struct src )SRC_BASE_ADDR;
662	unsigned reg = readl(&psrc->sbmr1) >> 11;	662	unsigned reg = readl(&psrc->sbmr1) >> 11;
663	/*	663	/*
664	* Upon reading BOOT_CFG register the following map is done:	664	* Upon reading BOOT_CFG register the following map is done:
665	* Bit 11 and 12 of BOOT_CFG register can determine the current	665	* Bit 11 and 12 of BOOT_CFG register can determine the current
666	* mmc port	666	* mmc port
667	* 0x1 SD1	667	* 0x1 SD1
668	* 0x2 SD2	668	* 0x2 SD2
669	* 0x3 SD4	669	* 0x3 SD4
670	*/	670	*/
671		671
672	switch (reg & 0x3) {	672	switch (reg & 0x3) {
673	case 0x1:	673	case 0x1:
674	SETUP_IOMUX_PADS(usdhc2_pads);	674	SETUP_IOMUX_PADS(usdhc2_pads);
675	usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;	675	usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
676	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);	676	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
677	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;	677	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
678	break;	678	break;
679	case 0x2:	679	case 0x2:
680	SETUP_IOMUX_PADS(usdhc3_pads);	680	SETUP_IOMUX_PADS(usdhc3_pads);
681	usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;	681	usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
682	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);	682	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
683	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;	683	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
684	break;	684	break;
685	case 0x3:	685	case 0x3:
686	SETUP_IOMUX_PADS(usdhc4_pads);	686	SETUP_IOMUX_PADS(usdhc4_pads);
687	usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;	687	usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
688	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);	688	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
689	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;	689	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
690	break;	690	break;
691	}	691	}
692		692
693	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);	693	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
694	#endif	694	#endif
695	}	695	}
696	#endif	696	#endif
697		697
698	static int ar8031_phy_fixup(struct phy_device *phydev)	698	static int ar8031_phy_fixup(struct phy_device *phydev)
699	{	699	{
700	unsigned short val;	700	unsigned short val;
701		701
702	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */	702	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
703	if (!is_mx6dqp()) {	703	if (!is_mx6dqp()) {
704	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);	704	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
705	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);	705	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
706	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);	706	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
707		707
708	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);	708	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
709	val &= 0xffe3;	709	val &= 0xffe3;
710	val \|= 0x18;	710	val \|= 0x18;
711	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);	711	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
712	}	712	}
713		713
714	/* set the IO voltage to 1.8v */	714	/* set the IO voltage to 1.8v */
715	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);	715	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
716	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);	716	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
717		717
718	/* introduce tx clock delay */	718	/* introduce tx clock delay */
719	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);	719	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
720	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);	720	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
721	val \|= 0x0100;	721	val \|= 0x0100;
722	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);	722	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
723		723
724	return 0;	724	return 0;
725	}	725	}
726		726
727	int board_phy_config(struct phy_device *phydev)	727	int board_phy_config(struct phy_device *phydev)
728	{	728	{
729	ar8031_phy_fixup(phydev);	729	ar8031_phy_fixup(phydev);
730		730
731	if (phydev->drv->config)	731	if (phydev->drv->config)
732	phydev->drv->config(phydev);	732	phydev->drv->config(phydev);
733		733
734	return 0;	734	return 0;
735	}	735	}
736		736
737	#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)	737	#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
738	vidinfo_t panel_info = {	738	vidinfo_t panel_info = {
739	.vl_refresh = 85,	739	.vl_refresh = 85,
740	.vl_col = 800,	740	.vl_col = 800,
741	.vl_row = 600,	741	.vl_row = 600,
742	.vl_pixclock = 26666667,	742	.vl_pixclock = 26666667,
743	.vl_left_margin = 8,	743	.vl_left_margin = 8,
744	.vl_right_margin = 100,	744	.vl_right_margin = 100,
745	.vl_upper_margin = 4,	745	.vl_upper_margin = 4,
746	.vl_lower_margin = 8,	746	.vl_lower_margin = 8,
747	.vl_hsync = 4,	747	.vl_hsync = 4,
748	.vl_vsync = 1,	748	.vl_vsync = 1,
749	.vl_sync = 0,	749	.vl_sync = 0,
750	.vl_mode = 0,	750	.vl_mode = 0,
751	.vl_flag = 0,	751	.vl_flag = 0,
752	.vl_bpix = 3,	752	.vl_bpix = 3,
753	.cmap = 0,	753	.cmap = 0,
754	};	754	};
755		755
756	struct epdc_timing_params panel_timings = {	756	struct epdc_timing_params panel_timings = {
757	.vscan_holdoff = 4,	757	.vscan_holdoff = 4,
758	.sdoed_width = 10,	758	.sdoed_width = 10,
759	.sdoed_delay = 20,	759	.sdoed_delay = 20,
760	.sdoez_width = 10,	760	.sdoez_width = 10,
761	.sdoez_delay = 20,	761	.sdoez_delay = 20,
762	.gdclk_hp_offs = 419,	762	.gdclk_hp_offs = 419,
763	.gdsp_offs = 20,	763	.gdsp_offs = 20,
764	.gdoe_offs = 0,	764	.gdoe_offs = 0,
765	.gdclk_offs = 5,	765	.gdclk_offs = 5,
766	.num_ce = 1,	766	.num_ce = 1,
767	};	767	};
768		768
769	static iomux_v3_cfg_t const epdc_pwr_ctrl_pads[] = {	769	static iomux_v3_cfg_t const epdc_pwr_ctrl_pads[] = {
770	IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	770	IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
771	IOMUX_PADS(PAD_EIM_D17__GPIO3_IO17 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	771	IOMUX_PADS(PAD_EIM_D17__GPIO3_IO17 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
772	IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	772	IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
773	IOMUX_PADS(PAD_EIM_A18__GPIO2_IO20 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),	773	IOMUX_PADS(PAD_EIM_A18__GPIO2_IO20 \| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
774	};	774	};
775		775
776	static void setup_epdc_power(void)	776	static void setup_epdc_power(void)
777	{	777	{
778	SETUP_IOMUX_PADS(epdc_pwr_ctrl_pads);	778	SETUP_IOMUX_PADS(epdc_pwr_ctrl_pads);
779		779
780	/* Setup epdc voltage */	780	/* Setup epdc voltage */
781		781
782	/* EIM_A17 - GPIO2[21] for PWR_GOOD status */	782	/* EIM_A17 - GPIO2[21] for PWR_GOOD status */
783	/* Set as input */	783	/* Set as input */
784	gpio_request(IMX_GPIO_NR(2, 21), "EPDC PWRSTAT");	784	gpio_request(IMX_GPIO_NR(2, 21), "EPDC PWRSTAT");
785	gpio_direction_input(IMX_GPIO_NR(2, 21));	785	gpio_direction_input(IMX_GPIO_NR(2, 21));
786		786
787	/* EIM_D17 - GPIO3[17] for VCOM control */	787	/* EIM_D17 - GPIO3[17] for VCOM control */
788	/* Set as output */	788	/* Set as output */
789	gpio_request(IMX_GPIO_NR(3, 17), "EPDC VCOM0");	789	gpio_request(IMX_GPIO_NR(3, 17), "EPDC VCOM0");
790	gpio_direction_output(IMX_GPIO_NR(3, 17), 1);	790	gpio_direction_output(IMX_GPIO_NR(3, 17), 1);
791		791
792	/* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */	792	/* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */
793	/* Set as output */	793	/* Set as output */
794	gpio_request(IMX_GPIO_NR(3, 20), "EPDC PWR WAKEUP");	794	gpio_request(IMX_GPIO_NR(3, 20), "EPDC PWR WAKEUP");
795	gpio_direction_output(IMX_GPIO_NR(3, 20), 1);	795	gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
796		796
797	/* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */	797	/* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */
798	/* Set as output */	798	/* Set as output */
799	gpio_request(IMX_GPIO_NR(2, 20), "EPDC PWR CTRL0");	799	gpio_request(IMX_GPIO_NR(2, 20), "EPDC PWR CTRL0");
800	gpio_direction_output(IMX_GPIO_NR(2, 20), 1);	800	gpio_direction_output(IMX_GPIO_NR(2, 20), 1);
801	}	801	}
802		802
803	static void epdc_enable_pins(void)	803	static void epdc_enable_pins(void)
804	{	804	{
805	/* epdc iomux settings */	805	/* epdc iomux settings */
806	SETUP_IOMUX_PADS(epdc_enable_pads);	806	SETUP_IOMUX_PADS(epdc_enable_pads);
807	}	807	}
808		808
809	static void epdc_disable_pins(void)	809	static void epdc_disable_pins(void)
810	{	810	{
811	/* Configure MUX settings for EPDC pins to GPIO */	811	/* Configure MUX settings for EPDC pins to GPIO */
812	SETUP_IOMUX_PADS(epdc_disable_pads);	812	SETUP_IOMUX_PADS(epdc_disable_pads);
813	}	813	}
814		814
815	static void setup_epdc(void)	815	static void setup_epdc(void)
816	{	816	{
817	unsigned int reg;	817	unsigned int reg;
818	struct mxc_ccm_reg ccm_regs = (struct mxc_ccm_reg )CCM_BASE_ADDR;	818	struct mxc_ccm_reg ccm_regs = (struct mxc_ccm_reg )CCM_BASE_ADDR;
819		819
820	/* Set pixel clock rates for EPDC */	820	/* Set pixel clock rates for EPDC */
821		821
822	/* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */	822	/* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */
823	reg = readl(&ccm_regs->cscdr3);	823	reg = readl(&ccm_regs->cscdr3);
824	reg &= ~0x7C000;	824	reg &= ~0x7C000;
825	reg \|= (1 << 16) \| (1 << 14);	825	reg \|= (1 << 16) \| (1 << 14);
826	writel(reg, &ccm_regs->cscdr3);	826	writel(reg, &ccm_regs->cscdr3);
827		827
828	/* EPDC AXI clk enable */	828	/* EPDC AXI clk enable */
829	reg = readl(&ccm_regs->CCGR3);	829	reg = readl(&ccm_regs->CCGR3);
830	reg \|= 0x00C0;	830	reg \|= 0x00C0;
831	writel(reg, &ccm_regs->CCGR3);	831	writel(reg, &ccm_regs->CCGR3);
832		832
833	/* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */	833	/* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */
834	reg = readl(&ccm_regs->cscdr2);	834	reg = readl(&ccm_regs->cscdr2);
835	reg &= ~0x3FE00;	835	reg &= ~0x3FE00;
836	reg \|= (2 << 15) \| (5 << 12);	836	reg \|= (2 << 15) \| (5 << 12);
837	writel(reg, &ccm_regs->cscdr2);	837	writel(reg, &ccm_regs->cscdr2);
838		838
839	/* PLL5 enable (defaults to 650) */	839	/* PLL5 enable (defaults to 650) */
840	reg = readl(&ccm_regs->analog_pll_video);	840	reg = readl(&ccm_regs->analog_pll_video);
841	reg &= ~((1 << 16) \| (1 << 12));	841	reg &= ~((1 << 16) \| (1 << 12));
842	reg \|= (1 << 13);	842	reg \|= (1 << 13);
843	writel(reg, &ccm_regs->analog_pll_video);	843	writel(reg, &ccm_regs->analog_pll_video);
844		844
845	/* EPDC PIX clk enable */	845	/* EPDC PIX clk enable */
846	reg = readl(&ccm_regs->CCGR3);	846	reg = readl(&ccm_regs->CCGR3);
847	reg \|= 0x0C00;	847	reg \|= 0x0C00;
848	writel(reg, &ccm_regs->CCGR3);	848	writel(reg, &ccm_regs->CCGR3);
849		849
850	panel_info.epdc_data.wv_modes.mode_init = 0;	850	panel_info.epdc_data.wv_modes.mode_init = 0;
851	panel_info.epdc_data.wv_modes.mode_du = 1;	851	panel_info.epdc_data.wv_modes.mode_du = 1;
852	panel_info.epdc_data.wv_modes.mode_gc4 = 3;	852	panel_info.epdc_data.wv_modes.mode_gc4 = 3;
853	panel_info.epdc_data.wv_modes.mode_gc8 = 2;	853	panel_info.epdc_data.wv_modes.mode_gc8 = 2;
854	panel_info.epdc_data.wv_modes.mode_gc16 = 2;	854	panel_info.epdc_data.wv_modes.mode_gc16 = 2;
855	panel_info.epdc_data.wv_modes.mode_gc32 = 2;	855	panel_info.epdc_data.wv_modes.mode_gc32 = 2;
856		856
857	panel_info.epdc_data.epdc_timings = panel_timings;	857	panel_info.epdc_data.epdc_timings = panel_timings;
858		858
859	setup_epdc_power();	859	setup_epdc_power();
860	}	860	}
861		861
862	void epdc_power_on(void)	862	void epdc_power_on(void)
863	{	863	{
864	unsigned int reg;	864	unsigned int reg;
865	struct gpio_regs gpio_regs = (struct gpio_regs )GPIO2_BASE_ADDR;	865	struct gpio_regs gpio_regs = (struct gpio_regs )GPIO2_BASE_ADDR;
866		866
867	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */	867	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
868	gpio_set_value(IMX_GPIO_NR(2, 20), 1);	868	gpio_set_value(IMX_GPIO_NR(2, 20), 1);
869	udelay(1000);	869	udelay(1000);
870		870
871	/* Enable epdc signal pin */	871	/* Enable epdc signal pin */
872	epdc_enable_pins();	872	epdc_enable_pins();
873		873
874	/* Set PMIC Wakeup to high - enable Display power */	874	/* Set PMIC Wakeup to high - enable Display power */
875	gpio_set_value(IMX_GPIO_NR(3, 20), 1);	875	gpio_set_value(IMX_GPIO_NR(3, 20), 1);
876		876
877	/* Wait for PWRGOOD == 1 */	877	/* Wait for PWRGOOD == 1 */
878	while (1) {	878	while (1) {
879	reg = readl(&gpio_regs->gpio_psr);	879	reg = readl(&gpio_regs->gpio_psr);
880	if (!(reg & (1 << 21)))	880	if (!(reg & (1 << 21)))
881	break;	881	break;
882		882
883	udelay(100);	883	udelay(100);
884	}	884	}
885		885
886	/* Enable VCOM */	886	/* Enable VCOM */
887	gpio_set_value(IMX_GPIO_NR(3, 17), 1);	887	gpio_set_value(IMX_GPIO_NR(3, 17), 1);
888		888
889	udelay(500);	889	udelay(500);
890	}	890	}
891		891
892	void epdc_power_off(void)	892	void epdc_power_off(void)
893	{	893	{
894	/* Set PMIC Wakeup to low - disable Display power */	894	/* Set PMIC Wakeup to low - disable Display power */
895	gpio_set_value(IMX_GPIO_NR(3, 20), 0);	895	gpio_set_value(IMX_GPIO_NR(3, 20), 0);
896		896
897	/* Disable VCOM */	897	/* Disable VCOM */
898	gpio_set_value(IMX_GPIO_NR(3, 17), 0);	898	gpio_set_value(IMX_GPIO_NR(3, 17), 0);
899		899
900	epdc_disable_pins();	900	epdc_disable_pins();
901		901
902	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */	902	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
903	gpio_set_value(IMX_GPIO_NR(2, 20), 0);	903	gpio_set_value(IMX_GPIO_NR(2, 20), 0);
904	}	904	}
905	#endif	905	#endif
906		906
907	#if defined(CONFIG_VIDEO_IPUV3)	907	#if defined(CONFIG_VIDEO_IPUV3)
908	static void disable_lvds(struct display_info_t const *dev)	908	static void disable_lvds(struct display_info_t const *dev)
909	{	909	{
910	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;	910	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
911		911
912	int reg = readl(&iomux->gpr[2]);	912	int reg = readl(&iomux->gpr[2]);
913		913
914	reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK \|	914	reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK \|
915	IOMUXC_GPR2_LVDS_CH1_MODE_MASK);	915	IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
916		916
917	writel(reg, &iomux->gpr[2]);	917	writel(reg, &iomux->gpr[2]);
918	}	918	}
919		919
920	static void do_enable_hdmi(struct display_info_t const *dev)	920	static void do_enable_hdmi(struct display_info_t const *dev)
921	{	921	{
922	disable_lvds(dev);	922	disable_lvds(dev);
923	imx_enable_hdmi_phy();	923	imx_enable_hdmi_phy();
924	}	924	}
925		925
926	struct display_info_t const displays[] = {{	926	struct display_info_t const displays[] = {{
927	.bus = -1,	927	.bus = -1,
928	.addr = 0,	928	.addr = 0,
929	.pixfmt = IPU_PIX_FMT_RGB666,	929	.pixfmt = IPU_PIX_FMT_RGB666,
930	.detect = NULL,	930	.detect = NULL,
931	.enable = enable_lvds,	931	.enable = enable_lvds,
932	.mode = {	932	.mode = {
933	.name = "Hannstar-XGA",	933	.name = "Hannstar-XGA",
934	.refresh = 60,	934	.refresh = 60,
935	.xres = 1024,	935	.xres = 1024,
936	.yres = 768,	936	.yres = 768,
937	.pixclock = 15384,	937	.pixclock = 15384,
938	.left_margin = 160,	938	.left_margin = 160,
939	.right_margin = 24,	939	.right_margin = 24,
940	.upper_margin = 29,	940	.upper_margin = 29,
941	.lower_margin = 3,	941	.lower_margin = 3,
942	.hsync_len = 136,	942	.hsync_len = 136,
943	.vsync_len = 6,	943	.vsync_len = 6,
944	.sync = FB_SYNC_EXT,	944	.sync = FB_SYNC_EXT,
945	.vmode = FB_VMODE_NONINTERLACED	945	.vmode = FB_VMODE_NONINTERLACED
946	} }, {	946	} }, {
947	.bus = -1,	947	.bus = -1,
948	.addr = 0,	948	.addr = 0,
949	.pixfmt = IPU_PIX_FMT_RGB24,	949	.pixfmt = IPU_PIX_FMT_RGB24,
950	.detect = NULL,	950	.detect = NULL,
951	.enable = do_enable_hdmi,	951	.enable = do_enable_hdmi,
952	.mode = {	952	.mode = {
953	.name = "HDMI",	953	.name = "HDMI",
954	.refresh = 60,	954	.refresh = 60,
955	.xres = 640,	955	.xres = 640,
956	.yres = 480,	956	.yres = 480,
957	.pixclock = 39721,	957	.pixclock = 39721,
958	.left_margin = 48,	958	.left_margin = 48,
959	.right_margin = 16,	959	.right_margin = 16,
960	.upper_margin = 33,	960	.upper_margin = 33,
961	.lower_margin = 10,	961	.lower_margin = 10,
962	.hsync_len = 96,	962	.hsync_len = 96,
963	.vsync_len = 2,	963	.vsync_len = 2,
964	.sync = 0,	964	.sync = 0,
965	.vmode = FB_VMODE_NONINTERLACED	965	.vmode = FB_VMODE_NONINTERLACED
966	} }, {	966	} }, {
967	.bus = -1,	967	.bus = -1,
968	.addr = 0,	968	.addr = 0,
969	.pixfmt = IPU_PIX_FMT_RGB24,	969	.pixfmt = IPU_PIX_FMT_RGB24,
970	.detect = NULL,	970	.detect = NULL,
971	.enable = enable_rgb,	971	.enable = enable_rgb,
972	.mode = {	972	.mode = {
973	.name = "SEIKO-WVGA",	973	.name = "SEIKO-WVGA",
974	.refresh = 60,	974	.refresh = 60,
975	.xres = 800,	975	.xres = 800,
976	.yres = 480,	976	.yres = 480,
977	.pixclock = 29850,	977	.pixclock = 29850,
978	.left_margin = 89,	978	.left_margin = 89,
979	.right_margin = 164,	979	.right_margin = 164,
980	.upper_margin = 23,	980	.upper_margin = 23,
981	.lower_margin = 10,	981	.lower_margin = 10,
982	.hsync_len = 10,	982	.hsync_len = 10,
983	.vsync_len = 10,	983	.vsync_len = 10,
984	.sync = 0,	984	.sync = 0,
985	.vmode = FB_VMODE_NONINTERLACED	985	.vmode = FB_VMODE_NONINTERLACED
986	} } };	986	} } };
987	size_t display_count = ARRAY_SIZE(displays);	987	size_t display_count = ARRAY_SIZE(displays);
988		988
989	static void setup_display(void)	989	static void setup_display(void)
990	{	990	{
991	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;	991	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
992	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;	992	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
993	int reg;	993	int reg;
994		994
995	/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */	995	/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
996	SETUP_IOMUX_PADS(di0_pads);	996	SETUP_IOMUX_PADS(di0_pads);
997		997
998	enable_ipu_clock();	998	enable_ipu_clock();
999	imx_setup_hdmi();	999	imx_setup_hdmi();
1000		1000
1001	/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */	1001	/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
1002	reg = readl(&mxc_ccm->CCGR3);	1002	reg = readl(&mxc_ccm->CCGR3);
1003	reg \|= MXC_CCM_CCGR3_LDB_DI0_MASK \| MXC_CCM_CCGR3_LDB_DI1_MASK;	1003	reg \|= MXC_CCM_CCGR3_LDB_DI0_MASK \| MXC_CCM_CCGR3_LDB_DI1_MASK;
1004	writel(reg, &mxc_ccm->CCGR3);	1004	writel(reg, &mxc_ccm->CCGR3);
1005		1005
1006	/* set LDB0, LDB1 clk select to 011/011 */	1006	/* set LDB0, LDB1 clk select to 011/011 */
1007	reg = readl(&mxc_ccm->cs2cdr);	1007	reg = readl(&mxc_ccm->cs2cdr);
1008	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK	1008	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
1009	\| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);	1009	\| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
1010	reg \|= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)	1010	reg \|= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
1011	\| (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);	1011	\| (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
1012	writel(reg, &mxc_ccm->cs2cdr);	1012	writel(reg, &mxc_ccm->cs2cdr);
1013		1013
1014	reg = readl(&mxc_ccm->cscmr2);	1014	reg = readl(&mxc_ccm->cscmr2);
1015	reg \|= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV \| MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;	1015	reg \|= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV \| MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
1016	writel(reg, &mxc_ccm->cscmr2);	1016	writel(reg, &mxc_ccm->cscmr2);
1017		1017
1018	reg = readl(&mxc_ccm->chsccdr);	1018	reg = readl(&mxc_ccm->chsccdr);
1019	reg \|= (CHSCCDR_CLK_SEL_LDB_DI0	1019	reg \|= (CHSCCDR_CLK_SEL_LDB_DI0
1020	<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);	1020	<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
1021	reg \|= (CHSCCDR_CLK_SEL_LDB_DI0	1021	reg \|= (CHSCCDR_CLK_SEL_LDB_DI0
1022	<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);	1022	<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
1023	writel(reg, &mxc_ccm->chsccdr);	1023	writel(reg, &mxc_ccm->chsccdr);
1024		1024
1025	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES	1025	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
1026	\| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW	1026	\| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
1027	\| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW	1027	\| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
1028	\| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG	1028	\| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
1029	\| IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT	1029	\| IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
1030	\| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG	1030	\| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
1031	\| IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT	1031	\| IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
1032	\| IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED	1032	\| IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
1033	\| IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;	1033	\| IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
1034	writel(reg, &iomux->gpr[2]);	1034	writel(reg, &iomux->gpr[2]);
1035		1035
1036	reg = readl(&iomux->gpr[3]);	1036	reg = readl(&iomux->gpr[3]);
1037	reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK	1037	reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
1038	\| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))	1038	\| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
1039	\| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0	1039	\| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
1040	<< IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);	1040	<< IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
1041	writel(reg, &iomux->gpr[3]);	1041	writel(reg, &iomux->gpr[3]);
1042	}	1042	}
1043	#endif /* CONFIG_VIDEO_IPUV3 */	1043	#endif /* CONFIG_VIDEO_IPUV3 */
1044		1044
1045	/*	1045	/*
1046	* Do not overwrite the console	1046	* Do not overwrite the console
1047	* Use always serial for U-Boot console	1047	* Use always serial for U-Boot console
1048	*/	1048	*/
1049	int overwrite_console(void)	1049	int overwrite_console(void)
1050	{	1050	{
1051	return 1;	1051	return 1;
1052	}	1052	}
1053		1053
1054	static void setup_fec(void)	1054	static void setup_fec(void)
1055	{	1055	{
1056	if (is_mx6dqp()) {	1056	if (is_mx6dqp()) {
1057	int ret;	1057	int ret;
1058		1058
1059	/* select ENET MAC0 TX clock from PLL */	1059	/* select ENET MAC0 TX clock from PLL */
1060	imx_iomux_set_gpr_register(5, 9, 1, 1);	1060	imx_iomux_set_gpr_register(5, 9, 1, 1);
1061	ret = enable_fec_anatop_clock(0, ENET_125MHZ);	1061	ret = enable_fec_anatop_clock(0, ENET_125MHZ);
1062	if (ret)	1062	if (ret)
1063	printf("Error fec anatop clock settings!\n");	1063	printf("Error fec anatop clock settings!\n");
1064	}	1064	}
1065	}	1065	}
1066		1066
1067	int board_eth_init(bd_t *bis)	1067	int board_eth_init(bd_t *bis)
1068	{	1068	{
1069	setup_iomux_enet();	1069	setup_iomux_enet();
1070	return cpu_eth_init(bis);	1070	return cpu_eth_init(bis);
1071	}	1071	}
1072		1072
1073	#ifdef CONFIG_USB_EHCI_MX6	1073	#ifdef CONFIG_USB_EHCI_MX6
1074	#ifdef CONFIG_DM_USB	1074	#ifdef CONFIG_DM_USB
1075	int board_ehci_hcd_init(int port)	1075	int board_ehci_hcd_init(int port)
1076	{	1076	{
1077	switch (port) {	1077	switch (port) {
1078	case 0:	1078	case 0:
1079	/*	1079	/*
1080	* Set daisy chain for otg_pin_id on 6q.	1080	* Set daisy chain for otg_pin_id on 6q.
1081	* For 6dl, this bit is reserved.	1081	* For 6dl, this bit is reserved.
1082	*/	1082	*/
1083	imx_iomux_set_gpr_register(1, 13, 1, 0);	1083	imx_iomux_set_gpr_register(1, 13, 1, 0);
1084	break;	1084	break;
1085	case 1:	1085	case 1:
1086	break;	1086	break;
1087	default:	1087	default:
1088	printf("MXC USB port %d not yet supported\n", port);	1088	printf("MXC USB port %d not yet supported\n", port);
1089	return -EINVAL;	1089	return -EINVAL;
1090	}	1090	}
1091	return 0;	1091	return 0;
1092	}	1092	}
1093	#else	1093	#else
1094	#define USB_OTHERREGS_OFFSET 0x800	1094	#define USB_OTHERREGS_OFFSET 0x800
1095	#define UCTRL_PWR_POL (1 << 9)	1095	#define UCTRL_PWR_POL (1 << 9)
1096		1096
1097	static iomux_v3_cfg_t const usb_otg_pads[] = {	1097	static iomux_v3_cfg_t const usb_otg_pads[] = {
1098	/* OTG Over Current */	1098	/* OTG Over Current */
1099	IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 \| MUX_PAD_CTRL(WEAK_PULLUP)),	1099	IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 \| MUX_PAD_CTRL(WEAK_PULLUP)),
1100	/* OTG ID */	1100	/* OTG ID */
1101	IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID \| MUX_PAD_CTRL(WEAK_PULLUP)),	1101	IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID \| MUX_PAD_CTRL(WEAK_PULLUP)),
1102	/* OTG Power enable */	1102	/* OTG Power enable */
1103	IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 \| MUX_PAD_CTRL(OUTPUT_40OHM)),	1103	IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 \| MUX_PAD_CTRL(OUTPUT_40OHM)),
1104	};	1104	};
1105		1105
1106	static iomux_v3_cfg_t const usb_hc1_pads[] = {	1106	static iomux_v3_cfg_t const usb_hc1_pads[] = {
1107	/* USB1 Over Current */	1107	/* USB1 Over Current */
1108	IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 \| MUX_PAD_CTRL(WEAK_PULLUP)),	1108	IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 \| MUX_PAD_CTRL(WEAK_PULLUP)),
1109	/* USB1 Power enable */	1109	/* USB1 Power enable */
1110	IOMUX_PADS(MX6_PAD_ENET_RXD1__GPIO1_IO26 \| MUX_PAD_CTRL(OUTPUT_40OHM)),	1110	IOMUX_PADS(MX6_PAD_ENET_RXD1__GPIO1_IO26 \| MUX_PAD_CTRL(OUTPUT_40OHM)),
1111	};	1111	};
1112		1112
1113	int board_ehci_hcd_init(int port)	1113	int board_ehci_hcd_init(int port)
1114	{	1114	{
1115	u32 *usbnc_usb_ctrl;	1115	u32 *usbnc_usb_ctrl;
1116		1116
1117	switch (port) {	1117	switch (port) {
1118	case 0:	1118	case 0:
1119	SETUP_IOMUX_PADS(usb_otg_pads);	1119	SETUP_IOMUX_PADS(usb_otg_pads);
1120	gpio_request(IMX_GPIO_NR(1, 29), "USB OTG Power Enable")	1120	gpio_request(IMX_GPIO_NR(1, 29), "USB OTG Power Enable")
1121	gpio_request(IMX_GPIO_NR(1, 30), "USB OTG Over Current")	1121	gpio_request(IMX_GPIO_NR(1, 30), "USB OTG Over Current")
1122		1122
1123	/*	1123	/*
1124	* Set daisy chain for otg_pin_id on 6q.	1124	* Set daisy chain for otg_pin_id on 6q.
1125	* For 6dl, this bit is reserved.	1125	* For 6dl, this bit is reserved.
1126	*/	1126	*/
1127	imx_iomux_set_gpr_register(1, 13, 1, 0);	1127	imx_iomux_set_gpr_register(1, 13, 1, 0);
1128		1128
1129	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +	1129	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
1130	port * 4);	1130	port * 4);
1131		1131
1132	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);	1132	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
1133	break;	1133	break;
1134	case 1:	1134	case 1:
1135	SETUP_IOMUX_PADS(usb_hc1_pads);	1135	SETUP_IOMUX_PADS(usb_hc1_pads);
1136	gpio_request(IMX_GPIO_NR(1, 26), "USB HC1 Power Enable");	1136	gpio_request(IMX_GPIO_NR(1, 26), "USB HC1 Power Enable");
1137	gpio_request(IMX_GPIO_NR(1, 27), "USB HC1 Over Current");	1137	gpio_request(IMX_GPIO_NR(1, 27), "USB HC1 Over Current");
1138	break;	1138	break;
1139	default:	1139	default:
1140	printf("MXC USB port %d not yet supported\n", port);	1140	printf("MXC USB port %d not yet supported\n", port);
1141	return -EINVAL;	1141	return -EINVAL;
1142	}	1142	}
1143		1143
1144	return 0;	1144	return 0;
1145	}	1145	}
1146		1146
1147	int board_ehci_power(int port, int on)	1147	int board_ehci_power(int port, int on)
1148	{	1148	{
1149	switch (port) {	1149	switch (port) {
1150	case 0:	1150	case 0:
1151	if (on)	1151	if (on)
1152	gpio_direction_output(IMX_GPIO_NR(1, 29), 1);	1152	gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
1153	gpio_direction_input(IMX_GPIO_NR(1, 30));	1153	gpio_direction_input(IMX_GPIO_NR(1, 30));
1154	else	1154	else
1155	gpio_direction_output(IMX_GPIO_NR(1, 29), 0);	1155	gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
1156	break;	1156	break;
1157	break;	1157	break;
1158	case 1:	1158	case 1:
1159	if (on)	1159	if (on)
1160	gpio_direction_output(IMX_GPIO_NR(1, 26), 1);	1160	gpio_direction_output(IMX_GPIO_NR(1, 26), 1);
1161	gpio_direction_input(IMX_GPIO_NR(1, 27));	1161	gpio_direction_input(IMX_GPIO_NR(1, 27));
1162	else	1162	else
1163	gpio_direction_output(IMX_GPIO_NR(1, 26), 0);	1163	gpio_direction_output(IMX_GPIO_NR(1, 26), 0);
1164	break;	1164	break;
1165	default:	1165	default:
1166	printf("MXC USB port %d not yet supported\n", port);	1166	printf("MXC USB port %d not yet supported\n", port);
1167	return -EINVAL;	1167	return -EINVAL;
1168	}	1168	}
1169		1169
1170	return 0;	1170	return 0;
1171	}	1171	}
1172	#endif	1172	#endif
1173	#endif	1173	#endif
1174		1174
1175	int board_early_init_f(void)	1175	int board_early_init_f(void)
1176	{	1176	{
1177	setup_iomux_wdt();	1177	setup_iomux_wdt();
1178	setup_iomux_reset_out();	1178	setup_iomux_reset_out();
1179	setup_iomux_uart1();	1179	setup_iomux_uart1();
1180	setup_iomux_uart2();	1180	setup_iomux_uart2();
1181	setup_iomux_uart4();	1181	setup_iomux_uart4();
1182	setup_iomux_uart5();	1182	setup_iomux_uart5();
1183	#if defined(CONFIG_VIDEO_IPUV3)	1183	#if defined(CONFIG_VIDEO_IPUV3)
1184	setup_display();	1184	setup_display();
1185	#endif	1185	#endif
1186	setup_spi1();	1186	setup_spi1();
1187	setup_flexcan1();	1187	setup_flexcan1();
1188	setup_flexcan2();	1188	setup_flexcan2();
1189	setup_gpios();	1189	setup_gpios();
1190	setup_misc();	1190	setup_misc();
1191		1191
1192	return 0;	1192	return 0;
1193	}	1193	}
1194		1194
1195	int board_init(void)	1195	int board_init(void)
1196	{	1196	{
1197	/* address of boot parameters */	1197	/* address of boot parameters */
1198	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;	1198	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
1199		1199
1200	#ifdef CONFIG_MXC_SPI	1200	#ifdef CONFIG_MXC_SPI
1201	// Make sure we enable ECSPI2 clock	1201	// Make sure we enable ECSPI2 clock
1202	int reg;	1202	int reg;
1203	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;	1203	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
1204	reg = readl(&mxc_ccm->CCGR1);	1204	reg = readl(&mxc_ccm->CCGR1);
1205	reg \|= MXC_CCM_CCGR1_ECSPI2S_MASK;	1205	reg \|= MXC_CCM_CCGR1_ECSPI2S_MASK;
1206	writel(reg, &mxc_ccm->CCGR1);	1206	writel(reg, &mxc_ccm->CCGR1);
1207		1207
1208	gpio_request(IMX_GPIO_NR(4, 20), "SPI_LOCK_PIN");	1208	gpio_request(IMX_GPIO_NR(4, 20), "SPI_LOCK_PIN");
1209	/Unlock SPI Flash/	1209	/Unlock SPI Flash/
1210	gpio_direction_output(IMX_GPIO_NR(4,20), 1);	1210	gpio_direction_output(IMX_GPIO_NR(4,20), 1);
1211	setup_spinor();	1211	setup_spinor();
1212	#endif	1212	#endif
1213		1213
1214	#ifdef CONFIG_SYS_I2C	1214	#ifdef CONFIG_SYS_I2C
1215	setup_i2c(2, CONFIG_SYS_I2C_SPEED,	1215	setup_i2c(2, CONFIG_SYS_I2C_SPEED,
1216	0x70, &i2c_pad_info3);	1216	0x70, &i2c_pad_info3);
1217		1217
1218	/* Configure I2C switch (PCA9546) to enable channel 0. */	1218	/* Configure I2C switch (PCA9546) to enable channel 0. */
1219	i2c_set_bus_num(2);	1219	i2c_set_bus_num(2);
1220	uint8_t i2cbuf;	1220	uint8_t i2cbuf;
1221	i2cbuf = 0x07; /* Enable channel 0, 1, 2. */	1221	i2cbuf = 0x07; /* Enable channel 0, 1, 2. */
1222	if (i2c_write(0x70, 0,	1222	if (i2c_write(0x70, 0,
1223	0, &i2cbuf, 1)) {	1223	0, &i2cbuf, 1)) {
1224	printf("Write to MUX @ 0x%02x failed\n", 0x70);	1224	printf("Write to MUX @ 0x%02x failed\n", 0x70);
1225	return 1;	1225	return 1;
1226	}	1226	}
1227	#endif	1227	#endif
1228		1228
1229	#ifdef CONFIG_PCIE_IMX	1229	#ifdef CONFIG_PCIE_IMX
1230	setup_pcie();	1230	setup_pcie();
1231	#endif	1231	#endif
1232		1232
1233	#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)	1233	#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
1234	setup_epdc();	1234	setup_epdc();
1235	#endif	1235	#endif
1236		1236
1237	#ifdef CONFIG_SATA	1237	#ifdef CONFIG_SATA
1238	setup_sata();	1238	setup_sata();
1239	#endif	1239	#endif
1240		1240
1241	#ifdef CONFIG_FEC_MXC	1241	#ifdef CONFIG_FEC_MXC
1242	setup_fec();	1242	setup_fec();
1243	#endif	1243	#endif
1244		1244
1245	return 0;	1245	return 0;
1246	}	1246	}
1247		1247
1248	#ifdef CONFIG_CMD_BMODE	1248	#ifdef CONFIG_CMD_BMODE
1249	static const struct boot_mode board_boot_modes[] = {	1249	static const struct boot_mode board_boot_modes[] = {
1250	/* 4 bit bus width */	1250	/* 4 bit bus width */
1251	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},	1251	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
1252	{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},	1252	{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
1253	/* 8 bit bus width */	1253	/* 8 bit bus width */
1254	{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},	1254	{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
1255	{NULL, 0},	1255	{NULL, 0},
1256	};	1256	};
1257	#endif	1257	#endif
1258		1258
1259	int board_late_init(void)	1259	int board_late_init(void)
1260	{	1260	{
1261	#ifdef CONFIG_CMD_BMODE	1261	#ifdef CONFIG_CMD_BMODE
1262	add_board_boot_modes(board_boot_modes);	1262	add_board_boot_modes(board_boot_modes);
1263	#endif	1263	#endif
1264		1264
1265	env_set("tee", "no");	1265	env_set("tee", "no");
1266	#ifdef CONFIG_IMX_OPTEE	1266	#ifdef CONFIG_IMX_OPTEE
1267	env_set("tee", "yes");	1267	env_set("tee", "yes");
1268	#endif	1268	#endif
1269		1269
1270	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG	1270	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
1271	if (is_mx6dqp())	1271	if (is_mx6dqp())
1272	env_set("board_rev", "MX6QP");	1272	env_set("board_rev", "MX6QP");
1273	else if (is_mx6dq())	1273	else if (is_mx6dq())
1274	env_set("board_rev", "MX6Q");	1274	env_set("board_rev", "MX6Q");
1275	else if (is_mx6sdl())	1275	else if (is_mx6sdl())
1276	env_set("board_rev", "MX6DL");	1276	env_set("board_rev", "MX6DL");
1277	#endif	1277	#endif
1278		1278
1279	#ifdef CONFIG_ENV_IS_IN_MMC	1279	#ifdef CONFIG_ENV_IS_IN_MMC
1280	board_late_mmc_env_init();	1280	board_late_mmc_env_init();
1281	#endif	1281	#endif
1282		1282
1283	puts("---------Embedian SMARC-FiMX6------------\n");	1283	puts("---------Embedian SMARC-FiMX6------------\n");
1284	/* Read Module Information from on module EEPROM and pass	1284	/* Read Module Information from on module EEPROM and pass
1285	* mac address to kernel	1285	* mac address to kernel
1286	*/	1286	*/
1287	struct udevice *dev;	1287	struct udevice *dev;
1288	int ret;	1288	int ret;
1289	u8 name[8];	1289	u8 name[8];
1290	u8 serial[12];	1290	u8 serial[12];
1291	u8 revision[4];	1291	u8 revision[4];
1292	u8 mac[6];	1292	u8 mac[6];
1293		1293
1294	ret = i2c_get_chip_for_busnum(0, 0x50, 2, &dev);	1294	ret = i2c_get_chip_for_busnum(0, 0x50, 2, &dev);
1295	if (ret) {	1295	if (ret) {
1296	debug("failed to get eeprom\n");	1296	debug("failed to get eeprom\n");
1297	return 0;	1297	return 0;
1298	}	1298	}
1299		1299
1300	/* Board ID */	1300	/* Board ID */
1301	ret = dm_i2c_read(dev, 0x4, name, 8);	1301	ret = dm_i2c_read(dev, 0x4, name, 8);
1302	if (ret) {	1302	if (ret) {
1303	debug("failed to read board ID from EEPROM\n");	1303	debug("failed to read board ID from EEPROM\n");
1304	return 0;	1304	return 0;
1305	}	1305	}
1306	printf(" Board ID: %c%c%c%c%c%c%c%c\n",	1306	printf(" Board ID: %c%c%c%c%c%c%c%c\n",
1307	name[0], name[1], name[2], name[3], name[4], name[5], name[6], name[7]);	1307	name[0], name[1], name[2], name[3], name[4], name[5], name[6], name[7]);
1308		1308
1309	/* Board Hardware Revision */	1309	/* Board Hardware Revision */
1310	ret = dm_i2c_read(dev, 0xc, revision, 4);	1310	ret = dm_i2c_read(dev, 0xc, revision, 4);
1311	if (ret) {	1311	if (ret) {
1312	debug("failed to read hardware revison from EEPROM\n");	1312	debug("failed to read hardware revison from EEPROM\n");
1313	return 0;	1313	return 0;
1314	}	1314	}
1315	printf(" Hardware Revision: %c%c%c%c\n",	1315	printf(" Hardware Revision: %c%c%c%c\n",
1316	revision[0], revision[1], revision[2], revision[3]);	1316	revision[0], revision[1], revision[2], revision[3]);
1317		1317
1318	/* Serial number */	1318	/* Serial number */
1319	ret = dm_i2c_read(dev, 0x10, serial, 12);	1319	ret = dm_i2c_read(dev, 0x10, serial, 12);
1320	if (ret) {	1320	if (ret) {
1321	debug("failed to read srial number from EEPROM\n");	1321	debug("failed to read srial number from EEPROM\n");
1322	return 0;	1322	return 0;
1323	}	1323	}
1324	printf(" Serial Number#: %c%c%c%c%c%c%c%c%c%c%c%c\n",	1324	printf(" Serial Number#: %c%c%c%c%c%c%c%c%c%c%c%c\n",
1325	serial[0], serial[1], serial[2], serial[3], serial[4], serial[5], serial[6], serial[7], serial[8], serial[9], serial[10], serial[11]);	1325	serial[0], serial[1], serial[2], serial[3], serial[4], serial[5], serial[6], serial[7], serial[8], serial[9], serial[10], serial[11]);
1326		1326
1327	/MAC address/	1327	/MAC address/
1328	ret = dm_i2c_read(dev, 0x3c, mac, 6);	1328	ret = dm_i2c_read(dev, 0x3c, mac, 6);
1329	if (ret) {	1329	if (ret) {
1330	debug("failed to read eth0 mac address from EEPROM\n");	1330	debug("failed to read eth0 mac address from EEPROM\n");
1331	return 0;	1331	return 0;
1332	}	1332	}
1333		1333
1334	if (is_valid_ethaddr(mac))	1334	if (is_valid_ethaddr(mac))
1335	printf(" MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n",	1335	printf(" MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n",
1336	mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);	1336	mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
1337	eth_env_set_enetaddr("ethaddr", mac);	1337	eth_env_set_enetaddr("ethaddr", mac);
1338	puts("-----------------------------------------\n");	1338	puts("-----------------------------------------\n");
1339		1339
1340	/* Lock Up SPI NOR First to Free ECSPI2 Bus */	1340	/* Lock Up SPI NOR First to Free ECSPI2 Bus */
1341	gpio_direction_output(IMX_GPIO_NR(4,20), 0);	1341	gpio_direction_output(IMX_GPIO_NR(4,20), 0);
1342	/* SMARC BOOT_SEL*/	1342	/* SMARC BOOT_SEL*/
1343	gpio_request(IMX_GPIO_NR(1, 4), "BOOT_SEL_1");	1343	gpio_request(IMX_GPIO_NR(1, 4), "BOOT_SEL_1");
1344	gpio_request(IMX_GPIO_NR(1, 5), "BOOT_SEL_2");	1344	gpio_request(IMX_GPIO_NR(1, 5), "BOOT_SEL_2");
1345	gpio_request(IMX_GPIO_NR(1, 6), "BOOT_SEL_3");	1345	gpio_request(IMX_GPIO_NR(1, 6), "BOOT_SEL_3");
1346	if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {	1346	if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {
1347	puts("BOOT_SEL Detected: OFF OFF OFF, Load zImage from Carrier SATA...\n");	1347	puts("BOOT_SEL Detected: OFF OFF OFF, Load zImage from Carrier SATA...\n");
1348	env_set("root", "/dev/sda1 rootwait rw ");	1348	env_set("root", "/dev/sda1 rootwait rw ");
1349	env_set("bootcmd", "sata init; run findfdt; run loadsataenv; run importbootenv; run uenvcmd; run loadsatazimage; run loadsatafdt; run sataboot;");	1349	env_set("bootcmd", "sata init; run loadsataenv; run importbootenv; run uenvcmd; run loadsatazimage; run loadsatafdt; run sataboot;");
1350	} else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {	1350	} else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {
1351	puts("BOOT_SEL Detected: OFF OFF ON, USB Boot Up Not Defined...Carrier SPI Boot Not Supported...\n");	1351	puts("BOOT_SEL Detected: OFF OFF ON, USB Boot Up Not Defined...Carrier SPI Boot Not Supported...\n");
1352	hang();	1352	hang();
1353	} else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {	1353	} else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {
1354	puts("BOOT_SEL Detected: OFF ON OFF, Load zImage from Carrier SDMMC...\n");	1354	puts("BOOT_SEL Detected: OFF ON OFF, Load zImage from Carrier SDMMC...\n");
1355	env_set_ulong("mmcdev", 1);	1355	env_set_ulong("mmcdev", 1);
1356	env_set("bootcmd", "mmc rescan; run findfdt; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");	1356	env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");
1357	} else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {	1357	} else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {
1358	puts("BOOT_SEL Detected: ON OFF OFF, Load zImage from Carrier SD Card...\n");	1358	puts("BOOT_SEL Detected: ON OFF OFF, Load zImage from Carrier SD Card...\n");
1359	env_set_ulong("mmcdev", 0);	1359	env_set_ulong("mmcdev", 0);
1360	env_set("bootcmd", "mmc rescan; run findfdt; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");	1360	env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");
1361	} else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {	1361	} else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {
1362	puts("BOOT_SEL Detected: OFF ON ON, Load zImage from Module eMMC Flash...\n");	1362	puts("BOOT_SEL Detected: OFF ON ON, Load zImage from Module eMMC Flash...\n");
1363	env_set_ulong("mmcdev", 2);	1363	env_set_ulong("mmcdev", 2);
1364	env_set("bootcmd", "mmc rescan; run findfdt; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");	1364	env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");
1365	} else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {	1365	} else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {
1366	puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n");	1366	puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n");
1367	env_set("bootcmd", "run netboot;");	1367	env_set("bootcmd", "run netboot;");
1368	} else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {	1368	} else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) {
1369	puts("Carrier SPI Boot is not supported...\n");	1369	puts("Carrier SPI Boot is not supported...\n");
1370	hang();	1370	hang();
1371	} else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {	1371	} else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) {
1372	puts("BOOT_SEL Detected: ON ON ON, MOdule SPI Boot up is Default, Load zImage from Module eMMC...\n");	1372	puts("BOOT_SEL Detected: ON ON ON, MOdule SPI Boot up is Default, Load zImage from Module eMMC...\n");
1373	env_set_ulong("mmcdev", 2);	1373	env_set_ulong("mmcdev", 2);
1374	env_set("bootcmd", "mmc rescan; run findfdt; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");	1374	env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");
1375	} else {	1375	} else {
1376	puts("unsupported boot devices\n");	1376	puts("unsupported boot devices\n");
1377	hang();	1377	hang();
1378	}	1378	}
1379		1379
1380	return 0;	1380	return 0;
1381	}	1381	}
1382		1382
1383	#ifdef CONFIG_FSL_FASTBOOT	1383	#ifdef CONFIG_FSL_FASTBOOT
1384	#ifdef CONFIG_ANDROID_RECOVERY	1384	#ifdef CONFIG_ANDROID_RECOVERY
1385		1385
1386	#define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5)	1386	#define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5)
1387	iomux_v3_cfg_t const recovery_key_pads[] = {	1387	iomux_v3_cfg_t const recovery_key_pads[] = {
1388	IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 \| MUX_PAD_CTRL(NO_PAD_CTRL)),	1388	IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
1389	};	1389	};
1390		1390
1391	int is_recovery_key_pressing(void)	1391	int is_recovery_key_pressing(void)
1392	{	1392	{
1393	int button_pressed = 0;	1393	int button_pressed = 0;
1394		1394
1395	/* Check Recovery Combo Button press or not. */	1395	/* Check Recovery Combo Button press or not. */
1396	SETUP_IOMUX_PADS(recovery_key_pads);	1396	SETUP_IOMUX_PADS(recovery_key_pads);
1397		1397
1398	gpio_request(GPIO_VOL_DN_KEY, "volume_dn_key");	1398	gpio_request(GPIO_VOL_DN_KEY, "volume_dn_key");
1399	gpio_direction_input(GPIO_VOL_DN_KEY);	1399	gpio_direction_input(GPIO_VOL_DN_KEY);
1400		1400
1401	if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */	1401	if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */
1402	button_pressed = 1;	1402	button_pressed = 1;
1403	printf("Recovery key pressed\n");	1403	printf("Recovery key pressed\n");
1404	}	1404	}
1405		1405
1406	return button_pressed;	1406	return button_pressed;
1407	}	1407	}
1408		1408
1409	#endif /CONFIG_ANDROID_RECOVERY/	1409	#endif /CONFIG_ANDROID_RECOVERY/
1410		1410
1411	#endif /CONFIG_FSL_FASTBOOT/	1411	#endif /CONFIG_FSL_FASTBOOT/
1412		1412
1413	#ifdef CONFIG_SPL_BUILD	1413	#ifdef CONFIG_SPL_BUILD
1414	#include <asm/arch/mx6-ddr.h>	1414	#include <asm/arch/mx6-ddr.h>
1415	#include <spl.h>	1415	#include <spl.h>
1416	#include <linux/libfdt.h>	1416	#include <linux/libfdt.h>
1417		1417
1418	#ifdef CONFIG_SPL_OS_BOOT	1418	#ifdef CONFIG_SPL_OS_BOOT
1419	int spl_start_uboot(void)	1419	int spl_start_uboot(void)
1420	{	1420	{
1421	gpio_request(KEY_VOL_UP, "KEY Volume UP");	1421	gpio_request(KEY_VOL_UP, "KEY Volume UP");
1422	gpio_direction_input(KEY_VOL_UP);	1422	gpio_direction_input(KEY_VOL_UP);
1423		1423
1424	/* Only enter in Falcon mode if KEY_VOL_UP is pressed */	1424	/* Only enter in Falcon mode if KEY_VOL_UP is pressed */
1425	return gpio_get_value(KEY_VOL_UP);	1425	return gpio_get_value(KEY_VOL_UP);
1426	}	1426	}
1427	#endif	1427	#endif
1428		1428
1429	static void ccgr_init(void)	1429	static void ccgr_init(void)
1430	{	1430	{
1431	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;	1431	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
1432		1432
1433	writel(0x00C03F3F, &ccm->CCGR0);	1433	writel(0x00C03F3F, &ccm->CCGR0);
1434	writel(0x0030FC03, &ccm->CCGR1);	1434	writel(0x0030FC03, &ccm->CCGR1);
1435	writel(0x0FFFC000, &ccm->CCGR2);	1435	writel(0x0FFFC000, &ccm->CCGR2);
1436	writel(0x3FF00000, &ccm->CCGR3);	1436	writel(0x3FF00000, &ccm->CCGR3);
1437	writel(0x00FFF300, &ccm->CCGR4);	1437	writel(0x00FFF300, &ccm->CCGR4);
1438	writel(0x0F0000C3, &ccm->CCGR5);	1438	writel(0x0F0000C3, &ccm->CCGR5);
1439	writel(0x000003FF, &ccm->CCGR6);	1439	writel(0x000003FF, &ccm->CCGR6);
1440	}	1440	}
1441		1441
1442	static int mx6q_dcd_table[] = {	1442	static int mx6q_dcd_table[] = {
1443	0x020e0798, 0x000C0000,	1443	0x020e0798, 0x000C0000,
1444	0x020e0758, 0x00000000,	1444	0x020e0758, 0x00000000,
1445	0x020e0588, 0x00000030,	1445	0x020e0588, 0x00000030,
1446	0x020e0594, 0x00000030,	1446	0x020e0594, 0x00000030,
1447	0x020e056c, 0x00000030,	1447	0x020e056c, 0x00000030,
1448	0x020e0578, 0x00000030,	1448	0x020e0578, 0x00000030,
1449	0x020e074c, 0x00000030,	1449	0x020e074c, 0x00000030,
1450	0x020e057c, 0x00000030,	1450	0x020e057c, 0x00000030,
1451	0x020e058c, 0x00000000,	1451	0x020e058c, 0x00000000,
1452	0x020e059c, 0x00000030,	1452	0x020e059c, 0x00000030,
1453	0x020e05a0, 0x00000030,	1453	0x020e05a0, 0x00000030,
1454	0x020e078c, 0x00000030,	1454	0x020e078c, 0x00000030,
1455	0x020e0750, 0x00020000,	1455	0x020e0750, 0x00020000,
1456	0x020e05a8, 0x00000030,	1456	0x020e05a8, 0x00000030,
1457	0x020e05b0, 0x00000030,	1457	0x020e05b0, 0x00000030,
1458	0x020e0524, 0x00000030,	1458	0x020e0524, 0x00000030,
1459	0x020e051c, 0x00000030,	1459	0x020e051c, 0x00000030,
1460	0x020e0518, 0x00000030,	1460	0x020e0518, 0x00000030,
1461	0x020e050c, 0x00000030,	1461	0x020e050c, 0x00000030,
1462	0x020e05b8, 0x00000030,	1462	0x020e05b8, 0x00000030,
1463	0x020e05c0, 0x00000030,	1463	0x020e05c0, 0x00000030,
1464	0x020e0774, 0x00020000,	1464	0x020e0774, 0x00020000,
1465	0x020e0784, 0x00000030,	1465	0x020e0784, 0x00000030,
1466	0x020e0788, 0x00000030,	1466	0x020e0788, 0x00000030,
1467	0x020e0794, 0x00000030,	1467	0x020e0794, 0x00000030,
1468	0x020e079c, 0x00000030,	1468	0x020e079c, 0x00000030,
1469	0x020e07a0, 0x00000030,	1469	0x020e07a0, 0x00000030,
1470	0x020e07a4, 0x00000030,	1470	0x020e07a4, 0x00000030,
1471	0x020e07a8, 0x00000030,	1471	0x020e07a8, 0x00000030,
1472	0x020e0748, 0x00000030,	1472	0x020e0748, 0x00000030,
1473	0x020e05ac, 0x00000030,	1473	0x020e05ac, 0x00000030,
1474	0x020e05b4, 0x00000030,	1474	0x020e05b4, 0x00000030,
1475	0x020e0528, 0x00000030,	1475	0x020e0528, 0x00000030,
1476	0x020e0520, 0x00000030,	1476	0x020e0520, 0x00000030,
1477	0x020e0514, 0x00000030,	1477	0x020e0514, 0x00000030,
1478	0x020e0510, 0x00000030,	1478	0x020e0510, 0x00000030,
1479	0x020e05bc, 0x00000030,	1479	0x020e05bc, 0x00000030,
1480	0x020e05c4, 0x00000030,	1480	0x020e05c4, 0x00000030,
1481	0x021b0800, 0xa1390003,	1481	0x021b0800, 0xa1390003,
1482	0x021b080c, 0x001F001F,	1482	0x021b080c, 0x001F001F,
1483	0x021b0810, 0x001F001F,	1483	0x021b0810, 0x001F001F,
1484	0x021b480c, 0x001F001F,	1484	0x021b480c, 0x001F001F,
1485	0x021b4810, 0x001F001F,	1485	0x021b4810, 0x001F001F,
1486	0x021b083c, 0x43270338,	1486	0x021b083c, 0x43270338,
1487	0x021b0840, 0x03200314,	1487	0x021b0840, 0x03200314,
1488	0x021b483c, 0x431A032F,	1488	0x021b483c, 0x431A032F,
1489	0x021b4840, 0x03200263,	1489	0x021b4840, 0x03200263,
1490	0x021b0848, 0x4B434748,	1490	0x021b0848, 0x4B434748,
1491	0x021b4848, 0x4445404C,	1491	0x021b4848, 0x4445404C,
1492	0x021b0850, 0x38444542,	1492	0x021b0850, 0x38444542,
1493	0x021b4850, 0x4935493A,	1493	0x021b4850, 0x4935493A,
1494	0x021b081c, 0x33333333,	1494	0x021b081c, 0x33333333,
1495	0x021b0820, 0x33333333,	1495	0x021b0820, 0x33333333,
1496	0x021b0824, 0x33333333,	1496	0x021b0824, 0x33333333,
1497	0x021b0828, 0x33333333,	1497	0x021b0828, 0x33333333,
1498	0x021b481c, 0x33333333,	1498	0x021b481c, 0x33333333,
1499	0x021b4820, 0x33333333,	1499	0x021b4820, 0x33333333,
1500	0x021b4824, 0x33333333,	1500	0x021b4824, 0x33333333,
1501	0x021b4828, 0x33333333,	1501	0x021b4828, 0x33333333,
1502	0x021b08b8, 0x00000800,	1502	0x021b08b8, 0x00000800,
1503	0x021b48b8, 0x00000800,	1503	0x021b48b8, 0x00000800,
1504	0x021b0004, 0x00020036,	1504	0x021b0004, 0x00020036,
1505	0x021b0008, 0x09444040,	1505	0x021b0008, 0x09444040,
1506	0x021b000c, 0x555A7975,	1506	0x021b000c, 0x555A7975,
1507	0x021b0010, 0xFF538F64,	1507	0x021b0010, 0xFF538F64,
1508	0x021b0014, 0x01FF00DB,	1508	0x021b0014, 0x01FF00DB,
1509	0x021b0018, 0x00001740,	1509	0x021b0018, 0x00001740,
1510	0x021b001c, 0x00008000,	1510	0x021b001c, 0x00008000,
1511	0x021b002c, 0x000026d2,	1511	0x021b002c, 0x000026d2,
1512	0x021b0030, 0x005A1023,	1512	0x021b0030, 0x005A1023,
1513	0x021b0040, 0x00000027,	1513	0x021b0040, 0x00000027,
1514	0x021b0000, 0x831A0000,	1514	0x021b0000, 0x831A0000,
1515	0x021b001c, 0x04088032,	1515	0x021b001c, 0x04088032,
1516	0x021b001c, 0x00008033,	1516	0x021b001c, 0x00008033,
1517	0x021b001c, 0x00048031,	1517	0x021b001c, 0x00048031,
1518	0x021b001c, 0x09408030,	1518	0x021b001c, 0x09408030,
1519	0x021b001c, 0x04008040,	1519	0x021b001c, 0x04008040,
1520	0x021b0020, 0x00005800,	1520	0x021b0020, 0x00005800,
1521	0x021b0818, 0x00011117,	1521	0x021b0818, 0x00011117,
1522	0x021b4818, 0x00011117,	1522	0x021b4818, 0x00011117,
1523	0x021b0004, 0x00025576,	1523	0x021b0004, 0x00025576,
1524	0x021b0404, 0x00011006,	1524	0x021b0404, 0x00011006,
1525	0x021b001c, 0x00000000,	1525	0x021b001c, 0x00000000,
1526	};	1526	};
1527		1527
1528	static int mx6qp_dcd_table[] = {	1528	static int mx6qp_dcd_table[] = {
1529	0x020e0798, 0x000c0000,	1529	0x020e0798, 0x000c0000,
1530	0x020e0758, 0x00000000,	1530	0x020e0758, 0x00000000,
1531	0x020e0588, 0x00000030,	1531	0x020e0588, 0x00000030,
1532	0x020e0594, 0x00000030,	1532	0x020e0594, 0x00000030,
1533	0x020e056c, 0x00000030,	1533	0x020e056c, 0x00000030,
1534	0x020e0578, 0x00000030,	1534	0x020e0578, 0x00000030,
1535	0x020e074c, 0x00000030,	1535	0x020e074c, 0x00000030,
1536	0x020e057c, 0x00000030,	1536	0x020e057c, 0x00000030,
1537	0x020e058c, 0x00000000,	1537	0x020e058c, 0x00000000,
1538	0x020e059c, 0x00000030,	1538	0x020e059c, 0x00000030,
1539	0x020e05a0, 0x00000030,	1539	0x020e05a0, 0x00000030,
1540	0x020e078c, 0x00000030,	1540	0x020e078c, 0x00000030,
1541	0x020e0750, 0x00020000,	1541	0x020e0750, 0x00020000,
1542	0x020e05a8, 0x00000030,	1542	0x020e05a8, 0x00000030,
1543	0x020e05b0, 0x00000030,	1543	0x020e05b0, 0x00000030,
1544	0x020e0524, 0x00000030,	1544	0x020e0524, 0x00000030,
1545	0x020e051c, 0x00000030,	1545	0x020e051c, 0x00000030,
1546	0x020e0518, 0x00000030,	1546	0x020e0518, 0x00000030,
1547	0x020e050c, 0x00000030,	1547	0x020e050c, 0x00000030,
1548	0x020e05b8, 0x00000030,	1548	0x020e05b8, 0x00000030,
1549	0x020e05c0, 0x00000030,	1549	0x020e05c0, 0x00000030,
1550	0x020e0774, 0x00020000,	1550	0x020e0774, 0x00020000,
1551	0x020e0784, 0x00000030,	1551	0x020e0784, 0x00000030,
1552	0x020e0788, 0x00000030,	1552	0x020e0788, 0x00000030,
1553	0x020e0794, 0x00000030,	1553	0x020e0794, 0x00000030,
1554	0x020e079c, 0x00000030,	1554	0x020e079c, 0x00000030,
1555	0x020e07a0, 0x00000030,	1555	0x020e07a0, 0x00000030,
1556	0x020e07a4, 0x00000030,	1556	0x020e07a4, 0x00000030,
1557	0x020e07a8, 0x00000030,	1557	0x020e07a8, 0x00000030,
1558	0x020e0748, 0x00000030,	1558	0x020e0748, 0x00000030,
1559	0x020e05ac, 0x00000030,	1559	0x020e05ac, 0x00000030,
1560	0x020e05b4, 0x00000030,	1560	0x020e05b4, 0x00000030,
1561	0x020e0528, 0x00000030,	1561	0x020e0528, 0x00000030,
1562	0x020e0520, 0x00000030,	1562	0x020e0520, 0x00000030,
1563	0x020e0514, 0x00000030,	1563	0x020e0514, 0x00000030,
1564	0x020e0510, 0x00000030,	1564	0x020e0510, 0x00000030,
1565	0x020e05bc, 0x00000030,	1565	0x020e05bc, 0x00000030,
1566	0x020e05c4, 0x00000030,	1566	0x020e05c4, 0x00000030,
1567	0x021b0800, 0xa1390003,	1567	0x021b0800, 0xa1390003,
1568	0x021b080c, 0x001b001e,	1568	0x021b080c, 0x001b001e,
1569	0x021b0810, 0x002e0029,	1569	0x021b0810, 0x002e0029,
1570	0x021b480c, 0x001b002a,	1570	0x021b480c, 0x001b002a,
1571	0x021b4810, 0x0019002c,	1571	0x021b4810, 0x0019002c,
1572	0x021b083c, 0x43240334,	1572	0x021b083c, 0x43240334,
1573	0x021b0840, 0x0324031a,	1573	0x021b0840, 0x0324031a,
1574	0x021b483c, 0x43340344,	1574	0x021b483c, 0x43340344,
1575	0x021b4840, 0x03280276,	1575	0x021b4840, 0x03280276,
1576	0x021b0848, 0x44383A3E,	1576	0x021b0848, 0x44383A3E,
1577	0x021b4848, 0x3C3C3846,	1577	0x021b4848, 0x3C3C3846,
1578	0x021b0850, 0x2e303230,	1578	0x021b0850, 0x2e303230,
1579	0x021b4850, 0x38283E34,	1579	0x021b4850, 0x38283E34,
1580	0x021b081c, 0x33333333,	1580	0x021b081c, 0x33333333,
1581	0x021b0820, 0x33333333,	1581	0x021b0820, 0x33333333,
1582	0x021b0824, 0x33333333,	1582	0x021b0824, 0x33333333,
1583	0x021b0828, 0x33333333,	1583	0x021b0828, 0x33333333,
1584	0x021b481c, 0x33333333,	1584	0x021b481c, 0x33333333,
1585	0x021b4820, 0x33333333,	1585	0x021b4820, 0x33333333,
1586	0x021b4824, 0x33333333,	1586	0x021b4824, 0x33333333,
1587	0x021b4828, 0x33333333,	1587	0x021b4828, 0x33333333,
1588	0x021b08c0, 0x24912249,	1588	0x021b08c0, 0x24912249,
1589	0x021b48c0, 0x24914289,	1589	0x021b48c0, 0x24914289,
1590	0x021b08b8, 0x00000800,	1590	0x021b08b8, 0x00000800,
1591	0x021b48b8, 0x00000800,	1591	0x021b48b8, 0x00000800,
1592	0x021b0004, 0x00020036,	1592	0x021b0004, 0x00020036,
1593	0x021b0008, 0x24444040,	1593	0x021b0008, 0x24444040,
1594	0x021b000c, 0x555A7955,	1594	0x021b000c, 0x555A7955,
1595	0x021b0010, 0xFF320F64,	1595	0x021b0010, 0xFF320F64,
1596	0x021b0014, 0x01ff00db,	1596	0x021b0014, 0x01ff00db,
1597	0x021b0018, 0x00001740,	1597	0x021b0018, 0x00001740,
1598	0x021b001c, 0x00008000,	1598	0x021b001c, 0x00008000,
1599	0x021b002c, 0x000026d2,	1599	0x021b002c, 0x000026d2,
1600	0x021b0030, 0x005A1023,	1600	0x021b0030, 0x005A1023,
1601	0x021b0040, 0x00000027,	1601	0x021b0040, 0x00000027,
1602	0x021b0400, 0x14420000,	1602	0x021b0400, 0x14420000,
1603	0x021b0000, 0x831A0000,	1603	0x021b0000, 0x831A0000,
1604	0x021b0890, 0x00400C58,	1604	0x021b0890, 0x00400C58,
1605	0x00bb0008, 0x00000000,	1605	0x00bb0008, 0x00000000,
1606	0x00bb000c, 0x2891E41A,	1606	0x00bb000c, 0x2891E41A,
1607	0x00bb0038, 0x00000564,	1607	0x00bb0038, 0x00000564,
1608	0x00bb0014, 0x00000040,	1608	0x00bb0014, 0x00000040,
1609	0x00bb0028, 0x00000020,	1609	0x00bb0028, 0x00000020,
1610	0x00bb002c, 0x00000020,	1610	0x00bb002c, 0x00000020,
1611	0x021b001c, 0x04088032,	1611	0x021b001c, 0x04088032,
1612	0x021b001c, 0x00008033,	1612	0x021b001c, 0x00008033,
1613	0x021b001c, 0x00048031,	1613	0x021b001c, 0x00048031,
1614	0x021b001c, 0x09408030,	1614	0x021b001c, 0x09408030,
1615	0x021b001c, 0x04008040,	1615	0x021b001c, 0x04008040,
1616	0x021b0020, 0x00005800,	1616	0x021b0020, 0x00005800,
1617	0x021b0818, 0x00011117,	1617	0x021b0818, 0x00011117,
1618	0x021b4818, 0x00011117,	1618	0x021b4818, 0x00011117,
1619	0x021b0004, 0x00025576,	1619	0x021b0004, 0x00025576,
1620	0x021b0404, 0x00011006,	1620	0x021b0404, 0x00011006,
1621	0x021b001c, 0x00000000,	1621	0x021b001c, 0x00000000,
1622	};	1622	};
1623		1623
1624	static int mx6dl_dcd_table[] = {	1624	static int mx6dl_dcd_table[] = {
1625	0x020e0774, 0x000C0000,	1625	0x020e0774, 0x000C0000,
1626	0x020e0754, 0x00000000,	1626	0x020e0754, 0x00000000,
1627	0x020e04ac, 0x00000030,	1627	0x020e04ac, 0x00000030,
1628	0x020e04b0, 0x00000030,	1628	0x020e04b0, 0x00000030,
1629	0x020e0464, 0x00000030,	1629	0x020e0464, 0x00000030,
1630	0x020e0490, 0x00000030,	1630	0x020e0490, 0x00000030,
1631	0x020e074c, 0x00000030,	1631	0x020e074c, 0x00000030,
1632	0x020e0494, 0x00000030,	1632	0x020e0494, 0x00000030,
1633	0x020e04a0, 0x00000000,	1633	0x020e04a0, 0x00000000,
1634	0x020e04b4, 0x00000030,	1634	0x020e04b4, 0x00000030,
1635	0x020e04b8, 0x00000030,	1635	0x020e04b8, 0x00000030,
1636	0x020e076c, 0x00000030,	1636	0x020e076c, 0x00000030,
1637	0x020e0750, 0x00020000,	1637	0x020e0750, 0x00020000,
1638	0x020e04bc, 0x00000030,	1638	0x020e04bc, 0x00000030,
1639	0x020e04c0, 0x00000030,	1639	0x020e04c0, 0x00000030,
1640	0x020e04c4, 0x00000030,	1640	0x020e04c4, 0x00000030,
1641	0x020e04c8, 0x00000030,	1641	0x020e04c8, 0x00000030,
1642	0x020e04cc, 0x00000030,	1642	0x020e04cc, 0x00000030,
1643	0x020e04d0, 0x00000030,	1643	0x020e04d0, 0x00000030,
1644	0x020e04d4, 0x00000030,	1644	0x020e04d4, 0x00000030,
1645	0x020e04d8, 0x00000030,	1645	0x020e04d8, 0x00000030,
1646	0x020e0760, 0x00020000,	1646	0x020e0760, 0x00020000,
1647	0x020e0764, 0x00000030,	1647	0x020e0764, 0x00000030,
1648	0x020e0770, 0x00000030,	1648	0x020e0770, 0x00000030,
1649	0x020e0778, 0x00000030,	1649	0x020e0778, 0x00000030,
1650	0x020e077c, 0x00000030,	1650	0x020e077c, 0x00000030,
1651	0x020e0780, 0x00000030,	1651	0x020e0780, 0x00000030,
1652	0x020e0784, 0x00000030,	1652	0x020e0784, 0x00000030,
1653	0x020e078c, 0x00000030,	1653	0x020e078c, 0x00000030,
1654	0x020e0748, 0x00000030,	1654	0x020e0748, 0x00000030,
1655	0x020e0470, 0x00000030,	1655	0x020e0470, 0x00000030,
1656	0x020e0474, 0x00000030,	1656	0x020e0474, 0x00000030,
1657	0x020e0478, 0x00000030,	1657	0x020e0478, 0x00000030,
1658	0x020e047c, 0x00000030,	1658	0x020e047c, 0x00000030,
1659	0x020e0480, 0x00000030,	1659	0x020e0480, 0x00000030,
1660	0x020e0484, 0x00000030,	1660	0x020e0484, 0x00000030,
1661	0x020e0488, 0x00000030,	1661	0x020e0488, 0x00000030,
1662	0x020e048c, 0x00000030,	1662	0x020e048c, 0x00000030,
1663	0x021b0800, 0xa1390003,	1663	0x021b0800, 0xa1390003,
1664	0x021b080c, 0x001F001F,	1664	0x021b080c, 0x001F001F,
1665	0x021b0810, 0x001F001F,	1665	0x021b0810, 0x001F001F,
1666	0x021b480c, 0x001F001F,	1666	0x021b480c, 0x001F001F,
1667	0x021b4810, 0x001F001F,	1667	0x021b4810, 0x001F001F,
1668	0x021b083c, 0x4220021F,	1668	0x021b083c, 0x4220021F,
1669	0x021b0840, 0x0207017E,	1669	0x021b0840, 0x0207017E,
1670	0x021b483c, 0x4201020C,	1670	0x021b483c, 0x4201020C,
1671	0x021b4840, 0x01660172,	1671	0x021b4840, 0x01660172,
1672	0x021b0848, 0x4A4D4E4D,	1672	0x021b0848, 0x4A4D4E4D,
1673	0x021b4848, 0x4A4F5049,	1673	0x021b4848, 0x4A4F5049,
1674	0x021b0850, 0x3F3C3D31,	1674	0x021b0850, 0x3F3C3D31,
1675	0x021b4850, 0x3238372B,	1675	0x021b4850, 0x3238372B,
1676	0x021b081c, 0x33333333,	1676	0x021b081c, 0x33333333,
1677	0x021b0820, 0x33333333,	1677	0x021b0820, 0x33333333,
1678	0x021b0824, 0x33333333,	1678	0x021b0824, 0x33333333,
1679	0x021b0828, 0x33333333,	1679	0x021b0828, 0x33333333,
1680	0x021b481c, 0x33333333,	1680	0x021b481c, 0x33333333,
1681	0x021b4820, 0x33333333,	1681	0x021b4820, 0x33333333,
1682	0x021b4824, 0x33333333,	1682	0x021b4824, 0x33333333,
1683	0x021b4828, 0x33333333,	1683	0x021b4828, 0x33333333,
1684	0x021b08b8, 0x00000800,	1684	0x021b08b8, 0x00000800,
1685	0x021b48b8, 0x00000800,	1685	0x021b48b8, 0x00000800,
1686	0x021b0004, 0x0002002D,	1686	0x021b0004, 0x0002002D,
1687	0x021b0008, 0x00333030,	1687	0x021b0008, 0x00333030,
1688	0x021b000c, 0x3F435313,	1688	0x021b000c, 0x3F435313,
1689	0x021b0010, 0xB66E8B63,	1689	0x021b0010, 0xB66E8B63,
1690	0x021b0014, 0x01FF00DB,	1690	0x021b0014, 0x01FF00DB,
1691	0x021b0018, 0x00001740,	1691	0x021b0018, 0x00001740,
1692	0x021b001c, 0x00008000,	1692	0x021b001c, 0x00008000,
1693	0x021b002c, 0x000026d2,	1693	0x021b002c, 0x000026d2,
1694	0x021b0030, 0x00431023,	1694	0x021b0030, 0x00431023,
1695	0x021b0040, 0x00000027,	1695	0x021b0040, 0x00000027,
1696	0x021b0000, 0x831A0000,	1696	0x021b0000, 0x831A0000,
1697	0x021b001c, 0x04008032,	1697	0x021b001c, 0x04008032,
1698	0x021b001c, 0x00008033,	1698	0x021b001c, 0x00008033,
1699	0x021b001c, 0x00048031,	1699	0x021b001c, 0x00048031,
1700	0x021b001c, 0x05208030,	1700	0x021b001c, 0x05208030,
1701	0x021b001c, 0x04008040,	1701	0x021b001c, 0x04008040,
1702	0x021b0020, 0x00005800,	1702	0x021b0020, 0x00005800,
1703	0x021b0818, 0x00011117,	1703	0x021b0818, 0x00011117,
1704	0x021b4818, 0x00011117,	1704	0x021b4818, 0x00011117,
1705	0x021b0004, 0x0002556D,	1705	0x021b0004, 0x0002556D,
1706	0x021b0404, 0x00011006,	1706	0x021b0404, 0x00011006,
1707	0x021b001c, 0x00000000,	1707	0x021b001c, 0x00000000,
1708	};	1708	};
1709		1709
1710	static void ddr_init(int *table, int size)	1710	static void ddr_init(int *table, int size)
1711	{	1711	{
1712	int i;	1712	int i;
1713		1713
1714	for (i = 0; i < size / 2 ; i++)	1714	for (i = 0; i < size / 2 ; i++)
1715	writel(table[2 * i + 1], table[2 * i]);	1715	writel(table[2 * i + 1], table[2 * i]);
1716	}	1716	}
1717		1717
1718	static void spl_dram_init(void)	1718	static void spl_dram_init(void)
1719	{	1719	{
1720	if (is_mx6dq())	1720	if (is_mx6dq())
1721	ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));	1721	ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
1722	else if (is_mx6dqp())	1722	else if (is_mx6dqp())
1723	ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));	1723	ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
1724	else if (is_mx6sdl())	1724	else if (is_mx6sdl())
1725	ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));	1725	ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1726	}	1726	}
1727		1727
1728	void board_init_f(ulong dummy)	1728	void board_init_f(ulong dummy)
1729	{	1729	{
1730	/* DDR initialization */	1730	/* DDR initialization */
1731	spl_dram_init();	1731	spl_dram_init();
1732		1732
1733	/* setup AIPS and disable watchdog */	1733	/* setup AIPS and disable watchdog */
1734	arch_cpu_init();	1734	arch_cpu_init();
1735		1735
1736	ccgr_init();	1736	ccgr_init();
1737	gpr_init();	1737	gpr_init();
1738		1738
1739	/* iomux and setup of i2c */	1739	/* iomux and setup of i2c */
1740	board_early_init_f();	1740	board_early_init_f();
1741		1741
1742	/* setup GP timer */	1742	/* setup GP timer */
1743	timer_init();	1743	timer_init();
1744		1744
1745	/* UART clocks enabled and gd valid - init serial console */	1745	/* UART clocks enabled and gd valid - init serial console */
1746	preloader_console_init();	1746	preloader_console_init();
1747		1747
1748	/* Clear the BSS. */	1748	/* Clear the BSS. */
1749	memset(__bss_start, 0, __bss_end - __bss_start);	1749	memset(__bss_start, 0, __bss_end - __bss_start);
1750		1750
1751	/* load/boot image from boot device */	1751	/* load/boot image from boot device */
1752	board_init_r(NULL, 0);	1752	board_init_r(NULL, 0);
1753	}	1753	}
1754	#endif	1754	#endif
1755		1755

configs/smarcfimx6_dl_1g_ser0_android_defconfig

Diff comments View file @ 5769f67

1	CONFIG_ARM=y	1	CONFIG_ARM=y
2	CONFIG_ARCH_MX6=y	2	CONFIG_ARCH_MX6=y
3	CONFIG_TARGET_SMARCFIMX6=y	3	CONFIG_TARGET_SMARCFIMX6=y
4	CONFIG_VIDEO=y	4	CONFIG_VIDEO=y
5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6dl_4x_k4b2g1646q.cfg,MX6DL,ANDROID_SUPPORT"	5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6dl_4x_k4b2g1646q.cfg,MX6DL,ANDROID_SUPPORT"
6	CONFIG_CONSOLE_SER0=y	6	CONFIG_CONSOLE_SER0=y
7	CONFIG_SPI_BOOT=y	7	CONFIG_SPI_BOOT=y
8	CONFIG_BOOTDELAY=1	8	CONFIG_BOOTDELAY=1
9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y	9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y
10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y	10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
11	CONFIG_HUSH_PARSER=y	11	CONFIG_HUSH_PARSER=y
12	CONFIG_CMD_BOOTZ=y	12	CONFIG_CMD_BOOTZ=y
13	CONFIG_SYS_PROMPT="U-Boot# "	13	CONFIG_SYS_PROMPT="U-Boot# "
14	CONFIG_SYS_HUSH_PARSER=y	14	CONFIG_SYS_HUSH_PARSER=y
15	# CONFIG_CMD_IMLS is not set	15	# CONFIG_CMD_IMLS is not set
16	# CONFIG_CMD_FLASH is not set	16	# CONFIG_CMD_FLASH is not set
17	CONFIG_CMD_MEMTEST=y	17	CONFIG_CMD_MEMTEST=y
18	CONFIG_CMD_MMC=y	18	CONFIG_CMD_MMC=y
19	CONFIG_CMD_SF=y	19	CONFIG_CMD_SF=y
20	CONFIG_CMD_I2C=y	20	CONFIG_CMD_I2C=y
21	CONFIG_CMD_USB=y	21	CONFIG_CMD_USB=y
22	CONFIG_CMD_DFU=y	22	CONFIG_CMD_DFU=y
23	CONFIG_CMD_USB_MASS_STORAGE=y	23	CONFIG_CMD_USB_MASS_STORAGE=y
24	CONFIG_CMD_GPIO=y	24	CONFIG_CMD_GPIO=y
25	CONFIG_CMD_DHCP=y	25	CONFIG_CMD_DHCP=y
26	CONFIG_CMD_MII=y	26	CONFIG_CMD_MII=y
27	CONFIG_CMD_PING=y	27	CONFIG_CMD_PING=y
28	CONFIG_CMD_CACHE=y	28	CONFIG_CMD_CACHE=y
29	CONFIG_CMD_EXT2=y	29	CONFIG_CMD_EXT2=y
30	CONFIG_CMD_EXT4=y	30	CONFIG_CMD_EXT4=y
31	CONFIG_CMD_EXT4_WRITE=y	31	CONFIG_CMD_EXT4_WRITE=y
32	CONFIG_CMD_FAT=y	32	CONFIG_CMD_FAT=y
33	CONFIG_CMD_FS_GENERIC=y	33	CONFIG_CMD_FS_GENERIC=y
34	CONFIG_CMD_PART=y	34	CONFIG_CMD_PART=y
35	CONFIG_DFU_MMC=y	35	CONFIG_DFU_MMC=y
36	CONFIG_DFU_SF=y	36	CONFIG_DFU_SF=y
37	CONFIG_USB=y	37	CONFIG_USB=y
38	CONFIG_USB_STORAGE=y	38	CONFIG_USB_STORAGE=y
39	CONFIG_USB_GADGET=y	39	CONFIG_USB_GADGET=y
40	CONFIG_CI_UDC=y	40	CONFIG_CI_UDC=y
41	CONFIG_USB_GADGET_DOWNLOAD=y	41	CONFIG_USB_GADGET_DOWNLOAD=y
42	CONFIG_USB_GADGET_MANUFACTURER="FSL"	42	CONFIG_USB_GADGET_MANUFACTURER="FSL"
43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525	43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525
44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5	44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
45	# CONFIG_VIDEO_SW_CURSOR is not set	45	# CONFIG_VIDEO_SW_CURSOR is not set
46	CONFIG_OF_LIBFDT=y	46	CONFIG_OF_LIBFDT=y
47		47
48	CONFIG_DEFAULT_DEVICE_TREE="imx6q-smarcfimx6"	48	CONFIG_DEFAULT_DEVICE_TREE="imx6dl-smarcfimx6"
49	CONFIG_DEFAULT_FDT_FILE="imx6q-smarcfimx6.dtb"	49	CONFIG_DEFAULT_FDT_FILE="imx6dl-smarcfimx6.dtb"
50	CONFIG_OF_CONTROL=y	50	CONFIG_OF_CONTROL=y
51	CONFIG_DM_GPIO=y	51	CONFIG_DM_GPIO=y
52	CONFIG_DM_I2C=y	52	CONFIG_DM_I2C=y
53	CONFIG_DM_MMC=y	53	CONFIG_DM_MMC=y
54	CONFIG_PINCTRL=y	54	CONFIG_PINCTRL=y
55	CONFIG_PINCTRL_IMX6=y	55	CONFIG_PINCTRL_IMX6=y
56	CONFIG_DM_REGULATOR=y	56	CONFIG_DM_REGULATOR=y
57	CONFIG_DM_REGULATOR_FIXED=y	57	CONFIG_DM_REGULATOR_FIXED=y
58	CONFIG_DM_REGULATOR_GPIO=y	58	CONFIG_DM_REGULATOR_GPIO=y
59	CONFIG_DM_ETH=y	59	CONFIG_DM_ETH=y
60	CONFIG_DM_USB=y	60	CONFIG_DM_USB=y
61		61
62	CONFIG_CMD_FASTBOOT=y	62	CONFIG_CMD_FASTBOOT=y
63	CONFIG_USB_FUNCTION_FASTBOOT=y	63	CONFIG_USB_FUNCTION_FASTBOOT=y
64	CONFIG_FSL_FASTBOOT=y	64	CONFIG_FSL_FASTBOOT=y
65	CONFIG_FASTBOOT=y	65	CONFIG_FASTBOOT=y
66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000	66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000	67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000
68	CONFIG_FASTBOOT_FLASH=y	68	CONFIG_FASTBOOT_FLASH=y
69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2	69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2
70	CONFIG_EFI_PARTITION=y	70	CONFIG_EFI_PARTITION=y
71		71

configs/smarcfimx6_dl_1g_ser0_defconfig

Diff comments View file @ 5769f67

1	CONFIG_ARM=y	1	CONFIG_ARM=y
2	CONFIG_ARCH_MX6=y	2	CONFIG_ARCH_MX6=y
3	CONFIG_TARGET_SMARCFIMX6=y	3	CONFIG_TARGET_SMARCFIMX6=y
4	CONFIG_VIDEO=y	4	CONFIG_VIDEO=y
5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6dl_4x_k4b2g1646q.cfg,MX6DL"	5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6dl_4x_k4b2g1646q.cfg,MX6DL"
6	CONFIG_CONSOLE_SER0=y	6	CONFIG_CONSOLE_SER0=y
7	CONFIG_SPI_BOOT=y	7	CONFIG_SPI_BOOT=y
8	CONFIG_BOOTDELAY=1	8	CONFIG_BOOTDELAY=1
9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y	9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y
10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y	10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
11	CONFIG_HUSH_PARSER=y	11	CONFIG_HUSH_PARSER=y
12	CONFIG_CMD_BOOTZ=y	12	CONFIG_CMD_BOOTZ=y
13	CONFIG_SYS_PROMPT="U-Boot# "	13	CONFIG_SYS_PROMPT="U-Boot# "
14	CONFIG_SYS_HUSH_PARSER=y	14	CONFIG_SYS_HUSH_PARSER=y
15	# CONFIG_CMD_IMLS is not set	15	# CONFIG_CMD_IMLS is not set
16	# CONFIG_CMD_FLASH is not set	16	# CONFIG_CMD_FLASH is not set
17	CONFIG_CMD_MEMTEST=y	17	CONFIG_CMD_MEMTEST=y
18	CONFIG_CMD_MMC=y	18	CONFIG_CMD_MMC=y
19	CONFIG_CMD_SF=y	19	CONFIG_CMD_SF=y
20	CONFIG_CMD_I2C=y	20	CONFIG_CMD_I2C=y
21	CONFIG_CMD_USB=y	21	CONFIG_CMD_USB=y
22	CONFIG_CMD_DFU=y	22	CONFIG_CMD_DFU=y
23	CONFIG_CMD_USB_MASS_STORAGE=y	23	CONFIG_CMD_USB_MASS_STORAGE=y
24	CONFIG_CMD_GPIO=y	24	CONFIG_CMD_GPIO=y
25	CONFIG_CMD_DHCP=y	25	CONFIG_CMD_DHCP=y
26	CONFIG_CMD_MII=y	26	CONFIG_CMD_MII=y
27	CONFIG_CMD_PING=y	27	CONFIG_CMD_PING=y
28	CONFIG_CMD_CACHE=y	28	CONFIG_CMD_CACHE=y
29	CONFIG_CMD_EXT2=y	29	CONFIG_CMD_EXT2=y
30	CONFIG_CMD_EXT4=y	30	CONFIG_CMD_EXT4=y
31	CONFIG_CMD_EXT4_WRITE=y	31	CONFIG_CMD_EXT4_WRITE=y
32	CONFIG_CMD_FAT=y	32	CONFIG_CMD_FAT=y
33	CONFIG_CMD_FS_GENERIC=y	33	CONFIG_CMD_FS_GENERIC=y
34	CONFIG_CMD_PART=y	34	CONFIG_CMD_PART=y
35	CONFIG_DFU_MMC=y	35	CONFIG_DFU_MMC=y
36	CONFIG_DFU_SF=y	36	CONFIG_DFU_SF=y
37	CONFIG_USB=y	37	CONFIG_USB=y
38	CONFIG_USB_STORAGE=y	38	CONFIG_USB_STORAGE=y
39	CONFIG_USB_GADGET=y	39	CONFIG_USB_GADGET=y
40	CONFIG_CI_UDC=y	40	CONFIG_CI_UDC=y
41	CONFIG_USB_GADGET_DOWNLOAD=y	41	CONFIG_USB_GADGET_DOWNLOAD=y
42	CONFIG_USB_GADGET_MANUFACTURER="FSL"	42	CONFIG_USB_GADGET_MANUFACTURER="FSL"
43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525	43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525
44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5	44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
45	# CONFIG_VIDEO_SW_CURSOR is not set	45	# CONFIG_VIDEO_SW_CURSOR is not set
46	CONFIG_OF_LIBFDT=y	46	CONFIG_OF_LIBFDT=y
47		47
48	CONFIG_DEFAULT_DEVICE_TREE="imx6q-smarcfimx6"	48	CONFIG_DEFAULT_DEVICE_TREE="imx6dl-smarcfimx6"
49	CONFIG_DEFAULT_FDT_FILE="imx6q-smarcfimx6.dtb"	49	CONFIG_DEFAULT_FDT_FILE="imx6dl-smarcfimx6.dtb"
50	CONFIG_OF_CONTROL=y	50	CONFIG_OF_CONTROL=y
51	CONFIG_DM_GPIO=y	51	CONFIG_DM_GPIO=y
52	CONFIG_DM_I2C=y	52	CONFIG_DM_I2C=y
53	CONFIG_DM_MMC=y	53	CONFIG_DM_MMC=y
54	CONFIG_PINCTRL=y	54	CONFIG_PINCTRL=y
55	CONFIG_PINCTRL_IMX6=y	55	CONFIG_PINCTRL_IMX6=y
56	CONFIG_DM_REGULATOR=y	56	CONFIG_DM_REGULATOR=y
57	CONFIG_DM_REGULATOR_FIXED=y	57	CONFIG_DM_REGULATOR_FIXED=y
58	CONFIG_DM_REGULATOR_GPIO=y	58	CONFIG_DM_REGULATOR_GPIO=y
59	CONFIG_DM_ETH=y	59	CONFIG_DM_ETH=y
60	CONFIG_DM_USB=y	60	CONFIG_DM_USB=y
61		61
62	CONFIG_CMD_FASTBOOT=y	62	CONFIG_CMD_FASTBOOT=y
63	CONFIG_USB_FUNCTION_FASTBOOT=y	63	CONFIG_USB_FUNCTION_FASTBOOT=y
64	CONFIG_FSL_FASTBOOT=y	64	CONFIG_FSL_FASTBOOT=y
65	CONFIG_FASTBOOT=y	65	CONFIG_FASTBOOT=y
66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000	66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000	67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000
68	CONFIG_FASTBOOT_FLASH=y	68	CONFIG_FASTBOOT_FLASH=y
69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2	69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2
70	CONFIG_EFI_PARTITION=y	70	CONFIG_EFI_PARTITION=y
71		71

configs/smarcfimx6_dl_1g_ser1_android_defconfig

Diff comments View file @ 5769f67

1	CONFIG_ARM=y	1	CONFIG_ARM=y
2	CONFIG_ARCH_MX6=y	2	CONFIG_ARCH_MX6=y
3	CONFIG_TARGET_SMARCFIMX6=y	3	CONFIG_TARGET_SMARCFIMX6=y
4	CONFIG_VIDEO=y	4	CONFIG_VIDEO=y
5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6dl_4x_k4b2g1646q.cfg,MX6DL,ANDROID_SUPPORT"	5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6dl_4x_k4b2g1646q.cfg,MX6DL,ANDROID_SUPPORT"
6	CONFIG_CONSOLE_SER1=y	6	CONFIG_CONSOLE_SER1=y
7	CONFIG_SPI_BOOT=y	7	CONFIG_SPI_BOOT=y
8	CONFIG_BOOTDELAY=1	8	CONFIG_BOOTDELAY=1
9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y	9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y
10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y	10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
11	CONFIG_HUSH_PARSER=y	11	CONFIG_HUSH_PARSER=y
12	CONFIG_CMD_BOOTZ=y	12	CONFIG_CMD_BOOTZ=y
13	CONFIG_SYS_PROMPT="U-Boot# "	13	CONFIG_SYS_PROMPT="U-Boot# "
14	CONFIG_SYS_HUSH_PARSER=y	14	CONFIG_SYS_HUSH_PARSER=y
15	# CONFIG_CMD_IMLS is not set	15	# CONFIG_CMD_IMLS is not set
16	# CONFIG_CMD_FLASH is not set	16	# CONFIG_CMD_FLASH is not set
17	CONFIG_CMD_MEMTEST=y	17	CONFIG_CMD_MEMTEST=y
18	CONFIG_CMD_MMC=y	18	CONFIG_CMD_MMC=y
19	CONFIG_CMD_SF=y	19	CONFIG_CMD_SF=y
20	CONFIG_CMD_I2C=y	20	CONFIG_CMD_I2C=y
21	CONFIG_CMD_USB=y	21	CONFIG_CMD_USB=y
22	CONFIG_CMD_DFU=y	22	CONFIG_CMD_DFU=y
23	CONFIG_CMD_USB_MASS_STORAGE=y	23	CONFIG_CMD_USB_MASS_STORAGE=y
24	CONFIG_CMD_GPIO=y	24	CONFIG_CMD_GPIO=y
25	CONFIG_CMD_DHCP=y	25	CONFIG_CMD_DHCP=y
26	CONFIG_CMD_MII=y	26	CONFIG_CMD_MII=y
27	CONFIG_CMD_PING=y	27	CONFIG_CMD_PING=y
28	CONFIG_CMD_CACHE=y	28	CONFIG_CMD_CACHE=y
29	CONFIG_CMD_EXT2=y	29	CONFIG_CMD_EXT2=y
30	CONFIG_CMD_EXT4=y	30	CONFIG_CMD_EXT4=y
31	CONFIG_CMD_EXT4_WRITE=y	31	CONFIG_CMD_EXT4_WRITE=y
32	CONFIG_CMD_FAT=y	32	CONFIG_CMD_FAT=y
33	CONFIG_CMD_FS_GENERIC=y	33	CONFIG_CMD_FS_GENERIC=y
34	CONFIG_CMD_PART=y	34	CONFIG_CMD_PART=y
35	CONFIG_DFU_MMC=y	35	CONFIG_DFU_MMC=y
36	CONFIG_DFU_SF=y	36	CONFIG_DFU_SF=y
37	CONFIG_USB=y	37	CONFIG_USB=y
38	CONFIG_USB_STORAGE=y	38	CONFIG_USB_STORAGE=y
39	CONFIG_USB_GADGET=y	39	CONFIG_USB_GADGET=y
40	CONFIG_CI_UDC=y	40	CONFIG_CI_UDC=y
41	CONFIG_USB_GADGET_DOWNLOAD=y	41	CONFIG_USB_GADGET_DOWNLOAD=y
42	CONFIG_USB_GADGET_MANUFACTURER="FSL"	42	CONFIG_USB_GADGET_MANUFACTURER="FSL"
43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525	43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525
44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5	44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
45	# CONFIG_VIDEO_SW_CURSOR is not set	45	# CONFIG_VIDEO_SW_CURSOR is not set
46	CONFIG_OF_LIBFDT=y	46	CONFIG_OF_LIBFDT=y
47		47
48	CONFIG_DEFAULT_DEVICE_TREE="imx6q-smarcfimx6"	48	CONFIG_DEFAULT_DEVICE_TREE="imx6dl-smarcfimx6"
49	CONFIG_DEFAULT_FDT_FILE="imx6q-smarcfimx6.dtb"	49	CONFIG_DEFAULT_FDT_FILE="imx6dl-smarcfimx6.dtb"
50	CONFIG_OF_CONTROL=y	50	CONFIG_OF_CONTROL=y
51	CONFIG_DM_GPIO=y	51	CONFIG_DM_GPIO=y
52	CONFIG_DM_I2C=y	52	CONFIG_DM_I2C=y
53	CONFIG_DM_MMC=y	53	CONFIG_DM_MMC=y
54	CONFIG_PINCTRL=y	54	CONFIG_PINCTRL=y
55	CONFIG_PINCTRL_IMX6=y	55	CONFIG_PINCTRL_IMX6=y
56	CONFIG_DM_REGULATOR=y	56	CONFIG_DM_REGULATOR=y
57	CONFIG_DM_REGULATOR_FIXED=y	57	CONFIG_DM_REGULATOR_FIXED=y
58	CONFIG_DM_REGULATOR_GPIO=y	58	CONFIG_DM_REGULATOR_GPIO=y
59	CONFIG_DM_ETH=y	59	CONFIG_DM_ETH=y
60	CONFIG_DM_USB=y	60	CONFIG_DM_USB=y
61		61
62	CONFIG_CMD_FASTBOOT=y	62	CONFIG_CMD_FASTBOOT=y
63	CONFIG_USB_FUNCTION_FASTBOOT=y	63	CONFIG_USB_FUNCTION_FASTBOOT=y
64	CONFIG_FSL_FASTBOOT=y	64	CONFIG_FSL_FASTBOOT=y
65	CONFIG_FASTBOOT=y	65	CONFIG_FASTBOOT=y
66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000	66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000	67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000
68	CONFIG_FASTBOOT_FLASH=y	68	CONFIG_FASTBOOT_FLASH=y
69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2	69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2
70	CONFIG_EFI_PARTITION=y	70	CONFIG_EFI_PARTITION=y
71		71

configs/smarcfimx6_dl_1g_ser1_defconfig

Diff comments View file @ 5769f67

1	CONFIG_ARM=y	1	CONFIG_ARM=y
2	CONFIG_ARCH_MX6=y	2	CONFIG_ARCH_MX6=y
3	CONFIG_TARGET_SMARCFIMX6=y	3	CONFIG_TARGET_SMARCFIMX6=y
4	CONFIG_VIDEO=y	4	CONFIG_VIDEO=y
5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6dl_4x_k4b2g1646q.cfg,MX6DL"	5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6dl_4x_k4b2g1646q.cfg,MX6DL"
6	CONFIG_CONSOLE_SER1=y	6	CONFIG_CONSOLE_SER1=y
7	CONFIG_SPI_BOOT=y	7	CONFIG_SPI_BOOT=y
8	CONFIG_BOOTDELAY=1	8	CONFIG_BOOTDELAY=1
9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y	9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y
10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y	10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
11	CONFIG_HUSH_PARSER=y	11	CONFIG_HUSH_PARSER=y
12	CONFIG_CMD_BOOTZ=y	12	CONFIG_CMD_BOOTZ=y
13	CONFIG_SYS_PROMPT="U-Boot# "	13	CONFIG_SYS_PROMPT="U-Boot# "
14	CONFIG_SYS_HUSH_PARSER=y	14	CONFIG_SYS_HUSH_PARSER=y
15	# CONFIG_CMD_IMLS is not set	15	# CONFIG_CMD_IMLS is not set
16	# CONFIG_CMD_FLASH is not set	16	# CONFIG_CMD_FLASH is not set
17	CONFIG_CMD_MEMTEST=y	17	CONFIG_CMD_MEMTEST=y
18	CONFIG_CMD_MMC=y	18	CONFIG_CMD_MMC=y
19	CONFIG_CMD_SF=y	19	CONFIG_CMD_SF=y
20	CONFIG_CMD_I2C=y	20	CONFIG_CMD_I2C=y
21	CONFIG_CMD_USB=y	21	CONFIG_CMD_USB=y
22	CONFIG_CMD_DFU=y	22	CONFIG_CMD_DFU=y
23	CONFIG_CMD_USB_MASS_STORAGE=y	23	CONFIG_CMD_USB_MASS_STORAGE=y
24	CONFIG_CMD_GPIO=y	24	CONFIG_CMD_GPIO=y
25	CONFIG_CMD_DHCP=y	25	CONFIG_CMD_DHCP=y
26	CONFIG_CMD_MII=y	26	CONFIG_CMD_MII=y
27	CONFIG_CMD_PING=y	27	CONFIG_CMD_PING=y
28	CONFIG_CMD_CACHE=y	28	CONFIG_CMD_CACHE=y
29	CONFIG_CMD_EXT2=y	29	CONFIG_CMD_EXT2=y
30	CONFIG_CMD_EXT4=y	30	CONFIG_CMD_EXT4=y
31	CONFIG_CMD_EXT4_WRITE=y	31	CONFIG_CMD_EXT4_WRITE=y
32	CONFIG_CMD_FAT=y	32	CONFIG_CMD_FAT=y
33	CONFIG_CMD_FS_GENERIC=y	33	CONFIG_CMD_FS_GENERIC=y
34	CONFIG_CMD_PART=y	34	CONFIG_CMD_PART=y
35	CONFIG_DFU_MMC=y	35	CONFIG_DFU_MMC=y
36	CONFIG_DFU_SF=y	36	CONFIG_DFU_SF=y
37	CONFIG_USB=y	37	CONFIG_USB=y
38	CONFIG_USB_STORAGE=y	38	CONFIG_USB_STORAGE=y
39	CONFIG_USB_GADGET=y	39	CONFIG_USB_GADGET=y
40	CONFIG_CI_UDC=y	40	CONFIG_CI_UDC=y
41	CONFIG_USB_GADGET_DOWNLOAD=y	41	CONFIG_USB_GADGET_DOWNLOAD=y
42	CONFIG_USB_GADGET_MANUFACTURER="FSL"	42	CONFIG_USB_GADGET_MANUFACTURER="FSL"
43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525	43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525
44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5	44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
45	# CONFIG_VIDEO_SW_CURSOR is not set	45	# CONFIG_VIDEO_SW_CURSOR is not set
46	CONFIG_OF_LIBFDT=y	46	CONFIG_OF_LIBFDT=y
47		47
48	CONFIG_DEFAULT_DEVICE_TREE="imx6q-smarcfimx6"	48	CONFIG_DEFAULT_DEVICE_TREE="imx6dl-smarcfimx6"
49	CONFIG_DEFAULT_FDT_FILE="imx6q-smarcfimx6.dtb"	49	CONFIG_DEFAULT_FDT_FILE="imx6dl-smarcfimx6.dtb"
50	CONFIG_OF_CONTROL=y	50	CONFIG_OF_CONTROL=y
51	CONFIG_DM_GPIO=y	51	CONFIG_DM_GPIO=y
52	CONFIG_DM_I2C=y	52	CONFIG_DM_I2C=y
53	CONFIG_DM_MMC=y	53	CONFIG_DM_MMC=y
54	CONFIG_PINCTRL=y	54	CONFIG_PINCTRL=y
55	CONFIG_PINCTRL_IMX6=y	55	CONFIG_PINCTRL_IMX6=y
56	CONFIG_DM_REGULATOR=y	56	CONFIG_DM_REGULATOR=y
57	CONFIG_DM_REGULATOR_FIXED=y	57	CONFIG_DM_REGULATOR_FIXED=y
58	CONFIG_DM_REGULATOR_GPIO=y	58	CONFIG_DM_REGULATOR_GPIO=y
59	CONFIG_DM_ETH=y	59	CONFIG_DM_ETH=y
60	CONFIG_DM_USB=y	60	CONFIG_DM_USB=y
61		61
62	CONFIG_CMD_FASTBOOT=y	62	CONFIG_CMD_FASTBOOT=y
63	CONFIG_USB_FUNCTION_FASTBOOT=y	63	CONFIG_USB_FUNCTION_FASTBOOT=y
64	CONFIG_FSL_FASTBOOT=y	64	CONFIG_FSL_FASTBOOT=y
65	CONFIG_FASTBOOT=y	65	CONFIG_FASTBOOT=y
66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000	66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000	67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000
68	CONFIG_FASTBOOT_FLASH=y	68	CONFIG_FASTBOOT_FLASH=y
69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2	69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2
70	CONFIG_EFI_PARTITION=y	70	CONFIG_EFI_PARTITION=y
71		71

configs/smarcfimx6_dl_1g_ser2_android_defconfig

Diff comments View file @ 5769f67

1	CONFIG_ARM=y	1	CONFIG_ARM=y
2	CONFIG_ARCH_MX6=y	2	CONFIG_ARCH_MX6=y
3	CONFIG_TARGET_SMARCFIMX6=y	3	CONFIG_TARGET_SMARCFIMX6=y
4	CONFIG_VIDEO=y	4	CONFIG_VIDEO=y
5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6dl_4x_k4b2g1646q.cfg,MX6DL,ANDROID_SUPPORT"	5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6dl_4x_k4b2g1646q.cfg,MX6DL,ANDROID_SUPPORT"
6	CONFIG_CONSOLE_SER2=y	6	CONFIG_CONSOLE_SER2=y
7	CONFIG_SPI_BOOT=y	7	CONFIG_SPI_BOOT=y
8	CONFIG_BOOTDELAY=1	8	CONFIG_BOOTDELAY=1
9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y	9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y
10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y	10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
11	CONFIG_HUSH_PARSER=y	11	CONFIG_HUSH_PARSER=y
12	CONFIG_CMD_BOOTZ=y	12	CONFIG_CMD_BOOTZ=y
13	CONFIG_SYS_PROMPT="U-Boot# "	13	CONFIG_SYS_PROMPT="U-Boot# "
14	CONFIG_SYS_HUSH_PARSER=y	14	CONFIG_SYS_HUSH_PARSER=y
15	# CONFIG_CMD_IMLS is not set	15	# CONFIG_CMD_IMLS is not set
16	# CONFIG_CMD_FLASH is not set	16	# CONFIG_CMD_FLASH is not set
17	CONFIG_CMD_MEMTEST=y	17	CONFIG_CMD_MEMTEST=y
18	CONFIG_CMD_MMC=y	18	CONFIG_CMD_MMC=y
19	CONFIG_CMD_SF=y	19	CONFIG_CMD_SF=y
20	CONFIG_CMD_I2C=y	20	CONFIG_CMD_I2C=y
21	CONFIG_CMD_USB=y	21	CONFIG_CMD_USB=y
22	CONFIG_CMD_DFU=y	22	CONFIG_CMD_DFU=y
23	CONFIG_CMD_USB_MASS_STORAGE=y	23	CONFIG_CMD_USB_MASS_STORAGE=y
24	CONFIG_CMD_GPIO=y	24	CONFIG_CMD_GPIO=y
25	CONFIG_CMD_DHCP=y	25	CONFIG_CMD_DHCP=y
26	CONFIG_CMD_MII=y	26	CONFIG_CMD_MII=y
27	CONFIG_CMD_PING=y	27	CONFIG_CMD_PING=y
28	CONFIG_CMD_CACHE=y	28	CONFIG_CMD_CACHE=y
29	CONFIG_CMD_EXT2=y	29	CONFIG_CMD_EXT2=y
30	CONFIG_CMD_EXT4=y	30	CONFIG_CMD_EXT4=y
31	CONFIG_CMD_EXT4_WRITE=y	31	CONFIG_CMD_EXT4_WRITE=y
32	CONFIG_CMD_FAT=y	32	CONFIG_CMD_FAT=y
33	CONFIG_CMD_FS_GENERIC=y	33	CONFIG_CMD_FS_GENERIC=y
34	CONFIG_CMD_PART=y	34	CONFIG_CMD_PART=y
35	CONFIG_DFU_MMC=y	35	CONFIG_DFU_MMC=y
36	CONFIG_DFU_SF=y	36	CONFIG_DFU_SF=y
37	CONFIG_USB=y	37	CONFIG_USB=y
38	CONFIG_USB_STORAGE=y	38	CONFIG_USB_STORAGE=y
39	CONFIG_USB_GADGET=y	39	CONFIG_USB_GADGET=y
40	CONFIG_CI_UDC=y	40	CONFIG_CI_UDC=y
41	CONFIG_USB_GADGET_DOWNLOAD=y	41	CONFIG_USB_GADGET_DOWNLOAD=y
42	CONFIG_USB_GADGET_MANUFACTURER="FSL"	42	CONFIG_USB_GADGET_MANUFACTURER="FSL"
43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525	43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525
44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5	44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
45	# CONFIG_VIDEO_SW_CURSOR is not set	45	# CONFIG_VIDEO_SW_CURSOR is not set
46	CONFIG_OF_LIBFDT=y	46	CONFIG_OF_LIBFDT=y
47		47
48	CONFIG_DEFAULT_DEVICE_TREE="imx6q-smarcfimx6"	48	CONFIG_DEFAULT_DEVICE_TREE="imx6dl-smarcfimx6"
49	CONFIG_DEFAULT_FDT_FILE="imx6q-smarcfimx6.dtb"	49	CONFIG_DEFAULT_FDT_FILE="imx6dl-smarcfimx6.dtb"
50	CONFIG_OF_CONTROL=y	50	CONFIG_OF_CONTROL=y
51	CONFIG_DM_GPIO=y	51	CONFIG_DM_GPIO=y
52	CONFIG_DM_I2C=y	52	CONFIG_DM_I2C=y
53	CONFIG_DM_MMC=y	53	CONFIG_DM_MMC=y
54	CONFIG_PINCTRL=y	54	CONFIG_PINCTRL=y
55	CONFIG_PINCTRL_IMX6=y	55	CONFIG_PINCTRL_IMX6=y
56	CONFIG_DM_REGULATOR=y	56	CONFIG_DM_REGULATOR=y
57	CONFIG_DM_REGULATOR_FIXED=y	57	CONFIG_DM_REGULATOR_FIXED=y
58	CONFIG_DM_REGULATOR_GPIO=y	58	CONFIG_DM_REGULATOR_GPIO=y
59	CONFIG_DM_ETH=y	59	CONFIG_DM_ETH=y
60	CONFIG_DM_USB=y	60	CONFIG_DM_USB=y
61		61
62	CONFIG_CMD_FASTBOOT=y	62	CONFIG_CMD_FASTBOOT=y
63	CONFIG_USB_FUNCTION_FASTBOOT=y	63	CONFIG_USB_FUNCTION_FASTBOOT=y
64	CONFIG_FSL_FASTBOOT=y	64	CONFIG_FSL_FASTBOOT=y
65	CONFIG_FASTBOOT=y	65	CONFIG_FASTBOOT=y
66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000	66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000	67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000
68	CONFIG_FASTBOOT_FLASH=y	68	CONFIG_FASTBOOT_FLASH=y
69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2	69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2
70	CONFIG_EFI_PARTITION=y	70	CONFIG_EFI_PARTITION=y
71		71

configs/smarcfimx6_dl_1g_ser2_defconfig

Diff comments View file @ 5769f67

1	CONFIG_ARM=y	1	CONFIG_ARM=y
2	CONFIG_ARCH_MX6=y	2	CONFIG_ARCH_MX6=y
3	CONFIG_TARGET_SMARCFIMX6=y	3	CONFIG_TARGET_SMARCFIMX6=y
4	CONFIG_VIDEO=y	4	CONFIG_VIDEO=y
5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6dl_4x_k4b2g1646q.cfg,MX6DL"	5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6dl_4x_k4b2g1646q.cfg,MX6DL"
6	CONFIG_CONSOLE_SER2=y	6	CONFIG_CONSOLE_SER2=y
7	CONFIG_SPI_BOOT=y	7	CONFIG_SPI_BOOT=y
8	CONFIG_BOOTDELAY=1	8	CONFIG_BOOTDELAY=1
9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y	9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y
10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y	10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
11	CONFIG_HUSH_PARSER=y	11	CONFIG_HUSH_PARSER=y
12	CONFIG_CMD_BOOTZ=y	12	CONFIG_CMD_BOOTZ=y
13	CONFIG_SYS_PROMPT="U-Boot# "	13	CONFIG_SYS_PROMPT="U-Boot# "
14	CONFIG_SYS_HUSH_PARSER=y	14	CONFIG_SYS_HUSH_PARSER=y
15	# CONFIG_CMD_IMLS is not set	15	# CONFIG_CMD_IMLS is not set
16	# CONFIG_CMD_FLASH is not set	16	# CONFIG_CMD_FLASH is not set
17	CONFIG_CMD_MEMTEST=y	17	CONFIG_CMD_MEMTEST=y
18	CONFIG_CMD_MMC=y	18	CONFIG_CMD_MMC=y
19	CONFIG_CMD_SF=y	19	CONFIG_CMD_SF=y
20	CONFIG_CMD_I2C=y	20	CONFIG_CMD_I2C=y
21	CONFIG_CMD_USB=y	21	CONFIG_CMD_USB=y
22	CONFIG_CMD_DFU=y	22	CONFIG_CMD_DFU=y
23	CONFIG_CMD_USB_MASS_STORAGE=y	23	CONFIG_CMD_USB_MASS_STORAGE=y
24	CONFIG_CMD_GPIO=y	24	CONFIG_CMD_GPIO=y
25	CONFIG_CMD_DHCP=y	25	CONFIG_CMD_DHCP=y
26	CONFIG_CMD_MII=y	26	CONFIG_CMD_MII=y
27	CONFIG_CMD_PING=y	27	CONFIG_CMD_PING=y
28	CONFIG_CMD_CACHE=y	28	CONFIG_CMD_CACHE=y
29	CONFIG_CMD_EXT2=y	29	CONFIG_CMD_EXT2=y
30	CONFIG_CMD_EXT4=y	30	CONFIG_CMD_EXT4=y
31	CONFIG_CMD_EXT4_WRITE=y	31	CONFIG_CMD_EXT4_WRITE=y
32	CONFIG_CMD_FAT=y	32	CONFIG_CMD_FAT=y
33	CONFIG_CMD_FS_GENERIC=y	33	CONFIG_CMD_FS_GENERIC=y
34	CONFIG_CMD_PART=y	34	CONFIG_CMD_PART=y
35	CONFIG_DFU_MMC=y	35	CONFIG_DFU_MMC=y
36	CONFIG_DFU_SF=y	36	CONFIG_DFU_SF=y
37	CONFIG_USB=y	37	CONFIG_USB=y
38	CONFIG_USB_STORAGE=y	38	CONFIG_USB_STORAGE=y
39	CONFIG_USB_GADGET=y	39	CONFIG_USB_GADGET=y
40	CONFIG_CI_UDC=y	40	CONFIG_CI_UDC=y
41	CONFIG_USB_GADGET_DOWNLOAD=y	41	CONFIG_USB_GADGET_DOWNLOAD=y
42	CONFIG_USB_GADGET_MANUFACTURER="FSL"	42	CONFIG_USB_GADGET_MANUFACTURER="FSL"
43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525	43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525
44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5	44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
45	# CONFIG_VIDEO_SW_CURSOR is not set	45	# CONFIG_VIDEO_SW_CURSOR is not set
46	CONFIG_OF_LIBFDT=y	46	CONFIG_OF_LIBFDT=y
47		47
48	CONFIG_DEFAULT_DEVICE_TREE="imx6q-smarcfimx6"	48	CONFIG_DEFAULT_DEVICE_TREE="imx6dl-smarcfimx6"
49	CONFIG_DEFAULT_FDT_FILE="imx6q-smarcfimx6.dtb"	49	CONFIG_DEFAULT_FDT_FILE="imx6dl-smarcfimx6.dtb"
50	CONFIG_OF_CONTROL=y	50	CONFIG_OF_CONTROL=y
51	CONFIG_DM_GPIO=y	51	CONFIG_DM_GPIO=y
52	CONFIG_DM_I2C=y	52	CONFIG_DM_I2C=y
53	CONFIG_DM_MMC=y	53	CONFIG_DM_MMC=y
54	CONFIG_PINCTRL=y	54	CONFIG_PINCTRL=y
55	CONFIG_PINCTRL_IMX6=y	55	CONFIG_PINCTRL_IMX6=y
56	CONFIG_DM_REGULATOR=y	56	CONFIG_DM_REGULATOR=y
57	CONFIG_DM_REGULATOR_FIXED=y	57	CONFIG_DM_REGULATOR_FIXED=y
58	CONFIG_DM_REGULATOR_GPIO=y	58	CONFIG_DM_REGULATOR_GPIO=y
59	CONFIG_DM_ETH=y	59	CONFIG_DM_ETH=y
60	CONFIG_DM_USB=y	60	CONFIG_DM_USB=y
61		61
62	CONFIG_CMD_FASTBOOT=y	62	CONFIG_CMD_FASTBOOT=y
63	CONFIG_USB_FUNCTION_FASTBOOT=y	63	CONFIG_USB_FUNCTION_FASTBOOT=y
64	CONFIG_FSL_FASTBOOT=y	64	CONFIG_FSL_FASTBOOT=y
65	CONFIG_FASTBOOT=y	65	CONFIG_FASTBOOT=y
66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000	66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000	67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000
68	CONFIG_FASTBOOT_FLASH=y	68	CONFIG_FASTBOOT_FLASH=y
69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2	69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2
70	CONFIG_EFI_PARTITION=y	70	CONFIG_EFI_PARTITION=y
71		71

configs/smarcfimx6_dl_1g_ser3_android_defconfig

Diff comments View file @ 5769f67

1	CONFIG_ARM=y	1	CONFIG_ARM=y
2	CONFIG_ARCH_MX6=y	2	CONFIG_ARCH_MX6=y
3	CONFIG_TARGET_SMARCFIMX6=y	3	CONFIG_TARGET_SMARCFIMX6=y
4	CONFIG_VIDEO=y	4	CONFIG_VIDEO=y
5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6dl_4x_k4b2g1646q.cfg,MX6DL,ANDROID_SUPPORT"	5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6dl_4x_k4b2g1646q.cfg,MX6DL,ANDROID_SUPPORT"
6	CONFIG_CONSOLE_SER3=y	6	CONFIG_CONSOLE_SER3=y
7	CONFIG_SPI_BOOT=y	7	CONFIG_SPI_BOOT=y
8	CONFIG_BOOTDELAY=1	8	CONFIG_BOOTDELAY=1
9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y	9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y
10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y	10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
11	CONFIG_HUSH_PARSER=y	11	CONFIG_HUSH_PARSER=y
12	CONFIG_CMD_BOOTZ=y	12	CONFIG_CMD_BOOTZ=y
13	CONFIG_SYS_PROMPT="U-Boot# "	13	CONFIG_SYS_PROMPT="U-Boot# "
14	CONFIG_SYS_HUSH_PARSER=y	14	CONFIG_SYS_HUSH_PARSER=y
15	# CONFIG_CMD_IMLS is not set	15	# CONFIG_CMD_IMLS is not set
16	# CONFIG_CMD_FLASH is not set	16	# CONFIG_CMD_FLASH is not set
17	CONFIG_CMD_MEMTEST=y	17	CONFIG_CMD_MEMTEST=y
18	CONFIG_CMD_MMC=y	18	CONFIG_CMD_MMC=y
19	CONFIG_CMD_SF=y	19	CONFIG_CMD_SF=y
20	CONFIG_CMD_I2C=y	20	CONFIG_CMD_I2C=y
21	CONFIG_CMD_USB=y	21	CONFIG_CMD_USB=y
22	CONFIG_CMD_DFU=y	22	CONFIG_CMD_DFU=y
23	CONFIG_CMD_USB_MASS_STORAGE=y	23	CONFIG_CMD_USB_MASS_STORAGE=y
24	CONFIG_CMD_GPIO=y	24	CONFIG_CMD_GPIO=y
25	CONFIG_CMD_DHCP=y	25	CONFIG_CMD_DHCP=y
26	CONFIG_CMD_MII=y	26	CONFIG_CMD_MII=y
27	CONFIG_CMD_PING=y	27	CONFIG_CMD_PING=y
28	CONFIG_CMD_CACHE=y	28	CONFIG_CMD_CACHE=y
29	CONFIG_CMD_EXT2=y	29	CONFIG_CMD_EXT2=y
30	CONFIG_CMD_EXT4=y	30	CONFIG_CMD_EXT4=y
31	CONFIG_CMD_EXT4_WRITE=y	31	CONFIG_CMD_EXT4_WRITE=y
32	CONFIG_CMD_FAT=y	32	CONFIG_CMD_FAT=y
33	CONFIG_CMD_FS_GENERIC=y	33	CONFIG_CMD_FS_GENERIC=y
34	CONFIG_CMD_PART=y	34	CONFIG_CMD_PART=y
35	CONFIG_DFU_MMC=y	35	CONFIG_DFU_MMC=y
36	CONFIG_DFU_SF=y	36	CONFIG_DFU_SF=y
37	CONFIG_USB=y	37	CONFIG_USB=y
38	CONFIG_USB_STORAGE=y	38	CONFIG_USB_STORAGE=y
39	CONFIG_USB_GADGET=y	39	CONFIG_USB_GADGET=y
40	CONFIG_CI_UDC=y	40	CONFIG_CI_UDC=y
41	CONFIG_USB_GADGET_DOWNLOAD=y	41	CONFIG_USB_GADGET_DOWNLOAD=y
42	CONFIG_USB_GADGET_MANUFACTURER="FSL"	42	CONFIG_USB_GADGET_MANUFACTURER="FSL"
43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525	43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525
44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5	44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
45	# CONFIG_VIDEO_SW_CURSOR is not set	45	# CONFIG_VIDEO_SW_CURSOR is not set
46	CONFIG_OF_LIBFDT=y	46	CONFIG_OF_LIBFDT=y
47		47
48	CONFIG_DEFAULT_DEVICE_TREE="imx6q-smarcfimx6"	48	CONFIG_DEFAULT_DEVICE_TREE="imx6dl-smarcfimx6"
49	CONFIG_DEFAULT_FDT_FILE="imx6q-smarcfimx6.dtb"	49	CONFIG_DEFAULT_FDT_FILE="imx6dl-smarcfimx6.dtb"
50	CONFIG_OF_CONTROL=y	50	CONFIG_OF_CONTROL=y
51	CONFIG_DM_GPIO=y	51	CONFIG_DM_GPIO=y
52	CONFIG_DM_I2C=y	52	CONFIG_DM_I2C=y
53	CONFIG_DM_MMC=y	53	CONFIG_DM_MMC=y
54	CONFIG_PINCTRL=y	54	CONFIG_PINCTRL=y
55	CONFIG_PINCTRL_IMX6=y	55	CONFIG_PINCTRL_IMX6=y
56	CONFIG_DM_REGULATOR=y	56	CONFIG_DM_REGULATOR=y
57	CONFIG_DM_REGULATOR_FIXED=y	57	CONFIG_DM_REGULATOR_FIXED=y
58	CONFIG_DM_REGULATOR_GPIO=y	58	CONFIG_DM_REGULATOR_GPIO=y
59	CONFIG_DM_ETH=y	59	CONFIG_DM_ETH=y
60	CONFIG_DM_USB=y	60	CONFIG_DM_USB=y
61		61
62	CONFIG_CMD_FASTBOOT=y	62	CONFIG_CMD_FASTBOOT=y
63	CONFIG_USB_FUNCTION_FASTBOOT=y	63	CONFIG_USB_FUNCTION_FASTBOOT=y
64	CONFIG_FSL_FASTBOOT=y	64	CONFIG_FSL_FASTBOOT=y
65	CONFIG_FASTBOOT=y	65	CONFIG_FASTBOOT=y
66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000	66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000	67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000
68	CONFIG_FASTBOOT_FLASH=y	68	CONFIG_FASTBOOT_FLASH=y
69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2	69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2
70	CONFIG_EFI_PARTITION=y	70	CONFIG_EFI_PARTITION=y
71		71

configs/smarcfimx6_dl_1g_ser3_defconfig

Diff comments View file @ 5769f67

1	CONFIG_ARM=y	1	CONFIG_ARM=y
2	CONFIG_ARCH_MX6=y	2	CONFIG_ARCH_MX6=y
3	CONFIG_TARGET_SMARCFIMX6=y	3	CONFIG_TARGET_SMARCFIMX6=y
4	CONFIG_VIDEO=y	4	CONFIG_VIDEO=y
5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6dl_4x_k4b2g1646q.cfg,MX6DL"	5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6dl_4x_k4b2g1646q.cfg,MX6DL"
6	CONFIG_CONSOLE_SER3=y	6	CONFIG_CONSOLE_SER3=y
7	CONFIG_SPI_BOOT=y	7	CONFIG_SPI_BOOT=y
8	CONFIG_BOOTDELAY=1	8	CONFIG_BOOTDELAY=1
9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y	9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y
10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y	10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
11	CONFIG_HUSH_PARSER=y	11	CONFIG_HUSH_PARSER=y
12	CONFIG_CMD_BOOTZ=y	12	CONFIG_CMD_BOOTZ=y
13	CONFIG_SYS_PROMPT="U-Boot# "	13	CONFIG_SYS_PROMPT="U-Boot# "
14	CONFIG_SYS_HUSH_PARSER=y	14	CONFIG_SYS_HUSH_PARSER=y
15	# CONFIG_CMD_IMLS is not set	15	# CONFIG_CMD_IMLS is not set
16	# CONFIG_CMD_FLASH is not set	16	# CONFIG_CMD_FLASH is not set
17	CONFIG_CMD_MEMTEST=y	17	CONFIG_CMD_MEMTEST=y
18	CONFIG_CMD_MMC=y	18	CONFIG_CMD_MMC=y
19	CONFIG_CMD_SF=y	19	CONFIG_CMD_SF=y
20	CONFIG_CMD_I2C=y	20	CONFIG_CMD_I2C=y
21	CONFIG_CMD_USB=y	21	CONFIG_CMD_USB=y
22	CONFIG_CMD_DFU=y	22	CONFIG_CMD_DFU=y
23	CONFIG_CMD_USB_MASS_STORAGE=y	23	CONFIG_CMD_USB_MASS_STORAGE=y
24	CONFIG_CMD_GPIO=y	24	CONFIG_CMD_GPIO=y
25	CONFIG_CMD_DHCP=y	25	CONFIG_CMD_DHCP=y
26	CONFIG_CMD_MII=y	26	CONFIG_CMD_MII=y
27	CONFIG_CMD_PING=y	27	CONFIG_CMD_PING=y
28	CONFIG_CMD_CACHE=y	28	CONFIG_CMD_CACHE=y
29	CONFIG_CMD_EXT2=y	29	CONFIG_CMD_EXT2=y
30	CONFIG_CMD_EXT4=y	30	CONFIG_CMD_EXT4=y
31	CONFIG_CMD_EXT4_WRITE=y	31	CONFIG_CMD_EXT4_WRITE=y
32	CONFIG_CMD_FAT=y	32	CONFIG_CMD_FAT=y
33	CONFIG_CMD_FS_GENERIC=y	33	CONFIG_CMD_FS_GENERIC=y
34	CONFIG_CMD_PART=y	34	CONFIG_CMD_PART=y
35	CONFIG_DFU_MMC=y	35	CONFIG_DFU_MMC=y
36	CONFIG_DFU_SF=y	36	CONFIG_DFU_SF=y
37	CONFIG_USB=y	37	CONFIG_USB=y
38	CONFIG_USB_STORAGE=y	38	CONFIG_USB_STORAGE=y
39	CONFIG_USB_GADGET=y	39	CONFIG_USB_GADGET=y
40	CONFIG_CI_UDC=y	40	CONFIG_CI_UDC=y
41	CONFIG_USB_GADGET_DOWNLOAD=y	41	CONFIG_USB_GADGET_DOWNLOAD=y
42	CONFIG_USB_GADGET_MANUFACTURER="FSL"	42	CONFIG_USB_GADGET_MANUFACTURER="FSL"
43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525	43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525
44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5	44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
45	# CONFIG_VIDEO_SW_CURSOR is not set	45	# CONFIG_VIDEO_SW_CURSOR is not set
46	CONFIG_OF_LIBFDT=y	46	CONFIG_OF_LIBFDT=y
47		47
48	CONFIG_DEFAULT_DEVICE_TREE="imx6q-smarcfimx6"	48	CONFIG_DEFAULT_DEVICE_TREE="imx6dl-smarcfimx6"
49	CONFIG_DEFAULT_FDT_FILE="imx6q-smarcfimx6.dtb"	49	CONFIG_DEFAULT_FDT_FILE="imx6dl-smarcfimx6.dtb"
50	CONFIG_OF_CONTROL=y	50	CONFIG_OF_CONTROL=y
51	CONFIG_DM_GPIO=y	51	CONFIG_DM_GPIO=y
52	CONFIG_DM_I2C=y	52	CONFIG_DM_I2C=y
53	CONFIG_DM_MMC=y	53	CONFIG_DM_MMC=y
54	CONFIG_PINCTRL=y	54	CONFIG_PINCTRL=y
55	CONFIG_PINCTRL_IMX6=y	55	CONFIG_PINCTRL_IMX6=y
56	CONFIG_DM_REGULATOR=y	56	CONFIG_DM_REGULATOR=y
57	CONFIG_DM_REGULATOR_FIXED=y	57	CONFIG_DM_REGULATOR_FIXED=y
58	CONFIG_DM_REGULATOR_GPIO=y	58	CONFIG_DM_REGULATOR_GPIO=y
59	CONFIG_DM_ETH=y	59	CONFIG_DM_ETH=y
60	CONFIG_DM_USB=y	60	CONFIG_DM_USB=y
61		61
62	CONFIG_CMD_FASTBOOT=y	62	CONFIG_CMD_FASTBOOT=y
63	CONFIG_USB_FUNCTION_FASTBOOT=y	63	CONFIG_USB_FUNCTION_FASTBOOT=y
64	CONFIG_FSL_FASTBOOT=y	64	CONFIG_FSL_FASTBOOT=y
65	CONFIG_FASTBOOT=y	65	CONFIG_FASTBOOT=y
66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000	66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000	67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000
68	CONFIG_FASTBOOT_FLASH=y	68	CONFIG_FASTBOOT_FLASH=y
69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2	69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2
70	CONFIG_EFI_PARTITION=y	70	CONFIG_EFI_PARTITION=y
71		71

configs/smarcfimx6_solo_ser0_android_defconfig

Diff comments View file @ 5769f67

1	CONFIG_ARM=y	1	CONFIG_ARM=y
2	CONFIG_ARCH_MX6=y	2	CONFIG_ARCH_MX6=y
3	CONFIG_TARGET_SMARCFIMX6=y	3	CONFIG_TARGET_SMARCFIMX6=y
4	CONFIG_VIDEO=y	4	CONFIG_VIDEO=y
5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6solo_2x_k4b2g1646q.cfg,MX6S,ANDROID_SUPPORT"	5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6solo_2x_k4b2g1646q.cfg,MX6S,ANDROID_SUPPORT"
6	CONFIG_CONSOLE_SER0=y	6	CONFIG_CONSOLE_SER0=y
7	CONFIG_SPI_BOOT=y	7	CONFIG_SPI_BOOT=y
8	CONFIG_BOOTDELAY=1	8	CONFIG_BOOTDELAY=1
9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y	9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y
10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y	10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
11	CONFIG_HUSH_PARSER=y	11	CONFIG_HUSH_PARSER=y
12	CONFIG_CMD_BOOTZ=y	12	CONFIG_CMD_BOOTZ=y
13	CONFIG_SYS_PROMPT="U-Boot# "	13	CONFIG_SYS_PROMPT="U-Boot# "
14	CONFIG_SYS_HUSH_PARSER=y	14	CONFIG_SYS_HUSH_PARSER=y
15	# CONFIG_CMD_IMLS is not set	15	# CONFIG_CMD_IMLS is not set
16	# CONFIG_CMD_FLASH is not set	16	# CONFIG_CMD_FLASH is not set
17	CONFIG_CMD_MEMTEST=y	17	CONFIG_CMD_MEMTEST=y
18	CONFIG_CMD_MMC=y	18	CONFIG_CMD_MMC=y
19	CONFIG_CMD_SF=y	19	CONFIG_CMD_SF=y
20	CONFIG_CMD_I2C=y	20	CONFIG_CMD_I2C=y
21	CONFIG_CMD_USB=y	21	CONFIG_CMD_USB=y
22	CONFIG_CMD_DFU=y	22	CONFIG_CMD_DFU=y
23	CONFIG_CMD_USB_MASS_STORAGE=y	23	CONFIG_CMD_USB_MASS_STORAGE=y
24	CONFIG_CMD_GPIO=y	24	CONFIG_CMD_GPIO=y
25	CONFIG_CMD_DHCP=y	25	CONFIG_CMD_DHCP=y
26	CONFIG_CMD_MII=y	26	CONFIG_CMD_MII=y
27	CONFIG_CMD_PING=y	27	CONFIG_CMD_PING=y
28	CONFIG_CMD_CACHE=y	28	CONFIG_CMD_CACHE=y
29	CONFIG_CMD_EXT2=y	29	CONFIG_CMD_EXT2=y
30	CONFIG_CMD_EXT4=y	30	CONFIG_CMD_EXT4=y
31	CONFIG_CMD_EXT4_WRITE=y	31	CONFIG_CMD_EXT4_WRITE=y
32	CONFIG_CMD_FAT=y	32	CONFIG_CMD_FAT=y
33	CONFIG_CMD_FS_GENERIC=y	33	CONFIG_CMD_FS_GENERIC=y
34	CONFIG_CMD_PART=y	34	CONFIG_CMD_PART=y
35	CONFIG_DFU_MMC=y	35	CONFIG_DFU_MMC=y
36	CONFIG_DFU_SF=y	36	CONFIG_DFU_SF=y
37	CONFIG_USB=y	37	CONFIG_USB=y
38	CONFIG_USB_STORAGE=y	38	CONFIG_USB_STORAGE=y
39	CONFIG_USB_GADGET=y	39	CONFIG_USB_GADGET=y
40	CONFIG_CI_UDC=y	40	CONFIG_CI_UDC=y
41	CONFIG_USB_GADGET_DOWNLOAD=y	41	CONFIG_USB_GADGET_DOWNLOAD=y
42	CONFIG_USB_GADGET_MANUFACTURER="FSL"	42	CONFIG_USB_GADGET_MANUFACTURER="FSL"
43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525	43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525
44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5	44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
45	# CONFIG_VIDEO_SW_CURSOR is not set	45	# CONFIG_VIDEO_SW_CURSOR is not set
46	CONFIG_OF_LIBFDT=y	46	CONFIG_OF_LIBFDT=y
47		47
48	CONFIG_DEFAULT_DEVICE_TREE="imx6q-smarcfimx6"	48	CONFIG_DEFAULT_DEVICE_TREE="imx6dl-smarcfimx6"
49	CONFIG_DEFAULT_FDT_FILE="imx6q-smarcfimx6.dtb"	49	CONFIG_DEFAULT_FDT_FILE="imx6dl-smarcfimx6.dtb"
50	CONFIG_OF_CONTROL=y	50	CONFIG_OF_CONTROL=y
51	CONFIG_DM_GPIO=y	51	CONFIG_DM_GPIO=y
52	CONFIG_DM_I2C=y	52	CONFIG_DM_I2C=y
53	CONFIG_DM_MMC=y	53	CONFIG_DM_MMC=y
54	CONFIG_PINCTRL=y	54	CONFIG_PINCTRL=y
55	CONFIG_PINCTRL_IMX6=y	55	CONFIG_PINCTRL_IMX6=y
56	CONFIG_DM_REGULATOR=y	56	CONFIG_DM_REGULATOR=y
57	CONFIG_DM_REGULATOR_FIXED=y	57	CONFIG_DM_REGULATOR_FIXED=y
58	CONFIG_DM_REGULATOR_GPIO=y	58	CONFIG_DM_REGULATOR_GPIO=y
59	CONFIG_DM_ETH=y	59	CONFIG_DM_ETH=y
60	CONFIG_DM_USB=y	60	CONFIG_DM_USB=y
61		61
62	CONFIG_CMD_FASTBOOT=y	62	CONFIG_CMD_FASTBOOT=y
63	CONFIG_USB_FUNCTION_FASTBOOT=y	63	CONFIG_USB_FUNCTION_FASTBOOT=y
64	CONFIG_FSL_FASTBOOT=y	64	CONFIG_FSL_FASTBOOT=y
65	CONFIG_FASTBOOT=y	65	CONFIG_FASTBOOT=y
66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000	66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000	67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000
68	CONFIG_FASTBOOT_FLASH=y	68	CONFIG_FASTBOOT_FLASH=y
69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2	69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2
70	CONFIG_EFI_PARTITION=y	70	CONFIG_EFI_PARTITION=y
71		71

configs/smarcfimx6_solo_ser0_defconfig

Diff comments View file @ 5769f67

1	CONFIG_ARM=y	1	CONFIG_ARM=y
2	CONFIG_ARCH_MX6=y	2	CONFIG_ARCH_MX6=y
3	CONFIG_TARGET_SMARCFIMX6=y	3	CONFIG_TARGET_SMARCFIMX6=y
4	CONFIG_VIDEO=y	4	CONFIG_VIDEO=y
5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6solo_2x_k4b2g1646q.cfg,MX6S"	5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6solo_2x_k4b2g1646q.cfg,MX6S"
6	CONFIG_CONSOLE_SER0=y	6	CONFIG_CONSOLE_SER0=y
7	CONFIG_SPI_BOOT=y	7	CONFIG_SPI_BOOT=y
8	CONFIG_BOOTDELAY=1	8	CONFIG_BOOTDELAY=1
9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y	9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y
10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y	10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
11	CONFIG_HUSH_PARSER=y	11	CONFIG_HUSH_PARSER=y
12	CONFIG_CMD_BOOTZ=y	12	CONFIG_CMD_BOOTZ=y
13	CONFIG_SYS_PROMPT="U-Boot# "	13	CONFIG_SYS_PROMPT="U-Boot# "
14	CONFIG_SYS_HUSH_PARSER=y	14	CONFIG_SYS_HUSH_PARSER=y
15	# CONFIG_CMD_IMLS is not set	15	# CONFIG_CMD_IMLS is not set
16	# CONFIG_CMD_FLASH is not set	16	# CONFIG_CMD_FLASH is not set
17	CONFIG_CMD_MEMTEST=y	17	CONFIG_CMD_MEMTEST=y
18	CONFIG_CMD_MMC=y	18	CONFIG_CMD_MMC=y
19	CONFIG_CMD_SF=y	19	CONFIG_CMD_SF=y
20	CONFIG_CMD_I2C=y	20	CONFIG_CMD_I2C=y
21	CONFIG_CMD_USB=y	21	CONFIG_CMD_USB=y
22	CONFIG_CMD_DFU=y	22	CONFIG_CMD_DFU=y
23	CONFIG_CMD_USB_MASS_STORAGE=y	23	CONFIG_CMD_USB_MASS_STORAGE=y
24	CONFIG_CMD_GPIO=y	24	CONFIG_CMD_GPIO=y
25	CONFIG_CMD_DHCP=y	25	CONFIG_CMD_DHCP=y
26	CONFIG_CMD_MII=y	26	CONFIG_CMD_MII=y
27	CONFIG_CMD_PING=y	27	CONFIG_CMD_PING=y
28	CONFIG_CMD_CACHE=y	28	CONFIG_CMD_CACHE=y
29	CONFIG_CMD_EXT2=y	29	CONFIG_CMD_EXT2=y
30	CONFIG_CMD_EXT4=y	30	CONFIG_CMD_EXT4=y
31	CONFIG_CMD_EXT4_WRITE=y	31	CONFIG_CMD_EXT4_WRITE=y
32	CONFIG_CMD_FAT=y	32	CONFIG_CMD_FAT=y
33	CONFIG_CMD_FS_GENERIC=y	33	CONFIG_CMD_FS_GENERIC=y
34	CONFIG_CMD_PART=y	34	CONFIG_CMD_PART=y
35	CONFIG_DFU_MMC=y	35	CONFIG_DFU_MMC=y
36	CONFIG_DFU_SF=y	36	CONFIG_DFU_SF=y
37	CONFIG_USB=y	37	CONFIG_USB=y
38	CONFIG_USB_STORAGE=y	38	CONFIG_USB_STORAGE=y
39	CONFIG_USB_GADGET=y	39	CONFIG_USB_GADGET=y
40	CONFIG_CI_UDC=y	40	CONFIG_CI_UDC=y
41	CONFIG_USB_GADGET_DOWNLOAD=y	41	CONFIG_USB_GADGET_DOWNLOAD=y
42	CONFIG_USB_GADGET_MANUFACTURER="FSL"	42	CONFIG_USB_GADGET_MANUFACTURER="FSL"
43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525	43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525
44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5	44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
45	# CONFIG_VIDEO_SW_CURSOR is not set	45	# CONFIG_VIDEO_SW_CURSOR is not set
46	CONFIG_OF_LIBFDT=y	46	CONFIG_OF_LIBFDT=y
47		47
48	CONFIG_DEFAULT_DEVICE_TREE="imx6q-smarcfimx6"	48	CONFIG_DEFAULT_DEVICE_TREE="imx6dl-smarcfimx6"
49	CONFIG_DEFAULT_FDT_FILE="imx6q-smarcfimx6.dtb"	49	CONFIG_DEFAULT_FDT_FILE="imx6dl-smarcfimx6.dtb"
50	CONFIG_OF_CONTROL=y	50	CONFIG_OF_CONTROL=y
51	CONFIG_DM_GPIO=y	51	CONFIG_DM_GPIO=y
52	CONFIG_DM_I2C=y	52	CONFIG_DM_I2C=y
53	CONFIG_DM_MMC=y	53	CONFIG_DM_MMC=y
54	CONFIG_PINCTRL=y	54	CONFIG_PINCTRL=y
55	CONFIG_PINCTRL_IMX6=y	55	CONFIG_PINCTRL_IMX6=y
56	CONFIG_DM_REGULATOR=y	56	CONFIG_DM_REGULATOR=y
57	CONFIG_DM_REGULATOR_FIXED=y	57	CONFIG_DM_REGULATOR_FIXED=y
58	CONFIG_DM_REGULATOR_GPIO=y	58	CONFIG_DM_REGULATOR_GPIO=y
59	CONFIG_DM_ETH=y	59	CONFIG_DM_ETH=y
60	CONFIG_DM_USB=y	60	CONFIG_DM_USB=y
61		61
62	CONFIG_CMD_FASTBOOT=y	62	CONFIG_CMD_FASTBOOT=y
63	CONFIG_USB_FUNCTION_FASTBOOT=y	63	CONFIG_USB_FUNCTION_FASTBOOT=y
64	CONFIG_FSL_FASTBOOT=y	64	CONFIG_FSL_FASTBOOT=y
65	CONFIG_FASTBOOT=y	65	CONFIG_FASTBOOT=y
66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000	66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000	67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000
68	CONFIG_FASTBOOT_FLASH=y	68	CONFIG_FASTBOOT_FLASH=y
69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2	69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2
70	CONFIG_EFI_PARTITION=y	70	CONFIG_EFI_PARTITION=y
71		71

configs/smarcfimx6_solo_ser1_android_defconfig

Diff comments View file @ 5769f67

1	CONFIG_ARM=y	1	CONFIG_ARM=y
2	CONFIG_ARCH_MX6=y	2	CONFIG_ARCH_MX6=y
3	CONFIG_TARGET_SMARCFIMX6=y	3	CONFIG_TARGET_SMARCFIMX6=y
4	CONFIG_VIDEO=y	4	CONFIG_VIDEO=y
5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6solo_2x_k4b2g1646q.cfg,MX6S,ANDROID_SUPPORT"	5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6solo_2x_k4b2g1646q.cfg,MX6S,ANDROID_SUPPORT"
6	CONFIG_CONSOLE_SER1=y	6	CONFIG_CONSOLE_SER1=y
7	CONFIG_SPI_BOOT=y	7	CONFIG_SPI_BOOT=y
8	CONFIG_BOOTDELAY=1	8	CONFIG_BOOTDELAY=1
9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y	9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y
10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y	10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
11	CONFIG_HUSH_PARSER=y	11	CONFIG_HUSH_PARSER=y
12	CONFIG_CMD_BOOTZ=y	12	CONFIG_CMD_BOOTZ=y
13	CONFIG_SYS_PROMPT="U-Boot# "	13	CONFIG_SYS_PROMPT="U-Boot# "
14	CONFIG_SYS_HUSH_PARSER=y	14	CONFIG_SYS_HUSH_PARSER=y
15	# CONFIG_CMD_IMLS is not set	15	# CONFIG_CMD_IMLS is not set
16	# CONFIG_CMD_FLASH is not set	16	# CONFIG_CMD_FLASH is not set
17	CONFIG_CMD_MEMTEST=y	17	CONFIG_CMD_MEMTEST=y
18	CONFIG_CMD_MMC=y	18	CONFIG_CMD_MMC=y
19	CONFIG_CMD_SF=y	19	CONFIG_CMD_SF=y
20	CONFIG_CMD_I2C=y	20	CONFIG_CMD_I2C=y
21	CONFIG_CMD_USB=y	21	CONFIG_CMD_USB=y
22	CONFIG_CMD_DFU=y	22	CONFIG_CMD_DFU=y
23	CONFIG_CMD_USB_MASS_STORAGE=y	23	CONFIG_CMD_USB_MASS_STORAGE=y
24	CONFIG_CMD_GPIO=y	24	CONFIG_CMD_GPIO=y
25	CONFIG_CMD_DHCP=y	25	CONFIG_CMD_DHCP=y
26	CONFIG_CMD_MII=y	26	CONFIG_CMD_MII=y
27	CONFIG_CMD_PING=y	27	CONFIG_CMD_PING=y
28	CONFIG_CMD_CACHE=y	28	CONFIG_CMD_CACHE=y
29	CONFIG_CMD_EXT2=y	29	CONFIG_CMD_EXT2=y
30	CONFIG_CMD_EXT4=y	30	CONFIG_CMD_EXT4=y
31	CONFIG_CMD_EXT4_WRITE=y	31	CONFIG_CMD_EXT4_WRITE=y
32	CONFIG_CMD_FAT=y	32	CONFIG_CMD_FAT=y
33	CONFIG_CMD_FS_GENERIC=y	33	CONFIG_CMD_FS_GENERIC=y
34	CONFIG_CMD_PART=y	34	CONFIG_CMD_PART=y
35	CONFIG_DFU_MMC=y	35	CONFIG_DFU_MMC=y
36	CONFIG_DFU_SF=y	36	CONFIG_DFU_SF=y
37	CONFIG_USB=y	37	CONFIG_USB=y
38	CONFIG_USB_STORAGE=y	38	CONFIG_USB_STORAGE=y
39	CONFIG_USB_GADGET=y	39	CONFIG_USB_GADGET=y
40	CONFIG_CI_UDC=y	40	CONFIG_CI_UDC=y
41	CONFIG_USB_GADGET_DOWNLOAD=y	41	CONFIG_USB_GADGET_DOWNLOAD=y
42	CONFIG_USB_GADGET_MANUFACTURER="FSL"	42	CONFIG_USB_GADGET_MANUFACTURER="FSL"
43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525	43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525
44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5	44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
45	# CONFIG_VIDEO_SW_CURSOR is not set	45	# CONFIG_VIDEO_SW_CURSOR is not set
46	CONFIG_OF_LIBFDT=y	46	CONFIG_OF_LIBFDT=y
47		47
48	CONFIG_DEFAULT_DEVICE_TREE="imx6q-smarcfimx6"	48	CONFIG_DEFAULT_DEVICE_TREE="imx6dl-smarcfimx6"
49	CONFIG_DEFAULT_FDT_FILE="imx6q-smarcfimx6.dtb"	49	CONFIG_DEFAULT_FDT_FILE="imx6dl-smarcfimx6.dtb"
50	CONFIG_OF_CONTROL=y	50	CONFIG_OF_CONTROL=y
51	CONFIG_DM_GPIO=y	51	CONFIG_DM_GPIO=y
52	CONFIG_DM_I2C=y	52	CONFIG_DM_I2C=y
53	CONFIG_DM_MMC=y	53	CONFIG_DM_MMC=y
54	CONFIG_PINCTRL=y	54	CONFIG_PINCTRL=y
55	CONFIG_PINCTRL_IMX6=y	55	CONFIG_PINCTRL_IMX6=y
56	CONFIG_DM_REGULATOR=y	56	CONFIG_DM_REGULATOR=y
57	CONFIG_DM_REGULATOR_FIXED=y	57	CONFIG_DM_REGULATOR_FIXED=y
58	CONFIG_DM_REGULATOR_GPIO=y	58	CONFIG_DM_REGULATOR_GPIO=y
59	CONFIG_DM_ETH=y	59	CONFIG_DM_ETH=y
60	CONFIG_DM_USB=y	60	CONFIG_DM_USB=y
61		61
62	CONFIG_CMD_FASTBOOT=y	62	CONFIG_CMD_FASTBOOT=y
63	CONFIG_USB_FUNCTION_FASTBOOT=y	63	CONFIG_USB_FUNCTION_FASTBOOT=y
64	CONFIG_FSL_FASTBOOT=y	64	CONFIG_FSL_FASTBOOT=y
65	CONFIG_FASTBOOT=y	65	CONFIG_FASTBOOT=y
66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000	66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000	67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000
68	CONFIG_FASTBOOT_FLASH=y	68	CONFIG_FASTBOOT_FLASH=y
69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2	69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2
70	CONFIG_EFI_PARTITION=y	70	CONFIG_EFI_PARTITION=y
71		71

configs/smarcfimx6_solo_ser1_defconfig

Diff comments View file @ 5769f67

1	CONFIG_ARM=y	1	CONFIG_ARM=y
2	CONFIG_ARCH_MX6=y	2	CONFIG_ARCH_MX6=y
3	CONFIG_TARGET_SMARCFIMX6=y	3	CONFIG_TARGET_SMARCFIMX6=y
4	CONFIG_VIDEO=y	4	CONFIG_VIDEO=y
5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6solo_2x_k4b2g1646q.cfg,MX6S"	5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6solo_2x_k4b2g1646q.cfg,MX6S"
6	CONFIG_CONSOLE_SER1=y	6	CONFIG_CONSOLE_SER1=y
7	CONFIG_SPI_BOOT=y	7	CONFIG_SPI_BOOT=y
8	CONFIG_BOOTDELAY=1	8	CONFIG_BOOTDELAY=1
9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y	9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y
10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y	10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
11	CONFIG_HUSH_PARSER=y	11	CONFIG_HUSH_PARSER=y
12	CONFIG_CMD_BOOTZ=y	12	CONFIG_CMD_BOOTZ=y
13	CONFIG_SYS_PROMPT="U-Boot# "	13	CONFIG_SYS_PROMPT="U-Boot# "
14	CONFIG_SYS_HUSH_PARSER=y	14	CONFIG_SYS_HUSH_PARSER=y
15	# CONFIG_CMD_IMLS is not set	15	# CONFIG_CMD_IMLS is not set
16	# CONFIG_CMD_FLASH is not set	16	# CONFIG_CMD_FLASH is not set
17	CONFIG_CMD_MEMTEST=y	17	CONFIG_CMD_MEMTEST=y
18	CONFIG_CMD_MMC=y	18	CONFIG_CMD_MMC=y
19	CONFIG_CMD_SF=y	19	CONFIG_CMD_SF=y
20	CONFIG_CMD_I2C=y	20	CONFIG_CMD_I2C=y
21	CONFIG_CMD_USB=y	21	CONFIG_CMD_USB=y
22	CONFIG_CMD_DFU=y	22	CONFIG_CMD_DFU=y
23	CONFIG_CMD_USB_MASS_STORAGE=y	23	CONFIG_CMD_USB_MASS_STORAGE=y
24	CONFIG_CMD_GPIO=y	24	CONFIG_CMD_GPIO=y
25	CONFIG_CMD_DHCP=y	25	CONFIG_CMD_DHCP=y
26	CONFIG_CMD_MII=y	26	CONFIG_CMD_MII=y
27	CONFIG_CMD_PING=y	27	CONFIG_CMD_PING=y
28	CONFIG_CMD_CACHE=y	28	CONFIG_CMD_CACHE=y
29	CONFIG_CMD_EXT2=y	29	CONFIG_CMD_EXT2=y
30	CONFIG_CMD_EXT4=y	30	CONFIG_CMD_EXT4=y
31	CONFIG_CMD_EXT4_WRITE=y	31	CONFIG_CMD_EXT4_WRITE=y
32	CONFIG_CMD_FAT=y	32	CONFIG_CMD_FAT=y
33	CONFIG_CMD_FS_GENERIC=y	33	CONFIG_CMD_FS_GENERIC=y
34	CONFIG_CMD_PART=y	34	CONFIG_CMD_PART=y
35	CONFIG_DFU_MMC=y	35	CONFIG_DFU_MMC=y
36	CONFIG_DFU_SF=y	36	CONFIG_DFU_SF=y
37	CONFIG_USB=y	37	CONFIG_USB=y
38	CONFIG_USB_STORAGE=y	38	CONFIG_USB_STORAGE=y
39	CONFIG_USB_GADGET=y	39	CONFIG_USB_GADGET=y
40	CONFIG_CI_UDC=y	40	CONFIG_CI_UDC=y
41	CONFIG_USB_GADGET_DOWNLOAD=y	41	CONFIG_USB_GADGET_DOWNLOAD=y
42	CONFIG_USB_GADGET_MANUFACTURER="FSL"	42	CONFIG_USB_GADGET_MANUFACTURER="FSL"
43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525	43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525
44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5	44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
45	# CONFIG_VIDEO_SW_CURSOR is not set	45	# CONFIG_VIDEO_SW_CURSOR is not set
46	CONFIG_OF_LIBFDT=y	46	CONFIG_OF_LIBFDT=y
47		47
48	CONFIG_DEFAULT_DEVICE_TREE="imx6q-smarcfimx6"	48	CONFIG_DEFAULT_DEVICE_TREE="imx6dl-smarcfimx6"
49	CONFIG_DEFAULT_FDT_FILE="imx6q-smarcfimx6.dtb"	49	CONFIG_DEFAULT_FDT_FILE="imx6dl-smarcfimx6.dtb"
50	CONFIG_OF_CONTROL=y	50	CONFIG_OF_CONTROL=y
51	CONFIG_DM_GPIO=y	51	CONFIG_DM_GPIO=y
52	CONFIG_DM_I2C=y	52	CONFIG_DM_I2C=y
53	CONFIG_DM_MMC=y	53	CONFIG_DM_MMC=y
54	CONFIG_PINCTRL=y	54	CONFIG_PINCTRL=y
55	CONFIG_PINCTRL_IMX6=y	55	CONFIG_PINCTRL_IMX6=y
56	CONFIG_DM_REGULATOR=y	56	CONFIG_DM_REGULATOR=y
57	CONFIG_DM_REGULATOR_FIXED=y	57	CONFIG_DM_REGULATOR_FIXED=y
58	CONFIG_DM_REGULATOR_GPIO=y	58	CONFIG_DM_REGULATOR_GPIO=y
59	CONFIG_DM_ETH=y	59	CONFIG_DM_ETH=y
60	CONFIG_DM_USB=y	60	CONFIG_DM_USB=y
61		61
62	CONFIG_CMD_FASTBOOT=y	62	CONFIG_CMD_FASTBOOT=y
63	CONFIG_USB_FUNCTION_FASTBOOT=y	63	CONFIG_USB_FUNCTION_FASTBOOT=y
64	CONFIG_FSL_FASTBOOT=y	64	CONFIG_FSL_FASTBOOT=y
65	CONFIG_FASTBOOT=y	65	CONFIG_FASTBOOT=y
66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000	66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000	67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000
68	CONFIG_FASTBOOT_FLASH=y	68	CONFIG_FASTBOOT_FLASH=y
69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2	69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2
70	CONFIG_EFI_PARTITION=y	70	CONFIG_EFI_PARTITION=y
71		71

configs/smarcfimx6_solo_ser2_android_defconfig

Diff comments View file @ 5769f67

1	CONFIG_ARM=y	1	CONFIG_ARM=y
2	CONFIG_ARCH_MX6=y	2	CONFIG_ARCH_MX6=y
3	CONFIG_TARGET_SMARCFIMX6=y	3	CONFIG_TARGET_SMARCFIMX6=y
4	CONFIG_VIDEO=y	4	CONFIG_VIDEO=y
5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6solo_2x_k4b2g1646q.cfg,MX6S,ANDROID_SUPPORT"	5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6solo_2x_k4b2g1646q.cfg,MX6S,ANDROID_SUPPORT"
6	CONFIG_CONSOLE_SER2=y	6	CONFIG_CONSOLE_SER2=y
7	CONFIG_SPI_BOOT=y	7	CONFIG_SPI_BOOT=y
8	CONFIG_BOOTDELAY=1	8	CONFIG_BOOTDELAY=1
9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y	9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y
10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y	10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
11	CONFIG_HUSH_PARSER=y	11	CONFIG_HUSH_PARSER=y
12	CONFIG_CMD_BOOTZ=y	12	CONFIG_CMD_BOOTZ=y
13	CONFIG_SYS_PROMPT="U-Boot# "	13	CONFIG_SYS_PROMPT="U-Boot# "
14	CONFIG_SYS_HUSH_PARSER=y	14	CONFIG_SYS_HUSH_PARSER=y
15	# CONFIG_CMD_IMLS is not set	15	# CONFIG_CMD_IMLS is not set
16	# CONFIG_CMD_FLASH is not set	16	# CONFIG_CMD_FLASH is not set
17	CONFIG_CMD_MEMTEST=y	17	CONFIG_CMD_MEMTEST=y
18	CONFIG_CMD_MMC=y	18	CONFIG_CMD_MMC=y
19	CONFIG_CMD_SF=y	19	CONFIG_CMD_SF=y
20	CONFIG_CMD_I2C=y	20	CONFIG_CMD_I2C=y
21	CONFIG_CMD_USB=y	21	CONFIG_CMD_USB=y
22	CONFIG_CMD_DFU=y	22	CONFIG_CMD_DFU=y
23	CONFIG_CMD_USB_MASS_STORAGE=y	23	CONFIG_CMD_USB_MASS_STORAGE=y
24	CONFIG_CMD_GPIO=y	24	CONFIG_CMD_GPIO=y
25	CONFIG_CMD_DHCP=y	25	CONFIG_CMD_DHCP=y
26	CONFIG_CMD_MII=y	26	CONFIG_CMD_MII=y
27	CONFIG_CMD_PING=y	27	CONFIG_CMD_PING=y
28	CONFIG_CMD_CACHE=y	28	CONFIG_CMD_CACHE=y
29	CONFIG_CMD_EXT2=y	29	CONFIG_CMD_EXT2=y
30	CONFIG_CMD_EXT4=y	30	CONFIG_CMD_EXT4=y
31	CONFIG_CMD_EXT4_WRITE=y	31	CONFIG_CMD_EXT4_WRITE=y
32	CONFIG_CMD_FAT=y	32	CONFIG_CMD_FAT=y
33	CONFIG_CMD_FS_GENERIC=y	33	CONFIG_CMD_FS_GENERIC=y
34	CONFIG_CMD_PART=y	34	CONFIG_CMD_PART=y
35	CONFIG_DFU_MMC=y	35	CONFIG_DFU_MMC=y
36	CONFIG_DFU_SF=y	36	CONFIG_DFU_SF=y
37	CONFIG_USB=y	37	CONFIG_USB=y
38	CONFIG_USB_STORAGE=y	38	CONFIG_USB_STORAGE=y
39	CONFIG_USB_GADGET=y	39	CONFIG_USB_GADGET=y
40	CONFIG_CI_UDC=y	40	CONFIG_CI_UDC=y
41	CONFIG_USB_GADGET_DOWNLOAD=y	41	CONFIG_USB_GADGET_DOWNLOAD=y
42	CONFIG_USB_GADGET_MANUFACTURER="FSL"	42	CONFIG_USB_GADGET_MANUFACTURER="FSL"
43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525	43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525
44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5	44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
45	# CONFIG_VIDEO_SW_CURSOR is not set	45	# CONFIG_VIDEO_SW_CURSOR is not set
46	CONFIG_OF_LIBFDT=y	46	CONFIG_OF_LIBFDT=y
47		47
48	CONFIG_DEFAULT_DEVICE_TREE="imx6q-smarcfimx6"	48	CONFIG_DEFAULT_DEVICE_TREE="imx6dl-smarcfimx6"
49	CONFIG_DEFAULT_FDT_FILE="imx6q-smarcfimx6.dtb"	49	CONFIG_DEFAULT_FDT_FILE="imx6dl-smarcfimx6.dtb"
50	CONFIG_OF_CONTROL=y	50	CONFIG_OF_CONTROL=y
51	CONFIG_DM_GPIO=y	51	CONFIG_DM_GPIO=y
52	CONFIG_DM_I2C=y	52	CONFIG_DM_I2C=y
53	CONFIG_DM_MMC=y	53	CONFIG_DM_MMC=y
54	CONFIG_PINCTRL=y	54	CONFIG_PINCTRL=y
55	CONFIG_PINCTRL_IMX6=y	55	CONFIG_PINCTRL_IMX6=y
56	CONFIG_DM_REGULATOR=y	56	CONFIG_DM_REGULATOR=y
57	CONFIG_DM_REGULATOR_FIXED=y	57	CONFIG_DM_REGULATOR_FIXED=y
58	CONFIG_DM_REGULATOR_GPIO=y	58	CONFIG_DM_REGULATOR_GPIO=y
59	CONFIG_DM_ETH=y	59	CONFIG_DM_ETH=y
60	CONFIG_DM_USB=y	60	CONFIG_DM_USB=y
61		61
62	CONFIG_CMD_FASTBOOT=y	62	CONFIG_CMD_FASTBOOT=y
63	CONFIG_USB_FUNCTION_FASTBOOT=y	63	CONFIG_USB_FUNCTION_FASTBOOT=y
64	CONFIG_FSL_FASTBOOT=y	64	CONFIG_FSL_FASTBOOT=y
65	CONFIG_FASTBOOT=y	65	CONFIG_FASTBOOT=y
66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000	66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000	67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000
68	CONFIG_FASTBOOT_FLASH=y	68	CONFIG_FASTBOOT_FLASH=y
69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2	69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2
70	CONFIG_EFI_PARTITION=y	70	CONFIG_EFI_PARTITION=y
71		71

configs/smarcfimx6_solo_ser2_defconfig

Diff comments View file @ 5769f67

1	CONFIG_ARM=y	1	CONFIG_ARM=y
2	CONFIG_ARCH_MX6=y	2	CONFIG_ARCH_MX6=y
3	CONFIG_TARGET_SMARCFIMX6=y	3	CONFIG_TARGET_SMARCFIMX6=y
4	CONFIG_VIDEO=y	4	CONFIG_VIDEO=y
5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6solo_2x_k4b2g1646q.cfg,MX6S"	5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6solo_2x_k4b2g1646q.cfg,MX6S"
6	CONFIG_CONSOLE_SER2=y	6	CONFIG_CONSOLE_SER2=y
7	CONFIG_SPI_BOOT=y	7	CONFIG_SPI_BOOT=y
8	CONFIG_BOOTDELAY=1	8	CONFIG_BOOTDELAY=1
9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y	9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y
10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y	10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
11	CONFIG_HUSH_PARSER=y	11	CONFIG_HUSH_PARSER=y
12	CONFIG_CMD_BOOTZ=y	12	CONFIG_CMD_BOOTZ=y
13	CONFIG_SYS_PROMPT="U-Boot# "	13	CONFIG_SYS_PROMPT="U-Boot# "
14	CONFIG_SYS_HUSH_PARSER=y	14	CONFIG_SYS_HUSH_PARSER=y
15	# CONFIG_CMD_IMLS is not set	15	# CONFIG_CMD_IMLS is not set
16	# CONFIG_CMD_FLASH is not set	16	# CONFIG_CMD_FLASH is not set
17	CONFIG_CMD_MEMTEST=y	17	CONFIG_CMD_MEMTEST=y
18	CONFIG_CMD_MMC=y	18	CONFIG_CMD_MMC=y
19	CONFIG_CMD_SF=y	19	CONFIG_CMD_SF=y
20	CONFIG_CMD_I2C=y	20	CONFIG_CMD_I2C=y
21	CONFIG_CMD_USB=y	21	CONFIG_CMD_USB=y
22	CONFIG_CMD_DFU=y	22	CONFIG_CMD_DFU=y
23	CONFIG_CMD_USB_MASS_STORAGE=y	23	CONFIG_CMD_USB_MASS_STORAGE=y
24	CONFIG_CMD_GPIO=y	24	CONFIG_CMD_GPIO=y
25	CONFIG_CMD_DHCP=y	25	CONFIG_CMD_DHCP=y
26	CONFIG_CMD_MII=y	26	CONFIG_CMD_MII=y
27	CONFIG_CMD_PING=y	27	CONFIG_CMD_PING=y
28	CONFIG_CMD_CACHE=y	28	CONFIG_CMD_CACHE=y
29	CONFIG_CMD_EXT2=y	29	CONFIG_CMD_EXT2=y
30	CONFIG_CMD_EXT4=y	30	CONFIG_CMD_EXT4=y
31	CONFIG_CMD_EXT4_WRITE=y	31	CONFIG_CMD_EXT4_WRITE=y
32	CONFIG_CMD_FAT=y	32	CONFIG_CMD_FAT=y
33	CONFIG_CMD_FS_GENERIC=y	33	CONFIG_CMD_FS_GENERIC=y
34	CONFIG_CMD_PART=y	34	CONFIG_CMD_PART=y
35	CONFIG_DFU_MMC=y	35	CONFIG_DFU_MMC=y
36	CONFIG_DFU_SF=y	36	CONFIG_DFU_SF=y
37	CONFIG_USB=y	37	CONFIG_USB=y
38	CONFIG_USB_STORAGE=y	38	CONFIG_USB_STORAGE=y
39	CONFIG_USB_GADGET=y	39	CONFIG_USB_GADGET=y
40	CONFIG_CI_UDC=y	40	CONFIG_CI_UDC=y
41	CONFIG_USB_GADGET_DOWNLOAD=y	41	CONFIG_USB_GADGET_DOWNLOAD=y
42	CONFIG_USB_GADGET_MANUFACTURER="FSL"	42	CONFIG_USB_GADGET_MANUFACTURER="FSL"
43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525	43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525
44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5	44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
45	# CONFIG_VIDEO_SW_CURSOR is not set	45	# CONFIG_VIDEO_SW_CURSOR is not set
46	CONFIG_OF_LIBFDT=y	46	CONFIG_OF_LIBFDT=y
47		47
48	CONFIG_DEFAULT_DEVICE_TREE="imx6q-smarcfimx6"	48	CONFIG_DEFAULT_DEVICE_TREE="imx6dl-smarcfimx6"
49	CONFIG_DEFAULT_FDT_FILE="imx6q-smarcfimx6.dtb"	49	CONFIG_DEFAULT_FDT_FILE="imx6dl-smarcfimx6.dtb"
50	CONFIG_OF_CONTROL=y	50	CONFIG_OF_CONTROL=y
51	CONFIG_DM_GPIO=y	51	CONFIG_DM_GPIO=y
52	CONFIG_DM_I2C=y	52	CONFIG_DM_I2C=y
53	CONFIG_DM_MMC=y	53	CONFIG_DM_MMC=y
54	CONFIG_PINCTRL=y	54	CONFIG_PINCTRL=y
55	CONFIG_PINCTRL_IMX6=y	55	CONFIG_PINCTRL_IMX6=y
56	CONFIG_DM_REGULATOR=y	56	CONFIG_DM_REGULATOR=y
57	CONFIG_DM_REGULATOR_FIXED=y	57	CONFIG_DM_REGULATOR_FIXED=y
58	CONFIG_DM_REGULATOR_GPIO=y	58	CONFIG_DM_REGULATOR_GPIO=y
59	CONFIG_DM_ETH=y	59	CONFIG_DM_ETH=y
60	CONFIG_DM_USB=y	60	CONFIG_DM_USB=y
61		61
62	CONFIG_CMD_FASTBOOT=y	62	CONFIG_CMD_FASTBOOT=y
63	CONFIG_USB_FUNCTION_FASTBOOT=y	63	CONFIG_USB_FUNCTION_FASTBOOT=y
64	CONFIG_FSL_FASTBOOT=y	64	CONFIG_FSL_FASTBOOT=y
65	CONFIG_FASTBOOT=y	65	CONFIG_FASTBOOT=y
66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000	66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000	67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000
68	CONFIG_FASTBOOT_FLASH=y	68	CONFIG_FASTBOOT_FLASH=y
69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2	69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2
70	CONFIG_EFI_PARTITION=y	70	CONFIG_EFI_PARTITION=y
71		71

configs/smarcfimx6_solo_ser3_android_defconfig

Diff comments View file @ 5769f67

1	CONFIG_ARM=y	1	CONFIG_ARM=y
2	CONFIG_ARCH_MX6=y	2	CONFIG_ARCH_MX6=y
3	CONFIG_TARGET_SMARCFIMX6=y	3	CONFIG_TARGET_SMARCFIMX6=y
4	CONFIG_VIDEO=y	4	CONFIG_VIDEO=y
5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6solo_2x_k4b2g1646q.cfg,MX6S,ANDROID_SUPPORT"	5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6solo_2x_k4b2g1646q.cfg,MX6S,ANDROID_SUPPORT"
6	CONFIG_CONSOLE_SER3=y	6	CONFIG_CONSOLE_SER3=y
7	CONFIG_SPI_BOOT=y	7	CONFIG_SPI_BOOT=y
8	CONFIG_BOOTDELAY=1	8	CONFIG_BOOTDELAY=1
9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y	9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y
10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y	10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
11	CONFIG_HUSH_PARSER=y	11	CONFIG_HUSH_PARSER=y
12	CONFIG_CMD_BOOTZ=y	12	CONFIG_CMD_BOOTZ=y
13	CONFIG_SYS_PROMPT="U-Boot# "	13	CONFIG_SYS_PROMPT="U-Boot# "
14	CONFIG_SYS_HUSH_PARSER=y	14	CONFIG_SYS_HUSH_PARSER=y
15	# CONFIG_CMD_IMLS is not set	15	# CONFIG_CMD_IMLS is not set
16	# CONFIG_CMD_FLASH is not set	16	# CONFIG_CMD_FLASH is not set
17	CONFIG_CMD_MEMTEST=y	17	CONFIG_CMD_MEMTEST=y
18	CONFIG_CMD_MMC=y	18	CONFIG_CMD_MMC=y
19	CONFIG_CMD_SF=y	19	CONFIG_CMD_SF=y
20	CONFIG_CMD_I2C=y	20	CONFIG_CMD_I2C=y
21	CONFIG_CMD_USB=y	21	CONFIG_CMD_USB=y
22	CONFIG_CMD_DFU=y	22	CONFIG_CMD_DFU=y
23	CONFIG_CMD_USB_MASS_STORAGE=y	23	CONFIG_CMD_USB_MASS_STORAGE=y
24	CONFIG_CMD_GPIO=y	24	CONFIG_CMD_GPIO=y
25	CONFIG_CMD_DHCP=y	25	CONFIG_CMD_DHCP=y
26	CONFIG_CMD_MII=y	26	CONFIG_CMD_MII=y
27	CONFIG_CMD_PING=y	27	CONFIG_CMD_PING=y
28	CONFIG_CMD_CACHE=y	28	CONFIG_CMD_CACHE=y
29	CONFIG_CMD_EXT2=y	29	CONFIG_CMD_EXT2=y
30	CONFIG_CMD_EXT4=y	30	CONFIG_CMD_EXT4=y
31	CONFIG_CMD_EXT4_WRITE=y	31	CONFIG_CMD_EXT4_WRITE=y
32	CONFIG_CMD_FAT=y	32	CONFIG_CMD_FAT=y
33	CONFIG_CMD_FS_GENERIC=y	33	CONFIG_CMD_FS_GENERIC=y
34	CONFIG_CMD_PART=y	34	CONFIG_CMD_PART=y
35	CONFIG_DFU_MMC=y	35	CONFIG_DFU_MMC=y
36	CONFIG_DFU_SF=y	36	CONFIG_DFU_SF=y
37	CONFIG_USB=y	37	CONFIG_USB=y
38	CONFIG_USB_STORAGE=y	38	CONFIG_USB_STORAGE=y
39	CONFIG_USB_GADGET=y	39	CONFIG_USB_GADGET=y
40	CONFIG_CI_UDC=y	40	CONFIG_CI_UDC=y
41	CONFIG_USB_GADGET_DOWNLOAD=y	41	CONFIG_USB_GADGET_DOWNLOAD=y
42	CONFIG_USB_GADGET_MANUFACTURER="FSL"	42	CONFIG_USB_GADGET_MANUFACTURER="FSL"
43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525	43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525
44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5	44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
45	# CONFIG_VIDEO_SW_CURSOR is not set	45	# CONFIG_VIDEO_SW_CURSOR is not set
46	CONFIG_OF_LIBFDT=y	46	CONFIG_OF_LIBFDT=y
47		47
48	CONFIG_DEFAULT_DEVICE_TREE="imx6q-smarcfimx6"	48	CONFIG_DEFAULT_DEVICE_TREE="imx6dl-smarcfimx6"
49	CONFIG_DEFAULT_FDT_FILE="imx6q-smarcfimx6.dtb"	49	CONFIG_DEFAULT_FDT_FILE="imx6dl-smarcfimx6.dtb"
50	CONFIG_OF_CONTROL=y	50	CONFIG_OF_CONTROL=y
51	CONFIG_DM_GPIO=y	51	CONFIG_DM_GPIO=y
52	CONFIG_DM_I2C=y	52	CONFIG_DM_I2C=y
53	CONFIG_DM_MMC=y	53	CONFIG_DM_MMC=y
54	CONFIG_PINCTRL=y	54	CONFIG_PINCTRL=y
55	CONFIG_PINCTRL_IMX6=y	55	CONFIG_PINCTRL_IMX6=y
56	CONFIG_DM_REGULATOR=y	56	CONFIG_DM_REGULATOR=y
57	CONFIG_DM_REGULATOR_FIXED=y	57	CONFIG_DM_REGULATOR_FIXED=y
58	CONFIG_DM_REGULATOR_GPIO=y	58	CONFIG_DM_REGULATOR_GPIO=y
59	CONFIG_DM_ETH=y	59	CONFIG_DM_ETH=y
60	CONFIG_DM_USB=y	60	CONFIG_DM_USB=y
61		61
62	CONFIG_CMD_FASTBOOT=y	62	CONFIG_CMD_FASTBOOT=y
63	CONFIG_USB_FUNCTION_FASTBOOT=y	63	CONFIG_USB_FUNCTION_FASTBOOT=y
64	CONFIG_FSL_FASTBOOT=y	64	CONFIG_FSL_FASTBOOT=y
65	CONFIG_FASTBOOT=y	65	CONFIG_FASTBOOT=y
66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000	66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000	67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000
68	CONFIG_FASTBOOT_FLASH=y	68	CONFIG_FASTBOOT_FLASH=y
69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2	69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2
70	CONFIG_EFI_PARTITION=y	70	CONFIG_EFI_PARTITION=y
71		71

configs/smarcfimx6_solo_ser3_defconfig

Diff comments View file @ 5769f67

1	CONFIG_ARM=y	1	CONFIG_ARM=y
2	CONFIG_ARCH_MX6=y	2	CONFIG_ARCH_MX6=y
3	CONFIG_TARGET_SMARCFIMX6=y	3	CONFIG_TARGET_SMARCFIMX6=y
4	CONFIG_VIDEO=y	4	CONFIG_VIDEO=y
5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6solo_2x_k4b2g1646q.cfg,MX6S"	5	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/embedian/smarcfimx6/ddr3/mx6solo_2x_k4b2g1646q.cfg,MX6S"
6	CONFIG_CONSOLE_SER3=y	6	CONFIG_CONSOLE_SER3=y
7	CONFIG_SPI_BOOT=y	7	CONFIG_SPI_BOOT=y
8	CONFIG_BOOTDELAY=1	8	CONFIG_BOOTDELAY=1
9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y	9	CONFIG_SYS_CONSOLE_IS_IN_ENV=y
10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y	10	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
11	CONFIG_HUSH_PARSER=y	11	CONFIG_HUSH_PARSER=y
12	CONFIG_CMD_BOOTZ=y	12	CONFIG_CMD_BOOTZ=y
13	CONFIG_SYS_PROMPT="U-Boot# "	13	CONFIG_SYS_PROMPT="U-Boot# "
14	CONFIG_SYS_HUSH_PARSER=y	14	CONFIG_SYS_HUSH_PARSER=y
15	# CONFIG_CMD_IMLS is not set	15	# CONFIG_CMD_IMLS is not set
16	# CONFIG_CMD_FLASH is not set	16	# CONFIG_CMD_FLASH is not set
17	CONFIG_CMD_MEMTEST=y	17	CONFIG_CMD_MEMTEST=y
18	CONFIG_CMD_MMC=y	18	CONFIG_CMD_MMC=y
19	CONFIG_CMD_SF=y	19	CONFIG_CMD_SF=y
20	CONFIG_CMD_I2C=y	20	CONFIG_CMD_I2C=y
21	CONFIG_CMD_USB=y	21	CONFIG_CMD_USB=y
22	CONFIG_CMD_DFU=y	22	CONFIG_CMD_DFU=y
23	CONFIG_CMD_USB_MASS_STORAGE=y	23	CONFIG_CMD_USB_MASS_STORAGE=y
24	CONFIG_CMD_GPIO=y	24	CONFIG_CMD_GPIO=y
25	CONFIG_CMD_DHCP=y	25	CONFIG_CMD_DHCP=y
26	CONFIG_CMD_MII=y	26	CONFIG_CMD_MII=y
27	CONFIG_CMD_PING=y	27	CONFIG_CMD_PING=y
28	CONFIG_CMD_CACHE=y	28	CONFIG_CMD_CACHE=y
29	CONFIG_CMD_EXT2=y	29	CONFIG_CMD_EXT2=y
30	CONFIG_CMD_EXT4=y	30	CONFIG_CMD_EXT4=y
31	CONFIG_CMD_EXT4_WRITE=y	31	CONFIG_CMD_EXT4_WRITE=y
32	CONFIG_CMD_FAT=y	32	CONFIG_CMD_FAT=y
33	CONFIG_CMD_FS_GENERIC=y	33	CONFIG_CMD_FS_GENERIC=y
34	CONFIG_CMD_PART=y	34	CONFIG_CMD_PART=y
35	CONFIG_DFU_MMC=y	35	CONFIG_DFU_MMC=y
36	CONFIG_DFU_SF=y	36	CONFIG_DFU_SF=y
37	CONFIG_USB=y	37	CONFIG_USB=y
38	CONFIG_USB_STORAGE=y	38	CONFIG_USB_STORAGE=y
39	CONFIG_USB_GADGET=y	39	CONFIG_USB_GADGET=y
40	CONFIG_CI_UDC=y	40	CONFIG_CI_UDC=y
41	CONFIG_USB_GADGET_DOWNLOAD=y	41	CONFIG_USB_GADGET_DOWNLOAD=y
42	CONFIG_USB_GADGET_MANUFACTURER="FSL"	42	CONFIG_USB_GADGET_MANUFACTURER="FSL"
43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525	43	CONFIG_USB_GADGET_VENDOR_NUM=0x0525
44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5	44	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
45	# CONFIG_VIDEO_SW_CURSOR is not set	45	# CONFIG_VIDEO_SW_CURSOR is not set
46	CONFIG_OF_LIBFDT=y	46	CONFIG_OF_LIBFDT=y
47		47
48	CONFIG_DEFAULT_DEVICE_TREE="imx6q-smarcfimx6"	48	CONFIG_DEFAULT_DEVICE_TREE="imx6dl-smarcfimx6"
49	CONFIG_DEFAULT_FDT_FILE="imx6q-smarcfimx6.dtb"	49	CONFIG_DEFAULT_FDT_FILE="imx6dl-smarcfimx6.dtb"
50	CONFIG_OF_CONTROL=y	50	CONFIG_OF_CONTROL=y
51	CONFIG_DM_GPIO=y	51	CONFIG_DM_GPIO=y
52	CONFIG_DM_I2C=y	52	CONFIG_DM_I2C=y
53	CONFIG_DM_MMC=y	53	CONFIG_DM_MMC=y
54	CONFIG_PINCTRL=y	54	CONFIG_PINCTRL=y
55	CONFIG_PINCTRL_IMX6=y	55	CONFIG_PINCTRL_IMX6=y
56	CONFIG_DM_REGULATOR=y	56	CONFIG_DM_REGULATOR=y
57	CONFIG_DM_REGULATOR_FIXED=y	57	CONFIG_DM_REGULATOR_FIXED=y
58	CONFIG_DM_REGULATOR_GPIO=y	58	CONFIG_DM_REGULATOR_GPIO=y
59	CONFIG_DM_ETH=y	59	CONFIG_DM_ETH=y
60	CONFIG_DM_USB=y	60	CONFIG_DM_USB=y
61		61
62	CONFIG_CMD_FASTBOOT=y	62	CONFIG_CMD_FASTBOOT=y
63	CONFIG_USB_FUNCTION_FASTBOOT=y	63	CONFIG_USB_FUNCTION_FASTBOOT=y
64	CONFIG_FSL_FASTBOOT=y	64	CONFIG_FSL_FASTBOOT=y
65	CONFIG_FASTBOOT=y	65	CONFIG_FASTBOOT=y
66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000	66	CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000	67	CONFIG_FASTBOOT_BUF_SIZE=0x40000000
68	CONFIG_FASTBOOT_FLASH=y	68	CONFIG_FASTBOOT_FLASH=y
69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2	69	CONFIG_FASTBOOT_FLASH_MMC_DEV=2
70	CONFIG_EFI_PARTITION=y	70	CONFIG_EFI_PARTITION=y
71		71

include/configs/smarcfimx6_common.h

Diff comments View file @ 5769f67

 /*
  * Copyright (C) 2012 Freescale Semiconductor, Inc.
  * Copyright 2018 NXP
  *
  * Configuration settings for the Freescale i.MX6Q SabreSD board.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __SMARCFIMX6_COMMON_CONFIG_H
 #define __SMARCFIMX6_COMMON_CONFIG_H
 #include "mx6_common.h"
 #include "imx_env.h"
 #define CONFIG_IMX_THERMAL
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
 #define CONFIG_MXC_UART
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
 #define CONFIG_FEC_XCV_TYPE		RGMII
 #ifdef CONFIG_DM_ETH
 #define CONFIG_ETHPRIME			"eth0"
 #else
 #define CONFIG_ETHPRIME			"FEC"
 #endif
 #define CONFIG_FEC_MXC_PHYADDR		6
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 #ifdef CONFIG_MX6S
 #define SYS_NOSMP "nosmp"
 #else
 #define SYS_NOSMP
 #endif
 #ifdef CONFIG_NAND_BOOT
 #define MFG_NAND_PARTITION "mtdparts=8000000.nor:1m(boot),-(rootfs)\\;gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs) "
 #else
 #define MFG_NAND_PARTITION ""
 #endif
 #define CONFIG_CMD_READ
 #define CONFIG_SERIAL_TAG
 #define CONFIG_FASTBOOT_USB_DEV 0
 #define CONFIG_MFG_ENV_SETTINGS \
 	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
 	"initrd_addr=0x12C00000\0" \
 	"initrd_high=0xffffffff\0" \
 	"emmc_dev=2\0"\
 	"sd_dev=1\0" \
 	"weim_uboot=0x08001000\0"\
 	"weim_base=0x08000000\0"\
 	"spi_bus=1\0"\
 	"spi_uboot=0x400\0" \
 	"mtdparts=" MFG_NAND_PARTITION \
 	"\0"\
 #ifdef CONFIG_SUPPORT_EMMC_BOOT
 #define EMMC_ENV \
 	"emmcdev=2\0" \
 	"update_emmc_firmware=" \
 		"if test ${ip_dyn} = yes; then " \
 			"setenv get_cmd dhcp; " \
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
 		"if ${get_cmd} ${update_sd_firmware_filename}; then " \
 			"if mmc dev ${emmcdev} 1; then "	\
 				"setexpr fw_sz ${filesize} / 0x200; " \
 				"setexpr fw_sz ${fw_sz} + 1; "	\
 				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
 			"fi; "	\
 		"fi\0"
 #else
 #define EMMC_ENV ""
 #endif
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 #if defined(CONFIG_NAND_BOOT)
 	/*
 	 * The dts also enables the WEIN NOR which is mtd0.
 	 * So the partions' layout for NAND is:
 	 *     mtd1: 16M      (uboot)
 	 *     mtd2: 16M      (kernel)
 	 *     mtd3: 16M      (dtb)
 	 *     mtd4: left     (rootfs)
 	 */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	CONFIG_MFG_ENV_SETTINGS \
 	TEE_ENV \
 	"fdt_addr=0x18000000\0" \
 	"fdt_high=0xffffffff\0"	  \
 	"console=" CONSOLE_DEV "\0" \
 	"bootargs=console=" CONSOLE_DEV ",115200 ubi.mtd=6 "  \
 		"root=ubi0:nandrootfs rootfstype=ubifs "		     \
 		MFG_NAND_PARTITION \
 		"\0" \
 	"bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
 		"nand read ${fdt_addr} 0x5000000 0x100000;"\
 		"if test ${tee} = yes; then " \
 			"nand read ${tee_addr} 0x4000000 0x400000;"\
 			"bootm ${teeaddr} - ${fdt_addr};" \
 		"else " \
 			"bootz ${loadaddr} - ${fdt_addr};" \
 		"fi\0"
 #elif defined(CONFIG_SATA_BOOT)
 #define CONFIG_EXTRA_ENV_SETTINGS \
 		CONFIG_MFG_ENV_SETTINGS \
 		TEE_ENV \
 		"image=zImage\0" \
-		"fdt_file=undefined\0" \
+        	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
 		"fdt_addr=0x18000000\0" \
 		"fdt_high=0xffffffff\0"   \
 		"tee_addr=0x20000000\0" \
 		"tee_file=undefined\0" \
 		"findfdt="\
 			"if test $fdt_file = undefined; then " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \
 					"setenv fdt_file imx6qp-sabreauto.dtb; fi; " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \
 					"setenv fdt_file imx6q-sabreauto.dtb; fi; " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
 					"setenv fdt_file imx6dl-sabreauto.dtb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
 					"setenv fdt_file imx6qp-sabresd.dtb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
 					"setenv fdt_file imx6q-sabresd.dtb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
 					"setenv fdt_file imx6dl-sabresd.dtb; fi; " \
 				"if test $fdt_file = undefined; then " \
 					"echo WARNING: Could not determine dtb to use; " \
 				"fi; " \
 			"fi;\0" \
 		"findtee="\
 			"if test $tee_file = undefined; then " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \
 					"setenv tee_file uTee-6qpauto; fi; " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \
 					"setenv tee_file uTee-6qauto; fi; " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
 					"setenv tee_file uTee-6dlauto; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
 					"setenv tee_file uTee-6qpsdb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
 					"setenv tee_file uTee-6qsdb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
 					"setenv tee_file uTee-6dlsdb; fi; " \
 				"if test $tee_file = undefined; then " \
 					"echo WARNING: Could not determine tee to use; fi; " \
 			"fi;\0" \
 		"bootargs=console=" CONSOLE_DEV ",115200 \0"\
 		"bootargs_sata=setenv bootargs ${bootargs} " \
 			"root=/dev/sda2 rootwait rw \0" \
 		"bootcmd_sata=run bootargs_sata; sata init; " \
-			"run findfdt; run findtee;" \
 			"fatload sata 0:1 ${loadaddr} ${image}; " \
-			"fatload sata 0:1 ${fdt_addr} ${fdt_file}; " \
+			"fatload sata 0:1 ${fdt_addr} /dtbs/${fdt_file}; " \
 			"if test ${tee} = yes; then " \
 				"fatload sata 0:1 ${tee_addr} ${tee_file}; " \
 				"bootm ${tee_addr} - ${fdt_addr}; " \
 			"else " \
 				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"fi \0"\
 		"bootcmd=run bootcmd_sata \0"
 #else
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	CONFIG_MFG_ENV_SETTINGS \
 	TEE_ENV \
 	"epdc_waveform=epdc_splash.bin\0" \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
-	"fdt_file=undefined\0" \
+        "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"fdt_addr=0x18000000\0" \
 	"tee_addr=0x20000000\0" \
 	"tee_file=undefined\0" \
        	"fec.macaddr=${ethaddr}\0" \
        	"ipaddr=192.168.1.60\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
 	"console=" CONSOLE_DEV "\0" \
 	"dfuspi=dfu 1 sf 0:0:10000000:0\0" \
 	"dfu_alt_info_spl=spl raw 0x400\0" \
 	"dfu_alt_info_img=u-boot raw 0x10000\0" \
 	"dfu_alt_info=spl raw 0x400\0" \
 	"fdt_high=0xffffffff\0"	  \
 	"initrd_high=0xffffffff\0" \
 	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
 	"mmcpart=1\0" \
 	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
        	"sataroot=/dev/sda2 rootwait rw\0" \
        	"mmcrootfstype=ext4 rootwait\0" \
        	"satarootfstype=ext4 rootwait\0" \
 	"mmcautodetect=yes\0" \
 	"update_sd_firmware=" \
 		"if test ${ip_dyn} = yes; then " \
 			"setenv get_cmd dhcp; " \
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
 		"if mmc dev ${mmcdev}; then "	\
 			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
 				"setexpr fw_sz ${filesize} / 0x200; " \
 				"setexpr fw_sz ${fw_sz} + 1; "	\
 				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
 			"fi; "	\
 		"fi\0" \
 	EMMC_ENV	  \
 	"smp=" SYS_NOSMP "\0"\
 	"mmcargs=setenv bootargs console=${console},${baudrate} ${smp} " \
                	"root=${mmcroot}\0" \
                	"rootfstype=${mmcrootfstype} " \
                	"video=${video}\0" \
        	"sataargs=setenv bootargs console=${console},${baudrate} ${smp} " \
                	"${optargs} " \
                	"root=${sataroot}\0" \
                	"rootfstype=${satarootfstype} " \
                	"video=${video}\0" \
        	"loadbootenv=load mmc ${mmcdev}:${mmcpart} ${loadaddr} uEnv.txt\0" \
        	"loadsataenv=load sata 0:1 ${loadaddr} uEnv.txt\0" \
        	"importbootenv=echo Importing environment from mmc (uEnv.txt)...; " \
                	"env import -t $loadaddr $filesize\0" \
 	"loadbootscript=" \
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
        	"loadzimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
        	"loadsatazimage=load sata 0:1 ${loadaddr} ${image}\0" \
        	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} /dtbs/${fdt_file}\0" \
        	"loadsatafdt=load sata 0:1 ${fdt_addr} /dtbs/${fdt_file}\0" \
 	"loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${tee} = yes; then " \
 			"run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \
 		"else " \
 			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 				"if run loadfdt; then " \
 					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
 					"if test ${boot_fdt} = try; then " \
 						"bootz; " \
 					"else " \
 						"echo WARN: Cannot load the DT; " \
 					"fi; " \
 				"fi; " \
 			"else " \
 				"bootz; " \
 			"fi;" \
 		"fi;\0" \
        	"sataboot=echo Booting from sata ...; " \
                	"run sataargs; " \
                	"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
                        	"if run loadsatafdt; then " \
                                	"bootz ${loadaddr} - ${fdt_addr}; " \
                        	"else " \
                                	"if test ${boot_fdt} = try; then " \
                                        	"bootz; " \
                                	"else " \
                                        	"echo WARN: Cannot load the DT; " \
                                	"fi; " \
                        	"fi; " \
                	"else " \
                        	"bootz; " \
                	"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} ${smp} " \
 		"root=/dev/nfs " \
 		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
 	"netboot=echo Booting from net ...; " \
 		"run netargs; " \
 		"if test ${ip_dyn} = yes; then " \
 			"setenv get_cmd dhcp; " \
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
 		"${get_cmd} ${image}; " \
 		"if test ${tee} = yes; then " \
 			"${get_cmd} ${tee_addr} ${tee_file}; " \
 			"${get_cmd} ${fdt_addr} ${fdt_file}; " \
 			"bootm ${tee_addr} - ${fdt_addr}; " \
 		"else " \
 			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
 					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
 					"if test ${boot_fdt} = try; then " \
 						"bootz; " \
 					"else " \
 						"echo WARN: Cannot load the DT; " \
 					"fi; " \
 				"fi; " \
 			"else " \
 				"bootz; " \
 			"fi; " \
 		"fi;\0" \
 		"findfdt="\
 			"if test $fdt_file = undefined; then " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \
 					"setenv fdt_file imx6qp-sabreauto.dtb; fi; " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \
 					"setenv fdt_file imx6q-sabreauto.dtb; fi; " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
 					"setenv fdt_file imx6dl-sabreauto.dtb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
 					"setenv fdt_file imx6qp-sabresd.dtb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
 					"setenv fdt_file imx6q-sabresd.dtb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
 					"setenv fdt_file imx6dl-sabresd.dtb; fi; " \
                                	"if test $board_name = SMCMX1QP || test $board_name = SMCMX2QP && test $board_rev = MX6QP; then " \
                                        	"setenv fdt_file imx6qp-smarcfimx6.dtb; fi; " \
                                	"if test $board_name = SMCMXQ1G || test $board_name = SMCMXQ2G || test $board_name = SMCMXD1G || test $board_name = SMCMXD2G && test $board_rev = MX6Q; then " \
                                        	"setenv fdt_file imx6q-smarcfimx6.dtb; fi; " \
                                	"if test $board_name = SMCMXU1G || test $board_name = SMCMXSLO && test $board_rev = MX6DL; then " \
                                        	"setenv fdt_file imx6dl-smarcfimx6.dtb; fi; " \
 				"if test $fdt_file = undefined; then " \
 					"echo WARNING: Could not determine dtb to use; " \
 				"fi; " \
 			"fi;\0" \
 		"findtee="\
 			"if test $tee_file = undefined; then " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \
 					"setenv tee_file uTee-6qpauto; fi; " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \
 					"setenv tee_file uTee-6qauto; fi; " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
 					"setenv tee_file uTee-6dlauto; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
 					"setenv tee_file uTee-6qpsdb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
 					"setenv tee_file uTee-6qsdb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
 					"setenv tee_file uTee-6dlsdb; fi; " \
 				"if test $tee_file = undefined; then " \
 					"echo WARNING: Could not determine tee to use; fi; " \
 			"fi;\0" \
 #define CONFIG_BOOTCOMMAND \
-	"run findfdt;" \
-	"run findtee;" \
        	"if mmc rescan; then " \
                	"echo SD/MMC found on device ${mmcdev};" \
                	"if run loadbootenv; then " \
                        	"run importbootenv;" \
                	"fi;" \
                	"echo Checking if uenvcmd is set ...;" \
                	"if test -n $uenvcmd; then " \
                        	"echo Running uenvcmd ...;" \
                        	"run uenvcmd;" \
                	"fi;" \
                	"echo Running default loadzimage ...;" \
                	"if run loadzimage; then " \
                        	"run loadfdt;" \
                        	"run mmcboot;" \
                	"fi;" \
 	"else run netboot; fi"
 #endif
 #define CONFIG_ARP_TIMEOUT     200UL
 #define CONFIG_SYS_MEMTEST_START       0x10000000
 #define CONFIG_SYS_MEMTEST_END         0x10010000
 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS           1
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
 #define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 #define CONFIG_SYS_INIT_SP_OFFSET \
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 /* Environment organization */
 #define CONFIG_ENV_SIZE			(8 * 1024)
 #if defined CONFIG_SPI_BOOT
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #elif defined CONFIG_NOR_BOOT
 #define CONFIG_MTD_NOR_FLASH
 #define CONFIG_ENV_IS_IN_FLASH
 #elif defined CONFIG_NAND_BOOT
 #define CONFIG_CMD_NAND
 #define CONFIG_ENV_IS_IN_NAND
 #elif defined CONFIG_SATA_BOOT
 #define CONFIG_ENV_IS_IN_SATA
 #define CONFIG_CMD_SATA
 #else
 #define CONFIG_ENV_IS_IN_MMC
 #endif
 #ifdef CONFIG_SATA
 #define CONFIG_DWC_AHSATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	1
 #define CONFIG_DWC_AHSATA_PORT_ID	0
 #define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
 #define CONFIG_LBA48
 #define CONFIG_LIBATA
 #endif
 #ifdef CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_MACRONIX
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS  1
 #define CONFIG_SF_DEFAULT_SPEED 20000000
 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
 #endif
 #ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
 #define CONFIG_SYS_FLASH_SECT_SIZE      (128 * 1024)
 #define CONFIG_SYS_MAX_FLASH_BANKS 1    /* max number of memory banks */
 #define CONFIG_SYS_MAX_FLASH_SECT 256   /* max number of sectors on one chip */
 #define CONFIG_SYS_FLASH_CFI            /* Flash memory is CFI compliant */
 #define CONFIG_FLASH_CFI_DRIVER         /* Use drivers/cfi_flash.c */
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 #endif
 #ifdef CONFIG_CMD_NAND
 /* NAND flash command */
 #define CONFIG_CMD_NAND_TRIMFFS
 /* NAND stuff */
 #define CONFIG_NAND_MXS
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 /* DMA stuff, needed for GPMI/MXS NAND support */
 #define CONFIG_APBH_DMA
 #define CONFIG_APBH_DMA_BURST
 #define CONFIG_APBH_DMA_BURST8
 #endif
 #if defined(CONFIG_ENV_IS_IN_MMC)
 #define CONFIG_ENV_OFFSET		(896 * 1024)
 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 #define CONFIG_ENV_OFFSET              (896 * 1024)
 #define CONFIG_ENV_SECT_SIZE           (64 * 1024)
 #define CONFIG_ENV_SPI_BUS             CONFIG_SF_DEFAULT_BUS
 #define CONFIG_ENV_SPI_CS              CONFIG_SF_DEFAULT_CS
 #define CONFIG_ENV_SPI_MODE            CONFIG_SF_DEFAULT_MODE
 #define CONFIG_ENV_SPI_MAX_HZ          CONFIG_SF_DEFAULT_SPEED
 #elif defined(CONFIG_ENV_IS_IN_FLASH)
 #undef CONFIG_ENV_SIZE
 #define CONFIG_ENV_SIZE                        CONFIG_SYS_FLASH_SECT_SIZE
 #define CONFIG_ENV_SECT_SIZE           CONFIG_SYS_FLASH_SECT_SIZE
 #define CONFIG_ENV_OFFSET              (7 * CONFIG_SYS_FLASH_SECT_SIZE)
 #elif defined(CONFIG_ENV_IS_IN_NAND)
 #undef CONFIG_ENV_SIZE
 #define CONFIG_ENV_OFFSET              (60 << 20)
 #define CONFIG_ENV_SECT_SIZE           (128 << 10)
 #define CONFIG_ENV_SIZE                        CONFIG_ENV_SECT_SIZE
 #elif defined(CONFIG_ENV_IS_IN_SATA)
 #define CONFIG_ENV_OFFSET		(896 * 1024)
 #define CONFIG_SYS_SATA_ENV_DEV		0
 #define CONFIG_SYS_DCACHE_OFF /* remove when sata driver support cache */
 #endif
 /* I2C Configs */
 #ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
 #endif
 #ifdef CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		  100000
 #endif
 /* I2C switch definitions for PCA9546 chip */
 #define CONFIG_SYS_NUM_I2C_BUSES        5
 #define CONFIG_SYS_I2C_MAX_HOPS         2
 #define CONFIG_SYS_I2C_BUSES    {       {0, {I2C_NULL_HOP}}, \
                                         {1, {I2C_NULL_HOP}}, \
                                         {2, {{I2C_MUX_PCA9546, 0x70, 1}}}, \
                                         {2, {{I2C_MUX_PCA9546, 0x70, 2}}}, \
                                         {2, {{I2C_MUX_PCA9546, 0x70, 3}}}, \
                                 }
 /* Framebuffer */
 #define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 #if defined(CONFIG_ANDROID_SUPPORT)
 #include "smarcfimx6android_common.h"
 #else
 #define CONFIG_USBD_HS
 #endif /* CONFIG_ANDROID_SUPPORT */
 #endif                         /* __SMARCFIMX6_COMMON_CONFIG_H */