Commit 57e535649cba0900d49c3a06ddb7b3c15b900255
1 parent
fed31bd596
Exists in
smarc_8mq_lf_v2020.04
and in
2 other branches
Turn on level shift in PMIC
Showing 18 changed files with 19 additions and 19 deletions Inline Diff
- board/embedian/smarcimx8mp/lpddr4_timing.c
- board/embedian/smarcimx8mp/smarcimx8mp.c
- configs/smarcimx8mp_4g_ser0_android_defconfig
- configs/smarcimx8mp_4g_ser0_defconfig
- configs/smarcimx8mp_4g_ser1_android_defconfig
- configs/smarcimx8mp_4g_ser1_defconfig
- configs/smarcimx8mp_4g_ser2_android_defconfig
- configs/smarcimx8mp_4g_ser2_defconfig
- configs/smarcimx8mp_4g_ser3_android_defconfig
- configs/smarcimx8mp_4g_ser3_defconfig
- configs/smarcimx8mp_6g_ser0_android_defconfig
- configs/smarcimx8mp_6g_ser0_defconfig
- configs/smarcimx8mp_6g_ser1_android_defconfig
- configs/smarcimx8mp_6g_ser1_defconfig
- configs/smarcimx8mp_6g_ser2_android_defconfig
- configs/smarcimx8mp_6g_ser2_defconfig
- configs/smarcimx8mp_6g_ser3_android_defconfig
- configs/smarcimx8mp_6g_ser3_defconfig
board/embedian/smarcimx8mp/lpddr4_timing.c
| 1 | /* | 1 | /* |
| 2 | * Copyright 2019 NXP | 2 | * Copyright 2019 NXP |
| 3 | * | 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | * | 5 | * |
| 6 | * Generated code from MX8M_DDR_tool | 6 | * Generated code from MX8M_DDR_tool |
| 7 | * | 7 | * |
| 8 | * Align with uboot version: | 8 | * Align with uboot version: |
| 9 | * imx_v2019.04_5.4.x and above version | 9 | * imx_v2019.04_5.4.x and above version |
| 10 | * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: | 10 | * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: |
| 11 | * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h> | 11 | * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h> |
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
| 15 | #include <common.h> | 15 | #include <common.h> |
| 16 | #include <asm/arch/ddr.h> | 16 | #include <asm/arch/ddr.h> |
| 17 | 17 | ||
| 18 | #if defined(CONFIG_4GB_LPDDR4) | 18 | #if defined(CONFIG_4GB_LPDDR4) |
| 19 | struct dram_cfg_param ddr_ddrc_cfg[] = { | 19 | struct dram_cfg_param ddr_ddrc_cfg[] = { |
| 20 | /** Initialize DDRC registers **/ | 20 | /** Initialize DDRC registers **/ |
| 21 | { 0x3d400304, 0x1 }, | 21 | { 0x3d400304, 0x1 }, |
| 22 | { 0x3d400030, 0x1 }, | 22 | { 0x3d400030, 0x1 }, |
| 23 | { 0x3d400000, 0xa3080020 }, | 23 | { 0x3d400000, 0xa3080020 }, |
| 24 | { 0x3d400020, 0x1322 }, | 24 | { 0x3d400020, 0x1322 }, |
| 25 | { 0x3d400024, 0x1e84800 }, | 25 | { 0x3d400024, 0x1e84800 }, |
| 26 | { 0x3d400064, 0x3d0118 }, | 26 | { 0x3d400064, 0x3d0118 }, |
| 27 | { 0x3d400070, 0x61027f10 }, | 27 | { 0x3d400070, 0x61027f10 }, |
| 28 | { 0x3d400074, 0x7b0 }, | 28 | { 0x3d400074, 0x7b0 }, |
| 29 | { 0x3d4000d0, 0xc00307a3 }, | 29 | { 0x3d4000d0, 0xc00307a3 }, |
| 30 | { 0x3d4000d4, 0xc50000 }, | 30 | { 0x3d4000d4, 0xc50000 }, |
| 31 | { 0x3d4000dc, 0xf4003f }, | 31 | { 0x3d4000dc, 0xf4003f }, |
| 32 | { 0x3d4000e0, 0x330000 }, | 32 | { 0x3d4000e0, 0x330000 }, |
| 33 | { 0x3d4000e8, 0x660048 }, | 33 | { 0x3d4000e8, 0x660048 }, |
| 34 | { 0x3d4000ec, 0x160048 }, | 34 | { 0x3d4000ec, 0x160048 }, |
| 35 | { 0x3d400100, 0x2028112a }, | 35 | { 0x3d400100, 0x2028112a }, |
| 36 | { 0x3d400104, 0x8083f }, | 36 | { 0x3d400104, 0x8083f }, |
| 37 | { 0x3d40010c, 0xe0e000 }, | 37 | { 0x3d40010c, 0xe0e000 }, |
| 38 | { 0x3d400110, 0x12040a12 }, | 38 | { 0x3d400110, 0x12040a12 }, |
| 39 | { 0x3d400114, 0x2050f0f }, | 39 | { 0x3d400114, 0x2050f0f }, |
| 40 | { 0x3d400118, 0x1010009 }, | 40 | { 0x3d400118, 0x1010009 }, |
| 41 | { 0x3d40011c, 0x501 }, | 41 | { 0x3d40011c, 0x501 }, |
| 42 | { 0x3d400130, 0x20800 }, | 42 | { 0x3d400130, 0x20800 }, |
| 43 | { 0x3d400134, 0xe100002 }, | 43 | { 0x3d400134, 0xe100002 }, |
| 44 | { 0x3d400138, 0x120 }, | 44 | { 0x3d400138, 0x120 }, |
| 45 | { 0x3d400144, 0xc80064 }, | 45 | { 0x3d400144, 0xc80064 }, |
| 46 | { 0x3d400180, 0x3e8001e }, | 46 | { 0x3d400180, 0x3e8001e }, |
| 47 | { 0x3d400184, 0x3207a12 }, | 47 | { 0x3d400184, 0x3207a12 }, |
| 48 | { 0x3d400188, 0x0 }, | 48 | { 0x3d400188, 0x0 }, |
| 49 | { 0x3d400190, 0x49f820e }, | 49 | { 0x3d400190, 0x49f820e }, |
| 50 | { 0x3d400194, 0x80303 }, | 50 | { 0x3d400194, 0x80303 }, |
| 51 | { 0x3d4001b4, 0x1f0e }, | 51 | { 0x3d4001b4, 0x1f0e }, |
| 52 | { 0x3d4001a0, 0xe0400018 }, | 52 | { 0x3d4001a0, 0xe0400018 }, |
| 53 | { 0x3d4001a4, 0xdf00e4 }, | 53 | { 0x3d4001a4, 0xdf00e4 }, |
| 54 | { 0x3d4001a8, 0x80000000 }, | 54 | { 0x3d4001a8, 0x80000000 }, |
| 55 | { 0x3d4001b0, 0x11 }, | 55 | { 0x3d4001b0, 0x11 }, |
| 56 | { 0x3d4001c0, 0x1 }, | 56 | { 0x3d4001c0, 0x1 }, |
| 57 | { 0x3d4001c4, 0x1 }, | 57 | { 0x3d4001c4, 0x1 }, |
| 58 | { 0x3d4000f4, 0xc99 }, | 58 | { 0x3d4000f4, 0xc99 }, |
| 59 | { 0x3d400108, 0x9121c1c }, | 59 | { 0x3d400108, 0x9121c1c }, |
| 60 | { 0x3d400200, 0x17 }, | 60 | { 0x3d400200, 0x17 }, |
| 61 | { 0x3d40020c, 0x0 }, | 61 | { 0x3d40020c, 0x0 }, |
| 62 | { 0x3d400210, 0x1f1f }, | 62 | { 0x3d400210, 0x1f1f }, |
| 63 | { 0x3d400204, 0x80808 }, | 63 | { 0x3d400204, 0x80808 }, |
| 64 | { 0x3d400214, 0x7070707 }, | 64 | { 0x3d400214, 0x7070707 }, |
| 65 | { 0x3d400218, 0x7070707 }, | 65 | { 0x3d400218, 0x7070707 }, |
| 66 | { 0x3d40021c, 0xf0f }, | 66 | { 0x3d40021c, 0xf0f }, |
| 67 | { 0x3d400250, 0x1705 }, | 67 | { 0x3d400250, 0x1705 }, |
| 68 | { 0x3d400254, 0x2c }, | 68 | { 0x3d400254, 0x2c }, |
| 69 | { 0x3d40025c, 0x4000030 }, | 69 | { 0x3d40025c, 0x4000030 }, |
| 70 | { 0x3d400264, 0x900093e7 }, | 70 | { 0x3d400264, 0x900093e7 }, |
| 71 | { 0x3d40026c, 0x2005574 }, | 71 | { 0x3d40026c, 0x2005574 }, |
| 72 | { 0x3d400400, 0x111 }, | 72 | { 0x3d400400, 0x111 }, |
| 73 | { 0x3d400404, 0x72ff }, | 73 | { 0x3d400404, 0x72ff }, |
| 74 | { 0x3d400408, 0x72ff }, | 74 | { 0x3d400408, 0x72ff }, |
| 75 | { 0x3d400494, 0x2100e07 }, | 75 | { 0x3d400494, 0x2100e07 }, |
| 76 | { 0x3d400498, 0x620096 }, | 76 | { 0x3d400498, 0x620096 }, |
| 77 | { 0x3d40049c, 0x1100e07 }, | 77 | { 0x3d40049c, 0x1100e07 }, |
| 78 | { 0x3d4004a0, 0xc8012c }, | 78 | { 0x3d4004a0, 0xc8012c }, |
| 79 | { 0x3d402020, 0x1020 }, | 79 | { 0x3d402020, 0x1020 }, |
| 80 | { 0x3d402024, 0x30d400 }, | 80 | { 0x3d402024, 0x30d400 }, |
| 81 | { 0x3d402050, 0x20d000 }, | 81 | { 0x3d402050, 0x20d000 }, |
| 82 | { 0x3d402064, 0x6001c }, | 82 | { 0x3d402064, 0x6001c }, |
| 83 | { 0x3d4020dc, 0x840000 }, | 83 | { 0x3d4020dc, 0x840000 }, |
| 84 | { 0x3d4020e0, 0x330000 }, | 84 | { 0x3d4020e0, 0x330000 }, |
| 85 | { 0x3d4020e8, 0x660048 }, | 85 | { 0x3d4020e8, 0x660048 }, |
| 86 | { 0x3d4020ec, 0x160048 }, | 86 | { 0x3d4020ec, 0x160048 }, |
| 87 | { 0x3d402100, 0xa040105 }, | 87 | { 0x3d402100, 0xa040105 }, |
| 88 | { 0x3d402104, 0x30407 }, | 88 | { 0x3d402104, 0x30407 }, |
| 89 | { 0x3d402108, 0x203060b }, | 89 | { 0x3d402108, 0x203060b }, |
| 90 | { 0x3d40210c, 0x505000 }, | 90 | { 0x3d40210c, 0x505000 }, |
| 91 | { 0x3d402110, 0x2040202 }, | 91 | { 0x3d402110, 0x2040202 }, |
| 92 | { 0x3d402114, 0x2030202 }, | 92 | { 0x3d402114, 0x2030202 }, |
| 93 | { 0x3d402118, 0x1010004 }, | 93 | { 0x3d402118, 0x1010004 }, |
| 94 | { 0x3d40211c, 0x301 }, | 94 | { 0x3d40211c, 0x301 }, |
| 95 | { 0x3d402130, 0x20300 }, | 95 | { 0x3d402130, 0x20300 }, |
| 96 | { 0x3d402134, 0xa100002 }, | 96 | { 0x3d402134, 0xa100002 }, |
| 97 | { 0x3d402138, 0x1d }, | 97 | { 0x3d402138, 0x1d }, |
| 98 | { 0x3d402144, 0x14000a }, | 98 | { 0x3d402144, 0x14000a }, |
| 99 | { 0x3d402180, 0x640004 }, | 99 | { 0x3d402180, 0x640004 }, |
| 100 | { 0x3d402190, 0x3818200 }, | 100 | { 0x3d402190, 0x3818200 }, |
| 101 | { 0x3d402194, 0x80303 }, | 101 | { 0x3d402194, 0x80303 }, |
| 102 | { 0x3d4021b4, 0x100 }, | 102 | { 0x3d4021b4, 0x100 }, |
| 103 | { 0x3d4020f4, 0xc99 }, | 103 | { 0x3d4020f4, 0xc99 }, |
| 104 | { 0x3d403020, 0x1020 }, | 104 | { 0x3d403020, 0x1020 }, |
| 105 | { 0x3d403024, 0xc3500 }, | 105 | { 0x3d403024, 0xc3500 }, |
| 106 | { 0x3d403050, 0x20d000 }, | 106 | { 0x3d403050, 0x20d000 }, |
| 107 | { 0x3d403064, 0x30007 }, | 107 | { 0x3d403064, 0x30007 }, |
| 108 | { 0x3d4030dc, 0x840000 }, | 108 | { 0x3d4030dc, 0x840000 }, |
| 109 | { 0x3d4030e0, 0x330000 }, | 109 | { 0x3d4030e0, 0x330000 }, |
| 110 | { 0x3d4030e8, 0x660048 }, | 110 | { 0x3d4030e8, 0x660048 }, |
| 111 | { 0x3d4030ec, 0x160048 }, | 111 | { 0x3d4030ec, 0x160048 }, |
| 112 | { 0x3d403100, 0xa010102 }, | 112 | { 0x3d403100, 0xa010102 }, |
| 113 | { 0x3d403104, 0x30404 }, | 113 | { 0x3d403104, 0x30404 }, |
| 114 | { 0x3d403108, 0x203060b }, | 114 | { 0x3d403108, 0x203060b }, |
| 115 | { 0x3d40310c, 0x505000 }, | 115 | { 0x3d40310c, 0x505000 }, |
| 116 | { 0x3d403110, 0x2040202 }, | 116 | { 0x3d403110, 0x2040202 }, |
| 117 | { 0x3d403114, 0x2030202 }, | 117 | { 0x3d403114, 0x2030202 }, |
| 118 | { 0x3d403118, 0x1010004 }, | 118 | { 0x3d403118, 0x1010004 }, |
| 119 | { 0x3d40311c, 0x301 }, | 119 | { 0x3d40311c, 0x301 }, |
| 120 | { 0x3d403130, 0x20300 }, | 120 | { 0x3d403130, 0x20300 }, |
| 121 | { 0x3d403134, 0xa100002 }, | 121 | { 0x3d403134, 0xa100002 }, |
| 122 | { 0x3d403138, 0x8 }, | 122 | { 0x3d403138, 0x8 }, |
| 123 | { 0x3d403144, 0x50003 }, | 123 | { 0x3d403144, 0x50003 }, |
| 124 | { 0x3d403180, 0x190004 }, | 124 | { 0x3d403180, 0x190004 }, |
| 125 | { 0x3d403190, 0x3818200 }, | 125 | { 0x3d403190, 0x3818200 }, |
| 126 | { 0x3d403194, 0x80303 }, | 126 | { 0x3d403194, 0x80303 }, |
| 127 | { 0x3d4031b4, 0x100 }, | 127 | { 0x3d4031b4, 0x100 }, |
| 128 | { 0x3d4030f4, 0xc99 }, | 128 | { 0x3d4030f4, 0xc99 }, |
| 129 | { 0x3d400028, 0x0 }, | 129 | { 0x3d400028, 0x0 }, |
| 130 | }; | 130 | }; |
| 131 | 131 | ||
| 132 | /* PHY Initialize Configuration */ | 132 | /* PHY Initialize Configuration */ |
| 133 | struct dram_cfg_param ddr_ddrphy_cfg[] = { | 133 | struct dram_cfg_param ddr_ddrphy_cfg[] = { |
| 134 | { 0x100a0, 0x0 }, | 134 | { 0x100a0, 0x0 }, |
| 135 | { 0x100a1, 0x1 }, | 135 | { 0x100a1, 0x1 }, |
| 136 | { 0x100a2, 0x2 }, | 136 | { 0x100a2, 0x2 }, |
| 137 | { 0x100a3, 0x3 }, | 137 | { 0x100a3, 0x3 }, |
| 138 | { 0x100a4, 0x4 }, | 138 | { 0x100a4, 0x4 }, |
| 139 | { 0x100a5, 0x5 }, | 139 | { 0x100a5, 0x5 }, |
| 140 | { 0x100a6, 0x6 }, | 140 | { 0x100a6, 0x6 }, |
| 141 | { 0x100a7, 0x7 }, | 141 | { 0x100a7, 0x7 }, |
| 142 | { 0x110a0, 0x0 }, | 142 | { 0x110a0, 0x0 }, |
| 143 | { 0x110a1, 0x1 }, | 143 | { 0x110a1, 0x1 }, |
| 144 | { 0x110a2, 0x3 }, | 144 | { 0x110a2, 0x3 }, |
| 145 | { 0x110a3, 0x4 }, | 145 | { 0x110a3, 0x4 }, |
| 146 | { 0x110a4, 0x5 }, | 146 | { 0x110a4, 0x5 }, |
| 147 | { 0x110a5, 0x2 }, | 147 | { 0x110a5, 0x2 }, |
| 148 | { 0x110a6, 0x7 }, | 148 | { 0x110a6, 0x7 }, |
| 149 | { 0x110a7, 0x6 }, | 149 | { 0x110a7, 0x6 }, |
| 150 | { 0x120a0, 0x0 }, | 150 | { 0x120a0, 0x0 }, |
| 151 | { 0x120a1, 0x1 }, | 151 | { 0x120a1, 0x1 }, |
| 152 | { 0x120a2, 0x3 }, | 152 | { 0x120a2, 0x3 }, |
| 153 | { 0x120a3, 0x2 }, | 153 | { 0x120a3, 0x2 }, |
| 154 | { 0x120a4, 0x5 }, | 154 | { 0x120a4, 0x5 }, |
| 155 | { 0x120a5, 0x4 }, | 155 | { 0x120a5, 0x4 }, |
| 156 | { 0x120a6, 0x7 }, | 156 | { 0x120a6, 0x7 }, |
| 157 | { 0x120a7, 0x6 }, | 157 | { 0x120a7, 0x6 }, |
| 158 | { 0x130a0, 0x0 }, | 158 | { 0x130a0, 0x0 }, |
| 159 | { 0x130a1, 0x1 }, | 159 | { 0x130a1, 0x1 }, |
| 160 | { 0x130a2, 0x2 }, | 160 | { 0x130a2, 0x2 }, |
| 161 | { 0x130a3, 0x3 }, | 161 | { 0x130a3, 0x3 }, |
| 162 | { 0x130a4, 0x4 }, | 162 | { 0x130a4, 0x4 }, |
| 163 | { 0x130a5, 0x5 }, | 163 | { 0x130a5, 0x5 }, |
| 164 | { 0x130a6, 0x6 }, | 164 | { 0x130a6, 0x6 }, |
| 165 | { 0x130a7, 0x7 }, | 165 | { 0x130a7, 0x7 }, |
| 166 | { 0x1005f, 0x1ff }, | 166 | { 0x1005f, 0x1ff }, |
| 167 | { 0x1015f, 0x1ff }, | 167 | { 0x1015f, 0x1ff }, |
| 168 | { 0x1105f, 0x1ff }, | 168 | { 0x1105f, 0x1ff }, |
| 169 | { 0x1115f, 0x1ff }, | 169 | { 0x1115f, 0x1ff }, |
| 170 | { 0x1205f, 0x1ff }, | 170 | { 0x1205f, 0x1ff }, |
| 171 | { 0x1215f, 0x1ff }, | 171 | { 0x1215f, 0x1ff }, |
| 172 | { 0x1305f, 0x1ff }, | 172 | { 0x1305f, 0x1ff }, |
| 173 | { 0x1315f, 0x1ff }, | 173 | { 0x1315f, 0x1ff }, |
| 174 | { 0x11005f, 0x1ff }, | 174 | { 0x11005f, 0x1ff }, |
| 175 | { 0x11015f, 0x1ff }, | 175 | { 0x11015f, 0x1ff }, |
| 176 | { 0x11105f, 0x1ff }, | 176 | { 0x11105f, 0x1ff }, |
| 177 | { 0x11115f, 0x1ff }, | 177 | { 0x11115f, 0x1ff }, |
| 178 | { 0x11205f, 0x1ff }, | 178 | { 0x11205f, 0x1ff }, |
| 179 | { 0x11215f, 0x1ff }, | 179 | { 0x11215f, 0x1ff }, |
| 180 | { 0x11305f, 0x1ff }, | 180 | { 0x11305f, 0x1ff }, |
| 181 | { 0x11315f, 0x1ff }, | 181 | { 0x11315f, 0x1ff }, |
| 182 | { 0x21005f, 0x1ff }, | 182 | { 0x21005f, 0x1ff }, |
| 183 | { 0x21015f, 0x1ff }, | 183 | { 0x21015f, 0x1ff }, |
| 184 | { 0x21105f, 0x1ff }, | 184 | { 0x21105f, 0x1ff }, |
| 185 | { 0x21115f, 0x1ff }, | 185 | { 0x21115f, 0x1ff }, |
| 186 | { 0x21205f, 0x1ff }, | 186 | { 0x21205f, 0x1ff }, |
| 187 | { 0x21215f, 0x1ff }, | 187 | { 0x21215f, 0x1ff }, |
| 188 | { 0x21305f, 0x1ff }, | 188 | { 0x21305f, 0x1ff }, |
| 189 | { 0x21315f, 0x1ff }, | 189 | { 0x21315f, 0x1ff }, |
| 190 | { 0x55, 0x1ff }, | 190 | { 0x55, 0x1ff }, |
| 191 | { 0x1055, 0x1ff }, | 191 | { 0x1055, 0x1ff }, |
| 192 | { 0x2055, 0x1ff }, | 192 | { 0x2055, 0x1ff }, |
| 193 | { 0x3055, 0x1ff }, | 193 | { 0x3055, 0x1ff }, |
| 194 | { 0x4055, 0x1ff }, | 194 | { 0x4055, 0x1ff }, |
| 195 | { 0x5055, 0x1ff }, | 195 | { 0x5055, 0x1ff }, |
| 196 | { 0x6055, 0x1ff }, | 196 | { 0x6055, 0x1ff }, |
| 197 | { 0x7055, 0x1ff }, | 197 | { 0x7055, 0x1ff }, |
| 198 | { 0x8055, 0x1ff }, | 198 | { 0x8055, 0x1ff }, |
| 199 | { 0x9055, 0x1ff }, | 199 | { 0x9055, 0x1ff }, |
| 200 | { 0x200c5, 0x18 }, | 200 | { 0x200c5, 0x18 }, |
| 201 | { 0x1200c5, 0x7 }, | 201 | { 0x1200c5, 0x7 }, |
| 202 | { 0x2200c5, 0x7 }, | 202 | { 0x2200c5, 0x7 }, |
| 203 | { 0x2002e, 0x2 }, | 203 | { 0x2002e, 0x2 }, |
| 204 | { 0x12002e, 0x2 }, | 204 | { 0x12002e, 0x2 }, |
| 205 | { 0x22002e, 0x2 }, | 205 | { 0x22002e, 0x2 }, |
| 206 | { 0x90204, 0x0 }, | 206 | { 0x90204, 0x0 }, |
| 207 | { 0x190204, 0x0 }, | 207 | { 0x190204, 0x0 }, |
| 208 | { 0x290204, 0x0 }, | 208 | { 0x290204, 0x0 }, |
| 209 | { 0x20024, 0x1e3 }, | 209 | { 0x20024, 0x1e3 }, |
| 210 | { 0x2003a, 0x2 }, | 210 | { 0x2003a, 0x2 }, |
| 211 | { 0x120024, 0x1e3 }, | 211 | { 0x120024, 0x1e3 }, |
| 212 | { 0x2003a, 0x2 }, | 212 | { 0x2003a, 0x2 }, |
| 213 | { 0x220024, 0x1e3 }, | 213 | { 0x220024, 0x1e3 }, |
| 214 | { 0x2003a, 0x2 }, | 214 | { 0x2003a, 0x2 }, |
| 215 | { 0x20056, 0x3 }, | 215 | { 0x20056, 0x3 }, |
| 216 | { 0x120056, 0x3 }, | 216 | { 0x120056, 0x3 }, |
| 217 | { 0x220056, 0x3 }, | 217 | { 0x220056, 0x3 }, |
| 218 | { 0x1004d, 0xe00 }, | 218 | { 0x1004d, 0xe00 }, |
| 219 | { 0x1014d, 0xe00 }, | 219 | { 0x1014d, 0xe00 }, |
| 220 | { 0x1104d, 0xe00 }, | 220 | { 0x1104d, 0xe00 }, |
| 221 | { 0x1114d, 0xe00 }, | 221 | { 0x1114d, 0xe00 }, |
| 222 | { 0x1204d, 0xe00 }, | 222 | { 0x1204d, 0xe00 }, |
| 223 | { 0x1214d, 0xe00 }, | 223 | { 0x1214d, 0xe00 }, |
| 224 | { 0x1304d, 0xe00 }, | 224 | { 0x1304d, 0xe00 }, |
| 225 | { 0x1314d, 0xe00 }, | 225 | { 0x1314d, 0xe00 }, |
| 226 | { 0x11004d, 0xe00 }, | 226 | { 0x11004d, 0xe00 }, |
| 227 | { 0x11014d, 0xe00 }, | 227 | { 0x11014d, 0xe00 }, |
| 228 | { 0x11104d, 0xe00 }, | 228 | { 0x11104d, 0xe00 }, |
| 229 | { 0x11114d, 0xe00 }, | 229 | { 0x11114d, 0xe00 }, |
| 230 | { 0x11204d, 0xe00 }, | 230 | { 0x11204d, 0xe00 }, |
| 231 | { 0x11214d, 0xe00 }, | 231 | { 0x11214d, 0xe00 }, |
| 232 | { 0x11304d, 0xe00 }, | 232 | { 0x11304d, 0xe00 }, |
| 233 | { 0x11314d, 0xe00 }, | 233 | { 0x11314d, 0xe00 }, |
| 234 | { 0x21004d, 0xe00 }, | 234 | { 0x21004d, 0xe00 }, |
| 235 | { 0x21014d, 0xe00 }, | 235 | { 0x21014d, 0xe00 }, |
| 236 | { 0x21104d, 0xe00 }, | 236 | { 0x21104d, 0xe00 }, |
| 237 | { 0x21114d, 0xe00 }, | 237 | { 0x21114d, 0xe00 }, |
| 238 | { 0x21204d, 0xe00 }, | 238 | { 0x21204d, 0xe00 }, |
| 239 | { 0x21214d, 0xe00 }, | 239 | { 0x21214d, 0xe00 }, |
| 240 | { 0x21304d, 0xe00 }, | 240 | { 0x21304d, 0xe00 }, |
| 241 | { 0x21314d, 0xe00 }, | 241 | { 0x21314d, 0xe00 }, |
| 242 | { 0x10049, 0xeba }, | 242 | { 0x10049, 0xeba }, |
| 243 | { 0x10149, 0xeba }, | 243 | { 0x10149, 0xeba }, |
| 244 | { 0x11049, 0xeba }, | 244 | { 0x11049, 0xeba }, |
| 245 | { 0x11149, 0xeba }, | 245 | { 0x11149, 0xeba }, |
| 246 | { 0x12049, 0xeba }, | 246 | { 0x12049, 0xeba }, |
| 247 | { 0x12149, 0xeba }, | 247 | { 0x12149, 0xeba }, |
| 248 | { 0x13049, 0xeba }, | 248 | { 0x13049, 0xeba }, |
| 249 | { 0x13149, 0xeba }, | 249 | { 0x13149, 0xeba }, |
| 250 | { 0x110049, 0xeba }, | 250 | { 0x110049, 0xeba }, |
| 251 | { 0x110149, 0xeba }, | 251 | { 0x110149, 0xeba }, |
| 252 | { 0x111049, 0xeba }, | 252 | { 0x111049, 0xeba }, |
| 253 | { 0x111149, 0xeba }, | 253 | { 0x111149, 0xeba }, |
| 254 | { 0x112049, 0xeba }, | 254 | { 0x112049, 0xeba }, |
| 255 | { 0x112149, 0xeba }, | 255 | { 0x112149, 0xeba }, |
| 256 | { 0x113049, 0xeba }, | 256 | { 0x113049, 0xeba }, |
| 257 | { 0x113149, 0xeba }, | 257 | { 0x113149, 0xeba }, |
| 258 | { 0x210049, 0xeba }, | 258 | { 0x210049, 0xeba }, |
| 259 | { 0x210149, 0xeba }, | 259 | { 0x210149, 0xeba }, |
| 260 | { 0x211049, 0xeba }, | 260 | { 0x211049, 0xeba }, |
| 261 | { 0x211149, 0xeba }, | 261 | { 0x211149, 0xeba }, |
| 262 | { 0x212049, 0xeba }, | 262 | { 0x212049, 0xeba }, |
| 263 | { 0x212149, 0xeba }, | 263 | { 0x212149, 0xeba }, |
| 264 | { 0x213049, 0xeba }, | 264 | { 0x213049, 0xeba }, |
| 265 | { 0x213149, 0xeba }, | 265 | { 0x213149, 0xeba }, |
| 266 | { 0x43, 0x63 }, | 266 | { 0x43, 0x63 }, |
| 267 | { 0x1043, 0x63 }, | 267 | { 0x1043, 0x63 }, |
| 268 | { 0x2043, 0x63 }, | 268 | { 0x2043, 0x63 }, |
| 269 | { 0x3043, 0x63 }, | 269 | { 0x3043, 0x63 }, |
| 270 | { 0x4043, 0x63 }, | 270 | { 0x4043, 0x63 }, |
| 271 | { 0x5043, 0x63 }, | 271 | { 0x5043, 0x63 }, |
| 272 | { 0x6043, 0x63 }, | 272 | { 0x6043, 0x63 }, |
| 273 | { 0x7043, 0x63 }, | 273 | { 0x7043, 0x63 }, |
| 274 | { 0x8043, 0x63 }, | 274 | { 0x8043, 0x63 }, |
| 275 | { 0x9043, 0x63 }, | 275 | { 0x9043, 0x63 }, |
| 276 | { 0x20018, 0x3 }, | 276 | { 0x20018, 0x3 }, |
| 277 | { 0x20075, 0x4 }, | 277 | { 0x20075, 0x4 }, |
| 278 | { 0x20050, 0x0 }, | 278 | { 0x20050, 0x0 }, |
| 279 | { 0x20008, 0x3e8 }, | 279 | { 0x20008, 0x3e8 }, |
| 280 | { 0x120008, 0x64 }, | 280 | { 0x120008, 0x64 }, |
| 281 | { 0x220008, 0x19 }, | 281 | { 0x220008, 0x19 }, |
| 282 | { 0x20088, 0x9 }, | 282 | { 0x20088, 0x9 }, |
| 283 | { 0x200b2, 0x104 }, | 283 | { 0x200b2, 0x104 }, |
| 284 | { 0x10043, 0x5a1 }, | 284 | { 0x10043, 0x5a1 }, |
| 285 | { 0x10143, 0x5a1 }, | 285 | { 0x10143, 0x5a1 }, |
| 286 | { 0x11043, 0x5a1 }, | 286 | { 0x11043, 0x5a1 }, |
| 287 | { 0x11143, 0x5a1 }, | 287 | { 0x11143, 0x5a1 }, |
| 288 | { 0x12043, 0x5a1 }, | 288 | { 0x12043, 0x5a1 }, |
| 289 | { 0x12143, 0x5a1 }, | 289 | { 0x12143, 0x5a1 }, |
| 290 | { 0x13043, 0x5a1 }, | 290 | { 0x13043, 0x5a1 }, |
| 291 | { 0x13143, 0x5a1 }, | 291 | { 0x13143, 0x5a1 }, |
| 292 | { 0x1200b2, 0x104 }, | 292 | { 0x1200b2, 0x104 }, |
| 293 | { 0x110043, 0x5a1 }, | 293 | { 0x110043, 0x5a1 }, |
| 294 | { 0x110143, 0x5a1 }, | 294 | { 0x110143, 0x5a1 }, |
| 295 | { 0x111043, 0x5a1 }, | 295 | { 0x111043, 0x5a1 }, |
| 296 | { 0x111143, 0x5a1 }, | 296 | { 0x111143, 0x5a1 }, |
| 297 | { 0x112043, 0x5a1 }, | 297 | { 0x112043, 0x5a1 }, |
| 298 | { 0x112143, 0x5a1 }, | 298 | { 0x112143, 0x5a1 }, |
| 299 | { 0x113043, 0x5a1 }, | 299 | { 0x113043, 0x5a1 }, |
| 300 | { 0x113143, 0x5a1 }, | 300 | { 0x113143, 0x5a1 }, |
| 301 | { 0x2200b2, 0x104 }, | 301 | { 0x2200b2, 0x104 }, |
| 302 | { 0x210043, 0x5a1 }, | 302 | { 0x210043, 0x5a1 }, |
| 303 | { 0x210143, 0x5a1 }, | 303 | { 0x210143, 0x5a1 }, |
| 304 | { 0x211043, 0x5a1 }, | 304 | { 0x211043, 0x5a1 }, |
| 305 | { 0x211143, 0x5a1 }, | 305 | { 0x211143, 0x5a1 }, |
| 306 | { 0x212043, 0x5a1 }, | 306 | { 0x212043, 0x5a1 }, |
| 307 | { 0x212143, 0x5a1 }, | 307 | { 0x212143, 0x5a1 }, |
| 308 | { 0x213043, 0x5a1 }, | 308 | { 0x213043, 0x5a1 }, |
| 309 | { 0x213143, 0x5a1 }, | 309 | { 0x213143, 0x5a1 }, |
| 310 | { 0x200fa, 0x1 }, | 310 | { 0x200fa, 0x1 }, |
| 311 | { 0x1200fa, 0x1 }, | 311 | { 0x1200fa, 0x1 }, |
| 312 | { 0x2200fa, 0x1 }, | 312 | { 0x2200fa, 0x1 }, |
| 313 | { 0x20019, 0x1 }, | 313 | { 0x20019, 0x1 }, |
| 314 | { 0x120019, 0x1 }, | 314 | { 0x120019, 0x1 }, |
| 315 | { 0x220019, 0x1 }, | 315 | { 0x220019, 0x1 }, |
| 316 | { 0x200f0, 0x660 }, | 316 | { 0x200f0, 0x660 }, |
| 317 | { 0x200f1, 0x0 }, | 317 | { 0x200f1, 0x0 }, |
| 318 | { 0x200f2, 0x4444 }, | 318 | { 0x200f2, 0x4444 }, |
| 319 | { 0x200f3, 0x8888 }, | 319 | { 0x200f3, 0x8888 }, |
| 320 | { 0x200f4, 0x5665 }, | 320 | { 0x200f4, 0x5665 }, |
| 321 | { 0x200f5, 0x0 }, | 321 | { 0x200f5, 0x0 }, |
| 322 | { 0x200f6, 0x0 }, | 322 | { 0x200f6, 0x0 }, |
| 323 | { 0x200f7, 0xf000 }, | 323 | { 0x200f7, 0xf000 }, |
| 324 | { 0x20025, 0x0 }, | 324 | { 0x20025, 0x0 }, |
| 325 | { 0x2002d, 0x0 }, | 325 | { 0x2002d, 0x0 }, |
| 326 | { 0x12002d, 0x0 }, | 326 | { 0x12002d, 0x0 }, |
| 327 | { 0x22002d, 0x0 }, | 327 | { 0x22002d, 0x0 }, |
| 328 | { 0x2007d, 0x212 }, | 328 | { 0x2007d, 0x212 }, |
| 329 | { 0x12007d, 0x212 }, | 329 | { 0x12007d, 0x212 }, |
| 330 | { 0x22007d, 0x212 }, | 330 | { 0x22007d, 0x212 }, |
| 331 | { 0x2007c, 0x61 }, | 331 | { 0x2007c, 0x61 }, |
| 332 | { 0x12007c, 0x61 }, | 332 | { 0x12007c, 0x61 }, |
| 333 | { 0x22007c, 0x61 }, | 333 | { 0x22007c, 0x61 }, |
| 334 | { 0x1004a, 0x500 }, | 334 | { 0x1004a, 0x500 }, |
| 335 | { 0x1104a, 0x500 }, | 335 | { 0x1104a, 0x500 }, |
| 336 | { 0x1204a, 0x500 }, | 336 | { 0x1204a, 0x500 }, |
| 337 | { 0x1304a, 0x500 }, | 337 | { 0x1304a, 0x500 }, |
| 338 | { 0x2002c, 0x0 }, | 338 | { 0x2002c, 0x0 }, |
| 339 | }; | 339 | }; |
| 340 | 340 | ||
| 341 | /* ddr phy trained csr */ | 341 | /* ddr phy trained csr */ |
| 342 | struct dram_cfg_param ddr_ddrphy_trained_csr[] = { | 342 | struct dram_cfg_param ddr_ddrphy_trained_csr[] = { |
| 343 | { 0x200b2, 0x0 }, | 343 | { 0x200b2, 0x0 }, |
| 344 | { 0x1200b2, 0x0 }, | 344 | { 0x1200b2, 0x0 }, |
| 345 | { 0x2200b2, 0x0 }, | 345 | { 0x2200b2, 0x0 }, |
| 346 | { 0x200cb, 0x0 }, | 346 | { 0x200cb, 0x0 }, |
| 347 | { 0x10043, 0x0 }, | 347 | { 0x10043, 0x0 }, |
| 348 | { 0x110043, 0x0 }, | 348 | { 0x110043, 0x0 }, |
| 349 | { 0x210043, 0x0 }, | 349 | { 0x210043, 0x0 }, |
| 350 | { 0x10143, 0x0 }, | 350 | { 0x10143, 0x0 }, |
| 351 | { 0x110143, 0x0 }, | 351 | { 0x110143, 0x0 }, |
| 352 | { 0x210143, 0x0 }, | 352 | { 0x210143, 0x0 }, |
| 353 | { 0x11043, 0x0 }, | 353 | { 0x11043, 0x0 }, |
| 354 | { 0x111043, 0x0 }, | 354 | { 0x111043, 0x0 }, |
| 355 | { 0x211043, 0x0 }, | 355 | { 0x211043, 0x0 }, |
| 356 | { 0x11143, 0x0 }, | 356 | { 0x11143, 0x0 }, |
| 357 | { 0x111143, 0x0 }, | 357 | { 0x111143, 0x0 }, |
| 358 | { 0x211143, 0x0 }, | 358 | { 0x211143, 0x0 }, |
| 359 | { 0x12043, 0x0 }, | 359 | { 0x12043, 0x0 }, |
| 360 | { 0x112043, 0x0 }, | 360 | { 0x112043, 0x0 }, |
| 361 | { 0x212043, 0x0 }, | 361 | { 0x212043, 0x0 }, |
| 362 | { 0x12143, 0x0 }, | 362 | { 0x12143, 0x0 }, |
| 363 | { 0x112143, 0x0 }, | 363 | { 0x112143, 0x0 }, |
| 364 | { 0x212143, 0x0 }, | 364 | { 0x212143, 0x0 }, |
| 365 | { 0x13043, 0x0 }, | 365 | { 0x13043, 0x0 }, |
| 366 | { 0x113043, 0x0 }, | 366 | { 0x113043, 0x0 }, |
| 367 | { 0x213043, 0x0 }, | 367 | { 0x213043, 0x0 }, |
| 368 | { 0x13143, 0x0 }, | 368 | { 0x13143, 0x0 }, |
| 369 | { 0x113143, 0x0 }, | 369 | { 0x113143, 0x0 }, |
| 370 | { 0x213143, 0x0 }, | 370 | { 0x213143, 0x0 }, |
| 371 | { 0x80, 0x0 }, | 371 | { 0x80, 0x0 }, |
| 372 | { 0x100080, 0x0 }, | 372 | { 0x100080, 0x0 }, |
| 373 | { 0x200080, 0x0 }, | 373 | { 0x200080, 0x0 }, |
| 374 | { 0x1080, 0x0 }, | 374 | { 0x1080, 0x0 }, |
| 375 | { 0x101080, 0x0 }, | 375 | { 0x101080, 0x0 }, |
| 376 | { 0x201080, 0x0 }, | 376 | { 0x201080, 0x0 }, |
| 377 | { 0x2080, 0x0 }, | 377 | { 0x2080, 0x0 }, |
| 378 | { 0x102080, 0x0 }, | 378 | { 0x102080, 0x0 }, |
| 379 | { 0x202080, 0x0 }, | 379 | { 0x202080, 0x0 }, |
| 380 | { 0x3080, 0x0 }, | 380 | { 0x3080, 0x0 }, |
| 381 | { 0x103080, 0x0 }, | 381 | { 0x103080, 0x0 }, |
| 382 | { 0x203080, 0x0 }, | 382 | { 0x203080, 0x0 }, |
| 383 | { 0x4080, 0x0 }, | 383 | { 0x4080, 0x0 }, |
| 384 | { 0x104080, 0x0 }, | 384 | { 0x104080, 0x0 }, |
| 385 | { 0x204080, 0x0 }, | 385 | { 0x204080, 0x0 }, |
| 386 | { 0x5080, 0x0 }, | 386 | { 0x5080, 0x0 }, |
| 387 | { 0x105080, 0x0 }, | 387 | { 0x105080, 0x0 }, |
| 388 | { 0x205080, 0x0 }, | 388 | { 0x205080, 0x0 }, |
| 389 | { 0x6080, 0x0 }, | 389 | { 0x6080, 0x0 }, |
| 390 | { 0x106080, 0x0 }, | 390 | { 0x106080, 0x0 }, |
| 391 | { 0x206080, 0x0 }, | 391 | { 0x206080, 0x0 }, |
| 392 | { 0x7080, 0x0 }, | 392 | { 0x7080, 0x0 }, |
| 393 | { 0x107080, 0x0 }, | 393 | { 0x107080, 0x0 }, |
| 394 | { 0x207080, 0x0 }, | 394 | { 0x207080, 0x0 }, |
| 395 | { 0x8080, 0x0 }, | 395 | { 0x8080, 0x0 }, |
| 396 | { 0x108080, 0x0 }, | 396 | { 0x108080, 0x0 }, |
| 397 | { 0x208080, 0x0 }, | 397 | { 0x208080, 0x0 }, |
| 398 | { 0x9080, 0x0 }, | 398 | { 0x9080, 0x0 }, |
| 399 | { 0x109080, 0x0 }, | 399 | { 0x109080, 0x0 }, |
| 400 | { 0x209080, 0x0 }, | 400 | { 0x209080, 0x0 }, |
| 401 | { 0x10080, 0x0 }, | 401 | { 0x10080, 0x0 }, |
| 402 | { 0x110080, 0x0 }, | 402 | { 0x110080, 0x0 }, |
| 403 | { 0x210080, 0x0 }, | 403 | { 0x210080, 0x0 }, |
| 404 | { 0x10180, 0x0 }, | 404 | { 0x10180, 0x0 }, |
| 405 | { 0x110180, 0x0 }, | 405 | { 0x110180, 0x0 }, |
| 406 | { 0x210180, 0x0 }, | 406 | { 0x210180, 0x0 }, |
| 407 | { 0x11080, 0x0 }, | 407 | { 0x11080, 0x0 }, |
| 408 | { 0x111080, 0x0 }, | 408 | { 0x111080, 0x0 }, |
| 409 | { 0x211080, 0x0 }, | 409 | { 0x211080, 0x0 }, |
| 410 | { 0x11180, 0x0 }, | 410 | { 0x11180, 0x0 }, |
| 411 | { 0x111180, 0x0 }, | 411 | { 0x111180, 0x0 }, |
| 412 | { 0x211180, 0x0 }, | 412 | { 0x211180, 0x0 }, |
| 413 | { 0x12080, 0x0 }, | 413 | { 0x12080, 0x0 }, |
| 414 | { 0x112080, 0x0 }, | 414 | { 0x112080, 0x0 }, |
| 415 | { 0x212080, 0x0 }, | 415 | { 0x212080, 0x0 }, |
| 416 | { 0x12180, 0x0 }, | 416 | { 0x12180, 0x0 }, |
| 417 | { 0x112180, 0x0 }, | 417 | { 0x112180, 0x0 }, |
| 418 | { 0x212180, 0x0 }, | 418 | { 0x212180, 0x0 }, |
| 419 | { 0x13080, 0x0 }, | 419 | { 0x13080, 0x0 }, |
| 420 | { 0x113080, 0x0 }, | 420 | { 0x113080, 0x0 }, |
| 421 | { 0x213080, 0x0 }, | 421 | { 0x213080, 0x0 }, |
| 422 | { 0x13180, 0x0 }, | 422 | { 0x13180, 0x0 }, |
| 423 | { 0x113180, 0x0 }, | 423 | { 0x113180, 0x0 }, |
| 424 | { 0x213180, 0x0 }, | 424 | { 0x213180, 0x0 }, |
| 425 | { 0x10081, 0x0 }, | 425 | { 0x10081, 0x0 }, |
| 426 | { 0x110081, 0x0 }, | 426 | { 0x110081, 0x0 }, |
| 427 | { 0x210081, 0x0 }, | 427 | { 0x210081, 0x0 }, |
| 428 | { 0x10181, 0x0 }, | 428 | { 0x10181, 0x0 }, |
| 429 | { 0x110181, 0x0 }, | 429 | { 0x110181, 0x0 }, |
| 430 | { 0x210181, 0x0 }, | 430 | { 0x210181, 0x0 }, |
| 431 | { 0x11081, 0x0 }, | 431 | { 0x11081, 0x0 }, |
| 432 | { 0x111081, 0x0 }, | 432 | { 0x111081, 0x0 }, |
| 433 | { 0x211081, 0x0 }, | 433 | { 0x211081, 0x0 }, |
| 434 | { 0x11181, 0x0 }, | 434 | { 0x11181, 0x0 }, |
| 435 | { 0x111181, 0x0 }, | 435 | { 0x111181, 0x0 }, |
| 436 | { 0x211181, 0x0 }, | 436 | { 0x211181, 0x0 }, |
| 437 | { 0x12081, 0x0 }, | 437 | { 0x12081, 0x0 }, |
| 438 | { 0x112081, 0x0 }, | 438 | { 0x112081, 0x0 }, |
| 439 | { 0x212081, 0x0 }, | 439 | { 0x212081, 0x0 }, |
| 440 | { 0x12181, 0x0 }, | 440 | { 0x12181, 0x0 }, |
| 441 | { 0x112181, 0x0 }, | 441 | { 0x112181, 0x0 }, |
| 442 | { 0x212181, 0x0 }, | 442 | { 0x212181, 0x0 }, |
| 443 | { 0x13081, 0x0 }, | 443 | { 0x13081, 0x0 }, |
| 444 | { 0x113081, 0x0 }, | 444 | { 0x113081, 0x0 }, |
| 445 | { 0x213081, 0x0 }, | 445 | { 0x213081, 0x0 }, |
| 446 | { 0x13181, 0x0 }, | 446 | { 0x13181, 0x0 }, |
| 447 | { 0x113181, 0x0 }, | 447 | { 0x113181, 0x0 }, |
| 448 | { 0x213181, 0x0 }, | 448 | { 0x213181, 0x0 }, |
| 449 | { 0x100d0, 0x0 }, | 449 | { 0x100d0, 0x0 }, |
| 450 | { 0x1100d0, 0x0 }, | 450 | { 0x1100d0, 0x0 }, |
| 451 | { 0x2100d0, 0x0 }, | 451 | { 0x2100d0, 0x0 }, |
| 452 | { 0x101d0, 0x0 }, | 452 | { 0x101d0, 0x0 }, |
| 453 | { 0x1101d0, 0x0 }, | 453 | { 0x1101d0, 0x0 }, |
| 454 | { 0x2101d0, 0x0 }, | 454 | { 0x2101d0, 0x0 }, |
| 455 | { 0x110d0, 0x0 }, | 455 | { 0x110d0, 0x0 }, |
| 456 | { 0x1110d0, 0x0 }, | 456 | { 0x1110d0, 0x0 }, |
| 457 | { 0x2110d0, 0x0 }, | 457 | { 0x2110d0, 0x0 }, |
| 458 | { 0x111d0, 0x0 }, | 458 | { 0x111d0, 0x0 }, |
| 459 | { 0x1111d0, 0x0 }, | 459 | { 0x1111d0, 0x0 }, |
| 460 | { 0x2111d0, 0x0 }, | 460 | { 0x2111d0, 0x0 }, |
| 461 | { 0x120d0, 0x0 }, | 461 | { 0x120d0, 0x0 }, |
| 462 | { 0x1120d0, 0x0 }, | 462 | { 0x1120d0, 0x0 }, |
| 463 | { 0x2120d0, 0x0 }, | 463 | { 0x2120d0, 0x0 }, |
| 464 | { 0x121d0, 0x0 }, | 464 | { 0x121d0, 0x0 }, |
| 465 | { 0x1121d0, 0x0 }, | 465 | { 0x1121d0, 0x0 }, |
| 466 | { 0x2121d0, 0x0 }, | 466 | { 0x2121d0, 0x0 }, |
| 467 | { 0x130d0, 0x0 }, | 467 | { 0x130d0, 0x0 }, |
| 468 | { 0x1130d0, 0x0 }, | 468 | { 0x1130d0, 0x0 }, |
| 469 | { 0x2130d0, 0x0 }, | 469 | { 0x2130d0, 0x0 }, |
| 470 | { 0x131d0, 0x0 }, | 470 | { 0x131d0, 0x0 }, |
| 471 | { 0x1131d0, 0x0 }, | 471 | { 0x1131d0, 0x0 }, |
| 472 | { 0x2131d0, 0x0 }, | 472 | { 0x2131d0, 0x0 }, |
| 473 | { 0x100d1, 0x0 }, | 473 | { 0x100d1, 0x0 }, |
| 474 | { 0x1100d1, 0x0 }, | 474 | { 0x1100d1, 0x0 }, |
| 475 | { 0x2100d1, 0x0 }, | 475 | { 0x2100d1, 0x0 }, |
| 476 | { 0x101d1, 0x0 }, | 476 | { 0x101d1, 0x0 }, |
| 477 | { 0x1101d1, 0x0 }, | 477 | { 0x1101d1, 0x0 }, |
| 478 | { 0x2101d1, 0x0 }, | 478 | { 0x2101d1, 0x0 }, |
| 479 | { 0x110d1, 0x0 }, | 479 | { 0x110d1, 0x0 }, |
| 480 | { 0x1110d1, 0x0 }, | 480 | { 0x1110d1, 0x0 }, |
| 481 | { 0x2110d1, 0x0 }, | 481 | { 0x2110d1, 0x0 }, |
| 482 | { 0x111d1, 0x0 }, | 482 | { 0x111d1, 0x0 }, |
| 483 | { 0x1111d1, 0x0 }, | 483 | { 0x1111d1, 0x0 }, |
| 484 | { 0x2111d1, 0x0 }, | 484 | { 0x2111d1, 0x0 }, |
| 485 | { 0x120d1, 0x0 }, | 485 | { 0x120d1, 0x0 }, |
| 486 | { 0x1120d1, 0x0 }, | 486 | { 0x1120d1, 0x0 }, |
| 487 | { 0x2120d1, 0x0 }, | 487 | { 0x2120d1, 0x0 }, |
| 488 | { 0x121d1, 0x0 }, | 488 | { 0x121d1, 0x0 }, |
| 489 | { 0x1121d1, 0x0 }, | 489 | { 0x1121d1, 0x0 }, |
| 490 | { 0x2121d1, 0x0 }, | 490 | { 0x2121d1, 0x0 }, |
| 491 | { 0x130d1, 0x0 }, | 491 | { 0x130d1, 0x0 }, |
| 492 | { 0x1130d1, 0x0 }, | 492 | { 0x1130d1, 0x0 }, |
| 493 | { 0x2130d1, 0x0 }, | 493 | { 0x2130d1, 0x0 }, |
| 494 | { 0x131d1, 0x0 }, | 494 | { 0x131d1, 0x0 }, |
| 495 | { 0x1131d1, 0x0 }, | 495 | { 0x1131d1, 0x0 }, |
| 496 | { 0x2131d1, 0x0 }, | 496 | { 0x2131d1, 0x0 }, |
| 497 | { 0x10068, 0x0 }, | 497 | { 0x10068, 0x0 }, |
| 498 | { 0x10168, 0x0 }, | 498 | { 0x10168, 0x0 }, |
| 499 | { 0x10268, 0x0 }, | 499 | { 0x10268, 0x0 }, |
| 500 | { 0x10368, 0x0 }, | 500 | { 0x10368, 0x0 }, |
| 501 | { 0x10468, 0x0 }, | 501 | { 0x10468, 0x0 }, |
| 502 | { 0x10568, 0x0 }, | 502 | { 0x10568, 0x0 }, |
| 503 | { 0x10668, 0x0 }, | 503 | { 0x10668, 0x0 }, |
| 504 | { 0x10768, 0x0 }, | 504 | { 0x10768, 0x0 }, |
| 505 | { 0x10868, 0x0 }, | 505 | { 0x10868, 0x0 }, |
| 506 | { 0x11068, 0x0 }, | 506 | { 0x11068, 0x0 }, |
| 507 | { 0x11168, 0x0 }, | 507 | { 0x11168, 0x0 }, |
| 508 | { 0x11268, 0x0 }, | 508 | { 0x11268, 0x0 }, |
| 509 | { 0x11368, 0x0 }, | 509 | { 0x11368, 0x0 }, |
| 510 | { 0x11468, 0x0 }, | 510 | { 0x11468, 0x0 }, |
| 511 | { 0x11568, 0x0 }, | 511 | { 0x11568, 0x0 }, |
| 512 | { 0x11668, 0x0 }, | 512 | { 0x11668, 0x0 }, |
| 513 | { 0x11768, 0x0 }, | 513 | { 0x11768, 0x0 }, |
| 514 | { 0x11868, 0x0 }, | 514 | { 0x11868, 0x0 }, |
| 515 | { 0x12068, 0x0 }, | 515 | { 0x12068, 0x0 }, |
| 516 | { 0x12168, 0x0 }, | 516 | { 0x12168, 0x0 }, |
| 517 | { 0x12268, 0x0 }, | 517 | { 0x12268, 0x0 }, |
| 518 | { 0x12368, 0x0 }, | 518 | { 0x12368, 0x0 }, |
| 519 | { 0x12468, 0x0 }, | 519 | { 0x12468, 0x0 }, |
| 520 | { 0x12568, 0x0 }, | 520 | { 0x12568, 0x0 }, |
| 521 | { 0x12668, 0x0 }, | 521 | { 0x12668, 0x0 }, |
| 522 | { 0x12768, 0x0 }, | 522 | { 0x12768, 0x0 }, |
| 523 | { 0x12868, 0x0 }, | 523 | { 0x12868, 0x0 }, |
| 524 | { 0x13068, 0x0 }, | 524 | { 0x13068, 0x0 }, |
| 525 | { 0x13168, 0x0 }, | 525 | { 0x13168, 0x0 }, |
| 526 | { 0x13268, 0x0 }, | 526 | { 0x13268, 0x0 }, |
| 527 | { 0x13368, 0x0 }, | 527 | { 0x13368, 0x0 }, |
| 528 | { 0x13468, 0x0 }, | 528 | { 0x13468, 0x0 }, |
| 529 | { 0x13568, 0x0 }, | 529 | { 0x13568, 0x0 }, |
| 530 | { 0x13668, 0x0 }, | 530 | { 0x13668, 0x0 }, |
| 531 | { 0x13768, 0x0 }, | 531 | { 0x13768, 0x0 }, |
| 532 | { 0x13868, 0x0 }, | 532 | { 0x13868, 0x0 }, |
| 533 | { 0x10069, 0x0 }, | 533 | { 0x10069, 0x0 }, |
| 534 | { 0x10169, 0x0 }, | 534 | { 0x10169, 0x0 }, |
| 535 | { 0x10269, 0x0 }, | 535 | { 0x10269, 0x0 }, |
| 536 | { 0x10369, 0x0 }, | 536 | { 0x10369, 0x0 }, |
| 537 | { 0x10469, 0x0 }, | 537 | { 0x10469, 0x0 }, |
| 538 | { 0x10569, 0x0 }, | 538 | { 0x10569, 0x0 }, |
| 539 | { 0x10669, 0x0 }, | 539 | { 0x10669, 0x0 }, |
| 540 | { 0x10769, 0x0 }, | 540 | { 0x10769, 0x0 }, |
| 541 | { 0x10869, 0x0 }, | 541 | { 0x10869, 0x0 }, |
| 542 | { 0x11069, 0x0 }, | 542 | { 0x11069, 0x0 }, |
| 543 | { 0x11169, 0x0 }, | 543 | { 0x11169, 0x0 }, |
| 544 | { 0x11269, 0x0 }, | 544 | { 0x11269, 0x0 }, |
| 545 | { 0x11369, 0x0 }, | 545 | { 0x11369, 0x0 }, |
| 546 | { 0x11469, 0x0 }, | 546 | { 0x11469, 0x0 }, |
| 547 | { 0x11569, 0x0 }, | 547 | { 0x11569, 0x0 }, |
| 548 | { 0x11669, 0x0 }, | 548 | { 0x11669, 0x0 }, |
| 549 | { 0x11769, 0x0 }, | 549 | { 0x11769, 0x0 }, |
| 550 | { 0x11869, 0x0 }, | 550 | { 0x11869, 0x0 }, |
| 551 | { 0x12069, 0x0 }, | 551 | { 0x12069, 0x0 }, |
| 552 | { 0x12169, 0x0 }, | 552 | { 0x12169, 0x0 }, |
| 553 | { 0x12269, 0x0 }, | 553 | { 0x12269, 0x0 }, |
| 554 | { 0x12369, 0x0 }, | 554 | { 0x12369, 0x0 }, |
| 555 | { 0x12469, 0x0 }, | 555 | { 0x12469, 0x0 }, |
| 556 | { 0x12569, 0x0 }, | 556 | { 0x12569, 0x0 }, |
| 557 | { 0x12669, 0x0 }, | 557 | { 0x12669, 0x0 }, |
| 558 | { 0x12769, 0x0 }, | 558 | { 0x12769, 0x0 }, |
| 559 | { 0x12869, 0x0 }, | 559 | { 0x12869, 0x0 }, |
| 560 | { 0x13069, 0x0 }, | 560 | { 0x13069, 0x0 }, |
| 561 | { 0x13169, 0x0 }, | 561 | { 0x13169, 0x0 }, |
| 562 | { 0x13269, 0x0 }, | 562 | { 0x13269, 0x0 }, |
| 563 | { 0x13369, 0x0 }, | 563 | { 0x13369, 0x0 }, |
| 564 | { 0x13469, 0x0 }, | 564 | { 0x13469, 0x0 }, |
| 565 | { 0x13569, 0x0 }, | 565 | { 0x13569, 0x0 }, |
| 566 | { 0x13669, 0x0 }, | 566 | { 0x13669, 0x0 }, |
| 567 | { 0x13769, 0x0 }, | 567 | { 0x13769, 0x0 }, |
| 568 | { 0x13869, 0x0 }, | 568 | { 0x13869, 0x0 }, |
| 569 | { 0x1008c, 0x0 }, | 569 | { 0x1008c, 0x0 }, |
| 570 | { 0x11008c, 0x0 }, | 570 | { 0x11008c, 0x0 }, |
| 571 | { 0x21008c, 0x0 }, | 571 | { 0x21008c, 0x0 }, |
| 572 | { 0x1018c, 0x0 }, | 572 | { 0x1018c, 0x0 }, |
| 573 | { 0x11018c, 0x0 }, | 573 | { 0x11018c, 0x0 }, |
| 574 | { 0x21018c, 0x0 }, | 574 | { 0x21018c, 0x0 }, |
| 575 | { 0x1108c, 0x0 }, | 575 | { 0x1108c, 0x0 }, |
| 576 | { 0x11108c, 0x0 }, | 576 | { 0x11108c, 0x0 }, |
| 577 | { 0x21108c, 0x0 }, | 577 | { 0x21108c, 0x0 }, |
| 578 | { 0x1118c, 0x0 }, | 578 | { 0x1118c, 0x0 }, |
| 579 | { 0x11118c, 0x0 }, | 579 | { 0x11118c, 0x0 }, |
| 580 | { 0x21118c, 0x0 }, | 580 | { 0x21118c, 0x0 }, |
| 581 | { 0x1208c, 0x0 }, | 581 | { 0x1208c, 0x0 }, |
| 582 | { 0x11208c, 0x0 }, | 582 | { 0x11208c, 0x0 }, |
| 583 | { 0x21208c, 0x0 }, | 583 | { 0x21208c, 0x0 }, |
| 584 | { 0x1218c, 0x0 }, | 584 | { 0x1218c, 0x0 }, |
| 585 | { 0x11218c, 0x0 }, | 585 | { 0x11218c, 0x0 }, |
| 586 | { 0x21218c, 0x0 }, | 586 | { 0x21218c, 0x0 }, |
| 587 | { 0x1308c, 0x0 }, | 587 | { 0x1308c, 0x0 }, |
| 588 | { 0x11308c, 0x0 }, | 588 | { 0x11308c, 0x0 }, |
| 589 | { 0x21308c, 0x0 }, | 589 | { 0x21308c, 0x0 }, |
| 590 | { 0x1318c, 0x0 }, | 590 | { 0x1318c, 0x0 }, |
| 591 | { 0x11318c, 0x0 }, | 591 | { 0x11318c, 0x0 }, |
| 592 | { 0x21318c, 0x0 }, | 592 | { 0x21318c, 0x0 }, |
| 593 | { 0x1008d, 0x0 }, | 593 | { 0x1008d, 0x0 }, |
| 594 | { 0x11008d, 0x0 }, | 594 | { 0x11008d, 0x0 }, |
| 595 | { 0x21008d, 0x0 }, | 595 | { 0x21008d, 0x0 }, |
| 596 | { 0x1018d, 0x0 }, | 596 | { 0x1018d, 0x0 }, |
| 597 | { 0x11018d, 0x0 }, | 597 | { 0x11018d, 0x0 }, |
| 598 | { 0x21018d, 0x0 }, | 598 | { 0x21018d, 0x0 }, |
| 599 | { 0x1108d, 0x0 }, | 599 | { 0x1108d, 0x0 }, |
| 600 | { 0x11108d, 0x0 }, | 600 | { 0x11108d, 0x0 }, |
| 601 | { 0x21108d, 0x0 }, | 601 | { 0x21108d, 0x0 }, |
| 602 | { 0x1118d, 0x0 }, | 602 | { 0x1118d, 0x0 }, |
| 603 | { 0x11118d, 0x0 }, | 603 | { 0x11118d, 0x0 }, |
| 604 | { 0x21118d, 0x0 }, | 604 | { 0x21118d, 0x0 }, |
| 605 | { 0x1208d, 0x0 }, | 605 | { 0x1208d, 0x0 }, |
| 606 | { 0x11208d, 0x0 }, | 606 | { 0x11208d, 0x0 }, |
| 607 | { 0x21208d, 0x0 }, | 607 | { 0x21208d, 0x0 }, |
| 608 | { 0x1218d, 0x0 }, | 608 | { 0x1218d, 0x0 }, |
| 609 | { 0x11218d, 0x0 }, | 609 | { 0x11218d, 0x0 }, |
| 610 | { 0x21218d, 0x0 }, | 610 | { 0x21218d, 0x0 }, |
| 611 | { 0x1308d, 0x0 }, | 611 | { 0x1308d, 0x0 }, |
| 612 | { 0x11308d, 0x0 }, | 612 | { 0x11308d, 0x0 }, |
| 613 | { 0x21308d, 0x0 }, | 613 | { 0x21308d, 0x0 }, |
| 614 | { 0x1318d, 0x0 }, | 614 | { 0x1318d, 0x0 }, |
| 615 | { 0x11318d, 0x0 }, | 615 | { 0x11318d, 0x0 }, |
| 616 | { 0x21318d, 0x0 }, | 616 | { 0x21318d, 0x0 }, |
| 617 | { 0x100c0, 0x0 }, | 617 | { 0x100c0, 0x0 }, |
| 618 | { 0x1100c0, 0x0 }, | 618 | { 0x1100c0, 0x0 }, |
| 619 | { 0x2100c0, 0x0 }, | 619 | { 0x2100c0, 0x0 }, |
| 620 | { 0x101c0, 0x0 }, | 620 | { 0x101c0, 0x0 }, |
| 621 | { 0x1101c0, 0x0 }, | 621 | { 0x1101c0, 0x0 }, |
| 622 | { 0x2101c0, 0x0 }, | 622 | { 0x2101c0, 0x0 }, |
| 623 | { 0x102c0, 0x0 }, | 623 | { 0x102c0, 0x0 }, |
| 624 | { 0x1102c0, 0x0 }, | 624 | { 0x1102c0, 0x0 }, |
| 625 | { 0x2102c0, 0x0 }, | 625 | { 0x2102c0, 0x0 }, |
| 626 | { 0x103c0, 0x0 }, | 626 | { 0x103c0, 0x0 }, |
| 627 | { 0x1103c0, 0x0 }, | 627 | { 0x1103c0, 0x0 }, |
| 628 | { 0x2103c0, 0x0 }, | 628 | { 0x2103c0, 0x0 }, |
| 629 | { 0x104c0, 0x0 }, | 629 | { 0x104c0, 0x0 }, |
| 630 | { 0x1104c0, 0x0 }, | 630 | { 0x1104c0, 0x0 }, |
| 631 | { 0x2104c0, 0x0 }, | 631 | { 0x2104c0, 0x0 }, |
| 632 | { 0x105c0, 0x0 }, | 632 | { 0x105c0, 0x0 }, |
| 633 | { 0x1105c0, 0x0 }, | 633 | { 0x1105c0, 0x0 }, |
| 634 | { 0x2105c0, 0x0 }, | 634 | { 0x2105c0, 0x0 }, |
| 635 | { 0x106c0, 0x0 }, | 635 | { 0x106c0, 0x0 }, |
| 636 | { 0x1106c0, 0x0 }, | 636 | { 0x1106c0, 0x0 }, |
| 637 | { 0x2106c0, 0x0 }, | 637 | { 0x2106c0, 0x0 }, |
| 638 | { 0x107c0, 0x0 }, | 638 | { 0x107c0, 0x0 }, |
| 639 | { 0x1107c0, 0x0 }, | 639 | { 0x1107c0, 0x0 }, |
| 640 | { 0x2107c0, 0x0 }, | 640 | { 0x2107c0, 0x0 }, |
| 641 | { 0x108c0, 0x0 }, | 641 | { 0x108c0, 0x0 }, |
| 642 | { 0x1108c0, 0x0 }, | 642 | { 0x1108c0, 0x0 }, |
| 643 | { 0x2108c0, 0x0 }, | 643 | { 0x2108c0, 0x0 }, |
| 644 | { 0x110c0, 0x0 }, | 644 | { 0x110c0, 0x0 }, |
| 645 | { 0x1110c0, 0x0 }, | 645 | { 0x1110c0, 0x0 }, |
| 646 | { 0x2110c0, 0x0 }, | 646 | { 0x2110c0, 0x0 }, |
| 647 | { 0x111c0, 0x0 }, | 647 | { 0x111c0, 0x0 }, |
| 648 | { 0x1111c0, 0x0 }, | 648 | { 0x1111c0, 0x0 }, |
| 649 | { 0x2111c0, 0x0 }, | 649 | { 0x2111c0, 0x0 }, |
| 650 | { 0x112c0, 0x0 }, | 650 | { 0x112c0, 0x0 }, |
| 651 | { 0x1112c0, 0x0 }, | 651 | { 0x1112c0, 0x0 }, |
| 652 | { 0x2112c0, 0x0 }, | 652 | { 0x2112c0, 0x0 }, |
| 653 | { 0x113c0, 0x0 }, | 653 | { 0x113c0, 0x0 }, |
| 654 | { 0x1113c0, 0x0 }, | 654 | { 0x1113c0, 0x0 }, |
| 655 | { 0x2113c0, 0x0 }, | 655 | { 0x2113c0, 0x0 }, |
| 656 | { 0x114c0, 0x0 }, | 656 | { 0x114c0, 0x0 }, |
| 657 | { 0x1114c0, 0x0 }, | 657 | { 0x1114c0, 0x0 }, |
| 658 | { 0x2114c0, 0x0 }, | 658 | { 0x2114c0, 0x0 }, |
| 659 | { 0x115c0, 0x0 }, | 659 | { 0x115c0, 0x0 }, |
| 660 | { 0x1115c0, 0x0 }, | 660 | { 0x1115c0, 0x0 }, |
| 661 | { 0x2115c0, 0x0 }, | 661 | { 0x2115c0, 0x0 }, |
| 662 | { 0x116c0, 0x0 }, | 662 | { 0x116c0, 0x0 }, |
| 663 | { 0x1116c0, 0x0 }, | 663 | { 0x1116c0, 0x0 }, |
| 664 | { 0x2116c0, 0x0 }, | 664 | { 0x2116c0, 0x0 }, |
| 665 | { 0x117c0, 0x0 }, | 665 | { 0x117c0, 0x0 }, |
| 666 | { 0x1117c0, 0x0 }, | 666 | { 0x1117c0, 0x0 }, |
| 667 | { 0x2117c0, 0x0 }, | 667 | { 0x2117c0, 0x0 }, |
| 668 | { 0x118c0, 0x0 }, | 668 | { 0x118c0, 0x0 }, |
| 669 | { 0x1118c0, 0x0 }, | 669 | { 0x1118c0, 0x0 }, |
| 670 | { 0x2118c0, 0x0 }, | 670 | { 0x2118c0, 0x0 }, |
| 671 | { 0x120c0, 0x0 }, | 671 | { 0x120c0, 0x0 }, |
| 672 | { 0x1120c0, 0x0 }, | 672 | { 0x1120c0, 0x0 }, |
| 673 | { 0x2120c0, 0x0 }, | 673 | { 0x2120c0, 0x0 }, |
| 674 | { 0x121c0, 0x0 }, | 674 | { 0x121c0, 0x0 }, |
| 675 | { 0x1121c0, 0x0 }, | 675 | { 0x1121c0, 0x0 }, |
| 676 | { 0x2121c0, 0x0 }, | 676 | { 0x2121c0, 0x0 }, |
| 677 | { 0x122c0, 0x0 }, | 677 | { 0x122c0, 0x0 }, |
| 678 | { 0x1122c0, 0x0 }, | 678 | { 0x1122c0, 0x0 }, |
| 679 | { 0x2122c0, 0x0 }, | 679 | { 0x2122c0, 0x0 }, |
| 680 | { 0x123c0, 0x0 }, | 680 | { 0x123c0, 0x0 }, |
| 681 | { 0x1123c0, 0x0 }, | 681 | { 0x1123c0, 0x0 }, |
| 682 | { 0x2123c0, 0x0 }, | 682 | { 0x2123c0, 0x0 }, |
| 683 | { 0x124c0, 0x0 }, | 683 | { 0x124c0, 0x0 }, |
| 684 | { 0x1124c0, 0x0 }, | 684 | { 0x1124c0, 0x0 }, |
| 685 | { 0x2124c0, 0x0 }, | 685 | { 0x2124c0, 0x0 }, |
| 686 | { 0x125c0, 0x0 }, | 686 | { 0x125c0, 0x0 }, |
| 687 | { 0x1125c0, 0x0 }, | 687 | { 0x1125c0, 0x0 }, |
| 688 | { 0x2125c0, 0x0 }, | 688 | { 0x2125c0, 0x0 }, |
| 689 | { 0x126c0, 0x0 }, | 689 | { 0x126c0, 0x0 }, |
| 690 | { 0x1126c0, 0x0 }, | 690 | { 0x1126c0, 0x0 }, |
| 691 | { 0x2126c0, 0x0 }, | 691 | { 0x2126c0, 0x0 }, |
| 692 | { 0x127c0, 0x0 }, | 692 | { 0x127c0, 0x0 }, |
| 693 | { 0x1127c0, 0x0 }, | 693 | { 0x1127c0, 0x0 }, |
| 694 | { 0x2127c0, 0x0 }, | 694 | { 0x2127c0, 0x0 }, |
| 695 | { 0x128c0, 0x0 }, | 695 | { 0x128c0, 0x0 }, |
| 696 | { 0x1128c0, 0x0 }, | 696 | { 0x1128c0, 0x0 }, |
| 697 | { 0x2128c0, 0x0 }, | 697 | { 0x2128c0, 0x0 }, |
| 698 | { 0x130c0, 0x0 }, | 698 | { 0x130c0, 0x0 }, |
| 699 | { 0x1130c0, 0x0 }, | 699 | { 0x1130c0, 0x0 }, |
| 700 | { 0x2130c0, 0x0 }, | 700 | { 0x2130c0, 0x0 }, |
| 701 | { 0x131c0, 0x0 }, | 701 | { 0x131c0, 0x0 }, |
| 702 | { 0x1131c0, 0x0 }, | 702 | { 0x1131c0, 0x0 }, |
| 703 | { 0x2131c0, 0x0 }, | 703 | { 0x2131c0, 0x0 }, |
| 704 | { 0x132c0, 0x0 }, | 704 | { 0x132c0, 0x0 }, |
| 705 | { 0x1132c0, 0x0 }, | 705 | { 0x1132c0, 0x0 }, |
| 706 | { 0x2132c0, 0x0 }, | 706 | { 0x2132c0, 0x0 }, |
| 707 | { 0x133c0, 0x0 }, | 707 | { 0x133c0, 0x0 }, |
| 708 | { 0x1133c0, 0x0 }, | 708 | { 0x1133c0, 0x0 }, |
| 709 | { 0x2133c0, 0x0 }, | 709 | { 0x2133c0, 0x0 }, |
| 710 | { 0x134c0, 0x0 }, | 710 | { 0x134c0, 0x0 }, |
| 711 | { 0x1134c0, 0x0 }, | 711 | { 0x1134c0, 0x0 }, |
| 712 | { 0x2134c0, 0x0 }, | 712 | { 0x2134c0, 0x0 }, |
| 713 | { 0x135c0, 0x0 }, | 713 | { 0x135c0, 0x0 }, |
| 714 | { 0x1135c0, 0x0 }, | 714 | { 0x1135c0, 0x0 }, |
| 715 | { 0x2135c0, 0x0 }, | 715 | { 0x2135c0, 0x0 }, |
| 716 | { 0x136c0, 0x0 }, | 716 | { 0x136c0, 0x0 }, |
| 717 | { 0x1136c0, 0x0 }, | 717 | { 0x1136c0, 0x0 }, |
| 718 | { 0x2136c0, 0x0 }, | 718 | { 0x2136c0, 0x0 }, |
| 719 | { 0x137c0, 0x0 }, | 719 | { 0x137c0, 0x0 }, |
| 720 | { 0x1137c0, 0x0 }, | 720 | { 0x1137c0, 0x0 }, |
| 721 | { 0x2137c0, 0x0 }, | 721 | { 0x2137c0, 0x0 }, |
| 722 | { 0x138c0, 0x0 }, | 722 | { 0x138c0, 0x0 }, |
| 723 | { 0x1138c0, 0x0 }, | 723 | { 0x1138c0, 0x0 }, |
| 724 | { 0x2138c0, 0x0 }, | 724 | { 0x2138c0, 0x0 }, |
| 725 | { 0x100c1, 0x0 }, | 725 | { 0x100c1, 0x0 }, |
| 726 | { 0x1100c1, 0x0 }, | 726 | { 0x1100c1, 0x0 }, |
| 727 | { 0x2100c1, 0x0 }, | 727 | { 0x2100c1, 0x0 }, |
| 728 | { 0x101c1, 0x0 }, | 728 | { 0x101c1, 0x0 }, |
| 729 | { 0x1101c1, 0x0 }, | 729 | { 0x1101c1, 0x0 }, |
| 730 | { 0x2101c1, 0x0 }, | 730 | { 0x2101c1, 0x0 }, |
| 731 | { 0x102c1, 0x0 }, | 731 | { 0x102c1, 0x0 }, |
| 732 | { 0x1102c1, 0x0 }, | 732 | { 0x1102c1, 0x0 }, |
| 733 | { 0x2102c1, 0x0 }, | 733 | { 0x2102c1, 0x0 }, |
| 734 | { 0x103c1, 0x0 }, | 734 | { 0x103c1, 0x0 }, |
| 735 | { 0x1103c1, 0x0 }, | 735 | { 0x1103c1, 0x0 }, |
| 736 | { 0x2103c1, 0x0 }, | 736 | { 0x2103c1, 0x0 }, |
| 737 | { 0x104c1, 0x0 }, | 737 | { 0x104c1, 0x0 }, |
| 738 | { 0x1104c1, 0x0 }, | 738 | { 0x1104c1, 0x0 }, |
| 739 | { 0x2104c1, 0x0 }, | 739 | { 0x2104c1, 0x0 }, |
| 740 | { 0x105c1, 0x0 }, | 740 | { 0x105c1, 0x0 }, |
| 741 | { 0x1105c1, 0x0 }, | 741 | { 0x1105c1, 0x0 }, |
| 742 | { 0x2105c1, 0x0 }, | 742 | { 0x2105c1, 0x0 }, |
| 743 | { 0x106c1, 0x0 }, | 743 | { 0x106c1, 0x0 }, |
| 744 | { 0x1106c1, 0x0 }, | 744 | { 0x1106c1, 0x0 }, |
| 745 | { 0x2106c1, 0x0 }, | 745 | { 0x2106c1, 0x0 }, |
| 746 | { 0x107c1, 0x0 }, | 746 | { 0x107c1, 0x0 }, |
| 747 | { 0x1107c1, 0x0 }, | 747 | { 0x1107c1, 0x0 }, |
| 748 | { 0x2107c1, 0x0 }, | 748 | { 0x2107c1, 0x0 }, |
| 749 | { 0x108c1, 0x0 }, | 749 | { 0x108c1, 0x0 }, |
| 750 | { 0x1108c1, 0x0 }, | 750 | { 0x1108c1, 0x0 }, |
| 751 | { 0x2108c1, 0x0 }, | 751 | { 0x2108c1, 0x0 }, |
| 752 | { 0x110c1, 0x0 }, | 752 | { 0x110c1, 0x0 }, |
| 753 | { 0x1110c1, 0x0 }, | 753 | { 0x1110c1, 0x0 }, |
| 754 | { 0x2110c1, 0x0 }, | 754 | { 0x2110c1, 0x0 }, |
| 755 | { 0x111c1, 0x0 }, | 755 | { 0x111c1, 0x0 }, |
| 756 | { 0x1111c1, 0x0 }, | 756 | { 0x1111c1, 0x0 }, |
| 757 | { 0x2111c1, 0x0 }, | 757 | { 0x2111c1, 0x0 }, |
| 758 | { 0x112c1, 0x0 }, | 758 | { 0x112c1, 0x0 }, |
| 759 | { 0x1112c1, 0x0 }, | 759 | { 0x1112c1, 0x0 }, |
| 760 | { 0x2112c1, 0x0 }, | 760 | { 0x2112c1, 0x0 }, |
| 761 | { 0x113c1, 0x0 }, | 761 | { 0x113c1, 0x0 }, |
| 762 | { 0x1113c1, 0x0 }, | 762 | { 0x1113c1, 0x0 }, |
| 763 | { 0x2113c1, 0x0 }, | 763 | { 0x2113c1, 0x0 }, |
| 764 | { 0x114c1, 0x0 }, | 764 | { 0x114c1, 0x0 }, |
| 765 | { 0x1114c1, 0x0 }, | 765 | { 0x1114c1, 0x0 }, |
| 766 | { 0x2114c1, 0x0 }, | 766 | { 0x2114c1, 0x0 }, |
| 767 | { 0x115c1, 0x0 }, | 767 | { 0x115c1, 0x0 }, |
| 768 | { 0x1115c1, 0x0 }, | 768 | { 0x1115c1, 0x0 }, |
| 769 | { 0x2115c1, 0x0 }, | 769 | { 0x2115c1, 0x0 }, |
| 770 | { 0x116c1, 0x0 }, | 770 | { 0x116c1, 0x0 }, |
| 771 | { 0x1116c1, 0x0 }, | 771 | { 0x1116c1, 0x0 }, |
| 772 | { 0x2116c1, 0x0 }, | 772 | { 0x2116c1, 0x0 }, |
| 773 | { 0x117c1, 0x0 }, | 773 | { 0x117c1, 0x0 }, |
| 774 | { 0x1117c1, 0x0 }, | 774 | { 0x1117c1, 0x0 }, |
| 775 | { 0x2117c1, 0x0 }, | 775 | { 0x2117c1, 0x0 }, |
| 776 | { 0x118c1, 0x0 }, | 776 | { 0x118c1, 0x0 }, |
| 777 | { 0x1118c1, 0x0 }, | 777 | { 0x1118c1, 0x0 }, |
| 778 | { 0x2118c1, 0x0 }, | 778 | { 0x2118c1, 0x0 }, |
| 779 | { 0x120c1, 0x0 }, | 779 | { 0x120c1, 0x0 }, |
| 780 | { 0x1120c1, 0x0 }, | 780 | { 0x1120c1, 0x0 }, |
| 781 | { 0x2120c1, 0x0 }, | 781 | { 0x2120c1, 0x0 }, |
| 782 | { 0x121c1, 0x0 }, | 782 | { 0x121c1, 0x0 }, |
| 783 | { 0x1121c1, 0x0 }, | 783 | { 0x1121c1, 0x0 }, |
| 784 | { 0x2121c1, 0x0 }, | 784 | { 0x2121c1, 0x0 }, |
| 785 | { 0x122c1, 0x0 }, | 785 | { 0x122c1, 0x0 }, |
| 786 | { 0x1122c1, 0x0 }, | 786 | { 0x1122c1, 0x0 }, |
| 787 | { 0x2122c1, 0x0 }, | 787 | { 0x2122c1, 0x0 }, |
| 788 | { 0x123c1, 0x0 }, | 788 | { 0x123c1, 0x0 }, |
| 789 | { 0x1123c1, 0x0 }, | 789 | { 0x1123c1, 0x0 }, |
| 790 | { 0x2123c1, 0x0 }, | 790 | { 0x2123c1, 0x0 }, |
| 791 | { 0x124c1, 0x0 }, | 791 | { 0x124c1, 0x0 }, |
| 792 | { 0x1124c1, 0x0 }, | 792 | { 0x1124c1, 0x0 }, |
| 793 | { 0x2124c1, 0x0 }, | 793 | { 0x2124c1, 0x0 }, |
| 794 | { 0x125c1, 0x0 }, | 794 | { 0x125c1, 0x0 }, |
| 795 | { 0x1125c1, 0x0 }, | 795 | { 0x1125c1, 0x0 }, |
| 796 | { 0x2125c1, 0x0 }, | 796 | { 0x2125c1, 0x0 }, |
| 797 | { 0x126c1, 0x0 }, | 797 | { 0x126c1, 0x0 }, |
| 798 | { 0x1126c1, 0x0 }, | 798 | { 0x1126c1, 0x0 }, |
| 799 | { 0x2126c1, 0x0 }, | 799 | { 0x2126c1, 0x0 }, |
| 800 | { 0x127c1, 0x0 }, | 800 | { 0x127c1, 0x0 }, |
| 801 | { 0x1127c1, 0x0 }, | 801 | { 0x1127c1, 0x0 }, |
| 802 | { 0x2127c1, 0x0 }, | 802 | { 0x2127c1, 0x0 }, |
| 803 | { 0x128c1, 0x0 }, | 803 | { 0x128c1, 0x0 }, |
| 804 | { 0x1128c1, 0x0 }, | 804 | { 0x1128c1, 0x0 }, |
| 805 | { 0x2128c1, 0x0 }, | 805 | { 0x2128c1, 0x0 }, |
| 806 | { 0x130c1, 0x0 }, | 806 | { 0x130c1, 0x0 }, |
| 807 | { 0x1130c1, 0x0 }, | 807 | { 0x1130c1, 0x0 }, |
| 808 | { 0x2130c1, 0x0 }, | 808 | { 0x2130c1, 0x0 }, |
| 809 | { 0x131c1, 0x0 }, | 809 | { 0x131c1, 0x0 }, |
| 810 | { 0x1131c1, 0x0 }, | 810 | { 0x1131c1, 0x0 }, |
| 811 | { 0x2131c1, 0x0 }, | 811 | { 0x2131c1, 0x0 }, |
| 812 | { 0x132c1, 0x0 }, | 812 | { 0x132c1, 0x0 }, |
| 813 | { 0x1132c1, 0x0 }, | 813 | { 0x1132c1, 0x0 }, |
| 814 | { 0x2132c1, 0x0 }, | 814 | { 0x2132c1, 0x0 }, |
| 815 | { 0x133c1, 0x0 }, | 815 | { 0x133c1, 0x0 }, |
| 816 | { 0x1133c1, 0x0 }, | 816 | { 0x1133c1, 0x0 }, |
| 817 | { 0x2133c1, 0x0 }, | 817 | { 0x2133c1, 0x0 }, |
| 818 | { 0x134c1, 0x0 }, | 818 | { 0x134c1, 0x0 }, |
| 819 | { 0x1134c1, 0x0 }, | 819 | { 0x1134c1, 0x0 }, |
| 820 | { 0x2134c1, 0x0 }, | 820 | { 0x2134c1, 0x0 }, |
| 821 | { 0x135c1, 0x0 }, | 821 | { 0x135c1, 0x0 }, |
| 822 | { 0x1135c1, 0x0 }, | 822 | { 0x1135c1, 0x0 }, |
| 823 | { 0x2135c1, 0x0 }, | 823 | { 0x2135c1, 0x0 }, |
| 824 | { 0x136c1, 0x0 }, | 824 | { 0x136c1, 0x0 }, |
| 825 | { 0x1136c1, 0x0 }, | 825 | { 0x1136c1, 0x0 }, |
| 826 | { 0x2136c1, 0x0 }, | 826 | { 0x2136c1, 0x0 }, |
| 827 | { 0x137c1, 0x0 }, | 827 | { 0x137c1, 0x0 }, |
| 828 | { 0x1137c1, 0x0 }, | 828 | { 0x1137c1, 0x0 }, |
| 829 | { 0x2137c1, 0x0 }, | 829 | { 0x2137c1, 0x0 }, |
| 830 | { 0x138c1, 0x0 }, | 830 | { 0x138c1, 0x0 }, |
| 831 | { 0x1138c1, 0x0 }, | 831 | { 0x1138c1, 0x0 }, |
| 832 | { 0x2138c1, 0x0 }, | 832 | { 0x2138c1, 0x0 }, |
| 833 | { 0x10020, 0x0 }, | 833 | { 0x10020, 0x0 }, |
| 834 | { 0x110020, 0x0 }, | 834 | { 0x110020, 0x0 }, |
| 835 | { 0x210020, 0x0 }, | 835 | { 0x210020, 0x0 }, |
| 836 | { 0x11020, 0x0 }, | 836 | { 0x11020, 0x0 }, |
| 837 | { 0x111020, 0x0 }, | 837 | { 0x111020, 0x0 }, |
| 838 | { 0x211020, 0x0 }, | 838 | { 0x211020, 0x0 }, |
| 839 | { 0x12020, 0x0 }, | 839 | { 0x12020, 0x0 }, |
| 840 | { 0x112020, 0x0 }, | 840 | { 0x112020, 0x0 }, |
| 841 | { 0x212020, 0x0 }, | 841 | { 0x212020, 0x0 }, |
| 842 | { 0x13020, 0x0 }, | 842 | { 0x13020, 0x0 }, |
| 843 | { 0x113020, 0x0 }, | 843 | { 0x113020, 0x0 }, |
| 844 | { 0x213020, 0x0 }, | 844 | { 0x213020, 0x0 }, |
| 845 | { 0x20072, 0x0 }, | 845 | { 0x20072, 0x0 }, |
| 846 | { 0x20073, 0x0 }, | 846 | { 0x20073, 0x0 }, |
| 847 | { 0x20074, 0x0 }, | 847 | { 0x20074, 0x0 }, |
| 848 | { 0x100aa, 0x0 }, | 848 | { 0x100aa, 0x0 }, |
| 849 | { 0x110aa, 0x0 }, | 849 | { 0x110aa, 0x0 }, |
| 850 | { 0x120aa, 0x0 }, | 850 | { 0x120aa, 0x0 }, |
| 851 | { 0x130aa, 0x0 }, | 851 | { 0x130aa, 0x0 }, |
| 852 | { 0x20010, 0x0 }, | 852 | { 0x20010, 0x0 }, |
| 853 | { 0x120010, 0x0 }, | 853 | { 0x120010, 0x0 }, |
| 854 | { 0x220010, 0x0 }, | 854 | { 0x220010, 0x0 }, |
| 855 | { 0x20011, 0x0 }, | 855 | { 0x20011, 0x0 }, |
| 856 | { 0x120011, 0x0 }, | 856 | { 0x120011, 0x0 }, |
| 857 | { 0x220011, 0x0 }, | 857 | { 0x220011, 0x0 }, |
| 858 | { 0x100ae, 0x0 }, | 858 | { 0x100ae, 0x0 }, |
| 859 | { 0x1100ae, 0x0 }, | 859 | { 0x1100ae, 0x0 }, |
| 860 | { 0x2100ae, 0x0 }, | 860 | { 0x2100ae, 0x0 }, |
| 861 | { 0x100af, 0x0 }, | 861 | { 0x100af, 0x0 }, |
| 862 | { 0x1100af, 0x0 }, | 862 | { 0x1100af, 0x0 }, |
| 863 | { 0x2100af, 0x0 }, | 863 | { 0x2100af, 0x0 }, |
| 864 | { 0x110ae, 0x0 }, | 864 | { 0x110ae, 0x0 }, |
| 865 | { 0x1110ae, 0x0 }, | 865 | { 0x1110ae, 0x0 }, |
| 866 | { 0x2110ae, 0x0 }, | 866 | { 0x2110ae, 0x0 }, |
| 867 | { 0x110af, 0x0 }, | 867 | { 0x110af, 0x0 }, |
| 868 | { 0x1110af, 0x0 }, | 868 | { 0x1110af, 0x0 }, |
| 869 | { 0x2110af, 0x0 }, | 869 | { 0x2110af, 0x0 }, |
| 870 | { 0x120ae, 0x0 }, | 870 | { 0x120ae, 0x0 }, |
| 871 | { 0x1120ae, 0x0 }, | 871 | { 0x1120ae, 0x0 }, |
| 872 | { 0x2120ae, 0x0 }, | 872 | { 0x2120ae, 0x0 }, |
| 873 | { 0x120af, 0x0 }, | 873 | { 0x120af, 0x0 }, |
| 874 | { 0x1120af, 0x0 }, | 874 | { 0x1120af, 0x0 }, |
| 875 | { 0x2120af, 0x0 }, | 875 | { 0x2120af, 0x0 }, |
| 876 | { 0x130ae, 0x0 }, | 876 | { 0x130ae, 0x0 }, |
| 877 | { 0x1130ae, 0x0 }, | 877 | { 0x1130ae, 0x0 }, |
| 878 | { 0x2130ae, 0x0 }, | 878 | { 0x2130ae, 0x0 }, |
| 879 | { 0x130af, 0x0 }, | 879 | { 0x130af, 0x0 }, |
| 880 | { 0x1130af, 0x0 }, | 880 | { 0x1130af, 0x0 }, |
| 881 | { 0x2130af, 0x0 }, | 881 | { 0x2130af, 0x0 }, |
| 882 | { 0x20020, 0x0 }, | 882 | { 0x20020, 0x0 }, |
| 883 | { 0x120020, 0x0 }, | 883 | { 0x120020, 0x0 }, |
| 884 | { 0x220020, 0x0 }, | 884 | { 0x220020, 0x0 }, |
| 885 | { 0x100a0, 0x0 }, | 885 | { 0x100a0, 0x0 }, |
| 886 | { 0x100a1, 0x0 }, | 886 | { 0x100a1, 0x0 }, |
| 887 | { 0x100a2, 0x0 }, | 887 | { 0x100a2, 0x0 }, |
| 888 | { 0x100a3, 0x0 }, | 888 | { 0x100a3, 0x0 }, |
| 889 | { 0x100a4, 0x0 }, | 889 | { 0x100a4, 0x0 }, |
| 890 | { 0x100a5, 0x0 }, | 890 | { 0x100a5, 0x0 }, |
| 891 | { 0x100a6, 0x0 }, | 891 | { 0x100a6, 0x0 }, |
| 892 | { 0x100a7, 0x0 }, | 892 | { 0x100a7, 0x0 }, |
| 893 | { 0x110a0, 0x0 }, | 893 | { 0x110a0, 0x0 }, |
| 894 | { 0x110a1, 0x0 }, | 894 | { 0x110a1, 0x0 }, |
| 895 | { 0x110a2, 0x0 }, | 895 | { 0x110a2, 0x0 }, |
| 896 | { 0x110a3, 0x0 }, | 896 | { 0x110a3, 0x0 }, |
| 897 | { 0x110a4, 0x0 }, | 897 | { 0x110a4, 0x0 }, |
| 898 | { 0x110a5, 0x0 }, | 898 | { 0x110a5, 0x0 }, |
| 899 | { 0x110a6, 0x0 }, | 899 | { 0x110a6, 0x0 }, |
| 900 | { 0x110a7, 0x0 }, | 900 | { 0x110a7, 0x0 }, |
| 901 | { 0x120a0, 0x0 }, | 901 | { 0x120a0, 0x0 }, |
| 902 | { 0x120a1, 0x0 }, | 902 | { 0x120a1, 0x0 }, |
| 903 | { 0x120a2, 0x0 }, | 903 | { 0x120a2, 0x0 }, |
| 904 | { 0x120a3, 0x0 }, | 904 | { 0x120a3, 0x0 }, |
| 905 | { 0x120a4, 0x0 }, | 905 | { 0x120a4, 0x0 }, |
| 906 | { 0x120a5, 0x0 }, | 906 | { 0x120a5, 0x0 }, |
| 907 | { 0x120a6, 0x0 }, | 907 | { 0x120a6, 0x0 }, |
| 908 | { 0x120a7, 0x0 }, | 908 | { 0x120a7, 0x0 }, |
| 909 | { 0x130a0, 0x0 }, | 909 | { 0x130a0, 0x0 }, |
| 910 | { 0x130a1, 0x0 }, | 910 | { 0x130a1, 0x0 }, |
| 911 | { 0x130a2, 0x0 }, | 911 | { 0x130a2, 0x0 }, |
| 912 | { 0x130a3, 0x0 }, | 912 | { 0x130a3, 0x0 }, |
| 913 | { 0x130a4, 0x0 }, | 913 | { 0x130a4, 0x0 }, |
| 914 | { 0x130a5, 0x0 }, | 914 | { 0x130a5, 0x0 }, |
| 915 | { 0x130a6, 0x0 }, | 915 | { 0x130a6, 0x0 }, |
| 916 | { 0x130a7, 0x0 }, | 916 | { 0x130a7, 0x0 }, |
| 917 | { 0x2007c, 0x0 }, | 917 | { 0x2007c, 0x0 }, |
| 918 | { 0x12007c, 0x0 }, | 918 | { 0x12007c, 0x0 }, |
| 919 | { 0x22007c, 0x0 }, | 919 | { 0x22007c, 0x0 }, |
| 920 | { 0x2007d, 0x0 }, | 920 | { 0x2007d, 0x0 }, |
| 921 | { 0x12007d, 0x0 }, | 921 | { 0x12007d, 0x0 }, |
| 922 | { 0x22007d, 0x0 }, | 922 | { 0x22007d, 0x0 }, |
| 923 | { 0x400fd, 0x0 }, | 923 | { 0x400fd, 0x0 }, |
| 924 | { 0x400c0, 0x0 }, | 924 | { 0x400c0, 0x0 }, |
| 925 | { 0x90201, 0x0 }, | 925 | { 0x90201, 0x0 }, |
| 926 | { 0x190201, 0x0 }, | 926 | { 0x190201, 0x0 }, |
| 927 | { 0x290201, 0x0 }, | 927 | { 0x290201, 0x0 }, |
| 928 | { 0x90202, 0x0 }, | 928 | { 0x90202, 0x0 }, |
| 929 | { 0x190202, 0x0 }, | 929 | { 0x190202, 0x0 }, |
| 930 | { 0x290202, 0x0 }, | 930 | { 0x290202, 0x0 }, |
| 931 | { 0x90203, 0x0 }, | 931 | { 0x90203, 0x0 }, |
| 932 | { 0x190203, 0x0 }, | 932 | { 0x190203, 0x0 }, |
| 933 | { 0x290203, 0x0 }, | 933 | { 0x290203, 0x0 }, |
| 934 | { 0x90204, 0x0 }, | 934 | { 0x90204, 0x0 }, |
| 935 | { 0x190204, 0x0 }, | 935 | { 0x190204, 0x0 }, |
| 936 | { 0x290204, 0x0 }, | 936 | { 0x290204, 0x0 }, |
| 937 | { 0x90205, 0x0 }, | 937 | { 0x90205, 0x0 }, |
| 938 | { 0x190205, 0x0 }, | 938 | { 0x190205, 0x0 }, |
| 939 | { 0x290205, 0x0 }, | 939 | { 0x290205, 0x0 }, |
| 940 | { 0x90206, 0x0 }, | 940 | { 0x90206, 0x0 }, |
| 941 | { 0x190206, 0x0 }, | 941 | { 0x190206, 0x0 }, |
| 942 | { 0x290206, 0x0 }, | 942 | { 0x290206, 0x0 }, |
| 943 | { 0x90207, 0x0 }, | 943 | { 0x90207, 0x0 }, |
| 944 | { 0x190207, 0x0 }, | 944 | { 0x190207, 0x0 }, |
| 945 | { 0x290207, 0x0 }, | 945 | { 0x290207, 0x0 }, |
| 946 | { 0x90208, 0x0 }, | 946 | { 0x90208, 0x0 }, |
| 947 | { 0x190208, 0x0 }, | 947 | { 0x190208, 0x0 }, |
| 948 | { 0x290208, 0x0 }, | 948 | { 0x290208, 0x0 }, |
| 949 | { 0x10062, 0x0 }, | 949 | { 0x10062, 0x0 }, |
| 950 | { 0x10162, 0x0 }, | 950 | { 0x10162, 0x0 }, |
| 951 | { 0x10262, 0x0 }, | 951 | { 0x10262, 0x0 }, |
| 952 | { 0x10362, 0x0 }, | 952 | { 0x10362, 0x0 }, |
| 953 | { 0x10462, 0x0 }, | 953 | { 0x10462, 0x0 }, |
| 954 | { 0x10562, 0x0 }, | 954 | { 0x10562, 0x0 }, |
| 955 | { 0x10662, 0x0 }, | 955 | { 0x10662, 0x0 }, |
| 956 | { 0x10762, 0x0 }, | 956 | { 0x10762, 0x0 }, |
| 957 | { 0x10862, 0x0 }, | 957 | { 0x10862, 0x0 }, |
| 958 | { 0x11062, 0x0 }, | 958 | { 0x11062, 0x0 }, |
| 959 | { 0x11162, 0x0 }, | 959 | { 0x11162, 0x0 }, |
| 960 | { 0x11262, 0x0 }, | 960 | { 0x11262, 0x0 }, |
| 961 | { 0x11362, 0x0 }, | 961 | { 0x11362, 0x0 }, |
| 962 | { 0x11462, 0x0 }, | 962 | { 0x11462, 0x0 }, |
| 963 | { 0x11562, 0x0 }, | 963 | { 0x11562, 0x0 }, |
| 964 | { 0x11662, 0x0 }, | 964 | { 0x11662, 0x0 }, |
| 965 | { 0x11762, 0x0 }, | 965 | { 0x11762, 0x0 }, |
| 966 | { 0x11862, 0x0 }, | 966 | { 0x11862, 0x0 }, |
| 967 | { 0x12062, 0x0 }, | 967 | { 0x12062, 0x0 }, |
| 968 | { 0x12162, 0x0 }, | 968 | { 0x12162, 0x0 }, |
| 969 | { 0x12262, 0x0 }, | 969 | { 0x12262, 0x0 }, |
| 970 | { 0x12362, 0x0 }, | 970 | { 0x12362, 0x0 }, |
| 971 | { 0x12462, 0x0 }, | 971 | { 0x12462, 0x0 }, |
| 972 | { 0x12562, 0x0 }, | 972 | { 0x12562, 0x0 }, |
| 973 | { 0x12662, 0x0 }, | 973 | { 0x12662, 0x0 }, |
| 974 | { 0x12762, 0x0 }, | 974 | { 0x12762, 0x0 }, |
| 975 | { 0x12862, 0x0 }, | 975 | { 0x12862, 0x0 }, |
| 976 | { 0x13062, 0x0 }, | 976 | { 0x13062, 0x0 }, |
| 977 | { 0x13162, 0x0 }, | 977 | { 0x13162, 0x0 }, |
| 978 | { 0x13262, 0x0 }, | 978 | { 0x13262, 0x0 }, |
| 979 | { 0x13362, 0x0 }, | 979 | { 0x13362, 0x0 }, |
| 980 | { 0x13462, 0x0 }, | 980 | { 0x13462, 0x0 }, |
| 981 | { 0x13562, 0x0 }, | 981 | { 0x13562, 0x0 }, |
| 982 | { 0x13662, 0x0 }, | 982 | { 0x13662, 0x0 }, |
| 983 | { 0x13762, 0x0 }, | 983 | { 0x13762, 0x0 }, |
| 984 | { 0x13862, 0x0 }, | 984 | { 0x13862, 0x0 }, |
| 985 | { 0x20077, 0x0 }, | 985 | { 0x20077, 0x0 }, |
| 986 | { 0x10001, 0x0 }, | 986 | { 0x10001, 0x0 }, |
| 987 | { 0x11001, 0x0 }, | 987 | { 0x11001, 0x0 }, |
| 988 | { 0x12001, 0x0 }, | 988 | { 0x12001, 0x0 }, |
| 989 | { 0x13001, 0x0 }, | 989 | { 0x13001, 0x0 }, |
| 990 | { 0x10040, 0x0 }, | 990 | { 0x10040, 0x0 }, |
| 991 | { 0x10140, 0x0 }, | 991 | { 0x10140, 0x0 }, |
| 992 | { 0x10240, 0x0 }, | 992 | { 0x10240, 0x0 }, |
| 993 | { 0x10340, 0x0 }, | 993 | { 0x10340, 0x0 }, |
| 994 | { 0x10440, 0x0 }, | 994 | { 0x10440, 0x0 }, |
| 995 | { 0x10540, 0x0 }, | 995 | { 0x10540, 0x0 }, |
| 996 | { 0x10640, 0x0 }, | 996 | { 0x10640, 0x0 }, |
| 997 | { 0x10740, 0x0 }, | 997 | { 0x10740, 0x0 }, |
| 998 | { 0x10840, 0x0 }, | 998 | { 0x10840, 0x0 }, |
| 999 | { 0x10030, 0x0 }, | 999 | { 0x10030, 0x0 }, |
| 1000 | { 0x10130, 0x0 }, | 1000 | { 0x10130, 0x0 }, |
| 1001 | { 0x10230, 0x0 }, | 1001 | { 0x10230, 0x0 }, |
| 1002 | { 0x10330, 0x0 }, | 1002 | { 0x10330, 0x0 }, |
| 1003 | { 0x10430, 0x0 }, | 1003 | { 0x10430, 0x0 }, |
| 1004 | { 0x10530, 0x0 }, | 1004 | { 0x10530, 0x0 }, |
| 1005 | { 0x10630, 0x0 }, | 1005 | { 0x10630, 0x0 }, |
| 1006 | { 0x10730, 0x0 }, | 1006 | { 0x10730, 0x0 }, |
| 1007 | { 0x10830, 0x0 }, | 1007 | { 0x10830, 0x0 }, |
| 1008 | { 0x11040, 0x0 }, | 1008 | { 0x11040, 0x0 }, |
| 1009 | { 0x11140, 0x0 }, | 1009 | { 0x11140, 0x0 }, |
| 1010 | { 0x11240, 0x0 }, | 1010 | { 0x11240, 0x0 }, |
| 1011 | { 0x11340, 0x0 }, | 1011 | { 0x11340, 0x0 }, |
| 1012 | { 0x11440, 0x0 }, | 1012 | { 0x11440, 0x0 }, |
| 1013 | { 0x11540, 0x0 }, | 1013 | { 0x11540, 0x0 }, |
| 1014 | { 0x11640, 0x0 }, | 1014 | { 0x11640, 0x0 }, |
| 1015 | { 0x11740, 0x0 }, | 1015 | { 0x11740, 0x0 }, |
| 1016 | { 0x11840, 0x0 }, | 1016 | { 0x11840, 0x0 }, |
| 1017 | { 0x11030, 0x0 }, | 1017 | { 0x11030, 0x0 }, |
| 1018 | { 0x11130, 0x0 }, | 1018 | { 0x11130, 0x0 }, |
| 1019 | { 0x11230, 0x0 }, | 1019 | { 0x11230, 0x0 }, |
| 1020 | { 0x11330, 0x0 }, | 1020 | { 0x11330, 0x0 }, |
| 1021 | { 0x11430, 0x0 }, | 1021 | { 0x11430, 0x0 }, |
| 1022 | { 0x11530, 0x0 }, | 1022 | { 0x11530, 0x0 }, |
| 1023 | { 0x11630, 0x0 }, | 1023 | { 0x11630, 0x0 }, |
| 1024 | { 0x11730, 0x0 }, | 1024 | { 0x11730, 0x0 }, |
| 1025 | { 0x11830, 0x0 }, | 1025 | { 0x11830, 0x0 }, |
| 1026 | { 0x12040, 0x0 }, | 1026 | { 0x12040, 0x0 }, |
| 1027 | { 0x12140, 0x0 }, | 1027 | { 0x12140, 0x0 }, |
| 1028 | { 0x12240, 0x0 }, | 1028 | { 0x12240, 0x0 }, |
| 1029 | { 0x12340, 0x0 }, | 1029 | { 0x12340, 0x0 }, |
| 1030 | { 0x12440, 0x0 }, | 1030 | { 0x12440, 0x0 }, |
| 1031 | { 0x12540, 0x0 }, | 1031 | { 0x12540, 0x0 }, |
| 1032 | { 0x12640, 0x0 }, | 1032 | { 0x12640, 0x0 }, |
| 1033 | { 0x12740, 0x0 }, | 1033 | { 0x12740, 0x0 }, |
| 1034 | { 0x12840, 0x0 }, | 1034 | { 0x12840, 0x0 }, |
| 1035 | { 0x12030, 0x0 }, | 1035 | { 0x12030, 0x0 }, |
| 1036 | { 0x12130, 0x0 }, | 1036 | { 0x12130, 0x0 }, |
| 1037 | { 0x12230, 0x0 }, | 1037 | { 0x12230, 0x0 }, |
| 1038 | { 0x12330, 0x0 }, | 1038 | { 0x12330, 0x0 }, |
| 1039 | { 0x12430, 0x0 }, | 1039 | { 0x12430, 0x0 }, |
| 1040 | { 0x12530, 0x0 }, | 1040 | { 0x12530, 0x0 }, |
| 1041 | { 0x12630, 0x0 }, | 1041 | { 0x12630, 0x0 }, |
| 1042 | { 0x12730, 0x0 }, | 1042 | { 0x12730, 0x0 }, |
| 1043 | { 0x12830, 0x0 }, | 1043 | { 0x12830, 0x0 }, |
| 1044 | { 0x13040, 0x0 }, | 1044 | { 0x13040, 0x0 }, |
| 1045 | { 0x13140, 0x0 }, | 1045 | { 0x13140, 0x0 }, |
| 1046 | { 0x13240, 0x0 }, | 1046 | { 0x13240, 0x0 }, |
| 1047 | { 0x13340, 0x0 }, | 1047 | { 0x13340, 0x0 }, |
| 1048 | { 0x13440, 0x0 }, | 1048 | { 0x13440, 0x0 }, |
| 1049 | { 0x13540, 0x0 }, | 1049 | { 0x13540, 0x0 }, |
| 1050 | { 0x13640, 0x0 }, | 1050 | { 0x13640, 0x0 }, |
| 1051 | { 0x13740, 0x0 }, | 1051 | { 0x13740, 0x0 }, |
| 1052 | { 0x13840, 0x0 }, | 1052 | { 0x13840, 0x0 }, |
| 1053 | { 0x13030, 0x0 }, | 1053 | { 0x13030, 0x0 }, |
| 1054 | { 0x13130, 0x0 }, | 1054 | { 0x13130, 0x0 }, |
| 1055 | { 0x13230, 0x0 }, | 1055 | { 0x13230, 0x0 }, |
| 1056 | { 0x13330, 0x0 }, | 1056 | { 0x13330, 0x0 }, |
| 1057 | { 0x13430, 0x0 }, | 1057 | { 0x13430, 0x0 }, |
| 1058 | { 0x13530, 0x0 }, | 1058 | { 0x13530, 0x0 }, |
| 1059 | { 0x13630, 0x0 }, | 1059 | { 0x13630, 0x0 }, |
| 1060 | { 0x13730, 0x0 }, | 1060 | { 0x13730, 0x0 }, |
| 1061 | { 0x13830, 0x0 }, | 1061 | { 0x13830, 0x0 }, |
| 1062 | }; | 1062 | }; |
| 1063 | /* P0 message block paremeter for training firmware */ | 1063 | /* P0 message block paremeter for training firmware */ |
| 1064 | struct dram_cfg_param ddr_fsp0_cfg[] = { | 1064 | struct dram_cfg_param ddr_fsp0_cfg[] = { |
| 1065 | { 0xd0000, 0x0 }, | 1065 | { 0xd0000, 0x0 }, |
| 1066 | { 0x54003, 0xfa0 }, | 1066 | { 0x54003, 0xfa0 }, |
| 1067 | { 0x54004, 0x2 }, | 1067 | { 0x54004, 0x2 }, |
| 1068 | { 0x54005, 0x2228 }, | 1068 | { 0x54005, 0x2228 }, |
| 1069 | { 0x54006, 0x14 }, | 1069 | { 0x54006, 0x14 }, |
| 1070 | { 0x54008, 0x131f }, | 1070 | { 0x54008, 0x131f }, |
| 1071 | { 0x54009, 0xc8 }, | 1071 | { 0x54009, 0xc8 }, |
| 1072 | { 0x5400b, 0x2 }, | 1072 | { 0x5400b, 0x2 }, |
| 1073 | { 0x5400f, 0x100 }, | 1073 | { 0x5400f, 0x100 }, |
| 1074 | { 0x54012, 0x310 }, | 1074 | { 0x54012, 0x310 }, |
| 1075 | { 0x54019, 0x3ff4 }, | 1075 | { 0x54019, 0x3ff4 }, |
| 1076 | { 0x5401a, 0x33 }, | 1076 | { 0x5401a, 0x33 }, |
| 1077 | { 0x5401b, 0x4866 }, | 1077 | { 0x5401b, 0x4866 }, |
| 1078 | { 0x5401c, 0x4800 }, | 1078 | { 0x5401c, 0x4800 }, |
| 1079 | { 0x5401e, 0x16 }, | 1079 | { 0x5401e, 0x16 }, |
| 1080 | { 0x5401f, 0x3ff4 }, | 1080 | { 0x5401f, 0x3ff4 }, |
| 1081 | { 0x54020, 0x33 }, | 1081 | { 0x54020, 0x33 }, |
| 1082 | { 0x54021, 0x4866 }, | 1082 | { 0x54021, 0x4866 }, |
| 1083 | { 0x54022, 0x4800 }, | 1083 | { 0x54022, 0x4800 }, |
| 1084 | { 0x54024, 0x16 }, | 1084 | { 0x54024, 0x16 }, |
| 1085 | { 0x5402b, 0x1000 }, | 1085 | { 0x5402b, 0x1000 }, |
| 1086 | { 0x5402c, 0x3 }, | 1086 | { 0x5402c, 0x3 }, |
| 1087 | { 0x54032, 0xf400 }, | 1087 | { 0x54032, 0xf400 }, |
| 1088 | { 0x54033, 0x333f }, | 1088 | { 0x54033, 0x333f }, |
| 1089 | { 0x54034, 0x6600 }, | 1089 | { 0x54034, 0x6600 }, |
| 1090 | { 0x54035, 0x48 }, | 1090 | { 0x54035, 0x48 }, |
| 1091 | { 0x54036, 0x48 }, | 1091 | { 0x54036, 0x48 }, |
| 1092 | { 0x54037, 0x1600 }, | 1092 | { 0x54037, 0x1600 }, |
| 1093 | { 0x54038, 0xf400 }, | 1093 | { 0x54038, 0xf400 }, |
| 1094 | { 0x54039, 0x333f }, | 1094 | { 0x54039, 0x333f }, |
| 1095 | { 0x5403a, 0x6600 }, | 1095 | { 0x5403a, 0x6600 }, |
| 1096 | { 0x5403b, 0x48 }, | 1096 | { 0x5403b, 0x48 }, |
| 1097 | { 0x5403c, 0x48 }, | 1097 | { 0x5403c, 0x48 }, |
| 1098 | { 0x5403d, 0x1600 }, | 1098 | { 0x5403d, 0x1600 }, |
| 1099 | { 0xd0000, 0x1 }, | 1099 | { 0xd0000, 0x1 }, |
| 1100 | }; | 1100 | }; |
| 1101 | 1101 | ||
| 1102 | 1102 | ||
| 1103 | /* P1 message block paremeter for training firmware */ | 1103 | /* P1 message block paremeter for training firmware */ |
| 1104 | struct dram_cfg_param ddr_fsp1_cfg[] = { | 1104 | struct dram_cfg_param ddr_fsp1_cfg[] = { |
| 1105 | { 0xd0000, 0x0 }, | 1105 | { 0xd0000, 0x0 }, |
| 1106 | { 0x54002, 0x101 }, | 1106 | { 0x54002, 0x101 }, |
| 1107 | { 0x54003, 0x190 }, | 1107 | { 0x54003, 0x190 }, |
| 1108 | { 0x54004, 0x2 }, | 1108 | { 0x54004, 0x2 }, |
| 1109 | { 0x54005, 0x2228 }, | 1109 | { 0x54005, 0x2228 }, |
| 1110 | { 0x54006, 0x14 }, | 1110 | { 0x54006, 0x14 }, |
| 1111 | { 0x54008, 0x121f }, | 1111 | { 0x54008, 0x121f }, |
| 1112 | { 0x54009, 0xc8 }, | 1112 | { 0x54009, 0xc8 }, |
| 1113 | { 0x5400b, 0x2 }, | 1113 | { 0x5400b, 0x2 }, |
| 1114 | { 0x5400f, 0x100 }, | 1114 | { 0x5400f, 0x100 }, |
| 1115 | { 0x54012, 0x310 }, | 1115 | { 0x54012, 0x310 }, |
| 1116 | { 0x54019, 0x84 }, | 1116 | { 0x54019, 0x84 }, |
| 1117 | { 0x5401a, 0x33 }, | 1117 | { 0x5401a, 0x33 }, |
| 1118 | { 0x5401b, 0x4866 }, | 1118 | { 0x5401b, 0x4866 }, |
| 1119 | { 0x5401c, 0x4800 }, | 1119 | { 0x5401c, 0x4800 }, |
| 1120 | { 0x5401e, 0x16 }, | 1120 | { 0x5401e, 0x16 }, |
| 1121 | { 0x5401f, 0x84 }, | 1121 | { 0x5401f, 0x84 }, |
| 1122 | { 0x54020, 0x33 }, | 1122 | { 0x54020, 0x33 }, |
| 1123 | { 0x54021, 0x4866 }, | 1123 | { 0x54021, 0x4866 }, |
| 1124 | { 0x54022, 0x4800 }, | 1124 | { 0x54022, 0x4800 }, |
| 1125 | { 0x54024, 0x16 }, | 1125 | { 0x54024, 0x16 }, |
| 1126 | { 0x5402b, 0x1000 }, | 1126 | { 0x5402b, 0x1000 }, |
| 1127 | { 0x5402c, 0x3 }, | 1127 | { 0x5402c, 0x3 }, |
| 1128 | { 0x54032, 0x8400 }, | 1128 | { 0x54032, 0x8400 }, |
| 1129 | { 0x54033, 0x3300 }, | 1129 | { 0x54033, 0x3300 }, |
| 1130 | { 0x54034, 0x6600 }, | 1130 | { 0x54034, 0x6600 }, |
| 1131 | { 0x54035, 0x48 }, | 1131 | { 0x54035, 0x48 }, |
| 1132 | { 0x54036, 0x48 }, | 1132 | { 0x54036, 0x48 }, |
| 1133 | { 0x54037, 0x1600 }, | 1133 | { 0x54037, 0x1600 }, |
| 1134 | { 0x54038, 0x8400 }, | 1134 | { 0x54038, 0x8400 }, |
| 1135 | { 0x54039, 0x3300 }, | 1135 | { 0x54039, 0x3300 }, |
| 1136 | { 0x5403a, 0x6600 }, | 1136 | { 0x5403a, 0x6600 }, |
| 1137 | { 0x5403b, 0x48 }, | 1137 | { 0x5403b, 0x48 }, |
| 1138 | { 0x5403c, 0x48 }, | 1138 | { 0x5403c, 0x48 }, |
| 1139 | { 0x5403d, 0x1600 }, | 1139 | { 0x5403d, 0x1600 }, |
| 1140 | { 0xd0000, 0x1 }, | 1140 | { 0xd0000, 0x1 }, |
| 1141 | }; | 1141 | }; |
| 1142 | 1142 | ||
| 1143 | 1143 | ||
| 1144 | /* P2 message block paremeter for training firmware */ | 1144 | /* P2 message block paremeter for training firmware */ |
| 1145 | struct dram_cfg_param ddr_fsp2_cfg[] = { | 1145 | struct dram_cfg_param ddr_fsp2_cfg[] = { |
| 1146 | { 0xd0000, 0x0 }, | 1146 | { 0xd0000, 0x0 }, |
| 1147 | { 0x54002, 0x102 }, | 1147 | { 0x54002, 0x102 }, |
| 1148 | { 0x54003, 0x64 }, | 1148 | { 0x54003, 0x64 }, |
| 1149 | { 0x54004, 0x2 }, | 1149 | { 0x54004, 0x2 }, |
| 1150 | { 0x54005, 0x2228 }, | 1150 | { 0x54005, 0x2228 }, |
| 1151 | { 0x54006, 0x14 }, | 1151 | { 0x54006, 0x14 }, |
| 1152 | { 0x54008, 0x121f }, | 1152 | { 0x54008, 0x121f }, |
| 1153 | { 0x54009, 0xc8 }, | 1153 | { 0x54009, 0xc8 }, |
| 1154 | { 0x5400b, 0x2 }, | 1154 | { 0x5400b, 0x2 }, |
| 1155 | { 0x5400f, 0x100 }, | 1155 | { 0x5400f, 0x100 }, |
| 1156 | { 0x54012, 0x310 }, | 1156 | { 0x54012, 0x310 }, |
| 1157 | { 0x54019, 0x84 }, | 1157 | { 0x54019, 0x84 }, |
| 1158 | { 0x5401a, 0x33 }, | 1158 | { 0x5401a, 0x33 }, |
| 1159 | { 0x5401b, 0x4866 }, | 1159 | { 0x5401b, 0x4866 }, |
| 1160 | { 0x5401c, 0x4800 }, | 1160 | { 0x5401c, 0x4800 }, |
| 1161 | { 0x5401e, 0x16 }, | 1161 | { 0x5401e, 0x16 }, |
| 1162 | { 0x5401f, 0x84 }, | 1162 | { 0x5401f, 0x84 }, |
| 1163 | { 0x54020, 0x33 }, | 1163 | { 0x54020, 0x33 }, |
| 1164 | { 0x54021, 0x4866 }, | 1164 | { 0x54021, 0x4866 }, |
| 1165 | { 0x54022, 0x4800 }, | 1165 | { 0x54022, 0x4800 }, |
| 1166 | { 0x54024, 0x16 }, | 1166 | { 0x54024, 0x16 }, |
| 1167 | { 0x5402b, 0x1000 }, | 1167 | { 0x5402b, 0x1000 }, |
| 1168 | { 0x5402c, 0x3 }, | 1168 | { 0x5402c, 0x3 }, |
| 1169 | { 0x54032, 0x8400 }, | 1169 | { 0x54032, 0x8400 }, |
| 1170 | { 0x54033, 0x3300 }, | 1170 | { 0x54033, 0x3300 }, |
| 1171 | { 0x54034, 0x6600 }, | 1171 | { 0x54034, 0x6600 }, |
| 1172 | { 0x54035, 0x48 }, | 1172 | { 0x54035, 0x48 }, |
| 1173 | { 0x54036, 0x48 }, | 1173 | { 0x54036, 0x48 }, |
| 1174 | { 0x54037, 0x1600 }, | 1174 | { 0x54037, 0x1600 }, |
| 1175 | { 0x54038, 0x8400 }, | 1175 | { 0x54038, 0x8400 }, |
| 1176 | { 0x54039, 0x3300 }, | 1176 | { 0x54039, 0x3300 }, |
| 1177 | { 0x5403a, 0x6600 }, | 1177 | { 0x5403a, 0x6600 }, |
| 1178 | { 0x5403b, 0x48 }, | 1178 | { 0x5403b, 0x48 }, |
| 1179 | { 0x5403c, 0x48 }, | 1179 | { 0x5403c, 0x48 }, |
| 1180 | { 0x5403d, 0x1600 }, | 1180 | { 0x5403d, 0x1600 }, |
| 1181 | { 0xd0000, 0x1 }, | 1181 | { 0xd0000, 0x1 }, |
| 1182 | }; | 1182 | }; |
| 1183 | 1183 | ||
| 1184 | 1184 | ||
| 1185 | /* P0 2D message block paremeter for training firmware */ | 1185 | /* P0 2D message block paremeter for training firmware */ |
| 1186 | struct dram_cfg_param ddr_fsp0_2d_cfg[] = { | 1186 | struct dram_cfg_param ddr_fsp0_2d_cfg[] = { |
| 1187 | { 0xd0000, 0x0 }, | 1187 | { 0xd0000, 0x0 }, |
| 1188 | { 0x54003, 0xfa0 }, | 1188 | { 0x54003, 0xfa0 }, |
| 1189 | { 0x54004, 0x2 }, | 1189 | { 0x54004, 0x2 }, |
| 1190 | { 0x54005, 0x2228 }, | 1190 | { 0x54005, 0x2228 }, |
| 1191 | { 0x54006, 0x14 }, | 1191 | { 0x54006, 0x14 }, |
| 1192 | { 0x54008, 0x61 }, | 1192 | { 0x54008, 0x61 }, |
| 1193 | { 0x54009, 0xc8 }, | 1193 | { 0x54009, 0xc8 }, |
| 1194 | { 0x5400b, 0x2 }, | 1194 | { 0x5400b, 0x2 }, |
| 1195 | { 0x5400f, 0x100 }, | 1195 | { 0x5400f, 0x100 }, |
| 1196 | { 0x54010, 0x1f7f }, | 1196 | { 0x54010, 0x1f7f }, |
| 1197 | { 0x54012, 0x310 }, | 1197 | { 0x54012, 0x310 }, |
| 1198 | { 0x54019, 0x3ff4 }, | 1198 | { 0x54019, 0x3ff4 }, |
| 1199 | { 0x5401a, 0x33 }, | 1199 | { 0x5401a, 0x33 }, |
| 1200 | { 0x5401b, 0x4866 }, | 1200 | { 0x5401b, 0x4866 }, |
| 1201 | { 0x5401c, 0x4800 }, | 1201 | { 0x5401c, 0x4800 }, |
| 1202 | { 0x5401e, 0x16 }, | 1202 | { 0x5401e, 0x16 }, |
| 1203 | { 0x5401f, 0x3ff4 }, | 1203 | { 0x5401f, 0x3ff4 }, |
| 1204 | { 0x54020, 0x33 }, | 1204 | { 0x54020, 0x33 }, |
| 1205 | { 0x54021, 0x4866 }, | 1205 | { 0x54021, 0x4866 }, |
| 1206 | { 0x54022, 0x4800 }, | 1206 | { 0x54022, 0x4800 }, |
| 1207 | { 0x54024, 0x16 }, | 1207 | { 0x54024, 0x16 }, |
| 1208 | { 0x5402b, 0x1000 }, | 1208 | { 0x5402b, 0x1000 }, |
| 1209 | { 0x5402c, 0x3 }, | 1209 | { 0x5402c, 0x3 }, |
| 1210 | { 0x54032, 0xf400 }, | 1210 | { 0x54032, 0xf400 }, |
| 1211 | { 0x54033, 0x333f }, | 1211 | { 0x54033, 0x333f }, |
| 1212 | { 0x54034, 0x6600 }, | 1212 | { 0x54034, 0x6600 }, |
| 1213 | { 0x54035, 0x48 }, | 1213 | { 0x54035, 0x48 }, |
| 1214 | { 0x54036, 0x48 }, | 1214 | { 0x54036, 0x48 }, |
| 1215 | { 0x54037, 0x1600 }, | 1215 | { 0x54037, 0x1600 }, |
| 1216 | { 0x54038, 0xf400 }, | 1216 | { 0x54038, 0xf400 }, |
| 1217 | { 0x54039, 0x333f }, | 1217 | { 0x54039, 0x333f }, |
| 1218 | { 0x5403a, 0x6600 }, | 1218 | { 0x5403a, 0x6600 }, |
| 1219 | { 0x5403b, 0x48 }, | 1219 | { 0x5403b, 0x48 }, |
| 1220 | { 0x5403c, 0x48 }, | 1220 | { 0x5403c, 0x48 }, |
| 1221 | { 0x5403d, 0x1600 }, | 1221 | { 0x5403d, 0x1600 }, |
| 1222 | { 0xd0000, 0x1 }, | 1222 | { 0xd0000, 0x1 }, |
| 1223 | }; | 1223 | }; |
| 1224 | 1224 | ||
| 1225 | /* DRAM PHY init engine image */ | 1225 | /* DRAM PHY init engine image */ |
| 1226 | struct dram_cfg_param ddr_phy_pie[] = { | 1226 | struct dram_cfg_param ddr_phy_pie[] = { |
| 1227 | { 0xd0000, 0x0 }, | 1227 | { 0xd0000, 0x0 }, |
| 1228 | { 0x90000, 0x10 }, | 1228 | { 0x90000, 0x10 }, |
| 1229 | { 0x90001, 0x400 }, | 1229 | { 0x90001, 0x400 }, |
| 1230 | { 0x90002, 0x10e }, | 1230 | { 0x90002, 0x10e }, |
| 1231 | { 0x90003, 0x0 }, | 1231 | { 0x90003, 0x0 }, |
| 1232 | { 0x90004, 0x0 }, | 1232 | { 0x90004, 0x0 }, |
| 1233 | { 0x90005, 0x8 }, | 1233 | { 0x90005, 0x8 }, |
| 1234 | { 0x90029, 0xb }, | 1234 | { 0x90029, 0xb }, |
| 1235 | { 0x9002a, 0x480 }, | 1235 | { 0x9002a, 0x480 }, |
| 1236 | { 0x9002b, 0x109 }, | 1236 | { 0x9002b, 0x109 }, |
| 1237 | { 0x9002c, 0x8 }, | 1237 | { 0x9002c, 0x8 }, |
| 1238 | { 0x9002d, 0x448 }, | 1238 | { 0x9002d, 0x448 }, |
| 1239 | { 0x9002e, 0x139 }, | 1239 | { 0x9002e, 0x139 }, |
| 1240 | { 0x9002f, 0x8 }, | 1240 | { 0x9002f, 0x8 }, |
| 1241 | { 0x90030, 0x478 }, | 1241 | { 0x90030, 0x478 }, |
| 1242 | { 0x90031, 0x109 }, | 1242 | { 0x90031, 0x109 }, |
| 1243 | { 0x90032, 0x0 }, | 1243 | { 0x90032, 0x0 }, |
| 1244 | { 0x90033, 0xe8 }, | 1244 | { 0x90033, 0xe8 }, |
| 1245 | { 0x90034, 0x109 }, | 1245 | { 0x90034, 0x109 }, |
| 1246 | { 0x90035, 0x2 }, | 1246 | { 0x90035, 0x2 }, |
| 1247 | { 0x90036, 0x10 }, | 1247 | { 0x90036, 0x10 }, |
| 1248 | { 0x90037, 0x139 }, | 1248 | { 0x90037, 0x139 }, |
| 1249 | { 0x90038, 0xb }, | 1249 | { 0x90038, 0xb }, |
| 1250 | { 0x90039, 0x7c0 }, | 1250 | { 0x90039, 0x7c0 }, |
| 1251 | { 0x9003a, 0x139 }, | 1251 | { 0x9003a, 0x139 }, |
| 1252 | { 0x9003b, 0x44 }, | 1252 | { 0x9003b, 0x44 }, |
| 1253 | { 0x9003c, 0x633 }, | 1253 | { 0x9003c, 0x633 }, |
| 1254 | { 0x9003d, 0x159 }, | 1254 | { 0x9003d, 0x159 }, |
| 1255 | { 0x9003e, 0x14f }, | 1255 | { 0x9003e, 0x14f }, |
| 1256 | { 0x9003f, 0x630 }, | 1256 | { 0x9003f, 0x630 }, |
| 1257 | { 0x90040, 0x159 }, | 1257 | { 0x90040, 0x159 }, |
| 1258 | { 0x90041, 0x47 }, | 1258 | { 0x90041, 0x47 }, |
| 1259 | { 0x90042, 0x633 }, | 1259 | { 0x90042, 0x633 }, |
| 1260 | { 0x90043, 0x149 }, | 1260 | { 0x90043, 0x149 }, |
| 1261 | { 0x90044, 0x4f }, | 1261 | { 0x90044, 0x4f }, |
| 1262 | { 0x90045, 0x633 }, | 1262 | { 0x90045, 0x633 }, |
| 1263 | { 0x90046, 0x179 }, | 1263 | { 0x90046, 0x179 }, |
| 1264 | { 0x90047, 0x8 }, | 1264 | { 0x90047, 0x8 }, |
| 1265 | { 0x90048, 0xe0 }, | 1265 | { 0x90048, 0xe0 }, |
| 1266 | { 0x90049, 0x109 }, | 1266 | { 0x90049, 0x109 }, |
| 1267 | { 0x9004a, 0x0 }, | 1267 | { 0x9004a, 0x0 }, |
| 1268 | { 0x9004b, 0x7c8 }, | 1268 | { 0x9004b, 0x7c8 }, |
| 1269 | { 0x9004c, 0x109 }, | 1269 | { 0x9004c, 0x109 }, |
| 1270 | { 0x9004d, 0x0 }, | 1270 | { 0x9004d, 0x0 }, |
| 1271 | { 0x9004e, 0x1 }, | 1271 | { 0x9004e, 0x1 }, |
| 1272 | { 0x9004f, 0x8 }, | 1272 | { 0x9004f, 0x8 }, |
| 1273 | { 0x90050, 0x0 }, | 1273 | { 0x90050, 0x0 }, |
| 1274 | { 0x90051, 0x45a }, | 1274 | { 0x90051, 0x45a }, |
| 1275 | { 0x90052, 0x9 }, | 1275 | { 0x90052, 0x9 }, |
| 1276 | { 0x90053, 0x0 }, | 1276 | { 0x90053, 0x0 }, |
| 1277 | { 0x90054, 0x448 }, | 1277 | { 0x90054, 0x448 }, |
| 1278 | { 0x90055, 0x109 }, | 1278 | { 0x90055, 0x109 }, |
| 1279 | { 0x90056, 0x40 }, | 1279 | { 0x90056, 0x40 }, |
| 1280 | { 0x90057, 0x633 }, | 1280 | { 0x90057, 0x633 }, |
| 1281 | { 0x90058, 0x179 }, | 1281 | { 0x90058, 0x179 }, |
| 1282 | { 0x90059, 0x1 }, | 1282 | { 0x90059, 0x1 }, |
| 1283 | { 0x9005a, 0x618 }, | 1283 | { 0x9005a, 0x618 }, |
| 1284 | { 0x9005b, 0x109 }, | 1284 | { 0x9005b, 0x109 }, |
| 1285 | { 0x9005c, 0x40c0 }, | 1285 | { 0x9005c, 0x40c0 }, |
| 1286 | { 0x9005d, 0x633 }, | 1286 | { 0x9005d, 0x633 }, |
| 1287 | { 0x9005e, 0x149 }, | 1287 | { 0x9005e, 0x149 }, |
| 1288 | { 0x9005f, 0x8 }, | 1288 | { 0x9005f, 0x8 }, |
| 1289 | { 0x90060, 0x4 }, | 1289 | { 0x90060, 0x4 }, |
| 1290 | { 0x90061, 0x48 }, | 1290 | { 0x90061, 0x48 }, |
| 1291 | { 0x90062, 0x4040 }, | 1291 | { 0x90062, 0x4040 }, |
| 1292 | { 0x90063, 0x633 }, | 1292 | { 0x90063, 0x633 }, |
| 1293 | { 0x90064, 0x149 }, | 1293 | { 0x90064, 0x149 }, |
| 1294 | { 0x90065, 0x0 }, | 1294 | { 0x90065, 0x0 }, |
| 1295 | { 0x90066, 0x4 }, | 1295 | { 0x90066, 0x4 }, |
| 1296 | { 0x90067, 0x48 }, | 1296 | { 0x90067, 0x48 }, |
| 1297 | { 0x90068, 0x40 }, | 1297 | { 0x90068, 0x40 }, |
| 1298 | { 0x90069, 0x633 }, | 1298 | { 0x90069, 0x633 }, |
| 1299 | { 0x9006a, 0x149 }, | 1299 | { 0x9006a, 0x149 }, |
| 1300 | { 0x9006b, 0x10 }, | 1300 | { 0x9006b, 0x10 }, |
| 1301 | { 0x9006c, 0x4 }, | 1301 | { 0x9006c, 0x4 }, |
| 1302 | { 0x9006d, 0x18 }, | 1302 | { 0x9006d, 0x18 }, |
| 1303 | { 0x9006e, 0x0 }, | 1303 | { 0x9006e, 0x0 }, |
| 1304 | { 0x9006f, 0x4 }, | 1304 | { 0x9006f, 0x4 }, |
| 1305 | { 0x90070, 0x78 }, | 1305 | { 0x90070, 0x78 }, |
| 1306 | { 0x90071, 0x549 }, | 1306 | { 0x90071, 0x549 }, |
| 1307 | { 0x90072, 0x633 }, | 1307 | { 0x90072, 0x633 }, |
| 1308 | { 0x90073, 0x159 }, | 1308 | { 0x90073, 0x159 }, |
| 1309 | { 0x90074, 0xd49 }, | 1309 | { 0x90074, 0xd49 }, |
| 1310 | { 0x90075, 0x633 }, | 1310 | { 0x90075, 0x633 }, |
| 1311 | { 0x90076, 0x159 }, | 1311 | { 0x90076, 0x159 }, |
| 1312 | { 0x90077, 0x94a }, | 1312 | { 0x90077, 0x94a }, |
| 1313 | { 0x90078, 0x633 }, | 1313 | { 0x90078, 0x633 }, |
| 1314 | { 0x90079, 0x159 }, | 1314 | { 0x90079, 0x159 }, |
| 1315 | { 0x9007a, 0x441 }, | 1315 | { 0x9007a, 0x441 }, |
| 1316 | { 0x9007b, 0x633 }, | 1316 | { 0x9007b, 0x633 }, |
| 1317 | { 0x9007c, 0x149 }, | 1317 | { 0x9007c, 0x149 }, |
| 1318 | { 0x9007d, 0x42 }, | 1318 | { 0x9007d, 0x42 }, |
| 1319 | { 0x9007e, 0x633 }, | 1319 | { 0x9007e, 0x633 }, |
| 1320 | { 0x9007f, 0x149 }, | 1320 | { 0x9007f, 0x149 }, |
| 1321 | { 0x90080, 0x1 }, | 1321 | { 0x90080, 0x1 }, |
| 1322 | { 0x90081, 0x633 }, | 1322 | { 0x90081, 0x633 }, |
| 1323 | { 0x90082, 0x149 }, | 1323 | { 0x90082, 0x149 }, |
| 1324 | { 0x90083, 0x0 }, | 1324 | { 0x90083, 0x0 }, |
| 1325 | { 0x90084, 0xe0 }, | 1325 | { 0x90084, 0xe0 }, |
| 1326 | { 0x90085, 0x109 }, | 1326 | { 0x90085, 0x109 }, |
| 1327 | { 0x90086, 0xa }, | 1327 | { 0x90086, 0xa }, |
| 1328 | { 0x90087, 0x10 }, | 1328 | { 0x90087, 0x10 }, |
| 1329 | { 0x90088, 0x109 }, | 1329 | { 0x90088, 0x109 }, |
| 1330 | { 0x90089, 0x9 }, | 1330 | { 0x90089, 0x9 }, |
| 1331 | { 0x9008a, 0x3c0 }, | 1331 | { 0x9008a, 0x3c0 }, |
| 1332 | { 0x9008b, 0x149 }, | 1332 | { 0x9008b, 0x149 }, |
| 1333 | { 0x9008c, 0x9 }, | 1333 | { 0x9008c, 0x9 }, |
| 1334 | { 0x9008d, 0x3c0 }, | 1334 | { 0x9008d, 0x3c0 }, |
| 1335 | { 0x9008e, 0x159 }, | 1335 | { 0x9008e, 0x159 }, |
| 1336 | { 0x9008f, 0x18 }, | 1336 | { 0x9008f, 0x18 }, |
| 1337 | { 0x90090, 0x10 }, | 1337 | { 0x90090, 0x10 }, |
| 1338 | { 0x90091, 0x109 }, | 1338 | { 0x90091, 0x109 }, |
| 1339 | { 0x90092, 0x0 }, | 1339 | { 0x90092, 0x0 }, |
| 1340 | { 0x90093, 0x3c0 }, | 1340 | { 0x90093, 0x3c0 }, |
| 1341 | { 0x90094, 0x109 }, | 1341 | { 0x90094, 0x109 }, |
| 1342 | { 0x90095, 0x18 }, | 1342 | { 0x90095, 0x18 }, |
| 1343 | { 0x90096, 0x4 }, | 1343 | { 0x90096, 0x4 }, |
| 1344 | { 0x90097, 0x48 }, | 1344 | { 0x90097, 0x48 }, |
| 1345 | { 0x90098, 0x18 }, | 1345 | { 0x90098, 0x18 }, |
| 1346 | { 0x90099, 0x4 }, | 1346 | { 0x90099, 0x4 }, |
| 1347 | { 0x9009a, 0x58 }, | 1347 | { 0x9009a, 0x58 }, |
| 1348 | { 0x9009b, 0xb }, | 1348 | { 0x9009b, 0xb }, |
| 1349 | { 0x9009c, 0x10 }, | 1349 | { 0x9009c, 0x10 }, |
| 1350 | { 0x9009d, 0x109 }, | 1350 | { 0x9009d, 0x109 }, |
| 1351 | { 0x9009e, 0x1 }, | 1351 | { 0x9009e, 0x1 }, |
| 1352 | { 0x9009f, 0x10 }, | 1352 | { 0x9009f, 0x10 }, |
| 1353 | { 0x900a0, 0x109 }, | 1353 | { 0x900a0, 0x109 }, |
| 1354 | { 0x900a1, 0x5 }, | 1354 | { 0x900a1, 0x5 }, |
| 1355 | { 0x900a2, 0x7c0 }, | 1355 | { 0x900a2, 0x7c0 }, |
| 1356 | { 0x900a3, 0x109 }, | 1356 | { 0x900a3, 0x109 }, |
| 1357 | { 0x40000, 0x811 }, | 1357 | { 0x40000, 0x811 }, |
| 1358 | { 0x40020, 0x880 }, | 1358 | { 0x40020, 0x880 }, |
| 1359 | { 0x40040, 0x0 }, | 1359 | { 0x40040, 0x0 }, |
| 1360 | { 0x40060, 0x0 }, | 1360 | { 0x40060, 0x0 }, |
| 1361 | { 0x40001, 0x4008 }, | 1361 | { 0x40001, 0x4008 }, |
| 1362 | { 0x40021, 0x83 }, | 1362 | { 0x40021, 0x83 }, |
| 1363 | { 0x40041, 0x4f }, | 1363 | { 0x40041, 0x4f }, |
| 1364 | { 0x40061, 0x0 }, | 1364 | { 0x40061, 0x0 }, |
| 1365 | { 0x40002, 0x4040 }, | 1365 | { 0x40002, 0x4040 }, |
| 1366 | { 0x40022, 0x83 }, | 1366 | { 0x40022, 0x83 }, |
| 1367 | { 0x40042, 0x51 }, | 1367 | { 0x40042, 0x51 }, |
| 1368 | { 0x40062, 0x0 }, | 1368 | { 0x40062, 0x0 }, |
| 1369 | { 0x40003, 0x811 }, | 1369 | { 0x40003, 0x811 }, |
| 1370 | { 0x40023, 0x880 }, | 1370 | { 0x40023, 0x880 }, |
| 1371 | { 0x40043, 0x0 }, | 1371 | { 0x40043, 0x0 }, |
| 1372 | { 0x40063, 0x0 }, | 1372 | { 0x40063, 0x0 }, |
| 1373 | { 0x40004, 0x720 }, | 1373 | { 0x40004, 0x720 }, |
| 1374 | { 0x40024, 0xf }, | 1374 | { 0x40024, 0xf }, |
| 1375 | { 0x40044, 0x1740 }, | 1375 | { 0x40044, 0x1740 }, |
| 1376 | { 0x40064, 0x0 }, | 1376 | { 0x40064, 0x0 }, |
| 1377 | { 0x40005, 0x16 }, | 1377 | { 0x40005, 0x16 }, |
| 1378 | { 0x40025, 0x83 }, | 1378 | { 0x40025, 0x83 }, |
| 1379 | { 0x40045, 0x4b }, | 1379 | { 0x40045, 0x4b }, |
| 1380 | { 0x40065, 0x0 }, | 1380 | { 0x40065, 0x0 }, |
| 1381 | { 0x40006, 0x716 }, | 1381 | { 0x40006, 0x716 }, |
| 1382 | { 0x40026, 0xf }, | 1382 | { 0x40026, 0xf }, |
| 1383 | { 0x40046, 0x2001 }, | 1383 | { 0x40046, 0x2001 }, |
| 1384 | { 0x40066, 0x0 }, | 1384 | { 0x40066, 0x0 }, |
| 1385 | { 0x40007, 0x716 }, | 1385 | { 0x40007, 0x716 }, |
| 1386 | { 0x40027, 0xf }, | 1386 | { 0x40027, 0xf }, |
| 1387 | { 0x40047, 0x2800 }, | 1387 | { 0x40047, 0x2800 }, |
| 1388 | { 0x40067, 0x0 }, | 1388 | { 0x40067, 0x0 }, |
| 1389 | { 0x40008, 0x716 }, | 1389 | { 0x40008, 0x716 }, |
| 1390 | { 0x40028, 0xf }, | 1390 | { 0x40028, 0xf }, |
| 1391 | { 0x40048, 0xf00 }, | 1391 | { 0x40048, 0xf00 }, |
| 1392 | { 0x40068, 0x0 }, | 1392 | { 0x40068, 0x0 }, |
| 1393 | { 0x40009, 0x720 }, | 1393 | { 0x40009, 0x720 }, |
| 1394 | { 0x40029, 0xf }, | 1394 | { 0x40029, 0xf }, |
| 1395 | { 0x40049, 0x1400 }, | 1395 | { 0x40049, 0x1400 }, |
| 1396 | { 0x40069, 0x0 }, | 1396 | { 0x40069, 0x0 }, |
| 1397 | { 0x4000a, 0xe08 }, | 1397 | { 0x4000a, 0xe08 }, |
| 1398 | { 0x4002a, 0xc15 }, | 1398 | { 0x4002a, 0xc15 }, |
| 1399 | { 0x4004a, 0x0 }, | 1399 | { 0x4004a, 0x0 }, |
| 1400 | { 0x4006a, 0x0 }, | 1400 | { 0x4006a, 0x0 }, |
| 1401 | { 0x4000b, 0x625 }, | 1401 | { 0x4000b, 0x625 }, |
| 1402 | { 0x4002b, 0x15 }, | 1402 | { 0x4002b, 0x15 }, |
| 1403 | { 0x4004b, 0x0 }, | 1403 | { 0x4004b, 0x0 }, |
| 1404 | { 0x4006b, 0x0 }, | 1404 | { 0x4006b, 0x0 }, |
| 1405 | { 0x4000c, 0x4028 }, | 1405 | { 0x4000c, 0x4028 }, |
| 1406 | { 0x4002c, 0x80 }, | 1406 | { 0x4002c, 0x80 }, |
| 1407 | { 0x4004c, 0x0 }, | 1407 | { 0x4004c, 0x0 }, |
| 1408 | { 0x4006c, 0x0 }, | 1408 | { 0x4006c, 0x0 }, |
| 1409 | { 0x4000d, 0xe08 }, | 1409 | { 0x4000d, 0xe08 }, |
| 1410 | { 0x4002d, 0xc1a }, | 1410 | { 0x4002d, 0xc1a }, |
| 1411 | { 0x4004d, 0x0 }, | 1411 | { 0x4004d, 0x0 }, |
| 1412 | { 0x4006d, 0x0 }, | 1412 | { 0x4006d, 0x0 }, |
| 1413 | { 0x4000e, 0x625 }, | 1413 | { 0x4000e, 0x625 }, |
| 1414 | { 0x4002e, 0x1a }, | 1414 | { 0x4002e, 0x1a }, |
| 1415 | { 0x4004e, 0x0 }, | 1415 | { 0x4004e, 0x0 }, |
| 1416 | { 0x4006e, 0x0 }, | 1416 | { 0x4006e, 0x0 }, |
| 1417 | { 0x4000f, 0x4040 }, | 1417 | { 0x4000f, 0x4040 }, |
| 1418 | { 0x4002f, 0x80 }, | 1418 | { 0x4002f, 0x80 }, |
| 1419 | { 0x4004f, 0x0 }, | 1419 | { 0x4004f, 0x0 }, |
| 1420 | { 0x4006f, 0x0 }, | 1420 | { 0x4006f, 0x0 }, |
| 1421 | { 0x40010, 0x2604 }, | 1421 | { 0x40010, 0x2604 }, |
| 1422 | { 0x40030, 0x15 }, | 1422 | { 0x40030, 0x15 }, |
| 1423 | { 0x40050, 0x0 }, | 1423 | { 0x40050, 0x0 }, |
| 1424 | { 0x40070, 0x0 }, | 1424 | { 0x40070, 0x0 }, |
| 1425 | { 0x40011, 0x708 }, | 1425 | { 0x40011, 0x708 }, |
| 1426 | { 0x40031, 0x5 }, | 1426 | { 0x40031, 0x5 }, |
| 1427 | { 0x40051, 0x0 }, | 1427 | { 0x40051, 0x0 }, |
| 1428 | { 0x40071, 0x2002 }, | 1428 | { 0x40071, 0x2002 }, |
| 1429 | { 0x40012, 0x8 }, | 1429 | { 0x40012, 0x8 }, |
| 1430 | { 0x40032, 0x80 }, | 1430 | { 0x40032, 0x80 }, |
| 1431 | { 0x40052, 0x0 }, | 1431 | { 0x40052, 0x0 }, |
| 1432 | { 0x40072, 0x0 }, | 1432 | { 0x40072, 0x0 }, |
| 1433 | { 0x40013, 0x2604 }, | 1433 | { 0x40013, 0x2604 }, |
| 1434 | { 0x40033, 0x1a }, | 1434 | { 0x40033, 0x1a }, |
| 1435 | { 0x40053, 0x0 }, | 1435 | { 0x40053, 0x0 }, |
| 1436 | { 0x40073, 0x0 }, | 1436 | { 0x40073, 0x0 }, |
| 1437 | { 0x40014, 0x708 }, | 1437 | { 0x40014, 0x708 }, |
| 1438 | { 0x40034, 0xa }, | 1438 | { 0x40034, 0xa }, |
| 1439 | { 0x40054, 0x0 }, | 1439 | { 0x40054, 0x0 }, |
| 1440 | { 0x40074, 0x2002 }, | 1440 | { 0x40074, 0x2002 }, |
| 1441 | { 0x40015, 0x4040 }, | 1441 | { 0x40015, 0x4040 }, |
| 1442 | { 0x40035, 0x80 }, | 1442 | { 0x40035, 0x80 }, |
| 1443 | { 0x40055, 0x0 }, | 1443 | { 0x40055, 0x0 }, |
| 1444 | { 0x40075, 0x0 }, | 1444 | { 0x40075, 0x0 }, |
| 1445 | { 0x40016, 0x60a }, | 1445 | { 0x40016, 0x60a }, |
| 1446 | { 0x40036, 0x15 }, | 1446 | { 0x40036, 0x15 }, |
| 1447 | { 0x40056, 0x1200 }, | 1447 | { 0x40056, 0x1200 }, |
| 1448 | { 0x40076, 0x0 }, | 1448 | { 0x40076, 0x0 }, |
| 1449 | { 0x40017, 0x61a }, | 1449 | { 0x40017, 0x61a }, |
| 1450 | { 0x40037, 0x15 }, | 1450 | { 0x40037, 0x15 }, |
| 1451 | { 0x40057, 0x1300 }, | 1451 | { 0x40057, 0x1300 }, |
| 1452 | { 0x40077, 0x0 }, | 1452 | { 0x40077, 0x0 }, |
| 1453 | { 0x40018, 0x60a }, | 1453 | { 0x40018, 0x60a }, |
| 1454 | { 0x40038, 0x1a }, | 1454 | { 0x40038, 0x1a }, |
| 1455 | { 0x40058, 0x1200 }, | 1455 | { 0x40058, 0x1200 }, |
| 1456 | { 0x40078, 0x0 }, | 1456 | { 0x40078, 0x0 }, |
| 1457 | { 0x40019, 0x642 }, | 1457 | { 0x40019, 0x642 }, |
| 1458 | { 0x40039, 0x1a }, | 1458 | { 0x40039, 0x1a }, |
| 1459 | { 0x40059, 0x1300 }, | 1459 | { 0x40059, 0x1300 }, |
| 1460 | { 0x40079, 0x0 }, | 1460 | { 0x40079, 0x0 }, |
| 1461 | { 0x4001a, 0x4808 }, | 1461 | { 0x4001a, 0x4808 }, |
| 1462 | { 0x4003a, 0x880 }, | 1462 | { 0x4003a, 0x880 }, |
| 1463 | { 0x4005a, 0x0 }, | 1463 | { 0x4005a, 0x0 }, |
| 1464 | { 0x4007a, 0x0 }, | 1464 | { 0x4007a, 0x0 }, |
| 1465 | { 0x900a4, 0x0 }, | 1465 | { 0x900a4, 0x0 }, |
| 1466 | { 0x900a5, 0x790 }, | 1466 | { 0x900a5, 0x790 }, |
| 1467 | { 0x900a6, 0x11a }, | 1467 | { 0x900a6, 0x11a }, |
| 1468 | { 0x900a7, 0x8 }, | 1468 | { 0x900a7, 0x8 }, |
| 1469 | { 0x900a8, 0x7aa }, | 1469 | { 0x900a8, 0x7aa }, |
| 1470 | { 0x900a9, 0x2a }, | 1470 | { 0x900a9, 0x2a }, |
| 1471 | { 0x900aa, 0x10 }, | 1471 | { 0x900aa, 0x10 }, |
| 1472 | { 0x900ab, 0x7b2 }, | 1472 | { 0x900ab, 0x7b2 }, |
| 1473 | { 0x900ac, 0x2a }, | 1473 | { 0x900ac, 0x2a }, |
| 1474 | { 0x900ad, 0x0 }, | 1474 | { 0x900ad, 0x0 }, |
| 1475 | { 0x900ae, 0x7c8 }, | 1475 | { 0x900ae, 0x7c8 }, |
| 1476 | { 0x900af, 0x109 }, | 1476 | { 0x900af, 0x109 }, |
| 1477 | { 0x900b0, 0x10 }, | 1477 | { 0x900b0, 0x10 }, |
| 1478 | { 0x900b1, 0x10 }, | 1478 | { 0x900b1, 0x10 }, |
| 1479 | { 0x900b2, 0x109 }, | 1479 | { 0x900b2, 0x109 }, |
| 1480 | { 0x900b3, 0x10 }, | 1480 | { 0x900b3, 0x10 }, |
| 1481 | { 0x900b4, 0x2a8 }, | 1481 | { 0x900b4, 0x2a8 }, |
| 1482 | { 0x900b5, 0x129 }, | 1482 | { 0x900b5, 0x129 }, |
| 1483 | { 0x900b6, 0x8 }, | 1483 | { 0x900b6, 0x8 }, |
| 1484 | { 0x900b7, 0x370 }, | 1484 | { 0x900b7, 0x370 }, |
| 1485 | { 0x900b8, 0x129 }, | 1485 | { 0x900b8, 0x129 }, |
| 1486 | { 0x900b9, 0xa }, | 1486 | { 0x900b9, 0xa }, |
| 1487 | { 0x900ba, 0x3c8 }, | 1487 | { 0x900ba, 0x3c8 }, |
| 1488 | { 0x900bb, 0x1a9 }, | 1488 | { 0x900bb, 0x1a9 }, |
| 1489 | { 0x900bc, 0xc }, | 1489 | { 0x900bc, 0xc }, |
| 1490 | { 0x900bd, 0x408 }, | 1490 | { 0x900bd, 0x408 }, |
| 1491 | { 0x900be, 0x199 }, | 1491 | { 0x900be, 0x199 }, |
| 1492 | { 0x900bf, 0x14 }, | 1492 | { 0x900bf, 0x14 }, |
| 1493 | { 0x900c0, 0x790 }, | 1493 | { 0x900c0, 0x790 }, |
| 1494 | { 0x900c1, 0x11a }, | 1494 | { 0x900c1, 0x11a }, |
| 1495 | { 0x900c2, 0x8 }, | 1495 | { 0x900c2, 0x8 }, |
| 1496 | { 0x900c3, 0x4 }, | 1496 | { 0x900c3, 0x4 }, |
| 1497 | { 0x900c4, 0x18 }, | 1497 | { 0x900c4, 0x18 }, |
| 1498 | { 0x900c5, 0xe }, | 1498 | { 0x900c5, 0xe }, |
| 1499 | { 0x900c6, 0x408 }, | 1499 | { 0x900c6, 0x408 }, |
| 1500 | { 0x900c7, 0x199 }, | 1500 | { 0x900c7, 0x199 }, |
| 1501 | { 0x900c8, 0x8 }, | 1501 | { 0x900c8, 0x8 }, |
| 1502 | { 0x900c9, 0x8568 }, | 1502 | { 0x900c9, 0x8568 }, |
| 1503 | { 0x900ca, 0x108 }, | 1503 | { 0x900ca, 0x108 }, |
| 1504 | { 0x900cb, 0x18 }, | 1504 | { 0x900cb, 0x18 }, |
| 1505 | { 0x900cc, 0x790 }, | 1505 | { 0x900cc, 0x790 }, |
| 1506 | { 0x900cd, 0x16a }, | 1506 | { 0x900cd, 0x16a }, |
| 1507 | { 0x900ce, 0x8 }, | 1507 | { 0x900ce, 0x8 }, |
| 1508 | { 0x900cf, 0x1d8 }, | 1508 | { 0x900cf, 0x1d8 }, |
| 1509 | { 0x900d0, 0x169 }, | 1509 | { 0x900d0, 0x169 }, |
| 1510 | { 0x900d1, 0x10 }, | 1510 | { 0x900d1, 0x10 }, |
| 1511 | { 0x900d2, 0x8558 }, | 1511 | { 0x900d2, 0x8558 }, |
| 1512 | { 0x900d3, 0x168 }, | 1512 | { 0x900d3, 0x168 }, |
| 1513 | { 0x900d4, 0x70 }, | 1513 | { 0x900d4, 0x70 }, |
| 1514 | { 0x900d5, 0x788 }, | 1514 | { 0x900d5, 0x788 }, |
| 1515 | { 0x900d6, 0x16a }, | 1515 | { 0x900d6, 0x16a }, |
| 1516 | { 0x900d7, 0x1ff8 }, | 1516 | { 0x900d7, 0x1ff8 }, |
| 1517 | { 0x900d8, 0x85a8 }, | 1517 | { 0x900d8, 0x85a8 }, |
| 1518 | { 0x900d9, 0x1e8 }, | 1518 | { 0x900d9, 0x1e8 }, |
| 1519 | { 0x900da, 0x50 }, | 1519 | { 0x900da, 0x50 }, |
| 1520 | { 0x900db, 0x798 }, | 1520 | { 0x900db, 0x798 }, |
| 1521 | { 0x900dc, 0x16a }, | 1521 | { 0x900dc, 0x16a }, |
| 1522 | { 0x900dd, 0x60 }, | 1522 | { 0x900dd, 0x60 }, |
| 1523 | { 0x900de, 0x7a0 }, | 1523 | { 0x900de, 0x7a0 }, |
| 1524 | { 0x900df, 0x16a }, | 1524 | { 0x900df, 0x16a }, |
| 1525 | { 0x900e0, 0x8 }, | 1525 | { 0x900e0, 0x8 }, |
| 1526 | { 0x900e1, 0x8310 }, | 1526 | { 0x900e1, 0x8310 }, |
| 1527 | { 0x900e2, 0x168 }, | 1527 | { 0x900e2, 0x168 }, |
| 1528 | { 0x900e3, 0x8 }, | 1528 | { 0x900e3, 0x8 }, |
| 1529 | { 0x900e4, 0xa310 }, | 1529 | { 0x900e4, 0xa310 }, |
| 1530 | { 0x900e5, 0x168 }, | 1530 | { 0x900e5, 0x168 }, |
| 1531 | { 0x900e6, 0xa }, | 1531 | { 0x900e6, 0xa }, |
| 1532 | { 0x900e7, 0x408 }, | 1532 | { 0x900e7, 0x408 }, |
| 1533 | { 0x900e8, 0x169 }, | 1533 | { 0x900e8, 0x169 }, |
| 1534 | { 0x900e9, 0x6e }, | 1534 | { 0x900e9, 0x6e }, |
| 1535 | { 0x900ea, 0x0 }, | 1535 | { 0x900ea, 0x0 }, |
| 1536 | { 0x900eb, 0x68 }, | 1536 | { 0x900eb, 0x68 }, |
| 1537 | { 0x900ec, 0x0 }, | 1537 | { 0x900ec, 0x0 }, |
| 1538 | { 0x900ed, 0x408 }, | 1538 | { 0x900ed, 0x408 }, |
| 1539 | { 0x900ee, 0x169 }, | 1539 | { 0x900ee, 0x169 }, |
| 1540 | { 0x900ef, 0x0 }, | 1540 | { 0x900ef, 0x0 }, |
| 1541 | { 0x900f0, 0x8310 }, | 1541 | { 0x900f0, 0x8310 }, |
| 1542 | { 0x900f1, 0x168 }, | 1542 | { 0x900f1, 0x168 }, |
| 1543 | { 0x900f2, 0x0 }, | 1543 | { 0x900f2, 0x0 }, |
| 1544 | { 0x900f3, 0xa310 }, | 1544 | { 0x900f3, 0xa310 }, |
| 1545 | { 0x900f4, 0x168 }, | 1545 | { 0x900f4, 0x168 }, |
| 1546 | { 0x900f5, 0x1ff8 }, | 1546 | { 0x900f5, 0x1ff8 }, |
| 1547 | { 0x900f6, 0x85a8 }, | 1547 | { 0x900f6, 0x85a8 }, |
| 1548 | { 0x900f7, 0x1e8 }, | 1548 | { 0x900f7, 0x1e8 }, |
| 1549 | { 0x900f8, 0x68 }, | 1549 | { 0x900f8, 0x68 }, |
| 1550 | { 0x900f9, 0x798 }, | 1550 | { 0x900f9, 0x798 }, |
| 1551 | { 0x900fa, 0x16a }, | 1551 | { 0x900fa, 0x16a }, |
| 1552 | { 0x900fb, 0x78 }, | 1552 | { 0x900fb, 0x78 }, |
| 1553 | { 0x900fc, 0x7a0 }, | 1553 | { 0x900fc, 0x7a0 }, |
| 1554 | { 0x900fd, 0x16a }, | 1554 | { 0x900fd, 0x16a }, |
| 1555 | { 0x900fe, 0x68 }, | 1555 | { 0x900fe, 0x68 }, |
| 1556 | { 0x900ff, 0x790 }, | 1556 | { 0x900ff, 0x790 }, |
| 1557 | { 0x90100, 0x16a }, | 1557 | { 0x90100, 0x16a }, |
| 1558 | { 0x90101, 0x8 }, | 1558 | { 0x90101, 0x8 }, |
| 1559 | { 0x90102, 0x8b10 }, | 1559 | { 0x90102, 0x8b10 }, |
| 1560 | { 0x90103, 0x168 }, | 1560 | { 0x90103, 0x168 }, |
| 1561 | { 0x90104, 0x8 }, | 1561 | { 0x90104, 0x8 }, |
| 1562 | { 0x90105, 0xab10 }, | 1562 | { 0x90105, 0xab10 }, |
| 1563 | { 0x90106, 0x168 }, | 1563 | { 0x90106, 0x168 }, |
| 1564 | { 0x90107, 0xa }, | 1564 | { 0x90107, 0xa }, |
| 1565 | { 0x90108, 0x408 }, | 1565 | { 0x90108, 0x408 }, |
| 1566 | { 0x90109, 0x169 }, | 1566 | { 0x90109, 0x169 }, |
| 1567 | { 0x9010a, 0x58 }, | 1567 | { 0x9010a, 0x58 }, |
| 1568 | { 0x9010b, 0x0 }, | 1568 | { 0x9010b, 0x0 }, |
| 1569 | { 0x9010c, 0x68 }, | 1569 | { 0x9010c, 0x68 }, |
| 1570 | { 0x9010d, 0x0 }, | 1570 | { 0x9010d, 0x0 }, |
| 1571 | { 0x9010e, 0x408 }, | 1571 | { 0x9010e, 0x408 }, |
| 1572 | { 0x9010f, 0x169 }, | 1572 | { 0x9010f, 0x169 }, |
| 1573 | { 0x90110, 0x0 }, | 1573 | { 0x90110, 0x0 }, |
| 1574 | { 0x90111, 0x8b10 }, | 1574 | { 0x90111, 0x8b10 }, |
| 1575 | { 0x90112, 0x168 }, | 1575 | { 0x90112, 0x168 }, |
| 1576 | { 0x90113, 0x1 }, | 1576 | { 0x90113, 0x1 }, |
| 1577 | { 0x90114, 0xab10 }, | 1577 | { 0x90114, 0xab10 }, |
| 1578 | { 0x90115, 0x168 }, | 1578 | { 0x90115, 0x168 }, |
| 1579 | { 0x90116, 0x0 }, | 1579 | { 0x90116, 0x0 }, |
| 1580 | { 0x90117, 0x1d8 }, | 1580 | { 0x90117, 0x1d8 }, |
| 1581 | { 0x90118, 0x169 }, | 1581 | { 0x90118, 0x169 }, |
| 1582 | { 0x90119, 0x80 }, | 1582 | { 0x90119, 0x80 }, |
| 1583 | { 0x9011a, 0x790 }, | 1583 | { 0x9011a, 0x790 }, |
| 1584 | { 0x9011b, 0x16a }, | 1584 | { 0x9011b, 0x16a }, |
| 1585 | { 0x9011c, 0x18 }, | 1585 | { 0x9011c, 0x18 }, |
| 1586 | { 0x9011d, 0x7aa }, | 1586 | { 0x9011d, 0x7aa }, |
| 1587 | { 0x9011e, 0x6a }, | 1587 | { 0x9011e, 0x6a }, |
| 1588 | { 0x9011f, 0xa }, | 1588 | { 0x9011f, 0xa }, |
| 1589 | { 0x90120, 0x0 }, | 1589 | { 0x90120, 0x0 }, |
| 1590 | { 0x90121, 0x1e9 }, | 1590 | { 0x90121, 0x1e9 }, |
| 1591 | { 0x90122, 0x8 }, | 1591 | { 0x90122, 0x8 }, |
| 1592 | { 0x90123, 0x8080 }, | 1592 | { 0x90123, 0x8080 }, |
| 1593 | { 0x90124, 0x108 }, | 1593 | { 0x90124, 0x108 }, |
| 1594 | { 0x90125, 0xf }, | 1594 | { 0x90125, 0xf }, |
| 1595 | { 0x90126, 0x408 }, | 1595 | { 0x90126, 0x408 }, |
| 1596 | { 0x90127, 0x169 }, | 1596 | { 0x90127, 0x169 }, |
| 1597 | { 0x90128, 0xc }, | 1597 | { 0x90128, 0xc }, |
| 1598 | { 0x90129, 0x0 }, | 1598 | { 0x90129, 0x0 }, |
| 1599 | { 0x9012a, 0x68 }, | 1599 | { 0x9012a, 0x68 }, |
| 1600 | { 0x9012b, 0x9 }, | 1600 | { 0x9012b, 0x9 }, |
| 1601 | { 0x9012c, 0x0 }, | 1601 | { 0x9012c, 0x0 }, |
| 1602 | { 0x9012d, 0x1a9 }, | 1602 | { 0x9012d, 0x1a9 }, |
| 1603 | { 0x9012e, 0x0 }, | 1603 | { 0x9012e, 0x0 }, |
| 1604 | { 0x9012f, 0x408 }, | 1604 | { 0x9012f, 0x408 }, |
| 1605 | { 0x90130, 0x169 }, | 1605 | { 0x90130, 0x169 }, |
| 1606 | { 0x90131, 0x0 }, | 1606 | { 0x90131, 0x0 }, |
| 1607 | { 0x90132, 0x8080 }, | 1607 | { 0x90132, 0x8080 }, |
| 1608 | { 0x90133, 0x108 }, | 1608 | { 0x90133, 0x108 }, |
| 1609 | { 0x90134, 0x8 }, | 1609 | { 0x90134, 0x8 }, |
| 1610 | { 0x90135, 0x7aa }, | 1610 | { 0x90135, 0x7aa }, |
| 1611 | { 0x90136, 0x6a }, | 1611 | { 0x90136, 0x6a }, |
| 1612 | { 0x90137, 0x0 }, | 1612 | { 0x90137, 0x0 }, |
| 1613 | { 0x90138, 0x8568 }, | 1613 | { 0x90138, 0x8568 }, |
| 1614 | { 0x90139, 0x108 }, | 1614 | { 0x90139, 0x108 }, |
| 1615 | { 0x9013a, 0xb7 }, | 1615 | { 0x9013a, 0xb7 }, |
| 1616 | { 0x9013b, 0x790 }, | 1616 | { 0x9013b, 0x790 }, |
| 1617 | { 0x9013c, 0x16a }, | 1617 | { 0x9013c, 0x16a }, |
| 1618 | { 0x9013d, 0x1f }, | 1618 | { 0x9013d, 0x1f }, |
| 1619 | { 0x9013e, 0x0 }, | 1619 | { 0x9013e, 0x0 }, |
| 1620 | { 0x9013f, 0x68 }, | 1620 | { 0x9013f, 0x68 }, |
| 1621 | { 0x90140, 0x8 }, | 1621 | { 0x90140, 0x8 }, |
| 1622 | { 0x90141, 0x8558 }, | 1622 | { 0x90141, 0x8558 }, |
| 1623 | { 0x90142, 0x168 }, | 1623 | { 0x90142, 0x168 }, |
| 1624 | { 0x90143, 0xf }, | 1624 | { 0x90143, 0xf }, |
| 1625 | { 0x90144, 0x408 }, | 1625 | { 0x90144, 0x408 }, |
| 1626 | { 0x90145, 0x169 }, | 1626 | { 0x90145, 0x169 }, |
| 1627 | { 0x90146, 0xd }, | 1627 | { 0x90146, 0xd }, |
| 1628 | { 0x90147, 0x0 }, | 1628 | { 0x90147, 0x0 }, |
| 1629 | { 0x90148, 0x68 }, | 1629 | { 0x90148, 0x68 }, |
| 1630 | { 0x90149, 0x0 }, | 1630 | { 0x90149, 0x0 }, |
| 1631 | { 0x9014a, 0x408 }, | 1631 | { 0x9014a, 0x408 }, |
| 1632 | { 0x9014b, 0x169 }, | 1632 | { 0x9014b, 0x169 }, |
| 1633 | { 0x9014c, 0x0 }, | 1633 | { 0x9014c, 0x0 }, |
| 1634 | { 0x9014d, 0x8558 }, | 1634 | { 0x9014d, 0x8558 }, |
| 1635 | { 0x9014e, 0x168 }, | 1635 | { 0x9014e, 0x168 }, |
| 1636 | { 0x9014f, 0x8 }, | 1636 | { 0x9014f, 0x8 }, |
| 1637 | { 0x90150, 0x3c8 }, | 1637 | { 0x90150, 0x3c8 }, |
| 1638 | { 0x90151, 0x1a9 }, | 1638 | { 0x90151, 0x1a9 }, |
| 1639 | { 0x90152, 0x3 }, | 1639 | { 0x90152, 0x3 }, |
| 1640 | { 0x90153, 0x370 }, | 1640 | { 0x90153, 0x370 }, |
| 1641 | { 0x90154, 0x129 }, | 1641 | { 0x90154, 0x129 }, |
| 1642 | { 0x90155, 0x20 }, | 1642 | { 0x90155, 0x20 }, |
| 1643 | { 0x90156, 0x2aa }, | 1643 | { 0x90156, 0x2aa }, |
| 1644 | { 0x90157, 0x9 }, | 1644 | { 0x90157, 0x9 }, |
| 1645 | { 0x90158, 0x8 }, | 1645 | { 0x90158, 0x8 }, |
| 1646 | { 0x90159, 0xe8 }, | 1646 | { 0x90159, 0xe8 }, |
| 1647 | { 0x9015a, 0x109 }, | 1647 | { 0x9015a, 0x109 }, |
| 1648 | { 0x9015b, 0x0 }, | 1648 | { 0x9015b, 0x0 }, |
| 1649 | { 0x9015c, 0x8140 }, | 1649 | { 0x9015c, 0x8140 }, |
| 1650 | { 0x9015d, 0x10c }, | 1650 | { 0x9015d, 0x10c }, |
| 1651 | { 0x9015e, 0x10 }, | 1651 | { 0x9015e, 0x10 }, |
| 1652 | { 0x9015f, 0x8138 }, | 1652 | { 0x9015f, 0x8138 }, |
| 1653 | { 0x90160, 0x104 }, | 1653 | { 0x90160, 0x104 }, |
| 1654 | { 0x90161, 0x8 }, | 1654 | { 0x90161, 0x8 }, |
| 1655 | { 0x90162, 0x448 }, | 1655 | { 0x90162, 0x448 }, |
| 1656 | { 0x90163, 0x109 }, | 1656 | { 0x90163, 0x109 }, |
| 1657 | { 0x90164, 0xf }, | 1657 | { 0x90164, 0xf }, |
| 1658 | { 0x90165, 0x7c0 }, | 1658 | { 0x90165, 0x7c0 }, |
| 1659 | { 0x90166, 0x109 }, | 1659 | { 0x90166, 0x109 }, |
| 1660 | { 0x90167, 0x0 }, | 1660 | { 0x90167, 0x0 }, |
| 1661 | { 0x90168, 0xe8 }, | 1661 | { 0x90168, 0xe8 }, |
| 1662 | { 0x90169, 0x109 }, | 1662 | { 0x90169, 0x109 }, |
| 1663 | { 0x9016a, 0x47 }, | 1663 | { 0x9016a, 0x47 }, |
| 1664 | { 0x9016b, 0x630 }, | 1664 | { 0x9016b, 0x630 }, |
| 1665 | { 0x9016c, 0x109 }, | 1665 | { 0x9016c, 0x109 }, |
| 1666 | { 0x9016d, 0x8 }, | 1666 | { 0x9016d, 0x8 }, |
| 1667 | { 0x9016e, 0x618 }, | 1667 | { 0x9016e, 0x618 }, |
| 1668 | { 0x9016f, 0x109 }, | 1668 | { 0x9016f, 0x109 }, |
| 1669 | { 0x90170, 0x8 }, | 1669 | { 0x90170, 0x8 }, |
| 1670 | { 0x90171, 0xe0 }, | 1670 | { 0x90171, 0xe0 }, |
| 1671 | { 0x90172, 0x109 }, | 1671 | { 0x90172, 0x109 }, |
| 1672 | { 0x90173, 0x0 }, | 1672 | { 0x90173, 0x0 }, |
| 1673 | { 0x90174, 0x7c8 }, | 1673 | { 0x90174, 0x7c8 }, |
| 1674 | { 0x90175, 0x109 }, | 1674 | { 0x90175, 0x109 }, |
| 1675 | { 0x90176, 0x8 }, | 1675 | { 0x90176, 0x8 }, |
| 1676 | { 0x90177, 0x8140 }, | 1676 | { 0x90177, 0x8140 }, |
| 1677 | { 0x90178, 0x10c }, | 1677 | { 0x90178, 0x10c }, |
| 1678 | { 0x90179, 0x0 }, | 1678 | { 0x90179, 0x0 }, |
| 1679 | { 0x9017a, 0x478 }, | 1679 | { 0x9017a, 0x478 }, |
| 1680 | { 0x9017b, 0x109 }, | 1680 | { 0x9017b, 0x109 }, |
| 1681 | { 0x9017c, 0x0 }, | 1681 | { 0x9017c, 0x0 }, |
| 1682 | { 0x9017d, 0x1 }, | 1682 | { 0x9017d, 0x1 }, |
| 1683 | { 0x9017e, 0x8 }, | 1683 | { 0x9017e, 0x8 }, |
| 1684 | { 0x9017f, 0x8 }, | 1684 | { 0x9017f, 0x8 }, |
| 1685 | { 0x90180, 0x4 }, | 1685 | { 0x90180, 0x4 }, |
| 1686 | { 0x90181, 0x0 }, | 1686 | { 0x90181, 0x0 }, |
| 1687 | { 0x90006, 0x8 }, | 1687 | { 0x90006, 0x8 }, |
| 1688 | { 0x90007, 0x7c8 }, | 1688 | { 0x90007, 0x7c8 }, |
| 1689 | { 0x90008, 0x109 }, | 1689 | { 0x90008, 0x109 }, |
| 1690 | { 0x90009, 0x0 }, | 1690 | { 0x90009, 0x0 }, |
| 1691 | { 0x9000a, 0x400 }, | 1691 | { 0x9000a, 0x400 }, |
| 1692 | { 0x9000b, 0x106 }, | 1692 | { 0x9000b, 0x106 }, |
| 1693 | { 0xd00e7, 0x400 }, | 1693 | { 0xd00e7, 0x400 }, |
| 1694 | { 0x90017, 0x0 }, | 1694 | { 0x90017, 0x0 }, |
| 1695 | { 0x9001f, 0x29 }, | 1695 | { 0x9001f, 0x29 }, |
| 1696 | { 0x90026, 0x68 }, | 1696 | { 0x90026, 0x68 }, |
| 1697 | { 0x400d0, 0x0 }, | 1697 | { 0x400d0, 0x0 }, |
| 1698 | { 0x400d1, 0x101 }, | 1698 | { 0x400d1, 0x101 }, |
| 1699 | { 0x400d2, 0x105 }, | 1699 | { 0x400d2, 0x105 }, |
| 1700 | { 0x400d3, 0x107 }, | 1700 | { 0x400d3, 0x107 }, |
| 1701 | { 0x400d4, 0x10f }, | 1701 | { 0x400d4, 0x10f }, |
| 1702 | { 0x400d5, 0x202 }, | 1702 | { 0x400d5, 0x202 }, |
| 1703 | { 0x400d6, 0x20a }, | 1703 | { 0x400d6, 0x20a }, |
| 1704 | { 0x400d7, 0x20b }, | 1704 | { 0x400d7, 0x20b }, |
| 1705 | { 0x2003a, 0x2 }, | 1705 | { 0x2003a, 0x2 }, |
| 1706 | { 0x200be, 0x3 }, | 1706 | { 0x200be, 0x3 }, |
| 1707 | { 0x2000b, 0x7d }, | 1707 | { 0x2000b, 0x7d }, |
| 1708 | { 0x2000c, 0xfa }, | 1708 | { 0x2000c, 0xfa }, |
| 1709 | { 0x2000d, 0x9c4 }, | 1709 | { 0x2000d, 0x9c4 }, |
| 1710 | { 0x2000e, 0x2c }, | 1710 | { 0x2000e, 0x2c }, |
| 1711 | { 0x12000b, 0xc }, | 1711 | { 0x12000b, 0xc }, |
| 1712 | { 0x12000c, 0x19 }, | 1712 | { 0x12000c, 0x19 }, |
| 1713 | { 0x12000d, 0xfa }, | 1713 | { 0x12000d, 0xfa }, |
| 1714 | { 0x12000e, 0x10 }, | 1714 | { 0x12000e, 0x10 }, |
| 1715 | { 0x22000b, 0x3 }, | 1715 | { 0x22000b, 0x3 }, |
| 1716 | { 0x22000c, 0x6 }, | 1716 | { 0x22000c, 0x6 }, |
| 1717 | { 0x22000d, 0x3e }, | 1717 | { 0x22000d, 0x3e }, |
| 1718 | { 0x22000e, 0x10 }, | 1718 | { 0x22000e, 0x10 }, |
| 1719 | { 0x9000c, 0x0 }, | 1719 | { 0x9000c, 0x0 }, |
| 1720 | { 0x9000d, 0x173 }, | 1720 | { 0x9000d, 0x173 }, |
| 1721 | { 0x9000e, 0x60 }, | 1721 | { 0x9000e, 0x60 }, |
| 1722 | { 0x9000f, 0x6110 }, | 1722 | { 0x9000f, 0x6110 }, |
| 1723 | { 0x90010, 0x2152 }, | 1723 | { 0x90010, 0x2152 }, |
| 1724 | { 0x90011, 0xdfbd }, | 1724 | { 0x90011, 0xdfbd }, |
| 1725 | { 0x90012, 0x2060 }, | 1725 | { 0x90012, 0x2060 }, |
| 1726 | { 0x90013, 0x6152 }, | 1726 | { 0x90013, 0x6152 }, |
| 1727 | { 0x20010, 0x5a }, | 1727 | { 0x20010, 0x5a }, |
| 1728 | { 0x20011, 0x3 }, | 1728 | { 0x20011, 0x3 }, |
| 1729 | { 0x40080, 0xe0 }, | 1729 | { 0x40080, 0xe0 }, |
| 1730 | { 0x40081, 0x12 }, | 1730 | { 0x40081, 0x12 }, |
| 1731 | { 0x40082, 0xe0 }, | 1731 | { 0x40082, 0xe0 }, |
| 1732 | { 0x40083, 0x12 }, | 1732 | { 0x40083, 0x12 }, |
| 1733 | { 0x40084, 0xe0 }, | 1733 | { 0x40084, 0xe0 }, |
| 1734 | { 0x40085, 0x12 }, | 1734 | { 0x40085, 0x12 }, |
| 1735 | { 0x140080, 0xe0 }, | 1735 | { 0x140080, 0xe0 }, |
| 1736 | { 0x140081, 0x12 }, | 1736 | { 0x140081, 0x12 }, |
| 1737 | { 0x140082, 0xe0 }, | 1737 | { 0x140082, 0xe0 }, |
| 1738 | { 0x140083, 0x12 }, | 1738 | { 0x140083, 0x12 }, |
| 1739 | { 0x140084, 0xe0 }, | 1739 | { 0x140084, 0xe0 }, |
| 1740 | { 0x140085, 0x12 }, | 1740 | { 0x140085, 0x12 }, |
| 1741 | { 0x240080, 0xe0 }, | 1741 | { 0x240080, 0xe0 }, |
| 1742 | { 0x240081, 0x12 }, | 1742 | { 0x240081, 0x12 }, |
| 1743 | { 0x240082, 0xe0 }, | 1743 | { 0x240082, 0xe0 }, |
| 1744 | { 0x240083, 0x12 }, | 1744 | { 0x240083, 0x12 }, |
| 1745 | { 0x240084, 0xe0 }, | 1745 | { 0x240084, 0xe0 }, |
| 1746 | { 0x240085, 0x12 }, | 1746 | { 0x240085, 0x12 }, |
| 1747 | { 0x400fd, 0xf }, | 1747 | { 0x400fd, 0xf }, |
| 1748 | { 0x10011, 0x1 }, | 1748 | { 0x10011, 0x1 }, |
| 1749 | { 0x10012, 0x1 }, | 1749 | { 0x10012, 0x1 }, |
| 1750 | { 0x10013, 0x180 }, | 1750 | { 0x10013, 0x180 }, |
| 1751 | { 0x10018, 0x1 }, | 1751 | { 0x10018, 0x1 }, |
| 1752 | { 0x10002, 0x6209 }, | 1752 | { 0x10002, 0x6209 }, |
| 1753 | { 0x100b2, 0x1 }, | 1753 | { 0x100b2, 0x1 }, |
| 1754 | { 0x101b4, 0x1 }, | 1754 | { 0x101b4, 0x1 }, |
| 1755 | { 0x102b4, 0x1 }, | 1755 | { 0x102b4, 0x1 }, |
| 1756 | { 0x103b4, 0x1 }, | 1756 | { 0x103b4, 0x1 }, |
| 1757 | { 0x104b4, 0x1 }, | 1757 | { 0x104b4, 0x1 }, |
| 1758 | { 0x105b4, 0x1 }, | 1758 | { 0x105b4, 0x1 }, |
| 1759 | { 0x106b4, 0x1 }, | 1759 | { 0x106b4, 0x1 }, |
| 1760 | { 0x107b4, 0x1 }, | 1760 | { 0x107b4, 0x1 }, |
| 1761 | { 0x108b4, 0x1 }, | 1761 | { 0x108b4, 0x1 }, |
| 1762 | { 0x11011, 0x1 }, | 1762 | { 0x11011, 0x1 }, |
| 1763 | { 0x11012, 0x1 }, | 1763 | { 0x11012, 0x1 }, |
| 1764 | { 0x11013, 0x180 }, | 1764 | { 0x11013, 0x180 }, |
| 1765 | { 0x11018, 0x1 }, | 1765 | { 0x11018, 0x1 }, |
| 1766 | { 0x11002, 0x6209 }, | 1766 | { 0x11002, 0x6209 }, |
| 1767 | { 0x110b2, 0x1 }, | 1767 | { 0x110b2, 0x1 }, |
| 1768 | { 0x111b4, 0x1 }, | 1768 | { 0x111b4, 0x1 }, |
| 1769 | { 0x112b4, 0x1 }, | 1769 | { 0x112b4, 0x1 }, |
| 1770 | { 0x113b4, 0x1 }, | 1770 | { 0x113b4, 0x1 }, |
| 1771 | { 0x114b4, 0x1 }, | 1771 | { 0x114b4, 0x1 }, |
| 1772 | { 0x115b4, 0x1 }, | 1772 | { 0x115b4, 0x1 }, |
| 1773 | { 0x116b4, 0x1 }, | 1773 | { 0x116b4, 0x1 }, |
| 1774 | { 0x117b4, 0x1 }, | 1774 | { 0x117b4, 0x1 }, |
| 1775 | { 0x118b4, 0x1 }, | 1775 | { 0x118b4, 0x1 }, |
| 1776 | { 0x12011, 0x1 }, | 1776 | { 0x12011, 0x1 }, |
| 1777 | { 0x12012, 0x1 }, | 1777 | { 0x12012, 0x1 }, |
| 1778 | { 0x12013, 0x180 }, | 1778 | { 0x12013, 0x180 }, |
| 1779 | { 0x12018, 0x1 }, | 1779 | { 0x12018, 0x1 }, |
| 1780 | { 0x12002, 0x6209 }, | 1780 | { 0x12002, 0x6209 }, |
| 1781 | { 0x120b2, 0x1 }, | 1781 | { 0x120b2, 0x1 }, |
| 1782 | { 0x121b4, 0x1 }, | 1782 | { 0x121b4, 0x1 }, |
| 1783 | { 0x122b4, 0x1 }, | 1783 | { 0x122b4, 0x1 }, |
| 1784 | { 0x123b4, 0x1 }, | 1784 | { 0x123b4, 0x1 }, |
| 1785 | { 0x124b4, 0x1 }, | 1785 | { 0x124b4, 0x1 }, |
| 1786 | { 0x125b4, 0x1 }, | 1786 | { 0x125b4, 0x1 }, |
| 1787 | { 0x126b4, 0x1 }, | 1787 | { 0x126b4, 0x1 }, |
| 1788 | { 0x127b4, 0x1 }, | 1788 | { 0x127b4, 0x1 }, |
| 1789 | { 0x128b4, 0x1 }, | 1789 | { 0x128b4, 0x1 }, |
| 1790 | { 0x13011, 0x1 }, | 1790 | { 0x13011, 0x1 }, |
| 1791 | { 0x13012, 0x1 }, | 1791 | { 0x13012, 0x1 }, |
| 1792 | { 0x13013, 0x180 }, | 1792 | { 0x13013, 0x180 }, |
| 1793 | { 0x13018, 0x1 }, | 1793 | { 0x13018, 0x1 }, |
| 1794 | { 0x13002, 0x6209 }, | 1794 | { 0x13002, 0x6209 }, |
| 1795 | { 0x130b2, 0x1 }, | 1795 | { 0x130b2, 0x1 }, |
| 1796 | { 0x131b4, 0x1 }, | 1796 | { 0x131b4, 0x1 }, |
| 1797 | { 0x132b4, 0x1 }, | 1797 | { 0x132b4, 0x1 }, |
| 1798 | { 0x133b4, 0x1 }, | 1798 | { 0x133b4, 0x1 }, |
| 1799 | { 0x134b4, 0x1 }, | 1799 | { 0x134b4, 0x1 }, |
| 1800 | { 0x135b4, 0x1 }, | 1800 | { 0x135b4, 0x1 }, |
| 1801 | { 0x136b4, 0x1 }, | 1801 | { 0x136b4, 0x1 }, |
| 1802 | { 0x137b4, 0x1 }, | 1802 | { 0x137b4, 0x1 }, |
| 1803 | { 0x138b4, 0x1 }, | 1803 | { 0x138b4, 0x1 }, |
| 1804 | { 0x20089, 0x1 }, | 1804 | { 0x20089, 0x1 }, |
| 1805 | { 0x20088, 0x19 }, | 1805 | { 0x20088, 0x19 }, |
| 1806 | { 0xc0080, 0x2 }, | 1806 | { 0xc0080, 0x2 }, |
| 1807 | { 0xd0000, 0x1 } | 1807 | { 0xd0000, 0x1 } |
| 1808 | }; | 1808 | }; |
| 1809 | 1809 | ||
| 1810 | struct dram_fsp_msg ddr_dram_fsp_msg[] = { | 1810 | struct dram_fsp_msg ddr_dram_fsp_msg[] = { |
| 1811 | { | 1811 | { |
| 1812 | /* P0 4000mts 1D */ | 1812 | /* P0 4000mts 1D */ |
| 1813 | .drate = 4000, | 1813 | .drate = 4000, |
| 1814 | .fw_type = FW_1D_IMAGE, | 1814 | .fw_type = FW_1D_IMAGE, |
| 1815 | .fsp_cfg = ddr_fsp0_cfg, | 1815 | .fsp_cfg = ddr_fsp0_cfg, |
| 1816 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), | 1816 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), |
| 1817 | }, | 1817 | }, |
| 1818 | { | 1818 | { |
| 1819 | /* P1 400mts 1D */ | 1819 | /* P1 400mts 1D */ |
| 1820 | .drate = 400, | 1820 | .drate = 400, |
| 1821 | .fw_type = FW_1D_IMAGE, | 1821 | .fw_type = FW_1D_IMAGE, |
| 1822 | .fsp_cfg = ddr_fsp1_cfg, | 1822 | .fsp_cfg = ddr_fsp1_cfg, |
| 1823 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), | 1823 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), |
| 1824 | }, | 1824 | }, |
| 1825 | { | 1825 | { |
| 1826 | /* P2 100mts 1D */ | 1826 | /* P2 100mts 1D */ |
| 1827 | .drate = 100, | 1827 | .drate = 100, |
| 1828 | .fw_type = FW_1D_IMAGE, | 1828 | .fw_type = FW_1D_IMAGE, |
| 1829 | .fsp_cfg = ddr_fsp2_cfg, | 1829 | .fsp_cfg = ddr_fsp2_cfg, |
| 1830 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), | 1830 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), |
| 1831 | }, | 1831 | }, |
| 1832 | { | 1832 | { |
| 1833 | /* P0 4000mts 2D */ | 1833 | /* P0 4000mts 2D */ |
| 1834 | .drate = 4000, | 1834 | .drate = 4000, |
| 1835 | .fw_type = FW_2D_IMAGE, | 1835 | .fw_type = FW_2D_IMAGE, |
| 1836 | .fsp_cfg = ddr_fsp0_2d_cfg, | 1836 | .fsp_cfg = ddr_fsp0_2d_cfg, |
| 1837 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), | 1837 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), |
| 1838 | }, | 1838 | }, |
| 1839 | }; | 1839 | }; |
| 1840 | 1840 | ||
| 1841 | /* ddr timing config params */ | 1841 | /* ddr timing config params */ |
| 1842 | struct dram_timing_info dram_timing = { | 1842 | struct dram_timing_info dram_timing = { |
| 1843 | .ddrc_cfg = ddr_ddrc_cfg, | 1843 | .ddrc_cfg = ddr_ddrc_cfg, |
| 1844 | .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), | 1844 | .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), |
| 1845 | .ddrphy_cfg = ddr_ddrphy_cfg, | 1845 | .ddrphy_cfg = ddr_ddrphy_cfg, |
| 1846 | .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), | 1846 | .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), |
| 1847 | .fsp_msg = ddr_dram_fsp_msg, | 1847 | .fsp_msg = ddr_dram_fsp_msg, |
| 1848 | .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), | 1848 | .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), |
| 1849 | .ddrphy_trained_csr = ddr_ddrphy_trained_csr, | 1849 | .ddrphy_trained_csr = ddr_ddrphy_trained_csr, |
| 1850 | .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), | 1850 | .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), |
| 1851 | .ddrphy_pie = ddr_phy_pie, | 1851 | .ddrphy_pie = ddr_phy_pie, |
| 1852 | .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), | 1852 | .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), |
| 1853 | .fsp_table = { 4000, 400, 100, }, | 1853 | .fsp_table = { 4000, 400, 100, }, |
| 1854 | }; | 1854 | }; |
| 1855 | #elif defined(CONFIG_6GB_LPDDR4) | 1855 | #elif defined(CONFIG_6GB_LPDDR4) |
| 1856 | struct dram_cfg_param ddr_ddrc_cfg[] = { | 1856 | struct dram_cfg_param ddr_ddrc_cfg[] = { |
| 1857 | /** Initialize DDRC registers **/ | 1857 | /** Initialize DDRC registers **/ |
| 1858 | { 0x3d400304, 0x1 }, | 1858 | { 0x3d400304, 0x1 }, |
| 1859 | { 0x3d400030, 0x1 }, | 1859 | { 0x3d400030, 0x1 }, |
| 1860 | { 0x3d400000, 0xa3080020 }, | 1860 | { 0x3d400000, 0xa3080020 }, |
| 1861 | { 0x3d400020, 0x1322 }, | 1861 | { 0x3d400020, 0x1322 }, |
| 1862 | { 0x3d400024, 0x1e84800 }, | 1862 | { 0x3d400024, 0x1e84800 }, |
| 1863 | { 0x3d400064, 0x3d017c }, | 1863 | { 0x3d400064, 0x3d017c }, |
| 1864 | { 0x3d400070, 0x1027f10 }, | 1864 | { 0x3d400070, 0x1027f10 }, |
| 1865 | { 0x3d400074, 0x7b0 }, | 1865 | { 0x3d400074, 0x7b0 }, |
| 1866 | { 0x3d4000d0, 0xc00307a3 }, | 1866 | { 0x3d4000d0, 0xc00307a3 }, |
| 1867 | { 0x3d4000d4, 0xc50000 }, | 1867 | { 0x3d4000d4, 0xc50000 }, |
| 1868 | { 0x3d4000dc, 0xf4003f }, | 1868 | { 0x3d4000dc, 0xf4003f }, |
| 1869 | { 0x3d4000e0, 0x330000 }, | 1869 | { 0x3d4000e0, 0x330000 }, |
| 1870 | { 0x3d4000e8, 0x660048 }, | 1870 | { 0x3d4000e8, 0x660048 }, |
| 1871 | { 0x3d4000ec, 0x160048 }, | 1871 | { 0x3d4000ec, 0x160048 }, |
| 1872 | { 0x3d400100, 0x2028112a }, | 1872 | { 0x3d400100, 0x2028112a }, |
| 1873 | { 0x3d400104, 0x8083f }, | 1873 | { 0x3d400104, 0x8083f }, |
| 1874 | { 0x3d40010c, 0xe0e000 }, | 1874 | { 0x3d40010c, 0xe0e000 }, |
| 1875 | { 0x3d400110, 0x12040a12 }, | 1875 | { 0x3d400110, 0x12040a12 }, |
| 1876 | { 0x3d400114, 0x2050f0f }, | 1876 | { 0x3d400114, 0x2050f0f }, |
| 1877 | { 0x3d400118, 0x1010009 }, | 1877 | { 0x3d400118, 0x1010009 }, |
| 1878 | { 0x3d40011c, 0x501 }, | 1878 | { 0x3d40011c, 0x501 }, |
| 1879 | { 0x3d400130, 0x20800 }, | 1879 | { 0x3d400130, 0x20800 }, |
| 1880 | { 0x3d400134, 0xe100002 }, | 1880 | { 0x3d400134, 0xe100002 }, |
| 1881 | { 0x3d400138, 0x184 }, | 1881 | { 0x3d400138, 0x184 }, |
| 1882 | { 0x3d400144, 0xc80064 }, | 1882 | { 0x3d400144, 0xc80064 }, |
| 1883 | { 0x3d400180, 0x3e8001e }, | 1883 | { 0x3d400180, 0x3e8001e }, |
| 1884 | { 0x3d400184, 0x3207a12 }, | 1884 | { 0x3d400184, 0x3207a12 }, |
| 1885 | { 0x3d400188, 0x0 }, | 1885 | { 0x3d400188, 0x0 }, |
| 1886 | { 0x3d400190, 0x49f820e }, | 1886 | { 0x3d400190, 0x49f820e }, |
| 1887 | { 0x3d400194, 0x80303 }, | 1887 | { 0x3d400194, 0x80303 }, |
| 1888 | { 0x3d4001b4, 0x1f0e }, | 1888 | { 0x3d4001b4, 0x1f0e }, |
| 1889 | { 0x3d4001a0, 0xe0400018 }, | 1889 | { 0x3d4001a0, 0xe0400018 }, |
| 1890 | { 0x3d4001a4, 0xdf00e4 }, | 1890 | { 0x3d4001a4, 0xdf00e4 }, |
| 1891 | { 0x3d4001a8, 0x80000000 }, | 1891 | { 0x3d4001a8, 0x80000000 }, |
| 1892 | { 0x3d4001b0, 0x11 }, | 1892 | { 0x3d4001b0, 0x11 }, |
| 1893 | { 0x3d4001c0, 0x1 }, | 1893 | { 0x3d4001c0, 0x1 }, |
| 1894 | { 0x3d4001c4, 0x1 }, | 1894 | { 0x3d4001c4, 0x1 }, |
| 1895 | { 0x3d4000f4, 0xc99 }, | 1895 | { 0x3d4000f4, 0xc99 }, |
| 1896 | { 0x3d400108, 0x9121c1c }, | 1896 | { 0x3d400108, 0x9121c1c }, |
| 1897 | { 0x3d400200, 0x16 }, | 1897 | { 0x3d400200, 0x16 }, |
| 1898 | { 0x3d40020c, 0x0 }, | 1898 | { 0x3d40020c, 0x0 }, |
| 1899 | { 0x3d400210, 0x1f1f }, | 1899 | { 0x3d400210, 0x1f1f }, |
| 1900 | { 0x3d400204, 0x80808 }, | 1900 | { 0x3d400204, 0x80808 }, |
| 1901 | { 0x3d400214, 0x7070707 }, | 1901 | { 0x3d400214, 0x7070707 }, |
| 1902 | { 0x3d400218, 0x68070707 }, | 1902 | { 0x3d400218, 0x68070707 }, |
| 1903 | { 0x3d40021c, 0xf08 }, | 1903 | { 0x3d40021c, 0xf08 }, |
| 1904 | { 0x3d400250, 0x1705 }, | 1904 | { 0x3d400250, 0x1705 }, |
| 1905 | { 0x3d400254, 0x2c }, | 1905 | { 0x3d400254, 0x2c }, |
| 1906 | { 0x3d40025c, 0x4000030 }, | 1906 | { 0x3d40025c, 0x4000030 }, |
| 1907 | { 0x3d400264, 0x900093e7 }, | 1907 | { 0x3d400264, 0x900093e7 }, |
| 1908 | { 0x3d40026c, 0x2005574 }, | 1908 | { 0x3d40026c, 0x2005574 }, |
| 1909 | { 0x3d400400, 0x111 }, | 1909 | { 0x3d400400, 0x111 }, |
| 1910 | { 0x3d400404, 0x72ff }, | 1910 | { 0x3d400404, 0x72ff }, |
| 1911 | { 0x3d400408, 0x72ff }, | 1911 | { 0x3d400408, 0x72ff }, |
| 1912 | { 0x3d400494, 0x2100e07 }, | 1912 | { 0x3d400494, 0x2100e07 }, |
| 1913 | { 0x3d400498, 0x620096 }, | 1913 | { 0x3d400498, 0x620096 }, |
| 1914 | { 0x3d40049c, 0x1100e07 }, | 1914 | { 0x3d40049c, 0x1100e07 }, |
| 1915 | { 0x3d4004a0, 0xc8012c }, | 1915 | { 0x3d4004a0, 0xc8012c }, |
| 1916 | { 0x3d402020, 0x1020 }, | 1916 | { 0x3d402020, 0x1020 }, |
| 1917 | { 0x3d402024, 0x30d400 }, | 1917 | { 0x3d402024, 0x30d400 }, |
| 1918 | { 0x3d402050, 0x20d000 }, | 1918 | { 0x3d402050, 0x20d000 }, |
| 1919 | { 0x3d402064, 0x60026 }, | 1919 | { 0x3d402064, 0x60026 }, |
| 1920 | { 0x3d4020dc, 0x840000 }, | 1920 | { 0x3d4020dc, 0x840000 }, |
| 1921 | { 0x3d4020e0, 0x330000 }, | 1921 | { 0x3d4020e0, 0x330000 }, |
| 1922 | { 0x3d4020e8, 0x660048 }, | 1922 | { 0x3d4020e8, 0x660048 }, |
| 1923 | { 0x3d4020ec, 0x160048 }, | 1923 | { 0x3d4020ec, 0x160048 }, |
| 1924 | { 0x3d402100, 0xa040105 }, | 1924 | { 0x3d402100, 0xa040105 }, |
| 1925 | { 0x3d402104, 0x30407 }, | 1925 | { 0x3d402104, 0x30407 }, |
| 1926 | { 0x3d402108, 0x203060b }, | 1926 | { 0x3d402108, 0x203060b }, |
| 1927 | { 0x3d40210c, 0x505000 }, | 1927 | { 0x3d40210c, 0x505000 }, |
| 1928 | { 0x3d402110, 0x2040202 }, | 1928 | { 0x3d402110, 0x2040202 }, |
| 1929 | { 0x3d402114, 0x2030202 }, | 1929 | { 0x3d402114, 0x2030202 }, |
| 1930 | { 0x3d402118, 0x1010004 }, | 1930 | { 0x3d402118, 0x1010004 }, |
| 1931 | { 0x3d40211c, 0x301 }, | 1931 | { 0x3d40211c, 0x301 }, |
| 1932 | { 0x3d402130, 0x20300 }, | 1932 | { 0x3d402130, 0x20300 }, |
| 1933 | { 0x3d402134, 0xa100002 }, | 1933 | { 0x3d402134, 0xa100002 }, |
| 1934 | { 0x3d402138, 0x27 }, | 1934 | { 0x3d402138, 0x27 }, |
| 1935 | { 0x3d402144, 0x14000a }, | 1935 | { 0x3d402144, 0x14000a }, |
| 1936 | { 0x3d402180, 0x640004 }, | 1936 | { 0x3d402180, 0x640004 }, |
| 1937 | { 0x3d402190, 0x3818200 }, | 1937 | { 0x3d402190, 0x3818200 }, |
| 1938 | { 0x3d402194, 0x80303 }, | 1938 | { 0x3d402194, 0x80303 }, |
| 1939 | { 0x3d4021b4, 0x100 }, | 1939 | { 0x3d4021b4, 0x100 }, |
| 1940 | { 0x3d4020f4, 0xc99 }, | 1940 | { 0x3d4020f4, 0xc99 }, |
| 1941 | { 0x3d403020, 0x1020 }, | 1941 | { 0x3d403020, 0x1020 }, |
| 1942 | { 0x3d403024, 0xc3500 }, | 1942 | { 0x3d403024, 0xc3500 }, |
| 1943 | { 0x3d403050, 0x20d000 }, | 1943 | { 0x3d403050, 0x20d000 }, |
| 1944 | { 0x3d403064, 0x3000a }, | 1944 | { 0x3d403064, 0x3000a }, |
| 1945 | { 0x3d4030dc, 0x840000 }, | 1945 | { 0x3d4030dc, 0x840000 }, |
| 1946 | { 0x3d4030e0, 0x330000 }, | 1946 | { 0x3d4030e0, 0x330000 }, |
| 1947 | { 0x3d4030e8, 0x660048 }, | 1947 | { 0x3d4030e8, 0x660048 }, |
| 1948 | { 0x3d4030ec, 0x160048 }, | 1948 | { 0x3d4030ec, 0x160048 }, |
| 1949 | { 0x3d403100, 0xa010102 }, | 1949 | { 0x3d403100, 0xa010102 }, |
| 1950 | { 0x3d403104, 0x30404 }, | 1950 | { 0x3d403104, 0x30404 }, |
| 1951 | { 0x3d403108, 0x203060b }, | 1951 | { 0x3d403108, 0x203060b }, |
| 1952 | { 0x3d40310c, 0x505000 }, | 1952 | { 0x3d40310c, 0x505000 }, |
| 1953 | { 0x3d403110, 0x2040202 }, | 1953 | { 0x3d403110, 0x2040202 }, |
| 1954 | { 0x3d403114, 0x2030202 }, | 1954 | { 0x3d403114, 0x2030202 }, |
| 1955 | { 0x3d403118, 0x1010004 }, | 1955 | { 0x3d403118, 0x1010004 }, |
| 1956 | { 0x3d40311c, 0x301 }, | 1956 | { 0x3d40311c, 0x301 }, |
| 1957 | { 0x3d403130, 0x20300 }, | 1957 | { 0x3d403130, 0x20300 }, |
| 1958 | { 0x3d403134, 0xa100002 }, | 1958 | { 0x3d403134, 0xa100002 }, |
| 1959 | { 0x3d403138, 0xa }, | 1959 | { 0x3d403138, 0xa }, |
| 1960 | { 0x3d403144, 0x50003 }, | 1960 | { 0x3d403144, 0x50003 }, |
| 1961 | { 0x3d403180, 0x190004 }, | 1961 | { 0x3d403180, 0x190004 }, |
| 1962 | { 0x3d403190, 0x3818200 }, | 1962 | { 0x3d403190, 0x3818200 }, |
| 1963 | { 0x3d403194, 0x80303 }, | 1963 | { 0x3d403194, 0x80303 }, |
| 1964 | { 0x3d4031b4, 0x100 }, | 1964 | { 0x3d4031b4, 0x100 }, |
| 1965 | { 0x3d4030f4, 0xc99 }, | 1965 | { 0x3d4030f4, 0xc99 }, |
| 1966 | { 0x3d400028, 0x0 }, | 1966 | { 0x3d400028, 0x0 }, |
| 1967 | }; | 1967 | }; |
| 1968 | 1968 | ||
| 1969 | /* PHY Initialize Configuration */ | 1969 | /* PHY Initialize Configuration */ |
| 1970 | struct dram_cfg_param ddr_ddrphy_cfg[] = { | 1970 | struct dram_cfg_param ddr_ddrphy_cfg[] = { |
| 1971 | { 0x100a0, 0x0 }, | 1971 | { 0x100a0, 0x0 }, |
| 1972 | { 0x100a1, 0x1 }, | 1972 | { 0x100a1, 0x1 }, |
| 1973 | { 0x100a2, 0x2 }, | 1973 | { 0x100a2, 0x2 }, |
| 1974 | { 0x100a3, 0x3 }, | 1974 | { 0x100a3, 0x3 }, |
| 1975 | { 0x100a4, 0x4 }, | 1975 | { 0x100a4, 0x4 }, |
| 1976 | { 0x100a5, 0x5 }, | 1976 | { 0x100a5, 0x5 }, |
| 1977 | { 0x100a6, 0x6 }, | 1977 | { 0x100a6, 0x6 }, |
| 1978 | { 0x100a7, 0x7 }, | 1978 | { 0x100a7, 0x7 }, |
| 1979 | { 0x110a0, 0x0 }, | 1979 | { 0x110a0, 0x0 }, |
| 1980 | { 0x110a1, 0x1 }, | 1980 | { 0x110a1, 0x1 }, |
| 1981 | { 0x110a2, 0x3 }, | 1981 | { 0x110a2, 0x3 }, |
| 1982 | { 0x110a3, 0x4 }, | 1982 | { 0x110a3, 0x4 }, |
| 1983 | { 0x110a4, 0x5 }, | 1983 | { 0x110a4, 0x5 }, |
| 1984 | { 0x110a5, 0x2 }, | 1984 | { 0x110a5, 0x2 }, |
| 1985 | { 0x110a6, 0x7 }, | 1985 | { 0x110a6, 0x7 }, |
| 1986 | { 0x110a7, 0x6 }, | 1986 | { 0x110a7, 0x6 }, |
| 1987 | { 0x120a0, 0x0 }, | 1987 | { 0x120a0, 0x0 }, |
| 1988 | { 0x120a1, 0x1 }, | 1988 | { 0x120a1, 0x1 }, |
| 1989 | { 0x120a2, 0x3 }, | 1989 | { 0x120a2, 0x3 }, |
| 1990 | { 0x120a3, 0x2 }, | 1990 | { 0x120a3, 0x2 }, |
| 1991 | { 0x120a4, 0x5 }, | 1991 | { 0x120a4, 0x5 }, |
| 1992 | { 0x120a5, 0x4 }, | 1992 | { 0x120a5, 0x4 }, |
| 1993 | { 0x120a6, 0x7 }, | 1993 | { 0x120a6, 0x7 }, |
| 1994 | { 0x120a7, 0x6 }, | 1994 | { 0x120a7, 0x6 }, |
| 1995 | { 0x130a0, 0x0 }, | 1995 | { 0x130a0, 0x0 }, |
| 1996 | { 0x130a1, 0x1 }, | 1996 | { 0x130a1, 0x1 }, |
| 1997 | { 0x130a2, 0x2 }, | 1997 | { 0x130a2, 0x2 }, |
| 1998 | { 0x130a3, 0x3 }, | 1998 | { 0x130a3, 0x3 }, |
| 1999 | { 0x130a4, 0x4 }, | 1999 | { 0x130a4, 0x4 }, |
| 2000 | { 0x130a5, 0x5 }, | 2000 | { 0x130a5, 0x5 }, |
| 2001 | { 0x130a6, 0x6 }, | 2001 | { 0x130a6, 0x6 }, |
| 2002 | { 0x130a7, 0x7 }, | 2002 | { 0x130a7, 0x7 }, |
| 2003 | { 0x1005f, 0x1ff }, | 2003 | { 0x1005f, 0x1ff }, |
| 2004 | { 0x1015f, 0x1ff }, | 2004 | { 0x1015f, 0x1ff }, |
| 2005 | { 0x1105f, 0x1ff }, | 2005 | { 0x1105f, 0x1ff }, |
| 2006 | { 0x1115f, 0x1ff }, | 2006 | { 0x1115f, 0x1ff }, |
| 2007 | { 0x1205f, 0x1ff }, | 2007 | { 0x1205f, 0x1ff }, |
| 2008 | { 0x1215f, 0x1ff }, | 2008 | { 0x1215f, 0x1ff }, |
| 2009 | { 0x1305f, 0x1ff }, | 2009 | { 0x1305f, 0x1ff }, |
| 2010 | { 0x1315f, 0x1ff }, | 2010 | { 0x1315f, 0x1ff }, |
| 2011 | { 0x11005f, 0x1ff }, | 2011 | { 0x11005f, 0x1ff }, |
| 2012 | { 0x11015f, 0x1ff }, | 2012 | { 0x11015f, 0x1ff }, |
| 2013 | { 0x11105f, 0x1ff }, | 2013 | { 0x11105f, 0x1ff }, |
| 2014 | { 0x11115f, 0x1ff }, | 2014 | { 0x11115f, 0x1ff }, |
| 2015 | { 0x11205f, 0x1ff }, | 2015 | { 0x11205f, 0x1ff }, |
| 2016 | { 0x11215f, 0x1ff }, | 2016 | { 0x11215f, 0x1ff }, |
| 2017 | { 0x11305f, 0x1ff }, | 2017 | { 0x11305f, 0x1ff }, |
| 2018 | { 0x11315f, 0x1ff }, | 2018 | { 0x11315f, 0x1ff }, |
| 2019 | { 0x21005f, 0x1ff }, | 2019 | { 0x21005f, 0x1ff }, |
| 2020 | { 0x21015f, 0x1ff }, | 2020 | { 0x21015f, 0x1ff }, |
| 2021 | { 0x21105f, 0x1ff }, | 2021 | { 0x21105f, 0x1ff }, |
| 2022 | { 0x21115f, 0x1ff }, | 2022 | { 0x21115f, 0x1ff }, |
| 2023 | { 0x21205f, 0x1ff }, | 2023 | { 0x21205f, 0x1ff }, |
| 2024 | { 0x21215f, 0x1ff }, | 2024 | { 0x21215f, 0x1ff }, |
| 2025 | { 0x21305f, 0x1ff }, | 2025 | { 0x21305f, 0x1ff }, |
| 2026 | { 0x21315f, 0x1ff }, | 2026 | { 0x21315f, 0x1ff }, |
| 2027 | { 0x55, 0x1ff }, | 2027 | { 0x55, 0x1ff }, |
| 2028 | { 0x1055, 0x1ff }, | 2028 | { 0x1055, 0x1ff }, |
| 2029 | { 0x2055, 0x1ff }, | 2029 | { 0x2055, 0x1ff }, |
| 2030 | { 0x3055, 0x1ff }, | 2030 | { 0x3055, 0x1ff }, |
| 2031 | { 0x4055, 0x1ff }, | 2031 | { 0x4055, 0x1ff }, |
| 2032 | { 0x5055, 0x1ff }, | 2032 | { 0x5055, 0x1ff }, |
| 2033 | { 0x6055, 0x1ff }, | 2033 | { 0x6055, 0x1ff }, |
| 2034 | { 0x7055, 0x1ff }, | 2034 | { 0x7055, 0x1ff }, |
| 2035 | { 0x8055, 0x1ff }, | 2035 | { 0x8055, 0x1ff }, |
| 2036 | { 0x9055, 0x1ff }, | 2036 | { 0x9055, 0x1ff }, |
| 2037 | { 0x200c5, 0x18 }, | 2037 | { 0x200c5, 0x18 }, |
| 2038 | { 0x1200c5, 0x7 }, | 2038 | { 0x1200c5, 0x7 }, |
| 2039 | { 0x2200c5, 0x7 }, | 2039 | { 0x2200c5, 0x7 }, |
| 2040 | { 0x2002e, 0x2 }, | 2040 | { 0x2002e, 0x2 }, |
| 2041 | { 0x12002e, 0x2 }, | 2041 | { 0x12002e, 0x2 }, |
| 2042 | { 0x22002e, 0x2 }, | 2042 | { 0x22002e, 0x2 }, |
| 2043 | { 0x90204, 0x0 }, | 2043 | { 0x90204, 0x0 }, |
| 2044 | { 0x190204, 0x0 }, | 2044 | { 0x190204, 0x0 }, |
| 2045 | { 0x290204, 0x0 }, | 2045 | { 0x290204, 0x0 }, |
| 2046 | { 0x20024, 0x1e3 }, | 2046 | { 0x20024, 0x1e3 }, |
| 2047 | { 0x2003a, 0x2 }, | 2047 | { 0x2003a, 0x2 }, |
| 2048 | { 0x120024, 0x1e3 }, | 2048 | { 0x120024, 0x1e3 }, |
| 2049 | { 0x2003a, 0x2 }, | 2049 | { 0x2003a, 0x2 }, |
| 2050 | { 0x220024, 0x1e3 }, | 2050 | { 0x220024, 0x1e3 }, |
| 2051 | { 0x2003a, 0x2 }, | 2051 | { 0x2003a, 0x2 }, |
| 2052 | { 0x20056, 0x3 }, | 2052 | { 0x20056, 0x3 }, |
| 2053 | { 0x120056, 0x3 }, | 2053 | { 0x120056, 0x3 }, |
| 2054 | { 0x220056, 0x3 }, | 2054 | { 0x220056, 0x3 }, |
| 2055 | { 0x1004d, 0xe00 }, | 2055 | { 0x1004d, 0xe00 }, |
| 2056 | { 0x1014d, 0xe00 }, | 2056 | { 0x1014d, 0xe00 }, |
| 2057 | { 0x1104d, 0xe00 }, | 2057 | { 0x1104d, 0xe00 }, |
| 2058 | { 0x1114d, 0xe00 }, | 2058 | { 0x1114d, 0xe00 }, |
| 2059 | { 0x1204d, 0xe00 }, | 2059 | { 0x1204d, 0xe00 }, |
| 2060 | { 0x1214d, 0xe00 }, | 2060 | { 0x1214d, 0xe00 }, |
| 2061 | { 0x1304d, 0xe00 }, | 2061 | { 0x1304d, 0xe00 }, |
| 2062 | { 0x1314d, 0xe00 }, | 2062 | { 0x1314d, 0xe00 }, |
| 2063 | { 0x11004d, 0xe00 }, | 2063 | { 0x11004d, 0xe00 }, |
| 2064 | { 0x11014d, 0xe00 }, | 2064 | { 0x11014d, 0xe00 }, |
| 2065 | { 0x11104d, 0xe00 }, | 2065 | { 0x11104d, 0xe00 }, |
| 2066 | { 0x11114d, 0xe00 }, | 2066 | { 0x11114d, 0xe00 }, |
| 2067 | { 0x11204d, 0xe00 }, | 2067 | { 0x11204d, 0xe00 }, |
| 2068 | { 0x11214d, 0xe00 }, | 2068 | { 0x11214d, 0xe00 }, |
| 2069 | { 0x11304d, 0xe00 }, | 2069 | { 0x11304d, 0xe00 }, |
| 2070 | { 0x11314d, 0xe00 }, | 2070 | { 0x11314d, 0xe00 }, |
| 2071 | { 0x21004d, 0xe00 }, | 2071 | { 0x21004d, 0xe00 }, |
| 2072 | { 0x21014d, 0xe00 }, | 2072 | { 0x21014d, 0xe00 }, |
| 2073 | { 0x21104d, 0xe00 }, | 2073 | { 0x21104d, 0xe00 }, |
| 2074 | { 0x21114d, 0xe00 }, | 2074 | { 0x21114d, 0xe00 }, |
| 2075 | { 0x21204d, 0xe00 }, | 2075 | { 0x21204d, 0xe00 }, |
| 2076 | { 0x21214d, 0xe00 }, | 2076 | { 0x21214d, 0xe00 }, |
| 2077 | { 0x21304d, 0xe00 }, | 2077 | { 0x21304d, 0xe00 }, |
| 2078 | { 0x21314d, 0xe00 }, | 2078 | { 0x21314d, 0xe00 }, |
| 2079 | { 0x10049, 0xeba }, | 2079 | { 0x10049, 0xeba }, |
| 2080 | { 0x10149, 0xeba }, | 2080 | { 0x10149, 0xeba }, |
| 2081 | { 0x11049, 0xeba }, | 2081 | { 0x11049, 0xeba }, |
| 2082 | { 0x11149, 0xeba }, | 2082 | { 0x11149, 0xeba }, |
| 2083 | { 0x12049, 0xeba }, | 2083 | { 0x12049, 0xeba }, |
| 2084 | { 0x12149, 0xeba }, | 2084 | { 0x12149, 0xeba }, |
| 2085 | { 0x13049, 0xeba }, | 2085 | { 0x13049, 0xeba }, |
| 2086 | { 0x13149, 0xeba }, | 2086 | { 0x13149, 0xeba }, |
| 2087 | { 0x110049, 0xeba }, | 2087 | { 0x110049, 0xeba }, |
| 2088 | { 0x110149, 0xeba }, | 2088 | { 0x110149, 0xeba }, |
| 2089 | { 0x111049, 0xeba }, | 2089 | { 0x111049, 0xeba }, |
| 2090 | { 0x111149, 0xeba }, | 2090 | { 0x111149, 0xeba }, |
| 2091 | { 0x112049, 0xeba }, | 2091 | { 0x112049, 0xeba }, |
| 2092 | { 0x112149, 0xeba }, | 2092 | { 0x112149, 0xeba }, |
| 2093 | { 0x113049, 0xeba }, | 2093 | { 0x113049, 0xeba }, |
| 2094 | { 0x113149, 0xeba }, | 2094 | { 0x113149, 0xeba }, |
| 2095 | { 0x210049, 0xeba }, | 2095 | { 0x210049, 0xeba }, |
| 2096 | { 0x210149, 0xeba }, | 2096 | { 0x210149, 0xeba }, |
| 2097 | { 0x211049, 0xeba }, | 2097 | { 0x211049, 0xeba }, |
| 2098 | { 0x211149, 0xeba }, | 2098 | { 0x211149, 0xeba }, |
| 2099 | { 0x212049, 0xeba }, | 2099 | { 0x212049, 0xeba }, |
| 2100 | { 0x212149, 0xeba }, | 2100 | { 0x212149, 0xeba }, |
| 2101 | { 0x213049, 0xeba }, | 2101 | { 0x213049, 0xeba }, |
| 2102 | { 0x213149, 0xeba }, | 2102 | { 0x213149, 0xeba }, |
| 2103 | { 0x43, 0x63 }, | 2103 | { 0x43, 0x63 }, |
| 2104 | { 0x1043, 0x63 }, | 2104 | { 0x1043, 0x63 }, |
| 2105 | { 0x2043, 0x63 }, | 2105 | { 0x2043, 0x63 }, |
| 2106 | { 0x3043, 0x63 }, | 2106 | { 0x3043, 0x63 }, |
| 2107 | { 0x4043, 0x63 }, | 2107 | { 0x4043, 0x63 }, |
| 2108 | { 0x5043, 0x63 }, | 2108 | { 0x5043, 0x63 }, |
| 2109 | { 0x6043, 0x63 }, | 2109 | { 0x6043, 0x63 }, |
| 2110 | { 0x7043, 0x63 }, | 2110 | { 0x7043, 0x63 }, |
| 2111 | { 0x8043, 0x63 }, | 2111 | { 0x8043, 0x63 }, |
| 2112 | { 0x9043, 0x63 }, | 2112 | { 0x9043, 0x63 }, |
| 2113 | { 0x20018, 0x3 }, | 2113 | { 0x20018, 0x3 }, |
| 2114 | { 0x20075, 0x4 }, | 2114 | { 0x20075, 0x4 }, |
| 2115 | { 0x20050, 0x0 }, | 2115 | { 0x20050, 0x0 }, |
| 2116 | { 0x20008, 0x3e8 }, | 2116 | { 0x20008, 0x3e8 }, |
| 2117 | { 0x120008, 0x64 }, | 2117 | { 0x120008, 0x64 }, |
| 2118 | { 0x220008, 0x19 }, | 2118 | { 0x220008, 0x19 }, |
| 2119 | { 0x20088, 0x9 }, | 2119 | { 0x20088, 0x9 }, |
| 2120 | { 0x200b2, 0x104 }, | 2120 | { 0x200b2, 0x104 }, |
| 2121 | { 0x10043, 0x5a1 }, | 2121 | { 0x10043, 0x5a1 }, |
| 2122 | { 0x10143, 0x5a1 }, | 2122 | { 0x10143, 0x5a1 }, |
| 2123 | { 0x11043, 0x5a1 }, | 2123 | { 0x11043, 0x5a1 }, |
| 2124 | { 0x11143, 0x5a1 }, | 2124 | { 0x11143, 0x5a1 }, |
| 2125 | { 0x12043, 0x5a1 }, | 2125 | { 0x12043, 0x5a1 }, |
| 2126 | { 0x12143, 0x5a1 }, | 2126 | { 0x12143, 0x5a1 }, |
| 2127 | { 0x13043, 0x5a1 }, | 2127 | { 0x13043, 0x5a1 }, |
| 2128 | { 0x13143, 0x5a1 }, | 2128 | { 0x13143, 0x5a1 }, |
| 2129 | { 0x1200b2, 0x104 }, | 2129 | { 0x1200b2, 0x104 }, |
| 2130 | { 0x110043, 0x5a1 }, | 2130 | { 0x110043, 0x5a1 }, |
| 2131 | { 0x110143, 0x5a1 }, | 2131 | { 0x110143, 0x5a1 }, |
| 2132 | { 0x111043, 0x5a1 }, | 2132 | { 0x111043, 0x5a1 }, |
| 2133 | { 0x111143, 0x5a1 }, | 2133 | { 0x111143, 0x5a1 }, |
| 2134 | { 0x112043, 0x5a1 }, | 2134 | { 0x112043, 0x5a1 }, |
| 2135 | { 0x112143, 0x5a1 }, | 2135 | { 0x112143, 0x5a1 }, |
| 2136 | { 0x113043, 0x5a1 }, | 2136 | { 0x113043, 0x5a1 }, |
| 2137 | { 0x113143, 0x5a1 }, | 2137 | { 0x113143, 0x5a1 }, |
| 2138 | { 0x2200b2, 0x104 }, | 2138 | { 0x2200b2, 0x104 }, |
| 2139 | { 0x210043, 0x5a1 }, | 2139 | { 0x210043, 0x5a1 }, |
| 2140 | { 0x210143, 0x5a1 }, | 2140 | { 0x210143, 0x5a1 }, |
| 2141 | { 0x211043, 0x5a1 }, | 2141 | { 0x211043, 0x5a1 }, |
| 2142 | { 0x211143, 0x5a1 }, | 2142 | { 0x211143, 0x5a1 }, |
| 2143 | { 0x212043, 0x5a1 }, | 2143 | { 0x212043, 0x5a1 }, |
| 2144 | { 0x212143, 0x5a1 }, | 2144 | { 0x212143, 0x5a1 }, |
| 2145 | { 0x213043, 0x5a1 }, | 2145 | { 0x213043, 0x5a1 }, |
| 2146 | { 0x213143, 0x5a1 }, | 2146 | { 0x213143, 0x5a1 }, |
| 2147 | { 0x200fa, 0x1 }, | 2147 | { 0x200fa, 0x1 }, |
| 2148 | { 0x1200fa, 0x1 }, | 2148 | { 0x1200fa, 0x1 }, |
| 2149 | { 0x2200fa, 0x1 }, | 2149 | { 0x2200fa, 0x1 }, |
| 2150 | { 0x20019, 0x1 }, | 2150 | { 0x20019, 0x1 }, |
| 2151 | { 0x120019, 0x1 }, | 2151 | { 0x120019, 0x1 }, |
| 2152 | { 0x220019, 0x1 }, | 2152 | { 0x220019, 0x1 }, |
| 2153 | { 0x200f0, 0x660 }, | 2153 | { 0x200f0, 0x660 }, |
| 2154 | { 0x200f1, 0x0 }, | 2154 | { 0x200f1, 0x0 }, |
| 2155 | { 0x200f2, 0x4444 }, | 2155 | { 0x200f2, 0x4444 }, |
| 2156 | { 0x200f3, 0x8888 }, | 2156 | { 0x200f3, 0x8888 }, |
| 2157 | { 0x200f4, 0x5665 }, | 2157 | { 0x200f4, 0x5665 }, |
| 2158 | { 0x200f5, 0x0 }, | 2158 | { 0x200f5, 0x0 }, |
| 2159 | { 0x200f6, 0x0 }, | 2159 | { 0x200f6, 0x0 }, |
| 2160 | { 0x200f7, 0xf000 }, | 2160 | { 0x200f7, 0xf000 }, |
| 2161 | { 0x20025, 0x0 }, | 2161 | { 0x20025, 0x0 }, |
| 2162 | { 0x2002d, 0x0 }, | 2162 | { 0x2002d, 0x0 }, |
| 2163 | { 0x12002d, 0x0 }, | 2163 | { 0x12002d, 0x0 }, |
| 2164 | { 0x22002d, 0x0 }, | 2164 | { 0x22002d, 0x0 }, |
| 2165 | { 0x2007d, 0x212 }, | 2165 | { 0x2007d, 0x212 }, |
| 2166 | { 0x12007d, 0x212 }, | 2166 | { 0x12007d, 0x212 }, |
| 2167 | { 0x22007d, 0x212 }, | 2167 | { 0x22007d, 0x212 }, |
| 2168 | { 0x2007c, 0x61 }, | 2168 | { 0x2007c, 0x61 }, |
| 2169 | { 0x12007c, 0x61 }, | 2169 | { 0x12007c, 0x61 }, |
| 2170 | { 0x22007c, 0x61 }, | 2170 | { 0x22007c, 0x61 }, |
| 2171 | { 0x1004a, 0x500 }, | 2171 | { 0x1004a, 0x500 }, |
| 2172 | { 0x1104a, 0x500 }, | 2172 | { 0x1104a, 0x500 }, |
| 2173 | { 0x1204a, 0x500 }, | 2173 | { 0x1204a, 0x500 }, |
| 2174 | { 0x1304a, 0x500 }, | 2174 | { 0x1304a, 0x500 }, |
| 2175 | { 0x2002c, 0x0 }, | 2175 | { 0x2002c, 0x0 }, |
| 2176 | }; | 2176 | }; |
| 2177 | ^M | 2177 | |
| 2178 | /* ddr phy trained csr */ | 2178 | /* ddr phy trained csr */ |
| 2179 | struct dram_cfg_param ddr_ddrphy_trained_csr[] = { | 2179 | struct dram_cfg_param ddr_ddrphy_trained_csr[] = { |
| 2180 | { 0x200b2, 0x0 }, | 2180 | { 0x200b2, 0x0 }, |
| 2181 | { 0x1200b2, 0x0 }, | 2181 | { 0x1200b2, 0x0 }, |
| 2182 | { 0x2200b2, 0x0 }, | 2182 | { 0x2200b2, 0x0 }, |
| 2183 | { 0x200cb, 0x0 }, | 2183 | { 0x200cb, 0x0 }, |
| 2184 | { 0x10043, 0x0 }, | 2184 | { 0x10043, 0x0 }, |
| 2185 | { 0x110043, 0x0 }, | 2185 | { 0x110043, 0x0 }, |
| 2186 | { 0x210043, 0x0 }, | 2186 | { 0x210043, 0x0 }, |
| 2187 | { 0x10143, 0x0 }, | 2187 | { 0x10143, 0x0 }, |
| 2188 | { 0x110143, 0x0 }, | 2188 | { 0x110143, 0x0 }, |
| 2189 | { 0x210143, 0x0 }, | 2189 | { 0x210143, 0x0 }, |
| 2190 | { 0x11043, 0x0 }, | 2190 | { 0x11043, 0x0 }, |
| 2191 | { 0x111043, 0x0 }, | 2191 | { 0x111043, 0x0 }, |
| 2192 | { 0x211043, 0x0 }, | 2192 | { 0x211043, 0x0 }, |
| 2193 | { 0x11143, 0x0 }, | 2193 | { 0x11143, 0x0 }, |
| 2194 | { 0x111143, 0x0 }, | 2194 | { 0x111143, 0x0 }, |
| 2195 | { 0x211143, 0x0 }, | 2195 | { 0x211143, 0x0 }, |
| 2196 | { 0x12043, 0x0 }, | 2196 | { 0x12043, 0x0 }, |
| 2197 | { 0x112043, 0x0 }, | 2197 | { 0x112043, 0x0 }, |
| 2198 | { 0x212043, 0x0 }, | 2198 | { 0x212043, 0x0 }, |
| 2199 | { 0x12143, 0x0 }, | 2199 | { 0x12143, 0x0 }, |
| 2200 | { 0x112143, 0x0 }, | 2200 | { 0x112143, 0x0 }, |
| 2201 | { 0x212143, 0x0 }, | 2201 | { 0x212143, 0x0 }, |
| 2202 | { 0x13043, 0x0 }, | 2202 | { 0x13043, 0x0 }, |
| 2203 | { 0x113043, 0x0 }, | 2203 | { 0x113043, 0x0 }, |
| 2204 | { 0x213043, 0x0 }, | 2204 | { 0x213043, 0x0 }, |
| 2205 | { 0x13143, 0x0 }, | 2205 | { 0x13143, 0x0 }, |
| 2206 | { 0x113143, 0x0 }, | 2206 | { 0x113143, 0x0 }, |
| 2207 | { 0x213143, 0x0 }, | 2207 | { 0x213143, 0x0 }, |
| 2208 | { 0x80, 0x0 }, | 2208 | { 0x80, 0x0 }, |
| 2209 | { 0x100080, 0x0 }, | 2209 | { 0x100080, 0x0 }, |
| 2210 | { 0x200080, 0x0 }, | 2210 | { 0x200080, 0x0 }, |
| 2211 | { 0x1080, 0x0 }, | 2211 | { 0x1080, 0x0 }, |
| 2212 | { 0x101080, 0x0 }, | 2212 | { 0x101080, 0x0 }, |
| 2213 | { 0x201080, 0x0 }, | 2213 | { 0x201080, 0x0 }, |
| 2214 | { 0x2080, 0x0 }, | 2214 | { 0x2080, 0x0 }, |
| 2215 | { 0x102080, 0x0 }, | 2215 | { 0x102080, 0x0 }, |
| 2216 | { 0x202080, 0x0 }, | 2216 | { 0x202080, 0x0 }, |
| 2217 | { 0x3080, 0x0 }, | 2217 | { 0x3080, 0x0 }, |
| 2218 | { 0x103080, 0x0 }, | 2218 | { 0x103080, 0x0 }, |
| 2219 | { 0x203080, 0x0 }, | 2219 | { 0x203080, 0x0 }, |
| 2220 | { 0x4080, 0x0 }, | 2220 | { 0x4080, 0x0 }, |
| 2221 | { 0x104080, 0x0 }, | 2221 | { 0x104080, 0x0 }, |
| 2222 | { 0x204080, 0x0 }, | 2222 | { 0x204080, 0x0 }, |
| 2223 | { 0x5080, 0x0 }, | 2223 | { 0x5080, 0x0 }, |
| 2224 | { 0x105080, 0x0 }, | 2224 | { 0x105080, 0x0 }, |
| 2225 | { 0x205080, 0x0 }, | 2225 | { 0x205080, 0x0 }, |
| 2226 | { 0x6080, 0x0 }, | 2226 | { 0x6080, 0x0 }, |
| 2227 | { 0x106080, 0x0 }, | 2227 | { 0x106080, 0x0 }, |
| 2228 | { 0x206080, 0x0 }, | 2228 | { 0x206080, 0x0 }, |
| 2229 | { 0x7080, 0x0 }, | 2229 | { 0x7080, 0x0 }, |
| 2230 | { 0x107080, 0x0 }, | 2230 | { 0x107080, 0x0 }, |
| 2231 | { 0x207080, 0x0 }, | 2231 | { 0x207080, 0x0 }, |
| 2232 | { 0x8080, 0x0 }, | 2232 | { 0x8080, 0x0 }, |
| 2233 | { 0x108080, 0x0 }, | 2233 | { 0x108080, 0x0 }, |
| 2234 | { 0x208080, 0x0 }, | 2234 | { 0x208080, 0x0 }, |
| 2235 | { 0x9080, 0x0 }, | 2235 | { 0x9080, 0x0 }, |
| 2236 | { 0x109080, 0x0 }, | 2236 | { 0x109080, 0x0 }, |
| 2237 | { 0x209080, 0x0 }, | 2237 | { 0x209080, 0x0 }, |
| 2238 | { 0x10080, 0x0 }, | 2238 | { 0x10080, 0x0 }, |
| 2239 | { 0x110080, 0x0 }, | 2239 | { 0x110080, 0x0 }, |
| 2240 | { 0x210080, 0x0 }, | 2240 | { 0x210080, 0x0 }, |
| 2241 | { 0x10180, 0x0 }, | 2241 | { 0x10180, 0x0 }, |
| 2242 | { 0x110180, 0x0 }, | 2242 | { 0x110180, 0x0 }, |
| 2243 | { 0x210180, 0x0 }, | 2243 | { 0x210180, 0x0 }, |
| 2244 | { 0x11080, 0x0 }, | 2244 | { 0x11080, 0x0 }, |
| 2245 | { 0x111080, 0x0 }, | 2245 | { 0x111080, 0x0 }, |
| 2246 | { 0x211080, 0x0 }, | 2246 | { 0x211080, 0x0 }, |
| 2247 | { 0x11180, 0x0 }, | 2247 | { 0x11180, 0x0 }, |
| 2248 | { 0x111180, 0x0 }, | 2248 | { 0x111180, 0x0 }, |
| 2249 | { 0x211180, 0x0 }, | 2249 | { 0x211180, 0x0 }, |
| 2250 | { 0x12080, 0x0 }, | 2250 | { 0x12080, 0x0 }, |
| 2251 | { 0x112080, 0x0 }, | 2251 | { 0x112080, 0x0 }, |
| 2252 | { 0x212080, 0x0 }, | 2252 | { 0x212080, 0x0 }, |
| 2253 | { 0x12180, 0x0 }, | 2253 | { 0x12180, 0x0 }, |
| 2254 | { 0x112180, 0x0 }, | 2254 | { 0x112180, 0x0 }, |
| 2255 | { 0x212180, 0x0 }, | 2255 | { 0x212180, 0x0 }, |
| 2256 | { 0x13080, 0x0 }, | 2256 | { 0x13080, 0x0 }, |
| 2257 | { 0x113080, 0x0 }, | 2257 | { 0x113080, 0x0 }, |
| 2258 | { 0x213080, 0x0 }, | 2258 | { 0x213080, 0x0 }, |
| 2259 | { 0x13180, 0x0 }, | 2259 | { 0x13180, 0x0 }, |
| 2260 | { 0x113180, 0x0 }, | 2260 | { 0x113180, 0x0 }, |
| 2261 | { 0x213180, 0x0 }, | 2261 | { 0x213180, 0x0 }, |
| 2262 | { 0x10081, 0x0 }, | 2262 | { 0x10081, 0x0 }, |
| 2263 | { 0x110081, 0x0 }, | 2263 | { 0x110081, 0x0 }, |
| 2264 | { 0x210081, 0x0 }, | 2264 | { 0x210081, 0x0 }, |
| 2265 | { 0x10181, 0x0 }, | 2265 | { 0x10181, 0x0 }, |
| 2266 | { 0x110181, 0x0 }, | 2266 | { 0x110181, 0x0 }, |
| 2267 | { 0x210181, 0x0 }, | 2267 | { 0x210181, 0x0 }, |
| 2268 | { 0x11081, 0x0 }, | 2268 | { 0x11081, 0x0 }, |
| 2269 | { 0x111081, 0x0 }, | 2269 | { 0x111081, 0x0 }, |
| 2270 | { 0x211081, 0x0 }, | 2270 | { 0x211081, 0x0 }, |
| 2271 | { 0x11181, 0x0 }, | 2271 | { 0x11181, 0x0 }, |
| 2272 | { 0x111181, 0x0 }, | 2272 | { 0x111181, 0x0 }, |
| 2273 | { 0x211181, 0x0 }, | 2273 | { 0x211181, 0x0 }, |
| 2274 | { 0x12081, 0x0 }, | 2274 | { 0x12081, 0x0 }, |
| 2275 | { 0x112081, 0x0 }, | 2275 | { 0x112081, 0x0 }, |
| 2276 | { 0x212081, 0x0 }, | 2276 | { 0x212081, 0x0 }, |
| 2277 | { 0x12181, 0x0 }, | 2277 | { 0x12181, 0x0 }, |
| 2278 | { 0x112181, 0x0 }, | 2278 | { 0x112181, 0x0 }, |
| 2279 | { 0x212181, 0x0 }, | 2279 | { 0x212181, 0x0 }, |
| 2280 | { 0x13081, 0x0 }, | 2280 | { 0x13081, 0x0 }, |
| 2281 | { 0x113081, 0x0 }, | 2281 | { 0x113081, 0x0 }, |
| 2282 | { 0x213081, 0x0 }, | 2282 | { 0x213081, 0x0 }, |
| 2283 | { 0x13181, 0x0 }, | 2283 | { 0x13181, 0x0 }, |
| 2284 | { 0x113181, 0x0 }, | 2284 | { 0x113181, 0x0 }, |
| 2285 | { 0x213181, 0x0 }, | 2285 | { 0x213181, 0x0 }, |
| 2286 | { 0x100d0, 0x0 }, | 2286 | { 0x100d0, 0x0 }, |
| 2287 | { 0x1100d0, 0x0 }, | 2287 | { 0x1100d0, 0x0 }, |
| 2288 | { 0x2100d0, 0x0 }, | 2288 | { 0x2100d0, 0x0 }, |
| 2289 | { 0x101d0, 0x0 }, | 2289 | { 0x101d0, 0x0 }, |
| 2290 | { 0x1101d0, 0x0 }, | 2290 | { 0x1101d0, 0x0 }, |
| 2291 | { 0x2101d0, 0x0 }, | 2291 | { 0x2101d0, 0x0 }, |
| 2292 | { 0x110d0, 0x0 }, | 2292 | { 0x110d0, 0x0 }, |
| 2293 | { 0x1110d0, 0x0 }, | 2293 | { 0x1110d0, 0x0 }, |
| 2294 | { 0x2110d0, 0x0 }, | 2294 | { 0x2110d0, 0x0 }, |
| 2295 | { 0x111d0, 0x0 }, | 2295 | { 0x111d0, 0x0 }, |
| 2296 | { 0x1111d0, 0x0 }, | 2296 | { 0x1111d0, 0x0 }, |
| 2297 | { 0x2111d0, 0x0 }, | 2297 | { 0x2111d0, 0x0 }, |
| 2298 | { 0x120d0, 0x0 }, | 2298 | { 0x120d0, 0x0 }, |
| 2299 | { 0x1120d0, 0x0 }, | 2299 | { 0x1120d0, 0x0 }, |
| 2300 | { 0x2120d0, 0x0 }, | 2300 | { 0x2120d0, 0x0 }, |
| 2301 | { 0x121d0, 0x0 }, | 2301 | { 0x121d0, 0x0 }, |
| 2302 | { 0x1121d0, 0x0 }, | 2302 | { 0x1121d0, 0x0 }, |
| 2303 | { 0x2121d0, 0x0 }, | 2303 | { 0x2121d0, 0x0 }, |
| 2304 | { 0x130d0, 0x0 }, | 2304 | { 0x130d0, 0x0 }, |
| 2305 | { 0x1130d0, 0x0 }, | 2305 | { 0x1130d0, 0x0 }, |
| 2306 | { 0x2130d0, 0x0 }, | 2306 | { 0x2130d0, 0x0 }, |
| 2307 | { 0x131d0, 0x0 }, | 2307 | { 0x131d0, 0x0 }, |
| 2308 | { 0x1131d0, 0x0 }, | 2308 | { 0x1131d0, 0x0 }, |
| 2309 | { 0x2131d0, 0x0 }, | 2309 | { 0x2131d0, 0x0 }, |
| 2310 | { 0x100d1, 0x0 }, | 2310 | { 0x100d1, 0x0 }, |
| 2311 | { 0x1100d1, 0x0 }, | 2311 | { 0x1100d1, 0x0 }, |
| 2312 | { 0x2100d1, 0x0 }, | 2312 | { 0x2100d1, 0x0 }, |
| 2313 | { 0x101d1, 0x0 }, | 2313 | { 0x101d1, 0x0 }, |
| 2314 | { 0x1101d1, 0x0 }, | 2314 | { 0x1101d1, 0x0 }, |
| 2315 | { 0x2101d1, 0x0 }, | 2315 | { 0x2101d1, 0x0 }, |
| 2316 | { 0x110d1, 0x0 }, | 2316 | { 0x110d1, 0x0 }, |
| 2317 | { 0x1110d1, 0x0 }, | 2317 | { 0x1110d1, 0x0 }, |
| 2318 | { 0x2110d1, 0x0 }, | 2318 | { 0x2110d1, 0x0 }, |
| 2319 | { 0x111d1, 0x0 }, | 2319 | { 0x111d1, 0x0 }, |
| 2320 | { 0x1111d1, 0x0 }, | 2320 | { 0x1111d1, 0x0 }, |
| 2321 | { 0x2111d1, 0x0 }, | 2321 | { 0x2111d1, 0x0 }, |
| 2322 | { 0x120d1, 0x0 }, | 2322 | { 0x120d1, 0x0 }, |
| 2323 | { 0x1120d1, 0x0 }, | 2323 | { 0x1120d1, 0x0 }, |
| 2324 | { 0x2120d1, 0x0 }, | 2324 | { 0x2120d1, 0x0 }, |
| 2325 | { 0x121d1, 0x0 }, | 2325 | { 0x121d1, 0x0 }, |
| 2326 | { 0x1121d1, 0x0 }, | 2326 | { 0x1121d1, 0x0 }, |
| 2327 | { 0x2121d1, 0x0 }, | 2327 | { 0x2121d1, 0x0 }, |
| 2328 | { 0x130d1, 0x0 }, | 2328 | { 0x130d1, 0x0 }, |
| 2329 | { 0x1130d1, 0x0 }, | 2329 | { 0x1130d1, 0x0 }, |
| 2330 | { 0x2130d1, 0x0 }, | 2330 | { 0x2130d1, 0x0 }, |
| 2331 | { 0x131d1, 0x0 }, | 2331 | { 0x131d1, 0x0 }, |
| 2332 | { 0x1131d1, 0x0 }, | 2332 | { 0x1131d1, 0x0 }, |
| 2333 | { 0x2131d1, 0x0 }, | 2333 | { 0x2131d1, 0x0 }, |
| 2334 | { 0x10068, 0x0 }, | 2334 | { 0x10068, 0x0 }, |
| 2335 | { 0x10168, 0x0 }, | 2335 | { 0x10168, 0x0 }, |
| 2336 | { 0x10268, 0x0 }, | 2336 | { 0x10268, 0x0 }, |
| 2337 | { 0x10368, 0x0 }, | 2337 | { 0x10368, 0x0 }, |
| 2338 | { 0x10468, 0x0 }, | 2338 | { 0x10468, 0x0 }, |
| 2339 | { 0x10568, 0x0 }, | 2339 | { 0x10568, 0x0 }, |
| 2340 | { 0x10668, 0x0 }, | 2340 | { 0x10668, 0x0 }, |
| 2341 | { 0x10768, 0x0 }, | 2341 | { 0x10768, 0x0 }, |
| 2342 | { 0x10868, 0x0 }, | 2342 | { 0x10868, 0x0 }, |
| 2343 | { 0x11068, 0x0 }, | 2343 | { 0x11068, 0x0 }, |
| 2344 | { 0x11168, 0x0 }, | 2344 | { 0x11168, 0x0 }, |
| 2345 | { 0x11268, 0x0 }, | 2345 | { 0x11268, 0x0 }, |
| 2346 | { 0x11368, 0x0 }, | 2346 | { 0x11368, 0x0 }, |
| 2347 | { 0x11468, 0x0 }, | 2347 | { 0x11468, 0x0 }, |
| 2348 | { 0x11568, 0x0 }, | 2348 | { 0x11568, 0x0 }, |
| 2349 | { 0x11668, 0x0 }, | 2349 | { 0x11668, 0x0 }, |
| 2350 | { 0x11768, 0x0 }, | 2350 | { 0x11768, 0x0 }, |
| 2351 | { 0x11868, 0x0 }, | 2351 | { 0x11868, 0x0 }, |
| 2352 | { 0x12068, 0x0 }, | 2352 | { 0x12068, 0x0 }, |
| 2353 | { 0x12168, 0x0 }, | 2353 | { 0x12168, 0x0 }, |
| 2354 | { 0x12268, 0x0 }, | 2354 | { 0x12268, 0x0 }, |
| 2355 | { 0x12368, 0x0 }, | 2355 | { 0x12368, 0x0 }, |
| 2356 | { 0x12468, 0x0 }, | 2356 | { 0x12468, 0x0 }, |
| 2357 | { 0x12568, 0x0 }, | 2357 | { 0x12568, 0x0 }, |
| 2358 | { 0x12668, 0x0 }, | 2358 | { 0x12668, 0x0 }, |
| 2359 | { 0x12768, 0x0 }, | 2359 | { 0x12768, 0x0 }, |
| 2360 | { 0x12868, 0x0 }, | 2360 | { 0x12868, 0x0 }, |
| 2361 | { 0x13068, 0x0 }, | 2361 | { 0x13068, 0x0 }, |
| 2362 | { 0x13168, 0x0 }, | 2362 | { 0x13168, 0x0 }, |
| 2363 | { 0x13268, 0x0 }, | 2363 | { 0x13268, 0x0 }, |
| 2364 | { 0x13368, 0x0 }, | 2364 | { 0x13368, 0x0 }, |
| 2365 | { 0x13468, 0x0 }, | 2365 | { 0x13468, 0x0 }, |
| 2366 | { 0x13568, 0x0 }, | 2366 | { 0x13568, 0x0 }, |
| 2367 | { 0x13668, 0x0 }, | 2367 | { 0x13668, 0x0 }, |
| 2368 | { 0x13768, 0x0 }, | 2368 | { 0x13768, 0x0 }, |
| 2369 | { 0x13868, 0x0 }, | 2369 | { 0x13868, 0x0 }, |
| 2370 | { 0x10069, 0x0 }, | 2370 | { 0x10069, 0x0 }, |
| 2371 | { 0x10169, 0x0 }, | 2371 | { 0x10169, 0x0 }, |
| 2372 | { 0x10269, 0x0 }, | 2372 | { 0x10269, 0x0 }, |
| 2373 | { 0x10369, 0x0 }, | 2373 | { 0x10369, 0x0 }, |
| 2374 | { 0x10469, 0x0 }, | 2374 | { 0x10469, 0x0 }, |
| 2375 | { 0x10569, 0x0 }, | 2375 | { 0x10569, 0x0 }, |
| 2376 | { 0x10669, 0x0 }, | 2376 | { 0x10669, 0x0 }, |
| 2377 | { 0x10769, 0x0 }, | 2377 | { 0x10769, 0x0 }, |
| 2378 | { 0x10869, 0x0 }, | 2378 | { 0x10869, 0x0 }, |
| 2379 | { 0x11069, 0x0 }, | 2379 | { 0x11069, 0x0 }, |
| 2380 | { 0x11169, 0x0 }, | 2380 | { 0x11169, 0x0 }, |
| 2381 | { 0x11269, 0x0 }, | 2381 | { 0x11269, 0x0 }, |
| 2382 | { 0x11369, 0x0 }, | 2382 | { 0x11369, 0x0 }, |
| 2383 | { 0x11469, 0x0 }, | 2383 | { 0x11469, 0x0 }, |
| 2384 | { 0x11569, 0x0 }, | 2384 | { 0x11569, 0x0 }, |
| 2385 | { 0x11669, 0x0 }, | 2385 | { 0x11669, 0x0 }, |
| 2386 | { 0x11769, 0x0 }, | 2386 | { 0x11769, 0x0 }, |
| 2387 | { 0x11869, 0x0 }, | 2387 | { 0x11869, 0x0 }, |
| 2388 | { 0x12069, 0x0 }, | 2388 | { 0x12069, 0x0 }, |
| 2389 | { 0x12169, 0x0 }, | 2389 | { 0x12169, 0x0 }, |
| 2390 | { 0x12269, 0x0 }, | 2390 | { 0x12269, 0x0 }, |
| 2391 | { 0x12369, 0x0 }, | 2391 | { 0x12369, 0x0 }, |
| 2392 | { 0x12469, 0x0 }, | 2392 | { 0x12469, 0x0 }, |
| 2393 | { 0x12569, 0x0 }, | 2393 | { 0x12569, 0x0 }, |
| 2394 | { 0x12669, 0x0 }, | 2394 | { 0x12669, 0x0 }, |
| 2395 | { 0x12769, 0x0 }, | 2395 | { 0x12769, 0x0 }, |
| 2396 | { 0x12869, 0x0 }, | 2396 | { 0x12869, 0x0 }, |
| 2397 | { 0x13069, 0x0 }, | 2397 | { 0x13069, 0x0 }, |
| 2398 | { 0x13169, 0x0 }, | 2398 | { 0x13169, 0x0 }, |
| 2399 | { 0x13269, 0x0 }, | 2399 | { 0x13269, 0x0 }, |
| 2400 | { 0x13369, 0x0 }, | 2400 | { 0x13369, 0x0 }, |
| 2401 | { 0x13469, 0x0 }, | 2401 | { 0x13469, 0x0 }, |
| 2402 | { 0x13569, 0x0 }, | 2402 | { 0x13569, 0x0 }, |
| 2403 | { 0x13669, 0x0 }, | 2403 | { 0x13669, 0x0 }, |
| 2404 | { 0x13769, 0x0 }, | 2404 | { 0x13769, 0x0 }, |
| 2405 | { 0x13869, 0x0 }, | 2405 | { 0x13869, 0x0 }, |
| 2406 | { 0x1008c, 0x0 }, | 2406 | { 0x1008c, 0x0 }, |
| 2407 | { 0x11008c, 0x0 }, | 2407 | { 0x11008c, 0x0 }, |
| 2408 | { 0x21008c, 0x0 }, | 2408 | { 0x21008c, 0x0 }, |
| 2409 | { 0x1018c, 0x0 }, | 2409 | { 0x1018c, 0x0 }, |
| 2410 | { 0x11018c, 0x0 }, | 2410 | { 0x11018c, 0x0 }, |
| 2411 | { 0x21018c, 0x0 }, | 2411 | { 0x21018c, 0x0 }, |
| 2412 | { 0x1108c, 0x0 }, | 2412 | { 0x1108c, 0x0 }, |
| 2413 | { 0x11108c, 0x0 }, | 2413 | { 0x11108c, 0x0 }, |
| 2414 | { 0x21108c, 0x0 }, | 2414 | { 0x21108c, 0x0 }, |
| 2415 | { 0x1118c, 0x0 }, | 2415 | { 0x1118c, 0x0 }, |
| 2416 | { 0x11118c, 0x0 }, | 2416 | { 0x11118c, 0x0 }, |
| 2417 | { 0x21118c, 0x0 }, | 2417 | { 0x21118c, 0x0 }, |
| 2418 | { 0x1208c, 0x0 }, | 2418 | { 0x1208c, 0x0 }, |
| 2419 | { 0x11208c, 0x0 }, | 2419 | { 0x11208c, 0x0 }, |
| 2420 | { 0x21208c, 0x0 }, | 2420 | { 0x21208c, 0x0 }, |
| 2421 | { 0x1218c, 0x0 }, | 2421 | { 0x1218c, 0x0 }, |
| 2422 | { 0x11218c, 0x0 }, | 2422 | { 0x11218c, 0x0 }, |
| 2423 | { 0x21218c, 0x0 }, | 2423 | { 0x21218c, 0x0 }, |
| 2424 | { 0x1308c, 0x0 }, | 2424 | { 0x1308c, 0x0 }, |
| 2425 | { 0x11308c, 0x0 }, | 2425 | { 0x11308c, 0x0 }, |
| 2426 | { 0x21308c, 0x0 }, | 2426 | { 0x21308c, 0x0 }, |
| 2427 | { 0x1318c, 0x0 }, | 2427 | { 0x1318c, 0x0 }, |
| 2428 | { 0x11318c, 0x0 }, | 2428 | { 0x11318c, 0x0 }, |
| 2429 | { 0x21318c, 0x0 }, | 2429 | { 0x21318c, 0x0 }, |
| 2430 | { 0x1008d, 0x0 }, | 2430 | { 0x1008d, 0x0 }, |
| 2431 | { 0x11008d, 0x0 }, | 2431 | { 0x11008d, 0x0 }, |
| 2432 | { 0x21008d, 0x0 }, | 2432 | { 0x21008d, 0x0 }, |
| 2433 | { 0x1018d, 0x0 }, | 2433 | { 0x1018d, 0x0 }, |
| 2434 | { 0x11018d, 0x0 }, | 2434 | { 0x11018d, 0x0 }, |
| 2435 | { 0x21018d, 0x0 }, | 2435 | { 0x21018d, 0x0 }, |
| 2436 | { 0x1108d, 0x0 }, | 2436 | { 0x1108d, 0x0 }, |
| 2437 | { 0x11108d, 0x0 }, | 2437 | { 0x11108d, 0x0 }, |
| 2438 | { 0x21108d, 0x0 }, | 2438 | { 0x21108d, 0x0 }, |
| 2439 | { 0x1118d, 0x0 }, | 2439 | { 0x1118d, 0x0 }, |
| 2440 | { 0x11118d, 0x0 }, | 2440 | { 0x11118d, 0x0 }, |
| 2441 | { 0x21118d, 0x0 }, | 2441 | { 0x21118d, 0x0 }, |
| 2442 | { 0x1208d, 0x0 }, | 2442 | { 0x1208d, 0x0 }, |
| 2443 | { 0x11208d, 0x0 }, | 2443 | { 0x11208d, 0x0 }, |
| 2444 | { 0x21208d, 0x0 }, | 2444 | { 0x21208d, 0x0 }, |
| 2445 | { 0x1218d, 0x0 }, | 2445 | { 0x1218d, 0x0 }, |
| 2446 | { 0x11218d, 0x0 }, | 2446 | { 0x11218d, 0x0 }, |
| 2447 | { 0x21218d, 0x0 }, | 2447 | { 0x21218d, 0x0 }, |
| 2448 | { 0x1308d, 0x0 }, | 2448 | { 0x1308d, 0x0 }, |
| 2449 | { 0x11308d, 0x0 }, | 2449 | { 0x11308d, 0x0 }, |
| 2450 | { 0x21308d, 0x0 }, | 2450 | { 0x21308d, 0x0 }, |
| 2451 | { 0x1318d, 0x0 }, | 2451 | { 0x1318d, 0x0 }, |
| 2452 | { 0x11318d, 0x0 }, | 2452 | { 0x11318d, 0x0 }, |
| 2453 | { 0x21318d, 0x0 }, | 2453 | { 0x21318d, 0x0 }, |
| 2454 | { 0x100c0, 0x0 }, | 2454 | { 0x100c0, 0x0 }, |
| 2455 | { 0x1100c0, 0x0 }, | 2455 | { 0x1100c0, 0x0 }, |
| 2456 | { 0x2100c0, 0x0 }, | 2456 | { 0x2100c0, 0x0 }, |
| 2457 | { 0x101c0, 0x0 }, | 2457 | { 0x101c0, 0x0 }, |
| 2458 | { 0x1101c0, 0x0 }, | 2458 | { 0x1101c0, 0x0 }, |
| 2459 | { 0x2101c0, 0x0 }, | 2459 | { 0x2101c0, 0x0 }, |
| 2460 | { 0x102c0, 0x0 }, | 2460 | { 0x102c0, 0x0 }, |
| 2461 | { 0x1102c0, 0x0 }, | 2461 | { 0x1102c0, 0x0 }, |
| 2462 | { 0x2102c0, 0x0 }, | 2462 | { 0x2102c0, 0x0 }, |
| 2463 | { 0x103c0, 0x0 }, | 2463 | { 0x103c0, 0x0 }, |
| 2464 | { 0x1103c0, 0x0 }, | 2464 | { 0x1103c0, 0x0 }, |
| 2465 | { 0x2103c0, 0x0 }, | 2465 | { 0x2103c0, 0x0 }, |
| 2466 | { 0x104c0, 0x0 }, | 2466 | { 0x104c0, 0x0 }, |
| 2467 | { 0x1104c0, 0x0 }, | 2467 | { 0x1104c0, 0x0 }, |
| 2468 | { 0x2104c0, 0x0 }, | 2468 | { 0x2104c0, 0x0 }, |
| 2469 | { 0x105c0, 0x0 }, | 2469 | { 0x105c0, 0x0 }, |
| 2470 | { 0x1105c0, 0x0 }, | 2470 | { 0x1105c0, 0x0 }, |
| 2471 | { 0x2105c0, 0x0 }, | 2471 | { 0x2105c0, 0x0 }, |
| 2472 | { 0x106c0, 0x0 }, | 2472 | { 0x106c0, 0x0 }, |
| 2473 | { 0x1106c0, 0x0 }, | 2473 | { 0x1106c0, 0x0 }, |
| 2474 | { 0x2106c0, 0x0 }, | 2474 | { 0x2106c0, 0x0 }, |
| 2475 | { 0x107c0, 0x0 }, | 2475 | { 0x107c0, 0x0 }, |
| 2476 | { 0x1107c0, 0x0 }, | 2476 | { 0x1107c0, 0x0 }, |
| 2477 | { 0x2107c0, 0x0 }, | 2477 | { 0x2107c0, 0x0 }, |
| 2478 | { 0x108c0, 0x0 }, | 2478 | { 0x108c0, 0x0 }, |
| 2479 | { 0x1108c0, 0x0 }, | 2479 | { 0x1108c0, 0x0 }, |
| 2480 | { 0x2108c0, 0x0 }, | 2480 | { 0x2108c0, 0x0 }, |
| 2481 | { 0x110c0, 0x0 }, | 2481 | { 0x110c0, 0x0 }, |
| 2482 | { 0x1110c0, 0x0 }, | 2482 | { 0x1110c0, 0x0 }, |
| 2483 | { 0x2110c0, 0x0 }, | 2483 | { 0x2110c0, 0x0 }, |
| 2484 | { 0x111c0, 0x0 }, | 2484 | { 0x111c0, 0x0 }, |
| 2485 | { 0x1111c0, 0x0 }, | 2485 | { 0x1111c0, 0x0 }, |
| 2486 | { 0x2111c0, 0x0 }, | 2486 | { 0x2111c0, 0x0 }, |
| 2487 | { 0x112c0, 0x0 }, | 2487 | { 0x112c0, 0x0 }, |
| 2488 | { 0x1112c0, 0x0 }, | 2488 | { 0x1112c0, 0x0 }, |
| 2489 | { 0x2112c0, 0x0 }, | 2489 | { 0x2112c0, 0x0 }, |
| 2490 | { 0x113c0, 0x0 }, | 2490 | { 0x113c0, 0x0 }, |
| 2491 | { 0x1113c0, 0x0 }, | 2491 | { 0x1113c0, 0x0 }, |
| 2492 | { 0x2113c0, 0x0 }, | 2492 | { 0x2113c0, 0x0 }, |
| 2493 | { 0x114c0, 0x0 }, | 2493 | { 0x114c0, 0x0 }, |
| 2494 | { 0x1114c0, 0x0 }, | 2494 | { 0x1114c0, 0x0 }, |
| 2495 | { 0x2114c0, 0x0 }, | 2495 | { 0x2114c0, 0x0 }, |
| 2496 | { 0x115c0, 0x0 }, | 2496 | { 0x115c0, 0x0 }, |
| 2497 | { 0x1115c0, 0x0 }, | 2497 | { 0x1115c0, 0x0 }, |
| 2498 | { 0x2115c0, 0x0 }, | 2498 | { 0x2115c0, 0x0 }, |
| 2499 | { 0x116c0, 0x0 }, | 2499 | { 0x116c0, 0x0 }, |
| 2500 | { 0x1116c0, 0x0 }, | 2500 | { 0x1116c0, 0x0 }, |
| 2501 | { 0x2116c0, 0x0 }, | 2501 | { 0x2116c0, 0x0 }, |
| 2502 | { 0x117c0, 0x0 }, | 2502 | { 0x117c0, 0x0 }, |
| 2503 | { 0x1117c0, 0x0 }, | 2503 | { 0x1117c0, 0x0 }, |
| 2504 | { 0x2117c0, 0x0 }, | 2504 | { 0x2117c0, 0x0 }, |
| 2505 | { 0x118c0, 0x0 }, | 2505 | { 0x118c0, 0x0 }, |
| 2506 | { 0x1118c0, 0x0 }, | 2506 | { 0x1118c0, 0x0 }, |
| 2507 | { 0x2118c0, 0x0 }, | 2507 | { 0x2118c0, 0x0 }, |
| 2508 | { 0x120c0, 0x0 }, | 2508 | { 0x120c0, 0x0 }, |
| 2509 | { 0x1120c0, 0x0 }, | 2509 | { 0x1120c0, 0x0 }, |
| 2510 | { 0x2120c0, 0x0 }, | 2510 | { 0x2120c0, 0x0 }, |
| 2511 | { 0x121c0, 0x0 }, | 2511 | { 0x121c0, 0x0 }, |
| 2512 | { 0x1121c0, 0x0 }, | 2512 | { 0x1121c0, 0x0 }, |
| 2513 | { 0x2121c0, 0x0 }, | 2513 | { 0x2121c0, 0x0 }, |
| 2514 | { 0x122c0, 0x0 }, | 2514 | { 0x122c0, 0x0 }, |
| 2515 | { 0x1122c0, 0x0 }, | 2515 | { 0x1122c0, 0x0 }, |
| 2516 | { 0x2122c0, 0x0 }, | 2516 | { 0x2122c0, 0x0 }, |
| 2517 | { 0x123c0, 0x0 }, | 2517 | { 0x123c0, 0x0 }, |
| 2518 | { 0x1123c0, 0x0 }, | 2518 | { 0x1123c0, 0x0 }, |
| 2519 | { 0x2123c0, 0x0 }, | 2519 | { 0x2123c0, 0x0 }, |
| 2520 | { 0x124c0, 0x0 }, | 2520 | { 0x124c0, 0x0 }, |
| 2521 | { 0x1124c0, 0x0 }, | 2521 | { 0x1124c0, 0x0 }, |
| 2522 | { 0x2124c0, 0x0 }, | 2522 | { 0x2124c0, 0x0 }, |
| 2523 | { 0x125c0, 0x0 }, | 2523 | { 0x125c0, 0x0 }, |
| 2524 | { 0x1125c0, 0x0 }, | 2524 | { 0x1125c0, 0x0 }, |
| 2525 | { 0x2125c0, 0x0 }, | 2525 | { 0x2125c0, 0x0 }, |
| 2526 | { 0x126c0, 0x0 }, | 2526 | { 0x126c0, 0x0 }, |
| 2527 | { 0x1126c0, 0x0 }, | 2527 | { 0x1126c0, 0x0 }, |
| 2528 | { 0x2126c0, 0x0 }, | 2528 | { 0x2126c0, 0x0 }, |
| 2529 | { 0x127c0, 0x0 }, | 2529 | { 0x127c0, 0x0 }, |
| 2530 | { 0x1127c0, 0x0 }, | 2530 | { 0x1127c0, 0x0 }, |
| 2531 | { 0x2127c0, 0x0 }, | 2531 | { 0x2127c0, 0x0 }, |
| 2532 | { 0x128c0, 0x0 }, | 2532 | { 0x128c0, 0x0 }, |
| 2533 | { 0x1128c0, 0x0 }, | 2533 | { 0x1128c0, 0x0 }, |
| 2534 | { 0x2128c0, 0x0 }, | 2534 | { 0x2128c0, 0x0 }, |
| 2535 | { 0x130c0, 0x0 }, | 2535 | { 0x130c0, 0x0 }, |
| 2536 | { 0x1130c0, 0x0 }, | 2536 | { 0x1130c0, 0x0 }, |
| 2537 | { 0x2130c0, 0x0 }, | 2537 | { 0x2130c0, 0x0 }, |
| 2538 | { 0x131c0, 0x0 }, | 2538 | { 0x131c0, 0x0 }, |
| 2539 | { 0x1131c0, 0x0 }, | 2539 | { 0x1131c0, 0x0 }, |
| 2540 | { 0x2131c0, 0x0 }, | 2540 | { 0x2131c0, 0x0 }, |
| 2541 | { 0x132c0, 0x0 }, | 2541 | { 0x132c0, 0x0 }, |
| 2542 | { 0x1132c0, 0x0 }, | 2542 | { 0x1132c0, 0x0 }, |
| 2543 | { 0x2132c0, 0x0 }, | 2543 | { 0x2132c0, 0x0 }, |
| 2544 | { 0x133c0, 0x0 }, | 2544 | { 0x133c0, 0x0 }, |
| 2545 | { 0x1133c0, 0x0 }, | 2545 | { 0x1133c0, 0x0 }, |
| 2546 | { 0x2133c0, 0x0 }, | 2546 | { 0x2133c0, 0x0 }, |
| 2547 | { 0x134c0, 0x0 }, | 2547 | { 0x134c0, 0x0 }, |
| 2548 | { 0x1134c0, 0x0 }, | 2548 | { 0x1134c0, 0x0 }, |
| 2549 | { 0x2134c0, 0x0 }, | 2549 | { 0x2134c0, 0x0 }, |
| 2550 | { 0x135c0, 0x0 }, | 2550 | { 0x135c0, 0x0 }, |
| 2551 | { 0x1135c0, 0x0 }, | 2551 | { 0x1135c0, 0x0 }, |
| 2552 | { 0x2135c0, 0x0 }, | 2552 | { 0x2135c0, 0x0 }, |
| 2553 | { 0x136c0, 0x0 }, | 2553 | { 0x136c0, 0x0 }, |
| 2554 | { 0x1136c0, 0x0 }, | 2554 | { 0x1136c0, 0x0 }, |
| 2555 | { 0x2136c0, 0x0 }, | 2555 | { 0x2136c0, 0x0 }, |
| 2556 | { 0x137c0, 0x0 }, | 2556 | { 0x137c0, 0x0 }, |
| 2557 | { 0x1137c0, 0x0 }, | 2557 | { 0x1137c0, 0x0 }, |
| 2558 | { 0x2137c0, 0x0 }, | 2558 | { 0x2137c0, 0x0 }, |
| 2559 | { 0x138c0, 0x0 }, | 2559 | { 0x138c0, 0x0 }, |
| 2560 | { 0x1138c0, 0x0 }, | 2560 | { 0x1138c0, 0x0 }, |
| 2561 | { 0x2138c0, 0x0 }, | 2561 | { 0x2138c0, 0x0 }, |
| 2562 | { 0x100c1, 0x0 }, | 2562 | { 0x100c1, 0x0 }, |
| 2563 | { 0x1100c1, 0x0 }, | 2563 | { 0x1100c1, 0x0 }, |
| 2564 | { 0x2100c1, 0x0 }, | 2564 | { 0x2100c1, 0x0 }, |
| 2565 | { 0x101c1, 0x0 }, | 2565 | { 0x101c1, 0x0 }, |
| 2566 | { 0x1101c1, 0x0 }, | 2566 | { 0x1101c1, 0x0 }, |
| 2567 | { 0x2101c1, 0x0 }, | 2567 | { 0x2101c1, 0x0 }, |
| 2568 | { 0x102c1, 0x0 }, | 2568 | { 0x102c1, 0x0 }, |
| 2569 | { 0x1102c1, 0x0 }, | 2569 | { 0x1102c1, 0x0 }, |
| 2570 | { 0x2102c1, 0x0 }, | 2570 | { 0x2102c1, 0x0 }, |
| 2571 | { 0x103c1, 0x0 }, | 2571 | { 0x103c1, 0x0 }, |
| 2572 | { 0x1103c1, 0x0 }, | 2572 | { 0x1103c1, 0x0 }, |
| 2573 | { 0x2103c1, 0x0 }, | 2573 | { 0x2103c1, 0x0 }, |
| 2574 | { 0x104c1, 0x0 }, | 2574 | { 0x104c1, 0x0 }, |
| 2575 | { 0x1104c1, 0x0 }, | 2575 | { 0x1104c1, 0x0 }, |
| 2576 | { 0x2104c1, 0x0 }, | 2576 | { 0x2104c1, 0x0 }, |
| 2577 | { 0x105c1, 0x0 }, | 2577 | { 0x105c1, 0x0 }, |
| 2578 | { 0x1105c1, 0x0 }, | 2578 | { 0x1105c1, 0x0 }, |
| 2579 | { 0x2105c1, 0x0 }, | 2579 | { 0x2105c1, 0x0 }, |
| 2580 | { 0x106c1, 0x0 }, | 2580 | { 0x106c1, 0x0 }, |
| 2581 | { 0x1106c1, 0x0 }, | 2581 | { 0x1106c1, 0x0 }, |
| 2582 | { 0x2106c1, 0x0 }, | 2582 | { 0x2106c1, 0x0 }, |
| 2583 | { 0x107c1, 0x0 }, | 2583 | { 0x107c1, 0x0 }, |
| 2584 | { 0x1107c1, 0x0 }, | 2584 | { 0x1107c1, 0x0 }, |
| 2585 | { 0x2107c1, 0x0 }, | 2585 | { 0x2107c1, 0x0 }, |
| 2586 | { 0x108c1, 0x0 }, | 2586 | { 0x108c1, 0x0 }, |
| 2587 | { 0x1108c1, 0x0 }, | 2587 | { 0x1108c1, 0x0 }, |
| 2588 | { 0x2108c1, 0x0 }, | 2588 | { 0x2108c1, 0x0 }, |
| 2589 | { 0x110c1, 0x0 }, | 2589 | { 0x110c1, 0x0 }, |
| 2590 | { 0x1110c1, 0x0 }, | 2590 | { 0x1110c1, 0x0 }, |
| 2591 | { 0x2110c1, 0x0 }, | 2591 | { 0x2110c1, 0x0 }, |
| 2592 | { 0x111c1, 0x0 }, | 2592 | { 0x111c1, 0x0 }, |
| 2593 | { 0x1111c1, 0x0 }, | 2593 | { 0x1111c1, 0x0 }, |
| 2594 | { 0x2111c1, 0x0 }, | 2594 | { 0x2111c1, 0x0 }, |
| 2595 | { 0x112c1, 0x0 }, | 2595 | { 0x112c1, 0x0 }, |
| 2596 | { 0x1112c1, 0x0 }, | 2596 | { 0x1112c1, 0x0 }, |
| 2597 | { 0x2112c1, 0x0 }, | 2597 | { 0x2112c1, 0x0 }, |
| 2598 | { 0x113c1, 0x0 }, | 2598 | { 0x113c1, 0x0 }, |
| 2599 | { 0x1113c1, 0x0 }, | 2599 | { 0x1113c1, 0x0 }, |
| 2600 | { 0x2113c1, 0x0 }, | 2600 | { 0x2113c1, 0x0 }, |
| 2601 | { 0x114c1, 0x0 }, | 2601 | { 0x114c1, 0x0 }, |
| 2602 | { 0x1114c1, 0x0 }, | 2602 | { 0x1114c1, 0x0 }, |
| 2603 | { 0x2114c1, 0x0 }, | 2603 | { 0x2114c1, 0x0 }, |
| 2604 | { 0x115c1, 0x0 }, | 2604 | { 0x115c1, 0x0 }, |
| 2605 | { 0x1115c1, 0x0 }, | 2605 | { 0x1115c1, 0x0 }, |
| 2606 | { 0x2115c1, 0x0 }, | 2606 | { 0x2115c1, 0x0 }, |
| 2607 | { 0x116c1, 0x0 }, | 2607 | { 0x116c1, 0x0 }, |
| 2608 | { 0x1116c1, 0x0 }, | 2608 | { 0x1116c1, 0x0 }, |
| 2609 | { 0x2116c1, 0x0 }, | 2609 | { 0x2116c1, 0x0 }, |
| 2610 | { 0x117c1, 0x0 }, | 2610 | { 0x117c1, 0x0 }, |
| 2611 | { 0x1117c1, 0x0 }, | 2611 | { 0x1117c1, 0x0 }, |
| 2612 | { 0x2117c1, 0x0 }, | 2612 | { 0x2117c1, 0x0 }, |
| 2613 | { 0x118c1, 0x0 }, | 2613 | { 0x118c1, 0x0 }, |
| 2614 | { 0x1118c1, 0x0 }, | 2614 | { 0x1118c1, 0x0 }, |
| 2615 | { 0x2118c1, 0x0 }, | 2615 | { 0x2118c1, 0x0 }, |
| 2616 | { 0x120c1, 0x0 }, | 2616 | { 0x120c1, 0x0 }, |
| 2617 | { 0x1120c1, 0x0 }, | 2617 | { 0x1120c1, 0x0 }, |
| 2618 | { 0x2120c1, 0x0 }, | 2618 | { 0x2120c1, 0x0 }, |
| 2619 | { 0x121c1, 0x0 }, | 2619 | { 0x121c1, 0x0 }, |
| 2620 | { 0x1121c1, 0x0 }, | 2620 | { 0x1121c1, 0x0 }, |
| 2621 | { 0x2121c1, 0x0 }, | 2621 | { 0x2121c1, 0x0 }, |
| 2622 | { 0x122c1, 0x0 }, | 2622 | { 0x122c1, 0x0 }, |
| 2623 | { 0x1122c1, 0x0 }, | 2623 | { 0x1122c1, 0x0 }, |
| 2624 | { 0x2122c1, 0x0 }, | 2624 | { 0x2122c1, 0x0 }, |
| 2625 | { 0x123c1, 0x0 }, | 2625 | { 0x123c1, 0x0 }, |
| 2626 | { 0x1123c1, 0x0 }, | 2626 | { 0x1123c1, 0x0 }, |
| 2627 | { 0x2123c1, 0x0 }, | 2627 | { 0x2123c1, 0x0 }, |
| 2628 | { 0x124c1, 0x0 }, | 2628 | { 0x124c1, 0x0 }, |
| 2629 | { 0x1124c1, 0x0 }, | 2629 | { 0x1124c1, 0x0 }, |
| 2630 | { 0x2124c1, 0x0 }, | 2630 | { 0x2124c1, 0x0 }, |
| 2631 | { 0x125c1, 0x0 }, | 2631 | { 0x125c1, 0x0 }, |
| 2632 | { 0x1125c1, 0x0 }, | 2632 | { 0x1125c1, 0x0 }, |
| 2633 | { 0x2125c1, 0x0 }, | 2633 | { 0x2125c1, 0x0 }, |
| 2634 | { 0x126c1, 0x0 }, | 2634 | { 0x126c1, 0x0 }, |
| 2635 | { 0x1126c1, 0x0 }, | 2635 | { 0x1126c1, 0x0 }, |
| 2636 | { 0x2126c1, 0x0 }, | 2636 | { 0x2126c1, 0x0 }, |
| 2637 | { 0x127c1, 0x0 }, | 2637 | { 0x127c1, 0x0 }, |
| 2638 | { 0x1127c1, 0x0 }, | 2638 | { 0x1127c1, 0x0 }, |
| 2639 | { 0x2127c1, 0x0 }, | 2639 | { 0x2127c1, 0x0 }, |
| 2640 | { 0x128c1, 0x0 }, | 2640 | { 0x128c1, 0x0 }, |
| 2641 | { 0x1128c1, 0x0 }, | 2641 | { 0x1128c1, 0x0 }, |
| 2642 | { 0x2128c1, 0x0 }, | 2642 | { 0x2128c1, 0x0 }, |
| 2643 | { 0x130c1, 0x0 }, | 2643 | { 0x130c1, 0x0 }, |
| 2644 | { 0x1130c1, 0x0 }, | 2644 | { 0x1130c1, 0x0 }, |
| 2645 | { 0x2130c1, 0x0 }, | 2645 | { 0x2130c1, 0x0 }, |
| 2646 | { 0x131c1, 0x0 }, | 2646 | { 0x131c1, 0x0 }, |
| 2647 | { 0x1131c1, 0x0 }, | 2647 | { 0x1131c1, 0x0 }, |
| 2648 | { 0x2131c1, 0x0 }, | 2648 | { 0x2131c1, 0x0 }, |
| 2649 | { 0x132c1, 0x0 }, | 2649 | { 0x132c1, 0x0 }, |
| 2650 | { 0x1132c1, 0x0 }, | 2650 | { 0x1132c1, 0x0 }, |
| 2651 | { 0x2132c1, 0x0 }, | 2651 | { 0x2132c1, 0x0 }, |
| 2652 | { 0x133c1, 0x0 }, | 2652 | { 0x133c1, 0x0 }, |
| 2653 | { 0x1133c1, 0x0 }, | 2653 | { 0x1133c1, 0x0 }, |
| 2654 | { 0x2133c1, 0x0 }, | 2654 | { 0x2133c1, 0x0 }, |
| 2655 | { 0x134c1, 0x0 }, | 2655 | { 0x134c1, 0x0 }, |
| 2656 | { 0x1134c1, 0x0 }, | 2656 | { 0x1134c1, 0x0 }, |
| 2657 | { 0x2134c1, 0x0 }, | 2657 | { 0x2134c1, 0x0 }, |
| 2658 | { 0x135c1, 0x0 }, | 2658 | { 0x135c1, 0x0 }, |
| 2659 | { 0x1135c1, 0x0 }, | 2659 | { 0x1135c1, 0x0 }, |
| 2660 | { 0x2135c1, 0x0 }, | 2660 | { 0x2135c1, 0x0 }, |
| 2661 | { 0x136c1, 0x0 }, | 2661 | { 0x136c1, 0x0 }, |
| 2662 | { 0x1136c1, 0x0 }, | 2662 | { 0x1136c1, 0x0 }, |
| 2663 | { 0x2136c1, 0x0 }, | 2663 | { 0x2136c1, 0x0 }, |
| 2664 | { 0x137c1, 0x0 }, | 2664 | { 0x137c1, 0x0 }, |
| 2665 | { 0x1137c1, 0x0 }, | 2665 | { 0x1137c1, 0x0 }, |
| 2666 | { 0x2137c1, 0x0 }, | 2666 | { 0x2137c1, 0x0 }, |
| 2667 | { 0x138c1, 0x0 }, | 2667 | { 0x138c1, 0x0 }, |
| 2668 | { 0x1138c1, 0x0 }, | 2668 | { 0x1138c1, 0x0 }, |
| 2669 | { 0x2138c1, 0x0 }, | 2669 | { 0x2138c1, 0x0 }, |
| 2670 | { 0x10020, 0x0 }, | 2670 | { 0x10020, 0x0 }, |
| 2671 | { 0x110020, 0x0 }, | 2671 | { 0x110020, 0x0 }, |
| 2672 | { 0x210020, 0x0 }, | 2672 | { 0x210020, 0x0 }, |
| 2673 | { 0x11020, 0x0 }, | 2673 | { 0x11020, 0x0 }, |
| 2674 | { 0x111020, 0x0 }, | 2674 | { 0x111020, 0x0 }, |
| 2675 | { 0x211020, 0x0 }, | 2675 | { 0x211020, 0x0 }, |
| 2676 | { 0x12020, 0x0 }, | 2676 | { 0x12020, 0x0 }, |
| 2677 | { 0x112020, 0x0 }, | 2677 | { 0x112020, 0x0 }, |
| 2678 | { 0x212020, 0x0 }, | 2678 | { 0x212020, 0x0 }, |
| 2679 | { 0x13020, 0x0 }, | 2679 | { 0x13020, 0x0 }, |
| 2680 | { 0x113020, 0x0 }, | 2680 | { 0x113020, 0x0 }, |
| 2681 | { 0x213020, 0x0 }, | 2681 | { 0x213020, 0x0 }, |
| 2682 | { 0x20072, 0x0 }, | 2682 | { 0x20072, 0x0 }, |
| 2683 | { 0x20073, 0x0 }, | 2683 | { 0x20073, 0x0 }, |
| 2684 | { 0x20074, 0x0 }, | 2684 | { 0x20074, 0x0 }, |
| 2685 | { 0x100aa, 0x0 }, | 2685 | { 0x100aa, 0x0 }, |
| 2686 | { 0x110aa, 0x0 }, | 2686 | { 0x110aa, 0x0 }, |
| 2687 | { 0x120aa, 0x0 }, | 2687 | { 0x120aa, 0x0 }, |
| 2688 | { 0x130aa, 0x0 }, | 2688 | { 0x130aa, 0x0 }, |
| 2689 | { 0x20010, 0x0 }, | 2689 | { 0x20010, 0x0 }, |
| 2690 | { 0x120010, 0x0 }, | 2690 | { 0x120010, 0x0 }, |
| 2691 | { 0x220010, 0x0 }, | 2691 | { 0x220010, 0x0 }, |
| 2692 | { 0x20011, 0x0 }, | 2692 | { 0x20011, 0x0 }, |
| 2693 | { 0x120011, 0x0 }, | 2693 | { 0x120011, 0x0 }, |
| 2694 | { 0x220011, 0x0 }, | 2694 | { 0x220011, 0x0 }, |
| 2695 | { 0x100ae, 0x0 }, | 2695 | { 0x100ae, 0x0 }, |
| 2696 | { 0x1100ae, 0x0 }, | 2696 | { 0x1100ae, 0x0 }, |
| 2697 | { 0x2100ae, 0x0 }, | 2697 | { 0x2100ae, 0x0 }, |
| 2698 | { 0x100af, 0x0 }, | 2698 | { 0x100af, 0x0 }, |
| 2699 | { 0x1100af, 0x0 }, | 2699 | { 0x1100af, 0x0 }, |
| 2700 | { 0x2100af, 0x0 }, | 2700 | { 0x2100af, 0x0 }, |
| 2701 | { 0x110ae, 0x0 }, | 2701 | { 0x110ae, 0x0 }, |
| 2702 | { 0x1110ae, 0x0 }, | 2702 | { 0x1110ae, 0x0 }, |
| 2703 | { 0x2110ae, 0x0 }, | 2703 | { 0x2110ae, 0x0 }, |
| 2704 | { 0x110af, 0x0 }, | 2704 | { 0x110af, 0x0 }, |
| 2705 | { 0x1110af, 0x0 }, | 2705 | { 0x1110af, 0x0 }, |
| 2706 | { 0x2110af, 0x0 }, | 2706 | { 0x2110af, 0x0 }, |
| 2707 | { 0x120ae, 0x0 }, | 2707 | { 0x120ae, 0x0 }, |
| 2708 | { 0x1120ae, 0x0 }, | 2708 | { 0x1120ae, 0x0 }, |
| 2709 | { 0x2120ae, 0x0 }, | 2709 | { 0x2120ae, 0x0 }, |
| 2710 | { 0x120af, 0x0 }, | 2710 | { 0x120af, 0x0 }, |
| 2711 | { 0x1120af, 0x0 }, | 2711 | { 0x1120af, 0x0 }, |
| 2712 | { 0x2120af, 0x0 }, | 2712 | { 0x2120af, 0x0 }, |
| 2713 | { 0x130ae, 0x0 }, | 2713 | { 0x130ae, 0x0 }, |
| 2714 | { 0x1130ae, 0x0 }, | 2714 | { 0x1130ae, 0x0 }, |
| 2715 | { 0x2130ae, 0x0 }, | 2715 | { 0x2130ae, 0x0 }, |
| 2716 | { 0x130af, 0x0 }, | 2716 | { 0x130af, 0x0 }, |
| 2717 | { 0x1130af, 0x0 }, | 2717 | { 0x1130af, 0x0 }, |
| 2718 | { 0x2130af, 0x0 }, | 2718 | { 0x2130af, 0x0 }, |
| 2719 | { 0x20020, 0x0 }, | 2719 | { 0x20020, 0x0 }, |
| 2720 | { 0x120020, 0x0 }, | 2720 | { 0x120020, 0x0 }, |
| 2721 | { 0x220020, 0x0 }, | 2721 | { 0x220020, 0x0 }, |
| 2722 | { 0x100a0, 0x0 }, | 2722 | { 0x100a0, 0x0 }, |
| 2723 | { 0x100a1, 0x0 }, | 2723 | { 0x100a1, 0x0 }, |
| 2724 | { 0x100a2, 0x0 }, | 2724 | { 0x100a2, 0x0 }, |
| 2725 | { 0x100a3, 0x0 }, | 2725 | { 0x100a3, 0x0 }, |
| 2726 | { 0x100a4, 0x0 }, | 2726 | { 0x100a4, 0x0 }, |
| 2727 | { 0x100a5, 0x0 }, | 2727 | { 0x100a5, 0x0 }, |
| 2728 | { 0x100a6, 0x0 }, | 2728 | { 0x100a6, 0x0 }, |
| 2729 | { 0x100a7, 0x0 }, | 2729 | { 0x100a7, 0x0 }, |
| 2730 | { 0x110a0, 0x0 }, | 2730 | { 0x110a0, 0x0 }, |
| 2731 | { 0x110a1, 0x0 }, | 2731 | { 0x110a1, 0x0 }, |
| 2732 | { 0x110a2, 0x0 }, | 2732 | { 0x110a2, 0x0 }, |
| 2733 | { 0x110a3, 0x0 }, | 2733 | { 0x110a3, 0x0 }, |
| 2734 | { 0x110a4, 0x0 }, | 2734 | { 0x110a4, 0x0 }, |
| 2735 | { 0x110a5, 0x0 }, | 2735 | { 0x110a5, 0x0 }, |
| 2736 | { 0x110a6, 0x0 }, | 2736 | { 0x110a6, 0x0 }, |
| 2737 | { 0x110a7, 0x0 }, | 2737 | { 0x110a7, 0x0 }, |
| 2738 | { 0x120a0, 0x0 }, | 2738 | { 0x120a0, 0x0 }, |
| 2739 | { 0x120a1, 0x0 }, | 2739 | { 0x120a1, 0x0 }, |
| 2740 | { 0x120a2, 0x0 }, | 2740 | { 0x120a2, 0x0 }, |
| 2741 | { 0x120a3, 0x0 }, | 2741 | { 0x120a3, 0x0 }, |
| 2742 | { 0x120a4, 0x0 }, | 2742 | { 0x120a4, 0x0 }, |
| 2743 | { 0x120a5, 0x0 }, | 2743 | { 0x120a5, 0x0 }, |
| 2744 | { 0x120a6, 0x0 }, | 2744 | { 0x120a6, 0x0 }, |
| 2745 | { 0x120a7, 0x0 }, | 2745 | { 0x120a7, 0x0 }, |
| 2746 | { 0x130a0, 0x0 }, | 2746 | { 0x130a0, 0x0 }, |
| 2747 | { 0x130a1, 0x0 }, | 2747 | { 0x130a1, 0x0 }, |
| 2748 | { 0x130a2, 0x0 }, | 2748 | { 0x130a2, 0x0 }, |
| 2749 | { 0x130a3, 0x0 }, | 2749 | { 0x130a3, 0x0 }, |
| 2750 | { 0x130a4, 0x0 }, | 2750 | { 0x130a4, 0x0 }, |
| 2751 | { 0x130a5, 0x0 }, | 2751 | { 0x130a5, 0x0 }, |
| 2752 | { 0x130a6, 0x0 }, | 2752 | { 0x130a6, 0x0 }, |
| 2753 | { 0x130a7, 0x0 }, | 2753 | { 0x130a7, 0x0 }, |
| 2754 | { 0x2007c, 0x0 }, | 2754 | { 0x2007c, 0x0 }, |
| 2755 | { 0x12007c, 0x0 }, | 2755 | { 0x12007c, 0x0 }, |
| 2756 | { 0x22007c, 0x0 }, | 2756 | { 0x22007c, 0x0 }, |
| 2757 | { 0x2007d, 0x0 }, | 2757 | { 0x2007d, 0x0 }, |
| 2758 | { 0x12007d, 0x0 }, | 2758 | { 0x12007d, 0x0 }, |
| 2759 | { 0x22007d, 0x0 }, | 2759 | { 0x22007d, 0x0 }, |
| 2760 | { 0x400fd, 0x0 }, | 2760 | { 0x400fd, 0x0 }, |
| 2761 | { 0x400c0, 0x0 }, | 2761 | { 0x400c0, 0x0 }, |
| 2762 | { 0x90201, 0x0 }, | 2762 | { 0x90201, 0x0 }, |
| 2763 | { 0x190201, 0x0 }, | 2763 | { 0x190201, 0x0 }, |
| 2764 | { 0x290201, 0x0 }, | 2764 | { 0x290201, 0x0 }, |
| 2765 | { 0x90202, 0x0 }, | 2765 | { 0x90202, 0x0 }, |
| 2766 | { 0x190202, 0x0 }, | 2766 | { 0x190202, 0x0 }, |
| 2767 | { 0x290202, 0x0 }, | 2767 | { 0x290202, 0x0 }, |
| 2768 | { 0x90203, 0x0 }, | 2768 | { 0x90203, 0x0 }, |
| 2769 | { 0x190203, 0x0 }, | 2769 | { 0x190203, 0x0 }, |
| 2770 | { 0x290203, 0x0 }, | 2770 | { 0x290203, 0x0 }, |
| 2771 | { 0x90204, 0x0 }, | 2771 | { 0x90204, 0x0 }, |
| 2772 | { 0x190204, 0x0 }, | 2772 | { 0x190204, 0x0 }, |
| 2773 | { 0x290204, 0x0 }, | 2773 | { 0x290204, 0x0 }, |
| 2774 | { 0x90205, 0x0 }, | 2774 | { 0x90205, 0x0 }, |
| 2775 | { 0x190205, 0x0 }, | 2775 | { 0x190205, 0x0 }, |
| 2776 | { 0x290205, 0x0 }, | 2776 | { 0x290205, 0x0 }, |
| 2777 | { 0x90206, 0x0 }, | 2777 | { 0x90206, 0x0 }, |
| 2778 | { 0x190206, 0x0 }, | 2778 | { 0x190206, 0x0 }, |
| 2779 | { 0x290206, 0x0 }, | 2779 | { 0x290206, 0x0 }, |
| 2780 | { 0x90207, 0x0 }, | 2780 | { 0x90207, 0x0 }, |
| 2781 | { 0x190207, 0x0 }, | 2781 | { 0x190207, 0x0 }, |
| 2782 | { 0x290207, 0x0 }, | 2782 | { 0x290207, 0x0 }, |
| 2783 | { 0x90208, 0x0 }, | 2783 | { 0x90208, 0x0 }, |
| 2784 | { 0x190208, 0x0 }, | 2784 | { 0x190208, 0x0 }, |
| 2785 | { 0x290208, 0x0 }, | 2785 | { 0x290208, 0x0 }, |
| 2786 | { 0x10062, 0x0 }, | 2786 | { 0x10062, 0x0 }, |
| 2787 | { 0x10162, 0x0 }, | 2787 | { 0x10162, 0x0 }, |
| 2788 | { 0x10262, 0x0 }, | 2788 | { 0x10262, 0x0 }, |
| 2789 | { 0x10362, 0x0 }, | 2789 | { 0x10362, 0x0 }, |
| 2790 | { 0x10462, 0x0 }, | 2790 | { 0x10462, 0x0 }, |
| 2791 | { 0x10562, 0x0 }, | 2791 | { 0x10562, 0x0 }, |
| 2792 | { 0x10662, 0x0 }, | 2792 | { 0x10662, 0x0 }, |
| 2793 | { 0x10762, 0x0 }, | 2793 | { 0x10762, 0x0 }, |
| 2794 | { 0x10862, 0x0 }, | 2794 | { 0x10862, 0x0 }, |
| 2795 | { 0x11062, 0x0 }, | 2795 | { 0x11062, 0x0 }, |
| 2796 | { 0x11162, 0x0 }, | 2796 | { 0x11162, 0x0 }, |
| 2797 | { 0x11262, 0x0 }, | 2797 | { 0x11262, 0x0 }, |
| 2798 | { 0x11362, 0x0 }, | 2798 | { 0x11362, 0x0 }, |
| 2799 | { 0x11462, 0x0 }, | 2799 | { 0x11462, 0x0 }, |
| 2800 | { 0x11562, 0x0 }, | 2800 | { 0x11562, 0x0 }, |
| 2801 | { 0x11662, 0x0 }, | 2801 | { 0x11662, 0x0 }, |
| 2802 | { 0x11762, 0x0 }, | 2802 | { 0x11762, 0x0 }, |
| 2803 | { 0x11862, 0x0 }, | 2803 | { 0x11862, 0x0 }, |
| 2804 | { 0x12062, 0x0 }, | 2804 | { 0x12062, 0x0 }, |
| 2805 | { 0x12162, 0x0 }, | 2805 | { 0x12162, 0x0 }, |
| 2806 | { 0x12262, 0x0 }, | 2806 | { 0x12262, 0x0 }, |
| 2807 | { 0x12362, 0x0 }, | 2807 | { 0x12362, 0x0 }, |
| 2808 | { 0x12462, 0x0 }, | 2808 | { 0x12462, 0x0 }, |
| 2809 | { 0x12562, 0x0 }, | 2809 | { 0x12562, 0x0 }, |
| 2810 | { 0x12662, 0x0 }, | 2810 | { 0x12662, 0x0 }, |
| 2811 | { 0x12762, 0x0 }, | 2811 | { 0x12762, 0x0 }, |
| 2812 | { 0x12862, 0x0 }, | 2812 | { 0x12862, 0x0 }, |
| 2813 | { 0x13062, 0x0 }, | 2813 | { 0x13062, 0x0 }, |
| 2814 | { 0x13162, 0x0 }, | 2814 | { 0x13162, 0x0 }, |
| 2815 | { 0x13262, 0x0 }, | 2815 | { 0x13262, 0x0 }, |
| 2816 | { 0x13362, 0x0 }, | 2816 | { 0x13362, 0x0 }, |
| 2817 | { 0x13462, 0x0 }, | 2817 | { 0x13462, 0x0 }, |
| 2818 | { 0x13562, 0x0 }, | 2818 | { 0x13562, 0x0 }, |
| 2819 | { 0x13662, 0x0 }, | 2819 | { 0x13662, 0x0 }, |
| 2820 | { 0x13762, 0x0 }, | 2820 | { 0x13762, 0x0 }, |
| 2821 | { 0x13862, 0x0 }, | 2821 | { 0x13862, 0x0 }, |
| 2822 | { 0x20077, 0x0 }, | 2822 | { 0x20077, 0x0 }, |
| 2823 | { 0x10001, 0x0 }, | 2823 | { 0x10001, 0x0 }, |
| 2824 | { 0x11001, 0x0 }, | 2824 | { 0x11001, 0x0 }, |
| 2825 | { 0x12001, 0x0 }, | 2825 | { 0x12001, 0x0 }, |
| 2826 | { 0x13001, 0x0 }, | 2826 | { 0x13001, 0x0 }, |
| 2827 | { 0x10040, 0x0 }, | 2827 | { 0x10040, 0x0 }, |
| 2828 | { 0x10140, 0x0 }, | 2828 | { 0x10140, 0x0 }, |
| 2829 | { 0x10240, 0x0 }, | 2829 | { 0x10240, 0x0 }, |
| 2830 | { 0x10340, 0x0 }, | 2830 | { 0x10340, 0x0 }, |
| 2831 | { 0x10440, 0x0 }, | 2831 | { 0x10440, 0x0 }, |
| 2832 | { 0x10540, 0x0 }, | 2832 | { 0x10540, 0x0 }, |
| 2833 | { 0x10640, 0x0 }, | 2833 | { 0x10640, 0x0 }, |
| 2834 | { 0x10740, 0x0 }, | 2834 | { 0x10740, 0x0 }, |
| 2835 | { 0x10840, 0x0 }, | 2835 | { 0x10840, 0x0 }, |
| 2836 | { 0x10030, 0x0 }, | 2836 | { 0x10030, 0x0 }, |
| 2837 | { 0x10130, 0x0 }, | 2837 | { 0x10130, 0x0 }, |
| 2838 | { 0x10230, 0x0 }, | 2838 | { 0x10230, 0x0 }, |
| 2839 | { 0x10330, 0x0 }, | 2839 | { 0x10330, 0x0 }, |
| 2840 | { 0x10430, 0x0 }, | 2840 | { 0x10430, 0x0 }, |
| 2841 | { 0x10530, 0x0 }, | 2841 | { 0x10530, 0x0 }, |
| 2842 | { 0x10630, 0x0 }, | 2842 | { 0x10630, 0x0 }, |
| 2843 | { 0x10730, 0x0 }, | 2843 | { 0x10730, 0x0 }, |
| 2844 | { 0x10830, 0x0 }, | 2844 | { 0x10830, 0x0 }, |
| 2845 | { 0x11040, 0x0 }, | 2845 | { 0x11040, 0x0 }, |
| 2846 | { 0x11140, 0x0 }, | 2846 | { 0x11140, 0x0 }, |
| 2847 | { 0x11240, 0x0 }, | 2847 | { 0x11240, 0x0 }, |
| 2848 | { 0x11340, 0x0 }, | 2848 | { 0x11340, 0x0 }, |
| 2849 | { 0x11440, 0x0 }, | 2849 | { 0x11440, 0x0 }, |
| 2850 | { 0x11540, 0x0 }, | 2850 | { 0x11540, 0x0 }, |
| 2851 | { 0x11640, 0x0 }, | 2851 | { 0x11640, 0x0 }, |
| 2852 | { 0x11740, 0x0 }, | 2852 | { 0x11740, 0x0 }, |
| 2853 | { 0x11840, 0x0 }, | 2853 | { 0x11840, 0x0 }, |
| 2854 | { 0x11030, 0x0 }, | 2854 | { 0x11030, 0x0 }, |
| 2855 | { 0x11130, 0x0 }, | 2855 | { 0x11130, 0x0 }, |
| 2856 | { 0x11230, 0x0 }, | 2856 | { 0x11230, 0x0 }, |
| 2857 | { 0x11330, 0x0 }, | 2857 | { 0x11330, 0x0 }, |
| 2858 | { 0x11430, 0x0 }, | 2858 | { 0x11430, 0x0 }, |
| 2859 | { 0x11530, 0x0 }, | 2859 | { 0x11530, 0x0 }, |
| 2860 | { 0x11630, 0x0 }, | 2860 | { 0x11630, 0x0 }, |
| 2861 | { 0x11730, 0x0 }, | 2861 | { 0x11730, 0x0 }, |
| 2862 | { 0x11830, 0x0 }, | 2862 | { 0x11830, 0x0 }, |
| 2863 | { 0x12040, 0x0 }, | 2863 | { 0x12040, 0x0 }, |
| 2864 | { 0x12140, 0x0 }, | 2864 | { 0x12140, 0x0 }, |
| 2865 | { 0x12240, 0x0 }, | 2865 | { 0x12240, 0x0 }, |
| 2866 | { 0x12340, 0x0 }, | 2866 | { 0x12340, 0x0 }, |
| 2867 | { 0x12440, 0x0 }, | 2867 | { 0x12440, 0x0 }, |
| 2868 | { 0x12540, 0x0 }, | 2868 | { 0x12540, 0x0 }, |
| 2869 | { 0x12640, 0x0 }, | 2869 | { 0x12640, 0x0 }, |
| 2870 | { 0x12740, 0x0 }, | 2870 | { 0x12740, 0x0 }, |
| 2871 | { 0x12840, 0x0 }, | 2871 | { 0x12840, 0x0 }, |
| 2872 | { 0x12030, 0x0 }, | 2872 | { 0x12030, 0x0 }, |
| 2873 | { 0x12130, 0x0 }, | 2873 | { 0x12130, 0x0 }, |
| 2874 | { 0x12230, 0x0 }, | 2874 | { 0x12230, 0x0 }, |
| 2875 | { 0x12330, 0x0 }, | 2875 | { 0x12330, 0x0 }, |
| 2876 | { 0x12430, 0x0 }, | 2876 | { 0x12430, 0x0 }, |
| 2877 | { 0x12530, 0x0 }, | 2877 | { 0x12530, 0x0 }, |
| 2878 | { 0x12630, 0x0 }, | 2878 | { 0x12630, 0x0 }, |
| 2879 | { 0x12730, 0x0 }, | 2879 | { 0x12730, 0x0 }, |
| 2880 | { 0x12830, 0x0 }, | 2880 | { 0x12830, 0x0 }, |
| 2881 | { 0x13040, 0x0 }, | 2881 | { 0x13040, 0x0 }, |
| 2882 | { 0x13140, 0x0 }, | 2882 | { 0x13140, 0x0 }, |
| 2883 | { 0x13240, 0x0 }, | 2883 | { 0x13240, 0x0 }, |
| 2884 | { 0x13340, 0x0 }, | 2884 | { 0x13340, 0x0 }, |
| 2885 | { 0x13440, 0x0 }, | 2885 | { 0x13440, 0x0 }, |
| 2886 | { 0x13540, 0x0 }, | 2886 | { 0x13540, 0x0 }, |
| 2887 | { 0x13640, 0x0 }, | 2887 | { 0x13640, 0x0 }, |
| 2888 | { 0x13740, 0x0 }, | 2888 | { 0x13740, 0x0 }, |
| 2889 | { 0x13840, 0x0 }, | 2889 | { 0x13840, 0x0 }, |
| 2890 | { 0x13030, 0x0 }, | 2890 | { 0x13030, 0x0 }, |
| 2891 | { 0x13130, 0x0 }, | 2891 | { 0x13130, 0x0 }, |
| 2892 | { 0x13230, 0x0 }, | 2892 | { 0x13230, 0x0 }, |
| 2893 | { 0x13330, 0x0 }, | 2893 | { 0x13330, 0x0 }, |
| 2894 | { 0x13430, 0x0 }, | 2894 | { 0x13430, 0x0 }, |
| 2895 | { 0x13530, 0x0 }, | 2895 | { 0x13530, 0x0 }, |
| 2896 | { 0x13630, 0x0 }, | 2896 | { 0x13630, 0x0 }, |
| 2897 | { 0x13730, 0x0 }, | 2897 | { 0x13730, 0x0 }, |
| 2898 | { 0x13830, 0x0 }, | 2898 | { 0x13830, 0x0 }, |
| 2899 | }; | 2899 | }; |
| 2900 | /* P0 message block paremeter for training firmware */ | 2900 | /* P0 message block paremeter for training firmware */ |
| 2901 | struct dram_cfg_param ddr_fsp0_cfg[] = { | 2901 | struct dram_cfg_param ddr_fsp0_cfg[] = { |
| 2902 | { 0xd0000, 0x0 }, | 2902 | { 0xd0000, 0x0 }, |
| 2903 | { 0x54003, 0xfa0 }, | 2903 | { 0x54003, 0xfa0 }, |
| 2904 | { 0x54004, 0x2 }, | 2904 | { 0x54004, 0x2 }, |
| 2905 | { 0x54005, 0x2228 }, | 2905 | { 0x54005, 0x2228 }, |
| 2906 | { 0x54006, 0x14 }, | 2906 | { 0x54006, 0x14 }, |
| 2907 | { 0x54008, 0x131f }, | 2907 | { 0x54008, 0x131f }, |
| 2908 | { 0x54009, 0xc8 }, | 2908 | { 0x54009, 0xc8 }, |
| 2909 | { 0x5400b, 0x2 }, | 2909 | { 0x5400b, 0x2 }, |
| 2910 | { 0x5400f, 0x100 }, | 2910 | { 0x5400f, 0x100 }, |
| 2911 | { 0x54012, 0x310 }, | 2911 | { 0x54012, 0x310 }, |
| 2912 | { 0x54019, 0x3ff4 }, | 2912 | { 0x54019, 0x3ff4 }, |
| 2913 | { 0x5401a, 0x33 }, | 2913 | { 0x5401a, 0x33 }, |
| 2914 | { 0x5401b, 0x4866 }, | 2914 | { 0x5401b, 0x4866 }, |
| 2915 | { 0x5401c, 0x4800 }, | 2915 | { 0x5401c, 0x4800 }, |
| 2916 | { 0x5401e, 0x16 }, | 2916 | { 0x5401e, 0x16 }, |
| 2917 | { 0x5401f, 0x3ff4 }, | 2917 | { 0x5401f, 0x3ff4 }, |
| 2918 | { 0x54020, 0x33 }, | 2918 | { 0x54020, 0x33 }, |
| 2919 | { 0x54021, 0x4866 }, | 2919 | { 0x54021, 0x4866 }, |
| 2920 | { 0x54022, 0x4800 }, | 2920 | { 0x54022, 0x4800 }, |
| 2921 | { 0x54024, 0x16 }, | 2921 | { 0x54024, 0x16 }, |
| 2922 | { 0x5402b, 0x1000 }, | 2922 | { 0x5402b, 0x1000 }, |
| 2923 | { 0x5402c, 0x3 }, | 2923 | { 0x5402c, 0x3 }, |
| 2924 | { 0x54032, 0xf400 }, | 2924 | { 0x54032, 0xf400 }, |
| 2925 | { 0x54033, 0x333f }, | 2925 | { 0x54033, 0x333f }, |
| 2926 | { 0x54034, 0x6600 }, | 2926 | { 0x54034, 0x6600 }, |
| 2927 | { 0x54035, 0x48 }, | 2927 | { 0x54035, 0x48 }, |
| 2928 | { 0x54036, 0x48 }, | 2928 | { 0x54036, 0x48 }, |
| 2929 | { 0x54037, 0x1600 }, | 2929 | { 0x54037, 0x1600 }, |
| 2930 | { 0x54038, 0xf400 }, | 2930 | { 0x54038, 0xf400 }, |
| 2931 | { 0x54039, 0x333f }, | 2931 | { 0x54039, 0x333f }, |
| 2932 | { 0x5403a, 0x6600 }, | 2932 | { 0x5403a, 0x6600 }, |
| 2933 | { 0x5403b, 0x48 }, | 2933 | { 0x5403b, 0x48 }, |
| 2934 | { 0x5403c, 0x48 }, | 2934 | { 0x5403c, 0x48 }, |
| 2935 | { 0x5403d, 0x1600 }, | 2935 | { 0x5403d, 0x1600 }, |
| 2936 | { 0xd0000, 0x1 }, | 2936 | { 0xd0000, 0x1 }, |
| 2937 | }; | 2937 | }; |
| 2938 | 2938 | ||
| 2939 | 2939 | ||
| 2940 | /* P1 message block paremeter for training firmware */ | 2940 | /* P1 message block paremeter for training firmware */ |
| 2941 | struct dram_cfg_param ddr_fsp1_cfg[] = { | 2941 | struct dram_cfg_param ddr_fsp1_cfg[] = { |
| 2942 | { 0xd0000, 0x0 }, | 2942 | { 0xd0000, 0x0 }, |
| 2943 | { 0x54002, 0x101 }, | 2943 | { 0x54002, 0x101 }, |
| 2944 | { 0x54003, 0x190 }, | 2944 | { 0x54003, 0x190 }, |
| 2945 | { 0x54004, 0x2 }, | 2945 | { 0x54004, 0x2 }, |
| 2946 | { 0x54005, 0x2228 }, | 2946 | { 0x54005, 0x2228 }, |
| 2947 | { 0x54006, 0x14 }, | 2947 | { 0x54006, 0x14 }, |
| 2948 | { 0x54008, 0x121f }, | 2948 | { 0x54008, 0x121f }, |
| 2949 | { 0x54009, 0xc8 }, | 2949 | { 0x54009, 0xc8 }, |
| 2950 | { 0x5400b, 0x2 }, | 2950 | { 0x5400b, 0x2 }, |
| 2951 | { 0x5400f, 0x100 }, | 2951 | { 0x5400f, 0x100 }, |
| 2952 | { 0x54012, 0x310 }, | 2952 | { 0x54012, 0x310 }, |
| 2953 | { 0x54019, 0x84 }, | 2953 | { 0x54019, 0x84 }, |
| 2954 | { 0x5401a, 0x33 }, | 2954 | { 0x5401a, 0x33 }, |
| 2955 | { 0x5401b, 0x4866 }, | 2955 | { 0x5401b, 0x4866 }, |
| 2956 | { 0x5401c, 0x4800 }, | 2956 | { 0x5401c, 0x4800 }, |
| 2957 | { 0x5401e, 0x16 }, | 2957 | { 0x5401e, 0x16 }, |
| 2958 | { 0x5401f, 0x84 }, | 2958 | { 0x5401f, 0x84 }, |
| 2959 | { 0x54020, 0x33 }, | 2959 | { 0x54020, 0x33 }, |
| 2960 | { 0x54021, 0x4866 }, | 2960 | { 0x54021, 0x4866 }, |
| 2961 | { 0x54022, 0x4800 }, | 2961 | { 0x54022, 0x4800 }, |
| 2962 | { 0x54024, 0x16 }, | 2962 | { 0x54024, 0x16 }, |
| 2963 | { 0x5402b, 0x1000 }, | 2963 | { 0x5402b, 0x1000 }, |
| 2964 | { 0x5402c, 0x3 }, | 2964 | { 0x5402c, 0x3 }, |
| 2965 | { 0x54032, 0x8400 }, | 2965 | { 0x54032, 0x8400 }, |
| 2966 | { 0x54033, 0x3300 }, | 2966 | { 0x54033, 0x3300 }, |
| 2967 | { 0x54034, 0x6600 }, | 2967 | { 0x54034, 0x6600 }, |
| 2968 | { 0x54035, 0x48 }, | 2968 | { 0x54035, 0x48 }, |
| 2969 | { 0x54036, 0x48 }, | 2969 | { 0x54036, 0x48 }, |
| 2970 | { 0x54037, 0x1600 }, | 2970 | { 0x54037, 0x1600 }, |
| 2971 | { 0x54038, 0x8400 }, | 2971 | { 0x54038, 0x8400 }, |
| 2972 | { 0x54039, 0x3300 }, | 2972 | { 0x54039, 0x3300 }, |
| 2973 | { 0x5403a, 0x6600 }, | 2973 | { 0x5403a, 0x6600 }, |
| 2974 | { 0x5403b, 0x48 }, | 2974 | { 0x5403b, 0x48 }, |
| 2975 | { 0x5403c, 0x48 }, | 2975 | { 0x5403c, 0x48 }, |
| 2976 | { 0x5403d, 0x1600 }, | 2976 | { 0x5403d, 0x1600 }, |
| 2977 | { 0xd0000, 0x1 }, | 2977 | { 0xd0000, 0x1 }, |
| 2978 | }; | 2978 | }; |
| 2979 | 2979 | ||
| 2980 | 2980 | ||
| 2981 | /* P2 message block paremeter for training firmware */ | 2981 | /* P2 message block paremeter for training firmware */ |
| 2982 | struct dram_cfg_param ddr_fsp2_cfg[] = { | 2982 | struct dram_cfg_param ddr_fsp2_cfg[] = { |
| 2983 | { 0xd0000, 0x0 }, | 2983 | { 0xd0000, 0x0 }, |
| 2984 | { 0x54002, 0x102 }, | 2984 | { 0x54002, 0x102 }, |
| 2985 | { 0x54003, 0x64 }, | 2985 | { 0x54003, 0x64 }, |
| 2986 | { 0x54004, 0x2 }, | 2986 | { 0x54004, 0x2 }, |
| 2987 | { 0x54005, 0x2228 }, | 2987 | { 0x54005, 0x2228 }, |
| 2988 | { 0x54006, 0x14 }, | 2988 | { 0x54006, 0x14 }, |
| 2989 | { 0x54008, 0x121f }, | 2989 | { 0x54008, 0x121f }, |
| 2990 | { 0x54009, 0xc8 }, | 2990 | { 0x54009, 0xc8 }, |
| 2991 | { 0x5400b, 0x2 }, | 2991 | { 0x5400b, 0x2 }, |
| 2992 | { 0x5400f, 0x100 }, | 2992 | { 0x5400f, 0x100 }, |
| 2993 | { 0x54012, 0x310 }, | 2993 | { 0x54012, 0x310 }, |
| 2994 | { 0x54019, 0x84 }, | 2994 | { 0x54019, 0x84 }, |
| 2995 | { 0x5401a, 0x33 }, | 2995 | { 0x5401a, 0x33 }, |
| 2996 | { 0x5401b, 0x4866 }, | 2996 | { 0x5401b, 0x4866 }, |
| 2997 | { 0x5401c, 0x4800 }, | 2997 | { 0x5401c, 0x4800 }, |
| 2998 | { 0x5401e, 0x16 }, | 2998 | { 0x5401e, 0x16 }, |
| 2999 | { 0x5401f, 0x84 }, | 2999 | { 0x5401f, 0x84 }, |
| 3000 | { 0x54020, 0x33 }, | 3000 | { 0x54020, 0x33 }, |
| 3001 | { 0x54021, 0x4866 }, | 3001 | { 0x54021, 0x4866 }, |
| 3002 | { 0x54022, 0x4800 }, | 3002 | { 0x54022, 0x4800 }, |
| 3003 | { 0x54024, 0x16 }, | 3003 | { 0x54024, 0x16 }, |
| 3004 | { 0x5402b, 0x1000 }, | 3004 | { 0x5402b, 0x1000 }, |
| 3005 | { 0x5402c, 0x3 }, | 3005 | { 0x5402c, 0x3 }, |
| 3006 | { 0x54032, 0x8400 }, | 3006 | { 0x54032, 0x8400 }, |
| 3007 | { 0x54033, 0x3300 }, | 3007 | { 0x54033, 0x3300 }, |
| 3008 | { 0x54034, 0x6600 }, | 3008 | { 0x54034, 0x6600 }, |
| 3009 | { 0x54035, 0x48 }, | 3009 | { 0x54035, 0x48 }, |
| 3010 | { 0x54036, 0x48 }, | 3010 | { 0x54036, 0x48 }, |
| 3011 | { 0x54037, 0x1600 }, | 3011 | { 0x54037, 0x1600 }, |
| 3012 | { 0x54038, 0x8400 }, | 3012 | { 0x54038, 0x8400 }, |
| 3013 | { 0x54039, 0x3300 }, | 3013 | { 0x54039, 0x3300 }, |
| 3014 | { 0x5403a, 0x6600 }, | 3014 | { 0x5403a, 0x6600 }, |
| 3015 | { 0x5403b, 0x48 }, | 3015 | { 0x5403b, 0x48 }, |
| 3016 | { 0x5403c, 0x48 }, | 3016 | { 0x5403c, 0x48 }, |
| 3017 | { 0x5403d, 0x1600 }, | 3017 | { 0x5403d, 0x1600 }, |
| 3018 | { 0xd0000, 0x1 }, | 3018 | { 0xd0000, 0x1 }, |
| 3019 | }; | 3019 | }; |
| 3020 | 3020 | ||
| 3021 | 3021 | ||
| 3022 | /* P0 2D message block paremeter for training firmware */ | 3022 | /* P0 2D message block paremeter for training firmware */ |
| 3023 | struct dram_cfg_param ddr_fsp0_2d_cfg[] = { | 3023 | struct dram_cfg_param ddr_fsp0_2d_cfg[] = { |
| 3024 | { 0xd0000, 0x0 }, | 3024 | { 0xd0000, 0x0 }, |
| 3025 | { 0x54003, 0xfa0 }, | 3025 | { 0x54003, 0xfa0 }, |
| 3026 | { 0x54004, 0x2 }, | 3026 | { 0x54004, 0x2 }, |
| 3027 | { 0x54005, 0x2228 }, | 3027 | { 0x54005, 0x2228 }, |
| 3028 | { 0x54006, 0x14 }, | 3028 | { 0x54006, 0x14 }, |
| 3029 | { 0x54008, 0x61 }, | 3029 | { 0x54008, 0x61 }, |
| 3030 | { 0x54009, 0xc8 }, | 3030 | { 0x54009, 0xc8 }, |
| 3031 | { 0x5400b, 0x2 }, | 3031 | { 0x5400b, 0x2 }, |
| 3032 | { 0x5400f, 0x100 }, | 3032 | { 0x5400f, 0x100 }, |
| 3033 | { 0x54010, 0x1f7f }, | 3033 | { 0x54010, 0x1f7f }, |
| 3034 | { 0x54012, 0x310 }, | 3034 | { 0x54012, 0x310 }, |
| 3035 | { 0x54019, 0x3ff4 }, | 3035 | { 0x54019, 0x3ff4 }, |
| 3036 | { 0x5401a, 0x33 }, | 3036 | { 0x5401a, 0x33 }, |
| 3037 | { 0x5401b, 0x4866 }, | 3037 | { 0x5401b, 0x4866 }, |
| 3038 | { 0x5401c, 0x4800 }, | 3038 | { 0x5401c, 0x4800 }, |
| 3039 | { 0x5401e, 0x16 }, | 3039 | { 0x5401e, 0x16 }, |
| 3040 | { 0x5401f, 0x3ff4 }, | 3040 | { 0x5401f, 0x3ff4 }, |
| 3041 | { 0x54020, 0x33 }, | 3041 | { 0x54020, 0x33 }, |
| 3042 | { 0x54021, 0x4866 }, | 3042 | { 0x54021, 0x4866 }, |
| 3043 | { 0x54022, 0x4800 }, | 3043 | { 0x54022, 0x4800 }, |
| 3044 | { 0x54024, 0x16 }, | 3044 | { 0x54024, 0x16 }, |
| 3045 | { 0x5402b, 0x1000 }, | 3045 | { 0x5402b, 0x1000 }, |
| 3046 | { 0x5402c, 0x3 }, | 3046 | { 0x5402c, 0x3 }, |
| 3047 | { 0x54032, 0xf400 }, | 3047 | { 0x54032, 0xf400 }, |
| 3048 | { 0x54033, 0x333f }, | 3048 | { 0x54033, 0x333f }, |
| 3049 | { 0x54034, 0x6600 }, | 3049 | { 0x54034, 0x6600 }, |
| 3050 | { 0x54035, 0x48 }, | 3050 | { 0x54035, 0x48 }, |
| 3051 | { 0x54036, 0x48 }, | 3051 | { 0x54036, 0x48 }, |
| 3052 | { 0x54037, 0x1600 }, | 3052 | { 0x54037, 0x1600 }, |
| 3053 | { 0x54038, 0xf400 }, | 3053 | { 0x54038, 0xf400 }, |
| 3054 | { 0x54039, 0x333f }, | 3054 | { 0x54039, 0x333f }, |
| 3055 | { 0x5403a, 0x6600 }, | 3055 | { 0x5403a, 0x6600 }, |
| 3056 | { 0x5403b, 0x48 }, | 3056 | { 0x5403b, 0x48 }, |
| 3057 | { 0x5403c, 0x48 }, | 3057 | { 0x5403c, 0x48 }, |
| 3058 | { 0x5403d, 0x1600 }, | 3058 | { 0x5403d, 0x1600 }, |
| 3059 | { 0xd0000, 0x1 }, | 3059 | { 0xd0000, 0x1 }, |
| 3060 | }; | 3060 | }; |
| 3061 | 3061 | ||
| 3062 | /* DRAM PHY init engine image */ | 3062 | /* DRAM PHY init engine image */ |
| 3063 | struct dram_cfg_param ddr_phy_pie[] = { | 3063 | struct dram_cfg_param ddr_phy_pie[] = { |
| 3064 | { 0xd0000, 0x0 }, | 3064 | { 0xd0000, 0x0 }, |
| 3065 | { 0x90000, 0x10 }, | 3065 | { 0x90000, 0x10 }, |
| 3066 | { 0x90001, 0x400 }, | 3066 | { 0x90001, 0x400 }, |
| 3067 | { 0x90002, 0x10e }, | 3067 | { 0x90002, 0x10e }, |
| 3068 | { 0x90003, 0x0 }, | 3068 | { 0x90003, 0x0 }, |
| 3069 | { 0x90004, 0x0 }, | 3069 | { 0x90004, 0x0 }, |
| 3070 | { 0x90005, 0x8 }, | 3070 | { 0x90005, 0x8 }, |
| 3071 | { 0x90029, 0xb }, | 3071 | { 0x90029, 0xb }, |
| 3072 | { 0x9002a, 0x480 }, | 3072 | { 0x9002a, 0x480 }, |
| 3073 | { 0x9002b, 0x109 }, | 3073 | { 0x9002b, 0x109 }, |
| 3074 | { 0x9002c, 0x8 }, | 3074 | { 0x9002c, 0x8 }, |
| 3075 | { 0x9002d, 0x448 }, | 3075 | { 0x9002d, 0x448 }, |
| 3076 | { 0x9002e, 0x139 }, | 3076 | { 0x9002e, 0x139 }, |
| 3077 | { 0x9002f, 0x8 }, | 3077 | { 0x9002f, 0x8 }, |
| 3078 | { 0x90030, 0x478 }, | 3078 | { 0x90030, 0x478 }, |
| 3079 | { 0x90031, 0x109 }, | 3079 | { 0x90031, 0x109 }, |
| 3080 | { 0x90032, 0x0 }, | 3080 | { 0x90032, 0x0 }, |
| 3081 | { 0x90033, 0xe8 }, | 3081 | { 0x90033, 0xe8 }, |
| 3082 | { 0x90034, 0x109 }, | 3082 | { 0x90034, 0x109 }, |
| 3083 | { 0x90035, 0x2 }, | 3083 | { 0x90035, 0x2 }, |
| 3084 | { 0x90036, 0x10 }, | 3084 | { 0x90036, 0x10 }, |
| 3085 | { 0x90037, 0x139 }, | 3085 | { 0x90037, 0x139 }, |
| 3086 | { 0x90038, 0xb }, | 3086 | { 0x90038, 0xb }, |
| 3087 | { 0x90039, 0x7c0 }, | 3087 | { 0x90039, 0x7c0 }, |
| 3088 | { 0x9003a, 0x139 }, | 3088 | { 0x9003a, 0x139 }, |
| 3089 | { 0x9003b, 0x44 }, | 3089 | { 0x9003b, 0x44 }, |
| 3090 | { 0x9003c, 0x633 }, | 3090 | { 0x9003c, 0x633 }, |
| 3091 | { 0x9003d, 0x159 }, | 3091 | { 0x9003d, 0x159 }, |
| 3092 | { 0x9003e, 0x14f }, | 3092 | { 0x9003e, 0x14f }, |
| 3093 | { 0x9003f, 0x630 }, | 3093 | { 0x9003f, 0x630 }, |
| 3094 | { 0x90040, 0x159 }, | 3094 | { 0x90040, 0x159 }, |
| 3095 | { 0x90041, 0x47 }, | 3095 | { 0x90041, 0x47 }, |
| 3096 | { 0x90042, 0x633 }, | 3096 | { 0x90042, 0x633 }, |
| 3097 | { 0x90043, 0x149 }, | 3097 | { 0x90043, 0x149 }, |
| 3098 | { 0x90044, 0x4f }, | 3098 | { 0x90044, 0x4f }, |
| 3099 | { 0x90045, 0x633 }, | 3099 | { 0x90045, 0x633 }, |
| 3100 | { 0x90046, 0x179 }, | 3100 | { 0x90046, 0x179 }, |
| 3101 | { 0x90047, 0x8 }, | 3101 | { 0x90047, 0x8 }, |
| 3102 | { 0x90048, 0xe0 }, | 3102 | { 0x90048, 0xe0 }, |
| 3103 | { 0x90049, 0x109 }, | 3103 | { 0x90049, 0x109 }, |
| 3104 | { 0x9004a, 0x0 }, | 3104 | { 0x9004a, 0x0 }, |
| 3105 | { 0x9004b, 0x7c8 }, | 3105 | { 0x9004b, 0x7c8 }, |
| 3106 | { 0x9004c, 0x109 }, | 3106 | { 0x9004c, 0x109 }, |
| 3107 | { 0x9004d, 0x0 }, | 3107 | { 0x9004d, 0x0 }, |
| 3108 | { 0x9004e, 0x1 }, | 3108 | { 0x9004e, 0x1 }, |
| 3109 | { 0x9004f, 0x8 }, | 3109 | { 0x9004f, 0x8 }, |
| 3110 | { 0x90050, 0x0 }, | 3110 | { 0x90050, 0x0 }, |
| 3111 | { 0x90051, 0x45a }, | 3111 | { 0x90051, 0x45a }, |
| 3112 | { 0x90052, 0x9 }, | 3112 | { 0x90052, 0x9 }, |
| 3113 | { 0x90053, 0x0 }, | 3113 | { 0x90053, 0x0 }, |
| 3114 | { 0x90054, 0x448 }, | 3114 | { 0x90054, 0x448 }, |
| 3115 | { 0x90055, 0x109 }, | 3115 | { 0x90055, 0x109 }, |
| 3116 | { 0x90056, 0x40 }, | 3116 | { 0x90056, 0x40 }, |
| 3117 | { 0x90057, 0x633 }, | 3117 | { 0x90057, 0x633 }, |
| 3118 | { 0x90058, 0x179 }, | 3118 | { 0x90058, 0x179 }, |
| 3119 | { 0x90059, 0x1 }, | 3119 | { 0x90059, 0x1 }, |
| 3120 | { 0x9005a, 0x618 }, | 3120 | { 0x9005a, 0x618 }, |
| 3121 | { 0x9005b, 0x109 }, | 3121 | { 0x9005b, 0x109 }, |
| 3122 | { 0x9005c, 0x40c0 }, | 3122 | { 0x9005c, 0x40c0 }, |
| 3123 | { 0x9005d, 0x633 }, | 3123 | { 0x9005d, 0x633 }, |
| 3124 | { 0x9005e, 0x149 }, | 3124 | { 0x9005e, 0x149 }, |
| 3125 | { 0x9005f, 0x8 }, | 3125 | { 0x9005f, 0x8 }, |
| 3126 | { 0x90060, 0x4 }, | 3126 | { 0x90060, 0x4 }, |
| 3127 | { 0x90061, 0x48 }, | 3127 | { 0x90061, 0x48 }, |
| 3128 | { 0x90062, 0x4040 }, | 3128 | { 0x90062, 0x4040 }, |
| 3129 | { 0x90063, 0x633 }, | 3129 | { 0x90063, 0x633 }, |
| 3130 | { 0x90064, 0x149 }, | 3130 | { 0x90064, 0x149 }, |
| 3131 | { 0x90065, 0x0 }, | 3131 | { 0x90065, 0x0 }, |
| 3132 | { 0x90066, 0x4 }, | 3132 | { 0x90066, 0x4 }, |
| 3133 | { 0x90067, 0x48 }, | 3133 | { 0x90067, 0x48 }, |
| 3134 | { 0x90068, 0x40 }, | 3134 | { 0x90068, 0x40 }, |
| 3135 | { 0x90069, 0x633 }, | 3135 | { 0x90069, 0x633 }, |
| 3136 | { 0x9006a, 0x149 }, | 3136 | { 0x9006a, 0x149 }, |
| 3137 | { 0x9006b, 0x10 }, | 3137 | { 0x9006b, 0x10 }, |
| 3138 | { 0x9006c, 0x4 }, | 3138 | { 0x9006c, 0x4 }, |
| 3139 | { 0x9006d, 0x18 }, | 3139 | { 0x9006d, 0x18 }, |
| 3140 | { 0x9006e, 0x0 }, | 3140 | { 0x9006e, 0x0 }, |
| 3141 | { 0x9006f, 0x4 }, | 3141 | { 0x9006f, 0x4 }, |
| 3142 | { 0x90070, 0x78 }, | 3142 | { 0x90070, 0x78 }, |
| 3143 | { 0x90071, 0x549 }, | 3143 | { 0x90071, 0x549 }, |
| 3144 | { 0x90072, 0x633 }, | 3144 | { 0x90072, 0x633 }, |
| 3145 | { 0x90073, 0x159 }, | 3145 | { 0x90073, 0x159 }, |
| 3146 | { 0x90074, 0xd49 }, | 3146 | { 0x90074, 0xd49 }, |
| 3147 | { 0x90075, 0x633 }, | 3147 | { 0x90075, 0x633 }, |
| 3148 | { 0x90076, 0x159 }, | 3148 | { 0x90076, 0x159 }, |
| 3149 | { 0x90077, 0x94a }, | 3149 | { 0x90077, 0x94a }, |
| 3150 | { 0x90078, 0x633 }, | 3150 | { 0x90078, 0x633 }, |
| 3151 | { 0x90079, 0x159 }, | 3151 | { 0x90079, 0x159 }, |
| 3152 | { 0x9007a, 0x441 }, | 3152 | { 0x9007a, 0x441 }, |
| 3153 | { 0x9007b, 0x633 }, | 3153 | { 0x9007b, 0x633 }, |
| 3154 | { 0x9007c, 0x149 }, | 3154 | { 0x9007c, 0x149 }, |
| 3155 | { 0x9007d, 0x42 }, | 3155 | { 0x9007d, 0x42 }, |
| 3156 | { 0x9007e, 0x633 }, | 3156 | { 0x9007e, 0x633 }, |
| 3157 | { 0x9007f, 0x149 }, | 3157 | { 0x9007f, 0x149 }, |
| 3158 | { 0x90080, 0x1 }, | 3158 | { 0x90080, 0x1 }, |
| 3159 | { 0x90081, 0x633 }, | 3159 | { 0x90081, 0x633 }, |
| 3160 | { 0x90082, 0x149 }, | 3160 | { 0x90082, 0x149 }, |
| 3161 | { 0x90083, 0x0 }, | 3161 | { 0x90083, 0x0 }, |
| 3162 | { 0x90084, 0xe0 }, | 3162 | { 0x90084, 0xe0 }, |
| 3163 | { 0x90085, 0x109 }, | 3163 | { 0x90085, 0x109 }, |
| 3164 | { 0x90086, 0xa }, | 3164 | { 0x90086, 0xa }, |
| 3165 | { 0x90087, 0x10 }, | 3165 | { 0x90087, 0x10 }, |
| 3166 | { 0x90088, 0x109 }, | 3166 | { 0x90088, 0x109 }, |
| 3167 | { 0x90089, 0x9 }, | 3167 | { 0x90089, 0x9 }, |
| 3168 | { 0x9008a, 0x3c0 }, | 3168 | { 0x9008a, 0x3c0 }, |
| 3169 | { 0x9008b, 0x149 }, | 3169 | { 0x9008b, 0x149 }, |
| 3170 | { 0x9008c, 0x9 }, | 3170 | { 0x9008c, 0x9 }, |
| 3171 | { 0x9008d, 0x3c0 }, | 3171 | { 0x9008d, 0x3c0 }, |
| 3172 | { 0x9008e, 0x159 }, | 3172 | { 0x9008e, 0x159 }, |
| 3173 | { 0x9008f, 0x18 }, | 3173 | { 0x9008f, 0x18 }, |
| 3174 | { 0x90090, 0x10 }, | 3174 | { 0x90090, 0x10 }, |
| 3175 | { 0x90091, 0x109 }, | 3175 | { 0x90091, 0x109 }, |
| 3176 | { 0x90092, 0x0 }, | 3176 | { 0x90092, 0x0 }, |
| 3177 | { 0x90093, 0x3c0 }, | 3177 | { 0x90093, 0x3c0 }, |
| 3178 | { 0x90094, 0x109 }, | 3178 | { 0x90094, 0x109 }, |
| 3179 | { 0x90095, 0x18 }, | 3179 | { 0x90095, 0x18 }, |
| 3180 | { 0x90096, 0x4 }, | 3180 | { 0x90096, 0x4 }, |
| 3181 | { 0x90097, 0x48 }, | 3181 | { 0x90097, 0x48 }, |
| 3182 | { 0x90098, 0x18 }, | 3182 | { 0x90098, 0x18 }, |
| 3183 | { 0x90099, 0x4 }, | 3183 | { 0x90099, 0x4 }, |
| 3184 | { 0x9009a, 0x58 }, | 3184 | { 0x9009a, 0x58 }, |
| 3185 | { 0x9009b, 0xb }, | 3185 | { 0x9009b, 0xb }, |
| 3186 | { 0x9009c, 0x10 }, | 3186 | { 0x9009c, 0x10 }, |
| 3187 | { 0x9009d, 0x109 }, | 3187 | { 0x9009d, 0x109 }, |
| 3188 | { 0x9009e, 0x1 }, | 3188 | { 0x9009e, 0x1 }, |
| 3189 | { 0x9009f, 0x10 }, | 3189 | { 0x9009f, 0x10 }, |
| 3190 | { 0x900a0, 0x109 }, | 3190 | { 0x900a0, 0x109 }, |
| 3191 | { 0x900a1, 0x5 }, | 3191 | { 0x900a1, 0x5 }, |
| 3192 | { 0x900a2, 0x7c0 }, | 3192 | { 0x900a2, 0x7c0 }, |
| 3193 | { 0x900a3, 0x109 }, | 3193 | { 0x900a3, 0x109 }, |
| 3194 | { 0x40000, 0x811 }, | 3194 | { 0x40000, 0x811 }, |
| 3195 | { 0x40020, 0x880 }, | 3195 | { 0x40020, 0x880 }, |
| 3196 | { 0x40040, 0x0 }, | 3196 | { 0x40040, 0x0 }, |
| 3197 | { 0x40060, 0x0 }, | 3197 | { 0x40060, 0x0 }, |
| 3198 | { 0x40001, 0x4008 }, | 3198 | { 0x40001, 0x4008 }, |
| 3199 | { 0x40021, 0x83 }, | 3199 | { 0x40021, 0x83 }, |
| 3200 | { 0x40041, 0x4f }, | 3200 | { 0x40041, 0x4f }, |
| 3201 | { 0x40061, 0x0 }, | 3201 | { 0x40061, 0x0 }, |
| 3202 | { 0x40002, 0x4040 }, | 3202 | { 0x40002, 0x4040 }, |
| 3203 | { 0x40022, 0x83 }, | 3203 | { 0x40022, 0x83 }, |
| 3204 | { 0x40042, 0x51 }, | 3204 | { 0x40042, 0x51 }, |
| 3205 | { 0x40062, 0x0 }, | 3205 | { 0x40062, 0x0 }, |
| 3206 | { 0x40003, 0x811 }, | 3206 | { 0x40003, 0x811 }, |
| 3207 | { 0x40023, 0x880 }, | 3207 | { 0x40023, 0x880 }, |
| 3208 | { 0x40043, 0x0 }, | 3208 | { 0x40043, 0x0 }, |
| 3209 | { 0x40063, 0x0 }, | 3209 | { 0x40063, 0x0 }, |
| 3210 | { 0x40004, 0x720 }, | 3210 | { 0x40004, 0x720 }, |
| 3211 | { 0x40024, 0xf }, | 3211 | { 0x40024, 0xf }, |
| 3212 | { 0x40044, 0x1740 }, | 3212 | { 0x40044, 0x1740 }, |
| 3213 | { 0x40064, 0x0 }, | 3213 | { 0x40064, 0x0 }, |
| 3214 | { 0x40005, 0x16 }, | 3214 | { 0x40005, 0x16 }, |
| 3215 | { 0x40025, 0x83 }, | 3215 | { 0x40025, 0x83 }, |
| 3216 | { 0x40045, 0x4b }, | 3216 | { 0x40045, 0x4b }, |
| 3217 | { 0x40065, 0x0 }, | 3217 | { 0x40065, 0x0 }, |
| 3218 | { 0x40006, 0x716 }, | 3218 | { 0x40006, 0x716 }, |
| 3219 | { 0x40026, 0xf }, | 3219 | { 0x40026, 0xf }, |
| 3220 | { 0x40046, 0x2001 }, | 3220 | { 0x40046, 0x2001 }, |
| 3221 | { 0x40066, 0x0 }, | 3221 | { 0x40066, 0x0 }, |
| 3222 | { 0x40007, 0x716 }, | 3222 | { 0x40007, 0x716 }, |
| 3223 | { 0x40027, 0xf }, | 3223 | { 0x40027, 0xf }, |
| 3224 | { 0x40047, 0x2800 }, | 3224 | { 0x40047, 0x2800 }, |
| 3225 | { 0x40067, 0x0 }, | 3225 | { 0x40067, 0x0 }, |
| 3226 | { 0x40008, 0x716 }, | 3226 | { 0x40008, 0x716 }, |
| 3227 | { 0x40028, 0xf }, | 3227 | { 0x40028, 0xf }, |
| 3228 | { 0x40048, 0xf00 }, | 3228 | { 0x40048, 0xf00 }, |
| 3229 | { 0x40068, 0x0 }, | 3229 | { 0x40068, 0x0 }, |
| 3230 | { 0x40009, 0x720 }, | 3230 | { 0x40009, 0x720 }, |
| 3231 | { 0x40029, 0xf }, | 3231 | { 0x40029, 0xf }, |
| 3232 | { 0x40049, 0x1400 }, | 3232 | { 0x40049, 0x1400 }, |
| 3233 | { 0x40069, 0x0 }, | 3233 | { 0x40069, 0x0 }, |
| 3234 | { 0x4000a, 0xe08 }, | 3234 | { 0x4000a, 0xe08 }, |
| 3235 | { 0x4002a, 0xc15 }, | 3235 | { 0x4002a, 0xc15 }, |
| 3236 | { 0x4004a, 0x0 }, | 3236 | { 0x4004a, 0x0 }, |
| 3237 | { 0x4006a, 0x0 }, | 3237 | { 0x4006a, 0x0 }, |
| 3238 | { 0x4000b, 0x625 }, | 3238 | { 0x4000b, 0x625 }, |
| 3239 | { 0x4002b, 0x15 }, | 3239 | { 0x4002b, 0x15 }, |
| 3240 | { 0x4004b, 0x0 }, | 3240 | { 0x4004b, 0x0 }, |
| 3241 | { 0x4006b, 0x0 }, | 3241 | { 0x4006b, 0x0 }, |
| 3242 | { 0x4000c, 0x4028 }, | 3242 | { 0x4000c, 0x4028 }, |
| 3243 | { 0x4002c, 0x80 }, | 3243 | { 0x4002c, 0x80 }, |
| 3244 | { 0x4004c, 0x0 }, | 3244 | { 0x4004c, 0x0 }, |
| 3245 | { 0x4006c, 0x0 }, | 3245 | { 0x4006c, 0x0 }, |
| 3246 | { 0x4000d, 0xe08 }, | 3246 | { 0x4000d, 0xe08 }, |
| 3247 | { 0x4002d, 0xc1a }, | 3247 | { 0x4002d, 0xc1a }, |
| 3248 | { 0x4004d, 0x0 }, | 3248 | { 0x4004d, 0x0 }, |
| 3249 | { 0x4006d, 0x0 }, | 3249 | { 0x4006d, 0x0 }, |
| 3250 | { 0x4000e, 0x625 }, | 3250 | { 0x4000e, 0x625 }, |
| 3251 | { 0x4002e, 0x1a }, | 3251 | { 0x4002e, 0x1a }, |
| 3252 | { 0x4004e, 0x0 }, | 3252 | { 0x4004e, 0x0 }, |
| 3253 | { 0x4006e, 0x0 }, | 3253 | { 0x4006e, 0x0 }, |
| 3254 | { 0x4000f, 0x4040 }, | 3254 | { 0x4000f, 0x4040 }, |
| 3255 | { 0x4002f, 0x80 }, | 3255 | { 0x4002f, 0x80 }, |
| 3256 | { 0x4004f, 0x0 }, | 3256 | { 0x4004f, 0x0 }, |
| 3257 | { 0x4006f, 0x0 }, | 3257 | { 0x4006f, 0x0 }, |
| 3258 | { 0x40010, 0x2604 }, | 3258 | { 0x40010, 0x2604 }, |
| 3259 | { 0x40030, 0x15 }, | 3259 | { 0x40030, 0x15 }, |
| 3260 | { 0x40050, 0x0 }, | 3260 | { 0x40050, 0x0 }, |
| 3261 | { 0x40070, 0x0 }, | 3261 | { 0x40070, 0x0 }, |
| 3262 | { 0x40011, 0x708 }, | 3262 | { 0x40011, 0x708 }, |
| 3263 | { 0x40031, 0x5 }, | 3263 | { 0x40031, 0x5 }, |
| 3264 | { 0x40051, 0x0 }, | 3264 | { 0x40051, 0x0 }, |
| 3265 | { 0x40071, 0x2002 }, | 3265 | { 0x40071, 0x2002 }, |
| 3266 | { 0x40012, 0x8 }, | 3266 | { 0x40012, 0x8 }, |
| 3267 | { 0x40032, 0x80 }, | 3267 | { 0x40032, 0x80 }, |
| 3268 | { 0x40052, 0x0 }, | 3268 | { 0x40052, 0x0 }, |
| 3269 | { 0x40072, 0x0 }, | 3269 | { 0x40072, 0x0 }, |
| 3270 | { 0x40013, 0x2604 }, | 3270 | { 0x40013, 0x2604 }, |
| 3271 | { 0x40033, 0x1a }, | 3271 | { 0x40033, 0x1a }, |
| 3272 | { 0x40053, 0x0 }, | 3272 | { 0x40053, 0x0 }, |
| 3273 | { 0x40073, 0x0 }, | 3273 | { 0x40073, 0x0 }, |
| 3274 | { 0x40014, 0x708 }, | 3274 | { 0x40014, 0x708 }, |
| 3275 | { 0x40034, 0xa }, | 3275 | { 0x40034, 0xa }, |
| 3276 | { 0x40054, 0x0 }, | 3276 | { 0x40054, 0x0 }, |
| 3277 | { 0x40074, 0x2002 }, | 3277 | { 0x40074, 0x2002 }, |
| 3278 | { 0x40015, 0x4040 }, | 3278 | { 0x40015, 0x4040 }, |
| 3279 | { 0x40035, 0x80 }, | 3279 | { 0x40035, 0x80 }, |
| 3280 | { 0x40055, 0x0 }, | 3280 | { 0x40055, 0x0 }, |
| 3281 | { 0x40075, 0x0 }, | 3281 | { 0x40075, 0x0 }, |
| 3282 | { 0x40016, 0x60a }, | 3282 | { 0x40016, 0x60a }, |
| 3283 | { 0x40036, 0x15 }, | 3283 | { 0x40036, 0x15 }, |
| 3284 | { 0x40056, 0x1200 }, | 3284 | { 0x40056, 0x1200 }, |
| 3285 | { 0x40076, 0x0 }, | 3285 | { 0x40076, 0x0 }, |
| 3286 | { 0x40017, 0x61a }, | 3286 | { 0x40017, 0x61a }, |
| 3287 | { 0x40037, 0x15 }, | 3287 | { 0x40037, 0x15 }, |
| 3288 | { 0x40057, 0x1300 }, | 3288 | { 0x40057, 0x1300 }, |
| 3289 | { 0x40077, 0x0 }, | 3289 | { 0x40077, 0x0 }, |
| 3290 | { 0x40018, 0x60a }, | 3290 | { 0x40018, 0x60a }, |
| 3291 | { 0x40038, 0x1a }, | 3291 | { 0x40038, 0x1a }, |
| 3292 | { 0x40058, 0x1200 }, | 3292 | { 0x40058, 0x1200 }, |
| 3293 | { 0x40078, 0x0 }, | 3293 | { 0x40078, 0x0 }, |
| 3294 | { 0x40019, 0x642 }, | 3294 | { 0x40019, 0x642 }, |
| 3295 | { 0x40039, 0x1a }, | 3295 | { 0x40039, 0x1a }, |
| 3296 | { 0x40059, 0x1300 }, | 3296 | { 0x40059, 0x1300 }, |
| 3297 | { 0x40079, 0x0 }, | 3297 | { 0x40079, 0x0 }, |
| 3298 | { 0x4001a, 0x4808 }, | 3298 | { 0x4001a, 0x4808 }, |
| 3299 | { 0x4003a, 0x880 }, | 3299 | { 0x4003a, 0x880 }, |
| 3300 | { 0x4005a, 0x0 }, | 3300 | { 0x4005a, 0x0 }, |
| 3301 | { 0x4007a, 0x0 }, | 3301 | { 0x4007a, 0x0 }, |
| 3302 | { 0x900a4, 0x0 }, | 3302 | { 0x900a4, 0x0 }, |
| 3303 | { 0x900a5, 0x790 }, | 3303 | { 0x900a5, 0x790 }, |
| 3304 | { 0x900a6, 0x11a }, | 3304 | { 0x900a6, 0x11a }, |
| 3305 | { 0x900a7, 0x8 }, | 3305 | { 0x900a7, 0x8 }, |
| 3306 | { 0x900a8, 0x7aa }, | 3306 | { 0x900a8, 0x7aa }, |
| 3307 | { 0x900a9, 0x2a }, | 3307 | { 0x900a9, 0x2a }, |
| 3308 | { 0x900aa, 0x10 }, | 3308 | { 0x900aa, 0x10 }, |
| 3309 | { 0x900ab, 0x7b2 }, | 3309 | { 0x900ab, 0x7b2 }, |
| 3310 | { 0x900ac, 0x2a }, | 3310 | { 0x900ac, 0x2a }, |
| 3311 | { 0x900ad, 0x0 }, | 3311 | { 0x900ad, 0x0 }, |
| 3312 | { 0x900ae, 0x7c8 }, | 3312 | { 0x900ae, 0x7c8 }, |
| 3313 | { 0x900af, 0x109 }, | 3313 | { 0x900af, 0x109 }, |
| 3314 | { 0x900b0, 0x10 }, | 3314 | { 0x900b0, 0x10 }, |
| 3315 | { 0x900b1, 0x10 }, | 3315 | { 0x900b1, 0x10 }, |
| 3316 | { 0x900b2, 0x109 }, | 3316 | { 0x900b2, 0x109 }, |
| 3317 | { 0x900b3, 0x10 }, | 3317 | { 0x900b3, 0x10 }, |
| 3318 | { 0x900b4, 0x2a8 }, | 3318 | { 0x900b4, 0x2a8 }, |
| 3319 | { 0x900b5, 0x129 }, | 3319 | { 0x900b5, 0x129 }, |
| 3320 | { 0x900b6, 0x8 }, | 3320 | { 0x900b6, 0x8 }, |
| 3321 | { 0x900b7, 0x370 }, | 3321 | { 0x900b7, 0x370 }, |
| 3322 | { 0x900b8, 0x129 }, | 3322 | { 0x900b8, 0x129 }, |
| 3323 | { 0x900b9, 0xa }, | 3323 | { 0x900b9, 0xa }, |
| 3324 | { 0x900ba, 0x3c8 }, | 3324 | { 0x900ba, 0x3c8 }, |
| 3325 | { 0x900bb, 0x1a9 }, | 3325 | { 0x900bb, 0x1a9 }, |
| 3326 | { 0x900bc, 0xc }, | 3326 | { 0x900bc, 0xc }, |
| 3327 | { 0x900bd, 0x408 }, | 3327 | { 0x900bd, 0x408 }, |
| 3328 | { 0x900be, 0x199 }, | 3328 | { 0x900be, 0x199 }, |
| 3329 | { 0x900bf, 0x14 }, | 3329 | { 0x900bf, 0x14 }, |
| 3330 | { 0x900c0, 0x790 }, | 3330 | { 0x900c0, 0x790 }, |
| 3331 | { 0x900c1, 0x11a }, | 3331 | { 0x900c1, 0x11a }, |
| 3332 | { 0x900c2, 0x8 }, | 3332 | { 0x900c2, 0x8 }, |
| 3333 | { 0x900c3, 0x4 }, | 3333 | { 0x900c3, 0x4 }, |
| 3334 | { 0x900c4, 0x18 }, | 3334 | { 0x900c4, 0x18 }, |
| 3335 | { 0x900c5, 0xe }, | 3335 | { 0x900c5, 0xe }, |
| 3336 | { 0x900c6, 0x408 }, | 3336 | { 0x900c6, 0x408 }, |
| 3337 | { 0x900c7, 0x199 }, | 3337 | { 0x900c7, 0x199 }, |
| 3338 | { 0x900c8, 0x8 }, | 3338 | { 0x900c8, 0x8 }, |
| 3339 | { 0x900c9, 0x8568 }, | 3339 | { 0x900c9, 0x8568 }, |
| 3340 | { 0x900ca, 0x108 }, | 3340 | { 0x900ca, 0x108 }, |
| 3341 | { 0x900cb, 0x18 }, | 3341 | { 0x900cb, 0x18 }, |
| 3342 | { 0x900cc, 0x790 }, | 3342 | { 0x900cc, 0x790 }, |
| 3343 | { 0x900cd, 0x16a }, | 3343 | { 0x900cd, 0x16a }, |
| 3344 | { 0x900ce, 0x8 }, | 3344 | { 0x900ce, 0x8 }, |
| 3345 | { 0x900cf, 0x1d8 }, | 3345 | { 0x900cf, 0x1d8 }, |
| 3346 | { 0x900d0, 0x169 }, | 3346 | { 0x900d0, 0x169 }, |
| 3347 | { 0x900d1, 0x10 }, | 3347 | { 0x900d1, 0x10 }, |
| 3348 | { 0x900d2, 0x8558 }, | 3348 | { 0x900d2, 0x8558 }, |
| 3349 | { 0x900d3, 0x168 }, | 3349 | { 0x900d3, 0x168 }, |
| 3350 | { 0x900d4, 0x70 }, | 3350 | { 0x900d4, 0x70 }, |
| 3351 | { 0x900d5, 0x788 }, | 3351 | { 0x900d5, 0x788 }, |
| 3352 | { 0x900d6, 0x16a }, | 3352 | { 0x900d6, 0x16a }, |
| 3353 | { 0x900d7, 0x1ff8 }, | 3353 | { 0x900d7, 0x1ff8 }, |
| 3354 | { 0x900d8, 0x85a8 }, | 3354 | { 0x900d8, 0x85a8 }, |
| 3355 | { 0x900d9, 0x1e8 }, | 3355 | { 0x900d9, 0x1e8 }, |
| 3356 | { 0x900da, 0x50 }, | 3356 | { 0x900da, 0x50 }, |
| 3357 | { 0x900db, 0x798 }, | 3357 | { 0x900db, 0x798 }, |
| 3358 | { 0x900dc, 0x16a }, | 3358 | { 0x900dc, 0x16a }, |
| 3359 | { 0x900dd, 0x60 }, | 3359 | { 0x900dd, 0x60 }, |
| 3360 | { 0x900de, 0x7a0 }, | 3360 | { 0x900de, 0x7a0 }, |
| 3361 | { 0x900df, 0x16a }, | 3361 | { 0x900df, 0x16a }, |
| 3362 | { 0x900e0, 0x8 }, | 3362 | { 0x900e0, 0x8 }, |
| 3363 | { 0x900e1, 0x8310 }, | 3363 | { 0x900e1, 0x8310 }, |
| 3364 | { 0x900e2, 0x168 }, | 3364 | { 0x900e2, 0x168 }, |
| 3365 | { 0x900e3, 0x8 }, | 3365 | { 0x900e3, 0x8 }, |
| 3366 | { 0x900e4, 0xa310 }, | 3366 | { 0x900e4, 0xa310 }, |
| 3367 | { 0x900e5, 0x168 }, | 3367 | { 0x900e5, 0x168 }, |
| 3368 | { 0x900e6, 0xa }, | 3368 | { 0x900e6, 0xa }, |
| 3369 | { 0x900e7, 0x408 }, | 3369 | { 0x900e7, 0x408 }, |
| 3370 | { 0x900e8, 0x169 }, | 3370 | { 0x900e8, 0x169 }, |
| 3371 | { 0x900e9, 0x6e }, | 3371 | { 0x900e9, 0x6e }, |
| 3372 | { 0x900ea, 0x0 }, | 3372 | { 0x900ea, 0x0 }, |
| 3373 | { 0x900eb, 0x68 }, | 3373 | { 0x900eb, 0x68 }, |
| 3374 | { 0x900ec, 0x0 }, | 3374 | { 0x900ec, 0x0 }, |
| 3375 | { 0x900ed, 0x408 }, | 3375 | { 0x900ed, 0x408 }, |
| 3376 | { 0x900ee, 0x169 }, | 3376 | { 0x900ee, 0x169 }, |
| 3377 | { 0x900ef, 0x0 }, | 3377 | { 0x900ef, 0x0 }, |
| 3378 | { 0x900f0, 0x8310 }, | 3378 | { 0x900f0, 0x8310 }, |
| 3379 | { 0x900f1, 0x168 }, | 3379 | { 0x900f1, 0x168 }, |
| 3380 | { 0x900f2, 0x0 }, | 3380 | { 0x900f2, 0x0 }, |
| 3381 | { 0x900f3, 0xa310 }, | 3381 | { 0x900f3, 0xa310 }, |
| 3382 | { 0x900f4, 0x168 }, | 3382 | { 0x900f4, 0x168 }, |
| 3383 | { 0x900f5, 0x1ff8 }, | 3383 | { 0x900f5, 0x1ff8 }, |
| 3384 | { 0x900f6, 0x85a8 }, | 3384 | { 0x900f6, 0x85a8 }, |
| 3385 | { 0x900f7, 0x1e8 }, | 3385 | { 0x900f7, 0x1e8 }, |
| 3386 | { 0x900f8, 0x68 }, | 3386 | { 0x900f8, 0x68 }, |
| 3387 | { 0x900f9, 0x798 }, | 3387 | { 0x900f9, 0x798 }, |
| 3388 | { 0x900fa, 0x16a }, | 3388 | { 0x900fa, 0x16a }, |
| 3389 | { 0x900fb, 0x78 }, | 3389 | { 0x900fb, 0x78 }, |
| 3390 | { 0x900fc, 0x7a0 }, | 3390 | { 0x900fc, 0x7a0 }, |
| 3391 | { 0x900fd, 0x16a }, | 3391 | { 0x900fd, 0x16a }, |
| 3392 | { 0x900fe, 0x68 }, | 3392 | { 0x900fe, 0x68 }, |
| 3393 | { 0x900ff, 0x790 }, | 3393 | { 0x900ff, 0x790 }, |
| 3394 | { 0x90100, 0x16a }, | 3394 | { 0x90100, 0x16a }, |
| 3395 | { 0x90101, 0x8 }, | 3395 | { 0x90101, 0x8 }, |
| 3396 | { 0x90102, 0x8b10 }, | 3396 | { 0x90102, 0x8b10 }, |
| 3397 | { 0x90103, 0x168 }, | 3397 | { 0x90103, 0x168 }, |
| 3398 | { 0x90104, 0x8 }, | 3398 | { 0x90104, 0x8 }, |
| 3399 | { 0x90105, 0xab10 }, | 3399 | { 0x90105, 0xab10 }, |
| 3400 | { 0x90106, 0x168 }, | 3400 | { 0x90106, 0x168 }, |
| 3401 | { 0x90107, 0xa }, | 3401 | { 0x90107, 0xa }, |
| 3402 | { 0x90108, 0x408 }, | 3402 | { 0x90108, 0x408 }, |
| 3403 | { 0x90109, 0x169 }, | 3403 | { 0x90109, 0x169 }, |
| 3404 | { 0x9010a, 0x58 }, | 3404 | { 0x9010a, 0x58 }, |
| 3405 | { 0x9010b, 0x0 }, | 3405 | { 0x9010b, 0x0 }, |
| 3406 | { 0x9010c, 0x68 }, | 3406 | { 0x9010c, 0x68 }, |
| 3407 | { 0x9010d, 0x0 }, | 3407 | { 0x9010d, 0x0 }, |
| 3408 | { 0x9010e, 0x408 }, | 3408 | { 0x9010e, 0x408 }, |
| 3409 | { 0x9010f, 0x169 }, | 3409 | { 0x9010f, 0x169 }, |
| 3410 | { 0x90110, 0x0 }, | 3410 | { 0x90110, 0x0 }, |
| 3411 | { 0x90111, 0x8b10 }, | 3411 | { 0x90111, 0x8b10 }, |
| 3412 | { 0x90112, 0x168 }, | 3412 | { 0x90112, 0x168 }, |
| 3413 | { 0x90113, 0x1 }, | 3413 | { 0x90113, 0x1 }, |
| 3414 | { 0x90114, 0xab10 }, | 3414 | { 0x90114, 0xab10 }, |
| 3415 | { 0x90115, 0x168 }, | 3415 | { 0x90115, 0x168 }, |
| 3416 | { 0x90116, 0x0 }, | 3416 | { 0x90116, 0x0 }, |
| 3417 | { 0x90117, 0x1d8 }, | 3417 | { 0x90117, 0x1d8 }, |
| 3418 | { 0x90118, 0x169 }, | 3418 | { 0x90118, 0x169 }, |
| 3419 | { 0x90119, 0x80 }, | 3419 | { 0x90119, 0x80 }, |
| 3420 | { 0x9011a, 0x790 }, | 3420 | { 0x9011a, 0x790 }, |
| 3421 | { 0x9011b, 0x16a }, | 3421 | { 0x9011b, 0x16a }, |
| 3422 | { 0x9011c, 0x18 }, | 3422 | { 0x9011c, 0x18 }, |
| 3423 | { 0x9011d, 0x7aa }, | 3423 | { 0x9011d, 0x7aa }, |
| 3424 | { 0x9011e, 0x6a }, | 3424 | { 0x9011e, 0x6a }, |
| 3425 | { 0x9011f, 0xa }, | 3425 | { 0x9011f, 0xa }, |
| 3426 | { 0x90120, 0x0 }, | 3426 | { 0x90120, 0x0 }, |
| 3427 | { 0x90121, 0x1e9 }, | 3427 | { 0x90121, 0x1e9 }, |
| 3428 | { 0x90122, 0x8 }, | 3428 | { 0x90122, 0x8 }, |
| 3429 | { 0x90123, 0x8080 }, | 3429 | { 0x90123, 0x8080 }, |
| 3430 | { 0x90124, 0x108 }, | 3430 | { 0x90124, 0x108 }, |
| 3431 | { 0x90125, 0xf }, | 3431 | { 0x90125, 0xf }, |
| 3432 | { 0x90126, 0x408 }, | 3432 | { 0x90126, 0x408 }, |
| 3433 | { 0x90127, 0x169 }, | 3433 | { 0x90127, 0x169 }, |
| 3434 | { 0x90128, 0xc }, | 3434 | { 0x90128, 0xc }, |
| 3435 | { 0x90129, 0x0 }, | 3435 | { 0x90129, 0x0 }, |
| 3436 | { 0x9012a, 0x68 }, | 3436 | { 0x9012a, 0x68 }, |
| 3437 | { 0x9012b, 0x9 }, | 3437 | { 0x9012b, 0x9 }, |
| 3438 | { 0x9012c, 0x0 }, | 3438 | { 0x9012c, 0x0 }, |
| 3439 | { 0x9012d, 0x1a9 }, | 3439 | { 0x9012d, 0x1a9 }, |
| 3440 | { 0x9012e, 0x0 }, | 3440 | { 0x9012e, 0x0 }, |
| 3441 | { 0x9012f, 0x408 }, | 3441 | { 0x9012f, 0x408 }, |
| 3442 | { 0x90130, 0x169 }, | 3442 | { 0x90130, 0x169 }, |
| 3443 | { 0x90131, 0x0 }, | 3443 | { 0x90131, 0x0 }, |
| 3444 | { 0x90132, 0x8080 }, | 3444 | { 0x90132, 0x8080 }, |
| 3445 | { 0x90133, 0x108 }, | 3445 | { 0x90133, 0x108 }, |
| 3446 | { 0x90134, 0x8 }, | 3446 | { 0x90134, 0x8 }, |
| 3447 | { 0x90135, 0x7aa }, | 3447 | { 0x90135, 0x7aa }, |
| 3448 | { 0x90136, 0x6a }, | 3448 | { 0x90136, 0x6a }, |
| 3449 | { 0x90137, 0x0 }, | 3449 | { 0x90137, 0x0 }, |
| 3450 | { 0x90138, 0x8568 }, | 3450 | { 0x90138, 0x8568 }, |
| 3451 | { 0x90139, 0x108 }, | 3451 | { 0x90139, 0x108 }, |
| 3452 | { 0x9013a, 0xb7 }, | 3452 | { 0x9013a, 0xb7 }, |
| 3453 | { 0x9013b, 0x790 }, | 3453 | { 0x9013b, 0x790 }, |
| 3454 | { 0x9013c, 0x16a }, | 3454 | { 0x9013c, 0x16a }, |
| 3455 | { 0x9013d, 0x1f }, | 3455 | { 0x9013d, 0x1f }, |
| 3456 | { 0x9013e, 0x0 }, | 3456 | { 0x9013e, 0x0 }, |
| 3457 | { 0x9013f, 0x68 }, | 3457 | { 0x9013f, 0x68 }, |
| 3458 | { 0x90140, 0x8 }, | 3458 | { 0x90140, 0x8 }, |
| 3459 | { 0x90141, 0x8558 }, | 3459 | { 0x90141, 0x8558 }, |
| 3460 | { 0x90142, 0x168 }, | 3460 | { 0x90142, 0x168 }, |
| 3461 | { 0x90143, 0xf }, | 3461 | { 0x90143, 0xf }, |
| 3462 | { 0x90144, 0x408 }, | 3462 | { 0x90144, 0x408 }, |
| 3463 | { 0x90145, 0x169 }, | 3463 | { 0x90145, 0x169 }, |
| 3464 | { 0x90146, 0xd }, | 3464 | { 0x90146, 0xd }, |
| 3465 | { 0x90147, 0x0 }, | 3465 | { 0x90147, 0x0 }, |
| 3466 | { 0x90148, 0x68 }, | 3466 | { 0x90148, 0x68 }, |
| 3467 | { 0x90149, 0x0 }, | 3467 | { 0x90149, 0x0 }, |
| 3468 | { 0x9014a, 0x408 }, | 3468 | { 0x9014a, 0x408 }, |
| 3469 | { 0x9014b, 0x169 }, | 3469 | { 0x9014b, 0x169 }, |
| 3470 | { 0x9014c, 0x0 }, | 3470 | { 0x9014c, 0x0 }, |
| 3471 | { 0x9014d, 0x8558 }, | 3471 | { 0x9014d, 0x8558 }, |
| 3472 | { 0x9014e, 0x168 }, | 3472 | { 0x9014e, 0x168 }, |
| 3473 | { 0x9014f, 0x8 }, | 3473 | { 0x9014f, 0x8 }, |
| 3474 | { 0x90150, 0x3c8 }, | 3474 | { 0x90150, 0x3c8 }, |
| 3475 | { 0x90151, 0x1a9 }, | 3475 | { 0x90151, 0x1a9 }, |
| 3476 | { 0x90152, 0x3 }, | 3476 | { 0x90152, 0x3 }, |
| 3477 | { 0x90153, 0x370 }, | 3477 | { 0x90153, 0x370 }, |
| 3478 | { 0x90154, 0x129 }, | 3478 | { 0x90154, 0x129 }, |
| 3479 | { 0x90155, 0x20 }, | 3479 | { 0x90155, 0x20 }, |
| 3480 | { 0x90156, 0x2aa }, | 3480 | { 0x90156, 0x2aa }, |
| 3481 | { 0x90157, 0x9 }, | 3481 | { 0x90157, 0x9 }, |
| 3482 | { 0x90158, 0x8 }, | 3482 | { 0x90158, 0x8 }, |
| 3483 | { 0x90159, 0xe8 }, | 3483 | { 0x90159, 0xe8 }, |
| 3484 | { 0x9015a, 0x109 }, | 3484 | { 0x9015a, 0x109 }, |
| 3485 | { 0x9015b, 0x0 }, | 3485 | { 0x9015b, 0x0 }, |
| 3486 | { 0x9015c, 0x8140 }, | 3486 | { 0x9015c, 0x8140 }, |
| 3487 | { 0x9015d, 0x10c }, | 3487 | { 0x9015d, 0x10c }, |
| 3488 | { 0x9015e, 0x10 }, | 3488 | { 0x9015e, 0x10 }, |
| 3489 | { 0x9015f, 0x8138 }, | 3489 | { 0x9015f, 0x8138 }, |
| 3490 | { 0x90160, 0x104 }, | 3490 | { 0x90160, 0x104 }, |
| 3491 | { 0x90161, 0x8 }, | 3491 | { 0x90161, 0x8 }, |
| 3492 | { 0x90162, 0x448 }, | 3492 | { 0x90162, 0x448 }, |
| 3493 | { 0x90163, 0x109 }, | 3493 | { 0x90163, 0x109 }, |
| 3494 | { 0x90164, 0xf }, | 3494 | { 0x90164, 0xf }, |
| 3495 | { 0x90165, 0x7c0 }, | 3495 | { 0x90165, 0x7c0 }, |
| 3496 | { 0x90166, 0x109 }, | 3496 | { 0x90166, 0x109 }, |
| 3497 | { 0x90167, 0x0 }, | 3497 | { 0x90167, 0x0 }, |
| 3498 | { 0x90168, 0xe8 }, | 3498 | { 0x90168, 0xe8 }, |
| 3499 | { 0x90169, 0x109 }, | 3499 | { 0x90169, 0x109 }, |
| 3500 | { 0x9016a, 0x47 }, | 3500 | { 0x9016a, 0x47 }, |
| 3501 | { 0x9016b, 0x630 }, | 3501 | { 0x9016b, 0x630 }, |
| 3502 | { 0x9016c, 0x109 }, | 3502 | { 0x9016c, 0x109 }, |
| 3503 | { 0x9016d, 0x8 }, | 3503 | { 0x9016d, 0x8 }, |
| 3504 | { 0x9016e, 0x618 }, | 3504 | { 0x9016e, 0x618 }, |
| 3505 | { 0x9016f, 0x109 }, | 3505 | { 0x9016f, 0x109 }, |
| 3506 | { 0x90170, 0x8 }, | 3506 | { 0x90170, 0x8 }, |
| 3507 | { 0x90171, 0xe0 }, | 3507 | { 0x90171, 0xe0 }, |
| 3508 | { 0x90172, 0x109 }, | 3508 | { 0x90172, 0x109 }, |
| 3509 | { 0x90173, 0x0 }, | 3509 | { 0x90173, 0x0 }, |
| 3510 | { 0x90174, 0x7c8 }, | 3510 | { 0x90174, 0x7c8 }, |
| 3511 | { 0x90175, 0x109 }, | 3511 | { 0x90175, 0x109 }, |
| 3512 | { 0x90176, 0x8 }, | 3512 | { 0x90176, 0x8 }, |
| 3513 | { 0x90177, 0x8140 }, | 3513 | { 0x90177, 0x8140 }, |
| 3514 | { 0x90178, 0x10c }, | 3514 | { 0x90178, 0x10c }, |
| 3515 | { 0x90179, 0x0 }, | 3515 | { 0x90179, 0x0 }, |
| 3516 | { 0x9017a, 0x478 }, | 3516 | { 0x9017a, 0x478 }, |
| 3517 | { 0x9017b, 0x109 }, | 3517 | { 0x9017b, 0x109 }, |
| 3518 | { 0x9017c, 0x0 }, | 3518 | { 0x9017c, 0x0 }, |
| 3519 | { 0x9017d, 0x1 }, | 3519 | { 0x9017d, 0x1 }, |
| 3520 | { 0x9017e, 0x8 }, | 3520 | { 0x9017e, 0x8 }, |
| 3521 | { 0x9017f, 0x8 }, | 3521 | { 0x9017f, 0x8 }, |
| 3522 | { 0x90180, 0x4 }, | 3522 | { 0x90180, 0x4 }, |
| 3523 | { 0x90181, 0x0 }, | 3523 | { 0x90181, 0x0 }, |
| 3524 | { 0x90006, 0x8 }, | 3524 | { 0x90006, 0x8 }, |
| 3525 | { 0x90007, 0x7c8 }, | 3525 | { 0x90007, 0x7c8 }, |
| 3526 | { 0x90008, 0x109 }, | 3526 | { 0x90008, 0x109 }, |
| 3527 | { 0x90009, 0x0 }, | 3527 | { 0x90009, 0x0 }, |
| 3528 | { 0x9000a, 0x400 }, | 3528 | { 0x9000a, 0x400 }, |
| 3529 | { 0x9000b, 0x106 }, | 3529 | { 0x9000b, 0x106 }, |
| 3530 | { 0xd00e7, 0x400 }, | 3530 | { 0xd00e7, 0x400 }, |
| 3531 | { 0x90017, 0x0 }, | 3531 | { 0x90017, 0x0 }, |
| 3532 | { 0x9001f, 0x29 }, | 3532 | { 0x9001f, 0x29 }, |
| 3533 | { 0x90026, 0x68 }, | 3533 | { 0x90026, 0x68 }, |
| 3534 | { 0x400d0, 0x0 }, | 3534 | { 0x400d0, 0x0 }, |
| 3535 | { 0x400d1, 0x101 }, | 3535 | { 0x400d1, 0x101 }, |
| 3536 | { 0x400d2, 0x105 }, | 3536 | { 0x400d2, 0x105 }, |
| 3537 | { 0x400d3, 0x107 }, | 3537 | { 0x400d3, 0x107 }, |
| 3538 | { 0x400d4, 0x10f }, | 3538 | { 0x400d4, 0x10f }, |
| 3539 | { 0x400d5, 0x202 }, | 3539 | { 0x400d5, 0x202 }, |
| 3540 | { 0x400d6, 0x20a }, | 3540 | { 0x400d6, 0x20a }, |
| 3541 | { 0x400d7, 0x20b }, | 3541 | { 0x400d7, 0x20b }, |
| 3542 | { 0x2003a, 0x2 }, | 3542 | { 0x2003a, 0x2 }, |
| 3543 | { 0x200be, 0x3 }, | 3543 | { 0x200be, 0x3 }, |
| 3544 | { 0x2000b, 0x7d }, | 3544 | { 0x2000b, 0x7d }, |
| 3545 | { 0x2000c, 0xfa }, | 3545 | { 0x2000c, 0xfa }, |
| 3546 | { 0x2000d, 0x9c4 }, | 3546 | { 0x2000d, 0x9c4 }, |
| 3547 | { 0x2000e, 0x2c }, | 3547 | { 0x2000e, 0x2c }, |
| 3548 | { 0x12000b, 0xc }, | 3548 | { 0x12000b, 0xc }, |
| 3549 | { 0x12000c, 0x19 }, | 3549 | { 0x12000c, 0x19 }, |
| 3550 | { 0x12000d, 0xfa }, | 3550 | { 0x12000d, 0xfa }, |
| 3551 | { 0x12000e, 0x10 }, | 3551 | { 0x12000e, 0x10 }, |
| 3552 | { 0x22000b, 0x3 }, | 3552 | { 0x22000b, 0x3 }, |
| 3553 | { 0x22000c, 0x6 }, | 3553 | { 0x22000c, 0x6 }, |
| 3554 | { 0x22000d, 0x3e }, | 3554 | { 0x22000d, 0x3e }, |
| 3555 | { 0x22000e, 0x10 }, | 3555 | { 0x22000e, 0x10 }, |
| 3556 | { 0x9000c, 0x0 }, | 3556 | { 0x9000c, 0x0 }, |
| 3557 | { 0x9000d, 0x173 }, | 3557 | { 0x9000d, 0x173 }, |
| 3558 | { 0x9000e, 0x60 }, | 3558 | { 0x9000e, 0x60 }, |
| 3559 | { 0x9000f, 0x6110 }, | 3559 | { 0x9000f, 0x6110 }, |
| 3560 | { 0x90010, 0x2152 }, | 3560 | { 0x90010, 0x2152 }, |
| 3561 | { 0x90011, 0xdfbd }, | 3561 | { 0x90011, 0xdfbd }, |
| 3562 | { 0x90012, 0x2060 }, | 3562 | { 0x90012, 0x2060 }, |
| 3563 | { 0x90013, 0x6152 }, | 3563 | { 0x90013, 0x6152 }, |
| 3564 | { 0x20010, 0x5a }, | 3564 | { 0x20010, 0x5a }, |
| 3565 | { 0x20011, 0x3 }, | 3565 | { 0x20011, 0x3 }, |
| 3566 | { 0x40080, 0xe0 }, | 3566 | { 0x40080, 0xe0 }, |
| 3567 | { 0x40081, 0x12 }, | 3567 | { 0x40081, 0x12 }, |
| 3568 | { 0x40082, 0xe0 }, | 3568 | { 0x40082, 0xe0 }, |
| 3569 | { 0x40083, 0x12 }, | 3569 | { 0x40083, 0x12 }, |
| 3570 | { 0x40084, 0xe0 }, | 3570 | { 0x40084, 0xe0 }, |
| 3571 | { 0x40085, 0x12 }, | 3571 | { 0x40085, 0x12 }, |
| 3572 | { 0x140080, 0xe0 }, | 3572 | { 0x140080, 0xe0 }, |
| 3573 | { 0x140081, 0x12 }, | 3573 | { 0x140081, 0x12 }, |
| 3574 | { 0x140082, 0xe0 }, | 3574 | { 0x140082, 0xe0 }, |
| 3575 | { 0x140083, 0x12 }, | 3575 | { 0x140083, 0x12 }, |
| 3576 | { 0x140084, 0xe0 }, | 3576 | { 0x140084, 0xe0 }, |
| 3577 | { 0x140085, 0x12 }, | 3577 | { 0x140085, 0x12 }, |
| 3578 | { 0x240080, 0xe0 }, | 3578 | { 0x240080, 0xe0 }, |
| 3579 | { 0x240081, 0x12 }, | 3579 | { 0x240081, 0x12 }, |
| 3580 | { 0x240082, 0xe0 }, | 3580 | { 0x240082, 0xe0 }, |
| 3581 | { 0x240083, 0x12 }, | 3581 | { 0x240083, 0x12 }, |
| 3582 | { 0x240084, 0xe0 }, | 3582 | { 0x240084, 0xe0 }, |
| 3583 | { 0x240085, 0x12 }, | 3583 | { 0x240085, 0x12 }, |
| 3584 | { 0x400fd, 0xf }, | 3584 | { 0x400fd, 0xf }, |
| 3585 | { 0x10011, 0x1 }, | 3585 | { 0x10011, 0x1 }, |
| 3586 | { 0x10012, 0x1 }, | 3586 | { 0x10012, 0x1 }, |
| 3587 | { 0x10013, 0x180 }, | 3587 | { 0x10013, 0x180 }, |
| 3588 | { 0x10018, 0x1 }, | 3588 | { 0x10018, 0x1 }, |
| 3589 | { 0x10002, 0x6209 }, | 3589 | { 0x10002, 0x6209 }, |
| 3590 | { 0x100b2, 0x1 }, | 3590 | { 0x100b2, 0x1 }, |
| 3591 | { 0x101b4, 0x1 }, | 3591 | { 0x101b4, 0x1 }, |
| 3592 | { 0x102b4, 0x1 }, | 3592 | { 0x102b4, 0x1 }, |
| 3593 | { 0x103b4, 0x1 }, | 3593 | { 0x103b4, 0x1 }, |
| 3594 | { 0x104b4, 0x1 }, | 3594 | { 0x104b4, 0x1 }, |
| 3595 | { 0x105b4, 0x1 }, | 3595 | { 0x105b4, 0x1 }, |
| 3596 | { 0x106b4, 0x1 }, | 3596 | { 0x106b4, 0x1 }, |
| 3597 | { 0x107b4, 0x1 }, | 3597 | { 0x107b4, 0x1 }, |
| 3598 | { 0x108b4, 0x1 }, | 3598 | { 0x108b4, 0x1 }, |
| 3599 | { 0x11011, 0x1 }, | 3599 | { 0x11011, 0x1 }, |
| 3600 | { 0x11012, 0x1 }, | 3600 | { 0x11012, 0x1 }, |
| 3601 | { 0x11013, 0x180 }, | 3601 | { 0x11013, 0x180 }, |
| 3602 | { 0x11018, 0x1 }, | 3602 | { 0x11018, 0x1 }, |
| 3603 | { 0x11002, 0x6209 }, | 3603 | { 0x11002, 0x6209 }, |
| 3604 | { 0x110b2, 0x1 }, | 3604 | { 0x110b2, 0x1 }, |
| 3605 | { 0x111b4, 0x1 }, | 3605 | { 0x111b4, 0x1 }, |
| 3606 | { 0x112b4, 0x1 }, | 3606 | { 0x112b4, 0x1 }, |
| 3607 | { 0x113b4, 0x1 }, | 3607 | { 0x113b4, 0x1 }, |
| 3608 | { 0x114b4, 0x1 }, | 3608 | { 0x114b4, 0x1 }, |
| 3609 | { 0x115b4, 0x1 }, | 3609 | { 0x115b4, 0x1 }, |
| 3610 | { 0x116b4, 0x1 }, | 3610 | { 0x116b4, 0x1 }, |
| 3611 | { 0x117b4, 0x1 }, | 3611 | { 0x117b4, 0x1 }, |
| 3612 | { 0x118b4, 0x1 }, | 3612 | { 0x118b4, 0x1 }, |
| 3613 | { 0x12011, 0x1 }, | 3613 | { 0x12011, 0x1 }, |
| 3614 | { 0x12012, 0x1 }, | 3614 | { 0x12012, 0x1 }, |
| 3615 | { 0x12013, 0x180 }, | 3615 | { 0x12013, 0x180 }, |
| 3616 | { 0x12018, 0x1 }, | 3616 | { 0x12018, 0x1 }, |
| 3617 | { 0x12002, 0x6209 }, | 3617 | { 0x12002, 0x6209 }, |
| 3618 | { 0x120b2, 0x1 }, | 3618 | { 0x120b2, 0x1 }, |
| 3619 | { 0x121b4, 0x1 }, | 3619 | { 0x121b4, 0x1 }, |
| 3620 | { 0x122b4, 0x1 }, | 3620 | { 0x122b4, 0x1 }, |
| 3621 | { 0x123b4, 0x1 }, | 3621 | { 0x123b4, 0x1 }, |
| 3622 | { 0x124b4, 0x1 }, | 3622 | { 0x124b4, 0x1 }, |
| 3623 | { 0x125b4, 0x1 }, | 3623 | { 0x125b4, 0x1 }, |
| 3624 | { 0x126b4, 0x1 }, | 3624 | { 0x126b4, 0x1 }, |
| 3625 | { 0x127b4, 0x1 }, | 3625 | { 0x127b4, 0x1 }, |
| 3626 | { 0x128b4, 0x1 }, | 3626 | { 0x128b4, 0x1 }, |
| 3627 | { 0x13011, 0x1 }, | 3627 | { 0x13011, 0x1 }, |
| 3628 | { 0x13012, 0x1 }, | 3628 | { 0x13012, 0x1 }, |
| 3629 | { 0x13013, 0x180 }, | 3629 | { 0x13013, 0x180 }, |
| 3630 | { 0x13018, 0x1 }, | 3630 | { 0x13018, 0x1 }, |
| 3631 | { 0x13002, 0x6209 }, | 3631 | { 0x13002, 0x6209 }, |
| 3632 | { 0x130b2, 0x1 }, | 3632 | { 0x130b2, 0x1 }, |
| 3633 | { 0x131b4, 0x1 }, | 3633 | { 0x131b4, 0x1 }, |
| 3634 | { 0x132b4, 0x1 }, | 3634 | { 0x132b4, 0x1 }, |
| 3635 | { 0x133b4, 0x1 }, | 3635 | { 0x133b4, 0x1 }, |
| 3636 | { 0x134b4, 0x1 }, | 3636 | { 0x134b4, 0x1 }, |
| 3637 | { 0x135b4, 0x1 }, | 3637 | { 0x135b4, 0x1 }, |
| 3638 | { 0x136b4, 0x1 }, | 3638 | { 0x136b4, 0x1 }, |
| 3639 | { 0x137b4, 0x1 }, | 3639 | { 0x137b4, 0x1 }, |
| 3640 | { 0x138b4, 0x1 }, | 3640 | { 0x138b4, 0x1 }, |
| 3641 | { 0x20089, 0x1 }, | 3641 | { 0x20089, 0x1 }, |
| 3642 | { 0x20088, 0x19 }, | 3642 | { 0x20088, 0x19 }, |
| 3643 | { 0xc0080, 0x2 }, | 3643 | { 0xc0080, 0x2 }, |
| 3644 | { 0xd0000, 0x1 } | 3644 | { 0xd0000, 0x1 } |
| 3645 | }; | 3645 | }; |
| 3646 | 3646 | ||
| 3647 | struct dram_fsp_msg ddr_dram_fsp_msg[] = { | 3647 | struct dram_fsp_msg ddr_dram_fsp_msg[] = { |
| 3648 | { | 3648 | { |
| 3649 | /* P0 4000mts 1D */ | 3649 | /* P0 4000mts 1D */ |
| 3650 | .drate = 4000, | 3650 | .drate = 4000, |
| 3651 | .fw_type = FW_1D_IMAGE, | 3651 | .fw_type = FW_1D_IMAGE, |
| 3652 | .fsp_cfg = ddr_fsp0_cfg, | 3652 | .fsp_cfg = ddr_fsp0_cfg, |
| 3653 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), | 3653 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), |
| 3654 | }, | 3654 | }, |
| 3655 | { | 3655 | { |
| 3656 | /* P1 400mts 1D */ | 3656 | /* P1 400mts 1D */ |
| 3657 | .drate = 400, | 3657 | .drate = 400, |
| 3658 | .fw_type = FW_1D_IMAGE, | 3658 | .fw_type = FW_1D_IMAGE, |
| 3659 | .fsp_cfg = ddr_fsp1_cfg, | 3659 | .fsp_cfg = ddr_fsp1_cfg, |
| 3660 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), | 3660 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), |
| 3661 | }, | 3661 | }, |
| 3662 | { | 3662 | { |
| 3663 | /* P2 100mts 1D */ | 3663 | /* P2 100mts 1D */ |
| 3664 | .drate = 100, | 3664 | .drate = 100, |
| 3665 | .fw_type = FW_1D_IMAGE, | 3665 | .fw_type = FW_1D_IMAGE, |
| 3666 | .fsp_cfg = ddr_fsp2_cfg, | 3666 | .fsp_cfg = ddr_fsp2_cfg, |
| 3667 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), | 3667 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), |
| 3668 | }, | 3668 | }, |
| 3669 | { | 3669 | { |
| 3670 | /* P0 4000mts 2D */ | 3670 | /* P0 4000mts 2D */ |
| 3671 | .drate = 4000, | 3671 | .drate = 4000, |
| 3672 | .fw_type = FW_2D_IMAGE, | 3672 | .fw_type = FW_2D_IMAGE, |
| 3673 | .fsp_cfg = ddr_fsp0_2d_cfg, | 3673 | .fsp_cfg = ddr_fsp0_2d_cfg, |
| 3674 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), | 3674 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), |
| 3675 | }, | 3675 | }, |
| 3676 | }; | 3676 | }; |
| 3677 | 3677 | ||
| 3678 | /* ddr timing config params */ | 3678 | /* ddr timing config params */ |
| 3679 | struct dram_timing_info dram_timing = { | 3679 | struct dram_timing_info dram_timing = { |
| 3680 | .ddrc_cfg = ddr_ddrc_cfg, | 3680 | .ddrc_cfg = ddr_ddrc_cfg, |
| 3681 | .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), | 3681 | .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), |
| 3682 | .ddrphy_cfg = ddr_ddrphy_cfg, | 3682 | .ddrphy_cfg = ddr_ddrphy_cfg, |
| 3683 | .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), | 3683 | .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), |
| 3684 | .fsp_msg = ddr_dram_fsp_msg, | 3684 | .fsp_msg = ddr_dram_fsp_msg, |
| 3685 | .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), | 3685 | .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), |
| 3686 | .ddrphy_trained_csr = ddr_ddrphy_trained_csr, | 3686 | .ddrphy_trained_csr = ddr_ddrphy_trained_csr, |
| 3687 | .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), | 3687 | .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), |
| 3688 | .ddrphy_pie = ddr_phy_pie, | 3688 | .ddrphy_pie = ddr_phy_pie, |
| 3689 | .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), | 3689 | .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), |
| 3690 | .fsp_table = { 4000, 400, 100, }, | 3690 | .fsp_table = { 4000, 400, 100, }, |
| 3691 | }; | 3691 | }; |
| 3692 | #else | 3692 | #else |
| 3693 | #error "no configuration for this board" | 3693 | #error "no configuration for this board" |
| 3694 | #endif | 3694 | #endif |
| 3695 | 3695 |
board/embedian/smarcimx8mp/smarcimx8mp.c
| 1 | // SPDX-License-Identifier: GPL-2.0+ | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* | 2 | /* |
| 3 | * Copyright 2019 NXP | 3 | * Copyright 2019 NXP |
| 4 | */ | 4 | */ |
| 5 | 5 | ||
| 6 | #include <common.h> | 6 | #include <common.h> |
| 7 | #include <errno.h> | 7 | #include <errno.h> |
| 8 | #include <hang.h> | 8 | #include <hang.h> |
| 9 | #include <miiphy.h> | 9 | #include <miiphy.h> |
| 10 | #include <netdev.h> | 10 | #include <netdev.h> |
| 11 | #include <asm/io.h> | 11 | #include <asm/io.h> |
| 12 | #include <asm/mach-imx/iomux-v3.h> | 12 | #include <asm/mach-imx/iomux-v3.h> |
| 13 | #include <asm-generic/gpio.h> | 13 | #include <asm-generic/gpio.h> |
| 14 | #include <asm/arch/imx8mp_pins.h> | 14 | #include <asm/arch/imx8mp_pins.h> |
| 15 | #include <asm/arch/sys_proto.h> | 15 | #include <asm/arch/sys_proto.h> |
| 16 | #include <asm/mach-imx/gpio.h> | 16 | #include <asm/mach-imx/gpio.h> |
| 17 | #include <asm/mach-imx/mxc_i2c.h> | 17 | #include <asm/mach-imx/mxc_i2c.h> |
| 18 | #include <asm/arch/clock.h> | 18 | #include <asm/arch/clock.h> |
| 19 | #include <spl.h> | 19 | #include <spl.h> |
| 20 | #include <asm/mach-imx/dma.h> | 20 | #include <asm/mach-imx/dma.h> |
| 21 | #include <power/pmic.h> | 21 | #include <power/pmic.h> |
| 22 | #include "../../freescale/common/tcpc.h" | 22 | #include "../../freescale/common/tcpc.h" |
| 23 | #include <usb.h> | 23 | #include <usb.h> |
| 24 | #include <dwc3-uboot.h> | 24 | #include <dwc3-uboot.h> |
| 25 | #include <mmc.h> | 25 | #include <mmc.h> |
| 26 | 26 | ||
| 27 | DECLARE_GLOBAL_DATA_PTR; | 27 | DECLARE_GLOBAL_DATA_PTR; |
| 28 | 28 | ||
| 29 | #define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) | 29 | #define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) |
| 30 | #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) | 30 | #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) |
| 31 | #define WEAK_PULLUP (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) | 31 | #define WEAK_PULLUP (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) |
| 32 | #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) | 32 | #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) |
| 33 | #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) | 33 | #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) |
| 34 | 34 | ||
| 35 | #ifdef CONFIG_CONSOLE_SER0 | 35 | #ifdef CONFIG_CONSOLE_SER0 |
| 36 | static iomux_v3_cfg_t const uart1_pads[] = { | 36 | static iomux_v3_cfg_t const uart1_pads[] = { |
| 37 | MX8MP_PAD_SD1_CMD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | 37 | MX8MP_PAD_SD1_CMD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 38 | MX8MP_PAD_SD1_CLK__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | 38 | MX8MP_PAD_SD1_CLK__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 39 | }; | 39 | }; |
| 40 | #endif | 40 | #endif |
| 41 | 41 | ||
| 42 | #ifdef CONFIG_CONSOLE_SER1 | 42 | #ifdef CONFIG_CONSOLE_SER1 |
| 43 | static iomux_v3_cfg_t const uart4_pads[] = { | 43 | static iomux_v3_cfg_t const uart4_pads[] = { |
| 44 | MX8MP_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | 44 | MX8MP_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 45 | MX8MP_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | 45 | MX8MP_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 46 | }; | 46 | }; |
| 47 | #endif | 47 | #endif |
| 48 | 48 | ||
| 49 | #ifdef CONFIG_CONSOLE_SER2 | 49 | #ifdef CONFIG_CONSOLE_SER2 |
| 50 | static iomux_v3_cfg_t const uart3_pads[] = { | 50 | static iomux_v3_cfg_t const uart3_pads[] = { |
| 51 | MX8MP_PAD_SD1_DATA7__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | 51 | MX8MP_PAD_SD1_DATA7__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 52 | MX8MP_PAD_SD1_DATA6__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | 52 | MX8MP_PAD_SD1_DATA6__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 53 | }; | 53 | }; |
| 54 | #endif | 54 | #endif |
| 55 | 55 | ||
| 56 | #ifdef CONFIG_CONSOLE_SER3 | 56 | #ifdef CONFIG_CONSOLE_SER3 |
| 57 | static iomux_v3_cfg_t const uart2_pads[] = { | 57 | static iomux_v3_cfg_t const uart2_pads[] = { |
| 58 | MX8MP_PAD_SD1_DATA3__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | 58 | MX8MP_PAD_SD1_DATA3__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 59 | MX8MP_PAD_SD1_DATA2__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | 59 | MX8MP_PAD_SD1_DATA2__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 60 | }; | 60 | }; |
| 61 | #endif | 61 | #endif |
| 62 | 62 | ||
| 63 | static iomux_v3_cfg_t const wdog_pads[] = { | 63 | static iomux_v3_cfg_t const wdog_pads[] = { |
| 64 | MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), | 64 | MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), |
| 65 | }; | 65 | }; |
| 66 | 66 | ||
| 67 | /* MISC PINs */ | 67 | /* MISC PINs */ |
| 68 | static iomux_v3_cfg_t const misc_pads[] = { | 68 | static iomux_v3_cfg_t const misc_pads[] = { |
| 69 | MX8MP_PAD_SD1_DATA5__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /*S146, PCIE_WAKE */ | 69 | MX8MP_PAD_SD1_DATA5__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /*S146, PCIE_WAKE */ |
| 70 | MX8MP_PAD_I2C4_SCL__PCIE_CLKREQ_B | MUX_PAD_CTRL(WEAK_PULLUP), /*P78, PCIE_A_CKREQ# */ | 70 | MX8MP_PAD_I2C4_SCL__PCIE_CLKREQ_B | MUX_PAD_CTRL(WEAK_PULLUP), /*P78, PCIE_A_CKREQ# */ |
| 71 | MX8MP_PAD_GPIO1_IO05__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), | 71 | MX8MP_PAD_GPIO1_IO05__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), |
| 72 | /*P123, BOOT_SEL0# */ | 72 | /*P123, BOOT_SEL0# */ |
| 73 | MX8MP_PAD_GPIO1_IO06__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), | 73 | MX8MP_PAD_GPIO1_IO06__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), |
| 74 | /*P124, BOOT_SEL1# */ | 74 | /*P124, BOOT_SEL1# */ |
| 75 | MX8MP_PAD_GPIO1_IO07__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /*P125, BOOT_SEL2# */ | 75 | MX8MP_PAD_GPIO1_IO07__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /*P125, BOOT_SEL2# */ |
| 76 | }; | 76 | }; |
| 77 | 77 | ||
| 78 | static void setup_iomux_misc(void) | 78 | static void setup_iomux_misc(void) |
| 79 | { | 79 | { |
| 80 | imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); | 80 | imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); |
| 81 | 81 | ||
| 82 | /* Set PCIE_WAKE# as Input */ | 82 | /* Set PCIE_WAKE# as Input */ |
| 83 | gpio_request(IMX_GPIO_NR(2, 7), "PCIE_WAKE#"); | 83 | gpio_request(IMX_GPIO_NR(2, 7), "PCIE_WAKE#"); |
| 84 | gpio_direction_input(IMX_GPIO_NR(2, 7)); | 84 | gpio_direction_input(IMX_GPIO_NR(2, 7)); |
| 85 | /* Set BOOT_SEL0# as Input */ | 85 | /* Set BOOT_SEL0# as Input */ |
| 86 | gpio_request(IMX_GPIO_NR(1, 5), "BOOT_SEL0#"); | 86 | gpio_request(IMX_GPIO_NR(1, 5), "BOOT_SEL0#"); |
| 87 | gpio_direction_input(IMX_GPIO_NR(1, 5)); | 87 | gpio_direction_input(IMX_GPIO_NR(1, 5)); |
| 88 | /* Set BOOT_SEL1# as Input */ | 88 | /* Set BOOT_SEL1# as Input */ |
| 89 | gpio_request(IMX_GPIO_NR(1, 6), "BOOT_SEL1#"); | 89 | gpio_request(IMX_GPIO_NR(1, 6), "BOOT_SEL1#"); |
| 90 | gpio_direction_input(IMX_GPIO_NR(1, 6)); | 90 | gpio_direction_input(IMX_GPIO_NR(1, 6)); |
| 91 | /* Set BOOT_SEL2# as Input */ | 91 | /* Set BOOT_SEL2# as Input */ |
| 92 | gpio_request(IMX_GPIO_NR(1, 7), "BOOT_SEL2#"); | 92 | gpio_request(IMX_GPIO_NR(1, 7), "BOOT_SEL2#"); |
| 93 | gpio_direction_input(IMX_GPIO_NR(1, 7)); | 93 | gpio_direction_input(IMX_GPIO_NR(1, 7)); |
| 94 | } | 94 | } |
| 95 | 95 | ||
| 96 | /* GPIO PINs, By SMARC specification, GPIO0~GPIO5 are recommended set as Output Low by default and GPIO6~GPIO11 are recommended set as Input*/ | 96 | /* GPIO PINs, By SMARC specification, GPIO0~GPIO5 are recommended set as Output Low by default and GPIO6~GPIO11 are recommended set as Input*/ |
| 97 | static iomux_v3_cfg_t const gpio_pads[] = { | 97 | static iomux_v3_cfg_t const gpio_pads[] = { |
| 98 | MX8MP_PAD_NAND_DATA00__GPIO3_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), /*P108, GPIO0*/ | 98 | MX8MP_PAD_NAND_DATA00__GPIO3_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), /*P108, GPIO0*/ |
| 99 | MX8MP_PAD_NAND_DATA01__GPIO3_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /*P109, GPIO1*/ | 99 | MX8MP_PAD_NAND_DATA01__GPIO3_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /*P109, GPIO1*/ |
| 100 | MX8MP_PAD_NAND_DATA02__GPIO3_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), /*P110, GPIO2*/ | 100 | MX8MP_PAD_NAND_DATA02__GPIO3_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), /*P110, GPIO2*/ |
| 101 | MX8MP_PAD_NAND_DATA03__GPIO3_IO09 | MUX_PAD_CTRL(WEAK_PULLUP), /*P111, GPIO3*/ | 101 | MX8MP_PAD_NAND_DATA03__GPIO3_IO09 | MUX_PAD_CTRL(WEAK_PULLUP), /*P111, GPIO3*/ |
| 102 | MX8MP_PAD_GPIO1_IO15__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), /*P112, GPIO4*/ | 102 | MX8MP_PAD_GPIO1_IO15__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), /*P112, GPIO4*/ |
| 103 | MX8MP_PAD_I2C4_SDA__GPIO5_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), /*P113, GPIO5*/ | 103 | MX8MP_PAD_I2C4_SDA__GPIO5_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), /*P113, GPIO5*/ |
| 104 | MX8MP_PAD_SAI3_TXC__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), /*P114, GPIO6*/ | 104 | MX8MP_PAD_SAI3_TXC__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), /*P114, GPIO6*/ |
| 105 | MX8MP_PAD_SAI3_TXD__GPIO5_IO01 | MUX_PAD_CTRL(WEAK_PULLUP), /*P115, GPIO7*/ | 105 | MX8MP_PAD_SAI3_TXD__GPIO5_IO01 | MUX_PAD_CTRL(WEAK_PULLUP), /*P115, GPIO7*/ |
| 106 | MX8MP_PAD_SAI3_RXC__GPIO4_IO29 | MUX_PAD_CTRL(WEAK_PULLUP), /*P116, GPIO8*/ | 106 | MX8MP_PAD_SAI3_RXC__GPIO4_IO29 | MUX_PAD_CTRL(WEAK_PULLUP), /*P116, GPIO8*/ |
| 107 | MX8MP_PAD_SPDIF_TX__GPIO5_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), /*P114, GPIO9*/ | 107 | MX8MP_PAD_SPDIF_TX__GPIO5_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), /*P114, GPIO9*/ |
| 108 | MX8MP_PAD_SPDIF_RX__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), /*P115, GPIO10*/ | 108 | MX8MP_PAD_SPDIF_RX__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), /*P115, GPIO10*/ |
| 109 | MX8MP_PAD_SPDIF_EXT_CLK__GPIO5_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), /*P116, GPIO11*/ | 109 | MX8MP_PAD_SPDIF_EXT_CLK__GPIO5_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), /*P116, GPIO11*/ |
| 110 | }; | 110 | }; |
| 111 | 111 | ||
| 112 | static void setup_iomux_gpio(void) | 112 | static void setup_iomux_gpio(void) |
| 113 | { | 113 | { |
| 114 | imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); | 114 | imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); |
| 115 | 115 | ||
| 116 | /* Set GPIO0 as Output Low*/ | 116 | /* Set GPIO0 as Output Low*/ |
| 117 | gpio_request(IMX_GPIO_NR(3, 6), "GPIO0"); | 117 | gpio_request(IMX_GPIO_NR(3, 6), "GPIO0"); |
| 118 | gpio_direction_output(IMX_GPIO_NR(3, 6), 0); | 118 | gpio_direction_output(IMX_GPIO_NR(3, 6), 0); |
| 119 | /* Set GPIO1 as Output Low*/ | 119 | /* Set GPIO1 as Output Low*/ |
| 120 | gpio_request(IMX_GPIO_NR(3, 7), "GPIO1"); | 120 | gpio_request(IMX_GPIO_NR(3, 7), "GPIO1"); |
| 121 | gpio_direction_output(IMX_GPIO_NR(3, 7), 0); | 121 | gpio_direction_output(IMX_GPIO_NR(3, 7), 0); |
| 122 | /* Set GPIO2 as Output Low*/ | 122 | /* Set GPIO2 as Output Low*/ |
| 123 | gpio_request(IMX_GPIO_NR(3, 8), "GPIO2"); | 123 | gpio_request(IMX_GPIO_NR(3, 8), "GPIO2"); |
| 124 | gpio_direction_output(IMX_GPIO_NR(3, 8), 0); | 124 | gpio_direction_output(IMX_GPIO_NR(3, 8), 0); |
| 125 | /* Set GPIO3 as Output Low*/ | 125 | /* Set GPIO3 as Output Low*/ |
| 126 | gpio_request(IMX_GPIO_NR(3, 9), "GPIO3"); | 126 | gpio_request(IMX_GPIO_NR(3, 9), "GPIO3"); |
| 127 | gpio_direction_output(IMX_GPIO_NR(3, 9), 0); | 127 | gpio_direction_output(IMX_GPIO_NR(3, 9), 0); |
| 128 | /* Set GPIO4 as Output Low*/ | 128 | /* Set GPIO4 as Output Low*/ |
| 129 | gpio_request(IMX_GPIO_NR(1, 15), "GPIO4"); | 129 | gpio_request(IMX_GPIO_NR(1, 15), "GPIO4"); |
| 130 | gpio_direction_output(IMX_GPIO_NR(1, 15), 0); | 130 | gpio_direction_output(IMX_GPIO_NR(1, 15), 0); |
| 131 | /* Set GPIO5 as Output Low*/ | 131 | /* Set GPIO5 as Output Low*/ |
| 132 | gpio_request(IMX_GPIO_NR(5, 21), "GPIO5"); | 132 | gpio_request(IMX_GPIO_NR(5, 21), "GPIO5"); |
| 133 | gpio_direction_output(IMX_GPIO_NR(5, 21), 0); | 133 | gpio_direction_output(IMX_GPIO_NR(5, 21), 0); |
| 134 | /* Set GPIO6 as Input*/ | 134 | /* Set GPIO6 as Input*/ |
| 135 | gpio_request(IMX_GPIO_NR(5, 0), "GPIO6"); | 135 | gpio_request(IMX_GPIO_NR(5, 0), "GPIO6"); |
| 136 | gpio_direction_input(IMX_GPIO_NR(5, 0)); | 136 | gpio_direction_input(IMX_GPIO_NR(5, 0)); |
| 137 | /* Set GPIO7 as Input*/ | 137 | /* Set GPIO7 as Input*/ |
| 138 | gpio_request(IMX_GPIO_NR(5, 1), "GPIO7"); | 138 | gpio_request(IMX_GPIO_NR(5, 1), "GPIO7"); |
| 139 | gpio_direction_input(IMX_GPIO_NR(5, 1)); | 139 | gpio_direction_input(IMX_GPIO_NR(5, 1)); |
| 140 | /* Set GPIO8 as Input*/ | 140 | /* Set GPIO8 as Input*/ |
| 141 | gpio_request(IMX_GPIO_NR(4, 29), "GPIO8"); | 141 | gpio_request(IMX_GPIO_NR(4, 29), "GPIO8"); |
| 142 | gpio_direction_input(IMX_GPIO_NR(4, 29)); | 142 | gpio_direction_input(IMX_GPIO_NR(4, 29)); |
| 143 | /* Set GPIO9 as Input*/ | 143 | /* Set GPIO9 as Input*/ |
| 144 | gpio_request(IMX_GPIO_NR(5, 3), "GPIO9"); | 144 | gpio_request(IMX_GPIO_NR(5, 3), "GPIO9"); |
| 145 | gpio_direction_input(IMX_GPIO_NR(5, 3)); | 145 | gpio_direction_input(IMX_GPIO_NR(5, 3)); |
| 146 | /* Set GPIO10 as Input*/ | 146 | /* Set GPIO10 as Input*/ |
| 147 | gpio_request(IMX_GPIO_NR(5, 4), "GPIO10"); | 147 | gpio_request(IMX_GPIO_NR(5, 4), "GPIO10"); |
| 148 | gpio_direction_input(IMX_GPIO_NR(5, 4)); | 148 | gpio_direction_input(IMX_GPIO_NR(5, 4)); |
| 149 | /* Set GPIO11 as Input*/ | 149 | /* Set GPIO11 as Input*/ |
| 150 | gpio_request(IMX_GPIO_NR(5, 5), "GPIO11"); | 150 | gpio_request(IMX_GPIO_NR(5, 5), "GPIO11"); |
| 151 | gpio_direction_input(IMX_GPIO_NR(5, 5)); | 151 | gpio_direction_input(IMX_GPIO_NR(5, 5)); |
| 152 | } | 152 | } |
| 153 | 153 | ||
| 154 | #ifdef CONFIG_SYS_I2C | 154 | #ifdef CONFIG_SYS_I2C |
| 155 | /*I2C2, I2C_LCD*/ | 155 | /*I2C2, I2C_LCD*/ |
| 156 | struct i2c_pads_info i2c_pad_info2 = { | 156 | struct i2c_pads_info i2c_pad_info2 = { |
| 157 | .scl = { | 157 | .scl = { |
| 158 | .i2c_mode = MX8MP_PAD_I2C2_SCL__I2C2_SCL | I2C_PAD_CTRL, | 158 | .i2c_mode = MX8MP_PAD_I2C2_SCL__I2C2_SCL | I2C_PAD_CTRL, |
| 159 | .gpio_mode = MX8MP_PAD_I2C2_SCL__GPIO5_IO16 | I2C_PAD_CTRL, | 159 | .gpio_mode = MX8MP_PAD_I2C2_SCL__GPIO5_IO16 | I2C_PAD_CTRL, |
| 160 | .gp = IMX_GPIO_NR(5, 16), | 160 | .gp = IMX_GPIO_NR(5, 16), |
| 161 | }, | 161 | }, |
| 162 | .sda = { | 162 | .sda = { |
| 163 | .i2c_mode = MX8MP_PAD_I2C2_SDA__I2C2_SDA | I2C_PAD_CTRL, | 163 | .i2c_mode = MX8MP_PAD_I2C2_SDA__I2C2_SDA | I2C_PAD_CTRL, |
| 164 | .gpio_mode = MX8MP_PAD_I2C2_SDA__GPIO5_IO17 | I2C_PAD_CTRL, | 164 | .gpio_mode = MX8MP_PAD_I2C2_SDA__GPIO5_IO17 | I2C_PAD_CTRL, |
| 165 | .gp = IMX_GPIO_NR(5, 17), | 165 | .gp = IMX_GPIO_NR(5, 17), |
| 166 | }, | 166 | }, |
| 167 | }; | 167 | }; |
| 168 | 168 | ||
| 169 | /*I2C3, I2C_GP*/ | 169 | /*I2C3, I2C_GP*/ |
| 170 | struct i2c_pads_info i2c_pad_info3 = { | 170 | struct i2c_pads_info i2c_pad_info3 = { |
| 171 | .scl = { | 171 | .scl = { |
| 172 | .i2c_mode = MX8MP_PAD_I2C3_SCL__I2C3_SCL | I2C_PAD_CTRL, | 172 | .i2c_mode = MX8MP_PAD_I2C3_SCL__I2C3_SCL | I2C_PAD_CTRL, |
| 173 | .gpio_mode = MX8MP_PAD_I2C3_SCL__GPIO5_IO18 | I2C_PAD_CTRL, | 173 | .gpio_mode = MX8MP_PAD_I2C3_SCL__GPIO5_IO18 | I2C_PAD_CTRL, |
| 174 | .gp = IMX_GPIO_NR(5, 18), | 174 | .gp = IMX_GPIO_NR(5, 18), |
| 175 | }, | 175 | }, |
| 176 | .sda = { | 176 | .sda = { |
| 177 | .i2c_mode = MX8MP_PAD_I2C3_SDA__I2C3_SDA | I2C_PAD_CTRL, | 177 | .i2c_mode = MX8MP_PAD_I2C3_SDA__I2C3_SDA | I2C_PAD_CTRL, |
| 178 | .gpio_mode = MX8MP_PAD_I2C3_SDA__GPIO5_IO19 | I2C_PAD_CTRL, | 178 | .gpio_mode = MX8MP_PAD_I2C3_SDA__GPIO5_IO19 | I2C_PAD_CTRL, |
| 179 | .gp = IMX_GPIO_NR(5, 19), | 179 | .gp = IMX_GPIO_NR(5, 19), |
| 180 | }, | 180 | }, |
| 181 | }; | 181 | }; |
| 182 | 182 | ||
| 183 | /*I2C4, I2C_CAM0*/ | 183 | /*I2C4, I2C_CAM0*/ |
| 184 | struct i2c_pads_info i2c_pad_info4 = { | 184 | struct i2c_pads_info i2c_pad_info4 = { |
| 185 | .scl = { | 185 | .scl = { |
| 186 | .i2c_mode = MX8MP_PAD_ECSPI2_MISO__I2C4_SCL | I2C_PAD_CTRL, | 186 | .i2c_mode = MX8MP_PAD_ECSPI2_MISO__I2C4_SCL | I2C_PAD_CTRL, |
| 187 | .gpio_mode = MX8MP_PAD_ECSPI2_MISO__GPIO5_IO12 | I2C_PAD_CTRL, | 187 | .gpio_mode = MX8MP_PAD_ECSPI2_MISO__GPIO5_IO12 | I2C_PAD_CTRL, |
| 188 | .gp = IMX_GPIO_NR(5, 12), | 188 | .gp = IMX_GPIO_NR(5, 12), |
| 189 | }, | 189 | }, |
| 190 | .sda = { | 190 | .sda = { |
| 191 | .i2c_mode = MX8MP_PAD_ECSPI2_SS0__I2C4_SDA | I2C_PAD_CTRL, | 191 | .i2c_mode = MX8MP_PAD_ECSPI2_SS0__I2C4_SDA | I2C_PAD_CTRL, |
| 192 | .gpio_mode = MX8MP_PAD_ECSPI2_SS0__GPIO5_IO13 | I2C_PAD_CTRL, | 192 | .gpio_mode = MX8MP_PAD_ECSPI2_SS0__GPIO5_IO13 | I2C_PAD_CTRL, |
| 193 | .gp = IMX_GPIO_NR(5, 13), | 193 | .gp = IMX_GPIO_NR(5, 13), |
| 194 | }, | 194 | }, |
| 195 | }; | 195 | }; |
| 196 | 196 | ||
| 197 | /*I2C6, I2C_CAM1*/ | 197 | /*I2C6, I2C_CAM1*/ |
| 198 | struct i2c_pads_info i2c_pad_info6 = { | 198 | struct i2c_pads_info i2c_pad_info6 = { |
| 199 | .scl = { | 199 | .scl = { |
| 200 | .i2c_mode = MX8MP_PAD_SAI5_RXFS__I2C6_SCL | I2C_PAD_CTRL, | 200 | .i2c_mode = MX8MP_PAD_SAI5_RXFS__I2C6_SCL | I2C_PAD_CTRL, |
| 201 | .gpio_mode = MX8MP_PAD_SAI5_RXFS__GPIO3_IO19 | I2C_PAD_CTRL, | 201 | .gpio_mode = MX8MP_PAD_SAI5_RXFS__GPIO3_IO19 | I2C_PAD_CTRL, |
| 202 | .gp = IMX_GPIO_NR(3, 19), | 202 | .gp = IMX_GPIO_NR(3, 19), |
| 203 | }, | 203 | }, |
| 204 | .sda = { | 204 | .sda = { |
| 205 | .i2c_mode = MX8MP_PAD_SAI5_RXC__I2C6_SDA | I2C_PAD_CTRL, | 205 | .i2c_mode = MX8MP_PAD_SAI5_RXC__I2C6_SDA | I2C_PAD_CTRL, |
| 206 | .gpio_mode = MX8MP_PAD_SAI5_RXC__GPIO3_IO20 | I2C_PAD_CTRL, | 206 | .gpio_mode = MX8MP_PAD_SAI5_RXC__GPIO3_IO20 | I2C_PAD_CTRL, |
| 207 | .gp = IMX_GPIO_NR(3, 20), | 207 | .gp = IMX_GPIO_NR(3, 20), |
| 208 | }, | 208 | }, |
| 209 | }; | 209 | }; |
| 210 | #endif | 210 | #endif |
| 211 | 211 | ||
| 212 | #ifdef CONFIG_NAND_MXS | 212 | #ifdef CONFIG_NAND_MXS |
| 213 | 213 | ||
| 214 | static void setup_gpmi_nand(void) | 214 | static void setup_gpmi_nand(void) |
| 215 | { | 215 | { |
| 216 | init_nand_clk(); | 216 | init_nand_clk(); |
| 217 | } | 217 | } |
| 218 | #endif | 218 | #endif |
| 219 | 219 | ||
| 220 | int board_early_init_f(void) | 220 | int board_early_init_f(void) |
| 221 | { | 221 | { |
| 222 | struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; | 222 | struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; |
| 223 | 223 | ||
| 224 | imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); | 224 | imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); |
| 225 | 225 | ||
| 226 | set_wdog_reset(wdog); | 226 | set_wdog_reset(wdog); |
| 227 | 227 | ||
| 228 | #ifdef CONFIG_CONSOLE_SER0 | 228 | #ifdef CONFIG_CONSOLE_SER0 |
| 229 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); | 229 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| 230 | init_uart_clk(0); | 230 | init_uart_clk(0); |
| 231 | #endif | 231 | #endif |
| 232 | 232 | ||
| 233 | #ifdef CONFIG_CONSOLE_SER1 | 233 | #ifdef CONFIG_CONSOLE_SER1 |
| 234 | imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); | 234 | imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); |
| 235 | init_uart_clk(3); | 235 | init_uart_clk(3); |
| 236 | #endif | 236 | #endif |
| 237 | 237 | ||
| 238 | #ifdef CONFIG_CONSOLE_SER2 | 238 | #ifdef CONFIG_CONSOLE_SER2 |
| 239 | imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); | 239 | imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); |
| 240 | init_uart_clk(2); | 240 | init_uart_clk(2); |
| 241 | #endif | 241 | #endif |
| 242 | 242 | ||
| 243 | #ifdef CONFIG_CONSOLE_SER3 | 243 | #ifdef CONFIG_CONSOLE_SER3 |
| 244 | imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); | 244 | imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); |
| 245 | init_uart_clk(1); | 245 | init_uart_clk(1); |
| 246 | #endif | 246 | #endif |
| 247 | 247 | ||
| 248 | return 0; | 248 | return 0; |
| 249 | } | 249 | } |
| 250 | 250 | ||
| 251 | #ifdef CONFIG_OF_BOARD_SETUP | 251 | #ifdef CONFIG_OF_BOARD_SETUP |
| 252 | int ft_board_setup(void *blob, bd_t *bd) | 252 | int ft_board_setup(void *blob, bd_t *bd) |
| 253 | { | 253 | { |
| 254 | #ifdef CONFIG_IMX8M_DRAM_INLINE_ECC | 254 | #ifdef CONFIG_IMX8M_DRAM_INLINE_ECC |
| 255 | #ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK | 255 | #ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK |
| 256 | int rc; | 256 | int rc; |
| 257 | phys_addr_t ecc_start = 0x120000000; | 257 | phys_addr_t ecc_start = 0x120000000; |
| 258 | size_t ecc_size = 0x20000000; | 258 | size_t ecc_size = 0x20000000; |
| 259 | 259 | ||
| 260 | rc = add_res_mem_dt_node(blob, "ecc", ecc_start, ecc_size); | 260 | rc = add_res_mem_dt_node(blob, "ecc", ecc_start, ecc_size); |
| 261 | if (rc < 0) { | 261 | if (rc < 0) { |
| 262 | printf("Could not create ecc reserved-memory node.\n"); | 262 | printf("Could not create ecc reserved-memory node.\n"); |
| 263 | return rc; | 263 | return rc; |
| 264 | } | 264 | } |
| 265 | #else | 265 | #else |
| 266 | int rc; | 266 | int rc; |
| 267 | phys_addr_t ecc0_start = 0xb0000000; | 267 | phys_addr_t ecc0_start = 0xb0000000; |
| 268 | phys_addr_t ecc1_start = 0x130000000; | 268 | phys_addr_t ecc1_start = 0x130000000; |
| 269 | phys_addr_t ecc2_start = 0x1b0000000; | 269 | phys_addr_t ecc2_start = 0x1b0000000; |
| 270 | size_t ecc_size = 0x10000000; | 270 | size_t ecc_size = 0x10000000; |
| 271 | 271 | ||
| 272 | rc = add_res_mem_dt_node(blob, "ecc", ecc0_start, ecc_size); | 272 | rc = add_res_mem_dt_node(blob, "ecc", ecc0_start, ecc_size); |
| 273 | if (rc < 0) { | 273 | if (rc < 0) { |
| 274 | printf("Could not create ecc0 reserved-memory node.\n"); | 274 | printf("Could not create ecc0 reserved-memory node.\n"); |
| 275 | return rc; | 275 | return rc; |
| 276 | } | 276 | } |
| 277 | 277 | ||
| 278 | rc = add_res_mem_dt_node(blob, "ecc", ecc1_start, ecc_size); | 278 | rc = add_res_mem_dt_node(blob, "ecc", ecc1_start, ecc_size); |
| 279 | if (rc < 0) { | 279 | if (rc < 0) { |
| 280 | printf("Could not create ecc1 reserved-memory node.\n"); | 280 | printf("Could not create ecc1 reserved-memory node.\n"); |
| 281 | return rc; | 281 | return rc; |
| 282 | } | 282 | } |
| 283 | 283 | ||
| 284 | rc = add_res_mem_dt_node(blob, "ecc", ecc2_start, ecc_size); | 284 | rc = add_res_mem_dt_node(blob, "ecc", ecc2_start, ecc_size); |
| 285 | if (rc < 0) { | 285 | if (rc < 0) { |
| 286 | printf("Could not create ecc2 reserved-memory node.\n"); | 286 | printf("Could not create ecc2 reserved-memory node.\n"); |
| 287 | return rc; | 287 | return rc; |
| 288 | } | 288 | } |
| 289 | #endif | 289 | #endif |
| 290 | #endif | 290 | #endif |
| 291 | 291 | ||
| 292 | return 0; | 292 | return 0; |
| 293 | } | 293 | } |
| 294 | #endif | 294 | #endif |
| 295 | 295 | ||
| 296 | #ifdef CONFIG_FEC_MXC | 296 | #ifdef CONFIG_FEC_MXC |
| 297 | #define FEC_IRQ_PAD IMX_GPIO_NR(4, 21) | 297 | #define FEC_IRQ_PAD IMX_GPIO_NR(4, 21) |
| 298 | static iomux_v3_cfg_t const fec1_irq_pads[] = { | 298 | static iomux_v3_cfg_t const fec1_irq_pads[] = { |
| 299 | MX8MP_PAD_SAI2_RXFS__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), | 299 | MX8MP_PAD_SAI2_RXFS__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 300 | }; | 300 | }; |
| 301 | 301 | ||
| 302 | static void setup_iomux_fec(void) | 302 | static void setup_iomux_fec(void) |
| 303 | { | 303 | { |
| 304 | imx_iomux_v3_setup_multiple_pads(fec1_irq_pads, | 304 | imx_iomux_v3_setup_multiple_pads(fec1_irq_pads, |
| 305 | ARRAY_SIZE(fec1_irq_pads)); | 305 | ARRAY_SIZE(fec1_irq_pads)); |
| 306 | 306 | ||
| 307 | gpio_request(FEC_IRQ_PAD, "fec1_irq"); | 307 | gpio_request(FEC_IRQ_PAD, "fec1_irq"); |
| 308 | gpio_direction_input(FEC_IRQ_PAD); | 308 | gpio_direction_input(FEC_IRQ_PAD); |
| 309 | } | 309 | } |
| 310 | 310 | ||
| 311 | static int setup_fec(void) | 311 | static int setup_fec(void) |
| 312 | { | 312 | { |
| 313 | struct iomuxc_gpr_base_regs *gpr = | 313 | struct iomuxc_gpr_base_regs *gpr = |
| 314 | (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; | 314 | (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; |
| 315 | 315 | ||
| 316 | setup_iomux_fec(); | 316 | setup_iomux_fec(); |
| 317 | 317 | ||
| 318 | /* Enable RGMII TX clk output */ | 318 | /* Enable RGMII TX clk output */ |
| 319 | setbits_le32(&gpr->gpr[1], BIT(22)); | 319 | setbits_le32(&gpr->gpr[1], BIT(22)); |
| 320 | 320 | ||
| 321 | //return set_clk_enet(ENET_125MHZ); | 321 | //return set_clk_enet(ENET_125MHZ); |
| 322 | return 0; | 322 | return 0; |
| 323 | } | 323 | } |
| 324 | #endif | 324 | #endif |
| 325 | 325 | ||
| 326 | #ifdef CONFIG_DWC_ETH_QOS | 326 | #ifdef CONFIG_DWC_ETH_QOS |
| 327 | 327 | ||
| 328 | #define EQOS_IRQ_PAD IMX_GPIO_NR(4, 3) | 328 | #define EQOS_IRQ_PAD IMX_GPIO_NR(4, 3) |
| 329 | static iomux_v3_cfg_t const eqos_irq_pads[] = { | 329 | static iomux_v3_cfg_t const eqos_irq_pads[] = { |
| 330 | MX8MP_PAD_SAI1_RXD1__GPIO4_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL), | 330 | MX8MP_PAD_SAI1_RXD1__GPIO4_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 331 | }; | 331 | }; |
| 332 | 332 | ||
| 333 | static void setup_iomux_eqos(void) | 333 | static void setup_iomux_eqos(void) |
| 334 | { | 334 | { |
| 335 | imx_iomux_v3_setup_multiple_pads(eqos_irq_pads, | 335 | imx_iomux_v3_setup_multiple_pads(eqos_irq_pads, |
| 336 | ARRAY_SIZE(eqos_irq_pads)); | 336 | ARRAY_SIZE(eqos_irq_pads)); |
| 337 | 337 | ||
| 338 | gpio_request(EQOS_IRQ_PAD, "eqos_irq"); | 338 | gpio_request(EQOS_IRQ_PAD, "eqos_irq"); |
| 339 | gpio_direction_input(EQOS_IRQ_PAD); | 339 | gpio_direction_input(EQOS_IRQ_PAD); |
| 340 | } | 340 | } |
| 341 | 341 | ||
| 342 | static int setup_eqos(void) | 342 | static int setup_eqos(void) |
| 343 | { | 343 | { |
| 344 | struct iomuxc_gpr_base_regs *gpr = | 344 | struct iomuxc_gpr_base_regs *gpr = |
| 345 | (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; | 345 | (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; |
| 346 | 346 | ||
| 347 | setup_iomux_eqos(); | 347 | setup_iomux_eqos(); |
| 348 | 348 | ||
| 349 | /* set INTF as RGMII, enable RGMII TXC clock */ | 349 | /* set INTF as RGMII, enable RGMII TXC clock */ |
| 350 | clrsetbits_le32(&gpr->gpr[1], | 350 | clrsetbits_le32(&gpr->gpr[1], |
| 351 | IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); | 351 | IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); |
| 352 | setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); | 352 | setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); |
| 353 | 353 | ||
| 354 | return set_clk_eqos(ENET_125MHZ); | 354 | return set_clk_eqos(ENET_125MHZ); |
| 355 | } | 355 | } |
| 356 | #endif | 356 | #endif |
| 357 | 357 | ||
| 358 | #if defined(CONFIG_FEC_MXC) || defined(CONFIG_DWC_ETH_QOS) | 358 | #if defined(CONFIG_FEC_MXC) || defined(CONFIG_DWC_ETH_QOS) |
| 359 | int board_phy_config(struct phy_device *phydev) | 359 | int board_phy_config(struct phy_device *phydev) |
| 360 | { | 360 | { |
| 361 | if (phydev->drv->config) | 361 | if (phydev->drv->config) |
| 362 | phydev->drv->config(phydev); | 362 | phydev->drv->config(phydev); |
| 363 | return 0; | 363 | return 0; |
| 364 | } | 364 | } |
| 365 | #endif | 365 | #endif |
| 366 | 366 | ||
| 367 | /*USB Enable Over-Current Pin Setting*/ | 367 | /*USB Enable Over-Current Pin Setting*/ |
| 368 | static iomux_v3_cfg_t const usb_en_oc_pads[] = { | 368 | static iomux_v3_cfg_t const usb_en_oc_pads[] = { |
| 369 | MX8MP_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), | 369 | MX8MP_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), |
| 370 | MX8MP_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), | 370 | MX8MP_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), |
| 371 | }; | 371 | }; |
| 372 | 372 | ||
| 373 | static void setup_iomux_usb_en_oc(void) | 373 | static void setup_iomux_usb_en_oc(void) |
| 374 | { | 374 | { |
| 375 | imx_iomux_v3_setup_multiple_pads(usb_en_oc_pads, | 375 | imx_iomux_v3_setup_multiple_pads(usb_en_oc_pads, |
| 376 | ARRAY_SIZE(usb_en_oc_pads)); | 376 | ARRAY_SIZE(usb_en_oc_pads)); |
| 377 | 377 | ||
| 378 | gpio_request(IMX_GPIO_NR(1, 12), "usb0_en"); | 378 | gpio_request(IMX_GPIO_NR(1, 12), "usb0_en"); |
| 379 | gpio_direction_output(IMX_GPIO_NR(1, 12), 1); | 379 | gpio_direction_output(IMX_GPIO_NR(1, 12), 1); |
| 380 | gpio_request(IMX_GPIO_NR(1, 13), "usb0_oc#"); | 380 | gpio_request(IMX_GPIO_NR(1, 13), "usb0_oc#"); |
| 381 | gpio_direction_input(IMX_GPIO_NR(1, 13)); | 381 | gpio_direction_input(IMX_GPIO_NR(1, 13)); |
| 382 | } | 382 | } |
| 383 | 383 | ||
| 384 | #ifdef CONFIG_USB_TCPC | 384 | #ifdef CONFIG_USB_TCPC |
| 385 | struct tcpc_port port1; | 385 | struct tcpc_port port1; |
| 386 | struct tcpc_port port2; | 386 | struct tcpc_port port2; |
| 387 | 387 | ||
| 388 | static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr) | 388 | static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr) |
| 389 | { | 389 | { |
| 390 | struct udevice *bus; | 390 | struct udevice *bus; |
| 391 | struct udevice *i2c_dev = NULL; | 391 | struct udevice *i2c_dev = NULL; |
| 392 | int ret; | 392 | int ret; |
| 393 | uint8_t valb; | 393 | uint8_t valb; |
| 394 | 394 | ||
| 395 | ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); | 395 | ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); |
| 396 | if (ret) { | 396 | if (ret) { |
| 397 | printf("%s: Can't find bus\n", __func__); | 397 | printf("%s: Can't find bus\n", __func__); |
| 398 | return -EINVAL; | 398 | return -EINVAL; |
| 399 | } | 399 | } |
| 400 | 400 | ||
| 401 | ret = dm_i2c_probe(bus, addr, 0, &i2c_dev); | 401 | ret = dm_i2c_probe(bus, addr, 0, &i2c_dev); |
| 402 | if (ret) { | 402 | if (ret) { |
| 403 | printf("%s: Can't find device id=0x%x\n", | 403 | printf("%s: Can't find device id=0x%x\n", |
| 404 | __func__, addr); | 404 | __func__, addr); |
| 405 | return -ENODEV; | 405 | return -ENODEV; |
| 406 | } | 406 | } |
| 407 | 407 | ||
| 408 | ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1); | 408 | ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1); |
| 409 | if (ret) { | 409 | if (ret) { |
| 410 | printf("%s dm_i2c_read failed, err %d\n", __func__, ret); | 410 | printf("%s dm_i2c_read failed, err %d\n", __func__, ret); |
| 411 | return -EIO; | 411 | return -EIO; |
| 412 | } | 412 | } |
| 413 | valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */ | 413 | valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */ |
| 414 | ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1); | 414 | ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1); |
| 415 | if (ret) { | 415 | if (ret) { |
| 416 | printf("%s dm_i2c_write failed, err %d\n", __func__, ret); | 416 | printf("%s dm_i2c_write failed, err %d\n", __func__, ret); |
| 417 | return -EIO; | 417 | return -EIO; |
| 418 | } | 418 | } |
| 419 | 419 | ||
| 420 | /* Set OVP threshold to 23V */ | 420 | /* Set OVP threshold to 23V */ |
| 421 | valb = 0x6; | 421 | valb = 0x6; |
| 422 | ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1); | 422 | ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1); |
| 423 | if (ret) { | 423 | if (ret) { |
| 424 | printf("%s dm_i2c_write failed, err %d\n", __func__, ret); | 424 | printf("%s dm_i2c_write failed, err %d\n", __func__, ret); |
| 425 | return -EIO; | 425 | return -EIO; |
| 426 | } | 426 | } |
| 427 | 427 | ||
| 428 | return 0; | 428 | return 0; |
| 429 | } | 429 | } |
| 430 | 430 | ||
| 431 | int pd_switch_snk_enable(struct tcpc_port *port) | 431 | int pd_switch_snk_enable(struct tcpc_port *port) |
| 432 | { | 432 | { |
| 433 | if (port == &port1) { | 433 | if (port == &port1) { |
| 434 | debug("Setup pd switch on port 1\n"); | 434 | debug("Setup pd switch on port 1\n"); |
| 435 | return setup_pd_switch(1, 0x72); | 435 | return setup_pd_switch(1, 0x72); |
| 436 | } else | 436 | } else |
| 437 | return -EINVAL; | 437 | return -EINVAL; |
| 438 | } | 438 | } |
| 439 | 439 | ||
| 440 | /* Port2 is the power supply, port 1 does not support power */ | 440 | /* Port2 is the power supply, port 1 does not support power */ |
| 441 | struct tcpc_port_config port1_config = { | 441 | struct tcpc_port_config port1_config = { |
| 442 | .i2c_bus = 1, /*i2c2*/ | 442 | .i2c_bus = 1, /*i2c2*/ |
| 443 | .addr = 0x50, | 443 | .addr = 0x50, |
| 444 | .port_type = TYPEC_PORT_UFP, | 444 | .port_type = TYPEC_PORT_UFP, |
| 445 | .max_snk_mv = 20000, | 445 | .max_snk_mv = 20000, |
| 446 | .max_snk_ma = 3000, | 446 | .max_snk_ma = 3000, |
| 447 | .max_snk_mw = 45000, | 447 | .max_snk_mw = 45000, |
| 448 | .op_snk_mv = 15000, | 448 | .op_snk_mv = 15000, |
| 449 | .switch_setup_func = &pd_switch_snk_enable, | 449 | .switch_setup_func = &pd_switch_snk_enable, |
| 450 | .disable_pd = true, | 450 | .disable_pd = true, |
| 451 | }; | 451 | }; |
| 452 | 452 | ||
| 453 | struct tcpc_port_config port2_config = { | 453 | struct tcpc_port_config port2_config = { |
| 454 | .i2c_bus = 2, /*i2c3*/ | 454 | .i2c_bus = 2, /*i2c3*/ |
| 455 | .addr = 0x50, | 455 | .addr = 0x50, |
| 456 | .port_type = TYPEC_PORT_UFP, | 456 | .port_type = TYPEC_PORT_UFP, |
| 457 | .max_snk_mv = 20000, | 457 | .max_snk_mv = 20000, |
| 458 | .max_snk_ma = 3000, | 458 | .max_snk_ma = 3000, |
| 459 | .max_snk_mw = 45000, | 459 | .max_snk_mw = 45000, |
| 460 | .op_snk_mv = 15000, | 460 | .op_snk_mv = 15000, |
| 461 | }; | 461 | }; |
| 462 | 462 | ||
| 463 | #define USB_TYPEC_SEL IMX_GPIO_NR(4, 20) | 463 | #define USB_TYPEC_SEL IMX_GPIO_NR(4, 20) |
| 464 | #define USB_TYPEC_EN IMX_GPIO_NR(2, 20) | 464 | #define USB_TYPEC_EN IMX_GPIO_NR(2, 20) |
| 465 | 465 | ||
| 466 | static iomux_v3_cfg_t ss_mux_gpio[] = { | 466 | static iomux_v3_cfg_t ss_mux_gpio[] = { |
| 467 | MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), | 467 | MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 468 | MX8MP_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), | 468 | MX8MP_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 469 | }; | 469 | }; |
| 470 | 470 | ||
| 471 | void ss_mux_select(enum typec_cc_polarity pol) | 471 | void ss_mux_select(enum typec_cc_polarity pol) |
| 472 | { | 472 | { |
| 473 | if (pol == TYPEC_POLARITY_CC1) | 473 | if (pol == TYPEC_POLARITY_CC1) |
| 474 | gpio_direction_output(USB_TYPEC_SEL, 0); | 474 | gpio_direction_output(USB_TYPEC_SEL, 0); |
| 475 | else | 475 | else |
| 476 | gpio_direction_output(USB_TYPEC_SEL, 1); | 476 | gpio_direction_output(USB_TYPEC_SEL, 1); |
| 477 | } | 477 | } |
| 478 | 478 | ||
| 479 | static int setup_typec(void) | 479 | static int setup_typec(void) |
| 480 | { | 480 | { |
| 481 | int ret; | 481 | int ret; |
| 482 | struct gpio_desc per_12v_desc; | 482 | struct gpio_desc per_12v_desc; |
| 483 | 483 | ||
| 484 | debug("tcpc_init port 2\n"); | 484 | debug("tcpc_init port 2\n"); |
| 485 | ret = tcpc_init(&port2, port2_config, NULL); | 485 | ret = tcpc_init(&port2, port2_config, NULL); |
| 486 | if (ret) { | 486 | if (ret) { |
| 487 | printf("%s: tcpc port2 init failed, err=%d\n", | 487 | printf("%s: tcpc port2 init failed, err=%d\n", |
| 488 | __func__, ret); | 488 | __func__, ret); |
| 489 | } else if (tcpc_pd_sink_check_charging(&port2)) { | 489 | } else if (tcpc_pd_sink_check_charging(&port2)) { |
| 490 | printf("Power supply on USB2\n"); | 490 | printf("Power supply on USB2\n"); |
| 491 | 491 | ||
| 492 | /* Enable PER 12V, any check before it? */ | 492 | /* Enable PER 12V, any check before it? */ |
| 493 | ret = dm_gpio_lookup_name("gpio@20_1", &per_12v_desc); | 493 | ret = dm_gpio_lookup_name("gpio@20_1", &per_12v_desc); |
| 494 | if (ret) { | 494 | if (ret) { |
| 495 | printf("%s lookup gpio@20_1 failed ret = %d\n", __func__, ret); | 495 | printf("%s lookup gpio@20_1 failed ret = %d\n", __func__, ret); |
| 496 | return -ENODEV; | 496 | return -ENODEV; |
| 497 | } | 497 | } |
| 498 | 498 | ||
| 499 | ret = dm_gpio_request(&per_12v_desc, "per_12v_en"); | 499 | ret = dm_gpio_request(&per_12v_desc, "per_12v_en"); |
| 500 | if (ret) { | 500 | if (ret) { |
| 501 | printf("%s request per_12v failed ret = %d\n", __func__, ret); | 501 | printf("%s request per_12v failed ret = %d\n", __func__, ret); |
| 502 | return -EIO; | 502 | return -EIO; |
| 503 | } | 503 | } |
| 504 | 504 | ||
| 505 | /* Enable PER 12V regulator */ | 505 | /* Enable PER 12V regulator */ |
| 506 | dm_gpio_set_dir_flags(&per_12v_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); | 506 | dm_gpio_set_dir_flags(&per_12v_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); |
| 507 | } | 507 | } |
| 508 | 508 | ||
| 509 | debug("tcpc_init port 1\n"); | 509 | debug("tcpc_init port 1\n"); |
| 510 | imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); | 510 | imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); |
| 511 | gpio_request(USB_TYPEC_SEL, "typec_sel"); | 511 | gpio_request(USB_TYPEC_SEL, "typec_sel"); |
| 512 | gpio_request(USB_TYPEC_EN, "typec_en"); | 512 | gpio_request(USB_TYPEC_EN, "typec_en"); |
| 513 | gpio_direction_output(USB_TYPEC_EN, 0); | 513 | gpio_direction_output(USB_TYPEC_EN, 0); |
| 514 | 514 | ||
| 515 | ret = tcpc_init(&port1, port1_config, &ss_mux_select); | 515 | ret = tcpc_init(&port1, port1_config, &ss_mux_select); |
| 516 | if (ret) { | 516 | if (ret) { |
| 517 | printf("%s: tcpc port1 init failed, err=%d\n", | 517 | printf("%s: tcpc port1 init failed, err=%d\n", |
| 518 | __func__, ret); | 518 | __func__, ret); |
| 519 | } else { | 519 | } else { |
| 520 | return ret; | 520 | return ret; |
| 521 | } | 521 | } |
| 522 | 522 | ||
| 523 | return ret; | 523 | return ret; |
| 524 | } | 524 | } |
| 525 | #endif | 525 | #endif |
| 526 | 526 | ||
| 527 | #ifdef CONFIG_USB_DWC3 | 527 | #ifdef CONFIG_USB_DWC3 |
| 528 | 528 | ||
| 529 | #define USB_PHY_CTRL0 0xF0040 | 529 | #define USB_PHY_CTRL0 0xF0040 |
| 530 | #define USB_PHY_CTRL0_REF_SSP_EN BIT(2) | 530 | #define USB_PHY_CTRL0_REF_SSP_EN BIT(2) |
| 531 | 531 | ||
| 532 | #define USB_PHY_CTRL1 0xF0044 | 532 | #define USB_PHY_CTRL1 0xF0044 |
| 533 | #define USB_PHY_CTRL1_RESET BIT(0) | 533 | #define USB_PHY_CTRL1_RESET BIT(0) |
| 534 | #define USB_PHY_CTRL1_COMMONONN BIT(1) | 534 | #define USB_PHY_CTRL1_COMMONONN BIT(1) |
| 535 | #define USB_PHY_CTRL1_ATERESET BIT(3) | 535 | #define USB_PHY_CTRL1_ATERESET BIT(3) |
| 536 | #define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) | 536 | #define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) |
| 537 | #define USB_PHY_CTRL1_VDATDETENB0 BIT(20) | 537 | #define USB_PHY_CTRL1_VDATDETENB0 BIT(20) |
| 538 | 538 | ||
| 539 | #define USB_PHY_CTRL2 0xF0048 | 539 | #define USB_PHY_CTRL2 0xF0048 |
| 540 | #define USB_PHY_CTRL2_TXENABLEN0 BIT(8) | 540 | #define USB_PHY_CTRL2_TXENABLEN0 BIT(8) |
| 541 | 541 | ||
| 542 | #define USB_PHY_CTRL6 0xF0058 | 542 | #define USB_PHY_CTRL6 0xF0058 |
| 543 | 543 | ||
| 544 | #define HSIO_GPR_BASE (0x32F10000U) | 544 | #define HSIO_GPR_BASE (0x32F10000U) |
| 545 | #define HSIO_GPR_REG_0 (HSIO_GPR_BASE) | 545 | #define HSIO_GPR_REG_0 (HSIO_GPR_BASE) |
| 546 | #define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT (1) | 546 | #define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT (1) |
| 547 | #define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN (0x1U << HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT) | 547 | #define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN (0x1U << HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT) |
| 548 | 548 | ||
| 549 | 549 | ||
| 550 | static struct dwc3_device dwc3_device_data = { | 550 | static struct dwc3_device dwc3_device_data = { |
| 551 | #ifdef CONFIG_SPL_BUILD | 551 | #ifdef CONFIG_SPL_BUILD |
| 552 | .maximum_speed = USB_SPEED_HIGH, | 552 | .maximum_speed = USB_SPEED_HIGH, |
| 553 | #else | 553 | #else |
| 554 | .maximum_speed = USB_SPEED_SUPER, | 554 | .maximum_speed = USB_SPEED_SUPER, |
| 555 | #endif | 555 | #endif |
| 556 | .base = USB1_BASE_ADDR, | 556 | .base = USB1_BASE_ADDR, |
| 557 | .dr_mode = USB_DR_MODE_PERIPHERAL, | 557 | .dr_mode = USB_DR_MODE_PERIPHERAL, |
| 558 | .index = 0, | 558 | .index = 0, |
| 559 | .power_down_scale = 2, | 559 | .power_down_scale = 2, |
| 560 | }; | 560 | }; |
| 561 | 561 | ||
| 562 | int usb_gadget_handle_interrupts(void) | 562 | int usb_gadget_handle_interrupts(void) |
| 563 | { | 563 | { |
| 564 | dwc3_uboot_handle_interrupt(0); | 564 | dwc3_uboot_handle_interrupt(0); |
| 565 | return 0; | 565 | return 0; |
| 566 | } | 566 | } |
| 567 | 567 | ||
| 568 | static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) | 568 | static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) |
| 569 | { | 569 | { |
| 570 | u32 RegData; | 570 | u32 RegData; |
| 571 | 571 | ||
| 572 | /* enable usb clock via hsio gpr */ | 572 | /* enable usb clock via hsio gpr */ |
| 573 | RegData = readl(HSIO_GPR_REG_0); | 573 | RegData = readl(HSIO_GPR_REG_0); |
| 574 | RegData |= HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN; | 574 | RegData |= HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN; |
| 575 | writel(RegData, HSIO_GPR_REG_0); | 575 | writel(RegData, HSIO_GPR_REG_0); |
| 576 | 576 | ||
| 577 | /* USB3.0 PHY signal fsel for 100M ref */ | 577 | /* USB3.0 PHY signal fsel for 100M ref */ |
| 578 | RegData = readl(dwc3->base + USB_PHY_CTRL0); | 578 | RegData = readl(dwc3->base + USB_PHY_CTRL0); |
| 579 | RegData = (RegData & 0xfffff81f) | (0x2a<<5); | 579 | RegData = (RegData & 0xfffff81f) | (0x2a<<5); |
| 580 | writel(RegData, dwc3->base + USB_PHY_CTRL0); | 580 | writel(RegData, dwc3->base + USB_PHY_CTRL0); |
| 581 | 581 | ||
| 582 | RegData = readl(dwc3->base + USB_PHY_CTRL6); | 582 | RegData = readl(dwc3->base + USB_PHY_CTRL6); |
| 583 | RegData &=~0x1; | 583 | RegData &=~0x1; |
| 584 | writel(RegData, dwc3->base + USB_PHY_CTRL6); | 584 | writel(RegData, dwc3->base + USB_PHY_CTRL6); |
| 585 | 585 | ||
| 586 | RegData = readl(dwc3->base + USB_PHY_CTRL1); | 586 | RegData = readl(dwc3->base + USB_PHY_CTRL1); |
| 587 | RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | | 587 | RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | |
| 588 | USB_PHY_CTRL1_COMMONONN); | 588 | USB_PHY_CTRL1_COMMONONN); |
| 589 | RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; | 589 | RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; |
| 590 | writel(RegData, dwc3->base + USB_PHY_CTRL1); | 590 | writel(RegData, dwc3->base + USB_PHY_CTRL1); |
| 591 | 591 | ||
| 592 | RegData = readl(dwc3->base + USB_PHY_CTRL0); | 592 | RegData = readl(dwc3->base + USB_PHY_CTRL0); |
| 593 | RegData |= USB_PHY_CTRL0_REF_SSP_EN; | 593 | RegData |= USB_PHY_CTRL0_REF_SSP_EN; |
| 594 | writel(RegData, dwc3->base + USB_PHY_CTRL0); | 594 | writel(RegData, dwc3->base + USB_PHY_CTRL0); |
| 595 | 595 | ||
| 596 | RegData = readl(dwc3->base + USB_PHY_CTRL2); | 596 | RegData = readl(dwc3->base + USB_PHY_CTRL2); |
| 597 | RegData |= USB_PHY_CTRL2_TXENABLEN0; | 597 | RegData |= USB_PHY_CTRL2_TXENABLEN0; |
| 598 | writel(RegData, dwc3->base + USB_PHY_CTRL2); | 598 | writel(RegData, dwc3->base + USB_PHY_CTRL2); |
| 599 | 599 | ||
| 600 | RegData = readl(dwc3->base + USB_PHY_CTRL1); | 600 | RegData = readl(dwc3->base + USB_PHY_CTRL1); |
| 601 | RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); | 601 | RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); |
| 602 | writel(RegData, dwc3->base + USB_PHY_CTRL1); | 602 | writel(RegData, dwc3->base + USB_PHY_CTRL1); |
| 603 | } | 603 | } |
| 604 | #endif | 604 | #endif |
| 605 | 605 | ||
| 606 | #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) | 606 | #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) |
| 607 | #define USB2_PWR_EN IMX_GPIO_NR(1, 14) | 607 | #define USB2_PWR_EN IMX_GPIO_NR(1, 14) |
| 608 | int board_usb_init(int index, enum usb_init_type init) | 608 | int board_usb_init(int index, enum usb_init_type init) |
| 609 | { | 609 | { |
| 610 | int ret = 0; | 610 | int ret = 0; |
| 611 | imx8m_usb_power(index, true); | 611 | imx8m_usb_power(index, true); |
| 612 | 612 | ||
| 613 | if (index == 0 && init == USB_INIT_DEVICE) { | 613 | if (index == 0 && init == USB_INIT_DEVICE) { |
| 614 | #ifdef CONFIG_USB_TCPC | 614 | #ifdef CONFIG_USB_TCPC |
| 615 | ret = tcpc_setup_ufp_mode(&port1); | 615 | ret = tcpc_setup_ufp_mode(&port1); |
| 616 | if (ret) | 616 | if (ret) |
| 617 | return ret; | 617 | return ret; |
| 618 | #endif | 618 | #endif |
| 619 | dwc3_nxp_usb_phy_init(&dwc3_device_data); | 619 | dwc3_nxp_usb_phy_init(&dwc3_device_data); |
| 620 | return dwc3_uboot_init(&dwc3_device_data); | 620 | return dwc3_uboot_init(&dwc3_device_data); |
| 621 | } else if (index == 0 && init == USB_INIT_HOST) { | 621 | } else if (index == 0 && init == USB_INIT_HOST) { |
| 622 | #ifdef CONFIG_USB_TCPC | 622 | #ifdef CONFIG_USB_TCPC |
| 623 | ret = tcpc_setup_dfp_mode(&port1); | 623 | ret = tcpc_setup_dfp_mode(&port1); |
| 624 | #endif | 624 | #endif |
| 625 | return ret; | 625 | return ret; |
| 626 | } else if (index == 1 && init == USB_INIT_HOST) { | 626 | } else if (index == 1 && init == USB_INIT_HOST) { |
| 627 | /* Enable GPIO1_IO14 for 5V VBUS */ | 627 | /* Enable GPIO1_IO14 for 5V VBUS */ |
| 628 | gpio_request(USB2_PWR_EN, "usb2_pwr"); | 628 | gpio_request(USB2_PWR_EN, "usb2_pwr"); |
| 629 | gpio_direction_output(USB2_PWR_EN, 1); | 629 | gpio_direction_output(USB2_PWR_EN, 1); |
| 630 | } | 630 | } |
| 631 | 631 | ||
| 632 | return 0; | 632 | return 0; |
| 633 | } | 633 | } |
| 634 | 634 | ||
| 635 | int board_usb_cleanup(int index, enum usb_init_type init) | 635 | int board_usb_cleanup(int index, enum usb_init_type init) |
| 636 | { | 636 | { |
| 637 | int ret = 0; | 637 | int ret = 0; |
| 638 | if (index == 0 && init == USB_INIT_DEVICE) { | 638 | if (index == 0 && init == USB_INIT_DEVICE) { |
| 639 | dwc3_uboot_exit(index); | 639 | dwc3_uboot_exit(index); |
| 640 | } else if (index == 0 && init == USB_INIT_HOST) { | 640 | } else if (index == 0 && init == USB_INIT_HOST) { |
| 641 | #ifdef CONFIG_USB_TCPC | 641 | #ifdef CONFIG_USB_TCPC |
| 642 | ret = tcpc_disable_src_vbus(&port1); | 642 | ret = tcpc_disable_src_vbus(&port1); |
| 643 | #endif | 643 | #endif |
| 644 | } else if (index == 1 && init == USB_INIT_HOST) { | 644 | } else if (index == 1 && init == USB_INIT_HOST) { |
| 645 | /* Disable GPIO1_IO14 for 5V VBUS */ | 645 | /* Disable GPIO1_IO14 for 5V VBUS */ |
| 646 | gpio_direction_output(USB2_PWR_EN, 0); | 646 | gpio_direction_output(USB2_PWR_EN, 0); |
| 647 | } | 647 | } |
| 648 | 648 | ||
| 649 | imx8m_usb_power(index, false); | 649 | imx8m_usb_power(index, false); |
| 650 | 650 | ||
| 651 | return ret; | 651 | return ret; |
| 652 | } | 652 | } |
| 653 | 653 | ||
| 654 | #ifdef CONFIG_USB_TCPC | 654 | #ifdef CONFIG_USB_TCPC |
| 655 | /* Not used so far */ | 655 | /* Not used so far */ |
| 656 | int board_typec_get_mode(int index) | 656 | int board_typec_get_mode(int index) |
| 657 | { | 657 | { |
| 658 | int ret = 0; | 658 | int ret = 0; |
| 659 | enum typec_cc_polarity pol; | 659 | enum typec_cc_polarity pol; |
| 660 | enum typec_cc_state state; | 660 | enum typec_cc_state state; |
| 661 | 661 | ||
| 662 | if (index == 0) { | 662 | if (index == 0) { |
| 663 | tcpc_setup_ufp_mode(&port1); | 663 | tcpc_setup_ufp_mode(&port1); |
| 664 | 664 | ||
| 665 | ret = tcpc_get_cc_status(&port1, &pol, &state); | 665 | ret = tcpc_get_cc_status(&port1, &pol, &state); |
| 666 | if (!ret) { | 666 | if (!ret) { |
| 667 | if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD) | 667 | if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD) |
| 668 | return USB_INIT_HOST; | 668 | return USB_INIT_HOST; |
| 669 | } | 669 | } |
| 670 | 670 | ||
| 671 | return USB_INIT_DEVICE; | 671 | return USB_INIT_DEVICE; |
| 672 | } else { | 672 | } else { |
| 673 | return USB_INIT_HOST; | 673 | return USB_INIT_HOST; |
| 674 | } | 674 | } |
| 675 | } | 675 | } |
| 676 | #endif | 676 | #endif |
| 677 | #endif | 677 | #endif |
| 678 | 678 | ||
| 679 | #define FSL_SIP_GPC 0xC2000000 | 679 | #define FSL_SIP_GPC 0xC2000000 |
| 680 | #define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x3 | 680 | #define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x3 |
| 681 | #define DISPMIX 13 | 681 | #define DISPMIX 13 |
| 682 | #define MIPI 15 | 682 | #define MIPI 15 |
| 683 | 683 | ||
| 684 | int board_init(void) | 684 | int board_init(void) |
| 685 | { | 685 | { |
| 686 | setup_iomux_misc(); | 686 | setup_iomux_misc(); |
| 687 | setup_iomux_gpio(); | 687 | setup_iomux_gpio(); |
| 688 | setup_iomux_usb_en_oc(); | 688 | setup_iomux_usb_en_oc(); |
| 689 | #ifdef CONFIG_USB_TCPC | 689 | #ifdef CONFIG_USB_TCPC |
| 690 | setup_typec(); | 690 | setup_typec(); |
| 691 | #endif | 691 | #endif |
| 692 | 692 | ||
| 693 | #ifdef CONFIG_FEC_MXC | 693 | #ifdef CONFIG_FEC_MXC |
| 694 | setup_fec(); | 694 | setup_fec(); |
| 695 | #endif | 695 | #endif |
| 696 | 696 | ||
| 697 | #ifdef CONFIG_DWC_ETH_QOS | 697 | #ifdef CONFIG_DWC_ETH_QOS |
| 698 | /* clock, pin, gpr */ | 698 | /* clock, pin, gpr */ |
| 699 | setup_eqos(); | 699 | setup_eqos(); |
| 700 | #endif | 700 | #endif |
| 701 | 701 | ||
| 702 | #ifdef CONFIG_NAND_MXS | 702 | #ifdef CONFIG_NAND_MXS |
| 703 | setup_gpmi_nand(); | 703 | setup_gpmi_nand(); |
| 704 | #endif | 704 | #endif |
| 705 | 705 | ||
| 706 | #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) | 706 | #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) |
| 707 | init_usb_clk(); | 707 | init_usb_clk(); |
| 708 | #endif | 708 | #endif |
| 709 | 709 | ||
| 710 | /* enable the dispmix & mipi phy power domain */ | 710 | /* enable the dispmix & mipi phy power domain */ |
| 711 | call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, DISPMIX, true, 0); | 711 | call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, DISPMIX, true, 0); |
| 712 | call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, MIPI, true, 0); | 712 | call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, MIPI, true, 0); |
| 713 | 713 | ||
| 714 | return 0; | 714 | return 0; |
| 715 | } | 715 | } |
| 716 | 716 | ||
| 717 | int board_late_init(void) | 717 | int board_late_init(void) |
| 718 | { | 718 | { |
| 719 | /* Read Module Information from on module EEPROM and pass | 719 | /* Read Module Information from on module EEPROM and pass |
| 720 | * mac address to kernel | 720 | * mac address to kernel |
| 721 | */ | 721 | */ |
| 722 | struct udevice *dev; | 722 | struct udevice *dev; |
| 723 | int ret; | 723 | int ret; |
| 724 | u8 name[8]; | 724 | u8 name[8]; |
| 725 | u8 serial[12]; | 725 | u8 serial[12]; |
| 726 | u8 revision[4]; | 726 | u8 revision[4]; |
| 727 | u8 mac[6]; | 727 | u8 mac[6]; |
| 728 | u8 mac1[6]; | 728 | u8 mac1[6]; |
| 729 | 729 | ||
| 730 | ret = i2c_get_chip_for_busnum(2, 0x50, 2, &dev); | 730 | ret = i2c_get_chip_for_busnum(2, 0x50, 2, &dev); |
| 731 | if (ret) { | 731 | if (ret) { |
| 732 | debug("failed to get eeprom\n"); | 732 | debug("failed to get eeprom\n"); |
| 733 | return 0; | 733 | return 0; |
| 734 | } | 734 | } |
| 735 | 735 | ||
| 736 | /* Board ID */ | 736 | /* Board ID */ |
| 737 | ret = dm_i2c_read(dev, 0x4, name, 8); | 737 | ret = dm_i2c_read(dev, 0x4, name, 8); |
| 738 | if (ret) { | 738 | if (ret) { |
| 739 | debug("failed to read board ID from EEPROM\n"); | 739 | debug("failed to read board ID from EEPROM\n"); |
| 740 | return 0; | 740 | return 0; |
| 741 | } | 741 | } |
| 742 | puts("---------Embedian SMARC-iMX8MP------------\n"); | 742 | puts("---------Embedian SMARC-iMX8MP------------\n"); |
| 743 | printf(" Board ID: %c%c%c%c%c%c%c%c\n", | 743 | printf(" Board ID: %c%c%c%c%c%c%c%c\n", |
| 744 | name[0], name[1], name[2], name[3], name[4], name[5], name[6], name[7]); | 744 | name[0], name[1], name[2], name[3], name[4], name[5], name[6], name[7]); |
| 745 | 745 | ||
| 746 | /* Board Hardware Revision */ | 746 | /* Board Hardware Revision */ |
| 747 | ret = dm_i2c_read(dev, 0xc, revision, 4); | 747 | ret = dm_i2c_read(dev, 0xc, revision, 4); |
| 748 | if (ret) { | 748 | if (ret) { |
| 749 | debug("failed to read hardware revison from EEPROM\n"); | 749 | debug("failed to read hardware revison from EEPROM\n"); |
| 750 | return 0; | 750 | return 0; |
| 751 | } | 751 | } |
| 752 | printf(" Hardware Revision: %c%c%c%c\n", | 752 | printf(" Hardware Revision: %c%c%c%c\n", |
| 753 | revision[0], revision[1], revision[2], revision[3]); | 753 | revision[0], revision[1], revision[2], revision[3]); |
| 754 | 754 | ||
| 755 | /* Serial number */ | 755 | /* Serial number */ |
| 756 | ret = dm_i2c_read(dev, 0x10, serial, 12); | 756 | ret = dm_i2c_read(dev, 0x10, serial, 12); |
| 757 | if (ret) { | 757 | if (ret) { |
| 758 | debug("failed to read srial number from EEPROM\n"); | 758 | debug("failed to read srial number from EEPROM\n"); |
| 759 | return 0; | 759 | return 0; |
| 760 | } | 760 | } |
| 761 | printf(" Serial Number#: %c%c%c%c%c%c%c%c%c%c%c%c\n", | 761 | printf(" Serial Number#: %c%c%c%c%c%c%c%c%c%c%c%c\n", |
| 762 | serial[0], serial[1], serial[2], serial[3], serial[4], serial[5], serial[6], serial[7], serial[8], serial[9], serial[10], serial[11]); | 762 | serial[0], serial[1], serial[2], serial[3], serial[4], serial[5], serial[6], serial[7], serial[8], serial[9], serial[10], serial[11]); |
| 763 | 763 | ||
| 764 | /*MAC address */ | 764 | /*MAC address */ |
| 765 | ret = dm_i2c_read(dev, 0x3c, mac, 6); | 765 | ret = dm_i2c_read(dev, 0x3c, mac, 6); |
| 766 | if (ret) { | 766 | if (ret) { |
| 767 | debug("failed to read eth0 mac address from EEPROM\n"); | 767 | debug("failed to read eth0 mac address from EEPROM\n"); |
| 768 | return 0; | 768 | return 0; |
| 769 | } | 769 | } |
| 770 | 770 | ||
| 771 | if (is_valid_ethaddr(mac)) | 771 | if (is_valid_ethaddr(mac)) |
| 772 | printf(" MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n", | 772 | printf(" MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n", |
| 773 | mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); | 773 | mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); |
| 774 | eth_env_set_enetaddr("ethaddr", mac); | 774 | eth_env_set_enetaddr("ethaddr", mac); |
| 775 | 775 | ||
| 776 | /* MAC2 address */ | 776 | /* MAC2 address */ |
| 777 | ret = dm_i2c_read(dev, 0x42, mac1, 6); | 777 | ret = dm_i2c_read(dev, 0x42, mac1, 6); |
| 778 | if (ret) { | 778 | if (ret) { |
| 779 | debug("failed to read eth1 mac address from EEPROM\n"); | 779 | debug("failed to read eth1 mac address from EEPROM\n"); |
| 780 | return 0; | 780 | return 0; |
| 781 | } | 781 | } |
| 782 | 782 | ||
| 783 | if (is_valid_ethaddr(mac1)) | 783 | if (is_valid_ethaddr(mac1)) |
| 784 | printf(" MAC1 Address: %02x:%02x:%02x:%02x:%02x:%02x\n", | 784 | printf(" MAC1 Address: %02x:%02x:%02x:%02x:%02x:%02x\n", |
| 785 | mac1[0], mac1[1], mac1[2], mac1[3], mac1[4], mac1[5]); | 785 | mac1[0], mac1[1], mac1[2], mac1[3], mac1[4], mac1[5]); |
| 786 | eth_env_set_enetaddr("eth1addr", mac1); | 786 | eth_env_set_enetaddr("eth1addr", mac1); |
| 787 | puts("-----------------------------------------\n"); | 787 | puts("-----------------------------------------\n"); |
| 788 | 788 | ||
| 789 | #ifdef CONFIG_ENV_IS_IN_MMC | 789 | #ifdef CONFIG_ENV_IS_IN_MMC |
| 790 | board_late_mmc_env_init(); | 790 | board_late_mmc_env_init(); |
| 791 | #endif | 791 | #endif |
| 792 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG | 792 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
| 793 | env_set("board_name", "SMARC"); | 793 | env_set("board_name", "SMARC"); |
| 794 | env_set("board_rev", "iMX8MP"); | 794 | env_set("board_rev", "iMX8MP"); |
| 795 | #endif | 795 | #endif |
| 796 | 796 | ||
| 797 | if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 0)) { | 797 | if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 0)) { |
| 798 | puts("BOOT_SEL Detected: OFF OFF OFF, Boot from Carrier SATA is not supported...\n"); | 798 | puts("BOOT_SEL Detected: OFF OFF OFF, Boot from Carrier SATA is not supported...\n"); |
| 799 | hang(); | 799 | hang(); |
| 800 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 1)) { | 800 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 1)) { |
| 801 | puts("BOOT_SEL Detected: OFF OFF ON, Load Image from USB0...\n"); | 801 | puts("BOOT_SEL Detected: OFF OFF ON, Load Image from USB0...\n"); |
| 802 | env_set_ulong("usb dev", 1); | 802 | env_set_ulong("usb dev", 1); |
| 803 | env_set("bootcmd", "usb start; run loadusbbootenv; run importusbbootenv; run uenvcmd; loadusbimage; run usbboot;"); | 803 | env_set("bootcmd", "usb start; run loadusbbootenv; run importusbbootenv; run uenvcmd; loadusbimage; run usbboot;"); |
| 804 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 0)) { | 804 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 0)) { |
| 805 | puts("BOOT_SEL Detected: OFF ON OFF, Boot from Carrier eSPI is not supported...\n"); | 805 | puts("BOOT_SEL Detected: OFF ON OFF, Boot from Carrier eSPI is not supported...\n"); |
| 806 | hang(); | 806 | hang(); |
| 807 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 0)) { | 807 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 0)) { |
| 808 | puts("BOOT_SEL Detected: ON OFF OFF, Load Image from Carrier SD Card...\n"); | 808 | puts("BOOT_SEL Detected: ON OFF OFF, Load Image from Carrier SD Card...\n"); |
| 809 | env_set_ulong("mmcdev", 1); | 809 | env_set_ulong("mmcdev", 1); |
| 810 | env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;"); | 810 | env_set("bootcmd", "i2c dev 0; i2c mw 0x25 0x0a 0x3; mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;"); |
| 811 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 1)) { | 811 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 1)) { |
| 812 | puts("BOOT_SEL Detected: OFF ON ON, Load Image from Module eMMC Flash...\n"); | 812 | puts("BOOT_SEL Detected: OFF ON ON, Load Image from Module eMMC Flash...\n"); |
| 813 | env_set_ulong("mmcdev", 2); | 813 | env_set_ulong("mmcdev", 2); |
| 814 | env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;"); | 814 | env_set("bootcmd", "i2c dev 0; i2c mw 0x25 0x0a 0x3; mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;"); |
| 815 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 1)) { | 815 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 1)) { |
| 816 | puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n"); | 816 | puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n"); |
| 817 | env_set("bootcmd", "run netboot;"); | 817 | env_set("bootcmd", "run netboot;"); |
| 818 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 0)) { | 818 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 0)) { |
| 819 | puts("Carrier SPI Boot is not supported...\n"); | 819 | puts("Carrier SPI Boot is not supported...\n"); |
| 820 | hang(); | 820 | hang(); |
| 821 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 1)) { | 821 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 7)) == 1)) { |
| 822 | puts("BOOT_SEL Detected: ON ON ON, Boot from Module SPI is not supported...\n"); | 822 | puts("BOOT_SEL Detected: ON ON ON, Boot from Module SPI is not supported...\n"); |
| 823 | hang(); | 823 | hang(); |
| 824 | } else { | 824 | } else { |
| 825 | puts("unsupported boot devices\n"); | 825 | puts("unsupported boot devices\n"); |
| 826 | hang(); | 826 | hang(); |
| 827 | } | 827 | } |
| 828 | 828 | ||
| 829 | return 0; | 829 | return 0; |
| 830 | } | 830 | } |
| 831 | 831 | ||
| 832 | #ifdef CONFIG_IMX_BOOTAUX | 832 | #ifdef CONFIG_IMX_BOOTAUX |
| 833 | ulong board_get_usable_ram_top(ulong total_size) | 833 | ulong board_get_usable_ram_top(ulong total_size) |
| 834 | { | 834 | { |
| 835 | /* Reserve 16M memory used by M core vring/buffer, which begins at 16MB before optee */ | 835 | /* Reserve 16M memory used by M core vring/buffer, which begins at 16MB before optee */ |
| 836 | if (rom_pointer[1]) | 836 | if (rom_pointer[1]) |
| 837 | return gd->ram_top - SZ_16M; | 837 | return gd->ram_top - SZ_16M; |
| 838 | 838 | ||
| 839 | return gd->ram_top; | 839 | return gd->ram_top; |
| 840 | } | 840 | } |
| 841 | #endif | 841 | #endif |
| 842 | 842 | ||
| 843 | #ifdef CONFIG_FSL_FASTBOOT | 843 | #ifdef CONFIG_FSL_FASTBOOT |
| 844 | #ifdef CONFIG_ANDROID_RECOVERY | 844 | #ifdef CONFIG_ANDROID_RECOVERY |
| 845 | 845 | ||
| 846 | int is_recovery_key_pressing(void) | 846 | int is_recovery_key_pressing(void) |
| 847 | { | 847 | { |
| 848 | return 0; /*TODO*/ | 848 | return 0; /*TODO*/ |
| 849 | } | 849 | } |
| 850 | #endif /*CONFIG_ANDROID_RECOVERY*/ | 850 | #endif /*CONFIG_ANDROID_RECOVERY*/ |
| 851 | #endif /*CONFIG_FSL_FASTBOOT*/ | 851 | #endif /*CONFIG_FSL_FASTBOOT*/ |
| 852 | 852 | ||
| 853 | #ifdef CONFIG_ANDROID_SUPPORT | 853 | #ifdef CONFIG_ANDROID_SUPPORT |
| 854 | bool is_power_key_pressed(void) { | 854 | bool is_power_key_pressed(void) { |
| 855 | return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6))); | 855 | return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6))); |
| 856 | } | 856 | } |
| 857 | #endif | 857 | #endif |
| 858 | 858 | ||
| 859 | #ifdef CONFIG_SPL_MMC_SUPPORT | 859 | #ifdef CONFIG_SPL_MMC_SUPPORT |
| 860 | 860 | ||
| 861 | #define UBOOT_RAW_SECTOR_OFFSET 0x40 | 861 | #define UBOOT_RAW_SECTOR_OFFSET 0x40 |
| 862 | unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc) | 862 | unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc) |
| 863 | { | 863 | { |
| 864 | u32 boot_dev = spl_boot_device(); | 864 | u32 boot_dev = spl_boot_device(); |
| 865 | switch (boot_dev) { | 865 | switch (boot_dev) { |
| 866 | case BOOT_DEVICE_MMC2: | 866 | case BOOT_DEVICE_MMC2: |
| 867 | return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET; | 867 | return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET; |
| 868 | default: | 868 | default: |
| 869 | return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; | 869 | return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; |
| 870 | } | 870 | } |
| 871 | } | 871 | } |
| 872 | #endif | 872 | #endif |
| 873 | 873 |
configs/smarcimx8mp_4g_ser0_android_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_SYS_ICACHE_OFF=y | 2 | CONFIG_SPL_SYS_ICACHE_OFF=y |
| 3 | CONFIG_SPL_SYS_DCACHE_OFF=y | 3 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| 4 | CONFIG_ARCH_IMX8M=y | 4 | CONFIG_ARCH_IMX8M=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x40200000 | 5 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| 6 | CONFIG_SPL_GPIO_SUPPORT=y | 6 | CONFIG_SPL_GPIO_SUPPORT=y |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y | 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 10 | CONFIG_SYS_I2C_MXC_I2C1=y | 10 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 11 | CONFIG_SYS_I2C_MXC_I2C2=y | 11 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C3=y | 12 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 13 | CONFIG_SYS_I2C_MXC_I2C4=y | 13 | CONFIG_SYS_I2C_MXC_I2C4=y |
| 14 | CONFIG_SYS_I2C_MXC_I2C6=y | 14 | CONFIG_SYS_I2C_MXC_I2C6=y |
| 15 | CONFIG_ENV_SIZE=0x1000 | 15 | CONFIG_ENV_SIZE=0x1000 |
| 16 | CONFIG_ENV_OFFSET=0x400000 | 16 | CONFIG_ENV_OFFSET=0x400000 |
| 17 | CONFIG_ENV_SECT_SIZE=0x10000 | 17 | CONFIG_ENV_SECT_SIZE=0x10000 |
| 18 | CONFIG_DM_GPIO=y | 18 | CONFIG_DM_GPIO=y |
| 19 | CONFIG_BOOTDELAY=1 | 19 | CONFIG_BOOTDELAY=1 |
| 20 | CONFIG_TARGET_SMARCIMX8MP=y | 20 | CONFIG_TARGET_SMARCIMX8MP=y |
| 21 | CONFIG_ARCH_MISC_INIT=y | 21 | CONFIG_ARCH_MISC_INIT=y |
| 22 | CONFIG_SPL_SERIAL_SUPPORT=y | 22 | CONFIG_SPL_SERIAL_SUPPORT=y |
| 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 24 | CONFIG_SPL=y | 24 | CONFIG_SPL=y |
| 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 26 | CONFIG_CSF_SIZE=0x2000 | 26 | CONFIG_CSF_SIZE=0x2000 |
| 27 | CONFIG_SPL_TEXT_BASE=0x920000 | 27 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 28 | CONFIG_FIT=y | 28 | CONFIG_FIT=y |
| 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 30 | CONFIG_SPL_LOAD_FIT=y | 30 | CONFIG_SPL_LOAD_FIT=y |
| 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" |
| 32 | CONFIG_OF_SYSTEM_SETUP=y | 32 | CONFIG_OF_SYSTEM_SETUP=y |
| 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,4GB_LPDDR4" | 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,4GB_LPDDR4" |
| 34 | CONFIG_CONSOLE_SER0=y | 34 | CONFIG_CONSOLE_SER0=y |
| 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" | 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" |
| 36 | CONFIG_BOARD_LATE_INIT=y | 36 | CONFIG_BOARD_LATE_INIT=y |
| 37 | CONFIG_BOARD_EARLY_INIT_F=y | 37 | CONFIG_BOARD_EARLY_INIT_F=y |
| 38 | CONFIG_SPL_BOARD_INIT=y | 38 | CONFIG_SPL_BOARD_INIT=y |
| 39 | CONFIG_SPL_SEPARATE_BSS=y | 39 | CONFIG_SPL_SEPARATE_BSS=y |
| 40 | CONFIG_SPL_I2C_SUPPORT=y | 40 | CONFIG_SPL_I2C_SUPPORT=y |
| 41 | CONFIG_SPL_POWER_SUPPORT=y | 41 | CONFIG_SPL_POWER_SUPPORT=y |
| 42 | CONFIG_NR_DRAM_BANKS=3 | 42 | CONFIG_NR_DRAM_BANKS=3 |
| 43 | CONFIG_HUSH_PARSER=y | 43 | CONFIG_HUSH_PARSER=y |
| 44 | CONFIG_SYS_PROMPT="u-boot$ " | 44 | CONFIG_SYS_PROMPT="u-boot$ " |
| 45 | # CONFIG_CMD_EXPORTENV is not set | 45 | # CONFIG_CMD_EXPORTENV is not set |
| 46 | CONFIG_CMD_IMPORTENV=y | 46 | CONFIG_CMD_IMPORTENV=y |
| 47 | CONFIG_CMD_ERASEENV=y | 47 | CONFIG_CMD_ERASEENV=y |
| 48 | # CONFIG_CMD_CRC32 is not set | 48 | # CONFIG_CMD_CRC32 is not set |
| 49 | # CONFIG_BOOTM_NETBSD is not set | 49 | # CONFIG_BOOTM_NETBSD is not set |
| 50 | CONFIG_CMD_CLK=y | 50 | CONFIG_CMD_CLK=y |
| 51 | CONFIG_CMD_FUSE=y | 51 | CONFIG_CMD_FUSE=y |
| 52 | CONFIG_CMD_GPIO=y | 52 | CONFIG_CMD_GPIO=y |
| 53 | CONFIG_CMD_I2C=y | 53 | CONFIG_CMD_I2C=y |
| 54 | CONFIG_CMD_MMC=y | 54 | CONFIG_CMD_MMC=y |
| 55 | CONFIG_CMD_DHCP=y | 55 | CONFIG_CMD_DHCP=y |
| 56 | CONFIG_CMD_MII=y | 56 | CONFIG_CMD_MII=y |
| 57 | CONFIG_CMD_PING=y | 57 | CONFIG_CMD_PING=y |
| 58 | CONFIG_CMD_CACHE=y | 58 | CONFIG_CMD_CACHE=y |
| 59 | CONFIG_CMD_REGULATOR=y | 59 | CONFIG_CMD_REGULATOR=y |
| 60 | CONFIG_CMD_MEMTEST=y | 60 | CONFIG_CMD_MEMTEST=y |
| 61 | CONFIG_CMD_EXT2=y | 61 | CONFIG_CMD_EXT2=y |
| 62 | CONFIG_CMD_EXT4=y | 62 | CONFIG_CMD_EXT4=y |
| 63 | CONFIG_CMD_EXT4_WRITE=y | 63 | CONFIG_CMD_EXT4_WRITE=y |
| 64 | CONFIG_CMD_FAT=y | 64 | CONFIG_CMD_FAT=y |
| 65 | CONFIG_CMD_SF=y | 65 | CONFIG_CMD_SF=y |
| 66 | CONFIG_CMD_LED=y | 66 | CONFIG_CMD_LED=y |
| 67 | CONFIG_OF_CONTROL=y | 67 | CONFIG_OF_CONTROL=y |
| 68 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" | 68 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" |
| 69 | CONFIG_ENV_IS_IN_MMC=y | 69 | CONFIG_ENV_IS_IN_MMC=y |
| 70 | CONFIG_ENV_IS_IN_SPI_FLASH=y | 70 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 71 | CONFIG_ENV_IS_NOWHERE=y | 71 | CONFIG_ENV_IS_NOWHERE=y |
| 72 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | 72 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 73 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | 73 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 74 | CONFIG_CLK_COMPOSITE_CCF=y | 74 | CONFIG_CLK_COMPOSITE_CCF=y |
| 75 | CONFIG_CLK_IMX8MP=y | 75 | CONFIG_CLK_IMX8MP=y |
| 76 | CONFIG_MXC_GPIO=y | 76 | CONFIG_MXC_GPIO=y |
| 77 | CONFIG_DM_PCA953X=y | 77 | CONFIG_DM_PCA953X=y |
| 78 | CONFIG_FASTBOOT=y | 78 | CONFIG_FASTBOOT=y |
| 79 | CONFIG_USB_FUNCTION_FASTBOOT=y | 79 | CONFIG_USB_FUNCTION_FASTBOOT=y |
| 80 | CONFIG_CMD_FASTBOOT=y | 80 | CONFIG_CMD_FASTBOOT=y |
| 81 | CONFIG_ANDROID_BOOT_IMAGE=y | 81 | CONFIG_ANDROID_BOOT_IMAGE=y |
| 82 | CONFIG_FASTBOOT_UUU_SUPPORT=n | 82 | CONFIG_FASTBOOT_UUU_SUPPORT=n |
| 83 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 83 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
| 84 | CONFIG_FASTBOOT_BUF_SIZE=0xc800000 | 84 | CONFIG_FASTBOOT_BUF_SIZE=0xc800000 |
| 85 | CONFIG_FASTBOOT_FLASH=y | 85 | CONFIG_FASTBOOT_FLASH=y |
| 86 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 | 86 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
| 87 | CONFIG_DM_I2C=y | 87 | CONFIG_DM_I2C=y |
| 88 | CONFIG_CMD_GPT=y | 88 | CONFIG_CMD_GPT=y |
| 89 | CONFIG_CMD_TIME=y | 89 | CONFIG_CMD_TIME=y |
| 90 | CONFIG_SYS_I2C_MXC=y | 90 | CONFIG_SYS_I2C_MXC=y |
| 91 | CONFIG_LED=y | 91 | CONFIG_LED=y |
| 92 | CONFIG_LED_GPIO=y | 92 | CONFIG_LED_GPIO=y |
| 93 | CONFIG_DM_MMC=y | 93 | CONFIG_DM_MMC=y |
| 94 | CONFIG_MMC_IO_VOLTAGE=y | 94 | # CONFIG_MMC_IO_VOLTAGE is not set |
| 95 | CONFIG_MMC_UHS_SUPPORT=y | 95 | CONFIG_MMC_UHS_SUPPORT=y |
| 96 | CONFIG_MMC_HS400_SUPPORT=y | 96 | CONFIG_MMC_HS400_SUPPORT=y |
| 97 | CONFIG_MMC_HS400_ES_SUPPORT=y | 97 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 98 | CONFIG_EFI_PARTITION=y | 98 | CONFIG_EFI_PARTITION=y |
| 99 | CONFIG_SUPPORT_EMMC_BOOT=y | 99 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 100 | CONFIG_FSL_ESDHC_IMX=y | 100 | CONFIG_FSL_ESDHC_IMX=y |
| 101 | CONFIG_DM_SPI_FLASH=y | 101 | CONFIG_DM_SPI_FLASH=y |
| 102 | CONFIG_DM_SPI=y | 102 | CONFIG_DM_SPI=y |
| 103 | CONFIG_FSL_FSPI=y | 103 | CONFIG_FSL_FSPI=y |
| 104 | CONFIG_SPI=y | 104 | CONFIG_SPI=y |
| 105 | CONFIG_SPI_FLASH=y | 105 | CONFIG_SPI_FLASH=y |
| 106 | CONFIG_SPI_FLASH_BAR=y | 106 | CONFIG_SPI_FLASH_BAR=y |
| 107 | CONFIG_SPI_FLASH_MACRONIX=y | 107 | CONFIG_SPI_FLASH_MACRONIX=y |
| 108 | CONFIG_SF_DEFAULT_BUS=0 | 108 | CONFIG_SF_DEFAULT_BUS=0 |
| 109 | CONFIG_SF_DEFAULT_CS=0 | 109 | CONFIG_SF_DEFAULT_CS=0 |
| 110 | CONFIG_SF_DEFAULT_SPEED=40000000 | 110 | CONFIG_SF_DEFAULT_SPEED=40000000 |
| 111 | CONFIG_SF_DEFAULT_MODE=0 | 111 | CONFIG_SF_DEFAULT_MODE=0 |
| 112 | 112 | ||
| 113 | CONFIG_DM_ETH=y | 113 | CONFIG_DM_ETH=y |
| 114 | # CONFIG_DM_ETH_PHY=y | 114 | # CONFIG_DM_ETH_PHY=y |
| 115 | CONFIG_DWC_ETH_QOS=y | 115 | CONFIG_DWC_ETH_QOS=y |
| 116 | 116 | ||
| 117 | CONFIG_PHY_GIGE=y | 117 | CONFIG_PHY_GIGE=y |
| 118 | CONFIG_FEC_MXC=y | 118 | CONFIG_FEC_MXC=y |
| 119 | CONFIG_MII=y | 119 | CONFIG_MII=y |
| 120 | CONFIG_PHYLIB=y | 120 | CONFIG_PHYLIB=y |
| 121 | CONFIG_PHY_ATHEROS=y | 121 | CONFIG_PHY_ATHEROS=y |
| 122 | 122 | ||
| 123 | CONFIG_PINCTRL=y | 123 | CONFIG_PINCTRL=y |
| 124 | CONFIG_PINCTRL_IMX8M=y | 124 | CONFIG_PINCTRL_IMX8M=y |
| 125 | CONFIG_DM_REGULATOR=y | 125 | CONFIG_DM_REGULATOR=y |
| 126 | CONFIG_DM_REGULATOR_FIXED=y | 126 | CONFIG_DM_REGULATOR_FIXED=y |
| 127 | CONFIG_DM_REGULATOR_GPIO=y | 127 | CONFIG_DM_REGULATOR_GPIO=y |
| 128 | CONFIG_MXC_UART=y | 128 | CONFIG_MXC_UART=y |
| 129 | CONFIG_SYSRESET=y | 129 | CONFIG_SYSRESET=y |
| 130 | CONFIG_SYSRESET_PSCI=y | 130 | CONFIG_SYSRESET_PSCI=y |
| 131 | CONFIG_DM_THERMAL=y | 131 | CONFIG_DM_THERMAL=y |
| 132 | CONFIG_NXP_TMU=y | 132 | CONFIG_NXP_TMU=y |
| 133 | CONFIG_USB=y | 133 | CONFIG_USB=y |
| 134 | CONFIG_USB_GADGET=y | 134 | CONFIG_USB_GADGET=y |
| 135 | CONFIG_DM_USB=y | 135 | CONFIG_DM_USB=y |
| 136 | 136 | ||
| 137 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 137 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
| 138 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 138 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
| 139 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 139 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
| 140 | CONFIG_USB_GADGET_DOWNLOAD=y | 140 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 141 | CONFIG_USB_XHCI_HCD=y | 141 | CONFIG_USB_XHCI_HCD=y |
| 142 | CONFIG_USB_XHCI_IMX8M=y | 142 | CONFIG_USB_XHCI_IMX8M=y |
| 143 | CONFIG_USB_XHCI_DWC3=y | 143 | CONFIG_USB_XHCI_DWC3=y |
| 144 | CONFIG_USB_DWC3=y | 144 | CONFIG_USB_DWC3=y |
| 145 | CONFIG_USB_DWC3_GADGET=y | 145 | CONFIG_USB_DWC3_GADGET=y |
| 146 | 146 | ||
| 147 | CONFIG_OF_BOARD_SETUP=y | 147 | CONFIG_OF_BOARD_SETUP=y |
| 148 | 148 | ||
| 149 | CONFIG_REGMAP=y | 149 | CONFIG_REGMAP=y |
| 150 | CONFIG_SYSCON=y | 150 | CONFIG_SYSCON=y |
| 151 | CONFIG_VIDEO_IMX_LCDIFV3=y | 151 | CONFIG_VIDEO_IMX_LCDIFV3=y |
| 152 | CONFIG_DM_VIDEO=y | 152 | CONFIG_DM_VIDEO=y |
| 153 | CONFIG_SYS_WHITE_ON_BLACK=y | 153 | CONFIG_SYS_WHITE_ON_BLACK=y |
| 154 | 154 | ||
| 155 | CONFIG_LZ4=y | 155 | CONFIG_LZ4=y |
| 156 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y | 156 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y |
| 157 | CONFIG_APPEND_BOOTARGS=y | 157 | CONFIG_APPEND_BOOTARGS=y |
| 158 | CONFIG_SPL_MMC_SUPPORT=y | 158 | CONFIG_SPL_MMC_SUPPORT=y |
| 159 | CONFIG_AVB_WARNING_LOGO=y | 159 | CONFIG_AVB_WARNING_LOGO=y |
| 160 | CONFIG_AVB_WARNING_LOGO_COLS=0x320 | 160 | CONFIG_AVB_WARNING_LOGO_COLS=0x320 |
| 161 | CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 | 161 | CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 |
| 162 | CONFIG_VIRTUAL_AB_SUPPORT=y | 162 | CONFIG_VIRTUAL_AB_SUPPORT=y |
| 163 | CONFIG_ANDROID_SUPPORT=y | 163 | CONFIG_ANDROID_SUPPORT=y |
| 164 | CONFIG_APPEND_BOOTARGS=y | 164 | CONFIG_APPEND_BOOTARGS=y |
| 165 | CONFIG_ANDROID_AB_SUPPORT=y | 165 | CONFIG_ANDROID_AB_SUPPORT=y |
| 166 | 166 |
configs/smarcimx8mp_4g_ser0_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_SYS_ICACHE_OFF=y | 2 | CONFIG_SPL_SYS_ICACHE_OFF=y |
| 3 | CONFIG_SPL_SYS_DCACHE_OFF=y | 3 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| 4 | CONFIG_ARCH_IMX8M=y | 4 | CONFIG_ARCH_IMX8M=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x40200000 | 5 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| 6 | CONFIG_SPL_GPIO_SUPPORT=y | 6 | CONFIG_SPL_GPIO_SUPPORT=y |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y | 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 10 | CONFIG_SYS_I2C_MXC_I2C1=y | 10 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 11 | CONFIG_SYS_I2C_MXC_I2C2=y | 11 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C3=y | 12 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 13 | CONFIG_SYS_I2C_MXC_I2C4=y | 13 | CONFIG_SYS_I2C_MXC_I2C4=y |
| 14 | CONFIG_SYS_I2C_MXC_I2C6=y | 14 | CONFIG_SYS_I2C_MXC_I2C6=y |
| 15 | CONFIG_ENV_SIZE=0x1000 | 15 | CONFIG_ENV_SIZE=0x1000 |
| 16 | CONFIG_ENV_OFFSET=0x400000 | 16 | CONFIG_ENV_OFFSET=0x400000 |
| 17 | CONFIG_ENV_SECT_SIZE=0x10000 | 17 | CONFIG_ENV_SECT_SIZE=0x10000 |
| 18 | CONFIG_DM_GPIO=y | 18 | CONFIG_DM_GPIO=y |
| 19 | CONFIG_BOOTDELAY=1 | 19 | CONFIG_BOOTDELAY=1 |
| 20 | CONFIG_TARGET_SMARCIMX8MP=y | 20 | CONFIG_TARGET_SMARCIMX8MP=y |
| 21 | CONFIG_ARCH_MISC_INIT=y | 21 | CONFIG_ARCH_MISC_INIT=y |
| 22 | CONFIG_SPL_SERIAL_SUPPORT=y | 22 | CONFIG_SPL_SERIAL_SUPPORT=y |
| 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 24 | CONFIG_SPL=y | 24 | CONFIG_SPL=y |
| 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 26 | CONFIG_CSF_SIZE=0x2000 | 26 | CONFIG_CSF_SIZE=0x2000 |
| 27 | CONFIG_SPL_TEXT_BASE=0x920000 | 27 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 28 | CONFIG_FIT=y | 28 | CONFIG_FIT=y |
| 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 30 | CONFIG_SPL_LOAD_FIT=y | 30 | CONFIG_SPL_LOAD_FIT=y |
| 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" |
| 32 | CONFIG_OF_SYSTEM_SETUP=y | 32 | CONFIG_OF_SYSTEM_SETUP=y |
| 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,4GB_LPDDR4" | 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,4GB_LPDDR4" |
| 34 | CONFIG_CONSOLE_SER0=y | 34 | CONFIG_CONSOLE_SER0=y |
| 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" | 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" |
| 36 | CONFIG_BOARD_LATE_INIT=y | 36 | CONFIG_BOARD_LATE_INIT=y |
| 37 | CONFIG_BOARD_EARLY_INIT_F=y | 37 | CONFIG_BOARD_EARLY_INIT_F=y |
| 38 | CONFIG_SPL_BOARD_INIT=y | 38 | CONFIG_SPL_BOARD_INIT=y |
| 39 | CONFIG_SPL_BOOTROM_SUPPORT=y | 39 | CONFIG_SPL_BOOTROM_SUPPORT=y |
| 40 | CONFIG_SPL_SEPARATE_BSS=y | 40 | CONFIG_SPL_SEPARATE_BSS=y |
| 41 | CONFIG_SPL_I2C_SUPPORT=y | 41 | CONFIG_SPL_I2C_SUPPORT=y |
| 42 | CONFIG_SPL_POWER_SUPPORT=y | 42 | CONFIG_SPL_POWER_SUPPORT=y |
| 43 | CONFIG_NR_DRAM_BANKS=3 | 43 | CONFIG_NR_DRAM_BANKS=3 |
| 44 | CONFIG_HUSH_PARSER=y | 44 | CONFIG_HUSH_PARSER=y |
| 45 | CONFIG_SYS_PROMPT="u-boot$ " | 45 | CONFIG_SYS_PROMPT="u-boot$ " |
| 46 | # CONFIG_CMD_EXPORTENV is not set | 46 | # CONFIG_CMD_EXPORTENV is not set |
| 47 | CONFIG_CMD_IMPORTENV=y | 47 | CONFIG_CMD_IMPORTENV=y |
| 48 | CONFIG_CMD_ERASEENV=y | 48 | CONFIG_CMD_ERASEENV=y |
| 49 | # CONFIG_CMD_CRC32 is not set | 49 | # CONFIG_CMD_CRC32 is not set |
| 50 | # CONFIG_BOOTM_NETBSD is not set | 50 | # CONFIG_BOOTM_NETBSD is not set |
| 51 | CONFIG_CMD_CLK=y | 51 | CONFIG_CMD_CLK=y |
| 52 | CONFIG_CMD_FUSE=y | 52 | CONFIG_CMD_FUSE=y |
| 53 | CONFIG_CMD_GPIO=y | 53 | CONFIG_CMD_GPIO=y |
| 54 | CONFIG_CMD_I2C=y | 54 | CONFIG_CMD_I2C=y |
| 55 | CONFIG_CMD_MMC=y | 55 | CONFIG_CMD_MMC=y |
| 56 | CONFIG_CMD_DHCP=y | 56 | CONFIG_CMD_DHCP=y |
| 57 | CONFIG_CMD_MII=y | 57 | CONFIG_CMD_MII=y |
| 58 | CONFIG_CMD_PING=y | 58 | CONFIG_CMD_PING=y |
| 59 | CONFIG_CMD_CACHE=y | 59 | CONFIG_CMD_CACHE=y |
| 60 | CONFIG_CMD_REGULATOR=y | 60 | CONFIG_CMD_REGULATOR=y |
| 61 | CONFIG_CMD_MEMTEST=y | 61 | CONFIG_CMD_MEMTEST=y |
| 62 | CONFIG_CMD_EXT2=y | 62 | CONFIG_CMD_EXT2=y |
| 63 | CONFIG_CMD_EXT4=y | 63 | CONFIG_CMD_EXT4=y |
| 64 | CONFIG_CMD_EXT4_WRITE=y | 64 | CONFIG_CMD_EXT4_WRITE=y |
| 65 | CONFIG_CMD_FAT=y | 65 | CONFIG_CMD_FAT=y |
| 66 | CONFIG_CMD_SF=y | 66 | CONFIG_CMD_SF=y |
| 67 | CONFIG_CMD_LED=y | 67 | CONFIG_CMD_LED=y |
| 68 | CONFIG_OF_CONTROL=y | 68 | CONFIG_OF_CONTROL=y |
| 69 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" | 69 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" |
| 70 | CONFIG_ENV_IS_IN_MMC=y | 70 | CONFIG_ENV_IS_IN_MMC=y |
| 71 | CONFIG_ENV_IS_IN_SPI_FLASH=y | 71 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 72 | CONFIG_ENV_IS_NOWHERE=y | 72 | CONFIG_ENV_IS_NOWHERE=y |
| 73 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | 73 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 74 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | 74 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 75 | CONFIG_CLK_COMPOSITE_CCF=y | 75 | CONFIG_CLK_COMPOSITE_CCF=y |
| 76 | CONFIG_CLK_IMX8MP=y | 76 | CONFIG_CLK_IMX8MP=y |
| 77 | CONFIG_MXC_GPIO=y | 77 | CONFIG_MXC_GPIO=y |
| 78 | CONFIG_DM_PCA953X=y | 78 | CONFIG_DM_PCA953X=y |
| 79 | CONFIG_FASTBOOT=y | 79 | CONFIG_FASTBOOT=y |
| 80 | CONFIG_USB_FUNCTION_FASTBOOT=y | 80 | CONFIG_USB_FUNCTION_FASTBOOT=y |
| 81 | CONFIG_CMD_FASTBOOT=y | 81 | CONFIG_CMD_FASTBOOT=y |
| 82 | CONFIG_ANDROID_BOOT_IMAGE=y | 82 | CONFIG_ANDROID_BOOT_IMAGE=y |
| 83 | CONFIG_FASTBOOT_UUU_SUPPORT=y | 83 | CONFIG_FASTBOOT_UUU_SUPPORT=y |
| 84 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 84 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
| 85 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 85 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
| 86 | CONFIG_FASTBOOT_FLASH=y | 86 | CONFIG_FASTBOOT_FLASH=y |
| 87 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 | 87 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
| 88 | CONFIG_DM_I2C=y | 88 | CONFIG_DM_I2C=y |
| 89 | CONFIG_CMD_GPT=y | 89 | CONFIG_CMD_GPT=y |
| 90 | CONFIG_CMD_TIME=y | 90 | CONFIG_CMD_TIME=y |
| 91 | CONFIG_SYS_I2C_MXC=y | 91 | CONFIG_SYS_I2C_MXC=y |
| 92 | CONFIG_LED=y | 92 | CONFIG_LED=y |
| 93 | CONFIG_LED_GPIO=y | 93 | CONFIG_LED_GPIO=y |
| 94 | CONFIG_DM_MMC=y | 94 | CONFIG_DM_MMC=y |
| 95 | CONFIG_MMC_IO_VOLTAGE=y | 95 | # CONFIG_MMC_IO_VOLTAGE is not set |
| 96 | CONFIG_MMC_UHS_SUPPORT=y | 96 | CONFIG_MMC_UHS_SUPPORT=y |
| 97 | CONFIG_MMC_HS400_SUPPORT=y | 97 | CONFIG_MMC_HS400_SUPPORT=y |
| 98 | CONFIG_MMC_HS400_ES_SUPPORT=y | 98 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 99 | CONFIG_EFI_PARTITION=y | 99 | CONFIG_EFI_PARTITION=y |
| 100 | CONFIG_SUPPORT_EMMC_BOOT=y | 100 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 101 | CONFIG_FSL_ESDHC_IMX=y | 101 | CONFIG_FSL_ESDHC_IMX=y |
| 102 | CONFIG_DM_SPI_FLASH=y | 102 | CONFIG_DM_SPI_FLASH=y |
| 103 | CONFIG_DM_SPI=y | 103 | CONFIG_DM_SPI=y |
| 104 | CONFIG_FSL_FSPI=y | 104 | CONFIG_FSL_FSPI=y |
| 105 | CONFIG_SPI=y | 105 | CONFIG_SPI=y |
| 106 | CONFIG_SPI_FLASH=y | 106 | CONFIG_SPI_FLASH=y |
| 107 | CONFIG_SPI_FLASH_BAR=y | 107 | CONFIG_SPI_FLASH_BAR=y |
| 108 | CONFIG_SPI_FLASH_MACRONIX=y | 108 | CONFIG_SPI_FLASH_MACRONIX=y |
| 109 | CONFIG_SF_DEFAULT_BUS=0 | 109 | CONFIG_SF_DEFAULT_BUS=0 |
| 110 | CONFIG_SF_DEFAULT_CS=0 | 110 | CONFIG_SF_DEFAULT_CS=0 |
| 111 | CONFIG_SF_DEFAULT_SPEED=40000000 | 111 | CONFIG_SF_DEFAULT_SPEED=40000000 |
| 112 | CONFIG_SF_DEFAULT_MODE=0 | 112 | CONFIG_SF_DEFAULT_MODE=0 |
| 113 | 113 | ||
| 114 | CONFIG_DM_ETH=y | 114 | CONFIG_DM_ETH=y |
| 115 | # CONFIG_DM_ETH_PHY=y | 115 | # CONFIG_DM_ETH_PHY=y |
| 116 | CONFIG_DWC_ETH_QOS=y | 116 | CONFIG_DWC_ETH_QOS=y |
| 117 | 117 | ||
| 118 | CONFIG_PHY_GIGE=y | 118 | CONFIG_PHY_GIGE=y |
| 119 | CONFIG_FEC_MXC=y | 119 | CONFIG_FEC_MXC=y |
| 120 | CONFIG_MII=y | 120 | CONFIG_MII=y |
| 121 | CONFIG_PHYLIB=y | 121 | CONFIG_PHYLIB=y |
| 122 | CONFIG_PHY_ATHEROS=y | 122 | CONFIG_PHY_ATHEROS=y |
| 123 | 123 | ||
| 124 | CONFIG_PINCTRL=y | 124 | CONFIG_PINCTRL=y |
| 125 | CONFIG_PINCTRL_IMX8M=y | 125 | CONFIG_PINCTRL_IMX8M=y |
| 126 | CONFIG_DM_REGULATOR=y | 126 | CONFIG_DM_REGULATOR=y |
| 127 | CONFIG_DM_REGULATOR_FIXED=y | 127 | CONFIG_DM_REGULATOR_FIXED=y |
| 128 | CONFIG_DM_REGULATOR_GPIO=y | 128 | CONFIG_DM_REGULATOR_GPIO=y |
| 129 | CONFIG_MXC_UART=y | 129 | CONFIG_MXC_UART=y |
| 130 | CONFIG_SYSRESET=y | 130 | CONFIG_SYSRESET=y |
| 131 | CONFIG_SYSRESET_PSCI=y | 131 | CONFIG_SYSRESET_PSCI=y |
| 132 | CONFIG_DM_THERMAL=y | 132 | CONFIG_DM_THERMAL=y |
| 133 | CONFIG_NXP_TMU=y | 133 | CONFIG_NXP_TMU=y |
| 134 | CONFIG_USB=y | 134 | CONFIG_USB=y |
| 135 | CONFIG_USB_GADGET=y | 135 | CONFIG_USB_GADGET=y |
| 136 | CONFIG_DM_USB=y | 136 | CONFIG_DM_USB=y |
| 137 | 137 | ||
| 138 | CONFIG_OF_LIBFDT_OVERLAY=y | 138 | CONFIG_OF_LIBFDT_OVERLAY=y |
| 139 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 139 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
| 140 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 140 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
| 141 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 141 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
| 142 | CONFIG_USB_GADGET_DOWNLOAD=y | 142 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 143 | CONFIG_USB_XHCI_HCD=y | 143 | CONFIG_USB_XHCI_HCD=y |
| 144 | CONFIG_USB_XHCI_IMX8M=y | 144 | CONFIG_USB_XHCI_IMX8M=y |
| 145 | CONFIG_USB_XHCI_DWC3=y | 145 | CONFIG_USB_XHCI_DWC3=y |
| 146 | CONFIG_USB_DWC3=y | 146 | CONFIG_USB_DWC3=y |
| 147 | CONFIG_USB_DWC3_GADGET=y | 147 | CONFIG_USB_DWC3_GADGET=y |
| 148 | 148 | ||
| 149 | CONFIG_OF_BOARD_SETUP=y | 149 | CONFIG_OF_BOARD_SETUP=y |
| 150 | 150 | ||
| 151 | CONFIG_REGMAP=y | 151 | CONFIG_REGMAP=y |
| 152 | CONFIG_SYSCON=y | 152 | CONFIG_SYSCON=y |
| 153 | CONFIG_VIDEO_IMX_LCDIFV3=y | 153 | CONFIG_VIDEO_IMX_LCDIFV3=y |
| 154 | CONFIG_DM_VIDEO=y | 154 | CONFIG_DM_VIDEO=y |
| 155 | CONFIG_SYS_WHITE_ON_BLACK=y | 155 | CONFIG_SYS_WHITE_ON_BLACK=y |
| 156 | 156 |
configs/smarcimx8mp_4g_ser1_android_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_SYS_ICACHE_OFF=y | 2 | CONFIG_SPL_SYS_ICACHE_OFF=y |
| 3 | CONFIG_SPL_SYS_DCACHE_OFF=y | 3 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| 4 | CONFIG_ARCH_IMX8M=y | 4 | CONFIG_ARCH_IMX8M=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x40200000 | 5 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| 6 | CONFIG_SPL_GPIO_SUPPORT=y | 6 | CONFIG_SPL_GPIO_SUPPORT=y |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y | 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 10 | CONFIG_SYS_I2C_MXC_I2C1=y | 10 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 11 | CONFIG_SYS_I2C_MXC_I2C2=y | 11 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C3=y | 12 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 13 | CONFIG_SYS_I2C_MXC_I2C4=y | 13 | CONFIG_SYS_I2C_MXC_I2C4=y |
| 14 | CONFIG_SYS_I2C_MXC_I2C6=y | 14 | CONFIG_SYS_I2C_MXC_I2C6=y |
| 15 | CONFIG_ENV_SIZE=0x1000 | 15 | CONFIG_ENV_SIZE=0x1000 |
| 16 | CONFIG_ENV_OFFSET=0x400000 | 16 | CONFIG_ENV_OFFSET=0x400000 |
| 17 | CONFIG_ENV_SECT_SIZE=0x10000 | 17 | CONFIG_ENV_SECT_SIZE=0x10000 |
| 18 | CONFIG_DM_GPIO=y | 18 | CONFIG_DM_GPIO=y |
| 19 | CONFIG_BOOTDELAY=1 | 19 | CONFIG_BOOTDELAY=1 |
| 20 | CONFIG_TARGET_SMARCIMX8MP=y | 20 | CONFIG_TARGET_SMARCIMX8MP=y |
| 21 | CONFIG_ARCH_MISC_INIT=y | 21 | CONFIG_ARCH_MISC_INIT=y |
| 22 | CONFIG_SPL_SERIAL_SUPPORT=y | 22 | CONFIG_SPL_SERIAL_SUPPORT=y |
| 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 24 | CONFIG_SPL=y | 24 | CONFIG_SPL=y |
| 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 26 | CONFIG_CSF_SIZE=0x2000 | 26 | CONFIG_CSF_SIZE=0x2000 |
| 27 | CONFIG_SPL_TEXT_BASE=0x920000 | 27 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 28 | CONFIG_FIT=y | 28 | CONFIG_FIT=y |
| 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 30 | CONFIG_SPL_LOAD_FIT=y | 30 | CONFIG_SPL_LOAD_FIT=y |
| 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" |
| 32 | CONFIG_OF_SYSTEM_SETUP=y | 32 | CONFIG_OF_SYSTEM_SETUP=y |
| 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,4GB_LPDDR4" | 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,4GB_LPDDR4" |
| 34 | CONFIG_CONSOLE_SER1=y | 34 | CONFIG_CONSOLE_SER1=y |
| 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" | 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" |
| 36 | CONFIG_BOARD_LATE_INIT=y | 36 | CONFIG_BOARD_LATE_INIT=y |
| 37 | CONFIG_BOARD_EARLY_INIT_F=y | 37 | CONFIG_BOARD_EARLY_INIT_F=y |
| 38 | CONFIG_SPL_BOARD_INIT=y | 38 | CONFIG_SPL_BOARD_INIT=y |
| 39 | CONFIG_SPL_SEPARATE_BSS=y | 39 | CONFIG_SPL_SEPARATE_BSS=y |
| 40 | CONFIG_SPL_I2C_SUPPORT=y | 40 | CONFIG_SPL_I2C_SUPPORT=y |
| 41 | CONFIG_SPL_POWER_SUPPORT=y | 41 | CONFIG_SPL_POWER_SUPPORT=y |
| 42 | CONFIG_NR_DRAM_BANKS=3 | 42 | CONFIG_NR_DRAM_BANKS=3 |
| 43 | CONFIG_HUSH_PARSER=y | 43 | CONFIG_HUSH_PARSER=y |
| 44 | CONFIG_SYS_PROMPT="u-boot$ " | 44 | CONFIG_SYS_PROMPT="u-boot$ " |
| 45 | # CONFIG_CMD_EXPORTENV is not set | 45 | # CONFIG_CMD_EXPORTENV is not set |
| 46 | CONFIG_CMD_IMPORTENV=y | 46 | CONFIG_CMD_IMPORTENV=y |
| 47 | CONFIG_CMD_ERASEENV=y | 47 | CONFIG_CMD_ERASEENV=y |
| 48 | # CONFIG_CMD_CRC32 is not set | 48 | # CONFIG_CMD_CRC32 is not set |
| 49 | # CONFIG_BOOTM_NETBSD is not set | 49 | # CONFIG_BOOTM_NETBSD is not set |
| 50 | CONFIG_CMD_CLK=y | 50 | CONFIG_CMD_CLK=y |
| 51 | CONFIG_CMD_FUSE=y | 51 | CONFIG_CMD_FUSE=y |
| 52 | CONFIG_CMD_GPIO=y | 52 | CONFIG_CMD_GPIO=y |
| 53 | CONFIG_CMD_I2C=y | 53 | CONFIG_CMD_I2C=y |
| 54 | CONFIG_CMD_MMC=y | 54 | CONFIG_CMD_MMC=y |
| 55 | CONFIG_CMD_DHCP=y | 55 | CONFIG_CMD_DHCP=y |
| 56 | CONFIG_CMD_MII=y | 56 | CONFIG_CMD_MII=y |
| 57 | CONFIG_CMD_PING=y | 57 | CONFIG_CMD_PING=y |
| 58 | CONFIG_CMD_CACHE=y | 58 | CONFIG_CMD_CACHE=y |
| 59 | CONFIG_CMD_REGULATOR=y | 59 | CONFIG_CMD_REGULATOR=y |
| 60 | CONFIG_CMD_MEMTEST=y | 60 | CONFIG_CMD_MEMTEST=y |
| 61 | CONFIG_CMD_EXT2=y | 61 | CONFIG_CMD_EXT2=y |
| 62 | CONFIG_CMD_EXT4=y | 62 | CONFIG_CMD_EXT4=y |
| 63 | CONFIG_CMD_EXT4_WRITE=y | 63 | CONFIG_CMD_EXT4_WRITE=y |
| 64 | CONFIG_CMD_FAT=y | 64 | CONFIG_CMD_FAT=y |
| 65 | CONFIG_CMD_SF=y | 65 | CONFIG_CMD_SF=y |
| 66 | CONFIG_CMD_LED=y | 66 | CONFIG_CMD_LED=y |
| 67 | CONFIG_OF_CONTROL=y | 67 | CONFIG_OF_CONTROL=y |
| 68 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" | 68 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" |
| 69 | CONFIG_ENV_IS_IN_MMC=y | 69 | CONFIG_ENV_IS_IN_MMC=y |
| 70 | CONFIG_ENV_IS_IN_SPI_FLASH=y | 70 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 71 | CONFIG_ENV_IS_NOWHERE=y | 71 | CONFIG_ENV_IS_NOWHERE=y |
| 72 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | 72 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 73 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | 73 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 74 | CONFIG_CLK_COMPOSITE_CCF=y | 74 | CONFIG_CLK_COMPOSITE_CCF=y |
| 75 | CONFIG_CLK_IMX8MP=y | 75 | CONFIG_CLK_IMX8MP=y |
| 76 | CONFIG_MXC_GPIO=y | 76 | CONFIG_MXC_GPIO=y |
| 77 | CONFIG_DM_PCA953X=y | 77 | CONFIG_DM_PCA953X=y |
| 78 | CONFIG_FASTBOOT=y | 78 | CONFIG_FASTBOOT=y |
| 79 | CONFIG_USB_FUNCTION_FASTBOOT=y | 79 | CONFIG_USB_FUNCTION_FASTBOOT=y |
| 80 | CONFIG_CMD_FASTBOOT=y | 80 | CONFIG_CMD_FASTBOOT=y |
| 81 | CONFIG_ANDROID_BOOT_IMAGE=y | 81 | CONFIG_ANDROID_BOOT_IMAGE=y |
| 82 | CONFIG_FASTBOOT_UUU_SUPPORT=n | 82 | CONFIG_FASTBOOT_UUU_SUPPORT=n |
| 83 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 83 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
| 84 | CONFIG_FASTBOOT_BUF_SIZE=0xc800000 | 84 | CONFIG_FASTBOOT_BUF_SIZE=0xc800000 |
| 85 | CONFIG_FASTBOOT_FLASH=y | 85 | CONFIG_FASTBOOT_FLASH=y |
| 86 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 | 86 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
| 87 | CONFIG_DM_I2C=y | 87 | CONFIG_DM_I2C=y |
| 88 | CONFIG_CMD_GPT=y | 88 | CONFIG_CMD_GPT=y |
| 89 | CONFIG_CMD_TIME=y | 89 | CONFIG_CMD_TIME=y |
| 90 | CONFIG_SYS_I2C_MXC=y | 90 | CONFIG_SYS_I2C_MXC=y |
| 91 | CONFIG_LED=y | 91 | CONFIG_LED=y |
| 92 | CONFIG_LED_GPIO=y | 92 | CONFIG_LED_GPIO=y |
| 93 | CONFIG_DM_MMC=y | 93 | CONFIG_DM_MMC=y |
| 94 | CONFIG_MMC_IO_VOLTAGE=y | 94 | # CONFIG_MMC_IO_VOLTAGE is not set |
| 95 | CONFIG_MMC_UHS_SUPPORT=y | 95 | CONFIG_MMC_UHS_SUPPORT=y |
| 96 | CONFIG_MMC_HS400_SUPPORT=y | 96 | CONFIG_MMC_HS400_SUPPORT=y |
| 97 | CONFIG_MMC_HS400_ES_SUPPORT=y | 97 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 98 | CONFIG_EFI_PARTITION=y | 98 | CONFIG_EFI_PARTITION=y |
| 99 | CONFIG_SUPPORT_EMMC_BOOT=y | 99 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 100 | CONFIG_FSL_ESDHC_IMX=y | 100 | CONFIG_FSL_ESDHC_IMX=y |
| 101 | CONFIG_DM_SPI_FLASH=y | 101 | CONFIG_DM_SPI_FLASH=y |
| 102 | CONFIG_DM_SPI=y | 102 | CONFIG_DM_SPI=y |
| 103 | CONFIG_FSL_FSPI=y | 103 | CONFIG_FSL_FSPI=y |
| 104 | CONFIG_SPI=y | 104 | CONFIG_SPI=y |
| 105 | CONFIG_SPI_FLASH=y | 105 | CONFIG_SPI_FLASH=y |
| 106 | CONFIG_SPI_FLASH_BAR=y | 106 | CONFIG_SPI_FLASH_BAR=y |
| 107 | CONFIG_SPI_FLASH_MACRONIX=y | 107 | CONFIG_SPI_FLASH_MACRONIX=y |
| 108 | CONFIG_SF_DEFAULT_BUS=0 | 108 | CONFIG_SF_DEFAULT_BUS=0 |
| 109 | CONFIG_SF_DEFAULT_CS=0 | 109 | CONFIG_SF_DEFAULT_CS=0 |
| 110 | CONFIG_SF_DEFAULT_SPEED=40000000 | 110 | CONFIG_SF_DEFAULT_SPEED=40000000 |
| 111 | CONFIG_SF_DEFAULT_MODE=0 | 111 | CONFIG_SF_DEFAULT_MODE=0 |
| 112 | 112 | ||
| 113 | CONFIG_DM_ETH=y | 113 | CONFIG_DM_ETH=y |
| 114 | # CONFIG_DM_ETH_PHY=y | 114 | # CONFIG_DM_ETH_PHY=y |
| 115 | CONFIG_DWC_ETH_QOS=y | 115 | CONFIG_DWC_ETH_QOS=y |
| 116 | 116 | ||
| 117 | CONFIG_PHY_GIGE=y | 117 | CONFIG_PHY_GIGE=y |
| 118 | CONFIG_FEC_MXC=y | 118 | CONFIG_FEC_MXC=y |
| 119 | CONFIG_MII=y | 119 | CONFIG_MII=y |
| 120 | CONFIG_PHYLIB=y | 120 | CONFIG_PHYLIB=y |
| 121 | CONFIG_PHY_ATHEROS=y | 121 | CONFIG_PHY_ATHEROS=y |
| 122 | 122 | ||
| 123 | CONFIG_PINCTRL=y | 123 | CONFIG_PINCTRL=y |
| 124 | CONFIG_PINCTRL_IMX8M=y | 124 | CONFIG_PINCTRL_IMX8M=y |
| 125 | CONFIG_DM_REGULATOR=y | 125 | CONFIG_DM_REGULATOR=y |
| 126 | CONFIG_DM_REGULATOR_FIXED=y | 126 | CONFIG_DM_REGULATOR_FIXED=y |
| 127 | CONFIG_DM_REGULATOR_GPIO=y | 127 | CONFIG_DM_REGULATOR_GPIO=y |
| 128 | CONFIG_MXC_UART=y | 128 | CONFIG_MXC_UART=y |
| 129 | CONFIG_SYSRESET=y | 129 | CONFIG_SYSRESET=y |
| 130 | CONFIG_SYSRESET_PSCI=y | 130 | CONFIG_SYSRESET_PSCI=y |
| 131 | CONFIG_DM_THERMAL=y | 131 | CONFIG_DM_THERMAL=y |
| 132 | CONFIG_NXP_TMU=y | 132 | CONFIG_NXP_TMU=y |
| 133 | CONFIG_USB=y | 133 | CONFIG_USB=y |
| 134 | CONFIG_USB_GADGET=y | 134 | CONFIG_USB_GADGET=y |
| 135 | CONFIG_DM_USB=y | 135 | CONFIG_DM_USB=y |
| 136 | 136 | ||
| 137 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 137 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
| 138 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 138 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
| 139 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 139 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
| 140 | CONFIG_USB_GADGET_DOWNLOAD=y | 140 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 141 | CONFIG_USB_XHCI_HCD=y | 141 | CONFIG_USB_XHCI_HCD=y |
| 142 | CONFIG_USB_XHCI_IMX8M=y | 142 | CONFIG_USB_XHCI_IMX8M=y |
| 143 | CONFIG_USB_XHCI_DWC3=y | 143 | CONFIG_USB_XHCI_DWC3=y |
| 144 | CONFIG_USB_DWC3=y | 144 | CONFIG_USB_DWC3=y |
| 145 | CONFIG_USB_DWC3_GADGET=y | 145 | CONFIG_USB_DWC3_GADGET=y |
| 146 | 146 | ||
| 147 | CONFIG_OF_BOARD_SETUP=y | 147 | CONFIG_OF_BOARD_SETUP=y |
| 148 | 148 | ||
| 149 | CONFIG_REGMAP=y | 149 | CONFIG_REGMAP=y |
| 150 | CONFIG_SYSCON=y | 150 | CONFIG_SYSCON=y |
| 151 | CONFIG_VIDEO_IMX_LCDIFV3=y | 151 | CONFIG_VIDEO_IMX_LCDIFV3=y |
| 152 | CONFIG_DM_VIDEO=y | 152 | CONFIG_DM_VIDEO=y |
| 153 | CONFIG_SYS_WHITE_ON_BLACK=y | 153 | CONFIG_SYS_WHITE_ON_BLACK=y |
| 154 | 154 | ||
| 155 | CONFIG_LZ4=y | 155 | CONFIG_LZ4=y |
| 156 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y | 156 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y |
| 157 | CONFIG_APPEND_BOOTARGS=y | 157 | CONFIG_APPEND_BOOTARGS=y |
| 158 | CONFIG_SPL_MMC_SUPPORT=y | 158 | CONFIG_SPL_MMC_SUPPORT=y |
| 159 | CONFIG_AVB_WARNING_LOGO=y | 159 | CONFIG_AVB_WARNING_LOGO=y |
| 160 | CONFIG_AVB_WARNING_LOGO_COLS=0x320 | 160 | CONFIG_AVB_WARNING_LOGO_COLS=0x320 |
| 161 | CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 | 161 | CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 |
| 162 | CONFIG_VIRTUAL_AB_SUPPORT=y | 162 | CONFIG_VIRTUAL_AB_SUPPORT=y |
| 163 | CONFIG_ANDROID_SUPPORT=y | 163 | CONFIG_ANDROID_SUPPORT=y |
| 164 | CONFIG_APPEND_BOOTARGS=y | 164 | CONFIG_APPEND_BOOTARGS=y |
| 165 | CONFIG_ANDROID_AB_SUPPORT=y | 165 | CONFIG_ANDROID_AB_SUPPORT=y |
| 166 | 166 |
configs/smarcimx8mp_4g_ser1_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_SYS_ICACHE_OFF=y | 2 | CONFIG_SPL_SYS_ICACHE_OFF=y |
| 3 | CONFIG_SPL_SYS_DCACHE_OFF=y | 3 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| 4 | CONFIG_ARCH_IMX8M=y | 4 | CONFIG_ARCH_IMX8M=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x40200000 | 5 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| 6 | CONFIG_SPL_GPIO_SUPPORT=y | 6 | CONFIG_SPL_GPIO_SUPPORT=y |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y | 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 10 | CONFIG_SYS_I2C_MXC_I2C1=y | 10 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 11 | CONFIG_SYS_I2C_MXC_I2C2=y | 11 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C3=y | 12 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 13 | CONFIG_SYS_I2C_MXC_I2C4=y | 13 | CONFIG_SYS_I2C_MXC_I2C4=y |
| 14 | CONFIG_SYS_I2C_MXC_I2C6=y | 14 | CONFIG_SYS_I2C_MXC_I2C6=y |
| 15 | CONFIG_ENV_SIZE=0x1000 | 15 | CONFIG_ENV_SIZE=0x1000 |
| 16 | CONFIG_ENV_OFFSET=0x400000 | 16 | CONFIG_ENV_OFFSET=0x400000 |
| 17 | CONFIG_ENV_SECT_SIZE=0x10000 | 17 | CONFIG_ENV_SECT_SIZE=0x10000 |
| 18 | CONFIG_DM_GPIO=y | 18 | CONFIG_DM_GPIO=y |
| 19 | CONFIG_BOOTDELAY=1 | 19 | CONFIG_BOOTDELAY=1 |
| 20 | CONFIG_TARGET_SMARCIMX8MP=y | 20 | CONFIG_TARGET_SMARCIMX8MP=y |
| 21 | CONFIG_ARCH_MISC_INIT=y | 21 | CONFIG_ARCH_MISC_INIT=y |
| 22 | CONFIG_SPL_SERIAL_SUPPORT=y | 22 | CONFIG_SPL_SERIAL_SUPPORT=y |
| 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 24 | CONFIG_SPL=y | 24 | CONFIG_SPL=y |
| 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 26 | CONFIG_CSF_SIZE=0x2000 | 26 | CONFIG_CSF_SIZE=0x2000 |
| 27 | CONFIG_SPL_TEXT_BASE=0x920000 | 27 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 28 | CONFIG_FIT=y | 28 | CONFIG_FIT=y |
| 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 30 | CONFIG_SPL_LOAD_FIT=y | 30 | CONFIG_SPL_LOAD_FIT=y |
| 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" |
| 32 | CONFIG_OF_SYSTEM_SETUP=y | 32 | CONFIG_OF_SYSTEM_SETUP=y |
| 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,4GB_LPDDR4" | 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,4GB_LPDDR4" |
| 34 | CONFIG_CONSOLE_SER1=y | 34 | CONFIG_CONSOLE_SER1=y |
| 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" | 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" |
| 36 | CONFIG_BOARD_LATE_INIT=y | 36 | CONFIG_BOARD_LATE_INIT=y |
| 37 | CONFIG_BOARD_EARLY_INIT_F=y | 37 | CONFIG_BOARD_EARLY_INIT_F=y |
| 38 | CONFIG_SPL_BOARD_INIT=y | 38 | CONFIG_SPL_BOARD_INIT=y |
| 39 | CONFIG_SPL_BOOTROM_SUPPORT=y | 39 | CONFIG_SPL_BOOTROM_SUPPORT=y |
| 40 | CONFIG_SPL_SEPARATE_BSS=y | 40 | CONFIG_SPL_SEPARATE_BSS=y |
| 41 | CONFIG_SPL_I2C_SUPPORT=y | 41 | CONFIG_SPL_I2C_SUPPORT=y |
| 42 | CONFIG_SPL_POWER_SUPPORT=y | 42 | CONFIG_SPL_POWER_SUPPORT=y |
| 43 | CONFIG_NR_DRAM_BANKS=3 | 43 | CONFIG_NR_DRAM_BANKS=3 |
| 44 | CONFIG_HUSH_PARSER=y | 44 | CONFIG_HUSH_PARSER=y |
| 45 | CONFIG_SYS_PROMPT="u-boot$ " | 45 | CONFIG_SYS_PROMPT="u-boot$ " |
| 46 | # CONFIG_CMD_EXPORTENV is not set | 46 | # CONFIG_CMD_EXPORTENV is not set |
| 47 | CONFIG_CMD_IMPORTENV=y | 47 | CONFIG_CMD_IMPORTENV=y |
| 48 | CONFIG_CMD_ERASEENV=y | 48 | CONFIG_CMD_ERASEENV=y |
| 49 | # CONFIG_CMD_CRC32 is not set | 49 | # CONFIG_CMD_CRC32 is not set |
| 50 | # CONFIG_BOOTM_NETBSD is not set | 50 | # CONFIG_BOOTM_NETBSD is not set |
| 51 | CONFIG_CMD_CLK=y | 51 | CONFIG_CMD_CLK=y |
| 52 | CONFIG_CMD_FUSE=y | 52 | CONFIG_CMD_FUSE=y |
| 53 | CONFIG_CMD_GPIO=y | 53 | CONFIG_CMD_GPIO=y |
| 54 | CONFIG_CMD_I2C=y | 54 | CONFIG_CMD_I2C=y |
| 55 | CONFIG_CMD_MMC=y | 55 | CONFIG_CMD_MMC=y |
| 56 | CONFIG_CMD_DHCP=y | 56 | CONFIG_CMD_DHCP=y |
| 57 | CONFIG_CMD_MII=y | 57 | CONFIG_CMD_MII=y |
| 58 | CONFIG_CMD_PING=y | 58 | CONFIG_CMD_PING=y |
| 59 | CONFIG_CMD_CACHE=y | 59 | CONFIG_CMD_CACHE=y |
| 60 | CONFIG_CMD_REGULATOR=y | 60 | CONFIG_CMD_REGULATOR=y |
| 61 | CONFIG_CMD_MEMTEST=y | 61 | CONFIG_CMD_MEMTEST=y |
| 62 | CONFIG_CMD_EXT2=y | 62 | CONFIG_CMD_EXT2=y |
| 63 | CONFIG_CMD_EXT4=y | 63 | CONFIG_CMD_EXT4=y |
| 64 | CONFIG_CMD_EXT4_WRITE=y | 64 | CONFIG_CMD_EXT4_WRITE=y |
| 65 | CONFIG_CMD_FAT=y | 65 | CONFIG_CMD_FAT=y |
| 66 | CONFIG_CMD_SF=y | 66 | CONFIG_CMD_SF=y |
| 67 | CONFIG_CMD_LED=y | 67 | CONFIG_CMD_LED=y |
| 68 | CONFIG_OF_CONTROL=y | 68 | CONFIG_OF_CONTROL=y |
| 69 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" | 69 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" |
| 70 | CONFIG_ENV_IS_IN_MMC=y | 70 | CONFIG_ENV_IS_IN_MMC=y |
| 71 | CONFIG_ENV_IS_IN_SPI_FLASH=y | 71 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 72 | CONFIG_ENV_IS_NOWHERE=y | 72 | CONFIG_ENV_IS_NOWHERE=y |
| 73 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | 73 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 74 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | 74 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 75 | CONFIG_CLK_COMPOSITE_CCF=y | 75 | CONFIG_CLK_COMPOSITE_CCF=y |
| 76 | CONFIG_CLK_IMX8MP=y | 76 | CONFIG_CLK_IMX8MP=y |
| 77 | CONFIG_MXC_GPIO=y | 77 | CONFIG_MXC_GPIO=y |
| 78 | CONFIG_DM_PCA953X=y | 78 | CONFIG_DM_PCA953X=y |
| 79 | CONFIG_FASTBOOT=y | 79 | CONFIG_FASTBOOT=y |
| 80 | CONFIG_USB_FUNCTION_FASTBOOT=y | 80 | CONFIG_USB_FUNCTION_FASTBOOT=y |
| 81 | CONFIG_CMD_FASTBOOT=y | 81 | CONFIG_CMD_FASTBOOT=y |
| 82 | CONFIG_ANDROID_BOOT_IMAGE=y | 82 | CONFIG_ANDROID_BOOT_IMAGE=y |
| 83 | CONFIG_FASTBOOT_UUU_SUPPORT=y | 83 | CONFIG_FASTBOOT_UUU_SUPPORT=y |
| 84 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 84 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
| 85 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 85 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
| 86 | CONFIG_FASTBOOT_FLASH=y | 86 | CONFIG_FASTBOOT_FLASH=y |
| 87 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 | 87 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
| 88 | CONFIG_DM_I2C=y | 88 | CONFIG_DM_I2C=y |
| 89 | CONFIG_CMD_GPT=y | 89 | CONFIG_CMD_GPT=y |
| 90 | CONFIG_CMD_TIME=y | 90 | CONFIG_CMD_TIME=y |
| 91 | CONFIG_SYS_I2C_MXC=y | 91 | CONFIG_SYS_I2C_MXC=y |
| 92 | CONFIG_LED=y | 92 | CONFIG_LED=y |
| 93 | CONFIG_LED_GPIO=y | 93 | CONFIG_LED_GPIO=y |
| 94 | CONFIG_DM_MMC=y | 94 | CONFIG_DM_MMC=y |
| 95 | CONFIG_MMC_IO_VOLTAGE=y | 95 | # CONFIG_MMC_IO_VOLTAGE is not set |
| 96 | CONFIG_MMC_UHS_SUPPORT=y | 96 | CONFIG_MMC_UHS_SUPPORT=y |
| 97 | CONFIG_MMC_HS400_SUPPORT=y | 97 | CONFIG_MMC_HS400_SUPPORT=y |
| 98 | CONFIG_MMC_HS400_ES_SUPPORT=y | 98 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 99 | CONFIG_EFI_PARTITION=y | 99 | CONFIG_EFI_PARTITION=y |
| 100 | CONFIG_SUPPORT_EMMC_BOOT=y | 100 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 101 | CONFIG_FSL_ESDHC_IMX=y | 101 | CONFIG_FSL_ESDHC_IMX=y |
| 102 | CONFIG_DM_SPI_FLASH=y | 102 | CONFIG_DM_SPI_FLASH=y |
| 103 | CONFIG_DM_SPI=y | 103 | CONFIG_DM_SPI=y |
| 104 | CONFIG_FSL_FSPI=y | 104 | CONFIG_FSL_FSPI=y |
| 105 | CONFIG_SPI=y | 105 | CONFIG_SPI=y |
| 106 | CONFIG_SPI_FLASH=y | 106 | CONFIG_SPI_FLASH=y |
| 107 | CONFIG_SPI_FLASH_BAR=y | 107 | CONFIG_SPI_FLASH_BAR=y |
| 108 | CONFIG_SPI_FLASH_MACRONIX=y | 108 | CONFIG_SPI_FLASH_MACRONIX=y |
| 109 | CONFIG_SF_DEFAULT_BUS=0 | 109 | CONFIG_SF_DEFAULT_BUS=0 |
| 110 | CONFIG_SF_DEFAULT_CS=0 | 110 | CONFIG_SF_DEFAULT_CS=0 |
| 111 | CONFIG_SF_DEFAULT_SPEED=40000000 | 111 | CONFIG_SF_DEFAULT_SPEED=40000000 |
| 112 | CONFIG_SF_DEFAULT_MODE=0 | 112 | CONFIG_SF_DEFAULT_MODE=0 |
| 113 | 113 | ||
| 114 | CONFIG_DM_ETH=y | 114 | CONFIG_DM_ETH=y |
| 115 | # CONFIG_DM_ETH_PHY=y | 115 | # CONFIG_DM_ETH_PHY=y |
| 116 | CONFIG_DWC_ETH_QOS=y | 116 | CONFIG_DWC_ETH_QOS=y |
| 117 | 117 | ||
| 118 | CONFIG_PHY_GIGE=y | 118 | CONFIG_PHY_GIGE=y |
| 119 | CONFIG_FEC_MXC=y | 119 | CONFIG_FEC_MXC=y |
| 120 | CONFIG_MII=y | 120 | CONFIG_MII=y |
| 121 | CONFIG_PHYLIB=y | 121 | CONFIG_PHYLIB=y |
| 122 | CONFIG_PHY_ATHEROS=y | 122 | CONFIG_PHY_ATHEROS=y |
| 123 | 123 | ||
| 124 | CONFIG_PINCTRL=y | 124 | CONFIG_PINCTRL=y |
| 125 | CONFIG_PINCTRL_IMX8M=y | 125 | CONFIG_PINCTRL_IMX8M=y |
| 126 | CONFIG_DM_REGULATOR=y | 126 | CONFIG_DM_REGULATOR=y |
| 127 | CONFIG_DM_REGULATOR_FIXED=y | 127 | CONFIG_DM_REGULATOR_FIXED=y |
| 128 | CONFIG_DM_REGULATOR_GPIO=y | 128 | CONFIG_DM_REGULATOR_GPIO=y |
| 129 | CONFIG_MXC_UART=y | 129 | CONFIG_MXC_UART=y |
| 130 | CONFIG_SYSRESET=y | 130 | CONFIG_SYSRESET=y |
| 131 | CONFIG_SYSRESET_PSCI=y | 131 | CONFIG_SYSRESET_PSCI=y |
| 132 | CONFIG_DM_THERMAL=y | 132 | CONFIG_DM_THERMAL=y |
| 133 | CONFIG_NXP_TMU=y | 133 | CONFIG_NXP_TMU=y |
| 134 | CONFIG_USB=y | 134 | CONFIG_USB=y |
| 135 | CONFIG_USB_GADGET=y | 135 | CONFIG_USB_GADGET=y |
| 136 | CONFIG_DM_USB=y | 136 | CONFIG_DM_USB=y |
| 137 | 137 | ||
| 138 | CONFIG_OF_LIBFDT_OVERLAY=y | 138 | CONFIG_OF_LIBFDT_OVERLAY=y |
| 139 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 139 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
| 140 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 140 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
| 141 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 141 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
| 142 | CONFIG_USB_GADGET_DOWNLOAD=y | 142 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 143 | CONFIG_USB_XHCI_HCD=y | 143 | CONFIG_USB_XHCI_HCD=y |
| 144 | CONFIG_USB_XHCI_IMX8M=y | 144 | CONFIG_USB_XHCI_IMX8M=y |
| 145 | CONFIG_USB_XHCI_DWC3=y | 145 | CONFIG_USB_XHCI_DWC3=y |
| 146 | CONFIG_USB_DWC3=y | 146 | CONFIG_USB_DWC3=y |
| 147 | CONFIG_USB_DWC3_GADGET=y | 147 | CONFIG_USB_DWC3_GADGET=y |
| 148 | 148 | ||
| 149 | CONFIG_OF_BOARD_SETUP=y | 149 | CONFIG_OF_BOARD_SETUP=y |
| 150 | 150 | ||
| 151 | CONFIG_REGMAP=y | 151 | CONFIG_REGMAP=y |
| 152 | CONFIG_SYSCON=y | 152 | CONFIG_SYSCON=y |
| 153 | CONFIG_SYS_WHITE_ON_BLACK=y | 153 | CONFIG_SYS_WHITE_ON_BLACK=y |
| 154 | 154 |
configs/smarcimx8mp_4g_ser2_android_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_SYS_ICACHE_OFF=y | 2 | CONFIG_SPL_SYS_ICACHE_OFF=y |
| 3 | CONFIG_SPL_SYS_DCACHE_OFF=y | 3 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| 4 | CONFIG_ARCH_IMX8M=y | 4 | CONFIG_ARCH_IMX8M=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x40200000 | 5 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| 6 | CONFIG_SPL_GPIO_SUPPORT=y | 6 | CONFIG_SPL_GPIO_SUPPORT=y |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y | 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 10 | CONFIG_SYS_I2C_MXC_I2C1=y | 10 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 11 | CONFIG_SYS_I2C_MXC_I2C2=y | 11 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C3=y | 12 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 13 | CONFIG_SYS_I2C_MXC_I2C4=y | 13 | CONFIG_SYS_I2C_MXC_I2C4=y |
| 14 | CONFIG_SYS_I2C_MXC_I2C6=y | 14 | CONFIG_SYS_I2C_MXC_I2C6=y |
| 15 | CONFIG_ENV_SIZE=0x1000 | 15 | CONFIG_ENV_SIZE=0x1000 |
| 16 | CONFIG_ENV_OFFSET=0x400000 | 16 | CONFIG_ENV_OFFSET=0x400000 |
| 17 | CONFIG_ENV_SECT_SIZE=0x10000 | 17 | CONFIG_ENV_SECT_SIZE=0x10000 |
| 18 | CONFIG_DM_GPIO=y | 18 | CONFIG_DM_GPIO=y |
| 19 | CONFIG_BOOTDELAY=1 | 19 | CONFIG_BOOTDELAY=1 |
| 20 | CONFIG_TARGET_SMARCIMX8MP=y | 20 | CONFIG_TARGET_SMARCIMX8MP=y |
| 21 | CONFIG_ARCH_MISC_INIT=y | 21 | CONFIG_ARCH_MISC_INIT=y |
| 22 | CONFIG_SPL_SERIAL_SUPPORT=y | 22 | CONFIG_SPL_SERIAL_SUPPORT=y |
| 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 24 | CONFIG_SPL=y | 24 | CONFIG_SPL=y |
| 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 26 | CONFIG_CSF_SIZE=0x2000 | 26 | CONFIG_CSF_SIZE=0x2000 |
| 27 | CONFIG_SPL_TEXT_BASE=0x920000 | 27 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 28 | CONFIG_FIT=y | 28 | CONFIG_FIT=y |
| 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 30 | CONFIG_SPL_LOAD_FIT=y | 30 | CONFIG_SPL_LOAD_FIT=y |
| 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" |
| 32 | CONFIG_OF_SYSTEM_SETUP=y | 32 | CONFIG_OF_SYSTEM_SETUP=y |
| 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,4GB_LPDDR4" | 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,4GB_LPDDR4" |
| 34 | CONFIG_CONSOLE_SER2=y | 34 | CONFIG_CONSOLE_SER2=y |
| 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" | 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" |
| 36 | CONFIG_BOARD_LATE_INIT=y | 36 | CONFIG_BOARD_LATE_INIT=y |
| 37 | CONFIG_BOARD_EARLY_INIT_F=y | 37 | CONFIG_BOARD_EARLY_INIT_F=y |
| 38 | CONFIG_SPL_BOARD_INIT=y | 38 | CONFIG_SPL_BOARD_INIT=y |
| 39 | CONFIG_SPL_SEPARATE_BSS=y | 39 | CONFIG_SPL_SEPARATE_BSS=y |
| 40 | CONFIG_SPL_I2C_SUPPORT=y | 40 | CONFIG_SPL_I2C_SUPPORT=y |
| 41 | CONFIG_SPL_POWER_SUPPORT=y | 41 | CONFIG_SPL_POWER_SUPPORT=y |
| 42 | CONFIG_NR_DRAM_BANKS=3 | 42 | CONFIG_NR_DRAM_BANKS=3 |
| 43 | CONFIG_HUSH_PARSER=y | 43 | CONFIG_HUSH_PARSER=y |
| 44 | CONFIG_SYS_PROMPT="u-boot$ " | 44 | CONFIG_SYS_PROMPT="u-boot$ " |
| 45 | # CONFIG_CMD_EXPORTENV is not set | 45 | # CONFIG_CMD_EXPORTENV is not set |
| 46 | CONFIG_CMD_IMPORTENV=y | 46 | CONFIG_CMD_IMPORTENV=y |
| 47 | CONFIG_CMD_ERASEENV=y | 47 | CONFIG_CMD_ERASEENV=y |
| 48 | # CONFIG_CMD_CRC32 is not set | 48 | # CONFIG_CMD_CRC32 is not set |
| 49 | # CONFIG_BOOTM_NETBSD is not set | 49 | # CONFIG_BOOTM_NETBSD is not set |
| 50 | CONFIG_CMD_CLK=y | 50 | CONFIG_CMD_CLK=y |
| 51 | CONFIG_CMD_FUSE=y | 51 | CONFIG_CMD_FUSE=y |
| 52 | CONFIG_CMD_GPIO=y | 52 | CONFIG_CMD_GPIO=y |
| 53 | CONFIG_CMD_I2C=y | 53 | CONFIG_CMD_I2C=y |
| 54 | CONFIG_CMD_MMC=y | 54 | CONFIG_CMD_MMC=y |
| 55 | CONFIG_CMD_DHCP=y | 55 | CONFIG_CMD_DHCP=y |
| 56 | CONFIG_CMD_MII=y | 56 | CONFIG_CMD_MII=y |
| 57 | CONFIG_CMD_PING=y | 57 | CONFIG_CMD_PING=y |
| 58 | CONFIG_CMD_CACHE=y | 58 | CONFIG_CMD_CACHE=y |
| 59 | CONFIG_CMD_REGULATOR=y | 59 | CONFIG_CMD_REGULATOR=y |
| 60 | CONFIG_CMD_MEMTEST=y | 60 | CONFIG_CMD_MEMTEST=y |
| 61 | CONFIG_CMD_EXT2=y | 61 | CONFIG_CMD_EXT2=y |
| 62 | CONFIG_CMD_EXT4=y | 62 | CONFIG_CMD_EXT4=y |
| 63 | CONFIG_CMD_EXT4_WRITE=y | 63 | CONFIG_CMD_EXT4_WRITE=y |
| 64 | CONFIG_CMD_FAT=y | 64 | CONFIG_CMD_FAT=y |
| 65 | CONFIG_CMD_SF=y | 65 | CONFIG_CMD_SF=y |
| 66 | CONFIG_CMD_LED=y | 66 | CONFIG_CMD_LED=y |
| 67 | CONFIG_OF_CONTROL=y | 67 | CONFIG_OF_CONTROL=y |
| 68 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" | 68 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" |
| 69 | CONFIG_ENV_IS_IN_MMC=y | 69 | CONFIG_ENV_IS_IN_MMC=y |
| 70 | CONFIG_ENV_IS_IN_SPI_FLASH=y | 70 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 71 | CONFIG_ENV_IS_NOWHERE=y | 71 | CONFIG_ENV_IS_NOWHERE=y |
| 72 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | 72 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 73 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | 73 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 74 | CONFIG_CLK_COMPOSITE_CCF=y | 74 | CONFIG_CLK_COMPOSITE_CCF=y |
| 75 | CONFIG_CLK_IMX8MP=y | 75 | CONFIG_CLK_IMX8MP=y |
| 76 | CONFIG_MXC_GPIO=y | 76 | CONFIG_MXC_GPIO=y |
| 77 | CONFIG_DM_PCA953X=y | 77 | CONFIG_DM_PCA953X=y |
| 78 | CONFIG_FASTBOOT=y | 78 | CONFIG_FASTBOOT=y |
| 79 | CONFIG_USB_FUNCTION_FASTBOOT=y | 79 | CONFIG_USB_FUNCTION_FASTBOOT=y |
| 80 | CONFIG_CMD_FASTBOOT=y | 80 | CONFIG_CMD_FASTBOOT=y |
| 81 | CONFIG_ANDROID_BOOT_IMAGE=y | 81 | CONFIG_ANDROID_BOOT_IMAGE=y |
| 82 | CONFIG_FASTBOOT_UUU_SUPPORT=n | 82 | CONFIG_FASTBOOT_UUU_SUPPORT=n |
| 83 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 83 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
| 84 | CONFIG_FASTBOOT_BUF_SIZE=0xc800000 | 84 | CONFIG_FASTBOOT_BUF_SIZE=0xc800000 |
| 85 | CONFIG_FASTBOOT_FLASH=y | 85 | CONFIG_FASTBOOT_FLASH=y |
| 86 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 | 86 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
| 87 | CONFIG_DM_I2C=y | 87 | CONFIG_DM_I2C=y |
| 88 | CONFIG_CMD_GPT=y | 88 | CONFIG_CMD_GPT=y |
| 89 | CONFIG_CMD_TIME=y | 89 | CONFIG_CMD_TIME=y |
| 90 | CONFIG_SYS_I2C_MXC=y | 90 | CONFIG_SYS_I2C_MXC=y |
| 91 | CONFIG_LED=y | 91 | CONFIG_LED=y |
| 92 | CONFIG_LED_GPIO=y | 92 | CONFIG_LED_GPIO=y |
| 93 | CONFIG_DM_MMC=y | 93 | CONFIG_DM_MMC=y |
| 94 | CONFIG_MMC_IO_VOLTAGE=y | 94 | # CONFIG_MMC_IO_VOLTAGE is not set |
| 95 | CONFIG_MMC_UHS_SUPPORT=y | 95 | CONFIG_MMC_UHS_SUPPORT=y |
| 96 | CONFIG_MMC_HS400_SUPPORT=y | 96 | CONFIG_MMC_HS400_SUPPORT=y |
| 97 | CONFIG_MMC_HS400_ES_SUPPORT=y | 97 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 98 | CONFIG_EFI_PARTITION=y | 98 | CONFIG_EFI_PARTITION=y |
| 99 | CONFIG_SUPPORT_EMMC_BOOT=y | 99 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 100 | CONFIG_FSL_ESDHC_IMX=y | 100 | CONFIG_FSL_ESDHC_IMX=y |
| 101 | CONFIG_DM_SPI_FLASH=y | 101 | CONFIG_DM_SPI_FLASH=y |
| 102 | CONFIG_DM_SPI=y | 102 | CONFIG_DM_SPI=y |
| 103 | CONFIG_FSL_FSPI=y | 103 | CONFIG_FSL_FSPI=y |
| 104 | CONFIG_SPI=y | 104 | CONFIG_SPI=y |
| 105 | CONFIG_SPI_FLASH=y | 105 | CONFIG_SPI_FLASH=y |
| 106 | CONFIG_SPI_FLASH_BAR=y | 106 | CONFIG_SPI_FLASH_BAR=y |
| 107 | CONFIG_SPI_FLASH_MACRONIX=y | 107 | CONFIG_SPI_FLASH_MACRONIX=y |
| 108 | CONFIG_SF_DEFAULT_BUS=0 | 108 | CONFIG_SF_DEFAULT_BUS=0 |
| 109 | CONFIG_SF_DEFAULT_CS=0 | 109 | CONFIG_SF_DEFAULT_CS=0 |
| 110 | CONFIG_SF_DEFAULT_SPEED=40000000 | 110 | CONFIG_SF_DEFAULT_SPEED=40000000 |
| 111 | CONFIG_SF_DEFAULT_MODE=0 | 111 | CONFIG_SF_DEFAULT_MODE=0 |
| 112 | 112 | ||
| 113 | CONFIG_DM_ETH=y | 113 | CONFIG_DM_ETH=y |
| 114 | # CONFIG_DM_ETH_PHY=y | 114 | # CONFIG_DM_ETH_PHY=y |
| 115 | CONFIG_DWC_ETH_QOS=y | 115 | CONFIG_DWC_ETH_QOS=y |
| 116 | 116 | ||
| 117 | CONFIG_PHY_GIGE=y | 117 | CONFIG_PHY_GIGE=y |
| 118 | CONFIG_FEC_MXC=y | 118 | CONFIG_FEC_MXC=y |
| 119 | CONFIG_MII=y | 119 | CONFIG_MII=y |
| 120 | CONFIG_PHYLIB=y | 120 | CONFIG_PHYLIB=y |
| 121 | CONFIG_PHY_ATHEROS=y | 121 | CONFIG_PHY_ATHEROS=y |
| 122 | 122 | ||
| 123 | CONFIG_PINCTRL=y | 123 | CONFIG_PINCTRL=y |
| 124 | CONFIG_PINCTRL_IMX8M=y | 124 | CONFIG_PINCTRL_IMX8M=y |
| 125 | CONFIG_DM_REGULATOR=y | 125 | CONFIG_DM_REGULATOR=y |
| 126 | CONFIG_DM_REGULATOR_FIXED=y | 126 | CONFIG_DM_REGULATOR_FIXED=y |
| 127 | CONFIG_DM_REGULATOR_GPIO=y | 127 | CONFIG_DM_REGULATOR_GPIO=y |
| 128 | CONFIG_MXC_UART=y | 128 | CONFIG_MXC_UART=y |
| 129 | CONFIG_SYSRESET=y | 129 | CONFIG_SYSRESET=y |
| 130 | CONFIG_SYSRESET_PSCI=y | 130 | CONFIG_SYSRESET_PSCI=y |
| 131 | CONFIG_DM_THERMAL=y | 131 | CONFIG_DM_THERMAL=y |
| 132 | CONFIG_NXP_TMU=y | 132 | CONFIG_NXP_TMU=y |
| 133 | CONFIG_USB=y | 133 | CONFIG_USB=y |
| 134 | CONFIG_USB_GADGET=y | 134 | CONFIG_USB_GADGET=y |
| 135 | CONFIG_DM_USB=y | 135 | CONFIG_DM_USB=y |
| 136 | 136 | ||
| 137 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 137 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
| 138 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 138 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
| 139 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 139 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
| 140 | CONFIG_USB_GADGET_DOWNLOAD=y | 140 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 141 | CONFIG_USB_XHCI_HCD=y | 141 | CONFIG_USB_XHCI_HCD=y |
| 142 | CONFIG_USB_XHCI_IMX8M=y | 142 | CONFIG_USB_XHCI_IMX8M=y |
| 143 | CONFIG_USB_XHCI_DWC3=y | 143 | CONFIG_USB_XHCI_DWC3=y |
| 144 | CONFIG_USB_DWC3=y | 144 | CONFIG_USB_DWC3=y |
| 145 | CONFIG_USB_DWC3_GADGET=y | 145 | CONFIG_USB_DWC3_GADGET=y |
| 146 | 146 | ||
| 147 | CONFIG_OF_BOARD_SETUP=y | 147 | CONFIG_OF_BOARD_SETUP=y |
| 148 | 148 | ||
| 149 | CONFIG_REGMAP=y | 149 | CONFIG_REGMAP=y |
| 150 | CONFIG_SYSCON=y | 150 | CONFIG_SYSCON=y |
| 151 | CONFIG_VIDEO_IMX_LCDIFV3=y | 151 | CONFIG_VIDEO_IMX_LCDIFV3=y |
| 152 | CONFIG_DM_VIDEO=y | 152 | CONFIG_DM_VIDEO=y |
| 153 | CONFIG_SYS_WHITE_ON_BLACK=y | 153 | CONFIG_SYS_WHITE_ON_BLACK=y |
| 154 | 154 | ||
| 155 | CONFIG_LZ4=y | 155 | CONFIG_LZ4=y |
| 156 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y | 156 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y |
| 157 | CONFIG_APPEND_BOOTARGS=y | 157 | CONFIG_APPEND_BOOTARGS=y |
| 158 | CONFIG_SPL_MMC_SUPPORT=y | 158 | CONFIG_SPL_MMC_SUPPORT=y |
| 159 | CONFIG_AVB_WARNING_LOGO=y | 159 | CONFIG_AVB_WARNING_LOGO=y |
| 160 | CONFIG_AVB_WARNING_LOGO_COLS=0x320 | 160 | CONFIG_AVB_WARNING_LOGO_COLS=0x320 |
| 161 | CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 | 161 | CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 |
| 162 | CONFIG_VIRTUAL_AB_SUPPORT=y | 162 | CONFIG_VIRTUAL_AB_SUPPORT=y |
| 163 | CONFIG_ANDROID_SUPPORT=y | 163 | CONFIG_ANDROID_SUPPORT=y |
| 164 | CONFIG_APPEND_BOOTARGS=y | 164 | CONFIG_APPEND_BOOTARGS=y |
| 165 | CONFIG_ANDROID_AB_SUPPORT=y | 165 | CONFIG_ANDROID_AB_SUPPORT=y |
| 166 | 166 |
configs/smarcimx8mp_4g_ser2_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_SYS_ICACHE_OFF=y | 2 | CONFIG_SPL_SYS_ICACHE_OFF=y |
| 3 | CONFIG_SPL_SYS_DCACHE_OFF=y | 3 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| 4 | CONFIG_ARCH_IMX8M=y | 4 | CONFIG_ARCH_IMX8M=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x40200000 | 5 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| 6 | CONFIG_SPL_GPIO_SUPPORT=y | 6 | CONFIG_SPL_GPIO_SUPPORT=y |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y | 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 10 | CONFIG_SYS_I2C_MXC_I2C1=y | 10 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 11 | CONFIG_SYS_I2C_MXC_I2C2=y | 11 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C3=y | 12 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 13 | CONFIG_SYS_I2C_MXC_I2C4=y | 13 | CONFIG_SYS_I2C_MXC_I2C4=y |
| 14 | CONFIG_SYS_I2C_MXC_I2C6=y | 14 | CONFIG_SYS_I2C_MXC_I2C6=y |
| 15 | CONFIG_ENV_SIZE=0x1000 | 15 | CONFIG_ENV_SIZE=0x1000 |
| 16 | CONFIG_ENV_OFFSET=0x400000 | 16 | CONFIG_ENV_OFFSET=0x400000 |
| 17 | CONFIG_ENV_SECT_SIZE=0x10000 | 17 | CONFIG_ENV_SECT_SIZE=0x10000 |
| 18 | CONFIG_DM_GPIO=y | 18 | CONFIG_DM_GPIO=y |
| 19 | CONFIG_BOOTDELAY=1 | 19 | CONFIG_BOOTDELAY=1 |
| 20 | CONFIG_TARGET_SMARCIMX8MP=y | 20 | CONFIG_TARGET_SMARCIMX8MP=y |
| 21 | CONFIG_ARCH_MISC_INIT=y | 21 | CONFIG_ARCH_MISC_INIT=y |
| 22 | CONFIG_SPL_SERIAL_SUPPORT=y | 22 | CONFIG_SPL_SERIAL_SUPPORT=y |
| 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 24 | CONFIG_SPL=y | 24 | CONFIG_SPL=y |
| 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 26 | CONFIG_CSF_SIZE=0x2000 | 26 | CONFIG_CSF_SIZE=0x2000 |
| 27 | CONFIG_SPL_TEXT_BASE=0x920000 | 27 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 28 | CONFIG_FIT=y | 28 | CONFIG_FIT=y |
| 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 30 | CONFIG_SPL_LOAD_FIT=y | 30 | CONFIG_SPL_LOAD_FIT=y |
| 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" |
| 32 | CONFIG_OF_SYSTEM_SETUP=y | 32 | CONFIG_OF_SYSTEM_SETUP=y |
| 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,4GB_LPDDR4" | 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,4GB_LPDDR4" |
| 34 | CONFIG_CONSOLE_SER2=y | 34 | CONFIG_CONSOLE_SER2=y |
| 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" | 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" |
| 36 | CONFIG_BOARD_LATE_INIT=y | 36 | CONFIG_BOARD_LATE_INIT=y |
| 37 | CONFIG_BOARD_EARLY_INIT_F=y | 37 | CONFIG_BOARD_EARLY_INIT_F=y |
| 38 | CONFIG_SPL_BOARD_INIT=y | 38 | CONFIG_SPL_BOARD_INIT=y |
| 39 | CONFIG_SPL_BOOTROM_SUPPORT=y | 39 | CONFIG_SPL_BOOTROM_SUPPORT=y |
| 40 | CONFIG_SPL_SEPARATE_BSS=y | 40 | CONFIG_SPL_SEPARATE_BSS=y |
| 41 | CONFIG_SPL_I2C_SUPPORT=y | 41 | CONFIG_SPL_I2C_SUPPORT=y |
| 42 | CONFIG_SPL_POWER_SUPPORT=y | 42 | CONFIG_SPL_POWER_SUPPORT=y |
| 43 | CONFIG_NR_DRAM_BANKS=3 | 43 | CONFIG_NR_DRAM_BANKS=3 |
| 44 | CONFIG_HUSH_PARSER=y | 44 | CONFIG_HUSH_PARSER=y |
| 45 | CONFIG_SYS_PROMPT="u-boot$ " | 45 | CONFIG_SYS_PROMPT="u-boot$ " |
| 46 | # CONFIG_CMD_EXPORTENV is not set | 46 | # CONFIG_CMD_EXPORTENV is not set |
| 47 | CONFIG_CMD_IMPORTENV=y | 47 | CONFIG_CMD_IMPORTENV=y |
| 48 | CONFIG_CMD_ERASEENV=y | 48 | CONFIG_CMD_ERASEENV=y |
| 49 | # CONFIG_CMD_CRC32 is not set | 49 | # CONFIG_CMD_CRC32 is not set |
| 50 | # CONFIG_BOOTM_NETBSD is not set | 50 | # CONFIG_BOOTM_NETBSD is not set |
| 51 | CONFIG_CMD_CLK=y | 51 | CONFIG_CMD_CLK=y |
| 52 | CONFIG_CMD_FUSE=y | 52 | CONFIG_CMD_FUSE=y |
| 53 | CONFIG_CMD_GPIO=y | 53 | CONFIG_CMD_GPIO=y |
| 54 | CONFIG_CMD_I2C=y | 54 | CONFIG_CMD_I2C=y |
| 55 | CONFIG_CMD_MMC=y | 55 | CONFIG_CMD_MMC=y |
| 56 | CONFIG_CMD_DHCP=y | 56 | CONFIG_CMD_DHCP=y |
| 57 | CONFIG_CMD_MII=y | 57 | CONFIG_CMD_MII=y |
| 58 | CONFIG_CMD_PING=y | 58 | CONFIG_CMD_PING=y |
| 59 | CONFIG_CMD_CACHE=y | 59 | CONFIG_CMD_CACHE=y |
| 60 | CONFIG_CMD_REGULATOR=y | 60 | CONFIG_CMD_REGULATOR=y |
| 61 | CONFIG_CMD_MEMTEST=y | 61 | CONFIG_CMD_MEMTEST=y |
| 62 | CONFIG_CMD_EXT2=y | 62 | CONFIG_CMD_EXT2=y |
| 63 | CONFIG_CMD_EXT4=y | 63 | CONFIG_CMD_EXT4=y |
| 64 | CONFIG_CMD_EXT4_WRITE=y | 64 | CONFIG_CMD_EXT4_WRITE=y |
| 65 | CONFIG_CMD_FAT=y | 65 | CONFIG_CMD_FAT=y |
| 66 | CONFIG_CMD_SF=y | 66 | CONFIG_CMD_SF=y |
| 67 | CONFIG_CMD_LED=y | 67 | CONFIG_CMD_LED=y |
| 68 | CONFIG_OF_CONTROL=y | 68 | CONFIG_OF_CONTROL=y |
| 69 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" | 69 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" |
| 70 | CONFIG_ENV_IS_IN_MMC=y | 70 | CONFIG_ENV_IS_IN_MMC=y |
| 71 | CONFIG_ENV_IS_IN_SPI_FLASH=y | 71 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 72 | CONFIG_ENV_IS_NOWHERE=y | 72 | CONFIG_ENV_IS_NOWHERE=y |
| 73 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | 73 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 74 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | 74 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 75 | CONFIG_CLK_COMPOSITE_CCF=y | 75 | CONFIG_CLK_COMPOSITE_CCF=y |
| 76 | CONFIG_CLK_IMX8MP=y | 76 | CONFIG_CLK_IMX8MP=y |
| 77 | CONFIG_MXC_GPIO=y | 77 | CONFIG_MXC_GPIO=y |
| 78 | CONFIG_DM_PCA953X=y | 78 | CONFIG_DM_PCA953X=y |
| 79 | CONFIG_FASTBOOT=y | 79 | CONFIG_FASTBOOT=y |
| 80 | CONFIG_USB_FUNCTION_FASTBOOT=y | 80 | CONFIG_USB_FUNCTION_FASTBOOT=y |
| 81 | CONFIG_CMD_FASTBOOT=y | 81 | CONFIG_CMD_FASTBOOT=y |
| 82 | CONFIG_ANDROID_BOOT_IMAGE=y | 82 | CONFIG_ANDROID_BOOT_IMAGE=y |
| 83 | CONFIG_FASTBOOT_UUU_SUPPORT=y | 83 | CONFIG_FASTBOOT_UUU_SUPPORT=y |
| 84 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 84 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
| 85 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 85 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
| 86 | CONFIG_FASTBOOT_FLASH=y | 86 | CONFIG_FASTBOOT_FLASH=y |
| 87 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 | 87 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
| 88 | CONFIG_DM_I2C=y | 88 | CONFIG_DM_I2C=y |
| 89 | CONFIG_CMD_GPT=y | 89 | CONFIG_CMD_GPT=y |
| 90 | CONFIG_CMD_TIME=y | 90 | CONFIG_CMD_TIME=y |
| 91 | CONFIG_SYS_I2C_MXC=y | 91 | CONFIG_SYS_I2C_MXC=y |
| 92 | CONFIG_LED=y | 92 | CONFIG_LED=y |
| 93 | CONFIG_LED_GPIO=y | 93 | CONFIG_LED_GPIO=y |
| 94 | CONFIG_DM_MMC=y | 94 | CONFIG_DM_MMC=y |
| 95 | CONFIG_MMC_IO_VOLTAGE=y | 95 | # CONFIG_MMC_IO_VOLTAGE is not set |
| 96 | CONFIG_MMC_UHS_SUPPORT=y | 96 | CONFIG_MMC_UHS_SUPPORT=y |
| 97 | CONFIG_MMC_HS400_SUPPORT=y | 97 | CONFIG_MMC_HS400_SUPPORT=y |
| 98 | CONFIG_MMC_HS400_ES_SUPPORT=y | 98 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 99 | CONFIG_EFI_PARTITION=y | 99 | CONFIG_EFI_PARTITION=y |
| 100 | CONFIG_SUPPORT_EMMC_BOOT=y | 100 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 101 | CONFIG_FSL_ESDHC_IMX=y | 101 | CONFIG_FSL_ESDHC_IMX=y |
| 102 | CONFIG_DM_SPI_FLASH=y | 102 | CONFIG_DM_SPI_FLASH=y |
| 103 | CONFIG_DM_SPI=y | 103 | CONFIG_DM_SPI=y |
| 104 | CONFIG_FSL_FSPI=y | 104 | CONFIG_FSL_FSPI=y |
| 105 | CONFIG_SPI=y | 105 | CONFIG_SPI=y |
| 106 | CONFIG_SPI_FLASH=y | 106 | CONFIG_SPI_FLASH=y |
| 107 | CONFIG_SPI_FLASH_BAR=y | 107 | CONFIG_SPI_FLASH_BAR=y |
| 108 | CONFIG_SPI_FLASH_MACRONIX=y | 108 | CONFIG_SPI_FLASH_MACRONIX=y |
| 109 | CONFIG_SF_DEFAULT_BUS=0 | 109 | CONFIG_SF_DEFAULT_BUS=0 |
| 110 | CONFIG_SF_DEFAULT_CS=0 | 110 | CONFIG_SF_DEFAULT_CS=0 |
| 111 | CONFIG_SF_DEFAULT_SPEED=40000000 | 111 | CONFIG_SF_DEFAULT_SPEED=40000000 |
| 112 | CONFIG_SF_DEFAULT_MODE=0 | 112 | CONFIG_SF_DEFAULT_MODE=0 |
| 113 | 113 | ||
| 114 | CONFIG_DM_ETH=y | 114 | CONFIG_DM_ETH=y |
| 115 | # CONFIG_DM_ETH_PHY=y | 115 | # CONFIG_DM_ETH_PHY=y |
| 116 | CONFIG_DWC_ETH_QOS=y | 116 | CONFIG_DWC_ETH_QOS=y |
| 117 | 117 | ||
| 118 | CONFIG_PHY_GIGE=y | 118 | CONFIG_PHY_GIGE=y |
| 119 | CONFIG_FEC_MXC=y | 119 | CONFIG_FEC_MXC=y |
| 120 | CONFIG_MII=y | 120 | CONFIG_MII=y |
| 121 | CONFIG_PHYLIB=y | 121 | CONFIG_PHYLIB=y |
| 122 | CONFIG_PHY_ATHEROS=y | 122 | CONFIG_PHY_ATHEROS=y |
| 123 | 123 | ||
| 124 | CONFIG_PINCTRL=y | 124 | CONFIG_PINCTRL=y |
| 125 | CONFIG_PINCTRL_IMX8M=y | 125 | CONFIG_PINCTRL_IMX8M=y |
| 126 | CONFIG_DM_REGULATOR=y | 126 | CONFIG_DM_REGULATOR=y |
| 127 | CONFIG_DM_REGULATOR_FIXED=y | 127 | CONFIG_DM_REGULATOR_FIXED=y |
| 128 | CONFIG_DM_REGULATOR_GPIO=y | 128 | CONFIG_DM_REGULATOR_GPIO=y |
| 129 | CONFIG_MXC_UART=y | 129 | CONFIG_MXC_UART=y |
| 130 | CONFIG_SYSRESET=y | 130 | CONFIG_SYSRESET=y |
| 131 | CONFIG_SYSRESET_PSCI=y | 131 | CONFIG_SYSRESET_PSCI=y |
| 132 | CONFIG_DM_THERMAL=y | 132 | CONFIG_DM_THERMAL=y |
| 133 | CONFIG_NXP_TMU=y | 133 | CONFIG_NXP_TMU=y |
| 134 | CONFIG_USB=y | 134 | CONFIG_USB=y |
| 135 | CONFIG_USB_GADGET=y | 135 | CONFIG_USB_GADGET=y |
| 136 | CONFIG_DM_USB=y | 136 | CONFIG_DM_USB=y |
| 137 | 137 | ||
| 138 | CONFIG_OF_LIBFDT_OVERLAY=y | 138 | CONFIG_OF_LIBFDT_OVERLAY=y |
| 139 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 139 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
| 140 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 140 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
| 141 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 141 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
| 142 | CONFIG_USB_GADGET_DOWNLOAD=y | 142 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 143 | CONFIG_USB_XHCI_HCD=y | 143 | CONFIG_USB_XHCI_HCD=y |
| 144 | CONFIG_USB_XHCI_IMX8M=y | 144 | CONFIG_USB_XHCI_IMX8M=y |
| 145 | CONFIG_USB_XHCI_DWC3=y | 145 | CONFIG_USB_XHCI_DWC3=y |
| 146 | CONFIG_USB_DWC3=y | 146 | CONFIG_USB_DWC3=y |
| 147 | CONFIG_USB_DWC3_GADGET=y | 147 | CONFIG_USB_DWC3_GADGET=y |
| 148 | 148 | ||
| 149 | CONFIG_OF_BOARD_SETUP=y | 149 | CONFIG_OF_BOARD_SETUP=y |
| 150 | 150 | ||
| 151 | CONFIG_REGMAP=y | 151 | CONFIG_REGMAP=y |
| 152 | CONFIG_SYSCON=y | 152 | CONFIG_SYSCON=y |
| 153 | CONFIG_VIDEO_IMX_LCDIFV3=y | 153 | CONFIG_VIDEO_IMX_LCDIFV3=y |
| 154 | CONFIG_DM_VIDEO=y | 154 | CONFIG_DM_VIDEO=y |
| 155 | CONFIG_SYS_WHITE_ON_BLACK=y | 155 | CONFIG_SYS_WHITE_ON_BLACK=y |
| 156 | 156 |
configs/smarcimx8mp_4g_ser3_android_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_SYS_ICACHE_OFF=y | 2 | CONFIG_SPL_SYS_ICACHE_OFF=y |
| 3 | CONFIG_SPL_SYS_DCACHE_OFF=y | 3 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| 4 | CONFIG_ARCH_IMX8M=y | 4 | CONFIG_ARCH_IMX8M=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x40200000 | 5 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| 6 | CONFIG_SPL_GPIO_SUPPORT=y | 6 | CONFIG_SPL_GPIO_SUPPORT=y |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y | 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 10 | CONFIG_SYS_I2C_MXC_I2C1=y | 10 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 11 | CONFIG_SYS_I2C_MXC_I2C2=y | 11 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C3=y | 12 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 13 | CONFIG_SYS_I2C_MXC_I2C4=y | 13 | CONFIG_SYS_I2C_MXC_I2C4=y |
| 14 | CONFIG_SYS_I2C_MXC_I2C6=y | 14 | CONFIG_SYS_I2C_MXC_I2C6=y |
| 15 | CONFIG_ENV_SIZE=0x1000 | 15 | CONFIG_ENV_SIZE=0x1000 |
| 16 | CONFIG_ENV_OFFSET=0x400000 | 16 | CONFIG_ENV_OFFSET=0x400000 |
| 17 | CONFIG_ENV_SECT_SIZE=0x10000 | 17 | CONFIG_ENV_SECT_SIZE=0x10000 |
| 18 | CONFIG_DM_GPIO=y | 18 | CONFIG_DM_GPIO=y |
| 19 | CONFIG_BOOTDELAY=1 | 19 | CONFIG_BOOTDELAY=1 |
| 20 | CONFIG_TARGET_SMARCIMX8MP=y | 20 | CONFIG_TARGET_SMARCIMX8MP=y |
| 21 | CONFIG_ARCH_MISC_INIT=y | 21 | CONFIG_ARCH_MISC_INIT=y |
| 22 | CONFIG_SPL_SERIAL_SUPPORT=y | 22 | CONFIG_SPL_SERIAL_SUPPORT=y |
| 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 24 | CONFIG_SPL=y | 24 | CONFIG_SPL=y |
| 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 26 | CONFIG_CSF_SIZE=0x2000 | 26 | CONFIG_CSF_SIZE=0x2000 |
| 27 | CONFIG_SPL_TEXT_BASE=0x920000 | 27 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 28 | CONFIG_FIT=y | 28 | CONFIG_FIT=y |
| 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 30 | CONFIG_SPL_LOAD_FIT=y | 30 | CONFIG_SPL_LOAD_FIT=y |
| 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" |
| 32 | CONFIG_OF_SYSTEM_SETUP=y | 32 | CONFIG_OF_SYSTEM_SETUP=y |
| 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,4GB_LPDDR4" | 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,4GB_LPDDR4" |
| 34 | CONFIG_CONSOLE_SER3=y | 34 | CONFIG_CONSOLE_SER3=y |
| 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" | 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" |
| 36 | CONFIG_BOARD_LATE_INIT=y | 36 | CONFIG_BOARD_LATE_INIT=y |
| 37 | CONFIG_BOARD_EARLY_INIT_F=y | 37 | CONFIG_BOARD_EARLY_INIT_F=y |
| 38 | CONFIG_SPL_BOARD_INIT=y | 38 | CONFIG_SPL_BOARD_INIT=y |
| 39 | CONFIG_SPL_SEPARATE_BSS=y | 39 | CONFIG_SPL_SEPARATE_BSS=y |
| 40 | CONFIG_SPL_I2C_SUPPORT=y | 40 | CONFIG_SPL_I2C_SUPPORT=y |
| 41 | CONFIG_SPL_POWER_SUPPORT=y | 41 | CONFIG_SPL_POWER_SUPPORT=y |
| 42 | CONFIG_NR_DRAM_BANKS=3 | 42 | CONFIG_NR_DRAM_BANKS=3 |
| 43 | CONFIG_HUSH_PARSER=y | 43 | CONFIG_HUSH_PARSER=y |
| 44 | CONFIG_SYS_PROMPT="u-boot$ " | 44 | CONFIG_SYS_PROMPT="u-boot$ " |
| 45 | # CONFIG_CMD_EXPORTENV is not set | 45 | # CONFIG_CMD_EXPORTENV is not set |
| 46 | CONFIG_CMD_IMPORTENV=y | 46 | CONFIG_CMD_IMPORTENV=y |
| 47 | CONFIG_CMD_ERASEENV=y | 47 | CONFIG_CMD_ERASEENV=y |
| 48 | # CONFIG_CMD_CRC32 is not set | 48 | # CONFIG_CMD_CRC32 is not set |
| 49 | # CONFIG_BOOTM_NETBSD is not set | 49 | # CONFIG_BOOTM_NETBSD is not set |
| 50 | CONFIG_CMD_CLK=y | 50 | CONFIG_CMD_CLK=y |
| 51 | CONFIG_CMD_FUSE=y | 51 | CONFIG_CMD_FUSE=y |
| 52 | CONFIG_CMD_GPIO=y | 52 | CONFIG_CMD_GPIO=y |
| 53 | CONFIG_CMD_I2C=y | 53 | CONFIG_CMD_I2C=y |
| 54 | CONFIG_CMD_MMC=y | 54 | CONFIG_CMD_MMC=y |
| 55 | CONFIG_CMD_DHCP=y | 55 | CONFIG_CMD_DHCP=y |
| 56 | CONFIG_CMD_MII=y | 56 | CONFIG_CMD_MII=y |
| 57 | CONFIG_CMD_PING=y | 57 | CONFIG_CMD_PING=y |
| 58 | CONFIG_CMD_CACHE=y | 58 | CONFIG_CMD_CACHE=y |
| 59 | CONFIG_CMD_REGULATOR=y | 59 | CONFIG_CMD_REGULATOR=y |
| 60 | CONFIG_CMD_MEMTEST=y | 60 | CONFIG_CMD_MEMTEST=y |
| 61 | CONFIG_CMD_EXT2=y | 61 | CONFIG_CMD_EXT2=y |
| 62 | CONFIG_CMD_EXT4=y | 62 | CONFIG_CMD_EXT4=y |
| 63 | CONFIG_CMD_EXT4_WRITE=y | 63 | CONFIG_CMD_EXT4_WRITE=y |
| 64 | CONFIG_CMD_FAT=y | 64 | CONFIG_CMD_FAT=y |
| 65 | CONFIG_CMD_SF=y | 65 | CONFIG_CMD_SF=y |
| 66 | CONFIG_CMD_LED=y | 66 | CONFIG_CMD_LED=y |
| 67 | CONFIG_OF_CONTROL=y | 67 | CONFIG_OF_CONTROL=y |
| 68 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" | 68 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" |
| 69 | CONFIG_ENV_IS_IN_MMC=y | 69 | CONFIG_ENV_IS_IN_MMC=y |
| 70 | CONFIG_ENV_IS_IN_SPI_FLASH=y | 70 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 71 | CONFIG_ENV_IS_NOWHERE=y | 71 | CONFIG_ENV_IS_NOWHERE=y |
| 72 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | 72 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 73 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | 73 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 74 | CONFIG_CLK_COMPOSITE_CCF=y | 74 | CONFIG_CLK_COMPOSITE_CCF=y |
| 75 | CONFIG_CLK_IMX8MP=y | 75 | CONFIG_CLK_IMX8MP=y |
| 76 | CONFIG_MXC_GPIO=y | 76 | CONFIG_MXC_GPIO=y |
| 77 | CONFIG_DM_PCA953X=y | 77 | CONFIG_DM_PCA953X=y |
| 78 | CONFIG_FASTBOOT=y | 78 | CONFIG_FASTBOOT=y |
| 79 | CONFIG_USB_FUNCTION_FASTBOOT=y | 79 | CONFIG_USB_FUNCTION_FASTBOOT=y |
| 80 | CONFIG_CMD_FASTBOOT=y | 80 | CONFIG_CMD_FASTBOOT=y |
| 81 | CONFIG_ANDROID_BOOT_IMAGE=y | 81 | CONFIG_ANDROID_BOOT_IMAGE=y |
| 82 | CONFIG_FASTBOOT_UUU_SUPPORT=n | 82 | CONFIG_FASTBOOT_UUU_SUPPORT=n |
| 83 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 83 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
| 84 | CONFIG_FASTBOOT_BUF_SIZE=0xc800000 | 84 | CONFIG_FASTBOOT_BUF_SIZE=0xc800000 |
| 85 | CONFIG_FASTBOOT_FLASH=y | 85 | CONFIG_FASTBOOT_FLASH=y |
| 86 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 | 86 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
| 87 | CONFIG_DM_I2C=y | 87 | CONFIG_DM_I2C=y |
| 88 | CONFIG_CMD_GPT=y | 88 | CONFIG_CMD_GPT=y |
| 89 | CONFIG_CMD_TIME=y | 89 | CONFIG_CMD_TIME=y |
| 90 | CONFIG_SYS_I2C_MXC=y | 90 | CONFIG_SYS_I2C_MXC=y |
| 91 | CONFIG_LED=y | 91 | CONFIG_LED=y |
| 92 | CONFIG_LED_GPIO=y | 92 | CONFIG_LED_GPIO=y |
| 93 | CONFIG_DM_MMC=y | 93 | CONFIG_DM_MMC=y |
| 94 | CONFIG_MMC_IO_VOLTAGE=y | 94 | # CONFIG_MMC_IO_VOLTAGE is not set |
| 95 | CONFIG_MMC_UHS_SUPPORT=y | 95 | CONFIG_MMC_UHS_SUPPORT=y |
| 96 | CONFIG_MMC_HS400_SUPPORT=y | 96 | CONFIG_MMC_HS400_SUPPORT=y |
| 97 | CONFIG_MMC_HS400_ES_SUPPORT=y | 97 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 98 | CONFIG_EFI_PARTITION=y | 98 | CONFIG_EFI_PARTITION=y |
| 99 | CONFIG_SUPPORT_EMMC_BOOT=y | 99 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 100 | CONFIG_FSL_ESDHC_IMX=y | 100 | CONFIG_FSL_ESDHC_IMX=y |
| 101 | CONFIG_DM_SPI_FLASH=y | 101 | CONFIG_DM_SPI_FLASH=y |
| 102 | CONFIG_DM_SPI=y | 102 | CONFIG_DM_SPI=y |
| 103 | CONFIG_FSL_FSPI=y | 103 | CONFIG_FSL_FSPI=y |
| 104 | CONFIG_SPI=y | 104 | CONFIG_SPI=y |
| 105 | CONFIG_SPI_FLASH=y | 105 | CONFIG_SPI_FLASH=y |
| 106 | CONFIG_SPI_FLASH_BAR=y | 106 | CONFIG_SPI_FLASH_BAR=y |
| 107 | CONFIG_SPI_FLASH_MACRONIX=y | 107 | CONFIG_SPI_FLASH_MACRONIX=y |
| 108 | CONFIG_SF_DEFAULT_BUS=0 | 108 | CONFIG_SF_DEFAULT_BUS=0 |
| 109 | CONFIG_SF_DEFAULT_CS=0 | 109 | CONFIG_SF_DEFAULT_CS=0 |
| 110 | CONFIG_SF_DEFAULT_SPEED=40000000 | 110 | CONFIG_SF_DEFAULT_SPEED=40000000 |
| 111 | CONFIG_SF_DEFAULT_MODE=0 | 111 | CONFIG_SF_DEFAULT_MODE=0 |
| 112 | 112 | ||
| 113 | CONFIG_DM_ETH=y | 113 | CONFIG_DM_ETH=y |
| 114 | # CONFIG_DM_ETH_PHY=y | 114 | # CONFIG_DM_ETH_PHY=y |
| 115 | CONFIG_DWC_ETH_QOS=y | 115 | CONFIG_DWC_ETH_QOS=y |
| 116 | 116 | ||
| 117 | CONFIG_PHY_GIGE=y | 117 | CONFIG_PHY_GIGE=y |
| 118 | CONFIG_FEC_MXC=y | 118 | CONFIG_FEC_MXC=y |
| 119 | CONFIG_MII=y | 119 | CONFIG_MII=y |
| 120 | CONFIG_PHYLIB=y | 120 | CONFIG_PHYLIB=y |
| 121 | CONFIG_PHY_ATHEROS=y | 121 | CONFIG_PHY_ATHEROS=y |
| 122 | 122 | ||
| 123 | CONFIG_PINCTRL=y | 123 | CONFIG_PINCTRL=y |
| 124 | CONFIG_PINCTRL_IMX8M=y | 124 | CONFIG_PINCTRL_IMX8M=y |
| 125 | CONFIG_DM_REGULATOR=y | 125 | CONFIG_DM_REGULATOR=y |
| 126 | CONFIG_DM_REGULATOR_FIXED=y | 126 | CONFIG_DM_REGULATOR_FIXED=y |
| 127 | CONFIG_DM_REGULATOR_GPIO=y | 127 | CONFIG_DM_REGULATOR_GPIO=y |
| 128 | CONFIG_MXC_UART=y | 128 | CONFIG_MXC_UART=y |
| 129 | CONFIG_SYSRESET=y | 129 | CONFIG_SYSRESET=y |
| 130 | CONFIG_SYSRESET_PSCI=y | 130 | CONFIG_SYSRESET_PSCI=y |
| 131 | CONFIG_DM_THERMAL=y | 131 | CONFIG_DM_THERMAL=y |
| 132 | CONFIG_NXP_TMU=y | 132 | CONFIG_NXP_TMU=y |
| 133 | CONFIG_USB=y | 133 | CONFIG_USB=y |
| 134 | CONFIG_USB_GADGET=y | 134 | CONFIG_USB_GADGET=y |
| 135 | CONFIG_DM_USB=y | 135 | CONFIG_DM_USB=y |
| 136 | 136 | ||
| 137 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 137 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
| 138 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 138 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
| 139 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 139 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
| 140 | CONFIG_USB_GADGET_DOWNLOAD=y | 140 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 141 | CONFIG_USB_XHCI_HCD=y | 141 | CONFIG_USB_XHCI_HCD=y |
| 142 | CONFIG_USB_XHCI_IMX8M=y | 142 | CONFIG_USB_XHCI_IMX8M=y |
| 143 | CONFIG_USB_XHCI_DWC3=y | 143 | CONFIG_USB_XHCI_DWC3=y |
| 144 | CONFIG_USB_DWC3=y | 144 | CONFIG_USB_DWC3=y |
| 145 | CONFIG_USB_DWC3_GADGET=y | 145 | CONFIG_USB_DWC3_GADGET=y |
| 146 | 146 | ||
| 147 | CONFIG_OF_BOARD_SETUP=y | 147 | CONFIG_OF_BOARD_SETUP=y |
| 148 | 148 | ||
| 149 | CONFIG_REGMAP=y | 149 | CONFIG_REGMAP=y |
| 150 | CONFIG_SYSCON=y | 150 | CONFIG_SYSCON=y |
| 151 | CONFIG_VIDEO_IMX_LCDIFV3=y | 151 | CONFIG_VIDEO_IMX_LCDIFV3=y |
| 152 | CONFIG_DM_VIDEO=y | 152 | CONFIG_DM_VIDEO=y |
| 153 | CONFIG_SYS_WHITE_ON_BLACK=y | 153 | CONFIG_SYS_WHITE_ON_BLACK=y |
| 154 | 154 | ||
| 155 | CONFIG_LZ4=y | 155 | CONFIG_LZ4=y |
| 156 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y | 156 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y |
| 157 | CONFIG_APPEND_BOOTARGS=y | 157 | CONFIG_APPEND_BOOTARGS=y |
| 158 | CONFIG_SPL_MMC_SUPPORT=y | 158 | CONFIG_SPL_MMC_SUPPORT=y |
| 159 | CONFIG_AVB_WARNING_LOGO=y | 159 | CONFIG_AVB_WARNING_LOGO=y |
| 160 | CONFIG_AVB_WARNING_LOGO_COLS=0x320 | 160 | CONFIG_AVB_WARNING_LOGO_COLS=0x320 |
| 161 | CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 | 161 | CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 |
| 162 | CONFIG_VIRTUAL_AB_SUPPORT=y | 162 | CONFIG_VIRTUAL_AB_SUPPORT=y |
| 163 | CONFIG_ANDROID_SUPPORT=y | 163 | CONFIG_ANDROID_SUPPORT=y |
| 164 | CONFIG_APPEND_BOOTARGS=y | 164 | CONFIG_APPEND_BOOTARGS=y |
| 165 | CONFIG_ANDROID_AB_SUPPORT=y | 165 | CONFIG_ANDROID_AB_SUPPORT=y |
| 166 | 166 |
configs/smarcimx8mp_4g_ser3_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_SYS_ICACHE_OFF=y | 2 | CONFIG_SPL_SYS_ICACHE_OFF=y |
| 3 | CONFIG_SPL_SYS_DCACHE_OFF=y | 3 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| 4 | CONFIG_ARCH_IMX8M=y | 4 | CONFIG_ARCH_IMX8M=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x40200000 | 5 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| 6 | CONFIG_SPL_GPIO_SUPPORT=y | 6 | CONFIG_SPL_GPIO_SUPPORT=y |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y | 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 10 | CONFIG_SYS_I2C_MXC_I2C1=y | 10 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 11 | CONFIG_SYS_I2C_MXC_I2C2=y | 11 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C3=y | 12 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 13 | CONFIG_SYS_I2C_MXC_I2C4=y | 13 | CONFIG_SYS_I2C_MXC_I2C4=y |
| 14 | CONFIG_SYS_I2C_MXC_I2C6=y | 14 | CONFIG_SYS_I2C_MXC_I2C6=y |
| 15 | CONFIG_ENV_SIZE=0x1000 | 15 | CONFIG_ENV_SIZE=0x1000 |
| 16 | CONFIG_ENV_OFFSET=0x400000 | 16 | CONFIG_ENV_OFFSET=0x400000 |
| 17 | CONFIG_ENV_SECT_SIZE=0x10000 | 17 | CONFIG_ENV_SECT_SIZE=0x10000 |
| 18 | CONFIG_DM_GPIO=y | 18 | CONFIG_DM_GPIO=y |
| 19 | CONFIG_BOOTDELAY=1 | 19 | CONFIG_BOOTDELAY=1 |
| 20 | CONFIG_TARGET_SMARCIMX8MP=y | 20 | CONFIG_TARGET_SMARCIMX8MP=y |
| 21 | CONFIG_ARCH_MISC_INIT=y | 21 | CONFIG_ARCH_MISC_INIT=y |
| 22 | CONFIG_SPL_SERIAL_SUPPORT=y | 22 | CONFIG_SPL_SERIAL_SUPPORT=y |
| 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 24 | CONFIG_SPL=y | 24 | CONFIG_SPL=y |
| 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 26 | CONFIG_CSF_SIZE=0x2000 | 26 | CONFIG_CSF_SIZE=0x2000 |
| 27 | CONFIG_SPL_TEXT_BASE=0x920000 | 27 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 28 | CONFIG_FIT=y | 28 | CONFIG_FIT=y |
| 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 30 | CONFIG_SPL_LOAD_FIT=y | 30 | CONFIG_SPL_LOAD_FIT=y |
| 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" |
| 32 | CONFIG_OF_SYSTEM_SETUP=y | 32 | CONFIG_OF_SYSTEM_SETUP=y |
| 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,4GB_LPDDR4" | 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,4GB_LPDDR4" |
| 34 | CONFIG_CONSOLE_SER3=y | 34 | CONFIG_CONSOLE_SER3=y |
| 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" | 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" |
| 36 | CONFIG_BOARD_LATE_INIT=y | 36 | CONFIG_BOARD_LATE_INIT=y |
| 37 | CONFIG_BOARD_EARLY_INIT_F=y | 37 | CONFIG_BOARD_EARLY_INIT_F=y |
| 38 | CONFIG_SPL_BOARD_INIT=y | 38 | CONFIG_SPL_BOARD_INIT=y |
| 39 | CONFIG_SPL_BOOTROM_SUPPORT=y | 39 | CONFIG_SPL_BOOTROM_SUPPORT=y |
| 40 | CONFIG_SPL_SEPARATE_BSS=y | 40 | CONFIG_SPL_SEPARATE_BSS=y |
| 41 | CONFIG_SPL_I2C_SUPPORT=y | 41 | CONFIG_SPL_I2C_SUPPORT=y |
| 42 | CONFIG_SPL_POWER_SUPPORT=y | 42 | CONFIG_SPL_POWER_SUPPORT=y |
| 43 | CONFIG_NR_DRAM_BANKS=3 | 43 | CONFIG_NR_DRAM_BANKS=3 |
| 44 | CONFIG_HUSH_PARSER=y | 44 | CONFIG_HUSH_PARSER=y |
| 45 | CONFIG_SYS_PROMPT="u-boot$ " | 45 | CONFIG_SYS_PROMPT="u-boot$ " |
| 46 | # CONFIG_CMD_EXPORTENV is not set | 46 | # CONFIG_CMD_EXPORTENV is not set |
| 47 | CONFIG_CMD_IMPORTENV=y | 47 | CONFIG_CMD_IMPORTENV=y |
| 48 | CONFIG_CMD_ERASEENV=y | 48 | CONFIG_CMD_ERASEENV=y |
| 49 | # CONFIG_CMD_CRC32 is not set | 49 | # CONFIG_CMD_CRC32 is not set |
| 50 | # CONFIG_BOOTM_NETBSD is not set | 50 | # CONFIG_BOOTM_NETBSD is not set |
| 51 | CONFIG_CMD_CLK=y | 51 | CONFIG_CMD_CLK=y |
| 52 | CONFIG_CMD_FUSE=y | 52 | CONFIG_CMD_FUSE=y |
| 53 | CONFIG_CMD_GPIO=y | 53 | CONFIG_CMD_GPIO=y |
| 54 | CONFIG_CMD_I2C=y | 54 | CONFIG_CMD_I2C=y |
| 55 | CONFIG_CMD_MMC=y | 55 | CONFIG_CMD_MMC=y |
| 56 | CONFIG_CMD_DHCP=y | 56 | CONFIG_CMD_DHCP=y |
| 57 | CONFIG_CMD_MII=y | 57 | CONFIG_CMD_MII=y |
| 58 | CONFIG_CMD_PING=y | 58 | CONFIG_CMD_PING=y |
| 59 | CONFIG_CMD_CACHE=y | 59 | CONFIG_CMD_CACHE=y |
| 60 | CONFIG_CMD_REGULATOR=y | 60 | CONFIG_CMD_REGULATOR=y |
| 61 | CONFIG_CMD_MEMTEST=y | 61 | CONFIG_CMD_MEMTEST=y |
| 62 | CONFIG_CMD_EXT2=y | 62 | CONFIG_CMD_EXT2=y |
| 63 | CONFIG_CMD_EXT4=y | 63 | CONFIG_CMD_EXT4=y |
| 64 | CONFIG_CMD_EXT4_WRITE=y | 64 | CONFIG_CMD_EXT4_WRITE=y |
| 65 | CONFIG_CMD_FAT=y | 65 | CONFIG_CMD_FAT=y |
| 66 | CONFIG_CMD_SF=y | 66 | CONFIG_CMD_SF=y |
| 67 | CONFIG_CMD_LED=y | 67 | CONFIG_CMD_LED=y |
| 68 | CONFIG_OF_CONTROL=y | 68 | CONFIG_OF_CONTROL=y |
| 69 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" | 69 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" |
| 70 | CONFIG_ENV_IS_IN_MMC=y | 70 | CONFIG_ENV_IS_IN_MMC=y |
| 71 | CONFIG_ENV_IS_IN_SPI_FLASH=y | 71 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 72 | CONFIG_ENV_IS_NOWHERE=y | 72 | CONFIG_ENV_IS_NOWHERE=y |
| 73 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | 73 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 74 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | 74 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 75 | CONFIG_CLK_COMPOSITE_CCF=y | 75 | CONFIG_CLK_COMPOSITE_CCF=y |
| 76 | CONFIG_CLK_IMX8MP=y | 76 | CONFIG_CLK_IMX8MP=y |
| 77 | CONFIG_MXC_GPIO=y | 77 | CONFIG_MXC_GPIO=y |
| 78 | CONFIG_DM_PCA953X=y | 78 | CONFIG_DM_PCA953X=y |
| 79 | CONFIG_FASTBOOT=y | 79 | CONFIG_FASTBOOT=y |
| 80 | CONFIG_USB_FUNCTION_FASTBOOT=y | 80 | CONFIG_USB_FUNCTION_FASTBOOT=y |
| 81 | CONFIG_CMD_FASTBOOT=y | 81 | CONFIG_CMD_FASTBOOT=y |
| 82 | CONFIG_ANDROID_BOOT_IMAGE=y | 82 | CONFIG_ANDROID_BOOT_IMAGE=y |
| 83 | CONFIG_FASTBOOT_UUU_SUPPORT=y | 83 | CONFIG_FASTBOOT_UUU_SUPPORT=y |
| 84 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 84 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
| 85 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 85 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
| 86 | CONFIG_FASTBOOT_FLASH=y | 86 | CONFIG_FASTBOOT_FLASH=y |
| 87 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 | 87 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
| 88 | CONFIG_DM_I2C=y | 88 | CONFIG_DM_I2C=y |
| 89 | CONFIG_CMD_GPT=y | 89 | CONFIG_CMD_GPT=y |
| 90 | CONFIG_CMD_TIME=y | 90 | CONFIG_CMD_TIME=y |
| 91 | CONFIG_SYS_I2C_MXC=y | 91 | CONFIG_SYS_I2C_MXC=y |
| 92 | CONFIG_LED=y | 92 | CONFIG_LED=y |
| 93 | CONFIG_LED_GPIO=y | 93 | CONFIG_LED_GPIO=y |
| 94 | CONFIG_DM_MMC=y | 94 | CONFIG_DM_MMC=y |
| 95 | CONFIG_MMC_IO_VOLTAGE=y | 95 | # CONFIG_MMC_IO_VOLTAGE is not set |
| 96 | CONFIG_MMC_UHS_SUPPORT=y | 96 | CONFIG_MMC_UHS_SUPPORT=y |
| 97 | CONFIG_MMC_HS400_SUPPORT=y | 97 | CONFIG_MMC_HS400_SUPPORT=y |
| 98 | CONFIG_MMC_HS400_ES_SUPPORT=y | 98 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 99 | CONFIG_EFI_PARTITION=y | 99 | CONFIG_EFI_PARTITION=y |
| 100 | CONFIG_SUPPORT_EMMC_BOOT=y | 100 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 101 | CONFIG_FSL_ESDHC_IMX=y | 101 | CONFIG_FSL_ESDHC_IMX=y |
| 102 | CONFIG_DM_SPI_FLASH=y | 102 | CONFIG_DM_SPI_FLASH=y |
| 103 | CONFIG_DM_SPI=y | 103 | CONFIG_DM_SPI=y |
| 104 | CONFIG_FSL_FSPI=y | 104 | CONFIG_FSL_FSPI=y |
| 105 | CONFIG_SPI=y | 105 | CONFIG_SPI=y |
| 106 | CONFIG_SPI_FLASH=y | 106 | CONFIG_SPI_FLASH=y |
| 107 | CONFIG_SPI_FLASH_BAR=y | 107 | CONFIG_SPI_FLASH_BAR=y |
| 108 | CONFIG_SPI_FLASH_MACRONIX=y | 108 | CONFIG_SPI_FLASH_MACRONIX=y |
| 109 | CONFIG_SF_DEFAULT_BUS=0 | 109 | CONFIG_SF_DEFAULT_BUS=0 |
| 110 | CONFIG_SF_DEFAULT_CS=0 | 110 | CONFIG_SF_DEFAULT_CS=0 |
| 111 | CONFIG_SF_DEFAULT_SPEED=40000000 | 111 | CONFIG_SF_DEFAULT_SPEED=40000000 |
| 112 | CONFIG_SF_DEFAULT_MODE=0 | 112 | CONFIG_SF_DEFAULT_MODE=0 |
| 113 | 113 | ||
| 114 | CONFIG_DM_ETH=y | 114 | CONFIG_DM_ETH=y |
| 115 | # CONFIG_DM_ETH_PHY=y | 115 | # CONFIG_DM_ETH_PHY=y |
| 116 | CONFIG_DWC_ETH_QOS=y | 116 | CONFIG_DWC_ETH_QOS=y |
| 117 | 117 | ||
| 118 | CONFIG_PHY_GIGE=y | 118 | CONFIG_PHY_GIGE=y |
| 119 | CONFIG_FEC_MXC=y | 119 | CONFIG_FEC_MXC=y |
| 120 | CONFIG_MII=y | 120 | CONFIG_MII=y |
| 121 | CONFIG_PHYLIB=y | 121 | CONFIG_PHYLIB=y |
| 122 | CONFIG_PHY_ATHEROS=y | 122 | CONFIG_PHY_ATHEROS=y |
| 123 | 123 | ||
| 124 | CONFIG_PINCTRL=y | 124 | CONFIG_PINCTRL=y |
| 125 | CONFIG_PINCTRL_IMX8M=y | 125 | CONFIG_PINCTRL_IMX8M=y |
| 126 | CONFIG_DM_REGULATOR=y | 126 | CONFIG_DM_REGULATOR=y |
| 127 | CONFIG_DM_REGULATOR_FIXED=y | 127 | CONFIG_DM_REGULATOR_FIXED=y |
| 128 | CONFIG_DM_REGULATOR_GPIO=y | 128 | CONFIG_DM_REGULATOR_GPIO=y |
| 129 | CONFIG_MXC_UART=y | 129 | CONFIG_MXC_UART=y |
| 130 | CONFIG_SYSRESET=y | 130 | CONFIG_SYSRESET=y |
| 131 | CONFIG_SYSRESET_PSCI=y | 131 | CONFIG_SYSRESET_PSCI=y |
| 132 | CONFIG_DM_THERMAL=y | 132 | CONFIG_DM_THERMAL=y |
| 133 | CONFIG_NXP_TMU=y | 133 | CONFIG_NXP_TMU=y |
| 134 | CONFIG_USB=y | 134 | CONFIG_USB=y |
| 135 | CONFIG_USB_GADGET=y | 135 | CONFIG_USB_GADGET=y |
| 136 | CONFIG_DM_USB=y | 136 | CONFIG_DM_USB=y |
| 137 | 137 | ||
| 138 | CONFIG_OF_LIBFDT_OVERLAY=y | 138 | CONFIG_OF_LIBFDT_OVERLAY=y |
| 139 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 139 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
| 140 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 140 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
| 141 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 141 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
| 142 | CONFIG_USB_GADGET_DOWNLOAD=y | 142 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 143 | CONFIG_USB_XHCI_HCD=y | 143 | CONFIG_USB_XHCI_HCD=y |
| 144 | CONFIG_USB_XHCI_IMX8M=y | 144 | CONFIG_USB_XHCI_IMX8M=y |
| 145 | CONFIG_USB_XHCI_DWC3=y | 145 | CONFIG_USB_XHCI_DWC3=y |
| 146 | CONFIG_USB_DWC3=y | 146 | CONFIG_USB_DWC3=y |
| 147 | CONFIG_USB_DWC3_GADGET=y | 147 | CONFIG_USB_DWC3_GADGET=y |
| 148 | 148 | ||
| 149 | CONFIG_OF_BOARD_SETUP=y | 149 | CONFIG_OF_BOARD_SETUP=y |
| 150 | 150 | ||
| 151 | CONFIG_REGMAP=y | 151 | CONFIG_REGMAP=y |
| 152 | CONFIG_SYSCON=y | 152 | CONFIG_SYSCON=y |
| 153 | CONFIG_VIDEO_IMX_LCDIFV3=y | 153 | CONFIG_VIDEO_IMX_LCDIFV3=y |
| 154 | CONFIG_DM_VIDEO=y | 154 | CONFIG_DM_VIDEO=y |
| 155 | CONFIG_SYS_WHITE_ON_BLACK=y | 155 | CONFIG_SYS_WHITE_ON_BLACK=y |
| 156 | 156 |
configs/smarcimx8mp_6g_ser0_android_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_SYS_ICACHE_OFF=y | 2 | CONFIG_SPL_SYS_ICACHE_OFF=y |
| 3 | CONFIG_SPL_SYS_DCACHE_OFF=y | 3 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| 4 | CONFIG_ARCH_IMX8M=y | 4 | CONFIG_ARCH_IMX8M=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x40200000 | 5 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| 6 | CONFIG_SPL_GPIO_SUPPORT=y | 6 | CONFIG_SPL_GPIO_SUPPORT=y |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y | 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 10 | CONFIG_SYS_I2C_MXC_I2C1=y | 10 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 11 | CONFIG_SYS_I2C_MXC_I2C2=y | 11 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C3=y | 12 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 13 | CONFIG_SYS_I2C_MXC_I2C4=y | 13 | CONFIG_SYS_I2C_MXC_I2C4=y |
| 14 | CONFIG_SYS_I2C_MXC_I2C6=y | 14 | CONFIG_SYS_I2C_MXC_I2C6=y |
| 15 | CONFIG_ENV_SIZE=0x1000 | 15 | CONFIG_ENV_SIZE=0x1000 |
| 16 | CONFIG_ENV_OFFSET=0x400000 | 16 | CONFIG_ENV_OFFSET=0x400000 |
| 17 | CONFIG_ENV_SECT_SIZE=0x10000 | 17 | CONFIG_ENV_SECT_SIZE=0x10000 |
| 18 | CONFIG_DM_GPIO=y | 18 | CONFIG_DM_GPIO=y |
| 19 | CONFIG_BOOTDELAY=1 | 19 | CONFIG_BOOTDELAY=1 |
| 20 | CONFIG_TARGET_SMARCIMX8MP=y | 20 | CONFIG_TARGET_SMARCIMX8MP=y |
| 21 | CONFIG_ARCH_MISC_INIT=y | 21 | CONFIG_ARCH_MISC_INIT=y |
| 22 | CONFIG_SPL_SERIAL_SUPPORT=y | 22 | CONFIG_SPL_SERIAL_SUPPORT=y |
| 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 24 | CONFIG_SPL=y | 24 | CONFIG_SPL=y |
| 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 26 | CONFIG_CSF_SIZE=0x2000 | 26 | CONFIG_CSF_SIZE=0x2000 |
| 27 | CONFIG_SPL_TEXT_BASE=0x920000 | 27 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 28 | CONFIG_FIT=y | 28 | CONFIG_FIT=y |
| 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 30 | CONFIG_SPL_LOAD_FIT=y | 30 | CONFIG_SPL_LOAD_FIT=y |
| 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" |
| 32 | CONFIG_OF_SYSTEM_SETUP=y | 32 | CONFIG_OF_SYSTEM_SETUP=y |
| 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,6GB_LPDDR4" | 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,6GB_LPDDR4" |
| 34 | CONFIG_CONSOLE_SER0=y | 34 | CONFIG_CONSOLE_SER0=y |
| 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" | 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" |
| 36 | CONFIG_BOARD_LATE_INIT=y | 36 | CONFIG_BOARD_LATE_INIT=y |
| 37 | CONFIG_BOARD_EARLY_INIT_F=y | 37 | CONFIG_BOARD_EARLY_INIT_F=y |
| 38 | CONFIG_SPL_BOARD_INIT=y | 38 | CONFIG_SPL_BOARD_INIT=y |
| 39 | CONFIG_SPL_SEPARATE_BSS=y | 39 | CONFIG_SPL_SEPARATE_BSS=y |
| 40 | CONFIG_SPL_I2C_SUPPORT=y | 40 | CONFIG_SPL_I2C_SUPPORT=y |
| 41 | CONFIG_SPL_POWER_SUPPORT=y | 41 | CONFIG_SPL_POWER_SUPPORT=y |
| 42 | CONFIG_NR_DRAM_BANKS=3 | 42 | CONFIG_NR_DRAM_BANKS=3 |
| 43 | CONFIG_HUSH_PARSER=y | 43 | CONFIG_HUSH_PARSER=y |
| 44 | CONFIG_SYS_PROMPT="u-boot$ " | 44 | CONFIG_SYS_PROMPT="u-boot$ " |
| 45 | # CONFIG_CMD_EXPORTENV is not set | 45 | # CONFIG_CMD_EXPORTENV is not set |
| 46 | CONFIG_CMD_IMPORTENV=y | 46 | CONFIG_CMD_IMPORTENV=y |
| 47 | CONFIG_CMD_ERASEENV=y | 47 | CONFIG_CMD_ERASEENV=y |
| 48 | # CONFIG_CMD_CRC32 is not set | 48 | # CONFIG_CMD_CRC32 is not set |
| 49 | # CONFIG_BOOTM_NETBSD is not set | 49 | # CONFIG_BOOTM_NETBSD is not set |
| 50 | CONFIG_CMD_CLK=y | 50 | CONFIG_CMD_CLK=y |
| 51 | CONFIG_CMD_FUSE=y | 51 | CONFIG_CMD_FUSE=y |
| 52 | CONFIG_CMD_GPIO=y | 52 | CONFIG_CMD_GPIO=y |
| 53 | CONFIG_CMD_I2C=y | 53 | CONFIG_CMD_I2C=y |
| 54 | CONFIG_CMD_MMC=y | 54 | CONFIG_CMD_MMC=y |
| 55 | CONFIG_CMD_DHCP=y | 55 | CONFIG_CMD_DHCP=y |
| 56 | CONFIG_CMD_MII=y | 56 | CONFIG_CMD_MII=y |
| 57 | CONFIG_CMD_PING=y | 57 | CONFIG_CMD_PING=y |
| 58 | CONFIG_CMD_CACHE=y | 58 | CONFIG_CMD_CACHE=y |
| 59 | CONFIG_CMD_REGULATOR=y | 59 | CONFIG_CMD_REGULATOR=y |
| 60 | CONFIG_CMD_MEMTEST=y | 60 | CONFIG_CMD_MEMTEST=y |
| 61 | CONFIG_CMD_EXT2=y | 61 | CONFIG_CMD_EXT2=y |
| 62 | CONFIG_CMD_EXT4=y | 62 | CONFIG_CMD_EXT4=y |
| 63 | CONFIG_CMD_EXT4_WRITE=y | 63 | CONFIG_CMD_EXT4_WRITE=y |
| 64 | CONFIG_CMD_FAT=y | 64 | CONFIG_CMD_FAT=y |
| 65 | CONFIG_CMD_SF=y | 65 | CONFIG_CMD_SF=y |
| 66 | CONFIG_CMD_LED=y | 66 | CONFIG_CMD_LED=y |
| 67 | CONFIG_OF_CONTROL=y | 67 | CONFIG_OF_CONTROL=y |
| 68 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" | 68 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" |
| 69 | CONFIG_ENV_IS_IN_MMC=y | 69 | CONFIG_ENV_IS_IN_MMC=y |
| 70 | CONFIG_ENV_IS_IN_SPI_FLASH=y | 70 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 71 | CONFIG_ENV_IS_NOWHERE=y | 71 | CONFIG_ENV_IS_NOWHERE=y |
| 72 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | 72 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 73 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | 73 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 74 | CONFIG_CLK_COMPOSITE_CCF=y | 74 | CONFIG_CLK_COMPOSITE_CCF=y |
| 75 | CONFIG_CLK_IMX8MP=y | 75 | CONFIG_CLK_IMX8MP=y |
| 76 | CONFIG_MXC_GPIO=y | 76 | CONFIG_MXC_GPIO=y |
| 77 | CONFIG_DM_PCA953X=y | 77 | CONFIG_DM_PCA953X=y |
| 78 | CONFIG_FASTBOOT=y | 78 | CONFIG_FASTBOOT=y |
| 79 | CONFIG_USB_FUNCTION_FASTBOOT=y | 79 | CONFIG_USB_FUNCTION_FASTBOOT=y |
| 80 | CONFIG_CMD_FASTBOOT=y | 80 | CONFIG_CMD_FASTBOOT=y |
| 81 | CONFIG_ANDROID_BOOT_IMAGE=y | 81 | CONFIG_ANDROID_BOOT_IMAGE=y |
| 82 | CONFIG_FASTBOOT_UUU_SUPPORT=n | 82 | CONFIG_FASTBOOT_UUU_SUPPORT=n |
| 83 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 83 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
| 84 | CONFIG_FASTBOOT_BUF_SIZE=0xc800000 | 84 | CONFIG_FASTBOOT_BUF_SIZE=0xc800000 |
| 85 | CONFIG_FASTBOOT_FLASH=y | 85 | CONFIG_FASTBOOT_FLASH=y |
| 86 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 | 86 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
| 87 | CONFIG_DM_I2C=y | 87 | CONFIG_DM_I2C=y |
| 88 | CONFIG_CMD_GPT=y | 88 | CONFIG_CMD_GPT=y |
| 89 | CONFIG_CMD_TIME=y | 89 | CONFIG_CMD_TIME=y |
| 90 | CONFIG_SYS_I2C_MXC=y | 90 | CONFIG_SYS_I2C_MXC=y |
| 91 | CONFIG_LED=y | 91 | CONFIG_LED=y |
| 92 | CONFIG_LED_GPIO=y | 92 | CONFIG_LED_GPIO=y |
| 93 | CONFIG_DM_MMC=y | 93 | CONFIG_DM_MMC=y |
| 94 | CONFIG_MMC_IO_VOLTAGE=y | 94 | # CONFIG_MMC_IO_VOLTAGE is not set |
| 95 | CONFIG_MMC_UHS_SUPPORT=y | 95 | CONFIG_MMC_UHS_SUPPORT=y |
| 96 | CONFIG_MMC_HS400_SUPPORT=y | 96 | CONFIG_MMC_HS400_SUPPORT=y |
| 97 | CONFIG_MMC_HS400_ES_SUPPORT=y | 97 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 98 | CONFIG_EFI_PARTITION=y | 98 | CONFIG_EFI_PARTITION=y |
| 99 | CONFIG_SUPPORT_EMMC_BOOT=y | 99 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 100 | CONFIG_FSL_ESDHC_IMX=y | 100 | CONFIG_FSL_ESDHC_IMX=y |
| 101 | CONFIG_DM_SPI_FLASH=y | 101 | CONFIG_DM_SPI_FLASH=y |
| 102 | CONFIG_DM_SPI=y | 102 | CONFIG_DM_SPI=y |
| 103 | CONFIG_FSL_FSPI=y | 103 | CONFIG_FSL_FSPI=y |
| 104 | CONFIG_SPI=y | 104 | CONFIG_SPI=y |
| 105 | CONFIG_SPI_FLASH=y | 105 | CONFIG_SPI_FLASH=y |
| 106 | CONFIG_SPI_FLASH_BAR=y | 106 | CONFIG_SPI_FLASH_BAR=y |
| 107 | CONFIG_SPI_FLASH_MACRONIX=y | 107 | CONFIG_SPI_FLASH_MACRONIX=y |
| 108 | CONFIG_SF_DEFAULT_BUS=0 | 108 | CONFIG_SF_DEFAULT_BUS=0 |
| 109 | CONFIG_SF_DEFAULT_CS=0 | 109 | CONFIG_SF_DEFAULT_CS=0 |
| 110 | CONFIG_SF_DEFAULT_SPEED=40000000 | 110 | CONFIG_SF_DEFAULT_SPEED=40000000 |
| 111 | CONFIG_SF_DEFAULT_MODE=0 | 111 | CONFIG_SF_DEFAULT_MODE=0 |
| 112 | 112 | ||
| 113 | CONFIG_DM_ETH=y | 113 | CONFIG_DM_ETH=y |
| 114 | # CONFIG_DM_ETH_PHY=y | 114 | # CONFIG_DM_ETH_PHY=y |
| 115 | CONFIG_DWC_ETH_QOS=y | 115 | CONFIG_DWC_ETH_QOS=y |
| 116 | 116 | ||
| 117 | CONFIG_PHY_GIGE=y | 117 | CONFIG_PHY_GIGE=y |
| 118 | CONFIG_FEC_MXC=y | 118 | CONFIG_FEC_MXC=y |
| 119 | CONFIG_MII=y | 119 | CONFIG_MII=y |
| 120 | CONFIG_PHYLIB=y | 120 | CONFIG_PHYLIB=y |
| 121 | CONFIG_PHY_ATHEROS=y | 121 | CONFIG_PHY_ATHEROS=y |
| 122 | 122 | ||
| 123 | CONFIG_PINCTRL=y | 123 | CONFIG_PINCTRL=y |
| 124 | CONFIG_PINCTRL_IMX8M=y | 124 | CONFIG_PINCTRL_IMX8M=y |
| 125 | CONFIG_DM_REGULATOR=y | 125 | CONFIG_DM_REGULATOR=y |
| 126 | CONFIG_DM_REGULATOR_FIXED=y | 126 | CONFIG_DM_REGULATOR_FIXED=y |
| 127 | CONFIG_DM_REGULATOR_GPIO=y | 127 | CONFIG_DM_REGULATOR_GPIO=y |
| 128 | CONFIG_MXC_UART=y | 128 | CONFIG_MXC_UART=y |
| 129 | CONFIG_SYSRESET=y | 129 | CONFIG_SYSRESET=y |
| 130 | CONFIG_SYSRESET_PSCI=y | 130 | CONFIG_SYSRESET_PSCI=y |
| 131 | CONFIG_DM_THERMAL=y | 131 | CONFIG_DM_THERMAL=y |
| 132 | CONFIG_NXP_TMU=y | 132 | CONFIG_NXP_TMU=y |
| 133 | CONFIG_USB=y | 133 | CONFIG_USB=y |
| 134 | CONFIG_USB_GADGET=y | 134 | CONFIG_USB_GADGET=y |
| 135 | CONFIG_DM_USB=y | 135 | CONFIG_DM_USB=y |
| 136 | 136 | ||
| 137 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 137 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
| 138 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 138 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
| 139 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 139 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
| 140 | CONFIG_USB_GADGET_DOWNLOAD=y | 140 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 141 | CONFIG_USB_XHCI_HCD=y | 141 | CONFIG_USB_XHCI_HCD=y |
| 142 | CONFIG_USB_XHCI_IMX8M=y | 142 | CONFIG_USB_XHCI_IMX8M=y |
| 143 | CONFIG_USB_XHCI_DWC3=y | 143 | CONFIG_USB_XHCI_DWC3=y |
| 144 | CONFIG_USB_DWC3=y | 144 | CONFIG_USB_DWC3=y |
| 145 | CONFIG_USB_DWC3_GADGET=y | 145 | CONFIG_USB_DWC3_GADGET=y |
| 146 | 146 | ||
| 147 | CONFIG_OF_BOARD_SETUP=y | 147 | CONFIG_OF_BOARD_SETUP=y |
| 148 | 148 | ||
| 149 | CONFIG_REGMAP=y | 149 | CONFIG_REGMAP=y |
| 150 | CONFIG_SYSCON=y | 150 | CONFIG_SYSCON=y |
| 151 | CONFIG_VIDEO_IMX_LCDIFV3=y | 151 | CONFIG_VIDEO_IMX_LCDIFV3=y |
| 152 | CONFIG_DM_VIDEO=y | 152 | CONFIG_DM_VIDEO=y |
| 153 | CONFIG_SYS_WHITE_ON_BLACK=y | 153 | CONFIG_SYS_WHITE_ON_BLACK=y |
| 154 | 154 | ||
| 155 | CONFIG_LZ4=y | 155 | CONFIG_LZ4=y |
| 156 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y | 156 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y |
| 157 | CONFIG_APPEND_BOOTARGS=y | 157 | CONFIG_APPEND_BOOTARGS=y |
| 158 | CONFIG_SPL_MMC_SUPPORT=y | 158 | CONFIG_SPL_MMC_SUPPORT=y |
| 159 | CONFIG_AVB_WARNING_LOGO=y | 159 | CONFIG_AVB_WARNING_LOGO=y |
| 160 | CONFIG_AVB_WARNING_LOGO_COLS=0x320 | 160 | CONFIG_AVB_WARNING_LOGO_COLS=0x320 |
| 161 | CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 | 161 | CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 |
| 162 | CONFIG_VIRTUAL_AB_SUPPORT=y | 162 | CONFIG_VIRTUAL_AB_SUPPORT=y |
| 163 | CONFIG_ANDROID_SUPPORT=y | 163 | CONFIG_ANDROID_SUPPORT=y |
| 164 | CONFIG_APPEND_BOOTARGS=y | 164 | CONFIG_APPEND_BOOTARGS=y |
| 165 | CONFIG_ANDROID_AB_SUPPORT=y | 165 | CONFIG_ANDROID_AB_SUPPORT=y |
| 166 | 166 |
configs/smarcimx8mp_6g_ser0_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_SYS_ICACHE_OFF=y | 2 | CONFIG_SPL_SYS_ICACHE_OFF=y |
| 3 | CONFIG_SPL_SYS_DCACHE_OFF=y | 3 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| 4 | CONFIG_ARCH_IMX8M=y | 4 | CONFIG_ARCH_IMX8M=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x40200000 | 5 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| 6 | CONFIG_SPL_GPIO_SUPPORT=y | 6 | CONFIG_SPL_GPIO_SUPPORT=y |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y | 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 10 | CONFIG_SYS_I2C_MXC_I2C1=y | 10 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 11 | CONFIG_SYS_I2C_MXC_I2C2=y | 11 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C3=y | 12 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 13 | CONFIG_SYS_I2C_MXC_I2C4=y | 13 | CONFIG_SYS_I2C_MXC_I2C4=y |
| 14 | CONFIG_SYS_I2C_MXC_I2C6=y | 14 | CONFIG_SYS_I2C_MXC_I2C6=y |
| 15 | CONFIG_ENV_SIZE=0x1000 | 15 | CONFIG_ENV_SIZE=0x1000 |
| 16 | CONFIG_ENV_OFFSET=0x400000 | 16 | CONFIG_ENV_OFFSET=0x400000 |
| 17 | CONFIG_ENV_SECT_SIZE=0x10000 | 17 | CONFIG_ENV_SECT_SIZE=0x10000 |
| 18 | CONFIG_DM_GPIO=y | 18 | CONFIG_DM_GPIO=y |
| 19 | CONFIG_BOOTDELAY=1 | 19 | CONFIG_BOOTDELAY=1 |
| 20 | CONFIG_TARGET_SMARCIMX8MP=y | 20 | CONFIG_TARGET_SMARCIMX8MP=y |
| 21 | CONFIG_ARCH_MISC_INIT=y | 21 | CONFIG_ARCH_MISC_INIT=y |
| 22 | CONFIG_SPL_SERIAL_SUPPORT=y | 22 | CONFIG_SPL_SERIAL_SUPPORT=y |
| 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 24 | CONFIG_SPL=y | 24 | CONFIG_SPL=y |
| 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 26 | CONFIG_CSF_SIZE=0x2000 | 26 | CONFIG_CSF_SIZE=0x2000 |
| 27 | CONFIG_SPL_TEXT_BASE=0x920000 | 27 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 28 | CONFIG_FIT=y | 28 | CONFIG_FIT=y |
| 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 30 | CONFIG_SPL_LOAD_FIT=y | 30 | CONFIG_SPL_LOAD_FIT=y |
| 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" |
| 32 | CONFIG_OF_SYSTEM_SETUP=y | 32 | CONFIG_OF_SYSTEM_SETUP=y |
| 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,6GB_LPDDR4" | 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,6GB_LPDDR4" |
| 34 | CONFIG_CONSOLE_SER0=y | 34 | CONFIG_CONSOLE_SER0=y |
| 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" | 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" |
| 36 | CONFIG_BOARD_LATE_INIT=y | 36 | CONFIG_BOARD_LATE_INIT=y |
| 37 | CONFIG_BOARD_EARLY_INIT_F=y | 37 | CONFIG_BOARD_EARLY_INIT_F=y |
| 38 | CONFIG_SPL_BOARD_INIT=y | 38 | CONFIG_SPL_BOARD_INIT=y |
| 39 | CONFIG_SPL_BOOTROM_SUPPORT=y | 39 | CONFIG_SPL_BOOTROM_SUPPORT=y |
| 40 | CONFIG_SPL_SEPARATE_BSS=y | 40 | CONFIG_SPL_SEPARATE_BSS=y |
| 41 | CONFIG_SPL_I2C_SUPPORT=y | 41 | CONFIG_SPL_I2C_SUPPORT=y |
| 42 | CONFIG_SPL_POWER_SUPPORT=y | 42 | CONFIG_SPL_POWER_SUPPORT=y |
| 43 | CONFIG_NR_DRAM_BANKS=3 | 43 | CONFIG_NR_DRAM_BANKS=3 |
| 44 | CONFIG_HUSH_PARSER=y | 44 | CONFIG_HUSH_PARSER=y |
| 45 | CONFIG_SYS_PROMPT="u-boot$ " | 45 | CONFIG_SYS_PROMPT="u-boot$ " |
| 46 | # CONFIG_CMD_EXPORTENV is not set | 46 | # CONFIG_CMD_EXPORTENV is not set |
| 47 | CONFIG_CMD_IMPORTENV=y | 47 | CONFIG_CMD_IMPORTENV=y |
| 48 | CONFIG_CMD_ERASEENV=y | 48 | CONFIG_CMD_ERASEENV=y |
| 49 | # CONFIG_CMD_CRC32 is not set | 49 | # CONFIG_CMD_CRC32 is not set |
| 50 | # CONFIG_BOOTM_NETBSD is not set | 50 | # CONFIG_BOOTM_NETBSD is not set |
| 51 | CONFIG_CMD_CLK=y | 51 | CONFIG_CMD_CLK=y |
| 52 | CONFIG_CMD_FUSE=y | 52 | CONFIG_CMD_FUSE=y |
| 53 | CONFIG_CMD_GPIO=y | 53 | CONFIG_CMD_GPIO=y |
| 54 | CONFIG_CMD_I2C=y | 54 | CONFIG_CMD_I2C=y |
| 55 | CONFIG_CMD_MMC=y | 55 | CONFIG_CMD_MMC=y |
| 56 | CONFIG_CMD_DHCP=y | 56 | CONFIG_CMD_DHCP=y |
| 57 | CONFIG_CMD_MII=y | 57 | CONFIG_CMD_MII=y |
| 58 | CONFIG_CMD_PING=y | 58 | CONFIG_CMD_PING=y |
| 59 | CONFIG_CMD_CACHE=y | 59 | CONFIG_CMD_CACHE=y |
| 60 | CONFIG_CMD_REGULATOR=y | 60 | CONFIG_CMD_REGULATOR=y |
| 61 | CONFIG_CMD_MEMTEST=y | 61 | CONFIG_CMD_MEMTEST=y |
| 62 | CONFIG_CMD_EXT2=y | 62 | CONFIG_CMD_EXT2=y |
| 63 | CONFIG_CMD_EXT4=y | 63 | CONFIG_CMD_EXT4=y |
| 64 | CONFIG_CMD_EXT4_WRITE=y | 64 | CONFIG_CMD_EXT4_WRITE=y |
| 65 | CONFIG_CMD_FAT=y | 65 | CONFIG_CMD_FAT=y |
| 66 | CONFIG_CMD_SF=y | 66 | CONFIG_CMD_SF=y |
| 67 | CONFIG_CMD_LED=y | 67 | CONFIG_CMD_LED=y |
| 68 | CONFIG_OF_CONTROL=y | 68 | CONFIG_OF_CONTROL=y |
| 69 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" | 69 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" |
| 70 | CONFIG_ENV_IS_IN_MMC=y | 70 | CONFIG_ENV_IS_IN_MMC=y |
| 71 | CONFIG_ENV_IS_IN_SPI_FLASH=y | 71 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 72 | CONFIG_ENV_IS_NOWHERE=y | 72 | CONFIG_ENV_IS_NOWHERE=y |
| 73 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | 73 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 74 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | 74 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 75 | CONFIG_CLK_COMPOSITE_CCF=y | 75 | CONFIG_CLK_COMPOSITE_CCF=y |
| 76 | CONFIG_CLK_IMX8MP=y | 76 | CONFIG_CLK_IMX8MP=y |
| 77 | CONFIG_MXC_GPIO=y | 77 | CONFIG_MXC_GPIO=y |
| 78 | CONFIG_DM_PCA953X=y | 78 | CONFIG_DM_PCA953X=y |
| 79 | CONFIG_FASTBOOT=y | 79 | CONFIG_FASTBOOT=y |
| 80 | CONFIG_USB_FUNCTION_FASTBOOT=y | 80 | CONFIG_USB_FUNCTION_FASTBOOT=y |
| 81 | CONFIG_CMD_FASTBOOT=y | 81 | CONFIG_CMD_FASTBOOT=y |
| 82 | CONFIG_ANDROID_BOOT_IMAGE=y | 82 | CONFIG_ANDROID_BOOT_IMAGE=y |
| 83 | CONFIG_FASTBOOT_UUU_SUPPORT=y | 83 | CONFIG_FASTBOOT_UUU_SUPPORT=y |
| 84 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 84 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
| 85 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 85 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
| 86 | CONFIG_FASTBOOT_FLASH=y | 86 | CONFIG_FASTBOOT_FLASH=y |
| 87 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 | 87 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
| 88 | CONFIG_DM_I2C=y | 88 | CONFIG_DM_I2C=y |
| 89 | CONFIG_CMD_GPT=y | 89 | CONFIG_CMD_GPT=y |
| 90 | CONFIG_CMD_TIME=y | 90 | CONFIG_CMD_TIME=y |
| 91 | CONFIG_SYS_I2C_MXC=y | 91 | CONFIG_SYS_I2C_MXC=y |
| 92 | CONFIG_LED=y | 92 | CONFIG_LED=y |
| 93 | CONFIG_LED_GPIO=y | 93 | CONFIG_LED_GPIO=y |
| 94 | CONFIG_DM_MMC=y | 94 | CONFIG_DM_MMC=y |
| 95 | CONFIG_MMC_IO_VOLTAGE=y | 95 | # CONFIG_MMC_IO_VOLTAGE is not set |
| 96 | CONFIG_MMC_UHS_SUPPORT=y | 96 | CONFIG_MMC_UHS_SUPPORT=y |
| 97 | CONFIG_MMC_HS400_SUPPORT=y | 97 | CONFIG_MMC_HS400_SUPPORT=y |
| 98 | CONFIG_MMC_HS400_ES_SUPPORT=y | 98 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 99 | CONFIG_EFI_PARTITION=y | 99 | CONFIG_EFI_PARTITION=y |
| 100 | CONFIG_SUPPORT_EMMC_BOOT=y | 100 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 101 | CONFIG_FSL_ESDHC_IMX=y | 101 | CONFIG_FSL_ESDHC_IMX=y |
| 102 | CONFIG_DM_SPI_FLASH=y | 102 | CONFIG_DM_SPI_FLASH=y |
| 103 | CONFIG_DM_SPI=y | 103 | CONFIG_DM_SPI=y |
| 104 | CONFIG_FSL_FSPI=y | 104 | CONFIG_FSL_FSPI=y |
| 105 | CONFIG_SPI=y | 105 | CONFIG_SPI=y |
| 106 | CONFIG_SPI_FLASH=y | 106 | CONFIG_SPI_FLASH=y |
| 107 | CONFIG_SPI_FLASH_BAR=y | 107 | CONFIG_SPI_FLASH_BAR=y |
| 108 | CONFIG_SPI_FLASH_MACRONIX=y | 108 | CONFIG_SPI_FLASH_MACRONIX=y |
| 109 | CONFIG_SF_DEFAULT_BUS=0 | 109 | CONFIG_SF_DEFAULT_BUS=0 |
| 110 | CONFIG_SF_DEFAULT_CS=0 | 110 | CONFIG_SF_DEFAULT_CS=0 |
| 111 | CONFIG_SF_DEFAULT_SPEED=40000000 | 111 | CONFIG_SF_DEFAULT_SPEED=40000000 |
| 112 | CONFIG_SF_DEFAULT_MODE=0 | 112 | CONFIG_SF_DEFAULT_MODE=0 |
| 113 | 113 | ||
| 114 | CONFIG_DM_ETH=y | 114 | CONFIG_DM_ETH=y |
| 115 | # CONFIG_DM_ETH_PHY=y | 115 | # CONFIG_DM_ETH_PHY=y |
| 116 | CONFIG_DWC_ETH_QOS=y | 116 | CONFIG_DWC_ETH_QOS=y |
| 117 | 117 | ||
| 118 | CONFIG_PHY_GIGE=y | 118 | CONFIG_PHY_GIGE=y |
| 119 | CONFIG_FEC_MXC=y | 119 | CONFIG_FEC_MXC=y |
| 120 | CONFIG_MII=y | 120 | CONFIG_MII=y |
| 121 | CONFIG_PHYLIB=y | 121 | CONFIG_PHYLIB=y |
| 122 | CONFIG_PHY_ATHEROS=y | 122 | CONFIG_PHY_ATHEROS=y |
| 123 | 123 | ||
| 124 | CONFIG_PINCTRL=y | 124 | CONFIG_PINCTRL=y |
| 125 | CONFIG_PINCTRL_IMX8M=y | 125 | CONFIG_PINCTRL_IMX8M=y |
| 126 | CONFIG_DM_REGULATOR=y | 126 | CONFIG_DM_REGULATOR=y |
| 127 | CONFIG_DM_REGULATOR_FIXED=y | 127 | CONFIG_DM_REGULATOR_FIXED=y |
| 128 | CONFIG_DM_REGULATOR_GPIO=y | 128 | CONFIG_DM_REGULATOR_GPIO=y |
| 129 | CONFIG_MXC_UART=y | 129 | CONFIG_MXC_UART=y |
| 130 | CONFIG_SYSRESET=y | 130 | CONFIG_SYSRESET=y |
| 131 | CONFIG_SYSRESET_PSCI=y | 131 | CONFIG_SYSRESET_PSCI=y |
| 132 | CONFIG_DM_THERMAL=y | 132 | CONFIG_DM_THERMAL=y |
| 133 | CONFIG_NXP_TMU=y | 133 | CONFIG_NXP_TMU=y |
| 134 | CONFIG_USB=y | 134 | CONFIG_USB=y |
| 135 | CONFIG_USB_GADGET=y | 135 | CONFIG_USB_GADGET=y |
| 136 | CONFIG_DM_USB=y | 136 | CONFIG_DM_USB=y |
| 137 | 137 | ||
| 138 | CONFIG_OF_LIBFDT_OVERLAY=y | 138 | CONFIG_OF_LIBFDT_OVERLAY=y |
| 139 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 139 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
| 140 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 140 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
| 141 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 141 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
| 142 | CONFIG_USB_GADGET_DOWNLOAD=y | 142 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 143 | CONFIG_USB_XHCI_HCD=y | 143 | CONFIG_USB_XHCI_HCD=y |
| 144 | CONFIG_USB_XHCI_IMX8M=y | 144 | CONFIG_USB_XHCI_IMX8M=y |
| 145 | CONFIG_USB_XHCI_DWC3=y | 145 | CONFIG_USB_XHCI_DWC3=y |
| 146 | CONFIG_USB_DWC3=y | 146 | CONFIG_USB_DWC3=y |
| 147 | CONFIG_USB_DWC3_GADGET=y | 147 | CONFIG_USB_DWC3_GADGET=y |
| 148 | 148 | ||
| 149 | CONFIG_OF_BOARD_SETUP=y | 149 | CONFIG_OF_BOARD_SETUP=y |
| 150 | 150 | ||
| 151 | CONFIG_REGMAP=y | 151 | CONFIG_REGMAP=y |
| 152 | CONFIG_SYSCON=y | 152 | CONFIG_SYSCON=y |
| 153 | CONFIG_VIDEO_IMX_LCDIFV3=y | 153 | CONFIG_VIDEO_IMX_LCDIFV3=y |
| 154 | CONFIG_DM_VIDEO=y | 154 | CONFIG_DM_VIDEO=y |
| 155 | CONFIG_SYS_WHITE_ON_BLACK=y | 155 | CONFIG_SYS_WHITE_ON_BLACK=y |
| 156 | 156 |
configs/smarcimx8mp_6g_ser1_android_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_SYS_ICACHE_OFF=y | 2 | CONFIG_SPL_SYS_ICACHE_OFF=y |
| 3 | CONFIG_SPL_SYS_DCACHE_OFF=y | 3 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| 4 | CONFIG_ARCH_IMX8M=y | 4 | CONFIG_ARCH_IMX8M=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x40200000 | 5 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| 6 | CONFIG_SPL_GPIO_SUPPORT=y | 6 | CONFIG_SPL_GPIO_SUPPORT=y |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y | 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 10 | CONFIG_SYS_I2C_MXC_I2C1=y | 10 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 11 | CONFIG_SYS_I2C_MXC_I2C2=y | 11 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C3=y | 12 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 13 | CONFIG_SYS_I2C_MXC_I2C4=y | 13 | CONFIG_SYS_I2C_MXC_I2C4=y |
| 14 | CONFIG_SYS_I2C_MXC_I2C6=y | 14 | CONFIG_SYS_I2C_MXC_I2C6=y |
| 15 | CONFIG_ENV_SIZE=0x1000 | 15 | CONFIG_ENV_SIZE=0x1000 |
| 16 | CONFIG_ENV_OFFSET=0x400000 | 16 | CONFIG_ENV_OFFSET=0x400000 |
| 17 | CONFIG_ENV_SECT_SIZE=0x10000 | 17 | CONFIG_ENV_SECT_SIZE=0x10000 |
| 18 | CONFIG_DM_GPIO=y | 18 | CONFIG_DM_GPIO=y |
| 19 | CONFIG_BOOTDELAY=1 | 19 | CONFIG_BOOTDELAY=1 |
| 20 | CONFIG_TARGET_SMARCIMX8MP=y | 20 | CONFIG_TARGET_SMARCIMX8MP=y |
| 21 | CONFIG_ARCH_MISC_INIT=y | 21 | CONFIG_ARCH_MISC_INIT=y |
| 22 | CONFIG_SPL_SERIAL_SUPPORT=y | 22 | CONFIG_SPL_SERIAL_SUPPORT=y |
| 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 24 | CONFIG_SPL=y | 24 | CONFIG_SPL=y |
| 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 26 | CONFIG_CSF_SIZE=0x2000 | 26 | CONFIG_CSF_SIZE=0x2000 |
| 27 | CONFIG_SPL_TEXT_BASE=0x920000 | 27 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 28 | CONFIG_FIT=y | 28 | CONFIG_FIT=y |
| 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 30 | CONFIG_SPL_LOAD_FIT=y | 30 | CONFIG_SPL_LOAD_FIT=y |
| 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" |
| 32 | CONFIG_OF_SYSTEM_SETUP=y | 32 | CONFIG_OF_SYSTEM_SETUP=y |
| 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,6GB_LPDDR4" | 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,6GB_LPDDR4" |
| 34 | CONFIG_CONSOLE_SER1=y | 34 | CONFIG_CONSOLE_SER1=y |
| 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" | 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" |
| 36 | CONFIG_BOARD_LATE_INIT=y | 36 | CONFIG_BOARD_LATE_INIT=y |
| 37 | CONFIG_BOARD_EARLY_INIT_F=y | 37 | CONFIG_BOARD_EARLY_INIT_F=y |
| 38 | CONFIG_SPL_BOARD_INIT=y | 38 | CONFIG_SPL_BOARD_INIT=y |
| 39 | CONFIG_SPL_SEPARATE_BSS=y | 39 | CONFIG_SPL_SEPARATE_BSS=y |
| 40 | CONFIG_SPL_I2C_SUPPORT=y | 40 | CONFIG_SPL_I2C_SUPPORT=y |
| 41 | CONFIG_SPL_POWER_SUPPORT=y | 41 | CONFIG_SPL_POWER_SUPPORT=y |
| 42 | CONFIG_NR_DRAM_BANKS=3 | 42 | CONFIG_NR_DRAM_BANKS=3 |
| 43 | CONFIG_HUSH_PARSER=y | 43 | CONFIG_HUSH_PARSER=y |
| 44 | CONFIG_SYS_PROMPT="u-boot$ " | 44 | CONFIG_SYS_PROMPT="u-boot$ " |
| 45 | # CONFIG_CMD_EXPORTENV is not set | 45 | # CONFIG_CMD_EXPORTENV is not set |
| 46 | CONFIG_CMD_IMPORTENV=y | 46 | CONFIG_CMD_IMPORTENV=y |
| 47 | CONFIG_CMD_ERASEENV=y | 47 | CONFIG_CMD_ERASEENV=y |
| 48 | # CONFIG_CMD_CRC32 is not set | 48 | # CONFIG_CMD_CRC32 is not set |
| 49 | # CONFIG_BOOTM_NETBSD is not set | 49 | # CONFIG_BOOTM_NETBSD is not set |
| 50 | CONFIG_CMD_CLK=y | 50 | CONFIG_CMD_CLK=y |
| 51 | CONFIG_CMD_FUSE=y | 51 | CONFIG_CMD_FUSE=y |
| 52 | CONFIG_CMD_GPIO=y | 52 | CONFIG_CMD_GPIO=y |
| 53 | CONFIG_CMD_I2C=y | 53 | CONFIG_CMD_I2C=y |
| 54 | CONFIG_CMD_MMC=y | 54 | CONFIG_CMD_MMC=y |
| 55 | CONFIG_CMD_DHCP=y | 55 | CONFIG_CMD_DHCP=y |
| 56 | CONFIG_CMD_MII=y | 56 | CONFIG_CMD_MII=y |
| 57 | CONFIG_CMD_PING=y | 57 | CONFIG_CMD_PING=y |
| 58 | CONFIG_CMD_CACHE=y | 58 | CONFIG_CMD_CACHE=y |
| 59 | CONFIG_CMD_REGULATOR=y | 59 | CONFIG_CMD_REGULATOR=y |
| 60 | CONFIG_CMD_MEMTEST=y | 60 | CONFIG_CMD_MEMTEST=y |
| 61 | CONFIG_CMD_EXT2=y | 61 | CONFIG_CMD_EXT2=y |
| 62 | CONFIG_CMD_EXT4=y | 62 | CONFIG_CMD_EXT4=y |
| 63 | CONFIG_CMD_EXT4_WRITE=y | 63 | CONFIG_CMD_EXT4_WRITE=y |
| 64 | CONFIG_CMD_FAT=y | 64 | CONFIG_CMD_FAT=y |
| 65 | CONFIG_CMD_SF=y | 65 | CONFIG_CMD_SF=y |
| 66 | CONFIG_CMD_LED=y | 66 | CONFIG_CMD_LED=y |
| 67 | CONFIG_OF_CONTROL=y | 67 | CONFIG_OF_CONTROL=y |
| 68 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" | 68 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" |
| 69 | CONFIG_ENV_IS_IN_MMC=y | 69 | CONFIG_ENV_IS_IN_MMC=y |
| 70 | CONFIG_ENV_IS_IN_SPI_FLASH=y | 70 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 71 | CONFIG_ENV_IS_NOWHERE=y | 71 | CONFIG_ENV_IS_NOWHERE=y |
| 72 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | 72 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 73 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | 73 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 74 | CONFIG_CLK_COMPOSITE_CCF=y | 74 | CONFIG_CLK_COMPOSITE_CCF=y |
| 75 | CONFIG_CLK_IMX8MP=y | 75 | CONFIG_CLK_IMX8MP=y |
| 76 | CONFIG_MXC_GPIO=y | 76 | CONFIG_MXC_GPIO=y |
| 77 | CONFIG_DM_PCA953X=y | 77 | CONFIG_DM_PCA953X=y |
| 78 | CONFIG_FASTBOOT=y | 78 | CONFIG_FASTBOOT=y |
| 79 | CONFIG_USB_FUNCTION_FASTBOOT=y | 79 | CONFIG_USB_FUNCTION_FASTBOOT=y |
| 80 | CONFIG_CMD_FASTBOOT=y | 80 | CONFIG_CMD_FASTBOOT=y |
| 81 | CONFIG_ANDROID_BOOT_IMAGE=y | 81 | CONFIG_ANDROID_BOOT_IMAGE=y |
| 82 | CONFIG_FASTBOOT_UUU_SUPPORT=n | 82 | CONFIG_FASTBOOT_UUU_SUPPORT=n |
| 83 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 83 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
| 84 | CONFIG_FASTBOOT_BUF_SIZE=0xc800000 | 84 | CONFIG_FASTBOOT_BUF_SIZE=0xc800000 |
| 85 | CONFIG_FASTBOOT_FLASH=y | 85 | CONFIG_FASTBOOT_FLASH=y |
| 86 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 | 86 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
| 87 | CONFIG_DM_I2C=y | 87 | CONFIG_DM_I2C=y |
| 88 | CONFIG_CMD_GPT=y | 88 | CONFIG_CMD_GPT=y |
| 89 | CONFIG_CMD_TIME=y | 89 | CONFIG_CMD_TIME=y |
| 90 | CONFIG_SYS_I2C_MXC=y | 90 | CONFIG_SYS_I2C_MXC=y |
| 91 | CONFIG_LED=y | 91 | CONFIG_LED=y |
| 92 | CONFIG_LED_GPIO=y | 92 | CONFIG_LED_GPIO=y |
| 93 | CONFIG_DM_MMC=y | 93 | CONFIG_DM_MMC=y |
| 94 | CONFIG_MMC_IO_VOLTAGE=y | 94 | # CONFIG_MMC_IO_VOLTAGE is not set |
| 95 | CONFIG_MMC_UHS_SUPPORT=y | 95 | CONFIG_MMC_UHS_SUPPORT=y |
| 96 | CONFIG_MMC_HS400_SUPPORT=y | 96 | CONFIG_MMC_HS400_SUPPORT=y |
| 97 | CONFIG_MMC_HS400_ES_SUPPORT=y | 97 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 98 | CONFIG_EFI_PARTITION=y | 98 | CONFIG_EFI_PARTITION=y |
| 99 | CONFIG_SUPPORT_EMMC_BOOT=y | 99 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 100 | CONFIG_FSL_ESDHC_IMX=y | 100 | CONFIG_FSL_ESDHC_IMX=y |
| 101 | CONFIG_DM_SPI_FLASH=y | 101 | CONFIG_DM_SPI_FLASH=y |
| 102 | CONFIG_DM_SPI=y | 102 | CONFIG_DM_SPI=y |
| 103 | CONFIG_FSL_FSPI=y | 103 | CONFIG_FSL_FSPI=y |
| 104 | CONFIG_SPI=y | 104 | CONFIG_SPI=y |
| 105 | CONFIG_SPI_FLASH=y | 105 | CONFIG_SPI_FLASH=y |
| 106 | CONFIG_SPI_FLASH_BAR=y | 106 | CONFIG_SPI_FLASH_BAR=y |
| 107 | CONFIG_SPI_FLASH_MACRONIX=y | 107 | CONFIG_SPI_FLASH_MACRONIX=y |
| 108 | CONFIG_SF_DEFAULT_BUS=0 | 108 | CONFIG_SF_DEFAULT_BUS=0 |
| 109 | CONFIG_SF_DEFAULT_CS=0 | 109 | CONFIG_SF_DEFAULT_CS=0 |
| 110 | CONFIG_SF_DEFAULT_SPEED=40000000 | 110 | CONFIG_SF_DEFAULT_SPEED=40000000 |
| 111 | CONFIG_SF_DEFAULT_MODE=0 | 111 | CONFIG_SF_DEFAULT_MODE=0 |
| 112 | 112 | ||
| 113 | CONFIG_DM_ETH=y | 113 | CONFIG_DM_ETH=y |
| 114 | # CONFIG_DM_ETH_PHY=y | 114 | # CONFIG_DM_ETH_PHY=y |
| 115 | CONFIG_DWC_ETH_QOS=y | 115 | CONFIG_DWC_ETH_QOS=y |
| 116 | 116 | ||
| 117 | CONFIG_PHY_GIGE=y | 117 | CONFIG_PHY_GIGE=y |
| 118 | CONFIG_FEC_MXC=y | 118 | CONFIG_FEC_MXC=y |
| 119 | CONFIG_MII=y | 119 | CONFIG_MII=y |
| 120 | CONFIG_PHYLIB=y | 120 | CONFIG_PHYLIB=y |
| 121 | CONFIG_PHY_ATHEROS=y | 121 | CONFIG_PHY_ATHEROS=y |
| 122 | 122 | ||
| 123 | CONFIG_PINCTRL=y | 123 | CONFIG_PINCTRL=y |
| 124 | CONFIG_PINCTRL_IMX8M=y | 124 | CONFIG_PINCTRL_IMX8M=y |
| 125 | CONFIG_DM_REGULATOR=y | 125 | CONFIG_DM_REGULATOR=y |
| 126 | CONFIG_DM_REGULATOR_FIXED=y | 126 | CONFIG_DM_REGULATOR_FIXED=y |
| 127 | CONFIG_DM_REGULATOR_GPIO=y | 127 | CONFIG_DM_REGULATOR_GPIO=y |
| 128 | CONFIG_MXC_UART=y | 128 | CONFIG_MXC_UART=y |
| 129 | CONFIG_SYSRESET=y | 129 | CONFIG_SYSRESET=y |
| 130 | CONFIG_SYSRESET_PSCI=y | 130 | CONFIG_SYSRESET_PSCI=y |
| 131 | CONFIG_DM_THERMAL=y | 131 | CONFIG_DM_THERMAL=y |
| 132 | CONFIG_NXP_TMU=y | 132 | CONFIG_NXP_TMU=y |
| 133 | CONFIG_USB=y | 133 | CONFIG_USB=y |
| 134 | CONFIG_USB_GADGET=y | 134 | CONFIG_USB_GADGET=y |
| 135 | CONFIG_DM_USB=y | 135 | CONFIG_DM_USB=y |
| 136 | 136 | ||
| 137 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 137 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
| 138 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 138 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
| 139 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 139 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
| 140 | CONFIG_USB_GADGET_DOWNLOAD=y | 140 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 141 | CONFIG_USB_XHCI_HCD=y | 141 | CONFIG_USB_XHCI_HCD=y |
| 142 | CONFIG_USB_XHCI_IMX8M=y | 142 | CONFIG_USB_XHCI_IMX8M=y |
| 143 | CONFIG_USB_XHCI_DWC3=y | 143 | CONFIG_USB_XHCI_DWC3=y |
| 144 | CONFIG_USB_DWC3=y | 144 | CONFIG_USB_DWC3=y |
| 145 | CONFIG_USB_DWC3_GADGET=y | 145 | CONFIG_USB_DWC3_GADGET=y |
| 146 | 146 | ||
| 147 | CONFIG_OF_BOARD_SETUP=y | 147 | CONFIG_OF_BOARD_SETUP=y |
| 148 | 148 | ||
| 149 | CONFIG_REGMAP=y | 149 | CONFIG_REGMAP=y |
| 150 | CONFIG_SYSCON=y | 150 | CONFIG_SYSCON=y |
| 151 | CONFIG_VIDEO_IMX_LCDIFV3=y | 151 | CONFIG_VIDEO_IMX_LCDIFV3=y |
| 152 | CONFIG_DM_VIDEO=y | 152 | CONFIG_DM_VIDEO=y |
| 153 | CONFIG_SYS_WHITE_ON_BLACK=y | 153 | CONFIG_SYS_WHITE_ON_BLACK=y |
| 154 | 154 | ||
| 155 | CONFIG_LZ4=y | 155 | CONFIG_LZ4=y |
| 156 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y | 156 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y |
| 157 | CONFIG_APPEND_BOOTARGS=y | 157 | CONFIG_APPEND_BOOTARGS=y |
| 158 | CONFIG_SPL_MMC_SUPPORT=y | 158 | CONFIG_SPL_MMC_SUPPORT=y |
| 159 | CONFIG_AVB_WARNING_LOGO=y | 159 | CONFIG_AVB_WARNING_LOGO=y |
| 160 | CONFIG_AVB_WARNING_LOGO_COLS=0x320 | 160 | CONFIG_AVB_WARNING_LOGO_COLS=0x320 |
| 161 | CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 | 161 | CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 |
| 162 | CONFIG_VIRTUAL_AB_SUPPORT=y | 162 | CONFIG_VIRTUAL_AB_SUPPORT=y |
| 163 | CONFIG_ANDROID_SUPPORT=y | 163 | CONFIG_ANDROID_SUPPORT=y |
| 164 | CONFIG_APPEND_BOOTARGS=y | 164 | CONFIG_APPEND_BOOTARGS=y |
| 165 | CONFIG_ANDROID_AB_SUPPORT=y | 165 | CONFIG_ANDROID_AB_SUPPORT=y |
| 166 | 166 |
configs/smarcimx8mp_6g_ser1_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_SYS_ICACHE_OFF=y | 2 | CONFIG_SPL_SYS_ICACHE_OFF=y |
| 3 | CONFIG_SPL_SYS_DCACHE_OFF=y | 3 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| 4 | CONFIG_ARCH_IMX8M=y | 4 | CONFIG_ARCH_IMX8M=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x40200000 | 5 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| 6 | CONFIG_SPL_GPIO_SUPPORT=y | 6 | CONFIG_SPL_GPIO_SUPPORT=y |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y | 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 10 | CONFIG_SYS_I2C_MXC_I2C1=y | 10 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 11 | CONFIG_SYS_I2C_MXC_I2C2=y | 11 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C3=y | 12 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 13 | CONFIG_SYS_I2C_MXC_I2C4=y | 13 | CONFIG_SYS_I2C_MXC_I2C4=y |
| 14 | CONFIG_SYS_I2C_MXC_I2C6=y | 14 | CONFIG_SYS_I2C_MXC_I2C6=y |
| 15 | CONFIG_ENV_SIZE=0x1000 | 15 | CONFIG_ENV_SIZE=0x1000 |
| 16 | CONFIG_ENV_OFFSET=0x400000 | 16 | CONFIG_ENV_OFFSET=0x400000 |
| 17 | CONFIG_ENV_SECT_SIZE=0x10000 | 17 | CONFIG_ENV_SECT_SIZE=0x10000 |
| 18 | CONFIG_DM_GPIO=y | 18 | CONFIG_DM_GPIO=y |
| 19 | CONFIG_BOOTDELAY=1 | 19 | CONFIG_BOOTDELAY=1 |
| 20 | CONFIG_TARGET_SMARCIMX8MP=y | 20 | CONFIG_TARGET_SMARCIMX8MP=y |
| 21 | CONFIG_ARCH_MISC_INIT=y | 21 | CONFIG_ARCH_MISC_INIT=y |
| 22 | CONFIG_SPL_SERIAL_SUPPORT=y | 22 | CONFIG_SPL_SERIAL_SUPPORT=y |
| 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 24 | CONFIG_SPL=y | 24 | CONFIG_SPL=y |
| 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 26 | CONFIG_CSF_SIZE=0x2000 | 26 | CONFIG_CSF_SIZE=0x2000 |
| 27 | CONFIG_SPL_TEXT_BASE=0x920000 | 27 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 28 | CONFIG_FIT=y | 28 | CONFIG_FIT=y |
| 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 30 | CONFIG_SPL_LOAD_FIT=y | 30 | CONFIG_SPL_LOAD_FIT=y |
| 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" |
| 32 | CONFIG_OF_SYSTEM_SETUP=y | 32 | CONFIG_OF_SYSTEM_SETUP=y |
| 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,6GB_LPDDR4" | 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,6GB_LPDDR4" |
| 34 | CONFIG_CONSOLE_SER1=y | 34 | CONFIG_CONSOLE_SER1=y |
| 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" | 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" |
| 36 | CONFIG_BOARD_LATE_INIT=y | 36 | CONFIG_BOARD_LATE_INIT=y |
| 37 | CONFIG_BOARD_EARLY_INIT_F=y | 37 | CONFIG_BOARD_EARLY_INIT_F=y |
| 38 | CONFIG_SPL_BOARD_INIT=y | 38 | CONFIG_SPL_BOARD_INIT=y |
| 39 | CONFIG_SPL_BOOTROM_SUPPORT=y | 39 | CONFIG_SPL_BOOTROM_SUPPORT=y |
| 40 | CONFIG_SPL_SEPARATE_BSS=y | 40 | CONFIG_SPL_SEPARATE_BSS=y |
| 41 | CONFIG_SPL_I2C_SUPPORT=y | 41 | CONFIG_SPL_I2C_SUPPORT=y |
| 42 | CONFIG_SPL_POWER_SUPPORT=y | 42 | CONFIG_SPL_POWER_SUPPORT=y |
| 43 | CONFIG_NR_DRAM_BANKS=3 | 43 | CONFIG_NR_DRAM_BANKS=3 |
| 44 | CONFIG_HUSH_PARSER=y | 44 | CONFIG_HUSH_PARSER=y |
| 45 | CONFIG_SYS_PROMPT="u-boot$ " | 45 | CONFIG_SYS_PROMPT="u-boot$ " |
| 46 | # CONFIG_CMD_EXPORTENV is not set | 46 | # CONFIG_CMD_EXPORTENV is not set |
| 47 | CONFIG_CMD_IMPORTENV=y | 47 | CONFIG_CMD_IMPORTENV=y |
| 48 | CONFIG_CMD_ERASEENV=y | 48 | CONFIG_CMD_ERASEENV=y |
| 49 | # CONFIG_CMD_CRC32 is not set | 49 | # CONFIG_CMD_CRC32 is not set |
| 50 | # CONFIG_BOOTM_NETBSD is not set | 50 | # CONFIG_BOOTM_NETBSD is not set |
| 51 | CONFIG_CMD_CLK=y | 51 | CONFIG_CMD_CLK=y |
| 52 | CONFIG_CMD_FUSE=y | 52 | CONFIG_CMD_FUSE=y |
| 53 | CONFIG_CMD_GPIO=y | 53 | CONFIG_CMD_GPIO=y |
| 54 | CONFIG_CMD_I2C=y | 54 | CONFIG_CMD_I2C=y |
| 55 | CONFIG_CMD_MMC=y | 55 | CONFIG_CMD_MMC=y |
| 56 | CONFIG_CMD_DHCP=y | 56 | CONFIG_CMD_DHCP=y |
| 57 | CONFIG_CMD_MII=y | 57 | CONFIG_CMD_MII=y |
| 58 | CONFIG_CMD_PING=y | 58 | CONFIG_CMD_PING=y |
| 59 | CONFIG_CMD_CACHE=y | 59 | CONFIG_CMD_CACHE=y |
| 60 | CONFIG_CMD_REGULATOR=y | 60 | CONFIG_CMD_REGULATOR=y |
| 61 | CONFIG_CMD_MEMTEST=y | 61 | CONFIG_CMD_MEMTEST=y |
| 62 | CONFIG_CMD_EXT2=y | 62 | CONFIG_CMD_EXT2=y |
| 63 | CONFIG_CMD_EXT4=y | 63 | CONFIG_CMD_EXT4=y |
| 64 | CONFIG_CMD_EXT4_WRITE=y | 64 | CONFIG_CMD_EXT4_WRITE=y |
| 65 | CONFIG_CMD_FAT=y | 65 | CONFIG_CMD_FAT=y |
| 66 | CONFIG_CMD_SF=y | 66 | CONFIG_CMD_SF=y |
| 67 | CONFIG_CMD_LED=y | 67 | CONFIG_CMD_LED=y |
| 68 | CONFIG_OF_CONTROL=y | 68 | CONFIG_OF_CONTROL=y |
| 69 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" | 69 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" |
| 70 | CONFIG_ENV_IS_IN_MMC=y | 70 | CONFIG_ENV_IS_IN_MMC=y |
| 71 | CONFIG_ENV_IS_IN_SPI_FLASH=y | 71 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 72 | CONFIG_ENV_IS_NOWHERE=y | 72 | CONFIG_ENV_IS_NOWHERE=y |
| 73 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | 73 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 74 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | 74 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 75 | CONFIG_CLK_COMPOSITE_CCF=y | 75 | CONFIG_CLK_COMPOSITE_CCF=y |
| 76 | CONFIG_CLK_IMX8MP=y | 76 | CONFIG_CLK_IMX8MP=y |
| 77 | CONFIG_MXC_GPIO=y | 77 | CONFIG_MXC_GPIO=y |
| 78 | CONFIG_DM_PCA953X=y | 78 | CONFIG_DM_PCA953X=y |
| 79 | CONFIG_FASTBOOT=y | 79 | CONFIG_FASTBOOT=y |
| 80 | CONFIG_USB_FUNCTION_FASTBOOT=y | 80 | CONFIG_USB_FUNCTION_FASTBOOT=y |
| 81 | CONFIG_CMD_FASTBOOT=y | 81 | CONFIG_CMD_FASTBOOT=y |
| 82 | CONFIG_ANDROID_BOOT_IMAGE=y | 82 | CONFIG_ANDROID_BOOT_IMAGE=y |
| 83 | CONFIG_FASTBOOT_UUU_SUPPORT=y | 83 | CONFIG_FASTBOOT_UUU_SUPPORT=y |
| 84 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 84 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
| 85 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 85 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
| 86 | CONFIG_FASTBOOT_FLASH=y | 86 | CONFIG_FASTBOOT_FLASH=y |
| 87 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 | 87 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
| 88 | CONFIG_DM_I2C=y | 88 | CONFIG_DM_I2C=y |
| 89 | CONFIG_CMD_GPT=y | 89 | CONFIG_CMD_GPT=y |
| 90 | CONFIG_CMD_TIME=y | 90 | CONFIG_CMD_TIME=y |
| 91 | CONFIG_SYS_I2C_MXC=y | 91 | CONFIG_SYS_I2C_MXC=y |
| 92 | CONFIG_LED=y | 92 | CONFIG_LED=y |
| 93 | CONFIG_LED_GPIO=y | 93 | CONFIG_LED_GPIO=y |
| 94 | CONFIG_DM_MMC=y | 94 | CONFIG_DM_MMC=y |
| 95 | CONFIG_MMC_IO_VOLTAGE=y | 95 | # CONFIG_MMC_IO_VOLTAGE is not set |
| 96 | CONFIG_MMC_UHS_SUPPORT=y | 96 | CONFIG_MMC_UHS_SUPPORT=y |
| 97 | CONFIG_MMC_HS400_SUPPORT=y | 97 | CONFIG_MMC_HS400_SUPPORT=y |
| 98 | CONFIG_MMC_HS400_ES_SUPPORT=y | 98 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 99 | CONFIG_EFI_PARTITION=y | 99 | CONFIG_EFI_PARTITION=y |
| 100 | CONFIG_SUPPORT_EMMC_BOOT=y | 100 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 101 | CONFIG_FSL_ESDHC_IMX=y | 101 | CONFIG_FSL_ESDHC_IMX=y |
| 102 | CONFIG_DM_SPI_FLASH=y | 102 | CONFIG_DM_SPI_FLASH=y |
| 103 | CONFIG_DM_SPI=y | 103 | CONFIG_DM_SPI=y |
| 104 | CONFIG_FSL_FSPI=y | 104 | CONFIG_FSL_FSPI=y |
| 105 | CONFIG_SPI=y | 105 | CONFIG_SPI=y |
| 106 | CONFIG_SPI_FLASH=y | 106 | CONFIG_SPI_FLASH=y |
| 107 | CONFIG_SPI_FLASH_BAR=y | 107 | CONFIG_SPI_FLASH_BAR=y |
| 108 | CONFIG_SPI_FLASH_MACRONIX=y | 108 | CONFIG_SPI_FLASH_MACRONIX=y |
| 109 | CONFIG_SF_DEFAULT_BUS=0 | 109 | CONFIG_SF_DEFAULT_BUS=0 |
| 110 | CONFIG_SF_DEFAULT_CS=0 | 110 | CONFIG_SF_DEFAULT_CS=0 |
| 111 | CONFIG_SF_DEFAULT_SPEED=40000000 | 111 | CONFIG_SF_DEFAULT_SPEED=40000000 |
| 112 | CONFIG_SF_DEFAULT_MODE=0 | 112 | CONFIG_SF_DEFAULT_MODE=0 |
| 113 | 113 | ||
| 114 | CONFIG_DM_ETH=y | 114 | CONFIG_DM_ETH=y |
| 115 | # CONFIG_DM_ETH_PHY=y | 115 | # CONFIG_DM_ETH_PHY=y |
| 116 | CONFIG_DWC_ETH_QOS=y | 116 | CONFIG_DWC_ETH_QOS=y |
| 117 | 117 | ||
| 118 | CONFIG_PHY_GIGE=y | 118 | CONFIG_PHY_GIGE=y |
| 119 | CONFIG_FEC_MXC=y | 119 | CONFIG_FEC_MXC=y |
| 120 | CONFIG_MII=y | 120 | CONFIG_MII=y |
| 121 | CONFIG_PHYLIB=y | 121 | CONFIG_PHYLIB=y |
| 122 | CONFIG_PHY_ATHEROS=y | 122 | CONFIG_PHY_ATHEROS=y |
| 123 | 123 | ||
| 124 | CONFIG_PINCTRL=y | 124 | CONFIG_PINCTRL=y |
| 125 | CONFIG_PINCTRL_IMX8M=y | 125 | CONFIG_PINCTRL_IMX8M=y |
| 126 | CONFIG_DM_REGULATOR=y | 126 | CONFIG_DM_REGULATOR=y |
| 127 | CONFIG_DM_REGULATOR_FIXED=y | 127 | CONFIG_DM_REGULATOR_FIXED=y |
| 128 | CONFIG_DM_REGULATOR_GPIO=y | 128 | CONFIG_DM_REGULATOR_GPIO=y |
| 129 | CONFIG_MXC_UART=y | 129 | CONFIG_MXC_UART=y |
| 130 | CONFIG_SYSRESET=y | 130 | CONFIG_SYSRESET=y |
| 131 | CONFIG_SYSRESET_PSCI=y | 131 | CONFIG_SYSRESET_PSCI=y |
| 132 | CONFIG_DM_THERMAL=y | 132 | CONFIG_DM_THERMAL=y |
| 133 | CONFIG_NXP_TMU=y | 133 | CONFIG_NXP_TMU=y |
| 134 | CONFIG_USB=y | 134 | CONFIG_USB=y |
| 135 | CONFIG_USB_GADGET=y | 135 | CONFIG_USB_GADGET=y |
| 136 | CONFIG_DM_USB=y | 136 | CONFIG_DM_USB=y |
| 137 | 137 | ||
| 138 | CONFIG_OF_LIBFDT_OVERLAY=y | 138 | CONFIG_OF_LIBFDT_OVERLAY=y |
| 139 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 139 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
| 140 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 140 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
| 141 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 141 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
| 142 | CONFIG_USB_GADGET_DOWNLOAD=y | 142 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 143 | CONFIG_USB_XHCI_HCD=y | 143 | CONFIG_USB_XHCI_HCD=y |
| 144 | CONFIG_USB_XHCI_IMX8M=y | 144 | CONFIG_USB_XHCI_IMX8M=y |
| 145 | CONFIG_USB_XHCI_DWC3=y | 145 | CONFIG_USB_XHCI_DWC3=y |
| 146 | CONFIG_USB_DWC3=y | 146 | CONFIG_USB_DWC3=y |
| 147 | CONFIG_USB_DWC3_GADGET=y | 147 | CONFIG_USB_DWC3_GADGET=y |
| 148 | 148 | ||
| 149 | CONFIG_OF_BOARD_SETUP=y | 149 | CONFIG_OF_BOARD_SETUP=y |
| 150 | 150 | ||
| 151 | CONFIG_REGMAP=y | 151 | CONFIG_REGMAP=y |
| 152 | CONFIG_SYSCON=y | 152 | CONFIG_SYSCON=y |
| 153 | CONFIG_VIDEO_IMX_LCDIFV3=y | 153 | CONFIG_VIDEO_IMX_LCDIFV3=y |
| 154 | CONFIG_DM_VIDEO=y | 154 | CONFIG_DM_VIDEO=y |
| 155 | CONFIG_SYS_WHITE_ON_BLACK=y | 155 | CONFIG_SYS_WHITE_ON_BLACK=y |
| 156 | 156 |
configs/smarcimx8mp_6g_ser2_android_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_SYS_ICACHE_OFF=y | 2 | CONFIG_SPL_SYS_ICACHE_OFF=y |
| 3 | CONFIG_SPL_SYS_DCACHE_OFF=y | 3 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| 4 | CONFIG_ARCH_IMX8M=y | 4 | CONFIG_ARCH_IMX8M=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x40200000 | 5 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| 6 | CONFIG_SPL_GPIO_SUPPORT=y | 6 | CONFIG_SPL_GPIO_SUPPORT=y |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y | 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 10 | CONFIG_SYS_I2C_MXC_I2C1=y | 10 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 11 | CONFIG_SYS_I2C_MXC_I2C2=y | 11 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C3=y | 12 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 13 | CONFIG_SYS_I2C_MXC_I2C4=y | 13 | CONFIG_SYS_I2C_MXC_I2C4=y |
| 14 | CONFIG_SYS_I2C_MXC_I2C6=y | 14 | CONFIG_SYS_I2C_MXC_I2C6=y |
| 15 | CONFIG_ENV_SIZE=0x1000 | 15 | CONFIG_ENV_SIZE=0x1000 |
| 16 | CONFIG_ENV_OFFSET=0x400000 | 16 | CONFIG_ENV_OFFSET=0x400000 |
| 17 | CONFIG_ENV_SECT_SIZE=0x10000 | 17 | CONFIG_ENV_SECT_SIZE=0x10000 |
| 18 | CONFIG_DM_GPIO=y | 18 | CONFIG_DM_GPIO=y |
| 19 | CONFIG_BOOTDELAY=1 | 19 | CONFIG_BOOTDELAY=1 |
| 20 | CONFIG_TARGET_SMARCIMX8MP=y | 20 | CONFIG_TARGET_SMARCIMX8MP=y |
| 21 | CONFIG_ARCH_MISC_INIT=y | 21 | CONFIG_ARCH_MISC_INIT=y |
| 22 | CONFIG_SPL_SERIAL_SUPPORT=y | 22 | CONFIG_SPL_SERIAL_SUPPORT=y |
| 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 24 | CONFIG_SPL=y | 24 | CONFIG_SPL=y |
| 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 26 | CONFIG_CSF_SIZE=0x2000 | 26 | CONFIG_CSF_SIZE=0x2000 |
| 27 | CONFIG_SPL_TEXT_BASE=0x920000 | 27 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 28 | CONFIG_FIT=y | 28 | CONFIG_FIT=y |
| 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 30 | CONFIG_SPL_LOAD_FIT=y | 30 | CONFIG_SPL_LOAD_FIT=y |
| 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" |
| 32 | CONFIG_OF_SYSTEM_SETUP=y | 32 | CONFIG_OF_SYSTEM_SETUP=y |
| 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,6GB_LPDDR4" | 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,6GB_LPDDR4" |
| 34 | CONFIG_CONSOLE_SER2=y | 34 | CONFIG_CONSOLE_SER2=y |
| 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" | 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" |
| 36 | CONFIG_BOARD_LATE_INIT=y | 36 | CONFIG_BOARD_LATE_INIT=y |
| 37 | CONFIG_BOARD_EARLY_INIT_F=y | 37 | CONFIG_BOARD_EARLY_INIT_F=y |
| 38 | CONFIG_SPL_BOARD_INIT=y | 38 | CONFIG_SPL_BOARD_INIT=y |
| 39 | CONFIG_SPL_SEPARATE_BSS=y | 39 | CONFIG_SPL_SEPARATE_BSS=y |
| 40 | CONFIG_SPL_I2C_SUPPORT=y | 40 | CONFIG_SPL_I2C_SUPPORT=y |
| 41 | CONFIG_SPL_POWER_SUPPORT=y | 41 | CONFIG_SPL_POWER_SUPPORT=y |
| 42 | CONFIG_NR_DRAM_BANKS=3 | 42 | CONFIG_NR_DRAM_BANKS=3 |
| 43 | CONFIG_HUSH_PARSER=y | 43 | CONFIG_HUSH_PARSER=y |
| 44 | CONFIG_SYS_PROMPT="u-boot$ " | 44 | CONFIG_SYS_PROMPT="u-boot$ " |
| 45 | # CONFIG_CMD_EXPORTENV is not set | 45 | # CONFIG_CMD_EXPORTENV is not set |
| 46 | CONFIG_CMD_IMPORTENV=y | 46 | CONFIG_CMD_IMPORTENV=y |
| 47 | CONFIG_CMD_ERASEENV=y | 47 | CONFIG_CMD_ERASEENV=y |
| 48 | # CONFIG_CMD_CRC32 is not set | 48 | # CONFIG_CMD_CRC32 is not set |
| 49 | # CONFIG_BOOTM_NETBSD is not set | 49 | # CONFIG_BOOTM_NETBSD is not set |
| 50 | CONFIG_CMD_CLK=y | 50 | CONFIG_CMD_CLK=y |
| 51 | CONFIG_CMD_FUSE=y | 51 | CONFIG_CMD_FUSE=y |
| 52 | CONFIG_CMD_GPIO=y | 52 | CONFIG_CMD_GPIO=y |
| 53 | CONFIG_CMD_I2C=y | 53 | CONFIG_CMD_I2C=y |
| 54 | CONFIG_CMD_MMC=y | 54 | CONFIG_CMD_MMC=y |
| 55 | CONFIG_CMD_DHCP=y | 55 | CONFIG_CMD_DHCP=y |
| 56 | CONFIG_CMD_MII=y | 56 | CONFIG_CMD_MII=y |
| 57 | CONFIG_CMD_PING=y | 57 | CONFIG_CMD_PING=y |
| 58 | CONFIG_CMD_CACHE=y | 58 | CONFIG_CMD_CACHE=y |
| 59 | CONFIG_CMD_REGULATOR=y | 59 | CONFIG_CMD_REGULATOR=y |
| 60 | CONFIG_CMD_MEMTEST=y | 60 | CONFIG_CMD_MEMTEST=y |
| 61 | CONFIG_CMD_EXT2=y | 61 | CONFIG_CMD_EXT2=y |
| 62 | CONFIG_CMD_EXT4=y | 62 | CONFIG_CMD_EXT4=y |
| 63 | CONFIG_CMD_EXT4_WRITE=y | 63 | CONFIG_CMD_EXT4_WRITE=y |
| 64 | CONFIG_CMD_FAT=y | 64 | CONFIG_CMD_FAT=y |
| 65 | CONFIG_CMD_SF=y | 65 | CONFIG_CMD_SF=y |
| 66 | CONFIG_CMD_LED=y | 66 | CONFIG_CMD_LED=y |
| 67 | CONFIG_OF_CONTROL=y | 67 | CONFIG_OF_CONTROL=y |
| 68 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" | 68 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" |
| 69 | CONFIG_ENV_IS_IN_MMC=y | 69 | CONFIG_ENV_IS_IN_MMC=y |
| 70 | CONFIG_ENV_IS_IN_SPI_FLASH=y | 70 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 71 | CONFIG_ENV_IS_NOWHERE=y | 71 | CONFIG_ENV_IS_NOWHERE=y |
| 72 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | 72 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 73 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | 73 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 74 | CONFIG_CLK_COMPOSITE_CCF=y | 74 | CONFIG_CLK_COMPOSITE_CCF=y |
| 75 | CONFIG_CLK_IMX8MP=y | 75 | CONFIG_CLK_IMX8MP=y |
| 76 | CONFIG_MXC_GPIO=y | 76 | CONFIG_MXC_GPIO=y |
| 77 | CONFIG_DM_PCA953X=y | 77 | CONFIG_DM_PCA953X=y |
| 78 | CONFIG_FASTBOOT=y | 78 | CONFIG_FASTBOOT=y |
| 79 | CONFIG_USB_FUNCTION_FASTBOOT=y | 79 | CONFIG_USB_FUNCTION_FASTBOOT=y |
| 80 | CONFIG_CMD_FASTBOOT=y | 80 | CONFIG_CMD_FASTBOOT=y |
| 81 | CONFIG_ANDROID_BOOT_IMAGE=y | 81 | CONFIG_ANDROID_BOOT_IMAGE=y |
| 82 | CONFIG_FASTBOOT_UUU_SUPPORT=n | 82 | CONFIG_FASTBOOT_UUU_SUPPORT=n |
| 83 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 83 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
| 84 | CONFIG_FASTBOOT_BUF_SIZE=0xc800000 | 84 | CONFIG_FASTBOOT_BUF_SIZE=0xc800000 |
| 85 | CONFIG_FASTBOOT_FLASH=y | 85 | CONFIG_FASTBOOT_FLASH=y |
| 86 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 | 86 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
| 87 | CONFIG_DM_I2C=y | 87 | CONFIG_DM_I2C=y |
| 88 | CONFIG_CMD_GPT=y | 88 | CONFIG_CMD_GPT=y |
| 89 | CONFIG_CMD_TIME=y | 89 | CONFIG_CMD_TIME=y |
| 90 | CONFIG_SYS_I2C_MXC=y | 90 | CONFIG_SYS_I2C_MXC=y |
| 91 | CONFIG_LED=y | 91 | CONFIG_LED=y |
| 92 | CONFIG_LED_GPIO=y | 92 | CONFIG_LED_GPIO=y |
| 93 | CONFIG_DM_MMC=y | 93 | CONFIG_DM_MMC=y |
| 94 | CONFIG_MMC_IO_VOLTAGE=y | 94 | # CONFIG_MMC_IO_VOLTAGE is not set |
| 95 | CONFIG_MMC_UHS_SUPPORT=y | 95 | CONFIG_MMC_UHS_SUPPORT=y |
| 96 | CONFIG_MMC_HS400_SUPPORT=y | 96 | CONFIG_MMC_HS400_SUPPORT=y |
| 97 | CONFIG_MMC_HS400_ES_SUPPORT=y | 97 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 98 | CONFIG_EFI_PARTITION=y | 98 | CONFIG_EFI_PARTITION=y |
| 99 | CONFIG_SUPPORT_EMMC_BOOT=y | 99 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 100 | CONFIG_FSL_ESDHC_IMX=y | 100 | CONFIG_FSL_ESDHC_IMX=y |
| 101 | CONFIG_DM_SPI_FLASH=y | 101 | CONFIG_DM_SPI_FLASH=y |
| 102 | CONFIG_DM_SPI=y | 102 | CONFIG_DM_SPI=y |
| 103 | CONFIG_FSL_FSPI=y | 103 | CONFIG_FSL_FSPI=y |
| 104 | CONFIG_SPI=y | 104 | CONFIG_SPI=y |
| 105 | CONFIG_SPI_FLASH=y | 105 | CONFIG_SPI_FLASH=y |
| 106 | CONFIG_SPI_FLASH_BAR=y | 106 | CONFIG_SPI_FLASH_BAR=y |
| 107 | CONFIG_SPI_FLASH_MACRONIX=y | 107 | CONFIG_SPI_FLASH_MACRONIX=y |
| 108 | CONFIG_SF_DEFAULT_BUS=0 | 108 | CONFIG_SF_DEFAULT_BUS=0 |
| 109 | CONFIG_SF_DEFAULT_CS=0 | 109 | CONFIG_SF_DEFAULT_CS=0 |
| 110 | CONFIG_SF_DEFAULT_SPEED=40000000 | 110 | CONFIG_SF_DEFAULT_SPEED=40000000 |
| 111 | CONFIG_SF_DEFAULT_MODE=0 | 111 | CONFIG_SF_DEFAULT_MODE=0 |
| 112 | 112 | ||
| 113 | CONFIG_DM_ETH=y | 113 | CONFIG_DM_ETH=y |
| 114 | # CONFIG_DM_ETH_PHY=y | 114 | # CONFIG_DM_ETH_PHY=y |
| 115 | CONFIG_DWC_ETH_QOS=y | 115 | CONFIG_DWC_ETH_QOS=y |
| 116 | 116 | ||
| 117 | CONFIG_PHY_GIGE=y | 117 | CONFIG_PHY_GIGE=y |
| 118 | CONFIG_FEC_MXC=y | 118 | CONFIG_FEC_MXC=y |
| 119 | CONFIG_MII=y | 119 | CONFIG_MII=y |
| 120 | CONFIG_PHYLIB=y | 120 | CONFIG_PHYLIB=y |
| 121 | CONFIG_PHY_ATHEROS=y | 121 | CONFIG_PHY_ATHEROS=y |
| 122 | 122 | ||
| 123 | CONFIG_PINCTRL=y | 123 | CONFIG_PINCTRL=y |
| 124 | CONFIG_PINCTRL_IMX8M=y | 124 | CONFIG_PINCTRL_IMX8M=y |
| 125 | CONFIG_DM_REGULATOR=y | 125 | CONFIG_DM_REGULATOR=y |
| 126 | CONFIG_DM_REGULATOR_FIXED=y | 126 | CONFIG_DM_REGULATOR_FIXED=y |
| 127 | CONFIG_DM_REGULATOR_GPIO=y | 127 | CONFIG_DM_REGULATOR_GPIO=y |
| 128 | CONFIG_MXC_UART=y | 128 | CONFIG_MXC_UART=y |
| 129 | CONFIG_SYSRESET=y | 129 | CONFIG_SYSRESET=y |
| 130 | CONFIG_SYSRESET_PSCI=y | 130 | CONFIG_SYSRESET_PSCI=y |
| 131 | CONFIG_DM_THERMAL=y | 131 | CONFIG_DM_THERMAL=y |
| 132 | CONFIG_NXP_TMU=y | 132 | CONFIG_NXP_TMU=y |
| 133 | CONFIG_USB=y | 133 | CONFIG_USB=y |
| 134 | CONFIG_USB_GADGET=y | 134 | CONFIG_USB_GADGET=y |
| 135 | CONFIG_DM_USB=y | 135 | CONFIG_DM_USB=y |
| 136 | 136 | ||
| 137 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 137 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
| 138 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 138 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
| 139 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 139 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
| 140 | CONFIG_USB_GADGET_DOWNLOAD=y | 140 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 141 | CONFIG_USB_XHCI_HCD=y | 141 | CONFIG_USB_XHCI_HCD=y |
| 142 | CONFIG_USB_XHCI_IMX8M=y | 142 | CONFIG_USB_XHCI_IMX8M=y |
| 143 | CONFIG_USB_XHCI_DWC3=y | 143 | CONFIG_USB_XHCI_DWC3=y |
| 144 | CONFIG_USB_DWC3=y | 144 | CONFIG_USB_DWC3=y |
| 145 | CONFIG_USB_DWC3_GADGET=y | 145 | CONFIG_USB_DWC3_GADGET=y |
| 146 | 146 | ||
| 147 | CONFIG_OF_BOARD_SETUP=y | 147 | CONFIG_OF_BOARD_SETUP=y |
| 148 | 148 | ||
| 149 | CONFIG_REGMAP=y | 149 | CONFIG_REGMAP=y |
| 150 | CONFIG_SYSCON=y | 150 | CONFIG_SYSCON=y |
| 151 | CONFIG_VIDEO_IMX_LCDIFV3=y | 151 | CONFIG_VIDEO_IMX_LCDIFV3=y |
| 152 | CONFIG_DM_VIDEO=y | 152 | CONFIG_DM_VIDEO=y |
| 153 | CONFIG_SYS_WHITE_ON_BLACK=y | 153 | CONFIG_SYS_WHITE_ON_BLACK=y |
| 154 | 154 | ||
| 155 | CONFIG_LZ4=y | 155 | CONFIG_LZ4=y |
| 156 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y | 156 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y |
| 157 | CONFIG_APPEND_BOOTARGS=y | 157 | CONFIG_APPEND_BOOTARGS=y |
| 158 | CONFIG_SPL_MMC_SUPPORT=y | 158 | CONFIG_SPL_MMC_SUPPORT=y |
| 159 | CONFIG_AVB_WARNING_LOGO=y | 159 | CONFIG_AVB_WARNING_LOGO=y |
| 160 | CONFIG_AVB_WARNING_LOGO_COLS=0x320 | 160 | CONFIG_AVB_WARNING_LOGO_COLS=0x320 |
| 161 | CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 | 161 | CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 |
| 162 | CONFIG_VIRTUAL_AB_SUPPORT=y | 162 | CONFIG_VIRTUAL_AB_SUPPORT=y |
| 163 | CONFIG_ANDROID_SUPPORT=y | 163 | CONFIG_ANDROID_SUPPORT=y |
| 164 | CONFIG_APPEND_BOOTARGS=y | 164 | CONFIG_APPEND_BOOTARGS=y |
| 165 | CONFIG_ANDROID_AB_SUPPORT=y | 165 | CONFIG_ANDROID_AB_SUPPORT=y |
| 166 | 166 |
configs/smarcimx8mp_6g_ser2_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_SYS_ICACHE_OFF=y | 2 | CONFIG_SPL_SYS_ICACHE_OFF=y |
| 3 | CONFIG_SPL_SYS_DCACHE_OFF=y | 3 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| 4 | CONFIG_ARCH_IMX8M=y | 4 | CONFIG_ARCH_IMX8M=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x40200000 | 5 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| 6 | CONFIG_SPL_GPIO_SUPPORT=y | 6 | CONFIG_SPL_GPIO_SUPPORT=y |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y | 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 10 | CONFIG_SYS_I2C_MXC_I2C1=y | 10 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 11 | CONFIG_SYS_I2C_MXC_I2C2=y | 11 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C3=y | 12 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 13 | CONFIG_SYS_I2C_MXC_I2C4=y | 13 | CONFIG_SYS_I2C_MXC_I2C4=y |
| 14 | CONFIG_SYS_I2C_MXC_I2C6=y | 14 | CONFIG_SYS_I2C_MXC_I2C6=y |
| 15 | CONFIG_ENV_SIZE=0x1000 | 15 | CONFIG_ENV_SIZE=0x1000 |
| 16 | CONFIG_ENV_OFFSET=0x400000 | 16 | CONFIG_ENV_OFFSET=0x400000 |
| 17 | CONFIG_ENV_SECT_SIZE=0x10000 | 17 | CONFIG_ENV_SECT_SIZE=0x10000 |
| 18 | CONFIG_DM_GPIO=y | 18 | CONFIG_DM_GPIO=y |
| 19 | CONFIG_BOOTDELAY=1 | 19 | CONFIG_BOOTDELAY=1 |
| 20 | CONFIG_TARGET_SMARCIMX8MP=y | 20 | CONFIG_TARGET_SMARCIMX8MP=y |
| 21 | CONFIG_ARCH_MISC_INIT=y | 21 | CONFIG_ARCH_MISC_INIT=y |
| 22 | CONFIG_SPL_SERIAL_SUPPORT=y | 22 | CONFIG_SPL_SERIAL_SUPPORT=y |
| 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 24 | CONFIG_SPL=y | 24 | CONFIG_SPL=y |
| 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 26 | CONFIG_CSF_SIZE=0x2000 | 26 | CONFIG_CSF_SIZE=0x2000 |
| 27 | CONFIG_SPL_TEXT_BASE=0x920000 | 27 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 28 | CONFIG_FIT=y | 28 | CONFIG_FIT=y |
| 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 30 | CONFIG_SPL_LOAD_FIT=y | 30 | CONFIG_SPL_LOAD_FIT=y |
| 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" |
| 32 | CONFIG_OF_SYSTEM_SETUP=y | 32 | CONFIG_OF_SYSTEM_SETUP=y |
| 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,6GB_LPDDR4" | 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,6GB_LPDDR4" |
| 34 | CONFIG_CONSOLE_SER2=y | 34 | CONFIG_CONSOLE_SER2=y |
| 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" | 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" |
| 36 | CONFIG_BOARD_LATE_INIT=y | 36 | CONFIG_BOARD_LATE_INIT=y |
| 37 | CONFIG_BOARD_EARLY_INIT_F=y | 37 | CONFIG_BOARD_EARLY_INIT_F=y |
| 38 | CONFIG_SPL_BOARD_INIT=y | 38 | CONFIG_SPL_BOARD_INIT=y |
| 39 | CONFIG_SPL_BOOTROM_SUPPORT=y | 39 | CONFIG_SPL_BOOTROM_SUPPORT=y |
| 40 | CONFIG_SPL_SEPARATE_BSS=y | 40 | CONFIG_SPL_SEPARATE_BSS=y |
| 41 | CONFIG_SPL_I2C_SUPPORT=y | 41 | CONFIG_SPL_I2C_SUPPORT=y |
| 42 | CONFIG_SPL_POWER_SUPPORT=y | 42 | CONFIG_SPL_POWER_SUPPORT=y |
| 43 | CONFIG_NR_DRAM_BANKS=3 | 43 | CONFIG_NR_DRAM_BANKS=3 |
| 44 | CONFIG_HUSH_PARSER=y | 44 | CONFIG_HUSH_PARSER=y |
| 45 | CONFIG_SYS_PROMPT="u-boot$ " | 45 | CONFIG_SYS_PROMPT="u-boot$ " |
| 46 | # CONFIG_CMD_EXPORTENV is not set | 46 | # CONFIG_CMD_EXPORTENV is not set |
| 47 | CONFIG_CMD_IMPORTENV=y | 47 | CONFIG_CMD_IMPORTENV=y |
| 48 | CONFIG_CMD_ERASEENV=y | 48 | CONFIG_CMD_ERASEENV=y |
| 49 | # CONFIG_CMD_CRC32 is not set | 49 | # CONFIG_CMD_CRC32 is not set |
| 50 | # CONFIG_BOOTM_NETBSD is not set | 50 | # CONFIG_BOOTM_NETBSD is not set |
| 51 | CONFIG_CMD_CLK=y | 51 | CONFIG_CMD_CLK=y |
| 52 | CONFIG_CMD_FUSE=y | 52 | CONFIG_CMD_FUSE=y |
| 53 | CONFIG_CMD_GPIO=y | 53 | CONFIG_CMD_GPIO=y |
| 54 | CONFIG_CMD_I2C=y | 54 | CONFIG_CMD_I2C=y |
| 55 | CONFIG_CMD_MMC=y | 55 | CONFIG_CMD_MMC=y |
| 56 | CONFIG_CMD_DHCP=y | 56 | CONFIG_CMD_DHCP=y |
| 57 | CONFIG_CMD_MII=y | 57 | CONFIG_CMD_MII=y |
| 58 | CONFIG_CMD_PING=y | 58 | CONFIG_CMD_PING=y |
| 59 | CONFIG_CMD_CACHE=y | 59 | CONFIG_CMD_CACHE=y |
| 60 | CONFIG_CMD_REGULATOR=y | 60 | CONFIG_CMD_REGULATOR=y |
| 61 | CONFIG_CMD_MEMTEST=y | 61 | CONFIG_CMD_MEMTEST=y |
| 62 | CONFIG_CMD_EXT2=y | 62 | CONFIG_CMD_EXT2=y |
| 63 | CONFIG_CMD_EXT4=y | 63 | CONFIG_CMD_EXT4=y |
| 64 | CONFIG_CMD_EXT4_WRITE=y | 64 | CONFIG_CMD_EXT4_WRITE=y |
| 65 | CONFIG_CMD_FAT=y | 65 | CONFIG_CMD_FAT=y |
| 66 | CONFIG_CMD_SF=y | 66 | CONFIG_CMD_SF=y |
| 67 | CONFIG_CMD_LED=y | 67 | CONFIG_CMD_LED=y |
| 68 | CONFIG_OF_CONTROL=y | 68 | CONFIG_OF_CONTROL=y |
| 69 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" | 69 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" |
| 70 | CONFIG_ENV_IS_IN_MMC=y | 70 | CONFIG_ENV_IS_IN_MMC=y |
| 71 | CONFIG_ENV_IS_IN_SPI_FLASH=y | 71 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 72 | CONFIG_ENV_IS_NOWHERE=y | 72 | CONFIG_ENV_IS_NOWHERE=y |
| 73 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | 73 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 74 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | 74 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 75 | CONFIG_CLK_COMPOSITE_CCF=y | 75 | CONFIG_CLK_COMPOSITE_CCF=y |
| 76 | CONFIG_CLK_IMX8MP=y | 76 | CONFIG_CLK_IMX8MP=y |
| 77 | CONFIG_MXC_GPIO=y | 77 | CONFIG_MXC_GPIO=y |
| 78 | CONFIG_DM_PCA953X=y | 78 | CONFIG_DM_PCA953X=y |
| 79 | CONFIG_FASTBOOT=y | 79 | CONFIG_FASTBOOT=y |
| 80 | CONFIG_USB_FUNCTION_FASTBOOT=y | 80 | CONFIG_USB_FUNCTION_FASTBOOT=y |
| 81 | CONFIG_CMD_FASTBOOT=y | 81 | CONFIG_CMD_FASTBOOT=y |
| 82 | CONFIG_ANDROID_BOOT_IMAGE=y | 82 | CONFIG_ANDROID_BOOT_IMAGE=y |
| 83 | CONFIG_FASTBOOT_UUU_SUPPORT=y | 83 | CONFIG_FASTBOOT_UUU_SUPPORT=y |
| 84 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 84 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
| 85 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 85 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
| 86 | CONFIG_FASTBOOT_FLASH=y | 86 | CONFIG_FASTBOOT_FLASH=y |
| 87 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 | 87 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
| 88 | CONFIG_DM_I2C=y | 88 | CONFIG_DM_I2C=y |
| 89 | CONFIG_CMD_GPT=y | 89 | CONFIG_CMD_GPT=y |
| 90 | CONFIG_CMD_TIME=y | 90 | CONFIG_CMD_TIME=y |
| 91 | CONFIG_SYS_I2C_MXC=y | 91 | CONFIG_SYS_I2C_MXC=y |
| 92 | CONFIG_LED=y | 92 | CONFIG_LED=y |
| 93 | CONFIG_LED_GPIO=y | 93 | CONFIG_LED_GPIO=y |
| 94 | CONFIG_DM_MMC=y | 94 | CONFIG_DM_MMC=y |
| 95 | CONFIG_MMC_IO_VOLTAGE=y | 95 | # CONFIG_MMC_IO_VOLTAGE is not set |
| 96 | CONFIG_MMC_UHS_SUPPORT=y | 96 | CONFIG_MMC_UHS_SUPPORT=y |
| 97 | CONFIG_MMC_HS400_SUPPORT=y | 97 | CONFIG_MMC_HS400_SUPPORT=y |
| 98 | CONFIG_MMC_HS400_ES_SUPPORT=y | 98 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 99 | CONFIG_EFI_PARTITION=y | 99 | CONFIG_EFI_PARTITION=y |
| 100 | CONFIG_SUPPORT_EMMC_BOOT=y | 100 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 101 | CONFIG_FSL_ESDHC_IMX=y | 101 | CONFIG_FSL_ESDHC_IMX=y |
| 102 | CONFIG_DM_SPI_FLASH=y | 102 | CONFIG_DM_SPI_FLASH=y |
| 103 | CONFIG_DM_SPI=y | 103 | CONFIG_DM_SPI=y |
| 104 | CONFIG_FSL_FSPI=y | 104 | CONFIG_FSL_FSPI=y |
| 105 | CONFIG_SPI=y | 105 | CONFIG_SPI=y |
| 106 | CONFIG_SPI_FLASH=y | 106 | CONFIG_SPI_FLASH=y |
| 107 | CONFIG_SPI_FLASH_BAR=y | 107 | CONFIG_SPI_FLASH_BAR=y |
| 108 | CONFIG_SPI_FLASH_MACRONIX=y | 108 | CONFIG_SPI_FLASH_MACRONIX=y |
| 109 | CONFIG_SF_DEFAULT_BUS=0 | 109 | CONFIG_SF_DEFAULT_BUS=0 |
| 110 | CONFIG_SF_DEFAULT_CS=0 | 110 | CONFIG_SF_DEFAULT_CS=0 |
| 111 | CONFIG_SF_DEFAULT_SPEED=40000000 | 111 | CONFIG_SF_DEFAULT_SPEED=40000000 |
| 112 | CONFIG_SF_DEFAULT_MODE=0 | 112 | CONFIG_SF_DEFAULT_MODE=0 |
| 113 | 113 | ||
| 114 | CONFIG_DM_ETH=y | 114 | CONFIG_DM_ETH=y |
| 115 | # CONFIG_DM_ETH_PHY=y | 115 | # CONFIG_DM_ETH_PHY=y |
| 116 | CONFIG_DWC_ETH_QOS=y | 116 | CONFIG_DWC_ETH_QOS=y |
| 117 | 117 | ||
| 118 | CONFIG_PHY_GIGE=y | 118 | CONFIG_PHY_GIGE=y |
| 119 | CONFIG_FEC_MXC=y | 119 | CONFIG_FEC_MXC=y |
| 120 | CONFIG_MII=y | 120 | CONFIG_MII=y |
| 121 | CONFIG_PHYLIB=y | 121 | CONFIG_PHYLIB=y |
| 122 | CONFIG_PHY_ATHEROS=y | 122 | CONFIG_PHY_ATHEROS=y |
| 123 | 123 | ||
| 124 | CONFIG_PINCTRL=y | 124 | CONFIG_PINCTRL=y |
| 125 | CONFIG_PINCTRL_IMX8M=y | 125 | CONFIG_PINCTRL_IMX8M=y |
| 126 | CONFIG_DM_REGULATOR=y | 126 | CONFIG_DM_REGULATOR=y |
| 127 | CONFIG_DM_REGULATOR_FIXED=y | 127 | CONFIG_DM_REGULATOR_FIXED=y |
| 128 | CONFIG_DM_REGULATOR_GPIO=y | 128 | CONFIG_DM_REGULATOR_GPIO=y |
| 129 | CONFIG_MXC_UART=y | 129 | CONFIG_MXC_UART=y |
| 130 | CONFIG_SYSRESET=y | 130 | CONFIG_SYSRESET=y |
| 131 | CONFIG_SYSRESET_PSCI=y | 131 | CONFIG_SYSRESET_PSCI=y |
| 132 | CONFIG_DM_THERMAL=y | 132 | CONFIG_DM_THERMAL=y |
| 133 | CONFIG_NXP_TMU=y | 133 | CONFIG_NXP_TMU=y |
| 134 | CONFIG_USB=y | 134 | CONFIG_USB=y |
| 135 | CONFIG_USB_GADGET=y | 135 | CONFIG_USB_GADGET=y |
| 136 | CONFIG_DM_USB=y | 136 | CONFIG_DM_USB=y |
| 137 | 137 | ||
| 138 | CONFIG_OF_LIBFDT_OVERLAY=y | 138 | CONFIG_OF_LIBFDT_OVERLAY=y |
| 139 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 139 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
| 140 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 140 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
| 141 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 141 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
| 142 | CONFIG_USB_GADGET_DOWNLOAD=y | 142 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 143 | CONFIG_USB_XHCI_HCD=y | 143 | CONFIG_USB_XHCI_HCD=y |
| 144 | CONFIG_USB_XHCI_IMX8M=y | 144 | CONFIG_USB_XHCI_IMX8M=y |
| 145 | CONFIG_USB_XHCI_DWC3=y | 145 | CONFIG_USB_XHCI_DWC3=y |
| 146 | CONFIG_USB_DWC3=y | 146 | CONFIG_USB_DWC3=y |
| 147 | CONFIG_USB_DWC3_GADGET=y | 147 | CONFIG_USB_DWC3_GADGET=y |
| 148 | 148 | ||
| 149 | CONFIG_OF_BOARD_SETUP=y | 149 | CONFIG_OF_BOARD_SETUP=y |
| 150 | 150 | ||
| 151 | CONFIG_REGMAP=y | 151 | CONFIG_REGMAP=y |
| 152 | CONFIG_SYSCON=y | 152 | CONFIG_SYSCON=y |
| 153 | CONFIG_VIDEO_IMX_LCDIFV3=y | 153 | CONFIG_VIDEO_IMX_LCDIFV3=y |
| 154 | CONFIG_DM_VIDEO=y | 154 | CONFIG_DM_VIDEO=y |
| 155 | CONFIG_SYS_WHITE_ON_BLACK=y | 155 | CONFIG_SYS_WHITE_ON_BLACK=y |
| 156 | 156 |
configs/smarcimx8mp_6g_ser3_android_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_SYS_ICACHE_OFF=y | 2 | CONFIG_SPL_SYS_ICACHE_OFF=y |
| 3 | CONFIG_SPL_SYS_DCACHE_OFF=y | 3 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| 4 | CONFIG_ARCH_IMX8M=y | 4 | CONFIG_ARCH_IMX8M=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x40200000 | 5 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| 6 | CONFIG_SPL_GPIO_SUPPORT=y | 6 | CONFIG_SPL_GPIO_SUPPORT=y |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y | 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 10 | CONFIG_SYS_I2C_MXC_I2C1=y | 10 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 11 | CONFIG_SYS_I2C_MXC_I2C2=y | 11 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C3=y | 12 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 13 | CONFIG_SYS_I2C_MXC_I2C4=y | 13 | CONFIG_SYS_I2C_MXC_I2C4=y |
| 14 | CONFIG_SYS_I2C_MXC_I2C6=y | 14 | CONFIG_SYS_I2C_MXC_I2C6=y |
| 15 | CONFIG_ENV_SIZE=0x1000 | 15 | CONFIG_ENV_SIZE=0x1000 |
| 16 | CONFIG_ENV_OFFSET=0x400000 | 16 | CONFIG_ENV_OFFSET=0x400000 |
| 17 | CONFIG_ENV_SECT_SIZE=0x10000 | 17 | CONFIG_ENV_SECT_SIZE=0x10000 |
| 18 | CONFIG_DM_GPIO=y | 18 | CONFIG_DM_GPIO=y |
| 19 | CONFIG_BOOTDELAY=1 | 19 | CONFIG_BOOTDELAY=1 |
| 20 | CONFIG_TARGET_SMARCIMX8MP=y | 20 | CONFIG_TARGET_SMARCIMX8MP=y |
| 21 | CONFIG_ARCH_MISC_INIT=y | 21 | CONFIG_ARCH_MISC_INIT=y |
| 22 | CONFIG_SPL_SERIAL_SUPPORT=y | 22 | CONFIG_SPL_SERIAL_SUPPORT=y |
| 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 24 | CONFIG_SPL=y | 24 | CONFIG_SPL=y |
| 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 26 | CONFIG_CSF_SIZE=0x2000 | 26 | CONFIG_CSF_SIZE=0x2000 |
| 27 | CONFIG_SPL_TEXT_BASE=0x920000 | 27 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 28 | CONFIG_FIT=y | 28 | CONFIG_FIT=y |
| 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 30 | CONFIG_SPL_LOAD_FIT=y | 30 | CONFIG_SPL_LOAD_FIT=y |
| 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" |
| 32 | CONFIG_OF_SYSTEM_SETUP=y | 32 | CONFIG_OF_SYSTEM_SETUP=y |
| 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,6GB_LPDDR4" | 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,6GB_LPDDR4" |
| 34 | CONFIG_CONSOLE_SER3=y | 34 | CONFIG_CONSOLE_SER3=y |
| 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" | 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" |
| 36 | CONFIG_BOARD_LATE_INIT=y | 36 | CONFIG_BOARD_LATE_INIT=y |
| 37 | CONFIG_BOARD_EARLY_INIT_F=y | 37 | CONFIG_BOARD_EARLY_INIT_F=y |
| 38 | CONFIG_SPL_BOARD_INIT=y | 38 | CONFIG_SPL_BOARD_INIT=y |
| 39 | CONFIG_SPL_SEPARATE_BSS=y | 39 | CONFIG_SPL_SEPARATE_BSS=y |
| 40 | CONFIG_SPL_I2C_SUPPORT=y | 40 | CONFIG_SPL_I2C_SUPPORT=y |
| 41 | CONFIG_SPL_POWER_SUPPORT=y | 41 | CONFIG_SPL_POWER_SUPPORT=y |
| 42 | CONFIG_NR_DRAM_BANKS=3 | 42 | CONFIG_NR_DRAM_BANKS=3 |
| 43 | CONFIG_HUSH_PARSER=y | 43 | CONFIG_HUSH_PARSER=y |
| 44 | CONFIG_SYS_PROMPT="u-boot$ " | 44 | CONFIG_SYS_PROMPT="u-boot$ " |
| 45 | # CONFIG_CMD_EXPORTENV is not set | 45 | # CONFIG_CMD_EXPORTENV is not set |
| 46 | CONFIG_CMD_IMPORTENV=y | 46 | CONFIG_CMD_IMPORTENV=y |
| 47 | CONFIG_CMD_ERASEENV=y | 47 | CONFIG_CMD_ERASEENV=y |
| 48 | # CONFIG_CMD_CRC32 is not set | 48 | # CONFIG_CMD_CRC32 is not set |
| 49 | # CONFIG_BOOTM_NETBSD is not set | 49 | # CONFIG_BOOTM_NETBSD is not set |
| 50 | CONFIG_CMD_CLK=y | 50 | CONFIG_CMD_CLK=y |
| 51 | CONFIG_CMD_FUSE=y | 51 | CONFIG_CMD_FUSE=y |
| 52 | CONFIG_CMD_GPIO=y | 52 | CONFIG_CMD_GPIO=y |
| 53 | CONFIG_CMD_I2C=y | 53 | CONFIG_CMD_I2C=y |
| 54 | CONFIG_CMD_MMC=y | 54 | CONFIG_CMD_MMC=y |
| 55 | CONFIG_CMD_DHCP=y | 55 | CONFIG_CMD_DHCP=y |
| 56 | CONFIG_CMD_MII=y | 56 | CONFIG_CMD_MII=y |
| 57 | CONFIG_CMD_PING=y | 57 | CONFIG_CMD_PING=y |
| 58 | CONFIG_CMD_CACHE=y | 58 | CONFIG_CMD_CACHE=y |
| 59 | CONFIG_CMD_REGULATOR=y | 59 | CONFIG_CMD_REGULATOR=y |
| 60 | CONFIG_CMD_MEMTEST=y | 60 | CONFIG_CMD_MEMTEST=y |
| 61 | CONFIG_CMD_EXT2=y | 61 | CONFIG_CMD_EXT2=y |
| 62 | CONFIG_CMD_EXT4=y | 62 | CONFIG_CMD_EXT4=y |
| 63 | CONFIG_CMD_EXT4_WRITE=y | 63 | CONFIG_CMD_EXT4_WRITE=y |
| 64 | CONFIG_CMD_FAT=y | 64 | CONFIG_CMD_FAT=y |
| 65 | CONFIG_CMD_SF=y | 65 | CONFIG_CMD_SF=y |
| 66 | CONFIG_CMD_LED=y | 66 | CONFIG_CMD_LED=y |
| 67 | CONFIG_OF_CONTROL=y | 67 | CONFIG_OF_CONTROL=y |
| 68 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" | 68 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" |
| 69 | CONFIG_ENV_IS_IN_MMC=y | 69 | CONFIG_ENV_IS_IN_MMC=y |
| 70 | CONFIG_ENV_IS_IN_SPI_FLASH=y | 70 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 71 | CONFIG_ENV_IS_NOWHERE=y | 71 | CONFIG_ENV_IS_NOWHERE=y |
| 72 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | 72 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 73 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | 73 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 74 | CONFIG_CLK_COMPOSITE_CCF=y | 74 | CONFIG_CLK_COMPOSITE_CCF=y |
| 75 | CONFIG_CLK_IMX8MP=y | 75 | CONFIG_CLK_IMX8MP=y |
| 76 | CONFIG_MXC_GPIO=y | 76 | CONFIG_MXC_GPIO=y |
| 77 | CONFIG_DM_PCA953X=y | 77 | CONFIG_DM_PCA953X=y |
| 78 | CONFIG_FASTBOOT=y | 78 | CONFIG_FASTBOOT=y |
| 79 | CONFIG_USB_FUNCTION_FASTBOOT=y | 79 | CONFIG_USB_FUNCTION_FASTBOOT=y |
| 80 | CONFIG_CMD_FASTBOOT=y | 80 | CONFIG_CMD_FASTBOOT=y |
| 81 | CONFIG_ANDROID_BOOT_IMAGE=y | 81 | CONFIG_ANDROID_BOOT_IMAGE=y |
| 82 | CONFIG_FASTBOOT_UUU_SUPPORT=n | 82 | CONFIG_FASTBOOT_UUU_SUPPORT=n |
| 83 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 83 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
| 84 | CONFIG_FASTBOOT_BUF_SIZE=0xc800000 | 84 | CONFIG_FASTBOOT_BUF_SIZE=0xc800000 |
| 85 | CONFIG_FASTBOOT_FLASH=y | 85 | CONFIG_FASTBOOT_FLASH=y |
| 86 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 | 86 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
| 87 | CONFIG_DM_I2C=y | 87 | CONFIG_DM_I2C=y |
| 88 | CONFIG_CMD_GPT=y | 88 | CONFIG_CMD_GPT=y |
| 89 | CONFIG_CMD_TIME=y | 89 | CONFIG_CMD_TIME=y |
| 90 | CONFIG_SYS_I2C_MXC=y | 90 | CONFIG_SYS_I2C_MXC=y |
| 91 | CONFIG_LED=y | 91 | CONFIG_LED=y |
| 92 | CONFIG_LED_GPIO=y | 92 | CONFIG_LED_GPIO=y |
| 93 | CONFIG_DM_MMC=y | 93 | CONFIG_DM_MMC=y |
| 94 | CONFIG_MMC_IO_VOLTAGE=y | 94 | # CONFIG_MMC_IO_VOLTAGE is not set |
| 95 | CONFIG_MMC_UHS_SUPPORT=y | 95 | CONFIG_MMC_UHS_SUPPORT=y |
| 96 | CONFIG_MMC_HS400_SUPPORT=y | 96 | CONFIG_MMC_HS400_SUPPORT=y |
| 97 | CONFIG_MMC_HS400_ES_SUPPORT=y | 97 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 98 | CONFIG_EFI_PARTITION=y | 98 | CONFIG_EFI_PARTITION=y |
| 99 | CONFIG_SUPPORT_EMMC_BOOT=y | 99 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 100 | CONFIG_FSL_ESDHC_IMX=y | 100 | CONFIG_FSL_ESDHC_IMX=y |
| 101 | CONFIG_DM_SPI_FLASH=y | 101 | CONFIG_DM_SPI_FLASH=y |
| 102 | CONFIG_DM_SPI=y | 102 | CONFIG_DM_SPI=y |
| 103 | CONFIG_FSL_FSPI=y | 103 | CONFIG_FSL_FSPI=y |
| 104 | CONFIG_SPI=y | 104 | CONFIG_SPI=y |
| 105 | CONFIG_SPI_FLASH=y | 105 | CONFIG_SPI_FLASH=y |
| 106 | CONFIG_SPI_FLASH_BAR=y | 106 | CONFIG_SPI_FLASH_BAR=y |
| 107 | CONFIG_SPI_FLASH_MACRONIX=y | 107 | CONFIG_SPI_FLASH_MACRONIX=y |
| 108 | CONFIG_SF_DEFAULT_BUS=0 | 108 | CONFIG_SF_DEFAULT_BUS=0 |
| 109 | CONFIG_SF_DEFAULT_CS=0 | 109 | CONFIG_SF_DEFAULT_CS=0 |
| 110 | CONFIG_SF_DEFAULT_SPEED=40000000 | 110 | CONFIG_SF_DEFAULT_SPEED=40000000 |
| 111 | CONFIG_SF_DEFAULT_MODE=0 | 111 | CONFIG_SF_DEFAULT_MODE=0 |
| 112 | 112 | ||
| 113 | CONFIG_DM_ETH=y | 113 | CONFIG_DM_ETH=y |
| 114 | # CONFIG_DM_ETH_PHY=y | 114 | # CONFIG_DM_ETH_PHY=y |
| 115 | CONFIG_DWC_ETH_QOS=y | 115 | CONFIG_DWC_ETH_QOS=y |
| 116 | 116 | ||
| 117 | CONFIG_PHY_GIGE=y | 117 | CONFIG_PHY_GIGE=y |
| 118 | CONFIG_FEC_MXC=y | 118 | CONFIG_FEC_MXC=y |
| 119 | CONFIG_MII=y | 119 | CONFIG_MII=y |
| 120 | CONFIG_PHYLIB=y | 120 | CONFIG_PHYLIB=y |
| 121 | CONFIG_PHY_ATHEROS=y | 121 | CONFIG_PHY_ATHEROS=y |
| 122 | 122 | ||
| 123 | CONFIG_PINCTRL=y | 123 | CONFIG_PINCTRL=y |
| 124 | CONFIG_PINCTRL_IMX8M=y | 124 | CONFIG_PINCTRL_IMX8M=y |
| 125 | CONFIG_DM_REGULATOR=y | 125 | CONFIG_DM_REGULATOR=y |
| 126 | CONFIG_DM_REGULATOR_FIXED=y | 126 | CONFIG_DM_REGULATOR_FIXED=y |
| 127 | CONFIG_DM_REGULATOR_GPIO=y | 127 | CONFIG_DM_REGULATOR_GPIO=y |
| 128 | CONFIG_MXC_UART=y | 128 | CONFIG_MXC_UART=y |
| 129 | CONFIG_SYSRESET=y | 129 | CONFIG_SYSRESET=y |
| 130 | CONFIG_SYSRESET_PSCI=y | 130 | CONFIG_SYSRESET_PSCI=y |
| 131 | CONFIG_DM_THERMAL=y | 131 | CONFIG_DM_THERMAL=y |
| 132 | CONFIG_NXP_TMU=y | 132 | CONFIG_NXP_TMU=y |
| 133 | CONFIG_USB=y | 133 | CONFIG_USB=y |
| 134 | CONFIG_USB_GADGET=y | 134 | CONFIG_USB_GADGET=y |
| 135 | CONFIG_DM_USB=y | 135 | CONFIG_DM_USB=y |
| 136 | 136 | ||
| 137 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 137 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
| 138 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 138 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
| 139 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 139 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
| 140 | CONFIG_USB_GADGET_DOWNLOAD=y | 140 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 141 | CONFIG_USB_XHCI_HCD=y | 141 | CONFIG_USB_XHCI_HCD=y |
| 142 | CONFIG_USB_XHCI_IMX8M=y | 142 | CONFIG_USB_XHCI_IMX8M=y |
| 143 | CONFIG_USB_XHCI_DWC3=y | 143 | CONFIG_USB_XHCI_DWC3=y |
| 144 | CONFIG_USB_DWC3=y | 144 | CONFIG_USB_DWC3=y |
| 145 | CONFIG_USB_DWC3_GADGET=y | 145 | CONFIG_USB_DWC3_GADGET=y |
| 146 | 146 | ||
| 147 | CONFIG_OF_BOARD_SETUP=y | 147 | CONFIG_OF_BOARD_SETUP=y |
| 148 | 148 | ||
| 149 | CONFIG_REGMAP=y | 149 | CONFIG_REGMAP=y |
| 150 | CONFIG_SYSCON=y | 150 | CONFIG_SYSCON=y |
| 151 | CONFIG_VIDEO_IMX_LCDIFV3=y | 151 | CONFIG_VIDEO_IMX_LCDIFV3=y |
| 152 | CONFIG_DM_VIDEO=y | 152 | CONFIG_DM_VIDEO=y |
| 153 | CONFIG_SYS_WHITE_ON_BLACK=y | 153 | CONFIG_SYS_WHITE_ON_BLACK=y |
| 154 | 154 | ||
| 155 | CONFIG_LZ4=y | 155 | CONFIG_LZ4=y |
| 156 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y | 156 | CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y |
| 157 | CONFIG_APPEND_BOOTARGS=y | 157 | CONFIG_APPEND_BOOTARGS=y |
| 158 | CONFIG_SPL_MMC_SUPPORT=y | 158 | CONFIG_SPL_MMC_SUPPORT=y |
| 159 | CONFIG_AVB_WARNING_LOGO=y | 159 | CONFIG_AVB_WARNING_LOGO=y |
| 160 | CONFIG_AVB_WARNING_LOGO_COLS=0x320 | 160 | CONFIG_AVB_WARNING_LOGO_COLS=0x320 |
| 161 | CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 | 161 | CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 |
| 162 | CONFIG_VIRTUAL_AB_SUPPORT=y | 162 | CONFIG_VIRTUAL_AB_SUPPORT=y |
| 163 | CONFIG_ANDROID_SUPPORT=y | 163 | CONFIG_ANDROID_SUPPORT=y |
| 164 | CONFIG_APPEND_BOOTARGS=y | 164 | CONFIG_APPEND_BOOTARGS=y |
| 165 | CONFIG_ANDROID_AB_SUPPORT=y | 165 | CONFIG_ANDROID_AB_SUPPORT=y |
| 166 | 166 |
configs/smarcimx8mp_6g_ser3_defconfig
| 1 | CONFIG_ARM=y | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_SYS_ICACHE_OFF=y | 2 | CONFIG_SPL_SYS_ICACHE_OFF=y |
| 3 | CONFIG_SPL_SYS_DCACHE_OFF=y | 3 | CONFIG_SPL_SYS_DCACHE_OFF=y |
| 4 | CONFIG_ARCH_IMX8M=y | 4 | CONFIG_ARCH_IMX8M=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x40200000 | 5 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| 6 | CONFIG_SPL_GPIO_SUPPORT=y | 6 | CONFIG_SPL_GPIO_SUPPORT=y |
| 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y | 7 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | 8 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | 9 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 10 | CONFIG_SYS_I2C_MXC_I2C1=y | 10 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 11 | CONFIG_SYS_I2C_MXC_I2C2=y | 11 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C3=y | 12 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 13 | CONFIG_SYS_I2C_MXC_I2C4=y | 13 | CONFIG_SYS_I2C_MXC_I2C4=y |
| 14 | CONFIG_SYS_I2C_MXC_I2C6=y | 14 | CONFIG_SYS_I2C_MXC_I2C6=y |
| 15 | CONFIG_ENV_SIZE=0x1000 | 15 | CONFIG_ENV_SIZE=0x1000 |
| 16 | CONFIG_ENV_OFFSET=0x400000 | 16 | CONFIG_ENV_OFFSET=0x400000 |
| 17 | CONFIG_ENV_SECT_SIZE=0x10000 | 17 | CONFIG_ENV_SECT_SIZE=0x10000 |
| 18 | CONFIG_DM_GPIO=y | 18 | CONFIG_DM_GPIO=y |
| 19 | CONFIG_BOOTDELAY=1 | 19 | CONFIG_BOOTDELAY=1 |
| 20 | CONFIG_TARGET_SMARCIMX8MP=y | 20 | CONFIG_TARGET_SMARCIMX8MP=y |
| 21 | CONFIG_ARCH_MISC_INIT=y | 21 | CONFIG_ARCH_MISC_INIT=y |
| 22 | CONFIG_SPL_SERIAL_SUPPORT=y | 22 | CONFIG_SPL_SERIAL_SUPPORT=y |
| 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | 23 | CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
| 24 | CONFIG_SPL=y | 24 | CONFIG_SPL=y |
| 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | 25 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 26 | CONFIG_CSF_SIZE=0x2000 | 26 | CONFIG_CSF_SIZE=0x2000 |
| 27 | CONFIG_SPL_TEXT_BASE=0x920000 | 27 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 28 | CONFIG_FIT=y | 28 | CONFIG_FIT=y |
| 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | 29 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 30 | CONFIG_SPL_LOAD_FIT=y | 30 | CONFIG_SPL_LOAD_FIT=y |
| 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | 31 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" |
| 32 | CONFIG_OF_SYSTEM_SETUP=y | 32 | CONFIG_OF_SYSTEM_SETUP=y |
| 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,6GB_LPDDR4" | 33 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg,6GB_LPDDR4" |
| 34 | CONFIG_CONSOLE_SER3=y | 34 | CONFIG_CONSOLE_SER3=y |
| 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" | 35 | CONFIG_DEFAULT_FDT_FILE="imx8mp-smarc.dtb" |
| 36 | CONFIG_BOARD_LATE_INIT=y | 36 | CONFIG_BOARD_LATE_INIT=y |
| 37 | CONFIG_BOARD_EARLY_INIT_F=y | 37 | CONFIG_BOARD_EARLY_INIT_F=y |
| 38 | CONFIG_SPL_BOARD_INIT=y | 38 | CONFIG_SPL_BOARD_INIT=y |
| 39 | CONFIG_SPL_BOOTROM_SUPPORT=y | 39 | CONFIG_SPL_BOOTROM_SUPPORT=y |
| 40 | CONFIG_SPL_SEPARATE_BSS=y | 40 | CONFIG_SPL_SEPARATE_BSS=y |
| 41 | CONFIG_SPL_I2C_SUPPORT=y | 41 | CONFIG_SPL_I2C_SUPPORT=y |
| 42 | CONFIG_SPL_POWER_SUPPORT=y | 42 | CONFIG_SPL_POWER_SUPPORT=y |
| 43 | CONFIG_NR_DRAM_BANKS=3 | 43 | CONFIG_NR_DRAM_BANKS=3 |
| 44 | CONFIG_HUSH_PARSER=y | 44 | CONFIG_HUSH_PARSER=y |
| 45 | CONFIG_SYS_PROMPT="u-boot$ " | 45 | CONFIG_SYS_PROMPT="u-boot$ " |
| 46 | # CONFIG_CMD_EXPORTENV is not set | 46 | # CONFIG_CMD_EXPORTENV is not set |
| 47 | CONFIG_CMD_IMPORTENV=y | 47 | CONFIG_CMD_IMPORTENV=y |
| 48 | CONFIG_CMD_ERASEENV=y | 48 | CONFIG_CMD_ERASEENV=y |
| 49 | # CONFIG_CMD_CRC32 is not set | 49 | # CONFIG_CMD_CRC32 is not set |
| 50 | # CONFIG_BOOTM_NETBSD is not set | 50 | # CONFIG_BOOTM_NETBSD is not set |
| 51 | CONFIG_CMD_CLK=y | 51 | CONFIG_CMD_CLK=y |
| 52 | CONFIG_CMD_FUSE=y | 52 | CONFIG_CMD_FUSE=y |
| 53 | CONFIG_CMD_GPIO=y | 53 | CONFIG_CMD_GPIO=y |
| 54 | CONFIG_CMD_I2C=y | 54 | CONFIG_CMD_I2C=y |
| 55 | CONFIG_CMD_MMC=y | 55 | CONFIG_CMD_MMC=y |
| 56 | CONFIG_CMD_DHCP=y | 56 | CONFIG_CMD_DHCP=y |
| 57 | CONFIG_CMD_MII=y | 57 | CONFIG_CMD_MII=y |
| 58 | CONFIG_CMD_PING=y | 58 | CONFIG_CMD_PING=y |
| 59 | CONFIG_CMD_CACHE=y | 59 | CONFIG_CMD_CACHE=y |
| 60 | CONFIG_CMD_REGULATOR=y | 60 | CONFIG_CMD_REGULATOR=y |
| 61 | CONFIG_CMD_MEMTEST=y | 61 | CONFIG_CMD_MEMTEST=y |
| 62 | CONFIG_CMD_EXT2=y | 62 | CONFIG_CMD_EXT2=y |
| 63 | CONFIG_CMD_EXT4=y | 63 | CONFIG_CMD_EXT4=y |
| 64 | CONFIG_CMD_EXT4_WRITE=y | 64 | CONFIG_CMD_EXT4_WRITE=y |
| 65 | CONFIG_CMD_FAT=y | 65 | CONFIG_CMD_FAT=y |
| 66 | CONFIG_CMD_SF=y | 66 | CONFIG_CMD_SF=y |
| 67 | CONFIG_CMD_LED=y | 67 | CONFIG_CMD_LED=y |
| 68 | CONFIG_OF_CONTROL=y | 68 | CONFIG_OF_CONTROL=y |
| 69 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" | 69 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-smarc" |
| 70 | CONFIG_ENV_IS_IN_MMC=y | 70 | CONFIG_ENV_IS_IN_MMC=y |
| 71 | CONFIG_ENV_IS_IN_SPI_FLASH=y | 71 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 72 | CONFIG_ENV_IS_NOWHERE=y | 72 | CONFIG_ENV_IS_NOWHERE=y |
| 73 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | 73 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 74 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | 74 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 75 | CONFIG_CLK_COMPOSITE_CCF=y | 75 | CONFIG_CLK_COMPOSITE_CCF=y |
| 76 | CONFIG_CLK_IMX8MP=y | 76 | CONFIG_CLK_IMX8MP=y |
| 77 | CONFIG_MXC_GPIO=y | 77 | CONFIG_MXC_GPIO=y |
| 78 | CONFIG_DM_PCA953X=y | 78 | CONFIG_DM_PCA953X=y |
| 79 | CONFIG_FASTBOOT=y | 79 | CONFIG_FASTBOOT=y |
| 80 | CONFIG_USB_FUNCTION_FASTBOOT=y | 80 | CONFIG_USB_FUNCTION_FASTBOOT=y |
| 81 | CONFIG_CMD_FASTBOOT=y | 81 | CONFIG_CMD_FASTBOOT=y |
| 82 | CONFIG_ANDROID_BOOT_IMAGE=y | 82 | CONFIG_ANDROID_BOOT_IMAGE=y |
| 83 | CONFIG_FASTBOOT_UUU_SUPPORT=y | 83 | CONFIG_FASTBOOT_UUU_SUPPORT=y |
| 84 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | 84 | CONFIG_FASTBOOT_BUF_ADDR=0x42800000 |
| 85 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | 85 | CONFIG_FASTBOOT_BUF_SIZE=0x40000000 |
| 86 | CONFIG_FASTBOOT_FLASH=y | 86 | CONFIG_FASTBOOT_FLASH=y |
| 87 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 | 87 | CONFIG_FASTBOOT_FLASH_MMC_DEV=2 |
| 88 | CONFIG_DM_I2C=y | 88 | CONFIG_DM_I2C=y |
| 89 | CONFIG_CMD_GPT=y | 89 | CONFIG_CMD_GPT=y |
| 90 | CONFIG_CMD_TIME=y | 90 | CONFIG_CMD_TIME=y |
| 91 | CONFIG_SYS_I2C_MXC=y | 91 | CONFIG_SYS_I2C_MXC=y |
| 92 | CONFIG_LED=y | 92 | CONFIG_LED=y |
| 93 | CONFIG_LED_GPIO=y | 93 | CONFIG_LED_GPIO=y |
| 94 | CONFIG_DM_MMC=y | 94 | CONFIG_DM_MMC=y |
| 95 | CONFIG_MMC_IO_VOLTAGE=y | 95 | # CONFIG_MMC_IO_VOLTAGE is not set |
| 96 | CONFIG_MMC_UHS_SUPPORT=y | 96 | CONFIG_MMC_UHS_SUPPORT=y |
| 97 | CONFIG_MMC_HS400_SUPPORT=y | 97 | CONFIG_MMC_HS400_SUPPORT=y |
| 98 | CONFIG_MMC_HS400_ES_SUPPORT=y | 98 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 99 | CONFIG_EFI_PARTITION=y | 99 | CONFIG_EFI_PARTITION=y |
| 100 | CONFIG_SUPPORT_EMMC_BOOT=y | 100 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 101 | CONFIG_FSL_ESDHC_IMX=y | 101 | CONFIG_FSL_ESDHC_IMX=y |
| 102 | CONFIG_DM_SPI_FLASH=y | 102 | CONFIG_DM_SPI_FLASH=y |
| 103 | CONFIG_DM_SPI=y | 103 | CONFIG_DM_SPI=y |
| 104 | CONFIG_FSL_FSPI=y | 104 | CONFIG_FSL_FSPI=y |
| 105 | CONFIG_SPI=y | 105 | CONFIG_SPI=y |
| 106 | CONFIG_SPI_FLASH=y | 106 | CONFIG_SPI_FLASH=y |
| 107 | CONFIG_SPI_FLASH_BAR=y | 107 | CONFIG_SPI_FLASH_BAR=y |
| 108 | CONFIG_SPI_FLASH_MACRONIX=y | 108 | CONFIG_SPI_FLASH_MACRONIX=y |
| 109 | CONFIG_SF_DEFAULT_BUS=0 | 109 | CONFIG_SF_DEFAULT_BUS=0 |
| 110 | CONFIG_SF_DEFAULT_CS=0 | 110 | CONFIG_SF_DEFAULT_CS=0 |
| 111 | CONFIG_SF_DEFAULT_SPEED=40000000 | 111 | CONFIG_SF_DEFAULT_SPEED=40000000 |
| 112 | CONFIG_SF_DEFAULT_MODE=0 | 112 | CONFIG_SF_DEFAULT_MODE=0 |
| 113 | 113 | ||
| 114 | CONFIG_DM_ETH=y | 114 | CONFIG_DM_ETH=y |
| 115 | # CONFIG_DM_ETH_PHY=y | 115 | # CONFIG_DM_ETH_PHY=y |
| 116 | CONFIG_DWC_ETH_QOS=y | 116 | CONFIG_DWC_ETH_QOS=y |
| 117 | 117 | ||
| 118 | CONFIG_PHY_GIGE=y | 118 | CONFIG_PHY_GIGE=y |
| 119 | CONFIG_FEC_MXC=y | 119 | CONFIG_FEC_MXC=y |
| 120 | CONFIG_MII=y | 120 | CONFIG_MII=y |
| 121 | CONFIG_PHYLIB=y | 121 | CONFIG_PHYLIB=y |
| 122 | CONFIG_PHY_ATHEROS=y | 122 | CONFIG_PHY_ATHEROS=y |
| 123 | 123 | ||
| 124 | CONFIG_PINCTRL=y | 124 | CONFIG_PINCTRL=y |
| 125 | CONFIG_PINCTRL_IMX8M=y | 125 | CONFIG_PINCTRL_IMX8M=y |
| 126 | CONFIG_DM_REGULATOR=y | 126 | CONFIG_DM_REGULATOR=y |
| 127 | CONFIG_DM_REGULATOR_FIXED=y | 127 | CONFIG_DM_REGULATOR_FIXED=y |
| 128 | CONFIG_DM_REGULATOR_GPIO=y | 128 | CONFIG_DM_REGULATOR_GPIO=y |
| 129 | CONFIG_MXC_UART=y | 129 | CONFIG_MXC_UART=y |
| 130 | CONFIG_SYSRESET=y | 130 | CONFIG_SYSRESET=y |
| 131 | CONFIG_SYSRESET_PSCI=y | 131 | CONFIG_SYSRESET_PSCI=y |
| 132 | CONFIG_DM_THERMAL=y | 132 | CONFIG_DM_THERMAL=y |
| 133 | CONFIG_NXP_TMU=y | 133 | CONFIG_NXP_TMU=y |
| 134 | CONFIG_USB=y | 134 | CONFIG_USB=y |
| 135 | CONFIG_USB_GADGET=y | 135 | CONFIG_USB_GADGET=y |
| 136 | CONFIG_DM_USB=y | 136 | CONFIG_DM_USB=y |
| 137 | 137 | ||
| 138 | CONFIG_OF_LIBFDT_OVERLAY=y | 138 | CONFIG_OF_LIBFDT_OVERLAY=y |
| 139 | CONFIG_USB_GADGET_MANUFACTURER="FSL" | 139 | CONFIG_USB_GADGET_MANUFACTURER="FSL" |
| 140 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | 140 | CONFIG_USB_GADGET_VENDOR_NUM=0x0525 |
| 141 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | 141 | CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 |
| 142 | CONFIG_USB_GADGET_DOWNLOAD=y | 142 | CONFIG_USB_GADGET_DOWNLOAD=y |
| 143 | CONFIG_USB_XHCI_HCD=y | 143 | CONFIG_USB_XHCI_HCD=y |
| 144 | CONFIG_USB_XHCI_IMX8M=y | 144 | CONFIG_USB_XHCI_IMX8M=y |
| 145 | CONFIG_USB_XHCI_DWC3=y | 145 | CONFIG_USB_XHCI_DWC3=y |
| 146 | CONFIG_USB_DWC3=y | 146 | CONFIG_USB_DWC3=y |
| 147 | CONFIG_USB_DWC3_GADGET=y | 147 | CONFIG_USB_DWC3_GADGET=y |
| 148 | 148 | ||
| 149 | CONFIG_OF_BOARD_SETUP=y | 149 | CONFIG_OF_BOARD_SETUP=y |
| 150 | 150 | ||
| 151 | CONFIG_REGMAP=y | 151 | CONFIG_REGMAP=y |
| 152 | CONFIG_SYSCON=y | 152 | CONFIG_SYSCON=y |
| 153 | CONFIG_VIDEO_IMX_LCDIFV3=y | 153 | CONFIG_VIDEO_IMX_LCDIFV3=y |
| 154 | CONFIG_DM_VIDEO=y | 154 | CONFIG_DM_VIDEO=y |
| 155 | CONFIG_SYS_WHITE_ON_BLACK=y | 155 | CONFIG_SYS_WHITE_ON_BLACK=y |
| 156 | 156 |