Eric Lee / smarc-uboot

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Commit 57fa56f3ce6028b3b8cc75a905ba230dbee522dc

Authored by Zhang Bo
1 parent f3e266d088
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 4 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MA-14501[Android] change BOOTAUX_RESERVED_MEM macro to defconfig 

As the M4 use different DDR memory size in normal android/car2 and car
image, use different defconfig for car2 to decrease DDR memory
reservation. So memory reserved for each M4 core is 8MB in car2 and
normal android image. it's 32MB for car image.

Change-Id: Idf608f539cd614a154c78e3a1af28eff1da5c1f2
Signed-off-by: Zhang Bo <bo.zhang@nxp.com>

Showing 41 changed files with 369 additions and 11 deletions Inline Diff

arch/arm/mach-imx/Kconfig
Diff comments   View file @ 57fa56f
1 config HAS_CAAM 1 config HAS_CAAM
2 bool 2 bool
3 3
4 config IMX_CONFIG 4 config IMX_CONFIG
5 string 5 string
6 6
7 config IMX_OPTEE 7 config IMX_OPTEE
8 bool "Support OP-TEE" 8 bool "Support OP-TEE"
9 help 9 help
10 Enable support for OP-TEE 10 Enable support for OP-TEE
11 11
12 config ROM_UNIFIED_SECTIONS 12 config ROM_UNIFIED_SECTIONS
13 bool 13 bool
14 14
15 config SYSCOUNTER_TIMER 15 config SYSCOUNTER_TIMER
16 bool 16 bool
17 17
18 config GPT_TIMER 18 config GPT_TIMER
19 bool 19 bool
20 20
21 config FSL_CAAM_KB 21 config FSL_CAAM_KB
22 bool 22 bool
23 23
24 config IMX_SEC_INIT 24 config IMX_SEC_INIT
25 bool 25 bool
26 help 26 help
27 In most of i.MX board with CAAM this option is used 27 In most of i.MX board with CAAM this option is used
28 to init RNG from U-Boot 28 to init RNG from U-Boot
29 select FSL_CAAM_KB 29 select FSL_CAAM_KB
30 select SPL_CRYPTO_SUPPORT if SPL 30 select SPL_CRYPTO_SUPPORT if SPL
31 31
32 config IMX_RDC 32 config IMX_RDC
33 bool "i.MX Resource domain controller driver" 33 bool "i.MX Resource domain controller driver"
34 depends on ARCH_MX6 || ARCH_MX7 34 depends on ARCH_MX6 || ARCH_MX7
35 help 35 help
36 i.MX Resource domain controller is used to assign masters 36 i.MX Resource domain controller is used to assign masters
37 and peripherals to differet domains. This can be used to 37 and peripherals to differet domains. This can be used to
38 isolate resources. 38 isolate resources.
39 39
40 config IMX_BOOTAUX 40 config IMX_BOOTAUX
41 bool "Support boot auxiliary core" 41 bool "Support boot auxiliary core"
42 depends on ARCH_MX7 || ARCH_MX6 || ARCH_IMX8 || ARCH_IMX8M 42 depends on ARCH_MX7 || ARCH_MX6 || ARCH_IMX8 || ARCH_IMX8M
43 help 43 help
44 bootaux [addr] to boot auxiliary core. 44 bootaux [addr] to boot auxiliary core.
45 45
46 config BOOTAUX_RESERVED_MEM_BASE
47 hex "Define the reserved memory base address"
48 default 0x00
49 depends on ARCH_IMX8
50 help
51 reserve DDR memory for bootaux
52
53 config BOOTAUX_RESERVED_MEM_SIZE
54 hex "Define the reserved memory size"
55 default 0x00
56 depends on ARCH_IMX8
57 help
58 This memory will be reserved by system and linux cannot access.
59
46 config IMX_VSERVICE_SHARED_BUFFER 60 config IMX_VSERVICE_SHARED_BUFFER
47 hex "Define the buffer address used for virtual service" 61 hex "Define the buffer address used for virtual service"
48 depends on IMX_VSERVICE 62 depends on IMX_VSERVICE
49 help 63 help
50 IMX virtual service will use this buffer for exchanging data with remote core. 64 IMX virtual service will use this buffer for exchanging data with remote core.
51 65
52 config IMX_VSERVICE_SHARED_BUFFER_SIZE 66 config IMX_VSERVICE_SHARED_BUFFER_SIZE
53 hex "Define the size of buffer address used for virtual service" 67 hex "Define the size of buffer address used for virtual service"
54 default 0x400000 68 default 0x400000
55 depends on IMX_VSERVICE 69 depends on IMX_VSERVICE
56 help 70 help
57 The buffer size for IMX virtual service needs enough large to fit all possible message. 71 The buffer size for IMX virtual service needs enough large to fit all possible message.
58 72
59 config IMX_VSERVICE 73 config IMX_VSERVICE
60 bool 74 bool
61 select MISC 75 select MISC
62 select IMX_M4_MU 76 select IMX_M4_MU
63 help 77 help
64 This enables imx virtual service provides framework for imx virtual driver working. 78 This enables imx virtual service provides framework for imx virtual driver working.
65 79
66 config USE_IMXIMG_PLUGIN 80 config USE_IMXIMG_PLUGIN
67 bool "Use imximage plugin code" 81 bool "Use imximage plugin code"
68 depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX7ULP 82 depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX7ULP
69 help 83 help
70 i.MX6/7 supports DCD and Plugin. Enable this configuration 84 i.MX6/7 supports DCD and Plugin. Enable this configuration
71 to use Plugin, otherwise DCD will be used. 85 to use Plugin, otherwise DCD will be used.
72 86
73 config SECURE_BOOT 87 config SECURE_BOOT
74 bool "Support i.MX HAB features" 88 bool "Support i.MX HAB features"
75 depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_MX7ULP || ARCH_IMX8M 89 depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_MX7ULP || ARCH_IMX8M
76 select FSL_CAAM if HAS_CAAM 90 select FSL_CAAM if HAS_CAAM
77 imply CMD_DEKBLOB if HAS_CAAM 91 imply CMD_DEKBLOB if HAS_CAAM
78 help 92 help
79 This option enables the support for secure boot (HAB). 93 This option enables the support for secure boot (HAB).
80 See doc/README.mxc_hab for more details. 94 See doc/README.mxc_hab for more details.
81 95
82 config CMD_BMODE 96 config CMD_BMODE
83 bool "Support the 'bmode' command" 97 bool "Support the 'bmode' command"
84 default y 98 default y
85 depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 99 depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5
86 help 100 help
87 This enables the 'bmode' (bootmode) command for forcing 101 This enables the 'bmode' (bootmode) command for forcing
88 a boot from specific media. 102 a boot from specific media.
89 103
90 This is useful for forcing the ROM's usb downloader to 104 This is useful for forcing the ROM's usb downloader to
91 activate upon a watchdog reset which is nice when iterating 105 activate upon a watchdog reset which is nice when iterating
92 on U-Boot. Using the reset button or running bmode normal 106 on U-Boot. Using the reset button or running bmode normal
93 will set it back to normal. This command currently 107 will set it back to normal. This command currently
94 supports i.MX53 and i.MX6. 108 supports i.MX53 and i.MX6.
95 109
96 config CMD_DEKBLOB 110 config CMD_DEKBLOB
97 bool "Support the 'dek_blob' command" 111 bool "Support the 'dek_blob' command"
98 help 112 help
99 This enables the 'dek_blob' command which is used with the 113 This enables the 'dek_blob' command which is used with the
100 Freescale secure boot mechanism. This command encapsulates and 114 Freescale secure boot mechanism. This command encapsulates and
101 creates a blob of data. See also CMD_BLOB and doc/README.mxc_hab for 115 creates a blob of data. See also CMD_BLOB and doc/README.mxc_hab for
102 more information. 116 more information.
103 117
104 config CMD_PRIBLOB 118 config CMD_PRIBLOB
105 bool "Support the set_priblob_bitfield command" 119 bool "Support the set_priblob_bitfield command"
106 depends on HAS_CAAM && SECURE_BOOT 120 depends on HAS_CAAM && SECURE_BOOT
107 help 121 help
108 This option enables the priblob command which can be used 122 This option enables the priblob command which can be used
109 to set the priblob setting to 0x3. 123 to set the priblob setting to 0x3.
110 124
111 config CMD_HDMIDETECT 125 config CMD_HDMIDETECT
112 bool "Support the 'hdmidet' command" 126 bool "Support the 'hdmidet' command"
113 help 127 help
114 This enables the 'hdmidet' command which detects if an HDMI monitor 128 This enables the 'hdmidet' command which detects if an HDMI monitor
115 is connected. 129 is connected.
116 130
117 config FSL_MFGPROT 131 config FSL_MFGPROT
118 bool "Support the 'mfgprot' command" 132 bool "Support the 'mfgprot' command"
119 depends on SECURE_BOOT && ARCH_MX7 133 depends on SECURE_BOOT && ARCH_MX7
120 help 134 help
121 This option enables the manufacturing protection command 135 This option enables the manufacturing protection command
122 which can be used has a protection feature for Manufacturing 136 which can be used has a protection feature for Manufacturing
123 process. With this tool is possible to authenticate the 137 process. With this tool is possible to authenticate the
124 chip to the OEM's server. 138 chip to the OEM's server.
125 139
126 config DBG_MONITOR 140 config DBG_MONITOR
127 bool "Enable the AXI debug monitor" 141 bool "Enable the AXI debug monitor"
128 depends on ARCH_MX6 || ARCH_MX7 142 depends on ARCH_MX6 || ARCH_MX7
129 help 143 help
130 This option enables the debug monitor which prints out last 144 This option enables the debug monitor which prints out last
131 failed AXI access info when system reboot is caused by AXI 145 failed AXI access info when system reboot is caused by AXI
132 access failure. 146 access failure.
133 147
134 config NXP_BOARD_REVISION 148 config NXP_BOARD_REVISION
135 bool "Read NXP board revision from fuses" 149 bool "Read NXP board revision from fuses"
136 depends on ARCH_MX6 || ARCH_MX7 150 depends on ARCH_MX6 || ARCH_MX7
137 help 151 help
138 NXP boards based on i.MX6/7 contain the board revision information 152 NXP boards based on i.MX6/7 contain the board revision information
139 stored in the fuses. Select this option if you want to be able to 153 stored in the fuses. Select this option if you want to be able to
140 retrieve the board revision information. 154 retrieve the board revision information.
141 155
142 config FLASH_MCUFIRMWARE_SUPPORT 156 config FLASH_MCUFIRMWARE_SUPPORT
143 bool "Enable mcu firmware flash support" 157 bool "Enable mcu firmware flash support"
144 depends on ARCH_MX7ULP || ARCH_IMX8M 158 depends on ARCH_MX7ULP || ARCH_IMX8M
145 help 159 help
146 This enables the mcu firmware flash support for some SOCs. 160 This enables the mcu firmware flash support for some SOCs.
147 161
148 config IMX_TRUSTY_OS 162 config IMX_TRUSTY_OS
149 bool "Support Trusty OS related feature" 163 bool "Support Trusty OS related feature"
150 depends on ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M 164 depends on ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
151 select SYS_ARM_CACHE_WRITEALLOC 165 select SYS_ARM_CACHE_WRITEALLOC
152 166
153 config SYS_ARM_CACHE_WRITEALLOC 167 config SYS_ARM_CACHE_WRITEALLOC
154 bool "support cache write alloc" 168 bool "support cache write alloc"
155 169
arch/arm/mach-imx/imx8/cpu.c
Diff comments   View file @ 57fa56f
1 /* 1 /*
2 * Copyright 2017-2019 NXP 2 * Copyright 2017-2019 NXP
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 * 5 *
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <errno.h> 9 #include <errno.h>
10 #include <asm/io.h> 10 #include <asm/io.h>
11 #include <power-domain.h> 11 #include <power-domain.h>
12 #include <dm/device.h> 12 #include <dm/device.h>
13 #include <dm/uclass-internal.h> 13 #include <dm/uclass-internal.h>
14 #include <asm/mach-imx/sci/sci.h> 14 #include <asm/mach-imx/sci/sci.h>
15 #include <asm/mach-imx/boot_mode.h> 15 #include <asm/mach-imx/boot_mode.h>
16 #include <asm/arch/clock.h> 16 #include <asm/arch/clock.h>
17 #include <thermal.h> 17 #include <thermal.h>
18 #include <asm/armv8/mmu.h> 18 #include <asm/armv8/mmu.h>
19 #include <elf.h> 19 #include <elf.h>
20 #include <asm/arch/sid.h> 20 #include <asm/arch/sid.h>
21 #include <asm/arch-imx/cpu.h> 21 #include <asm/arch-imx/cpu.h>
22 #include <asm/arch/sys_proto.h> 22 #include <asm/arch/sys_proto.h>
23 #include <asm/arch/video_common.h> 23 #include <asm/arch/video_common.h>
24 #include <linux/libfdt.h> 24 #include <linux/libfdt.h>
25 #include <fdt_support.h> 25 #include <fdt_support.h>
26 #include <fdtdec.h> 26 #include <fdtdec.h>
27 #include <asm/arch/cpu.h> 27 #include <asm/arch/cpu.h>
28 #include <generated/version_autogenerated.h> 28 #include <generated/version_autogenerated.h>
29 #include <asm/setup.h> 29 #include <asm/setup.h>
30 #include <asm/arch/lpcg.h> 30 #include <asm/arch/lpcg.h>
31 #include <asm/mach-imx/imx_vservice.h> 31 #include <asm/mach-imx/imx_vservice.h>
32 #include <asm/arch/power-domain.h> 32 #include <asm/arch/power-domain.h>
33 #include <spl.h> 33 #include <spl.h>
34 34
35 DECLARE_GLOBAL_DATA_PTR; 35 DECLARE_GLOBAL_DATA_PTR;
36 36
37 struct edma_ch_map { 37 struct edma_ch_map {
38 sc_rsrc_t ch_start_rsrc; 38 sc_rsrc_t ch_start_rsrc;
39 u32 ch_start_regs; 39 u32 ch_start_regs;
40 u32 ch_num; 40 u32 ch_num;
41 const char* node_path; 41 const char* node_path;
42 }; 42 };
43 43
44 u32 get_cpu_rev(void) 44 u32 get_cpu_rev(void)
45 { 45 {
46 sc_ipc_t ipcHndl; 46 sc_ipc_t ipcHndl;
47 uint32_t id = 0, rev = 0; 47 uint32_t id = 0, rev = 0;
48 sc_err_t err; 48 sc_err_t err;
49 49
50 ipcHndl = gd->arch.ipc_channel_handle; 50 ipcHndl = gd->arch.ipc_channel_handle;
51 51
52 err = sc_misc_get_control(ipcHndl, SC_R_SYSTEM, SC_C_ID, &id); 52 err = sc_misc_get_control(ipcHndl, SC_R_SYSTEM, SC_C_ID, &id);
53 if (err != SC_ERR_NONE) 53 if (err != SC_ERR_NONE)
54 return 0; 54 return 0;
55 55
56 rev = (id >> 5) & 0xf; 56 rev = (id >> 5) & 0xf;
57 id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */ 57 id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
58 58
59 return (id << 12) | rev; 59 return (id << 12) | rev;
60 } 60 }
61 61
62 #ifdef CONFIG_DISPLAY_CPUINFO 62 #ifdef CONFIG_DISPLAY_CPUINFO
63 const char *get_imx8_type(u32 imxtype) 63 const char *get_imx8_type(u32 imxtype)
64 { 64 {
65 switch (imxtype) { 65 switch (imxtype) {
66 case MXC_CPU_IMX8QM: 66 case MXC_CPU_IMX8QM:
67 return "8QM"; /* i.MX8 Quad MAX */ 67 return "8QM"; /* i.MX8 Quad MAX */
68 case MXC_CPU_IMX8QXP: 68 case MXC_CPU_IMX8QXP:
69 return "8QXP"; /* i.MX8 Quad XP */ 69 return "8QXP"; /* i.MX8 Quad XP */
70 case MXC_CPU_IMX8DX: 70 case MXC_CPU_IMX8DX:
71 return "8DX"; /* i.MX8 Dual X */ 71 return "8DX"; /* i.MX8 Dual X */
72 default: 72 default:
73 return "??"; 73 return "??";
74 } 74 }
75 } 75 }
76 76
77 const char *get_imx8_rev(u32 rev) 77 const char *get_imx8_rev(u32 rev)
78 { 78 {
79 switch (rev) { 79 switch (rev) {
80 case CHIP_REV_A: 80 case CHIP_REV_A:
81 return "A"; 81 return "A";
82 case CHIP_REV_B: 82 case CHIP_REV_B:
83 return "B"; 83 return "B";
84 default: 84 default:
85 return "?"; 85 return "?";
86 } 86 }
87 } 87 }
88 88
89 const char *get_core_name(void) 89 const char *get_core_name(void)
90 { 90 {
91 if (is_cortex_a53()) 91 if (is_cortex_a53())
92 return "A53"; 92 return "A53";
93 else if (is_cortex_a35()) 93 else if (is_cortex_a35())
94 return "A35"; 94 return "A35";
95 else if (is_cortex_a72()) 95 else if (is_cortex_a72())
96 return "A72"; 96 return "A72";
97 else 97 else
98 return "?"; 98 return "?";
99 } 99 }
100 100
101 101
102 int print_cpuinfo(void) 102 int print_cpuinfo(void)
103 { 103 {
104 u32 cpurev; 104 u32 cpurev;
105 105
106 cpurev = get_cpu_rev(); 106 cpurev = get_cpu_rev();
107 107
108 printf("CPU: Freescale i.MX%s rev%s %s at %d MHz", 108 printf("CPU: Freescale i.MX%s rev%s %s at %d MHz",
109 get_imx8_type((cpurev & 0xFF000) >> 12), 109 get_imx8_type((cpurev & 0xFF000) >> 12),
110 get_imx8_rev((cpurev & 0xFFF)), 110 get_imx8_rev((cpurev & 0xFFF)),
111 get_core_name(), 111 get_core_name(),
112 mxc_get_clock(MXC_ARM_CLK) / 1000000); 112 mxc_get_clock(MXC_ARM_CLK) / 1000000);
113 113
114 #if defined(CONFIG_IMX_SC_THERMAL) 114 #if defined(CONFIG_IMX_SC_THERMAL)
115 struct udevice *thermal_dev; 115 struct udevice *thermal_dev;
116 int cpu_tmp, ret; 116 int cpu_tmp, ret;
117 117
118 if (is_imx8qm() && is_cortex_a72()) 118 if (is_imx8qm() && is_cortex_a72())
119 ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal1", &thermal_dev); 119 ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal1", &thermal_dev);
120 else 120 else
121 ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0", &thermal_dev); 121 ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0", &thermal_dev);
122 122
123 if (!ret) { 123 if (!ret) {
124 ret = thermal_get_temp(thermal_dev, &cpu_tmp); 124 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
125 125
126 if (!ret) 126 if (!ret)
127 printf(" at %dC", cpu_tmp); 127 printf(" at %dC", cpu_tmp);
128 else 128 else
129 debug(" - invalid sensor data"); 129 debug(" - invalid sensor data");
130 } else { 130 } else {
131 debug(" - invalid sensor device"); 131 debug(" - invalid sensor device");
132 } 132 }
133 #endif 133 #endif
134 134
135 printf("\n"); 135 printf("\n");
136 return 0; 136 return 0;
137 } 137 }
138 #endif 138 #endif
139 139
140 #define BT_PASSOVER_TAG (0x504F) 140 #define BT_PASSOVER_TAG (0x504F)
141 struct pass_over_info_t *get_pass_over_info(void) 141 struct pass_over_info_t *get_pass_over_info(void)
142 { 142 {
143 struct pass_over_info_t *p = (struct pass_over_info_t *)PASS_OVER_INFO_ADDR; 143 struct pass_over_info_t *p = (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
144 144
145 if (p->barker != BT_PASSOVER_TAG || p->len != sizeof(struct pass_over_info_t)) 145 if (p->barker != BT_PASSOVER_TAG || p->len != sizeof(struct pass_over_info_t))
146 return NULL; 146 return NULL;
147 147
148 return p; 148 return p;
149 } 149 }
150 150
151 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_RECOVER_SPL_DATA_SECTION) 151 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_RECOVER_SPL_DATA_SECTION)
152 char __data_save_start[0] __attribute__((section(".__data_save_start"))); 152 char __data_save_start[0] __attribute__((section(".__data_save_start")));
153 char __data_save_end[0] __attribute__((section(".__data_save_end"))); 153 char __data_save_end[0] __attribute__((section(".__data_save_end")));
154 154
155 u32 cold_reboot_flag = 1; 155 u32 cold_reboot_flag = 1;
156 156
157 static void save_restore_data(void) 157 static void save_restore_data(void)
158 { 158 {
159 u32 data_size = __data_save_end - __data_save_start; 159 u32 data_size = __data_save_end - __data_save_start;
160 160
161 if (cold_reboot_flag == 1) { 161 if (cold_reboot_flag == 1) {
162 /* Save data section to data_save section */ 162 /* Save data section to data_save section */
163 memcpy(__data_save_start, __data_save_start - data_size, data_size); 163 memcpy(__data_save_start, __data_save_start - data_size, data_size);
164 } else { 164 } else {
165 /* Restore the data_save section to data section */ 165 /* Restore the data_save section to data section */
166 memcpy(__data_save_start - data_size, __data_save_start, data_size); 166 memcpy(__data_save_start - data_size, __data_save_start, data_size);
167 } 167 }
168 cold_reboot_flag++; 168 cold_reboot_flag++;
169 } 169 }
170 #endif 170 #endif
171 171
172 int arch_cpu_init(void) 172 int arch_cpu_init(void)
173 { 173 {
174 sc_ipc_t ipcHndl = 0; 174 sc_ipc_t ipcHndl = 0;
175 sc_err_t sciErr = 0; 175 sc_err_t sciErr = 0;
176 struct pass_over_info_t *pass_over; 176 struct pass_over_info_t *pass_over;
177 177
178 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_RECOVER_SPL_DATA_SECTION) 178 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_RECOVER_SPL_DATA_SECTION)
179 save_restore_data(); 179 save_restore_data();
180 #endif 180 #endif
181 181
182 gd->arch.ipc_channel_handle = 0; 182 gd->arch.ipc_channel_handle = 0;
183 183
184 /* Open IPC channel */ 184 /* Open IPC channel */
185 sciErr = sc_ipc_open(&ipcHndl, SC_IPC_CH); 185 sciErr = sc_ipc_open(&ipcHndl, SC_IPC_CH);
186 if (sciErr != SC_ERR_NONE) 186 if (sciErr != SC_ERR_NONE)
187 return -EPERM; 187 return -EPERM;
188 188
189 gd->arch.ipc_channel_handle = ipcHndl; 189 gd->arch.ipc_channel_handle = ipcHndl;
190 190
191 /* Dual bootloader feature will require CAAM access, but JR0 and JR1 will be 191 /* Dual bootloader feature will require CAAM access, but JR0 and JR1 will be
192 * assigned to seco for imx8, use JR3 instead. 192 * assigned to seco for imx8, use JR3 instead.
193 */ 193 */
194 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_DUAL_BOOTLOADER) 194 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_DUAL_BOOTLOADER)
195 if (sc_pm_set_resource_power_mode(ipcHndl, 195 if (sc_pm_set_resource_power_mode(ipcHndl,
196 SC_R_CAAM_JR3, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 196 SC_R_CAAM_JR3, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
197 return -EPERM; 197 return -EPERM;
198 if (sc_pm_set_resource_power_mode(ipcHndl, 198 if (sc_pm_set_resource_power_mode(ipcHndl,
199 SC_R_CAAM_JR3_OUT, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 199 SC_R_CAAM_JR3_OUT, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
200 return -EPERM; 200 return -EPERM;
201 #endif 201 #endif
202 202
203 if (IS_ENABLED(CONFIG_XEN)) 203 if (IS_ENABLED(CONFIG_XEN))
204 return 0; 204 return 0;
205 205
206 if (is_soc_rev(CHIP_REV_A)) { 206 if (is_soc_rev(CHIP_REV_A)) {
207 pass_over = get_pass_over_info(); 207 pass_over = get_pass_over_info();
208 if (pass_over && pass_over->g_ap_mu == 0) { 208 if (pass_over && pass_over->g_ap_mu == 0) {
209 /* When ap_mu is 0, means the u-boot is boot from first container */ 209 /* When ap_mu is 0, means the u-boot is boot from first container */
210 sc_misc_boot_status(ipcHndl, SC_MISC_BOOT_STATUS_SUCCESS); 210 sc_misc_boot_status(ipcHndl, SC_MISC_BOOT_STATUS_SUCCESS);
211 } 211 }
212 } 212 }
213 213
214 #ifdef CONFIG_IMX_SMMU 214 #ifdef CONFIG_IMX_SMMU
215 sciErr = sc_pm_set_resource_power_mode(ipcHndl, SC_R_SMMU, 215 sciErr = sc_pm_set_resource_power_mode(ipcHndl, SC_R_SMMU,
216 SC_PM_PW_MODE_ON); 216 SC_PM_PW_MODE_ON);
217 if (sciErr != SC_ERR_NONE) 217 if (sciErr != SC_ERR_NONE)
218 return 0; 218 return 0;
219 #endif 219 #endif
220 220
221 return 0; 221 return 0;
222 } 222 }
223 223
224 u32 cpu_mask(void) 224 u32 cpu_mask(void)
225 { 225 {
226 #ifdef CONFIG_IMX8QM 226 #ifdef CONFIG_IMX8QM
227 return 0x3f; 227 return 0x3f;
228 #else 228 #else
229 return 0xf; /*For IMX8QXP*/ 229 return 0xf; /*For IMX8QXP*/
230 #endif 230 #endif
231 } 231 }
232 232
233 #define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 233 #define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
234 #define CCI400_SNOOP_REQ_EN 0x00000001 234 #define CCI400_SNOOP_REQ_EN 0x00000001
235 #define CHANGE_PENDING_BIT (1 << 0) 235 #define CHANGE_PENDING_BIT (1 << 0)
236 int imx8qm_wake_seconday_cores(void) 236 int imx8qm_wake_seconday_cores(void)
237 { 237 {
238 #ifdef CONFIG_ARMV8_MULTIENTRY 238 #ifdef CONFIG_ARMV8_MULTIENTRY
239 sc_ipc_t ipcHndl; 239 sc_ipc_t ipcHndl;
240 u64 *table = get_spin_tbl_addr(); 240 u64 *table = get_spin_tbl_addr();
241 241
242 /* Clear spin table so that secondary processors 242 /* Clear spin table so that secondary processors
243 * observe the correct value after waking up from wfe. 243 * observe the correct value after waking up from wfe.
244 */ 244 */
245 memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE); 245 memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
246 flush_dcache_range((unsigned long)table, 246 flush_dcache_range((unsigned long)table,
247 (unsigned long)table + 247 (unsigned long)table +
248 (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE)); 248 (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
249 249
250 /* Open IPC channel */ 250 /* Open IPC channel */
251 if (sc_ipc_open(&ipcHndl, SC_IPC_CH) != SC_ERR_NONE) 251 if (sc_ipc_open(&ipcHndl, SC_IPC_CH) != SC_ERR_NONE)
252 return -EIO; 252 return -EIO;
253 253
254 __raw_writel(0xc, 0x52090000); 254 __raw_writel(0xc, 0x52090000);
255 __raw_writel(1, 0x52090008); 255 __raw_writel(1, 0x52090008);
256 256
257 /* IPC to pwr up and boot other cores */ 257 /* IPC to pwr up and boot other cores */
258 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A53_1, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 258 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A53_1, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
259 return -EIO; 259 return -EIO;
260 if (sc_pm_cpu_start(ipcHndl, SC_R_A53_1, true, 0x80000000) != SC_ERR_NONE) 260 if (sc_pm_cpu_start(ipcHndl, SC_R_A53_1, true, 0x80000000) != SC_ERR_NONE)
261 return -EIO; 261 return -EIO;
262 262
263 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A53_2, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 263 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A53_2, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
264 return -EIO; 264 return -EIO;
265 if (sc_pm_cpu_start(ipcHndl, SC_R_A53_2, true, 0x80000000) != SC_ERR_NONE) 265 if (sc_pm_cpu_start(ipcHndl, SC_R_A53_2, true, 0x80000000) != SC_ERR_NONE)
266 return -EIO; 266 return -EIO;
267 267
268 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A53_3, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 268 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A53_3, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
269 return -EIO; 269 return -EIO;
270 if (sc_pm_cpu_start(ipcHndl, SC_R_A53_3, true, 0x80000000) != SC_ERR_NONE) 270 if (sc_pm_cpu_start(ipcHndl, SC_R_A53_3, true, 0x80000000) != SC_ERR_NONE)
271 return -EIO; 271 return -EIO;
272 272
273 /* Enable snoop and dvm msg requests for a53 port on CCI slave interface 3 */ 273 /* Enable snoop and dvm msg requests for a53 port on CCI slave interface 3 */
274 __raw_writel(CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN, 0x52094000); 274 __raw_writel(CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN, 0x52094000);
275 275
276 while (__raw_readl(0x5209000c) & CHANGE_PENDING_BIT) 276 while (__raw_readl(0x5209000c) & CHANGE_PENDING_BIT)
277 ; 277 ;
278 278
279 /* Pwr up cluster 1 and boot core 0*/ 279 /* Pwr up cluster 1 and boot core 0*/
280 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A72, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 280 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A72, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
281 return -EIO; 281 return -EIO;
282 282
283 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A72_0, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 283 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A72_0, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
284 return -EIO; 284 return -EIO;
285 if (sc_pm_cpu_start(ipcHndl, SC_R_A72_0, true, 0x80000000) != SC_ERR_NONE) 285 if (sc_pm_cpu_start(ipcHndl, SC_R_A72_0, true, 0x80000000) != SC_ERR_NONE)
286 return -EIO; 286 return -EIO;
287 287
288 /* IPC to pwr up and boot core 1 */ 288 /* IPC to pwr up and boot core 1 */
289 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A72_1, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 289 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A72_1, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
290 return -EIO; 290 return -EIO;
291 if (sc_pm_cpu_start(ipcHndl, SC_R_A72_1, true, 0x80000000) != SC_ERR_NONE) 291 if (sc_pm_cpu_start(ipcHndl, SC_R_A72_1, true, 0x80000000) != SC_ERR_NONE)
292 return -EIO; 292 return -EIO;
293 293
294 /* Enable snoop and dvm msg requests for a72 port on CCI slave interface 4 */ 294 /* Enable snoop and dvm msg requests for a72 port on CCI slave interface 4 */
295 __raw_writel(CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN, 0x52095000); 295 __raw_writel(CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN, 0x52095000);
296 296
297 while (__raw_readl(0x5209000c) & CHANGE_PENDING_BIT) 297 while (__raw_readl(0x5209000c) & CHANGE_PENDING_BIT)
298 ; 298 ;
299 #endif 299 #endif
300 return 0; 300 return 0;
301 } 301 }
302 302
303 int imx8qxp_wake_secondary_cores(void) 303 int imx8qxp_wake_secondary_cores(void)
304 { 304 {
305 #ifdef CONFIG_ARMV8_MULTIENTRY 305 #ifdef CONFIG_ARMV8_MULTIENTRY
306 sc_ipc_t ipcHndl; 306 sc_ipc_t ipcHndl;
307 u64 *table = get_spin_tbl_addr(); 307 u64 *table = get_spin_tbl_addr();
308 308
309 /* Clear spin table so that secondary processors 309 /* Clear spin table so that secondary processors
310 * observe the correct value after waking up from wfe. 310 * observe the correct value after waking up from wfe.
311 */ 311 */
312 memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE); 312 memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
313 flush_dcache_range((unsigned long)table, 313 flush_dcache_range((unsigned long)table,
314 (unsigned long)table + 314 (unsigned long)table +
315 (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE)); 315 (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
316 316
317 /* Open IPC channel */ 317 /* Open IPC channel */
318 if (sc_ipc_open(&ipcHndl, SC_IPC_CH) != SC_ERR_NONE) 318 if (sc_ipc_open(&ipcHndl, SC_IPC_CH) != SC_ERR_NONE)
319 return -EIO; 319 return -EIO;
320 320
321 /* IPC to pwr up and boot other cores */ 321 /* IPC to pwr up and boot other cores */
322 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A35_1, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 322 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A35_1, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
323 return -EIO; 323 return -EIO;
324 if (sc_pm_cpu_start(ipcHndl, SC_R_A35_1, true, 0x80000000) != SC_ERR_NONE) 324 if (sc_pm_cpu_start(ipcHndl, SC_R_A35_1, true, 0x80000000) != SC_ERR_NONE)
325 return -EIO; 325 return -EIO;
326 326
327 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A35_2, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 327 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A35_2, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
328 return -EIO; 328 return -EIO;
329 if (sc_pm_cpu_start(ipcHndl, SC_R_A35_2, true, 0x80000000) != SC_ERR_NONE) 329 if (sc_pm_cpu_start(ipcHndl, SC_R_A35_2, true, 0x80000000) != SC_ERR_NONE)
330 return -EIO; 330 return -EIO;
331 331
332 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A35_3, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 332 if (sc_pm_set_resource_power_mode(ipcHndl, SC_R_A35_3, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
333 return -EIO; 333 return -EIO;
334 if (sc_pm_cpu_start(ipcHndl, SC_R_A35_3, true, 0x80000000) != SC_ERR_NONE) 334 if (sc_pm_cpu_start(ipcHndl, SC_R_A35_3, true, 0x80000000) != SC_ERR_NONE)
335 return -EIO; 335 return -EIO;
336 336
337 #endif 337 #endif
338 return 0; 338 return 0;
339 } 339 }
340 340
341 #if defined(CONFIG_IMX8QM) 341 #if defined(CONFIG_IMX8QM)
342 #define FUSE_MAC0_WORD0 452 342 #define FUSE_MAC0_WORD0 452
343 #define FUSE_MAC0_WORD1 453 343 #define FUSE_MAC0_WORD1 453
344 #define FUSE_MAC1_WORD0 454 344 #define FUSE_MAC1_WORD0 454
345 #define FUSE_MAC1_WORD1 455 345 #define FUSE_MAC1_WORD1 455
346 #elif defined(CONFIG_IMX8QXP) 346 #elif defined(CONFIG_IMX8QXP)
347 #define FUSE_MAC0_WORD0 708 347 #define FUSE_MAC0_WORD0 708
348 #define FUSE_MAC0_WORD1 709 348 #define FUSE_MAC0_WORD1 709
349 #define FUSE_MAC1_WORD0 710 349 #define FUSE_MAC1_WORD0 710
350 #define FUSE_MAC1_WORD1 711 350 #define FUSE_MAC1_WORD1 711
351 #endif 351 #endif
352 352
353 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) 353 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
354 { 354 {
355 sc_err_t err; 355 sc_err_t err;
356 sc_ipc_t ipc; 356 sc_ipc_t ipc;
357 uint32_t val1 = 0, val2 = 0; 357 uint32_t val1 = 0, val2 = 0;
358 uint32_t word1, word2; 358 uint32_t word1, word2;
359 359
360 ipc = gd->arch.ipc_channel_handle; 360 ipc = gd->arch.ipc_channel_handle;
361 361
362 if (dev_id == 0) { 362 if (dev_id == 0) {
363 word1 = FUSE_MAC0_WORD0; 363 word1 = FUSE_MAC0_WORD0;
364 word2 = FUSE_MAC0_WORD1; 364 word2 = FUSE_MAC0_WORD1;
365 } else { 365 } else {
366 word1 = FUSE_MAC1_WORD0; 366 word1 = FUSE_MAC1_WORD0;
367 word2 = FUSE_MAC1_WORD1; 367 word2 = FUSE_MAC1_WORD1;
368 } 368 }
369 369
370 err = sc_misc_otp_fuse_read(ipc, word1, &val1); 370 err = sc_misc_otp_fuse_read(ipc, word1, &val1);
371 if (err != SC_ERR_NONE) { 371 if (err != SC_ERR_NONE) {
372 printf("%s fuse %d read error: %d\n", __func__, word1, err); 372 printf("%s fuse %d read error: %d\n", __func__, word1, err);
373 return; 373 return;
374 } 374 }
375 375
376 err = sc_misc_otp_fuse_read(ipc, word2, &val2); 376 err = sc_misc_otp_fuse_read(ipc, word2, &val2);
377 if (err != SC_ERR_NONE) { 377 if (err != SC_ERR_NONE) {
378 printf("%s fuse %d read error: %d\n", __func__, word2, err); 378 printf("%s fuse %d read error: %d\n", __func__, word2, err);
379 return; 379 return;
380 } 380 }
381 381
382 mac[0] = val1; 382 mac[0] = val1;
383 mac[1] = val1 >> 8; 383 mac[1] = val1 >> 8;
384 mac[2] = val1 >> 16; 384 mac[2] = val1 >> 16;
385 mac[3] = val1 >> 24; 385 mac[3] = val1 >> 24;
386 mac[4] = val2; 386 mac[4] = val2;
387 mac[5] = val2 >> 8; 387 mac[5] = val2 >> 8;
388 } 388 }
389 389
390 #ifdef CONFIG_IMX_BOOTAUX 390 #ifdef CONFIG_IMX_BOOTAUX
391 391
392 #ifdef CONFIG_IMX8QM 392 #ifdef CONFIG_IMX8QM
393 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) 393 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
394 { 394 {
395 sc_ipc_t ipcHndl; 395 sc_ipc_t ipcHndl;
396 sc_rsrc_t core_rsrc, mu_rsrc; 396 sc_rsrc_t core_rsrc, mu_rsrc;
397 sc_faddr_t tcml_addr; 397 sc_faddr_t tcml_addr;
398 u32 tcml_size = SZ_128K; 398 u32 tcml_size = SZ_128K;
399 ulong addr; 399 ulong addr;
400 400
401 ipcHndl = gd->arch.ipc_channel_handle; 401 ipcHndl = gd->arch.ipc_channel_handle;
402 402
403 switch (core_id) { 403 switch (core_id) {
404 case 0: 404 case 0:
405 core_rsrc = SC_R_M4_0_PID0; 405 core_rsrc = SC_R_M4_0_PID0;
406 tcml_addr = 0x34FE0000; 406 tcml_addr = 0x34FE0000;
407 mu_rsrc = SC_R_M4_0_MU_1A; 407 mu_rsrc = SC_R_M4_0_MU_1A;
408 break; 408 break;
409 case 1: 409 case 1:
410 core_rsrc = SC_R_M4_1_PID0; 410 core_rsrc = SC_R_M4_1_PID0;
411 tcml_addr = 0x38FE0000; 411 tcml_addr = 0x38FE0000;
412 mu_rsrc = SC_R_M4_1_MU_1A; 412 mu_rsrc = SC_R_M4_1_MU_1A;
413 break; 413 break;
414 default: 414 default:
415 printf("Not support this core boot up, ID:%u\n", core_id); 415 printf("Not support this core boot up, ID:%u\n", core_id);
416 return -EINVAL; 416 return -EINVAL;
417 } 417 }
418 418
419 addr = (sc_faddr_t)boot_private_data; 419 addr = (sc_faddr_t)boot_private_data;
420 420
421 if (addr >= tcml_addr && addr <= tcml_addr + tcml_size) { 421 if (addr >= tcml_addr && addr <= tcml_addr + tcml_size) {
422 printf("Wrong image address 0x%lx, should not in TCML\n", 422 printf("Wrong image address 0x%lx, should not in TCML\n",
423 addr); 423 addr);
424 return -EINVAL; 424 return -EINVAL;
425 } 425 }
426 426
427 printf("Power on M4 and MU\n"); 427 printf("Power on M4 and MU\n");
428 428
429 if (sc_pm_set_resource_power_mode(ipcHndl, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 429 if (sc_pm_set_resource_power_mode(ipcHndl, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
430 return -EIO; 430 return -EIO;
431 431
432 if (sc_pm_set_resource_power_mode(ipcHndl, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 432 if (sc_pm_set_resource_power_mode(ipcHndl, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
433 return -EIO; 433 return -EIO;
434 434
435 printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr); 435 printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr);
436 436
437 if (addr != tcml_addr) 437 if (addr != tcml_addr)
438 memcpy((void *)tcml_addr, (void *)addr, tcml_size); 438 memcpy((void *)tcml_addr, (void *)addr, tcml_size);
439 439
440 printf("Start M4 %u\n", core_id); 440 printf("Start M4 %u\n", core_id);
441 if (sc_pm_cpu_start(ipcHndl, core_rsrc, true, tcml_addr) != SC_ERR_NONE) 441 if (sc_pm_cpu_start(ipcHndl, core_rsrc, true, tcml_addr) != SC_ERR_NONE)
442 return -EIO; 442 return -EIO;
443 443
444 printf("bootaux complete\n"); 444 printf("bootaux complete\n");
445 return 0; 445 return 0;
446 } 446 }
447 #endif 447 #endif
448 448
449 #ifdef CONFIG_IMX8QXP 449 #ifdef CONFIG_IMX8QXP
450 static unsigned long load_elf_image_shdr(unsigned long addr) 450 static unsigned long load_elf_image_shdr(unsigned long addr)
451 { 451 {
452 Elf32_Ehdr *ehdr; /* Elf header structure pointer */ 452 Elf32_Ehdr *ehdr; /* Elf header structure pointer */
453 Elf32_Shdr *shdr; /* Section header structure pointer */ 453 Elf32_Shdr *shdr; /* Section header structure pointer */
454 unsigned char *strtab = 0; /* String table pointer */ 454 unsigned char *strtab = 0; /* String table pointer */
455 unsigned char *image; /* Binary image pointer */ 455 unsigned char *image; /* Binary image pointer */
456 int i; /* Loop counter */ 456 int i; /* Loop counter */
457 457
458 ehdr = (Elf32_Ehdr *)addr; 458 ehdr = (Elf32_Ehdr *)addr;
459 459
460 /* Find the section header string table for output info */ 460 /* Find the section header string table for output info */
461 shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff + 461 shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff +
462 (ehdr->e_shstrndx * sizeof(Elf32_Shdr))); 462 (ehdr->e_shstrndx * sizeof(Elf32_Shdr)));
463 463
464 if (shdr->sh_type == SHT_STRTAB) 464 if (shdr->sh_type == SHT_STRTAB)
465 strtab = (unsigned char *)(addr + shdr->sh_offset); 465 strtab = (unsigned char *)(addr + shdr->sh_offset);
466 466
467 /* Load each appropriate section */ 467 /* Load each appropriate section */
468 for (i = 0; i < ehdr->e_shnum; ++i) { 468 for (i = 0; i < ehdr->e_shnum; ++i) {
469 shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff + 469 shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff +
470 (i * sizeof(Elf32_Shdr))); 470 (i * sizeof(Elf32_Shdr)));
471 471
472 if (!(shdr->sh_flags & SHF_ALLOC) || 472 if (!(shdr->sh_flags & SHF_ALLOC) ||
473 shdr->sh_addr == 0 || shdr->sh_size == 0) { 473 shdr->sh_addr == 0 || shdr->sh_size == 0) {
474 continue; 474 continue;
475 } 475 }
476 476
477 if (strtab) { 477 if (strtab) {
478 debug("%sing %s @ 0x%08lx (%ld bytes)\n", 478 debug("%sing %s @ 0x%08lx (%ld bytes)\n",
479 (shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load", 479 (shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load",
480 &strtab[shdr->sh_name], 480 &strtab[shdr->sh_name],
481 (unsigned long)shdr->sh_addr, 481 (unsigned long)shdr->sh_addr,
482 (long)shdr->sh_size); 482 (long)shdr->sh_size);
483 } 483 }
484 484
485 if (shdr->sh_type == SHT_NOBITS) { 485 if (shdr->sh_type == SHT_NOBITS) {
486 memset((void *)(uintptr_t)shdr->sh_addr, 0, 486 memset((void *)(uintptr_t)shdr->sh_addr, 0,
487 shdr->sh_size); 487 shdr->sh_size);
488 } else { 488 } else {
489 image = (unsigned char *)addr + shdr->sh_offset; 489 image = (unsigned char *)addr + shdr->sh_offset;
490 memcpy((void *)(uintptr_t)shdr->sh_addr, 490 memcpy((void *)(uintptr_t)shdr->sh_addr,
491 (const void *)image, shdr->sh_size); 491 (const void *)image, shdr->sh_size);
492 } 492 }
493 flush_cache(shdr->sh_addr, shdr->sh_size); 493 flush_cache(shdr->sh_addr, shdr->sh_size);
494 } 494 }
495 495
496 return ehdr->e_entry; 496 return ehdr->e_entry;
497 } 497 }
498 498
499 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) 499 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
500 { 500 {
501 sc_ipc_t ipcHndl; 501 sc_ipc_t ipcHndl;
502 sc_rsrc_t core_rsrc, mu_rsrc = -1; 502 sc_rsrc_t core_rsrc, mu_rsrc = -1;
503 sc_faddr_t aux_core_ram; 503 sc_faddr_t aux_core_ram;
504 u32 size; 504 u32 size;
505 ulong addr; 505 ulong addr;
506 506
507 ipcHndl = gd->arch.ipc_channel_handle; 507 ipcHndl = gd->arch.ipc_channel_handle;
508 508
509 switch (core_id) { 509 switch (core_id) {
510 case 0: 510 case 0:
511 core_rsrc = SC_R_M4_0_PID0; 511 core_rsrc = SC_R_M4_0_PID0;
512 aux_core_ram = 0x34FE0000; 512 aux_core_ram = 0x34FE0000;
513 mu_rsrc = SC_R_M4_0_MU_1A; 513 mu_rsrc = SC_R_M4_0_MU_1A;
514 size = SZ_128K; 514 size = SZ_128K;
515 break; 515 break;
516 case 1: 516 case 1:
517 core_rsrc = SC_R_DSP; 517 core_rsrc = SC_R_DSP;
518 aux_core_ram = 0x596f8000; 518 aux_core_ram = 0x596f8000;
519 size = SZ_2K; 519 size = SZ_2K;
520 break; 520 break;
521 default: 521 default:
522 printf("Not support this core boot up, ID:%u\n", core_id); 522 printf("Not support this core boot up, ID:%u\n", core_id);
523 return -EINVAL; 523 return -EINVAL;
524 } 524 }
525 525
526 addr = (sc_faddr_t)boot_private_data; 526 addr = (sc_faddr_t)boot_private_data;
527 527
528 if (addr >= aux_core_ram && addr <= aux_core_ram + size) { 528 if (addr >= aux_core_ram && addr <= aux_core_ram + size) {
529 printf("Wrong image address 0x%lx, should not in aux core ram\n", 529 printf("Wrong image address 0x%lx, should not in aux core ram\n",
530 addr); 530 addr);
531 return -EINVAL; 531 return -EINVAL;
532 } 532 }
533 533
534 printf("Power on aux core %d\n", core_id); 534 printf("Power on aux core %d\n", core_id);
535 535
536 if (sc_pm_set_resource_power_mode(ipcHndl, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 536 if (sc_pm_set_resource_power_mode(ipcHndl, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
537 return -EIO; 537 return -EIO;
538 538
539 if (mu_rsrc != -1) { 539 if (mu_rsrc != -1) {
540 if (sc_pm_set_resource_power_mode(ipcHndl, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) 540 if (sc_pm_set_resource_power_mode(ipcHndl, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
541 return -EIO; 541 return -EIO;
542 } 542 }
543 543
544 if (core_id == 1) { 544 if (core_id == 1) {
545 struct power_domain pd; 545 struct power_domain pd;
546 546
547 if (sc_pm_clock_enable(ipcHndl, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) { 547 if (sc_pm_clock_enable(ipcHndl, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) {
548 printf("Error enable clock\n"); 548 printf("Error enable clock\n");
549 return -EIO; 549 return -EIO;
550 } 550 }
551 551
552 LPCG_AllClockOn(AUD_DSP_LPCG); 552 LPCG_AllClockOn(AUD_DSP_LPCG);
553 553
554 if (!power_domain_lookup_name("audio_sai0", &pd)) { 554 if (!power_domain_lookup_name("audio_sai0", &pd)) {
555 if (power_domain_on(&pd)) { 555 if (power_domain_on(&pd)) {
556 printf("Error power on SAI0\n"); 556 printf("Error power on SAI0\n");
557 return -EIO; 557 return -EIO;
558 } 558 }
559 } 559 }
560 560
561 if (!power_domain_lookup_name("audio_ocram", &pd)) { 561 if (!power_domain_lookup_name("audio_ocram", &pd)) {
562 if (power_domain_on(&pd)) { 562 if (power_domain_on(&pd)) {
563 printf("Error power on HIFI RAM\n"); 563 printf("Error power on HIFI RAM\n");
564 return -EIO; 564 return -EIO;
565 } 565 }
566 } 566 }
567 567
568 LPCG_AllClockOn(AUD_OCRAM_LPCG); 568 LPCG_AllClockOn(AUD_OCRAM_LPCG);
569 LPCG_AllClockOn(AUD_SAI_0_LPCG); 569 LPCG_AllClockOn(AUD_SAI_0_LPCG);
570 } 570 }
571 571
572 printf("Copy image from 0x%lx to 0x%lx\n", addr, (ulong)aux_core_ram); 572 printf("Copy image from 0x%lx to 0x%lx\n", addr, (ulong)aux_core_ram);
573 if (core_id == 0) { 573 if (core_id == 0) {
574 /* M4 use bin file */ 574 /* M4 use bin file */
575 memcpy((void *)aux_core_ram, (void *)addr, size); 575 memcpy((void *)aux_core_ram, (void *)addr, size);
576 } else { 576 } else {
577 /* HIFI use elf file */ 577 /* HIFI use elf file */
578 if (!valid_elf_image(addr)) 578 if (!valid_elf_image(addr))
579 return -1; 579 return -1;
580 addr = load_elf_image_shdr(addr); 580 addr = load_elf_image_shdr(addr);
581 } 581 }
582 582
583 printf("Start %s\n", core_id == 0 ? "M4" : "HIFI"); 583 printf("Start %s\n", core_id == 0 ? "M4" : "HIFI");
584 584
585 if (sc_pm_cpu_start(ipcHndl, core_rsrc, true, aux_core_ram) != SC_ERR_NONE) 585 if (sc_pm_cpu_start(ipcHndl, core_rsrc, true, aux_core_ram) != SC_ERR_NONE)
586 return -EIO; 586 return -EIO;
587 587
588 printf("bootaux complete\n"); 588 printf("bootaux complete\n");
589 return 0; 589 return 0;
590 } 590 }
591 #endif 591 #endif
592 592
593 int arch_auxiliary_core_check_up(u32 core_id) 593 int arch_auxiliary_core_check_up(u32 core_id)
594 { 594 {
595 sc_rsrc_t core_rsrc; 595 sc_rsrc_t core_rsrc;
596 sc_pm_power_mode_t power_mode; 596 sc_pm_power_mode_t power_mode;
597 sc_ipc_t ipcHndl; 597 sc_ipc_t ipcHndl;
598 598
599 ipcHndl = gd->arch.ipc_channel_handle; 599 ipcHndl = gd->arch.ipc_channel_handle;
600 600
601 switch (core_id) { 601 switch (core_id) {
602 case 0: 602 case 0:
603 core_rsrc = SC_R_M4_0_PID0; 603 core_rsrc = SC_R_M4_0_PID0;
604 break; 604 break;
605 #ifdef CONFIG_IMX8QM 605 #ifdef CONFIG_IMX8QM
606 case 1: 606 case 1:
607 core_rsrc = SC_R_M4_1_PID0; 607 core_rsrc = SC_R_M4_1_PID0;
608 break; 608 break;
609 #endif 609 #endif
610 default: 610 default:
611 printf("Not support this core, ID:%u\n", core_id); 611 printf("Not support this core, ID:%u\n", core_id);
612 return 0; 612 return 0;
613 } 613 }
614 614
615 if (sc_pm_get_resource_power_mode(ipcHndl, core_rsrc, &power_mode) != SC_ERR_NONE) 615 if (sc_pm_get_resource_power_mode(ipcHndl, core_rsrc, &power_mode) != SC_ERR_NONE)
616 return 0; 616 return 0;
617 617
618 if (power_mode != SC_PM_PW_MODE_OFF) 618 if (power_mode != SC_PM_PW_MODE_OFF)
619 return 1; 619 return 1;
620 620
621 return 0; 621 return 0;
622 } 622 }
623 #endif 623 #endif
624 624
625 static bool check_owned_resource(sc_rsrc_t rsrc_id) 625 static bool check_owned_resource(sc_rsrc_t rsrc_id)
626 { 626 {
627 sc_ipc_t ipcHndl = 0; 627 sc_ipc_t ipcHndl = 0;
628 bool owned; 628 bool owned;
629 629
630 ipcHndl = gd->arch.ipc_channel_handle; 630 ipcHndl = gd->arch.ipc_channel_handle;
631 631
632 owned = sc_rm_is_resource_owned(ipcHndl, rsrc_id); 632 owned = sc_rm_is_resource_owned(ipcHndl, rsrc_id);
633 633
634 return owned; 634 return owned;
635 } 635 }
636 636
637 #ifdef CONFIG_IMX_SMMU 637 #ifdef CONFIG_IMX_SMMU
638 struct smmu_sid dev_sids[] = { 638 struct smmu_sid dev_sids[] = {
639 }; 639 };
640 640
641 sc_err_t imx8_config_smmu_sid(struct smmu_sid *dev_sids, int size) 641 sc_err_t imx8_config_smmu_sid(struct smmu_sid *dev_sids, int size)
642 { 642 {
643 int i; 643 int i;
644 sc_err_t sciErr = SC_ERR_NONE; 644 sc_err_t sciErr = SC_ERR_NONE;
645 645
646 if ((dev_sids == NULL) || (size <= 0)) 646 if ((dev_sids == NULL) || (size <= 0))
647 return SC_ERR_NONE; 647 return SC_ERR_NONE;
648 648
649 for (i = 0; i < size; i++) { 649 for (i = 0; i < size; i++) {
650 if (!check_owned_resource(dev_sids[i].rsrc)) { 650 if (!check_owned_resource(dev_sids[i].rsrc)) {
651 printf("%s rsrc[%d] not owned\n", __func__, dev_sids[i].rsrc); 651 printf("%s rsrc[%d] not owned\n", __func__, dev_sids[i].rsrc);
652 continue; 652 continue;
653 } 653 }
654 sciErr = sc_rm_set_master_sid(gd->arch.ipc_channel_handle, 654 sciErr = sc_rm_set_master_sid(gd->arch.ipc_channel_handle,
655 dev_sids[i].rsrc, 655 dev_sids[i].rsrc,
656 dev_sids[i].sid); 656 dev_sids[i].sid);
657 if (sciErr != SC_ERR_NONE) { 657 if (sciErr != SC_ERR_NONE) {
658 printf("set master sid error\n"); 658 printf("set master sid error\n");
659 return sciErr; 659 return sciErr;
660 } 660 }
661 } 661 }
662 662
663 return SC_ERR_NONE; 663 return SC_ERR_NONE;
664 } 664 }
665 #endif 665 #endif
666 666
667 void arch_preboot_os(void) 667 void arch_preboot_os(void)
668 { 668 {
669 #if defined(CONFIG_VIDEO_IMXDPUV1) 669 #if defined(CONFIG_VIDEO_IMXDPUV1)
670 imxdpuv1_fb_disable(); 670 imxdpuv1_fb_disable();
671 #endif 671 #endif
672 #ifdef CONFIG_IMX_SMMU 672 #ifdef CONFIG_IMX_SMMU
673 imx8_config_smmu_sid(dev_sids, ARRAY_SIZE(dev_sids)); 673 imx8_config_smmu_sid(dev_sids, ARRAY_SIZE(dev_sids));
674 #endif 674 #endif
675 } 675 }
676 676
677 enum boot_device get_boot_device(void) 677 enum boot_device get_boot_device(void)
678 { 678 {
679 enum boot_device boot_dev = SD1_BOOT; 679 enum boot_device boot_dev = SD1_BOOT;
680 680
681 sc_ipc_t ipcHndl = 0; 681 sc_ipc_t ipcHndl = 0;
682 sc_rsrc_t dev_rsrc; 682 sc_rsrc_t dev_rsrc;
683 683
684 /* Note we only support android in EMMC SDHC0 */ 684 /* Note we only support android in EMMC SDHC0 */
685 if (IS_ENABLED(CONFIG_XEN)) 685 if (IS_ENABLED(CONFIG_XEN))
686 return MMC1_BOOT; 686 return MMC1_BOOT;
687 687
688 ipcHndl = gd->arch.ipc_channel_handle; 688 ipcHndl = gd->arch.ipc_channel_handle;
689 sc_misc_get_boot_dev(ipcHndl, &dev_rsrc); 689 sc_misc_get_boot_dev(ipcHndl, &dev_rsrc);
690 690
691 switch (dev_rsrc) { 691 switch (dev_rsrc) {
692 case SC_R_SDHC_0: 692 case SC_R_SDHC_0:
693 boot_dev = MMC1_BOOT; 693 boot_dev = MMC1_BOOT;
694 break; 694 break;
695 case SC_R_SDHC_1: 695 case SC_R_SDHC_1:
696 boot_dev = SD2_BOOT; 696 boot_dev = SD2_BOOT;
697 break; 697 break;
698 case SC_R_SDHC_2: 698 case SC_R_SDHC_2:
699 boot_dev = SD3_BOOT; 699 boot_dev = SD3_BOOT;
700 break; 700 break;
701 case SC_R_NAND: 701 case SC_R_NAND:
702 boot_dev = NAND_BOOT; 702 boot_dev = NAND_BOOT;
703 break; 703 break;
704 case SC_R_FSPI_0: 704 case SC_R_FSPI_0:
705 boot_dev = FLEXSPI_BOOT; 705 boot_dev = FLEXSPI_BOOT;
706 break; 706 break;
707 case SC_R_SATA_0: 707 case SC_R_SATA_0:
708 boot_dev = SATA_BOOT; 708 boot_dev = SATA_BOOT;
709 break; 709 break;
710 case SC_R_USB_0: 710 case SC_R_USB_0:
711 case SC_R_USB_1: 711 case SC_R_USB_1:
712 case SC_R_USB_2: 712 case SC_R_USB_2:
713 boot_dev = USB_BOOT; 713 boot_dev = USB_BOOT;
714 break; 714 break;
715 default: 715 default:
716 break; 716 break;
717 } 717 }
718 718
719 return boot_dev; 719 return boot_dev;
720 } 720 }
721 721
722 bool is_usb_boot(void) 722 bool is_usb_boot(void)
723 { 723 {
724 return get_boot_device() == USB_BOOT; 724 return get_boot_device() == USB_BOOT;
725 } 725 }
726 726
727 #if defined(CONFIG_ARCH_MISC_INIT) 727 #if defined(CONFIG_ARCH_MISC_INIT)
728 #define FSL_SIP_BUILDINFO 0xC2000003 728 #define FSL_SIP_BUILDINFO 0xC2000003
729 #define FSL_SIP_BUILDINFO_GET_COMMITHASH 0x00 729 #define FSL_SIP_BUILDINFO_GET_COMMITHASH 0x00
730 extern uint32_t _end_ofs; 730 extern uint32_t _end_ofs;
731 731
732 static void set_buildinfo_to_env(uint32_t scfw, uint32_t secofw, char *mkimage, char *atf) 732 static void set_buildinfo_to_env(uint32_t scfw, uint32_t secofw, char *mkimage, char *atf)
733 { 733 {
734 if (!mkimage || !atf) 734 if (!mkimage || !atf)
735 return; 735 return;
736 736
737 env_set("commit_mkimage", mkimage); 737 env_set("commit_mkimage", mkimage);
738 env_set("commit_atf", atf); 738 env_set("commit_atf", atf);
739 env_set_hex("commit_scfw", (ulong)scfw); 739 env_set_hex("commit_scfw", (ulong)scfw);
740 env_set_hex("commit_secofw", (ulong)secofw); 740 env_set_hex("commit_secofw", (ulong)secofw);
741 } 741 }
742 742
743 static void acquire_buildinfo(void) 743 static void acquire_buildinfo(void)
744 { 744 {
745 sc_ipc_t ipc; 745 sc_ipc_t ipc;
746 uint32_t sc_build = 0, sc_commit = 0; 746 uint32_t sc_build = 0, sc_commit = 0;
747 uint32_t seco_build = 0, seco_commit = 0; 747 uint32_t seco_build = 0, seco_commit = 0;
748 char *mkimage_commit, *temp; 748 char *mkimage_commit, *temp;
749 uint64_t atf_commit = 0; 749 uint64_t atf_commit = 0;
750 750
751 ipc = gd->arch.ipc_channel_handle; 751 ipc = gd->arch.ipc_channel_handle;
752 752
753 /* Get SCFW build and commit id */ 753 /* Get SCFW build and commit id */
754 sc_misc_build_info(ipc, &sc_build, &sc_commit); 754 sc_misc_build_info(ipc, &sc_build, &sc_commit);
755 if (sc_build == 0) { 755 if (sc_build == 0) {
756 debug("SCFW does not support build info\n"); 756 debug("SCFW does not support build info\n");
757 sc_commit = 0; /* Display 0 when the build info is not supported*/ 757 sc_commit = 0; /* Display 0 when the build info is not supported*/
758 } 758 }
759 759
760 /* Get SECO FW build and commit id */ 760 /* Get SECO FW build and commit id */
761 sc_seco_build_info(ipc, &seco_build, &seco_commit); 761 sc_seco_build_info(ipc, &seco_build, &seco_commit);
762 if (seco_build == 0) { 762 if (seco_build == 0) {
763 debug("SECO FW does not support build info\n"); 763 debug("SECO FW does not support build info\n");
764 seco_commit = 0; /* Display 0 when the build info is not supported*/ 764 seco_commit = 0; /* Display 0 when the build info is not supported*/
765 } 765 }
766 766
767 /* Get imx-mkimage commit id. 767 /* Get imx-mkimage commit id.
768 * The imx-mkimage puts the commit hash behind the end of u-boot.bin 768 * The imx-mkimage puts the commit hash behind the end of u-boot.bin
769 */ 769 */
770 mkimage_commit = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs + fdt_totalsize(gd->fdt_blob)); 770 mkimage_commit = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs + fdt_totalsize(gd->fdt_blob));
771 temp = mkimage_commit + 8; 771 temp = mkimage_commit + 8;
772 *temp = '\0'; 772 *temp = '\0';
773 773
774 if (strlen(mkimage_commit) == 0) { 774 if (strlen(mkimage_commit) == 0) {
775 debug("IMX-MKIMAGE does not support build info\n"); 775 debug("IMX-MKIMAGE does not support build info\n");
776 mkimage_commit = "0"; /* Display 0 */ 776 mkimage_commit = "0"; /* Display 0 */
777 } 777 }
778 778
779 /* Get ARM Trusted Firmware commit id */ 779 /* Get ARM Trusted Firmware commit id */
780 atf_commit = call_imx_sip(FSL_SIP_BUILDINFO, FSL_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0); 780 atf_commit = call_imx_sip(FSL_SIP_BUILDINFO, FSL_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0);
781 if (atf_commit == 0xffffffff) { 781 if (atf_commit == 0xffffffff) {
782 debug("ATF does not support build info\n"); 782 debug("ATF does not support build info\n");
783 atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */ 783 atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
784 } 784 }
785 785
786 /* Set all to env */ 786 /* Set all to env */
787 set_buildinfo_to_env(sc_commit, seco_commit, mkimage_commit, (char *)&atf_commit); 787 set_buildinfo_to_env(sc_commit, seco_commit, mkimage_commit, (char *)&atf_commit);
788 788
789 printf("\n BuildInfo: \n - SCFW %08x, SECO-FW %08x, IMX-MKIMAGE %s, ATF %s\n - %s \n\n", 789 printf("\n BuildInfo: \n - SCFW %08x, SECO-FW %08x, IMX-MKIMAGE %s, ATF %s\n - %s \n\n",
790 sc_commit, seco_commit, mkimage_commit, (char *)&atf_commit, U_BOOT_VERSION); 790 sc_commit, seco_commit, mkimage_commit, (char *)&atf_commit, U_BOOT_VERSION);
791 } 791 }
792 792
793 int arch_misc_init(void) 793 int arch_misc_init(void)
794 { 794 {
795 acquire_buildinfo(); 795 acquire_buildinfo();
796 796
797 return 0; 797 return 0;
798 } 798 }
799 #endif 799 #endif
800 800
801 int print_bootinfo(void) 801 int print_bootinfo(void)
802 { 802 {
803 enum boot_device bt_dev; 803 enum boot_device bt_dev;
804 bt_dev = get_boot_device(); 804 bt_dev = get_boot_device();
805 805
806 puts("Boot: "); 806 puts("Boot: ");
807 switch (bt_dev) { 807 switch (bt_dev) {
808 case SD1_BOOT: 808 case SD1_BOOT:
809 puts("SD0\n"); 809 puts("SD0\n");
810 break; 810 break;
811 case SD2_BOOT: 811 case SD2_BOOT:
812 puts("SD1\n"); 812 puts("SD1\n");
813 break; 813 break;
814 case SD3_BOOT: 814 case SD3_BOOT:
815 puts("SD2\n"); 815 puts("SD2\n");
816 break; 816 break;
817 case MMC1_BOOT: 817 case MMC1_BOOT:
818 puts("MMC0\n"); 818 puts("MMC0\n");
819 break; 819 break;
820 case MMC2_BOOT: 820 case MMC2_BOOT:
821 puts("MMC1\n"); 821 puts("MMC1\n");
822 break; 822 break;
823 case MMC3_BOOT: 823 case MMC3_BOOT:
824 puts("MMC2\n"); 824 puts("MMC2\n");
825 break; 825 break;
826 case FLEXSPI_BOOT: 826 case FLEXSPI_BOOT:
827 puts("FLEXSPI\n"); 827 puts("FLEXSPI\n");
828 break; 828 break;
829 case SATA_BOOT: 829 case SATA_BOOT:
830 puts("SATA\n"); 830 puts("SATA\n");
831 break; 831 break;
832 case NAND_BOOT: 832 case NAND_BOOT:
833 puts("NAND\n"); 833 puts("NAND\n");
834 break; 834 break;
835 case USB_BOOT: 835 case USB_BOOT:
836 puts("USB\n"); 836 puts("USB\n");
837 break; 837 break;
838 default: 838 default:
839 printf("Unknown device %u\n", bt_dev); 839 printf("Unknown device %u\n", bt_dev);
840 break; 840 break;
841 } 841 }
842 842
843 return 0; 843 return 0;
844 } 844 }
845 845
846 #ifdef CONFIG_SERIAL_TAG 846 #ifdef CONFIG_SERIAL_TAG
847 #define FUSE_UNIQUE_ID_WORD0 16 847 #define FUSE_UNIQUE_ID_WORD0 16
848 #define FUSE_UNIQUE_ID_WORD1 17 848 #define FUSE_UNIQUE_ID_WORD1 17
849 void get_board_serial(struct tag_serialnr *serialnr) 849 void get_board_serial(struct tag_serialnr *serialnr)
850 { 850 {
851 sc_err_t err; 851 sc_err_t err;
852 sc_ipc_t ipc; 852 sc_ipc_t ipc;
853 uint32_t val1 = 0, val2 = 0; 853 uint32_t val1 = 0, val2 = 0;
854 uint32_t word1, word2; 854 uint32_t word1, word2;
855 855
856 ipc = gd->arch.ipc_channel_handle; 856 ipc = gd->arch.ipc_channel_handle;
857 857
858 word1 = FUSE_UNIQUE_ID_WORD0; 858 word1 = FUSE_UNIQUE_ID_WORD0;
859 word2 = FUSE_UNIQUE_ID_WORD1; 859 word2 = FUSE_UNIQUE_ID_WORD1;
860 860
861 err = sc_misc_otp_fuse_read(ipc, word1, &val1); 861 err = sc_misc_otp_fuse_read(ipc, word1, &val1);
862 if (err != SC_ERR_NONE) { 862 if (err != SC_ERR_NONE) {
863 printf("%s fuse %d read error: %d\n", __func__,word1, err); 863 printf("%s fuse %d read error: %d\n", __func__,word1, err);
864 return; 864 return;
865 } 865 }
866 866
867 err = sc_misc_otp_fuse_read(ipc, word2, &val2); 867 err = sc_misc_otp_fuse_read(ipc, word2, &val2);
868 if (err != SC_ERR_NONE) { 868 if (err != SC_ERR_NONE) {
869 printf("%s fuse %d read error: %d\n", __func__, word2, err); 869 printf("%s fuse %d read error: %d\n", __func__, word2, err);
870 return; 870 return;
871 } 871 }
872 serialnr->low = val1; 872 serialnr->low = val1;
873 serialnr->high = val2; 873 serialnr->high = val2;
874 } 874 }
875 #endif /*CONFIG_SERIAL_TAG*/ 875 #endif /*CONFIG_SERIAL_TAG*/
876 876
877 __weak int board_mmc_get_env_dev(int devno) 877 __weak int board_mmc_get_env_dev(int devno)
878 { 878 {
879 return CONFIG_SYS_MMC_ENV_DEV; 879 return CONFIG_SYS_MMC_ENV_DEV;
880 } 880 }
881 881
882 int mmc_get_env_dev(void) 882 int mmc_get_env_dev(void)
883 { 883 {
884 sc_ipc_t ipcHndl = 0; 884 sc_ipc_t ipcHndl = 0;
885 sc_rsrc_t dev_rsrc; 885 sc_rsrc_t dev_rsrc;
886 int devno; 886 int devno;
887 887
888 ipcHndl = gd->arch.ipc_channel_handle; 888 ipcHndl = gd->arch.ipc_channel_handle;
889 sc_misc_get_boot_dev(ipcHndl, &dev_rsrc); 889 sc_misc_get_boot_dev(ipcHndl, &dev_rsrc);
890 890
891 switch(dev_rsrc) { 891 switch(dev_rsrc) {
892 case SC_R_SDHC_0: 892 case SC_R_SDHC_0:
893 devno = 0; 893 devno = 0;
894 break; 894 break;
895 case SC_R_SDHC_1: 895 case SC_R_SDHC_1:
896 devno = 1; 896 devno = 1;
897 break; 897 break;
898 case SC_R_SDHC_2: 898 case SC_R_SDHC_2:
899 devno = 2; 899 devno = 2;
900 break; 900 break;
901 default: 901 default:
902 /* If not boot from sd/mmc, use default value */ 902 /* If not boot from sd/mmc, use default value */
903 return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV); 903 return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV);
904 } 904 }
905 905
906 return board_mmc_get_env_dev(devno); 906 return board_mmc_get_env_dev(devno);
907 } 907 }
908 908
909 static bool check_owned_resources_in_pd_tree(void *blob, int nodeoff, 909 static bool check_owned_resources_in_pd_tree(void *blob, int nodeoff,
910 unsigned int *unowned_rsrc) 910 unsigned int *unowned_rsrc)
911 { 911 {
912 unsigned int rsrc_id; 912 unsigned int rsrc_id;
913 const fdt32_t *php; 913 const fdt32_t *php;
914 914
915 /* Search the ancestors nodes in current SS power-domain tree, 915 /* Search the ancestors nodes in current SS power-domain tree,
916 * if all ancestors' resources are owned, we can enable the node, 916 * if all ancestors' resources are owned, we can enable the node,
917 * otherwise any ancestor is not owned, we should disable the node. 917 * otherwise any ancestor is not owned, we should disable the node.
918 */ 918 */
919 919
920 do { 920 do {
921 php = fdt_getprop(blob, nodeoff, "power-domains", NULL); 921 php = fdt_getprop(blob, nodeoff, "power-domains", NULL);
922 if (!php) { 922 if (!php) {
923 debug(" - ignoring no power-domains\n"); 923 debug(" - ignoring no power-domains\n");
924 break; 924 break;
925 } 925 }
926 nodeoff = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*php)); 926 nodeoff = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*php));
927 927
928 rsrc_id = fdtdec_get_uint(blob, nodeoff, "reg", 0); 928 rsrc_id = fdtdec_get_uint(blob, nodeoff, "reg", 0);
929 if (rsrc_id == SC_R_NONE) { 929 if (rsrc_id == SC_R_NONE) {
930 debug("%s's power domain use SC_R_NONE\n", 930 debug("%s's power domain use SC_R_NONE\n",
931 fdt_get_name(blob, nodeoff, NULL)); 931 fdt_get_name(blob, nodeoff, NULL));
932 break; 932 break;
933 } 933 }
934 934
935 debug("power-domains node 0x%x, resource id %u\n", nodeoff, rsrc_id); 935 debug("power-domains node 0x%x, resource id %u\n", nodeoff, rsrc_id);
936 936
937 if (!check_owned_resource(rsrc_id)) { 937 if (!check_owned_resource(rsrc_id)) {
938 if (unowned_rsrc != NULL) 938 if (unowned_rsrc != NULL)
939 *unowned_rsrc = rsrc_id; 939 *unowned_rsrc = rsrc_id;
940 return false; 940 return false;
941 } 941 }
942 } while (fdt_node_check_compatible(blob, nodeoff, "nxp,imx8-pd")); 942 } while (fdt_node_check_compatible(blob, nodeoff, "nxp,imx8-pd"));
943 943
944 return true; 944 return true;
945 } 945 }
946 946
947 static int disable_fdt_node(void *blob, int nodeoffset) 947 static int disable_fdt_node(void *blob, int nodeoffset)
948 { 948 {
949 int rc, ret; 949 int rc, ret;
950 const char *status = "disabled"; 950 const char *status = "disabled";
951 951
952 do { 952 do {
953 rc = fdt_setprop(blob, nodeoffset, "status", status, strlen(status) + 1); 953 rc = fdt_setprop(blob, nodeoffset, "status", status, strlen(status) + 1);
954 if (rc) { 954 if (rc) {
955 if (rc == -FDT_ERR_NOSPACE) { 955 if (rc == -FDT_ERR_NOSPACE) {
956 ret = fdt_increase_size(blob, 512); 956 ret = fdt_increase_size(blob, 512);
957 if (ret) 957 if (ret)
958 return ret; 958 return ret;
959 } 959 }
960 } 960 }
961 } while (rc == -FDT_ERR_NOSPACE); 961 } while (rc == -FDT_ERR_NOSPACE);
962 962
963 return rc; 963 return rc;
964 } 964 }
965 965
966 static void fdt_edma_debug_int_array(u32 *array, int count, u32 stride) 966 static void fdt_edma_debug_int_array(u32 *array, int count, u32 stride)
967 { 967 {
968 #ifdef DEBUG 968 #ifdef DEBUG
969 int i; 969 int i;
970 for (i = 0; i < count; i++) { 970 for (i = 0; i < count; i++) {
971 printf("0x%x ", array[i]); 971 printf("0x%x ", array[i]);
972 if (i % stride == stride - 1) 972 if (i % stride == stride - 1)
973 printf("\n"); 973 printf("\n");
974 } 974 }
975 975
976 printf("\n"); 976 printf("\n");
977 #endif 977 #endif
978 } 978 }
979 979
980 static void fdt_edma_debug_stringlist(const char *stringlist, int length) 980 static void fdt_edma_debug_stringlist(const char *stringlist, int length)
981 { 981 {
982 #ifdef DEBUG 982 #ifdef DEBUG
983 int i = 0, len; 983 int i = 0, len;
984 while (i < length) { 984 while (i < length) {
985 printf("%s\n", stringlist); 985 printf("%s\n", stringlist);
986 986
987 len = strlen(stringlist) + 1; 987 len = strlen(stringlist) + 1;
988 i += len; 988 i += len;
989 stringlist += len; 989 stringlist += len;
990 } 990 }
991 991
992 printf("\n"); 992 printf("\n");
993 #endif 993 #endif
994 } 994 }
995 995
996 static void fdt_edma_swap_int_array(u32 *array, int count) 996 static void fdt_edma_swap_int_array(u32 *array, int count)
997 { 997 {
998 int i; 998 int i;
999 for (i = 0; i < count; i++) { 999 for (i = 0; i < count; i++) {
1000 array[i] = cpu_to_fdt32(array[i]); 1000 array[i] = cpu_to_fdt32(array[i]);
1001 } 1001 }
1002 } 1002 }
1003 1003
1004 static int fdt_edma_update_int_array(u32 *array, int count, u32 *new_array, u32 stride, int *remove_array, int remove_count) 1004 static int fdt_edma_update_int_array(u32 *array, int count, u32 *new_array, u32 stride, int *remove_array, int remove_count)
1005 { 1005 {
1006 int i = 0, j, curr = 0, new_cnt = 0; 1006 int i = 0, j, curr = 0, new_cnt = 0;
1007 1007
1008 do { 1008 do {
1009 if (remove_count && curr == remove_array[i]) { 1009 if (remove_count && curr == remove_array[i]) {
1010 i++; 1010 i++;
1011 remove_count--; 1011 remove_count--;
1012 array += stride; 1012 array += stride;
1013 } else { 1013 } else {
1014 for (j = 0; j< stride; j++) { 1014 for (j = 0; j< stride; j++) {
1015 *new_array = *array; 1015 *new_array = *array;
1016 new_array++; 1016 new_array++;
1017 array++; 1017 array++;
1018 } 1018 }
1019 new_cnt+= j; 1019 new_cnt+= j;
1020 } 1020 }
1021 curr++; 1021 curr++;
1022 } while ((curr * stride) < count); 1022 } while ((curr * stride) < count);
1023 1023
1024 return new_cnt; 1024 return new_cnt;
1025 } 1025 }
1026 1026
1027 static int fdt_edma_update_stringlist(const char *stringlist, int stringlist_count, char *newlist, int *remove_array, int remove_count) 1027 static int fdt_edma_update_stringlist(const char *stringlist, int stringlist_count, char *newlist, int *remove_array, int remove_count)
1028 { 1028 {
1029 int i = 0, curr = 0, new_len = 0; 1029 int i = 0, curr = 0, new_len = 0;
1030 int length; 1030 int length;
1031 1031
1032 debug("fdt_edma_update_stringlist, remove_cnt %d\n", remove_count); 1032 debug("fdt_edma_update_stringlist, remove_cnt %d\n", remove_count);
1033 1033
1034 do { 1034 do {
1035 if (remove_count && curr == remove_array[i]) { 1035 if (remove_count && curr == remove_array[i]) {
1036 debug("remove %s at %d\n", stringlist, remove_array[i]); 1036 debug("remove %s at %d\n", stringlist, remove_array[i]);
1037 1037
1038 length = strlen(stringlist) + 1; 1038 length = strlen(stringlist) + 1;
1039 stringlist += length; 1039 stringlist += length;
1040 i++; 1040 i++;
1041 remove_count--; 1041 remove_count--;
1042 } else { 1042 } else {
1043 length = strlen(stringlist) + 1; 1043 length = strlen(stringlist) + 1;
1044 strcpy(newlist, stringlist); 1044 strcpy(newlist, stringlist);
1045 1045
1046 debug("copy %s, %s, curr %d, len %d\n", newlist, stringlist, curr, length); 1046 debug("copy %s, %s, curr %d, len %d\n", newlist, stringlist, curr, length);
1047 1047
1048 stringlist += length; 1048 stringlist += length;
1049 newlist += length; 1049 newlist += length;
1050 new_len += length; 1050 new_len += length;
1051 } 1051 }
1052 curr++; 1052 curr++;
1053 } while (curr < stringlist_count); 1053 } while (curr < stringlist_count);
1054 1054
1055 return new_len; 1055 return new_len;
1056 } 1056 }
1057 1057
1058 static int fdt_edma_get_channel_id(u32 *regs, int index, struct edma_ch_map *edma) 1058 static int fdt_edma_get_channel_id(u32 *regs, int index, struct edma_ch_map *edma)
1059 { 1059 {
1060 u32 ch_reg = regs[(index << 2) + 1]; 1060 u32 ch_reg = regs[(index << 2) + 1];
1061 u32 ch_reg_size = regs[(index << 2) + 3]; 1061 u32 ch_reg_size = regs[(index << 2) + 3];
1062 int ch_id = (ch_reg - edma->ch_start_regs) / ch_reg_size; 1062 int ch_id = (ch_reg - edma->ch_start_regs) / ch_reg_size;
1063 if (ch_id >= edma->ch_num) 1063 if (ch_id >= edma->ch_num)
1064 return -1; 1064 return -1;
1065 1065
1066 return ch_id; 1066 return ch_id;
1067 } 1067 }
1068 1068
1069 static void update_fdt_edma_nodes(void *blob) 1069 static void update_fdt_edma_nodes(void *blob)
1070 { 1070 {
1071 struct edma_ch_map edma_qm[] = { 1071 struct edma_ch_map edma_qm[] = {
1072 { SC_R_DMA_0_CH0, 0x5a200000, 32, "/dma-controller@5a1f0000"}, 1072 { SC_R_DMA_0_CH0, 0x5a200000, 32, "/dma-controller@5a1f0000"},
1073 { SC_R_DMA_1_CH0, 0x5aa00000, 32, "/dma-controller@5a9f0000"}, 1073 { SC_R_DMA_1_CH0, 0x5aa00000, 32, "/dma-controller@5a9f0000"},
1074 { SC_R_DMA_2_CH0, 0x59200000, 5, "/dma-controller@591F0000"}, 1074 { SC_R_DMA_2_CH0, 0x59200000, 5, "/dma-controller@591F0000"},
1075 { SC_R_DMA_2_CH5, 0x59250000, 27, "/dma-controller@591F0000"}, 1075 { SC_R_DMA_2_CH5, 0x59250000, 27, "/dma-controller@591F0000"},
1076 { SC_R_DMA_3_CH0, 0x59a00000, 32, "/dma-controller@599F0000"}, 1076 { SC_R_DMA_3_CH0, 0x59a00000, 32, "/dma-controller@599F0000"},
1077 }; 1077 };
1078 1078
1079 struct edma_ch_map edma_qxp[] = { 1079 struct edma_ch_map edma_qxp[] = {
1080 { SC_R_DMA_0_CH0, 0x59200000, 32, "/dma-controller@591F0000"}, 1080 { SC_R_DMA_0_CH0, 0x59200000, 32, "/dma-controller@591F0000"},
1081 { SC_R_DMA_1_CH0, 0x59a00000, 32, "/dma-controller@599F0000"}, 1081 { SC_R_DMA_1_CH0, 0x59a00000, 32, "/dma-controller@599F0000"},
1082 { SC_R_DMA_2_CH0, 0x5a200000, 5, "/dma-controller@5a1f0000"}, 1082 { SC_R_DMA_2_CH0, 0x5a200000, 5, "/dma-controller@5a1f0000"},
1083 { SC_R_DMA_2_CH5, 0x5a250000, 27, "/dma-controller@5a1f0000"}, 1083 { SC_R_DMA_2_CH5, 0x5a250000, 27, "/dma-controller@5a1f0000"},
1084 { SC_R_DMA_3_CH0, 0x5aa00000, 32, "/dma-controller@5a9f0000"}, 1084 { SC_R_DMA_3_CH0, 0x5aa00000, 32, "/dma-controller@5a9f0000"},
1085 }; 1085 };
1086 1086
1087 u32 i, j, edma_size; 1087 u32 i, j, edma_size;
1088 int nodeoff, ret; 1088 int nodeoff, ret;
1089 struct edma_ch_map *edma_array; 1089 struct edma_ch_map *edma_array;
1090 1090
1091 if (is_imx8qm()) { 1091 if (is_imx8qm()) {
1092 edma_array = edma_qm; 1092 edma_array = edma_qm;
1093 edma_size = ARRAY_SIZE(edma_qm); 1093 edma_size = ARRAY_SIZE(edma_qm);
1094 } else { 1094 } else {
1095 edma_array = edma_qxp; 1095 edma_array = edma_qxp;
1096 edma_size = ARRAY_SIZE(edma_qxp); 1096 edma_size = ARRAY_SIZE(edma_qxp);
1097 } 1097 }
1098 1098
1099 for (i = 0; i < edma_size; i++, edma_array++) { 1099 for (i = 0; i < edma_size; i++, edma_array++) {
1100 u32 regs[128]; 1100 u32 regs[128];
1101 u32 interrupts[96]; 1101 u32 interrupts[96];
1102 u32 dma_channels; 1102 u32 dma_channels;
1103 int regs_count, interrupts_count, int_names_count; 1103 int regs_count, interrupts_count, int_names_count;
1104 1104
1105 const char *list; 1105 const char *list;
1106 int list_len, newlist_len; 1106 int list_len, newlist_len;
1107 int remove[32]; 1107 int remove[32];
1108 int remove_cnt = 0; 1108 int remove_cnt = 0;
1109 char * newlist; 1109 char * newlist;
1110 1110
1111 nodeoff = fdt_path_offset(blob, edma_array->node_path); 1111 nodeoff = fdt_path_offset(blob, edma_array->node_path);
1112 if (nodeoff < 0) 1112 if (nodeoff < 0)
1113 continue; /* Not found, skip it */ 1113 continue; /* Not found, skip it */
1114 1114
1115 printf("%s, %d\n", edma_array->node_path, nodeoff); 1115 printf("%s, %d\n", edma_array->node_path, nodeoff);
1116 1116
1117 regs_count = fdtdec_get_int_array_count(blob, nodeoff, "reg", regs, 128); 1117 regs_count = fdtdec_get_int_array_count(blob, nodeoff, "reg", regs, 128);
1118 debug("regs_count %d\n", regs_count); 1118 debug("regs_count %d\n", regs_count);
1119 if (regs_count < 0) 1119 if (regs_count < 0)
1120 continue; 1120 continue;
1121 1121
1122 interrupts_count = fdtdec_get_int_array_count(blob, nodeoff, "interrupts", interrupts, 96); 1122 interrupts_count = fdtdec_get_int_array_count(blob, nodeoff, "interrupts", interrupts, 96);
1123 debug("interrupts_count %d\n", interrupts_count); 1123 debug("interrupts_count %d\n", interrupts_count);
1124 if (interrupts_count < 0) 1124 if (interrupts_count < 0)
1125 continue; 1125 continue;
1126 1126
1127 dma_channels = fdtdec_get_uint(blob, nodeoff, "dma-channels", 0); 1127 dma_channels = fdtdec_get_uint(blob, nodeoff, "dma-channels", 0);
1128 if (dma_channels == 0) 1128 if (dma_channels == 0)
1129 continue; 1129 continue;
1130 1130
1131 list = fdt_getprop(blob, nodeoff, "interrupt-names", &list_len); 1131 list = fdt_getprop(blob, nodeoff, "interrupt-names", &list_len);
1132 if (!list) 1132 if (!list)
1133 continue; 1133 continue;
1134 1134
1135 int_names_count = fdt_stringlist_count(blob, nodeoff, "interrupt-names"); 1135 int_names_count = fdt_stringlist_count(blob, nodeoff, "interrupt-names");
1136 1136
1137 fdt_edma_debug_int_array(regs, regs_count, 4); 1137 fdt_edma_debug_int_array(regs, regs_count, 4);
1138 fdt_edma_debug_int_array(interrupts, interrupts_count, 3); 1138 fdt_edma_debug_int_array(interrupts, interrupts_count, 3);
1139 fdt_edma_debug_stringlist(list, list_len); 1139 fdt_edma_debug_stringlist(list, list_len);
1140 1140
1141 for (j = 0; j < (regs_count >> 2); j++) { 1141 for (j = 0; j < (regs_count >> 2); j++) {
1142 int ch_id = fdt_edma_get_channel_id(regs, j, edma_array); 1142 int ch_id = fdt_edma_get_channel_id(regs, j, edma_array);
1143 if (ch_id < 0) 1143 if (ch_id < 0)
1144 continue; 1144 continue;
1145 1145
1146 if (!check_owned_resource(edma_array->ch_start_rsrc + ch_id)) { 1146 if (!check_owned_resource(edma_array->ch_start_rsrc + ch_id)) {
1147 printf("remove edma items %d\n", j); 1147 printf("remove edma items %d\n", j);
1148 1148
1149 dma_channels--; 1149 dma_channels--;
1150 1150
1151 remove[remove_cnt] = j; 1151 remove[remove_cnt] = j;
1152 remove_cnt++; 1152 remove_cnt++;
1153 } 1153 }
1154 } 1154 }
1155 1155
1156 if (remove_cnt > 0) { 1156 if (remove_cnt > 0) {
1157 u32 new_regs[128]; 1157 u32 new_regs[128];
1158 u32 new_interrupts[96]; 1158 u32 new_interrupts[96];
1159 1159
1160 regs_count = fdt_edma_update_int_array(regs, regs_count, new_regs, 4, remove, remove_cnt); 1160 regs_count = fdt_edma_update_int_array(regs, regs_count, new_regs, 4, remove, remove_cnt);
1161 interrupts_count = fdt_edma_update_int_array(interrupts, interrupts_count, new_interrupts, 3, remove, remove_cnt); 1161 interrupts_count = fdt_edma_update_int_array(interrupts, interrupts_count, new_interrupts, 3, remove, remove_cnt);
1162 1162
1163 fdt_edma_debug_int_array(new_regs, regs_count, 4); 1163 fdt_edma_debug_int_array(new_regs, regs_count, 4);
1164 fdt_edma_debug_int_array(new_interrupts, interrupts_count, 3); 1164 fdt_edma_debug_int_array(new_interrupts, interrupts_count, 3);
1165 1165
1166 fdt_edma_swap_int_array(new_regs, regs_count); 1166 fdt_edma_swap_int_array(new_regs, regs_count);
1167 fdt_edma_swap_int_array(new_interrupts, interrupts_count); 1167 fdt_edma_swap_int_array(new_interrupts, interrupts_count);
1168 1168
1169 /* malloc a new string list */ 1169 /* malloc a new string list */
1170 newlist = (char *)malloc(list_len); 1170 newlist = (char *)malloc(list_len);
1171 if (!newlist) { 1171 if (!newlist) {
1172 printf("malloc new string list failed, len=%d\n", list_len); 1172 printf("malloc new string list failed, len=%d\n", list_len);
1173 continue; 1173 continue;
1174 } 1174 }
1175 1175
1176 newlist_len = fdt_edma_update_stringlist(list, int_names_count, newlist, remove, remove_cnt); 1176 newlist_len = fdt_edma_update_stringlist(list, int_names_count, newlist, remove, remove_cnt);
1177 fdt_edma_debug_stringlist(newlist, newlist_len); 1177 fdt_edma_debug_stringlist(newlist, newlist_len);
1178 1178
1179 ret = fdt_setprop(blob, nodeoff, "reg", new_regs, regs_count * sizeof(u32)); 1179 ret = fdt_setprop(blob, nodeoff, "reg", new_regs, regs_count * sizeof(u32));
1180 if (ret) 1180 if (ret)
1181 printf("fdt_setprop regs error %d\n", ret); 1181 printf("fdt_setprop regs error %d\n", ret);
1182 1182
1183 ret = fdt_setprop(blob, nodeoff, "interrupts", new_interrupts, interrupts_count * sizeof(u32)); 1183 ret = fdt_setprop(blob, nodeoff, "interrupts", new_interrupts, interrupts_count * sizeof(u32));
1184 if (ret) 1184 if (ret)
1185 printf("fdt_setprop interrupts error %d\n", ret); 1185 printf("fdt_setprop interrupts error %d\n", ret);
1186 1186
1187 ret = fdt_setprop_u32(blob, nodeoff, "dma-channels", dma_channels); 1187 ret = fdt_setprop_u32(blob, nodeoff, "dma-channels", dma_channels);
1188 if (ret) 1188 if (ret)
1189 printf("fdt_setprop_u32 dma-channels error %d\n", ret); 1189 printf("fdt_setprop_u32 dma-channels error %d\n", ret);
1190 1190
1191 ret = fdt_setprop(blob, nodeoff, "interrupt-names", newlist, newlist_len); 1191 ret = fdt_setprop(blob, nodeoff, "interrupt-names", newlist, newlist_len);
1192 if (ret) 1192 if (ret)
1193 printf("fdt_setprop interrupt-names error %d\n", ret); 1193 printf("fdt_setprop interrupt-names error %d\n", ret);
1194 1194
1195 free(newlist); 1195 free(newlist);
1196 } 1196 }
1197 } 1197 }
1198 } 1198 }
1199 1199
1200 static void update_fdt_with_owned_resources(void *blob) 1200 static void update_fdt_with_owned_resources(void *blob)
1201 { 1201 {
1202 /* Traverses the fdt nodes, 1202 /* Traverses the fdt nodes,
1203 * check its power domain and use the resource id in the power domain 1203 * check its power domain and use the resource id in the power domain
1204 * for checking whether it is owned by current partition 1204 * for checking whether it is owned by current partition
1205 */ 1205 */
1206 1206
1207 int offset = 0, next_off; 1207 int offset = 0, next_off;
1208 int depth = 0, next_depth; 1208 int depth = 0, next_depth;
1209 unsigned int rsrc_id; 1209 unsigned int rsrc_id;
1210 int rc; 1210 int rc;
1211 1211
1212 for (offset = fdt_next_node(blob, offset, &depth); offset > 0; 1212 for (offset = fdt_next_node(blob, offset, &depth); offset > 0;
1213 offset = fdt_next_node(blob, offset, &depth)) { 1213 offset = fdt_next_node(blob, offset, &depth)) {
1214 1214
1215 debug("Node name: %s, depth %d\n", fdt_get_name(blob, offset, NULL), depth); 1215 debug("Node name: %s, depth %d\n", fdt_get_name(blob, offset, NULL), depth);
1216 1216
1217 if (!fdtdec_get_is_enabled(blob, offset)) { 1217 if (!fdtdec_get_is_enabled(blob, offset)) {
1218 debug(" - ignoring disabled device\n"); 1218 debug(" - ignoring disabled device\n");
1219 continue; 1219 continue;
1220 } 1220 }
1221 1221
1222 if (!fdt_node_check_compatible(blob, offset, "nxp,imx8-pd")) { 1222 if (!fdt_node_check_compatible(blob, offset, "nxp,imx8-pd")) {
1223 /* Skip to next depth=1 node*/ 1223 /* Skip to next depth=1 node*/
1224 next_off = offset; 1224 next_off = offset;
1225 next_depth = depth; 1225 next_depth = depth;
1226 do { 1226 do {
1227 offset = next_off; 1227 offset = next_off;
1228 depth = next_depth; 1228 depth = next_depth;
1229 next_off = fdt_next_node(blob, offset, &next_depth); 1229 next_off = fdt_next_node(blob, offset, &next_depth);
1230 if (next_off < 0 || next_depth < 1) 1230 if (next_off < 0 || next_depth < 1)
1231 break; 1231 break;
1232 1232
1233 debug("PD name: %s, offset %d, depth %d\n", 1233 debug("PD name: %s, offset %d, depth %d\n",
1234 fdt_get_name(blob, next_off, NULL), next_off, next_depth); 1234 fdt_get_name(blob, next_off, NULL), next_off, next_depth);
1235 } while (next_depth > 1); 1235 } while (next_depth > 1);
1236 1236
1237 continue; 1237 continue;
1238 } 1238 }
1239 1239
1240 if (!check_owned_resources_in_pd_tree(blob, offset, &rsrc_id)) { 1240 if (!check_owned_resources_in_pd_tree(blob, offset, &rsrc_id)) {
1241 /* If the resource is not owned, disable it in FDT */ 1241 /* If the resource is not owned, disable it in FDT */
1242 rc = disable_fdt_node(blob, offset); 1242 rc = disable_fdt_node(blob, offset);
1243 if (!rc) 1243 if (!rc)
1244 printf("Disable %s, resource id %u not owned\n", 1244 printf("Disable %s, resource id %u not owned\n",
1245 fdt_get_name(blob, offset, NULL), rsrc_id); 1245 fdt_get_name(blob, offset, NULL), rsrc_id);
1246 else 1246 else
1247 printf("Unable to disable %s, err=%s\n", 1247 printf("Unable to disable %s, err=%s\n",
1248 fdt_get_name(blob, offset, NULL), fdt_strerror(rc)); 1248 fdt_get_name(blob, offset, NULL), fdt_strerror(rc));
1249 } 1249 }
1250 1250
1251 } 1251 }
1252 } 1252 }
1253 1253
1254 #ifdef CONFIG_IMX_SMMU 1254 #ifdef CONFIG_IMX_SMMU
1255 static int get_srsc_from_fdt_node_power_domain(void *blob, int device_offset) 1255 static int get_srsc_from_fdt_node_power_domain(void *blob, int device_offset)
1256 { 1256 {
1257 const fdt32_t *prop; 1257 const fdt32_t *prop;
1258 int pdnode_offset; 1258 int pdnode_offset;
1259 1259
1260 prop = fdt_getprop(blob, device_offset, "power-domains", NULL); 1260 prop = fdt_getprop(blob, device_offset, "power-domains", NULL);
1261 if (!prop) { 1261 if (!prop) {
1262 debug("node %s has no power-domains\n", 1262 debug("node %s has no power-domains\n",
1263 fdt_get_name(blob, device_offset, NULL)); 1263 fdt_get_name(blob, device_offset, NULL));
1264 return -ENOENT; 1264 return -ENOENT;
1265 } 1265 }
1266 1266
1267 pdnode_offset = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*prop)); 1267 pdnode_offset = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*prop));
1268 if (pdnode_offset < 0) { 1268 if (pdnode_offset < 0) {
1269 pr_err("failed to fetch node %s power-domain", 1269 pr_err("failed to fetch node %s power-domain",
1270 fdt_get_name(blob, device_offset, NULL)); 1270 fdt_get_name(blob, device_offset, NULL));
1271 return pdnode_offset; 1271 return pdnode_offset;
1272 } 1272 }
1273 1273
1274 return fdtdec_get_uint(blob, pdnode_offset, "reg", -ENOENT); 1274 return fdtdec_get_uint(blob, pdnode_offset, "reg", -ENOENT);
1275 } 1275 }
1276 1276
1277 static int config_smmu_resource_sid(int rsrc, int sid) 1277 static int config_smmu_resource_sid(int rsrc, int sid)
1278 { 1278 {
1279 sc_err_t err; 1279 sc_err_t err;
1280 1280
1281 if (!check_owned_resource(rsrc)) { 1281 if (!check_owned_resource(rsrc)) {
1282 printf("%s rsrc[%d] not owned\n", __func__, rsrc); 1282 printf("%s rsrc[%d] not owned\n", __func__, rsrc);
1283 return -1; 1283 return -1;
1284 } 1284 }
1285 err = sc_rm_set_master_sid(gd->arch.ipc_channel_handle, rsrc, sid); 1285 err = sc_rm_set_master_sid(gd->arch.ipc_channel_handle, rsrc, sid);
1286 debug("set_master_sid rsrc=%d sid=0x%x err=%d\n", rsrc, sid, err); 1286 debug("set_master_sid rsrc=%d sid=0x%x err=%d\n", rsrc, sid, err);
1287 if (err != SC_ERR_NONE) { 1287 if (err != SC_ERR_NONE) {
1288 pr_err("fail set_master_sid rsrc=%d sid=0x%x err=%d\n", rsrc, sid, err); 1288 pr_err("fail set_master_sid rsrc=%d sid=0x%x err=%d\n", rsrc, sid, err);
1289 return -EINVAL; 1289 return -EINVAL;
1290 } 1290 }
1291 1291
1292 return 0; 1292 return 0;
1293 } 1293 }
1294 1294
1295 static int config_smmu_fdt_device_sid(void *blob, int device_offset, int sid) 1295 static int config_smmu_fdt_device_sid(void *blob, int device_offset, int sid)
1296 { 1296 {
1297 int rsrc; 1297 int rsrc;
1298 int proplen; 1298 int proplen;
1299 const fdt32_t *prop; 1299 const fdt32_t *prop;
1300 const char *name = fdt_get_name(blob, device_offset, NULL); 1300 const char *name = fdt_get_name(blob, device_offset, NULL);
1301 1301
1302 prop = fdt_getprop(blob, device_offset, "fsl,sc_rsrc_id", &proplen); 1302 prop = fdt_getprop(blob, device_offset, "fsl,sc_rsrc_id", &proplen);
1303 if (prop) { 1303 if (prop) {
1304 int i; 1304 int i;
1305 1305
1306 debug("configure node %s sid 0x%x for %d resources\n", 1306 debug("configure node %s sid 0x%x for %d resources\n",
1307 name, sid, (int)(proplen / sizeof(fdt32_t))); 1307 name, sid, (int)(proplen / sizeof(fdt32_t)));
1308 for (i = 0; i < proplen / sizeof(fdt32_t); ++i) { 1308 for (i = 0; i < proplen / sizeof(fdt32_t); ++i) {
1309 config_smmu_resource_sid(fdt32_to_cpu(prop[i]), sid); 1309 config_smmu_resource_sid(fdt32_to_cpu(prop[i]), sid);
1310 } 1310 }
1311 1311
1312 return 0; 1312 return 0;
1313 } 1313 }
1314 1314
1315 rsrc = get_srsc_from_fdt_node_power_domain(blob, device_offset); 1315 rsrc = get_srsc_from_fdt_node_power_domain(blob, device_offset);
1316 debug("configure node %s sid 0x%x rsrc=%d\n", name, sid, rsrc); 1316 debug("configure node %s sid 0x%x rsrc=%d\n", name, sid, rsrc);
1317 if (rsrc < 0) { 1317 if (rsrc < 0) {
1318 debug("failed to determine SC_R_* for node %s\n", name); 1318 debug("failed to determine SC_R_* for node %s\n", name);
1319 return rsrc; 1319 return rsrc;
1320 } 1320 }
1321 1321
1322 return config_smmu_resource_sid(rsrc, sid); 1322 return config_smmu_resource_sid(rsrc, sid);
1323 } 1323 }
1324 1324
1325 /* assign master sid based on iommu properties in fdt */ 1325 /* assign master sid based on iommu properties in fdt */
1326 static int config_smmu_fdt(void *blob) 1326 static int config_smmu_fdt(void *blob)
1327 { 1327 {
1328 int offset, proplen, i; 1328 int offset, proplen, i;
1329 const fdt32_t *prop; 1329 const fdt32_t *prop;
1330 const char *name; 1330 const char *name;
1331 1331
1332 /* Legacy smmu bindings, still used by xen. */ 1332 /* Legacy smmu bindings, still used by xen. */
1333 offset = fdt_node_offset_by_compatible(blob, 0, "arm,mmu-500"); 1333 offset = fdt_node_offset_by_compatible(blob, 0, "arm,mmu-500");
1334 if (offset > 0 && (prop = fdt_getprop(blob, offset, "mmu-masters", &proplen))) 1334 if (offset > 0 && (prop = fdt_getprop(blob, offset, "mmu-masters", &proplen)))
1335 { 1335 {
1336 debug("found legacy mmu-masters property\n"); 1336 debug("found legacy mmu-masters property\n");
1337 1337
1338 for (i = 0; i < proplen / 8; ++i) { 1338 for (i = 0; i < proplen / 8; ++i) {
1339 uint32_t phandle = fdt32_to_cpu(prop[2 * i]); 1339 uint32_t phandle = fdt32_to_cpu(prop[2 * i]);
1340 int sid = fdt32_to_cpu(prop[2 * i + 1]); 1340 int sid = fdt32_to_cpu(prop[2 * i + 1]);
1341 int device_offset; 1341 int device_offset;
1342 1342
1343 device_offset = fdt_node_offset_by_phandle(blob, phandle); 1343 device_offset = fdt_node_offset_by_phandle(blob, phandle);
1344 if (device_offset < 0) { 1344 if (device_offset < 0) {
1345 pr_err("Failed to fetch device reference from mmu_masters: %d", device_offset); 1345 pr_err("Failed to fetch device reference from mmu_masters: %d", device_offset);
1346 continue; 1346 continue;
1347 } 1347 }
1348 config_smmu_fdt_device_sid(blob, device_offset, sid); 1348 config_smmu_fdt_device_sid(blob, device_offset, sid);
1349 } 1349 }
1350 1350
1351 /* Ignore new bindings if old bindings found, just like linux. */ 1351 /* Ignore new bindings if old bindings found, just like linux. */
1352 return 0; 1352 return 0;
1353 } 1353 }
1354 1354
1355 /* Generic smmu bindings */ 1355 /* Generic smmu bindings */
1356 offset = 0; 1356 offset = 0;
1357 while ((offset = fdt_next_node(blob, offset, NULL)) > 0) 1357 while ((offset = fdt_next_node(blob, offset, NULL)) > 0)
1358 { 1358 {
1359 name = fdt_get_name(blob, offset, NULL); 1359 name = fdt_get_name(blob, offset, NULL);
1360 prop = fdt_getprop(blob, offset, "iommus", &proplen); 1360 prop = fdt_getprop(blob, offset, "iommus", &proplen);
1361 if (!prop) 1361 if (!prop)
1362 continue; 1362 continue;
1363 debug("node %s iommus proplen %d\n", name, proplen); 1363 debug("node %s iommus proplen %d\n", name, proplen);
1364 1364
1365 if (proplen == 12) { 1365 if (proplen == 12) {
1366 int sid = fdt32_to_cpu(prop[1]); 1366 int sid = fdt32_to_cpu(prop[1]);
1367 config_smmu_fdt_device_sid(blob, offset, sid); 1367 config_smmu_fdt_device_sid(blob, offset, sid);
1368 } else if (proplen != 4) { 1368 } else if (proplen != 4) {
1369 debug("node %s ignore unexpected iommus proplen=%d\n", name, proplen); 1369 debug("node %s ignore unexpected iommus proplen=%d\n", name, proplen);
1370 } 1370 }
1371 } 1371 }
1372 1372
1373 return 0; 1373 return 0;
1374 } 1374 }
1375 #endif 1375 #endif
1376 1376
1377 #ifdef CONFIG_OF_SYSTEM_SETUP 1377 #ifdef CONFIG_OF_SYSTEM_SETUP
1378 static int ft_add_optee_node(void *fdt, bd_t *bd) 1378 static int ft_add_optee_node(void *fdt, bd_t *bd)
1379 { 1379 {
1380 const char *path, *subpath; 1380 const char *path, *subpath;
1381 int offs; 1381 int offs;
1382 1382
1383 /* 1383 /*
1384 * No TEE space allocated indicating no TEE running, so no 1384 * No TEE space allocated indicating no TEE running, so no
1385 * need to add optee node in dts 1385 * need to add optee node in dts
1386 */ 1386 */
1387 if (!rom_pointer[1]) 1387 if (!rom_pointer[1])
1388 return 0; 1388 return 0;
1389 1389
1390 offs = fdt_increase_size(fdt, 512); 1390 offs = fdt_increase_size(fdt, 512);
1391 if (offs) { 1391 if (offs) {
1392 printf("No Space for dtb\n"); 1392 printf("No Space for dtb\n");
1393 return 1; 1393 return 1;
1394 } 1394 }
1395 1395
1396 path = "/firmware"; 1396 path = "/firmware";
1397 offs = fdt_path_offset(fdt, path); 1397 offs = fdt_path_offset(fdt, path);
1398 if (offs < 0) { 1398 if (offs < 0) {
1399 path = "/"; 1399 path = "/";
1400 offs = fdt_path_offset(fdt, path); 1400 offs = fdt_path_offset(fdt, path);
1401 1401
1402 if (offs < 0) { 1402 if (offs < 0) {
1403 printf("Could not find root node.\n"); 1403 printf("Could not find root node.\n");
1404 return 1; 1404 return 1;
1405 } 1405 }
1406 1406
1407 subpath = "firmware"; 1407 subpath = "firmware";
1408 offs = fdt_add_subnode(fdt, offs, subpath); 1408 offs = fdt_add_subnode(fdt, offs, subpath);
1409 if (offs < 0) { 1409 if (offs < 0) {
1410 printf("Could not create %s node.\n", subpath); 1410 printf("Could not create %s node.\n", subpath);
1411 } 1411 }
1412 } 1412 }
1413 1413
1414 subpath = "optee"; 1414 subpath = "optee";
1415 offs = fdt_add_subnode(fdt, offs, subpath); 1415 offs = fdt_add_subnode(fdt, offs, subpath);
1416 if (offs < 0) { 1416 if (offs < 0) {
1417 printf("Could not create %s node.\n", subpath); 1417 printf("Could not create %s node.\n", subpath);
1418 } 1418 }
1419 1419
1420 fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz"); 1420 fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz");
1421 fdt_setprop_string(fdt, offs, "method", "smc"); 1421 fdt_setprop_string(fdt, offs, "method", "smc");
1422 1422
1423 return 0; 1423 return 0;
1424 } 1424 }
1425 1425
1426 int ft_system_setup(void *blob, bd_t *bd) 1426 int ft_system_setup(void *blob, bd_t *bd)
1427 { 1427 {
1428 #ifdef BOOTAUX_RESERVED_MEM_BASE 1428 #if (CONFIG_BOOTAUX_RESERVED_MEM_SIZE != 0x00)
1429 int off; 1429 int off;
1430 off = fdt_add_mem_rsv(blob, BOOTAUX_RESERVED_MEM_BASE, 1430 off = fdt_add_mem_rsv(blob, CONFIG_BOOTAUX_RESERVED_MEM_BASE,
1431 BOOTAUX_RESERVED_MEM_SIZE); 1431 CONFIG_BOOTAUX_RESERVED_MEM_SIZE);
1432 if (off < 0) 1432 if (off < 0)
1433 printf("Failed to reserve memory for bootaux: %s\n", 1433 printf("Failed to reserve memory for bootaux: %s\n",
1434 fdt_strerror(off)); 1434 fdt_strerror(off));
1435 #endif 1435 #endif
1436 1436
1437 #ifndef CONFIG_SKIP_RESOURCE_CHECING 1437 #ifndef CONFIG_SKIP_RESOURCE_CHECING
1438 update_fdt_with_owned_resources(blob); 1438 update_fdt_with_owned_resources(blob);
1439 #endif 1439 #endif
1440 1440
1441 update_fdt_edma_nodes(blob); 1441 update_fdt_edma_nodes(blob);
1442 #ifdef CONFIG_IMX_SMMU 1442 #ifdef CONFIG_IMX_SMMU
1443 config_smmu_fdt(blob); 1443 config_smmu_fdt(blob);
1444 #endif 1444 #endif
1445 1445
1446 ft_add_optee_node(blob, bd); 1446 ft_add_optee_node(blob, bd);
1447 return 0; 1447 return 0;
1448 } 1448 }
1449 #endif 1449 #endif
1450 1450
1451 #define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */ 1451 #define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */
1452 1452
1453 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start, sc_faddr_t *addr_end) 1453 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start, sc_faddr_t *addr_end)
1454 { 1454 {
1455 sc_ipc_t ipcHndl = 0; 1455 sc_ipc_t ipcHndl = 0;
1456 sc_err_t sciErr = 0; 1456 sc_err_t sciErr = 0;
1457 bool owned; 1457 bool owned;
1458 sc_faddr_t start, end; 1458 sc_faddr_t start, end;
1459 1459
1460 ipcHndl = gd->arch.ipc_channel_handle; 1460 ipcHndl = gd->arch.ipc_channel_handle;
1461 1461
1462 if (ipcHndl) { 1462 if (ipcHndl) {
1463 owned = sc_rm_is_memreg_owned(ipcHndl, mr); 1463 owned = sc_rm_is_memreg_owned(ipcHndl, mr);
1464 if (owned) { 1464 if (owned) {
1465 sciErr = sc_rm_get_memreg_info(ipcHndl, mr, &start, &end); 1465 sciErr = sc_rm_get_memreg_info(ipcHndl, mr, &start, &end);
1466 if (sciErr) { 1466 if (sciErr) {
1467 printf("Memreg get info failed, %d\n", sciErr); 1467 printf("Memreg get info failed, %d\n", sciErr);
1468 return -EINVAL; 1468 return -EINVAL;
1469 } else { 1469 } else {
1470 debug("0x%llx -- 0x%llx\n", start, end); 1470 debug("0x%llx -- 0x%llx\n", start, end);
1471 1471
1472 *addr_start = start; 1472 *addr_start = start;
1473 *addr_end = end; 1473 *addr_end = end;
1474 1474
1475 return 0; 1475 return 0;
1476 } 1476 }
1477 } 1477 }
1478 } 1478 }
1479 1479
1480 return -EINVAL; 1480 return -EINVAL;
1481 } 1481 }
1482 1482
1483 phys_size_t get_effective_memsize(void) 1483 phys_size_t get_effective_memsize(void)
1484 { 1484 {
1485 sc_rm_mr_t mr; 1485 sc_rm_mr_t mr;
1486 sc_faddr_t start, end, start_aligned; 1486 sc_faddr_t start, end, start_aligned;
1487 int err; 1487 int err;
1488 1488
1489 if (IS_ENABLED(CONFIG_XEN)) 1489 if (IS_ENABLED(CONFIG_XEN))
1490 return PHYS_SDRAM_1_SIZE; 1490 return PHYS_SDRAM_1_SIZE;
1491 1491
1492 for (mr = 0; mr < 64; mr++) { 1492 for (mr = 0; mr < 64; mr++) {
1493 err = get_owned_memreg(mr, &start, &end); 1493 err = get_owned_memreg(mr, &start, &end);
1494 if (!err) { 1494 if (!err) {
1495 start_aligned = roundup(start, MEMSTART_ALIGNMENT); 1495 start_aligned = roundup(start, MEMSTART_ALIGNMENT);
1496 if (start_aligned > end) /* Too small memory region, not use it */ 1496 if (start_aligned > end) /* Too small memory region, not use it */
1497 continue; 1497 continue;
1498 1498
1499 /* Find the memory region runs the u-boot */ 1499 /* Find the memory region runs the u-boot */
1500 if (start >= PHYS_SDRAM_1 && start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) 1500 if (start >= PHYS_SDRAM_1 && start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
1501 && (start <= CONFIG_SYS_TEXT_BASE && CONFIG_SYS_TEXT_BASE <= end)){ 1501 && (start <= CONFIG_SYS_TEXT_BASE && CONFIG_SYS_TEXT_BASE <= end)){
1502 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) 1502 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
1503 return (end - PHYS_SDRAM_1 + 1); 1503 return (end - PHYS_SDRAM_1 + 1);
1504 else 1504 else
1505 return PHYS_SDRAM_1_SIZE; 1505 return PHYS_SDRAM_1_SIZE;
1506 } 1506 }
1507 } 1507 }
1508 } 1508 }
1509 1509
1510 return PHYS_SDRAM_1_SIZE; 1510 return PHYS_SDRAM_1_SIZE;
1511 } 1511 }
1512 1512
1513 int dram_init(void) 1513 int dram_init(void)
1514 { 1514 {
1515 sc_rm_mr_t mr; 1515 sc_rm_mr_t mr;
1516 sc_faddr_t start, end; 1516 sc_faddr_t start, end;
1517 int err; 1517 int err;
1518 1518
1519 if (IS_ENABLED(CONFIG_XEN)) { 1519 if (IS_ENABLED(CONFIG_XEN)) {
1520 gd->ram_size = PHYS_SDRAM_1_SIZE; 1520 gd->ram_size = PHYS_SDRAM_1_SIZE;
1521 gd->ram_size += PHYS_SDRAM_2_SIZE; 1521 gd->ram_size += PHYS_SDRAM_2_SIZE;
1522 1522
1523 return 0; 1523 return 0;
1524 } 1524 }
1525 1525
1526 for (mr = 0; mr < 64; mr++) { 1526 for (mr = 0; mr < 64; mr++) {
1527 err = get_owned_memreg(mr, &start, &end); 1527 err = get_owned_memreg(mr, &start, &end);
1528 if (!err) { 1528 if (!err) {
1529 start = roundup(start, MEMSTART_ALIGNMENT); 1529 start = roundup(start, MEMSTART_ALIGNMENT);
1530 if (start > end) /* Too small memory region, not use it */ 1530 if (start > end) /* Too small memory region, not use it */
1531 continue; 1531 continue;
1532 1532
1533 if (start >= PHYS_SDRAM_1 && start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) { 1533 if (start >= PHYS_SDRAM_1 && start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) {
1534 1534
1535 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) 1535 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
1536 gd->ram_size += end - start + 1; 1536 gd->ram_size += end - start + 1;
1537 else 1537 else
1538 gd->ram_size += ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) - start; 1538 gd->ram_size += ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) - start;
1539 1539
1540 } else if (start >= PHYS_SDRAM_2 && start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)) { 1540 } else if (start >= PHYS_SDRAM_2 && start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)) {
1541 1541
1542 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)) 1542 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE))
1543 gd->ram_size += end - start + 1; 1543 gd->ram_size += end - start + 1;
1544 else 1544 else
1545 gd->ram_size += ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE) - start; 1545 gd->ram_size += ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE) - start;
1546 } 1546 }
1547 } 1547 }
1548 } 1548 }
1549 1549
1550 /* If error, set to the default value */ 1550 /* If error, set to the default value */
1551 if (!gd->ram_size) { 1551 if (!gd->ram_size) {
1552 gd->ram_size = PHYS_SDRAM_1_SIZE; 1552 gd->ram_size = PHYS_SDRAM_1_SIZE;
1553 gd->ram_size += PHYS_SDRAM_2_SIZE; 1553 gd->ram_size += PHYS_SDRAM_2_SIZE;
1554 } 1554 }
1555 return 0; 1555 return 0;
1556 } 1556 }
1557 1557
1558 static void dram_bank_sort(int current_bank) 1558 static void dram_bank_sort(int current_bank)
1559 { 1559 {
1560 phys_addr_t start; 1560 phys_addr_t start;
1561 phys_size_t size; 1561 phys_size_t size;
1562 while (current_bank > 0) { 1562 while (current_bank > 0) {
1563 if (gd->bd->bi_dram[current_bank - 1].start > gd->bd->bi_dram[current_bank].start) { 1563 if (gd->bd->bi_dram[current_bank - 1].start > gd->bd->bi_dram[current_bank].start) {
1564 start = gd->bd->bi_dram[current_bank - 1].start; 1564 start = gd->bd->bi_dram[current_bank - 1].start;
1565 size = gd->bd->bi_dram[current_bank - 1].size; 1565 size = gd->bd->bi_dram[current_bank - 1].size;
1566 1566
1567 gd->bd->bi_dram[current_bank - 1].start = gd->bd->bi_dram[current_bank].start; 1567 gd->bd->bi_dram[current_bank - 1].start = gd->bd->bi_dram[current_bank].start;
1568 gd->bd->bi_dram[current_bank - 1].size = gd->bd->bi_dram[current_bank].size; 1568 gd->bd->bi_dram[current_bank - 1].size = gd->bd->bi_dram[current_bank].size;
1569 1569
1570 gd->bd->bi_dram[current_bank].start = start; 1570 gd->bd->bi_dram[current_bank].start = start;
1571 gd->bd->bi_dram[current_bank].size = size; 1571 gd->bd->bi_dram[current_bank].size = size;
1572 } 1572 }
1573 1573
1574 current_bank--; 1574 current_bank--;
1575 } 1575 }
1576 } 1576 }
1577 1577
1578 int dram_init_banksize(void) 1578 int dram_init_banksize(void)
1579 { 1579 {
1580 sc_rm_mr_t mr; 1580 sc_rm_mr_t mr;
1581 sc_faddr_t start, end; 1581 sc_faddr_t start, end;
1582 int i = 0; 1582 int i = 0;
1583 int err; 1583 int err;
1584 1584
1585 if (IS_ENABLED(CONFIG_XEN)) { 1585 if (IS_ENABLED(CONFIG_XEN)) {
1586 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 1586 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
1587 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 1587 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
1588 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 1588 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
1589 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 1589 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
1590 1590
1591 return 0; 1591 return 0;
1592 } 1592 }
1593 1593
1594 for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) { 1594 for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
1595 err = get_owned_memreg(mr, &start, &end); 1595 err = get_owned_memreg(mr, &start, &end);
1596 if (!err) { 1596 if (!err) {
1597 start = roundup(start, MEMSTART_ALIGNMENT); 1597 start = roundup(start, MEMSTART_ALIGNMENT);
1598 if (start > end) /* Too small memory region, not use it */ 1598 if (start > end) /* Too small memory region, not use it */
1599 continue; 1599 continue;
1600 1600
1601 if (start >= PHYS_SDRAM_1 && start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) { 1601 if (start >= PHYS_SDRAM_1 && start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) {
1602 gd->bd->bi_dram[i].start = start; 1602 gd->bd->bi_dram[i].start = start;
1603 1603
1604 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) 1604 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
1605 gd->bd->bi_dram[i].size = end - start + 1; 1605 gd->bd->bi_dram[i].size = end - start + 1;
1606 else 1606 else
1607 gd->bd->bi_dram[i].size = ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) - start; 1607 gd->bd->bi_dram[i].size = ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) - start;
1608 1608
1609 dram_bank_sort(i); 1609 dram_bank_sort(i);
1610 i++; 1610 i++;
1611 } else if (start >= PHYS_SDRAM_2 && start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)) { 1611 } else if (start >= PHYS_SDRAM_2 && start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)) {
1612 gd->bd->bi_dram[i].start = start; 1612 gd->bd->bi_dram[i].start = start;
1613 1613
1614 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)) 1614 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE))
1615 gd->bd->bi_dram[i].size = end - start + 1; 1615 gd->bd->bi_dram[i].size = end - start + 1;
1616 else 1616 else
1617 gd->bd->bi_dram[i].size = ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE) - start; 1617 gd->bd->bi_dram[i].size = ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE) - start;
1618 1618
1619 dram_bank_sort(i); 1619 dram_bank_sort(i);
1620 i++; 1620 i++;
1621 } 1621 }
1622 1622
1623 } 1623 }
1624 } 1624 }
1625 1625
1626 /* If error, set to the default value */ 1626 /* If error, set to the default value */
1627 if (!i) { 1627 if (!i) {
1628 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 1628 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
1629 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 1629 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
1630 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 1630 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
1631 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 1631 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
1632 } 1632 }
1633 1633
1634 return 0; 1634 return 0;
1635 } 1635 }
1636 1636
1637 static u64 get_block_attrs(sc_faddr_t addr_start) 1637 static u64 get_block_attrs(sc_faddr_t addr_start)
1638 { 1638 {
1639 if ((addr_start >= PHYS_SDRAM_1 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) 1639 if ((addr_start >= PHYS_SDRAM_1 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
1640 || (addr_start >= PHYS_SDRAM_2 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE))) 1640 || (addr_start >= PHYS_SDRAM_2 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
1641 #ifdef CONFIG_IMX_TRUSTY_OS 1641 #ifdef CONFIG_IMX_TRUSTY_OS
1642 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE); 1642 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE);
1643 #else 1643 #else
1644 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE); 1644 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
1645 #endif 1645 #endif
1646 1646
1647 return (PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN); 1647 return (PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN);
1648 } 1648 }
1649 1649
1650 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end) 1650 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
1651 { 1651 {
1652 if (addr_start >= PHYS_SDRAM_1 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) { 1652 if (addr_start >= PHYS_SDRAM_1 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) {
1653 if ((addr_end + 1) > ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) 1653 if ((addr_end + 1) > ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
1654 return ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) - addr_start; 1654 return ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) - addr_start;
1655 1655
1656 } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)) { 1656 } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)) {
1657 1657
1658 if ((addr_end + 1) > ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)) 1658 if ((addr_end + 1) > ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE))
1659 return ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE) - addr_start; 1659 return ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE) - addr_start;
1660 } 1660 }
1661 1661
1662 return (addr_end - addr_start + 1); 1662 return (addr_end - addr_start + 1);
1663 } 1663 }
1664 1664
1665 #define MAX_PTE_ENTRIES 512 1665 #define MAX_PTE_ENTRIES 512
1666 #define MAX_MEM_MAP_REGIONS 16 1666 #define MAX_MEM_MAP_REGIONS 16
1667 1667
1668 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS]; 1668 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
1669 struct mm_region *mem_map = imx8_mem_map; 1669 struct mm_region *mem_map = imx8_mem_map;
1670 1670
1671 void enable_caches(void) 1671 void enable_caches(void)
1672 { 1672 {
1673 sc_rm_mr_t mr; 1673 sc_rm_mr_t mr;
1674 sc_faddr_t start, end; 1674 sc_faddr_t start, end;
1675 int err, i; 1675 int err, i;
1676 1676
1677 if (IS_ENABLED(CONFIG_XEN)) { 1677 if (IS_ENABLED(CONFIG_XEN)) {
1678 imx8_mem_map[0].virt = 0x00000000UL; 1678 imx8_mem_map[0].virt = 0x00000000UL;
1679 imx8_mem_map[0].phys = 0x00000000UL; 1679 imx8_mem_map[0].phys = 0x00000000UL;
1680 imx8_mem_map[0].size = 0x39000000UL; 1680 imx8_mem_map[0].size = 0x39000000UL;
1681 imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 1681 imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
1682 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; 1682 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
1683 imx8_mem_map[1].virt = 0x39000000UL; 1683 imx8_mem_map[1].virt = 0x39000000UL;
1684 imx8_mem_map[1].phys = 0x39000000UL; 1684 imx8_mem_map[1].phys = 0x39000000UL;
1685 imx8_mem_map[1].size = 0x01000000UL; 1685 imx8_mem_map[1].size = 0x01000000UL;
1686 imx8_mem_map[1].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE); 1686 imx8_mem_map[1].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE);
1687 1687
1688 imx8_mem_map[2].virt = 0x40000000UL; 1688 imx8_mem_map[2].virt = 0x40000000UL;
1689 imx8_mem_map[2].phys = 0x40000000UL; 1689 imx8_mem_map[2].phys = 0x40000000UL;
1690 imx8_mem_map[2].size = 0x40000000UL; 1690 imx8_mem_map[2].size = 0x40000000UL;
1691 imx8_mem_map[2].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 1691 imx8_mem_map[2].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
1692 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; 1692 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
1693 1693
1694 imx8_mem_map[3].virt = 0x80000000UL; 1694 imx8_mem_map[3].virt = 0x80000000UL;
1695 imx8_mem_map[3].phys = 0x80000000UL; 1695 imx8_mem_map[3].phys = 0x80000000UL;
1696 imx8_mem_map[3].size = 0x80000000UL; 1696 imx8_mem_map[3].size = 0x80000000UL;
1697 imx8_mem_map[3].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE); 1697 imx8_mem_map[3].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE);
1698 1698
1699 imx8_mem_map[4].virt = 0x100000000UL; 1699 imx8_mem_map[4].virt = 0x100000000UL;
1700 imx8_mem_map[4].phys = 0x100000000UL; 1700 imx8_mem_map[4].phys = 0x100000000UL;
1701 imx8_mem_map[4].size = 0x100000000UL; 1701 imx8_mem_map[4].size = 0x100000000UL;
1702 imx8_mem_map[4].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 1702 imx8_mem_map[4].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
1703 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; 1703 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
1704 1704
1705 icache_enable(); 1705 icache_enable();
1706 dcache_enable(); 1706 dcache_enable();
1707 1707
1708 return; 1708 return;
1709 } 1709 }
1710 1710
1711 /* Create map for registers access from 0x1c000000 to 0x80000000*/ 1711 /* Create map for registers access from 0x1c000000 to 0x80000000*/
1712 imx8_mem_map[0].virt = 0x1c000000UL; 1712 imx8_mem_map[0].virt = 0x1c000000UL;
1713 imx8_mem_map[0].phys = 0x1c000000UL; 1713 imx8_mem_map[0].phys = 0x1c000000UL;
1714 imx8_mem_map[0].size = 0x64000000UL; 1714 imx8_mem_map[0].size = 0x64000000UL;
1715 imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 1715 imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
1716 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; 1716 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
1717 1717
1718 i = 1; 1718 i = 1;
1719 1719
1720 #ifdef CONFIG_IMX_VSERVICE_SHARED_BUFFER 1720 #ifdef CONFIG_IMX_VSERVICE_SHARED_BUFFER
1721 imx8_mem_map[i].virt = CONFIG_IMX_VSERVICE_SHARED_BUFFER; 1721 imx8_mem_map[i].virt = CONFIG_IMX_VSERVICE_SHARED_BUFFER;
1722 imx8_mem_map[i].phys = CONFIG_IMX_VSERVICE_SHARED_BUFFER; 1722 imx8_mem_map[i].phys = CONFIG_IMX_VSERVICE_SHARED_BUFFER;
1723 imx8_mem_map[i].size = CONFIG_IMX_VSERVICE_SHARED_BUFFER_SIZE; 1723 imx8_mem_map[i].size = CONFIG_IMX_VSERVICE_SHARED_BUFFER_SIZE;
1724 imx8_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 1724 imx8_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
1725 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; 1725 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
1726 i++; 1726 i++;
1727 #endif 1727 #endif
1728 1728
1729 for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) { 1729 for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
1730 err = get_owned_memreg(mr, &start, &end); 1730 err = get_owned_memreg(mr, &start, &end);
1731 if (!err) { 1731 if (!err) {
1732 imx8_mem_map[i].virt = start; 1732 imx8_mem_map[i].virt = start;
1733 imx8_mem_map[i].phys = start; 1733 imx8_mem_map[i].phys = start;
1734 imx8_mem_map[i].size = get_block_size(start, end); 1734 imx8_mem_map[i].size = get_block_size(start, end);
1735 imx8_mem_map[i].attrs = get_block_attrs(start); 1735 imx8_mem_map[i].attrs = get_block_attrs(start);
1736 i++; 1736 i++;
1737 } 1737 }
1738 } 1738 }
1739 1739
1740 if (i < MAX_MEM_MAP_REGIONS) { 1740 if (i < MAX_MEM_MAP_REGIONS) {
1741 imx8_mem_map[i].size = 0; 1741 imx8_mem_map[i].size = 0;
1742 imx8_mem_map[i].attrs = 0; 1742 imx8_mem_map[i].attrs = 0;
1743 } else { 1743 } else {
1744 printf("Error, need more MEM MAP REGIONS reserved\n"); 1744 printf("Error, need more MEM MAP REGIONS reserved\n");
1745 icache_enable(); 1745 icache_enable();
1746 return; 1746 return;
1747 } 1747 }
1748 1748
1749 for (i = 0;i < MAX_MEM_MAP_REGIONS;i++) { 1749 for (i = 0;i < MAX_MEM_MAP_REGIONS;i++) {
1750 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n", i, 1750 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n", i,
1751 imx8_mem_map[i].virt, imx8_mem_map[i].phys, imx8_mem_map[i].size, imx8_mem_map[i].attrs); 1751 imx8_mem_map[i].virt, imx8_mem_map[i].phys, imx8_mem_map[i].size, imx8_mem_map[i].attrs);
1752 } 1752 }
1753 1753
1754 icache_enable(); 1754 icache_enable();
1755 dcache_enable(); 1755 dcache_enable();
1756 } 1756 }
1757 1757
1758 #ifndef CONFIG_SYS_DCACHE_OFF 1758 #ifndef CONFIG_SYS_DCACHE_OFF
1759 u64 get_page_table_size(void) 1759 u64 get_page_table_size(void)
1760 { 1760 {
1761 u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64); 1761 u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
1762 u64 size = 0; 1762 u64 size = 0;
1763 1763
1764 /* For each memory region, the max table size: 2 level 3 tables + 2 level 2 tables + 1 level 1 table*/ 1764 /* For each memory region, the max table size: 2 level 3 tables + 2 level 2 tables + 1 level 1 table*/
1765 size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt; 1765 size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
1766 1766
1767 /* 1767 /*
1768 * We need to duplicate our page table once to have an emergency pt to 1768 * We need to duplicate our page table once to have an emergency pt to
1769 * resort to when splitting page tables later on 1769 * resort to when splitting page tables later on
1770 */ 1770 */
1771 size *= 2; 1771 size *= 2;
1772 1772
1773 /* 1773 /*
1774 * We may need to split page tables later on if dcache settings change, 1774 * We may need to split page tables later on if dcache settings change,
1775 * so reserve up to 4 (random pick) page tables for that. 1775 * so reserve up to 4 (random pick) page tables for that.
1776 */ 1776 */
1777 size += one_pt * 4; 1777 size += one_pt * 4;
1778 1778
1779 return size; 1779 return size;
1780 } 1780 }
1781 #endif 1781 #endif
1782 1782
1783 static bool check_device_power_off(struct udevice *dev, 1783 static bool check_device_power_off(struct udevice *dev,
1784 const char* permanent_on_devices[], int size) 1784 const char* permanent_on_devices[], int size)
1785 { 1785 {
1786 int i; 1786 int i;
1787 1787
1788 for (i = 0; i < size; i++) { 1788 for (i = 0; i < size; i++) {
1789 if (!strcmp(dev->name, permanent_on_devices[i])) 1789 if (!strcmp(dev->name, permanent_on_devices[i]))
1790 return false; 1790 return false;
1791 } 1791 }
1792 1792
1793 return true; 1793 return true;
1794 } 1794 }
1795 1795
1796 void power_off_pd_devices(const char* permanent_on_devices[], int size) 1796 void power_off_pd_devices(const char* permanent_on_devices[], int size)
1797 { 1797 {
1798 struct udevice *dev; 1798 struct udevice *dev;
1799 struct power_domain pd; 1799 struct power_domain pd;
1800 1800
1801 for (uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev); dev; 1801 for (uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev); dev;
1802 uclass_find_next_device(&dev)) { 1802 uclass_find_next_device(&dev)) {
1803 1803
1804 if (device_active(dev)) { 1804 if (device_active(dev)) {
1805 /* Power off active pd devices except the permanent power on devices */ 1805 /* Power off active pd devices except the permanent power on devices */
1806 if (check_device_power_off(dev, permanent_on_devices, size)) { 1806 if (check_device_power_off(dev, permanent_on_devices, size)) {
1807 pd.dev = dev; 1807 pd.dev = dev;
1808 power_domain_off(&pd); 1808 power_domain_off(&pd);
1809 } 1809 }
1810 } 1810 }
1811 } 1811 }
1812 } 1812 }
1813 1813
1814 void disconnect_from_pc(void) 1814 void disconnect_from_pc(void)
1815 { 1815 {
1816 int ret; 1816 int ret;
1817 struct power_domain pd; 1817 struct power_domain pd;
1818 1818
1819 if (!power_domain_lookup_name("conn_usb0", &pd)) { 1819 if (!power_domain_lookup_name("conn_usb0", &pd)) {
1820 ret = power_domain_on(&pd); 1820 ret = power_domain_on(&pd);
1821 if (ret) { 1821 if (ret) {
1822 printf("conn_usb0 Power up failed! (error = %d)\n", ret); 1822 printf("conn_usb0 Power up failed! (error = %d)\n", ret);
1823 return; 1823 return;
1824 } 1824 }
1825 1825
1826 writel(0x0, USB_BASE_ADDR + 0x140); 1826 writel(0x0, USB_BASE_ADDR + 0x140);
1827 1827
1828 ret = power_domain_off(&pd); 1828 ret = power_domain_off(&pd);
1829 if (ret) { 1829 if (ret) {
1830 printf("conn_usb0 Power off failed! (error = %d)\n", ret); 1830 printf("conn_usb0 Power off failed! (error = %d)\n", ret);
1831 return; 1831 return;
1832 } 1832 }
1833 } else { 1833 } else {
1834 printf("conn_usb0 finding failed!\n"); 1834 printf("conn_usb0 finding failed!\n");
1835 return; 1835 return;
1836 } 1836 }
1837 } 1837 }
1838 1838
1839 bool check_owned_udevice(struct udevice *dev) 1839 bool check_owned_udevice(struct udevice *dev)
1840 { 1840 {
1841 int ret; 1841 int ret;
1842 sc_rsrc_t resource_id; 1842 sc_rsrc_t resource_id;
1843 struct ofnode_phandle_args args; 1843 struct ofnode_phandle_args args;
1844 1844
1845 /* Get the resource id from its power-domain */ 1845 /* Get the resource id from its power-domain */
1846 ret = dev_read_phandle_with_args(dev, "power-domains", 1846 ret = dev_read_phandle_with_args(dev, "power-domains",
1847 "#power-domain-cells", 0, 0, &args); 1847 "#power-domain-cells", 0, 0, &args);
1848 if (ret) { 1848 if (ret) {
1849 printf("no power-domains found\n"); 1849 printf("no power-domains found\n");
1850 return false; 1850 return false;
1851 } 1851 }
1852 1852
1853 /* Get the owner partition for resource*/ 1853 /* Get the owner partition for resource*/
1854 resource_id = (sc_rsrc_t)ofnode_read_u32_default(args.node, "reg", SC_R_NONE); 1854 resource_id = (sc_rsrc_t)ofnode_read_u32_default(args.node, "reg", SC_R_NONE);
1855 if (resource_id == SC_R_NONE) { 1855 if (resource_id == SC_R_NONE) {
1856 printf("Can't find the resource id for udev %s\n", dev->name); 1856 printf("Can't find the resource id for udev %s\n", dev->name);
1857 return false; 1857 return false;
1858 } 1858 }
1859 1859
1860 debug("udev %s, resource id %d\n", dev->name, resource_id); 1860 debug("udev %s, resource id %d\n", dev->name, resource_id);
1861 1861
1862 return check_owned_resource(resource_id); 1862 return check_owned_resource(resource_id);
1863 } 1863 }
1864 1864
1865 bool check_m4_parts_boot(void) 1865 bool check_m4_parts_boot(void)
1866 { 1866 {
1867 sc_rm_pt_t m4_parts[2]; 1867 sc_rm_pt_t m4_parts[2];
1868 sc_ipc_t ipc; 1868 sc_ipc_t ipc;
1869 sc_err_t err; 1869 sc_err_t err;
1870 1870
1871 ipc = gd->arch.ipc_channel_handle; 1871 ipc = gd->arch.ipc_channel_handle;
1872 1872
1873 err = sc_rm_get_resource_owner(ipc, SC_R_M4_0_PID0, &m4_parts[0]); 1873 err = sc_rm_get_resource_owner(ipc, SC_R_M4_0_PID0, &m4_parts[0]);
1874 if (err != SC_ERR_NONE) { 1874 if (err != SC_ERR_NONE) {
1875 printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_0_PID0, err); 1875 printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_0_PID0, err);
1876 return false; 1876 return false;
1877 } 1877 }
1878 1878
1879 if (sc_pm_is_partition_started(ipc, m4_parts[0])) 1879 if (sc_pm_is_partition_started(ipc, m4_parts[0]))
1880 return true; 1880 return true;
1881 1881
1882 if (is_imx8qm()) { 1882 if (is_imx8qm()) {
1883 err = sc_rm_get_resource_owner(ipc, SC_R_M4_1_PID0, &m4_parts[1]); 1883 err = sc_rm_get_resource_owner(ipc, SC_R_M4_1_PID0, &m4_parts[1]);
1884 if (err != SC_ERR_NONE) { 1884 if (err != SC_ERR_NONE) {
1885 printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_1_PID0, err); 1885 printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_1_PID0, err);
1886 return false; 1886 return false;
1887 } 1887 }
1888 1888
1889 if (sc_pm_is_partition_started(ipc, m4_parts[1])) 1889 if (sc_pm_is_partition_started(ipc, m4_parts[1]))
1890 return true; 1890 return true;
1891 } 1891 }
1892 1892
1893 return false; 1893 return false;
1894 } 1894 }
1895 1895
1896 #ifdef CONFIG_IMX_VSERVICE 1896 #ifdef CONFIG_IMX_VSERVICE
1897 struct udevice * board_imx_vservice_find_mu(struct udevice *dev) 1897 struct udevice * board_imx_vservice_find_mu(struct udevice *dev)
1898 { 1898 {
1899 int ret; 1899 int ret;
1900 const char *m4_mu_name[2] = { 1900 const char *m4_mu_name[2] = {
1901 "mu@5d230000", 1901 "mu@5d230000",
1902 "mu@5d240000" 1902 "mu@5d240000"
1903 }; 1903 };
1904 struct udevice *m4_mu[2]; 1904 struct udevice *m4_mu[2];
1905 sc_rm_pt_t m4_parts[2]; 1905 sc_rm_pt_t m4_parts[2];
1906 sc_ipc_t ipc; 1906 sc_ipc_t ipc;
1907 sc_err_t err; 1907 sc_err_t err;
1908 struct ofnode_phandle_args args; 1908 struct ofnode_phandle_args args;
1909 sc_rsrc_t resource_id; 1909 sc_rsrc_t resource_id;
1910 sc_rm_pt_t resource_part; 1910 sc_rm_pt_t resource_part;
1911 1911
1912 ipc = gd->arch.ipc_channel_handle; 1912 ipc = gd->arch.ipc_channel_handle;
1913 1913
1914 /* Get the resource id from its power-domain */ 1914 /* Get the resource id from its power-domain */
1915 ret = dev_read_phandle_with_args(dev, "power-domains", 1915 ret = dev_read_phandle_with_args(dev, "power-domains",
1916 "#power-domain-cells", 0, 0, &args); 1916 "#power-domain-cells", 0, 0, &args);
1917 if (ret) { 1917 if (ret) {
1918 printf("Can't find the power-domains property for udev %s\n", dev->name); 1918 printf("Can't find the power-domains property for udev %s\n", dev->name);
1919 return NULL; 1919 return NULL;
1920 } 1920 }
1921 1921
1922 /* Get the owner partition for resource*/ 1922 /* Get the owner partition for resource*/
1923 resource_id = (sc_rsrc_t)ofnode_read_u32_default(args.node, "reg", SC_R_NONE); 1923 resource_id = (sc_rsrc_t)ofnode_read_u32_default(args.node, "reg", SC_R_NONE);
1924 if (resource_id == SC_R_NONE) { 1924 if (resource_id == SC_R_NONE) {
1925 printf("Can't find the resource id for udev %s\n", dev->name); 1925 printf("Can't find the resource id for udev %s\n", dev->name);
1926 return NULL; 1926 return NULL;
1927 } 1927 }
1928 1928
1929 err = sc_rm_get_resource_owner(ipc, resource_id, &resource_part); 1929 err = sc_rm_get_resource_owner(ipc, resource_id, &resource_part);
1930 if (err != SC_ERR_NONE) { 1930 if (err != SC_ERR_NONE) {
1931 printf("%s get resource [%d] owner error: %d\n", __func__, resource_id, err); 1931 printf("%s get resource [%d] owner error: %d\n", __func__, resource_id, err);
1932 return NULL; 1932 return NULL;
1933 } 1933 }
1934 1934
1935 debug("udev %s, resource id %d, resource part %d\n", dev->name, resource_id, resource_part); 1935 debug("udev %s, resource id %d, resource part %d\n", dev->name, resource_id, resource_part);
1936 1936
1937 /* MU8 for communication between M4_0 and u-boot, MU9 for M4_1 and u-boot */ 1937 /* MU8 for communication between M4_0 and u-boot, MU9 for M4_1 and u-boot */
1938 err = sc_rm_get_resource_owner(ipc, SC_R_M4_0_PID0, &m4_parts[0]); 1938 err = sc_rm_get_resource_owner(ipc, SC_R_M4_0_PID0, &m4_parts[0]);
1939 if (err != SC_ERR_NONE) { 1939 if (err != SC_ERR_NONE) {
1940 printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_0_PID0, err); 1940 printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_0_PID0, err);
1941 return NULL; 1941 return NULL;
1942 } 1942 }
1943 1943
1944 ret = uclass_find_device_by_name(UCLASS_MISC, m4_mu_name[0], &m4_mu[0]); 1944 ret = uclass_find_device_by_name(UCLASS_MISC, m4_mu_name[0], &m4_mu[0]);
1945 if (!ret) { 1945 if (!ret) {
1946 /* If the i2c is in m4_0 partition, return the mu8 */ 1946 /* If the i2c is in m4_0 partition, return the mu8 */
1947 if (resource_part == m4_parts[0]) 1947 if (resource_part == m4_parts[0])
1948 return m4_mu[0]; 1948 return m4_mu[0];
1949 } 1949 }
1950 1950
1951 if (is_imx8qm()) { 1951 if (is_imx8qm()) {
1952 err = sc_rm_get_resource_owner(ipc, SC_R_M4_1_PID0, &m4_parts[1]); 1952 err = sc_rm_get_resource_owner(ipc, SC_R_M4_1_PID0, &m4_parts[1]);
1953 if (err != SC_ERR_NONE) { 1953 if (err != SC_ERR_NONE) {
1954 printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_1_PID0, err); 1954 printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_1_PID0, err);
1955 return NULL; 1955 return NULL;
1956 } 1956 }
1957 1957
1958 ret = uclass_find_device_by_name(UCLASS_MISC, m4_mu_name[1], &m4_mu[1]); 1958 ret = uclass_find_device_by_name(UCLASS_MISC, m4_mu_name[1], &m4_mu[1]);
1959 if (!ret) { 1959 if (!ret) {
1960 /* If the i2c is in m4_1 partition, return the mu9 */ 1960 /* If the i2c is in m4_1 partition, return the mu9 */
1961 if (resource_part == m4_parts[1]) 1961 if (resource_part == m4_parts[1])
1962 return m4_mu[1]; 1962 return m4_mu[1];
1963 } 1963 }
1964 } 1964 }
1965 1965
1966 return NULL; 1966 return NULL;
1967 } 1967 }
1968 1968
1969 void * board_imx_vservice_get_buffer(struct imx_vservice_channel *node, u32 size) 1969 void * board_imx_vservice_get_buffer(struct imx_vservice_channel *node, u32 size)
1970 { 1970 {
1971 const char *m4_mu_name[2] = { 1971 const char *m4_mu_name[2] = {
1972 "mu@5d230000", 1972 "mu@5d230000",
1973 "mu@5d240000" 1973 "mu@5d240000"
1974 }; 1974 };
1975 1975
1976 /* Each MU ownes 1M buffer */ 1976 /* Each MU ownes 1M buffer */
1977 if (size <= 0x100000) { 1977 if (size <= 0x100000) {
1978 if (!strcmp(node->mu_dev->name, m4_mu_name[0])) 1978 if (!strcmp(node->mu_dev->name, m4_mu_name[0]))
1979 return (void * )CONFIG_IMX_VSERVICE_SHARED_BUFFER; 1979 return (void * )CONFIG_IMX_VSERVICE_SHARED_BUFFER;
1980 else if (!strcmp(node->mu_dev->name, m4_mu_name[1])) 1980 else if (!strcmp(node->mu_dev->name, m4_mu_name[1]))
1981 return (void * )(CONFIG_IMX_VSERVICE_SHARED_BUFFER + 0x100000); 1981 return (void * )(CONFIG_IMX_VSERVICE_SHARED_BUFFER + 0x100000);
1982 else 1982 else
1983 return NULL; 1983 return NULL;
1984 } 1984 }
1985 1985
1986 return NULL; 1986 return NULL;
1987 } 1987 }
1988 #endif 1988 #endif
1989 1989
1990 /* imx8qxp i2c1 has lots of devices may used by both M4 and A core 1990 /* imx8qxp i2c1 has lots of devices may used by both M4 and A core
1991 * If A core partition does not own the resource, we will start 1991 * If A core partition does not own the resource, we will start
1992 * virtual i2c driver. Otherwise use local i2c driver. 1992 * virtual i2c driver. Otherwise use local i2c driver.
1993 */ 1993 */
1994 int board_imx_virt_i2c_bind(struct udevice *dev) 1994 int board_imx_virt_i2c_bind(struct udevice *dev)
1995 { 1995 {
1996 if (check_owned_udevice(dev)) 1996 if (check_owned_udevice(dev))
1997 return -ENODEV; 1997 return -ENODEV;
1998 1998
1999 return 0; 1999 return 0;
2000 } 2000 }
2001 2001
2002 int board_imx_lpi2c_bind(struct udevice *dev) 2002 int board_imx_lpi2c_bind(struct udevice *dev)
2003 { 2003 {
2004 if (check_owned_udevice(dev)) 2004 if (check_owned_udevice(dev))
2005 return 0; 2005 return 0;
2006 2006
2007 return -ENODEV; 2007 return -ENODEV;
2008 } 2008 }
2009 2009
2010 void board_boot_order(u32 *spl_boot_list) 2010 void board_boot_order(u32 *spl_boot_list)
2011 { 2011 {
2012 spl_boot_list[0] = spl_boot_device(); 2012 spl_boot_list[0] = spl_boot_device();
2013 2013
2014 if (spl_boot_list[0] == BOOT_DEVICE_SPI) { 2014 if (spl_boot_list[0] == BOOT_DEVICE_SPI) {
2015 /* Check whether we own the flexspi0, if not, use NOR boot */ 2015 /* Check whether we own the flexspi0, if not, use NOR boot */
2016 if (!check_owned_resource(SC_R_FSPI_0)) 2016 if (!check_owned_resource(SC_R_FSPI_0))
2017 spl_boot_list[0] = BOOT_DEVICE_NOR; 2017 spl_boot_list[0] = BOOT_DEVICE_NOR;
2018 } 2018 }
2019 } 2019 }
2020 2020
configs/imx8qm_ddr4_arm2_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-ddr4-arm2" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-ddr4-arm2"
4 CONFIG_TARGET_IMX8QM_DDR4_ARM2=y 4 CONFIG_TARGET_IMX8QM_DDR4_ARM2=y
5 CONFIG_SYS_TEXT_BASE=0x80020000 5 CONFIG_SYS_TEXT_BASE=0x80020000
6 CONFIG_CMD_IMPORTENV=n 6 CONFIG_CMD_IMPORTENV=n
7 CONFIG_SYS_MALLOC_F_LEN=0x2000 7 CONFIG_SYS_MALLOC_F_LEN=0x2000
8 CONFIG_DM=y 8 CONFIG_DM=y
9 CONFIG_CMD_CACHE=y 9 CONFIG_CMD_CACHE=y
10 10
11 CONFIG_DM_SERIAL=y 11 CONFIG_DM_SERIAL=y
12 CONFIG_FSL_LPUART=y 12 CONFIG_FSL_LPUART=y
13 CONFIG_OF_CONTROL=y 13 CONFIG_OF_CONTROL=y
14 CONFIG_DM_I2C=y 14 CONFIG_DM_I2C=y
15 # CONFIG_DM_I2C_COMPAT is not set 15 # CONFIG_DM_I2C_COMPAT is not set
16 CONFIG_SYS_I2C_IMX_LPI2C=y 16 CONFIG_SYS_I2C_IMX_LPI2C=y
17 CONFIG_CMD_I2C=y 17 CONFIG_CMD_I2C=y
18 18
19 CONFIG_USB_XHCI_HCD=y 19 CONFIG_USB_XHCI_HCD=y
20 CONFIG_USB_XHCI_IMX8=y 20 CONFIG_USB_XHCI_IMX8=y
21 21
22 CONFIG_DM_USB=y 22 CONFIG_DM_USB=y
23 CONFIG_USB_EHCI_HCD=y 23 CONFIG_USB_EHCI_HCD=y
24 24
25 CONFIG_CMD_USB=y 25 CONFIG_CMD_USB=y
26 CONFIG_USB=y 26 CONFIG_USB=y
27 CONFIG_USB_STORAGE=y 27 CONFIG_USB_STORAGE=y
28 28
29 CONFIG_CMD_USB_MASS_STORAGE=y 29 CONFIG_CMD_USB_MASS_STORAGE=y
30 CONFIG_USB_GADGET=y 30 CONFIG_USB_GADGET=y
31 # CONFIG_CI_UDC=y 31 # CONFIG_CI_UDC=y
32 CONFIG_USB_GADGET_DOWNLOAD=y 32 CONFIG_USB_GADGET_DOWNLOAD=y
33 CONFIG_USB_GADGET_MANUFACTURER="FSL" 33 CONFIG_USB_GADGET_MANUFACTURER="FSL"
34 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 34 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
35 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 35 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
36 36
37 CONFIG_USB_CDNS3=y 37 CONFIG_USB_CDNS3=y
38 CONFIG_USB_CDNS3_GADGET=y 38 CONFIG_USB_CDNS3_GADGET=y
39 CONFIG_USB_GADGET_DUALSPEED=y 39 CONFIG_USB_GADGET_DUALSPEED=y
40 40
41 CONFIG_CMD_GPIO=y 41 CONFIG_CMD_GPIO=y
42 CONFIG_DM_GPIO=y 42 CONFIG_DM_GPIO=y
43 CONFIG_DM_PCA953X=y 43 CONFIG_DM_PCA953X=y
44 CONFIG_BOOTDELAY=3 44 CONFIG_BOOTDELAY=3
45 CONFIG_IMX_BOOTAUX=y 45 CONFIG_IMX_BOOTAUX=y
46 CONFIG_FS_FAT=y 46 CONFIG_FS_FAT=y
47 CONFIG_CMD_FAT=y 47 CONFIG_CMD_FAT=y
48 CONFIG_CMD_MMC=y 48 CONFIG_CMD_MMC=y
49 CONFIG_DM_MMC=y 49 CONFIG_DM_MMC=y
50 CONFIG_MMC_IO_VOLTAGE=y 50 CONFIG_MMC_IO_VOLTAGE=y
51 CONFIG_MMC_UHS_SUPPORT=y 51 CONFIG_MMC_UHS_SUPPORT=y
52 CONFIG_MMC_HS400_SUPPORT=y 52 CONFIG_MMC_HS400_SUPPORT=y
53 CONFIG_FSL_FSPI=y 53 CONFIG_FSL_FSPI=y
54 CONFIG_DM_SPI=y 54 CONFIG_DM_SPI=y
55 CONFIG_DM_SPI_FLASH=y 55 CONFIG_DM_SPI_FLASH=y
56 CONFIG_SPI_FLASH=y 56 CONFIG_SPI_FLASH=y
57 CONFIG_SPI_FLASH_4BYTES_ADDR=y 57 CONFIG_SPI_FLASH_4BYTES_ADDR=y
58 CONFIG_SPI_FLASH_STMICRO=y 58 CONFIG_SPI_FLASH_STMICRO=y
59 CONFIG_CMD_SF=y 59 CONFIG_CMD_SF=y
60 60
61 CONFIG_CMD_PING=y 61 CONFIG_CMD_PING=y
62 CONFIG_CMD_DHCP=y 62 CONFIG_CMD_DHCP=y
63 CONFIG_CMD_MII=y 63 CONFIG_CMD_MII=y
64 CONFIG_DM_ETH=y 64 CONFIG_DM_ETH=y
65 # CONFIG_EFI_LOADER is not set 65 # CONFIG_EFI_LOADER is not set
66 66
67 CONFIG_DM_REGULATOR=y 67 CONFIG_DM_REGULATOR=y
68 CONFIG_DM_REGULATOR_FIXED=y 68 CONFIG_DM_REGULATOR_FIXED=y
69 CONFIG_DM_REGULATOR_GPIO=y 69 CONFIG_DM_REGULATOR_GPIO=y
70 70
71 CONFIG_VIDEO=y 71 CONFIG_VIDEO=y
72 CONFIG_VIDEO_IMX_HDP_LOAD=y 72 CONFIG_VIDEO_IMX_HDP_LOAD=y
73 73
74 CONFIG_PINCTRL=y 74 CONFIG_PINCTRL=y
75 CONFIG_PINCTRL_IMX8=y 75 CONFIG_PINCTRL_IMX8=y
76 76
77 CONFIG_POWER_DOMAIN=y 77 CONFIG_POWER_DOMAIN=y
78 CONFIG_IMX8_POWER_DOMAIN=y 78 CONFIG_IMX8_POWER_DOMAIN=y
79 79
80 CONFIG_DM_THERMAL=y 80 CONFIG_DM_THERMAL=y
81 CONFIG_IMX_SC_THERMAL=y 81 CONFIG_IMX_SC_THERMAL=y
82 82
83 CONFIG_ENV_IS_IN_MMC=y 83 CONFIG_ENV_IS_IN_MMC=y
84 84
85 CONFIG_SMC_FUSE=y 85 CONFIG_SMC_FUSE=y
86 CONFIG_CMD_MEMTEST=y 86 CONFIG_CMD_MEMTEST=y
87
88 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
89 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
87 90
configs/imx8qm_ddr4_arm2_spl_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-ddr4-arm2" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-ddr4-arm2"
4 CONFIG_TARGET_IMX8QM_DDR4_ARM2=y 4 CONFIG_TARGET_IMX8QM_DDR4_ARM2=y
5 CONFIG_SYS_TEXT_BASE=0x80020000 5 CONFIG_SYS_TEXT_BASE=0x80020000
6 CONFIG_CMD_IMPORTENV=n 6 CONFIG_CMD_IMPORTENV=n
7 CONFIG_SYS_MALLOC_F_LEN=0x2000 7 CONFIG_SYS_MALLOC_F_LEN=0x2000
8 CONFIG_DM=y 8 CONFIG_DM=y
9 CONFIG_CMD_CACHE=y 9 CONFIG_CMD_CACHE=y
10 10
11 CONFIG_DM_SERIAL=y 11 CONFIG_DM_SERIAL=y
12 CONFIG_FSL_LPUART=y 12 CONFIG_FSL_LPUART=y
13 CONFIG_OF_CONTROL=y 13 CONFIG_OF_CONTROL=y
14 CONFIG_DM_I2C=y 14 CONFIG_DM_I2C=y
15 # CONFIG_DM_I2C_COMPAT is not set 15 # CONFIG_DM_I2C_COMPAT is not set
16 CONFIG_SYS_I2C_IMX_LPI2C=y 16 CONFIG_SYS_I2C_IMX_LPI2C=y
17 CONFIG_CMD_I2C=y 17 CONFIG_CMD_I2C=y
18 18
19 CONFIG_SPL=y 19 CONFIG_SPL=y
20 CONFIG_SPL_GPIO_SUPPORT=y 20 CONFIG_SPL_GPIO_SUPPORT=y
21 CONFIG_SPL_MMC_SUPPORT=y 21 CONFIG_SPL_MMC_SUPPORT=y
22 CONFIG_SPL_BOARD_INIT=y 22 CONFIG_SPL_BOARD_INIT=y
23 CONFIG_SPL_SYS_MALLOC_SIMPLE=y 23 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
24 CONFIG_SPL_TINY_MEMSET=y 24 CONFIG_SPL_TINY_MEMSET=y
25 CONFIG_SPL_OF_CONTROL=y 25 CONFIG_SPL_OF_CONTROL=y
26 26
27 CONFIG_USB_XHCI_HCD=y 27 CONFIG_USB_XHCI_HCD=y
28 CONFIG_USB_XHCI_IMX8=y 28 CONFIG_USB_XHCI_IMX8=y
29 29
30 CONFIG_DM_USB=y 30 CONFIG_DM_USB=y
31 CONFIG_USB_EHCI_HCD=y 31 CONFIG_USB_EHCI_HCD=y
32 32
33 CONFIG_CMD_USB=y 33 CONFIG_CMD_USB=y
34 CONFIG_USB=y 34 CONFIG_USB=y
35 CONFIG_USB_STORAGE=y 35 CONFIG_USB_STORAGE=y
36 36
37 CONFIG_CMD_USB_MASS_STORAGE=y 37 CONFIG_CMD_USB_MASS_STORAGE=y
38 CONFIG_USB_GADGET=y 38 CONFIG_USB_GADGET=y
39 # CONFIG_CI_UDC=y 39 # CONFIG_CI_UDC=y
40 CONFIG_USB_GADGET_DOWNLOAD=y 40 CONFIG_USB_GADGET_DOWNLOAD=y
41 CONFIG_USB_GADGET_MANUFACTURER="FSL" 41 CONFIG_USB_GADGET_MANUFACTURER="FSL"
42 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 42 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
43 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 43 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
44 44
45 CONFIG_USB_CDNS3=y 45 CONFIG_USB_CDNS3=y
46 CONFIG_USB_CDNS3_GADGET=y 46 CONFIG_USB_CDNS3_GADGET=y
47 CONFIG_USB_GADGET_DUALSPEED=y 47 CONFIG_USB_GADGET_DUALSPEED=y
48 48
49 CONFIG_CMD_GPIO=y 49 CONFIG_CMD_GPIO=y
50 CONFIG_DM_GPIO=y 50 CONFIG_DM_GPIO=y
51 CONFIG_DM_PCA953X=y 51 CONFIG_DM_PCA953X=y
52 CONFIG_BOOTDELAY=3 52 CONFIG_BOOTDELAY=3
53 CONFIG_IMX_BOOTAUX=y 53 CONFIG_IMX_BOOTAUX=y
54 CONFIG_FS_FAT=y 54 CONFIG_FS_FAT=y
55 CONFIG_CMD_FAT=y 55 CONFIG_CMD_FAT=y
56 CONFIG_CMD_MMC=y 56 CONFIG_CMD_MMC=y
57 CONFIG_DM_MMC=y 57 CONFIG_DM_MMC=y
58 CONFIG_MMC_IO_VOLTAGE=y 58 CONFIG_MMC_IO_VOLTAGE=y
59 CONFIG_MMC_UHS_SUPPORT=y 59 CONFIG_MMC_UHS_SUPPORT=y
60 CONFIG_MMC_HS400_SUPPORT=y 60 CONFIG_MMC_HS400_SUPPORT=y
61 CONFIG_FSL_FSPI=y 61 CONFIG_FSL_FSPI=y
62 CONFIG_DM_SPI=y 62 CONFIG_DM_SPI=y
63 CONFIG_DM_SPI_FLASH=y 63 CONFIG_DM_SPI_FLASH=y
64 CONFIG_SPI_FLASH=y 64 CONFIG_SPI_FLASH=y
65 CONFIG_SPI_FLASH_4BYTES_ADDR=y 65 CONFIG_SPI_FLASH_4BYTES_ADDR=y
66 CONFIG_SPI_FLASH_STMICRO=y 66 CONFIG_SPI_FLASH_STMICRO=y
67 CONFIG_CMD_SF=y 67 CONFIG_CMD_SF=y
68 68
69 CONFIG_CMD_PING=y 69 CONFIG_CMD_PING=y
70 CONFIG_CMD_DHCP=y 70 CONFIG_CMD_DHCP=y
71 CONFIG_CMD_MII=y 71 CONFIG_CMD_MII=y
72 CONFIG_DM_ETH=y 72 CONFIG_DM_ETH=y
73 # CONFIG_EFI_LOADER is not set 73 # CONFIG_EFI_LOADER is not set
74 74
75 CONFIG_DM_REGULATOR=y 75 CONFIG_DM_REGULATOR=y
76 CONFIG_DM_REGULATOR_FIXED=y 76 CONFIG_DM_REGULATOR_FIXED=y
77 CONFIG_DM_REGULATOR_GPIO=y 77 CONFIG_DM_REGULATOR_GPIO=y
78 78
79 CONFIG_VIDEO=y 79 CONFIG_VIDEO=y
80 CONFIG_VIDEO_IMX_HDP_LOAD=y 80 CONFIG_VIDEO_IMX_HDP_LOAD=y
81 81
82 CONFIG_PINCTRL=y 82 CONFIG_PINCTRL=y
83 CONFIG_PINCTRL_IMX8=y 83 CONFIG_PINCTRL_IMX8=y
84 84
85 CONFIG_POWER_DOMAIN=y 85 CONFIG_POWER_DOMAIN=y
86 CONFIG_IMX8_POWER_DOMAIN=y 86 CONFIG_IMX8_POWER_DOMAIN=y
87 87
88 CONFIG_DM_THERMAL=y 88 CONFIG_DM_THERMAL=y
89 CONFIG_IMX_SC_THERMAL=y 89 CONFIG_IMX_SC_THERMAL=y
90 90
91 CONFIG_ENV_IS_IN_MMC=y 91 CONFIG_ENV_IS_IN_MMC=y
92 92
93 CONFIG_SMC_FUSE=y 93 CONFIG_SMC_FUSE=y
94 CONFIG_CMD_MEMTEST=y 94 CONFIG_CMD_MEMTEST=y
95
96 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
97 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
95 98
configs/imx8qm_lpddr4_arm2_android_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-lpddr4-arm2" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-lpddr4-arm2"
4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT" 4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT"
5 CONFIG_EFI_PARTITION=y 5 CONFIG_EFI_PARTITION=y
6 CONFIG_TARGET_IMX8QM_LPDDR4_ARM2=y 6 CONFIG_TARGET_IMX8QM_LPDDR4_ARM2=y
7 CONFIG_SYS_TEXT_BASE=0x80020000 7 CONFIG_SYS_TEXT_BASE=0x80020000
8 CONFIG_CMD_IMPORTENV=n 8 CONFIG_CMD_IMPORTENV=n
9 CONFIG_SYS_MALLOC_F_LEN=0x2000 9 CONFIG_SYS_MALLOC_F_LEN=0x2000
10 CONFIG_DM=y 10 CONFIG_DM=y
11 CONFIG_CMD_CACHE=y 11 CONFIG_CMD_CACHE=y
12 12
13 CONFIG_DM_SERIAL=y 13 CONFIG_DM_SERIAL=y
14 CONFIG_FSL_LPUART=y 14 CONFIG_FSL_LPUART=y
15 CONFIG_OF_CONTROL=y 15 CONFIG_OF_CONTROL=y
16 CONFIG_DM_I2C=y 16 CONFIG_DM_I2C=y
17 # CONFIG_DM_I2C_COMPAT is not set 17 # CONFIG_DM_I2C_COMPAT is not set
18 CONFIG_SYS_I2C_IMX_LPI2C=y 18 CONFIG_SYS_I2C_IMX_LPI2C=y
19 CONFIG_CMD_I2C=y 19 CONFIG_CMD_I2C=y
20 20
21 CONFIG_USB_XHCI_HCD=y 21 CONFIG_USB_XHCI_HCD=y
22 CONFIG_USB_XHCI_IMX8=y 22 CONFIG_USB_XHCI_IMX8=y
23 23
24 CONFIG_DM_USB=y 24 CONFIG_DM_USB=y
25 CONFIG_USB_EHCI_HCD=y 25 CONFIG_USB_EHCI_HCD=y
26 26
27 CONFIG_CMD_USB=y 27 CONFIG_CMD_USB=y
28 CONFIG_USB=y 28 CONFIG_USB=y
29 CONFIG_USB_STORAGE=y 29 CONFIG_USB_STORAGE=y
30 30
31 CONFIG_CMD_USB_MASS_STORAGE=y 31 CONFIG_CMD_USB_MASS_STORAGE=y
32 CONFIG_USB_GADGET=y 32 CONFIG_USB_GADGET=y
33 # CONFIG_CI_UDC=y 33 # CONFIG_CI_UDC=y
34 CONFIG_USB_GADGET_DOWNLOAD=y 34 CONFIG_USB_GADGET_DOWNLOAD=y
35 CONFIG_USB_GADGET_MANUFACTURER="FSL" 35 CONFIG_USB_GADGET_MANUFACTURER="FSL"
36 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 36 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
37 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 37 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02
38 38
39 CONFIG_USB_CDNS3=y 39 CONFIG_USB_CDNS3=y
40 CONFIG_USB_CDNS3_GADGET=y 40 CONFIG_USB_CDNS3_GADGET=y
41 CONFIG_USB_GADGET_DUALSPEED=y 41 CONFIG_USB_GADGET_DUALSPEED=y
42 42
43 CONFIG_CMD_GPIO=y 43 CONFIG_CMD_GPIO=y
44 CONFIG_DM_GPIO=y 44 CONFIG_DM_GPIO=y
45 CONFIG_DM_PCA953X=y 45 CONFIG_DM_PCA953X=y
46 CONFIG_BOOTDELAY=1 46 CONFIG_BOOTDELAY=1
47 CONFIG_IMX_BOOTAUX=y 47 CONFIG_IMX_BOOTAUX=y
48 CONFIG_FS_FAT=y 48 CONFIG_FS_FAT=y
49 CONFIG_CMD_FAT=y 49 CONFIG_CMD_FAT=y
50 CONFIG_CMD_MMC=y 50 CONFIG_CMD_MMC=y
51 CONFIG_DM_MMC=y 51 CONFIG_DM_MMC=y
52 CONFIG_MMC_IO_VOLTAGE=y 52 CONFIG_MMC_IO_VOLTAGE=y
53 CONFIG_MMC_UHS_SUPPORT=y 53 CONFIG_MMC_UHS_SUPPORT=y
54 CONFIG_MMC_HS400_SUPPORT=y 54 CONFIG_MMC_HS400_SUPPORT=y
55 CONFIG_FSL_FSPI=y 55 CONFIG_FSL_FSPI=y
56 CONFIG_DM_SPI=y 56 CONFIG_DM_SPI=y
57 CONFIG_DM_SPI_FLASH=y 57 CONFIG_DM_SPI_FLASH=y
58 CONFIG_SPI_FLASH=y 58 CONFIG_SPI_FLASH=y
59 CONFIG_SPI_FLASH_4BYTES_ADDR=y 59 CONFIG_SPI_FLASH_4BYTES_ADDR=y
60 CONFIG_SPI_FLASH_STMICRO=y 60 CONFIG_SPI_FLASH_STMICRO=y
61 CONFIG_CMD_SF=y 61 CONFIG_CMD_SF=y
62 62
63 CONFIG_CMD_PING=y 63 CONFIG_CMD_PING=y
64 CONFIG_CMD_DHCP=y 64 CONFIG_CMD_DHCP=y
65 CONFIG_CMD_MII=y 65 CONFIG_CMD_MII=y
66 CONFIG_DM_ETH=y 66 CONFIG_DM_ETH=y
67 # CONFIG_EFI_LOADER is not set 67 # CONFIG_EFI_LOADER is not set
68 68
69 CONFIG_DM_REGULATOR=y 69 CONFIG_DM_REGULATOR=y
70 CONFIG_DM_REGULATOR_FIXED=y 70 CONFIG_DM_REGULATOR_FIXED=y
71 CONFIG_DM_REGULATOR_GPIO=y 71 CONFIG_DM_REGULATOR_GPIO=y
72 72
73 CONFIG_VIDEO=y 73 CONFIG_VIDEO=y
74 CONFIG_VIDEO_IMX_HDP_LOAD=y 74 CONFIG_VIDEO_IMX_HDP_LOAD=y
75 75
76 CONFIG_PINCTRL=y 76 CONFIG_PINCTRL=y
77 CONFIG_PINCTRL_IMX8=y 77 CONFIG_PINCTRL_IMX8=y
78 78
79 CONFIG_POWER_DOMAIN=y 79 CONFIG_POWER_DOMAIN=y
80 CONFIG_IMX8_POWER_DOMAIN=y 80 CONFIG_IMX8_POWER_DOMAIN=y
81 81
82 CONFIG_DM_THERMAL=y 82 CONFIG_DM_THERMAL=y
83 CONFIG_IMX_SC_THERMAL=y 83 CONFIG_IMX_SC_THERMAL=y
84 84
85 CONFIG_ENV_IS_IN_MMC=y 85 CONFIG_ENV_IS_IN_MMC=y
86 86
87 CONFIG_SMC_FUSE=y 87 CONFIG_SMC_FUSE=y
88 CONFIG_CMD_MEMTEST=y 88 CONFIG_CMD_MEMTEST=y
89
90 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
91 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
89 92
configs/imx8qm_lpddr4_arm2_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-lpddr4-arm2" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-lpddr4-arm2"
4 CONFIG_TARGET_IMX8QM_LPDDR4_ARM2=y 4 CONFIG_TARGET_IMX8QM_LPDDR4_ARM2=y
5 CONFIG_SYS_TEXT_BASE=0x80020000 5 CONFIG_SYS_TEXT_BASE=0x80020000
6 CONFIG_CMD_IMPORTENV=n 6 CONFIG_CMD_IMPORTENV=n
7 CONFIG_SYS_MALLOC_F_LEN=0x2000 7 CONFIG_SYS_MALLOC_F_LEN=0x2000
8 CONFIG_DM=y 8 CONFIG_DM=y
9 CONFIG_CMD_CACHE=y 9 CONFIG_CMD_CACHE=y
10 10
11 CONFIG_DM_SERIAL=y 11 CONFIG_DM_SERIAL=y
12 CONFIG_FSL_LPUART=y 12 CONFIG_FSL_LPUART=y
13 CONFIG_OF_CONTROL=y 13 CONFIG_OF_CONTROL=y
14 CONFIG_DM_I2C=y 14 CONFIG_DM_I2C=y
15 # CONFIG_DM_I2C_COMPAT is not set 15 # CONFIG_DM_I2C_COMPAT is not set
16 CONFIG_SYS_I2C_IMX_LPI2C=y 16 CONFIG_SYS_I2C_IMX_LPI2C=y
17 CONFIG_CMD_I2C=y 17 CONFIG_CMD_I2C=y
18 18
19 CONFIG_USB_XHCI_HCD=y 19 CONFIG_USB_XHCI_HCD=y
20 CONFIG_USB_XHCI_IMX8=y 20 CONFIG_USB_XHCI_IMX8=y
21 21
22 CONFIG_DM_USB=y 22 CONFIG_DM_USB=y
23 CONFIG_USB_EHCI_HCD=y 23 CONFIG_USB_EHCI_HCD=y
24 24
25 CONFIG_CMD_USB=y 25 CONFIG_CMD_USB=y
26 CONFIG_USB=y 26 CONFIG_USB=y
27 CONFIG_USB_STORAGE=y 27 CONFIG_USB_STORAGE=y
28 28
29 CONFIG_CMD_USB_MASS_STORAGE=y 29 CONFIG_CMD_USB_MASS_STORAGE=y
30 CONFIG_USB_GADGET=y 30 CONFIG_USB_GADGET=y
31 # CONFIG_CI_UDC=y 31 # CONFIG_CI_UDC=y
32 CONFIG_USB_GADGET_DOWNLOAD=y 32 CONFIG_USB_GADGET_DOWNLOAD=y
33 CONFIG_USB_GADGET_MANUFACTURER="FSL" 33 CONFIG_USB_GADGET_MANUFACTURER="FSL"
34 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 34 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
35 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 35 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
36 36
37 CONFIG_USB_CDNS3=y 37 CONFIG_USB_CDNS3=y
38 CONFIG_USB_CDNS3_GADGET=y 38 CONFIG_USB_CDNS3_GADGET=y
39 CONFIG_USB_GADGET_DUALSPEED=y 39 CONFIG_USB_GADGET_DUALSPEED=y
40 40
41 CONFIG_CMD_GPIO=y 41 CONFIG_CMD_GPIO=y
42 CONFIG_DM_GPIO=y 42 CONFIG_DM_GPIO=y
43 CONFIG_DM_PCA953X=y 43 CONFIG_DM_PCA953X=y
44 CONFIG_BOOTDELAY=3 44 CONFIG_BOOTDELAY=3
45 CONFIG_IMX_BOOTAUX=y 45 CONFIG_IMX_BOOTAUX=y
46 CONFIG_FS_FAT=y 46 CONFIG_FS_FAT=y
47 CONFIG_CMD_FAT=y 47 CONFIG_CMD_FAT=y
48 CONFIG_CMD_MMC=y 48 CONFIG_CMD_MMC=y
49 CONFIG_DM_MMC=y 49 CONFIG_DM_MMC=y
50 CONFIG_MMC_IO_VOLTAGE=y 50 CONFIG_MMC_IO_VOLTAGE=y
51 CONFIG_MMC_UHS_SUPPORT=y 51 CONFIG_MMC_UHS_SUPPORT=y
52 CONFIG_MMC_HS400_SUPPORT=y 52 CONFIG_MMC_HS400_SUPPORT=y
53 CONFIG_FSL_FSPI=y 53 CONFIG_FSL_FSPI=y
54 CONFIG_DM_SPI=y 54 CONFIG_DM_SPI=y
55 CONFIG_DM_SPI_FLASH=y 55 CONFIG_DM_SPI_FLASH=y
56 CONFIG_SPI_FLASH=y 56 CONFIG_SPI_FLASH=y
57 CONFIG_SPI_FLASH_4BYTES_ADDR=y 57 CONFIG_SPI_FLASH_4BYTES_ADDR=y
58 CONFIG_SPI_FLASH_STMICRO=y 58 CONFIG_SPI_FLASH_STMICRO=y
59 CONFIG_CMD_SF=y 59 CONFIG_CMD_SF=y
60 60
61 CONFIG_CMD_PING=y 61 CONFIG_CMD_PING=y
62 CONFIG_CMD_DHCP=y 62 CONFIG_CMD_DHCP=y
63 CONFIG_CMD_MII=y 63 CONFIG_CMD_MII=y
64 CONFIG_DM_ETH=y 64 CONFIG_DM_ETH=y
65 # CONFIG_EFI_LOADER is not set 65 # CONFIG_EFI_LOADER is not set
66 66
67 CONFIG_DM_REGULATOR=y 67 CONFIG_DM_REGULATOR=y
68 CONFIG_DM_REGULATOR_FIXED=y 68 CONFIG_DM_REGULATOR_FIXED=y
69 CONFIG_DM_REGULATOR_GPIO=y 69 CONFIG_DM_REGULATOR_GPIO=y
70 70
71 CONFIG_VIDEO=y 71 CONFIG_VIDEO=y
72 CONFIG_VIDEO_IMX_HDP_LOAD=y 72 CONFIG_VIDEO_IMX_HDP_LOAD=y
73 73
74 CONFIG_PINCTRL=y 74 CONFIG_PINCTRL=y
75 CONFIG_PINCTRL_IMX8=y 75 CONFIG_PINCTRL_IMX8=y
76 76
77 CONFIG_POWER_DOMAIN=y 77 CONFIG_POWER_DOMAIN=y
78 CONFIG_IMX8_POWER_DOMAIN=y 78 CONFIG_IMX8_POWER_DOMAIN=y
79 79
80 CONFIG_DM_THERMAL=y 80 CONFIG_DM_THERMAL=y
81 CONFIG_IMX_SC_THERMAL=y 81 CONFIG_IMX_SC_THERMAL=y
82 82
83 CONFIG_ENV_IS_IN_MMC=y 83 CONFIG_ENV_IS_IN_MMC=y
84 84
85 CONFIG_SMC_FUSE=y 85 CONFIG_SMC_FUSE=y
86 CONFIG_CMD_MEMTEST=y 86 CONFIG_CMD_MEMTEST=y
87
88 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
89 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
87 90
configs/imx8qm_lpddr4_arm2_fspi_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-lpddr4-arm2" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-lpddr4-arm2"
4 CONFIG_TARGET_IMX8QM_LPDDR4_ARM2=y 4 CONFIG_TARGET_IMX8QM_LPDDR4_ARM2=y
5 CONFIG_SYS_TEXT_BASE=0x80020000 5 CONFIG_SYS_TEXT_BASE=0x80020000
6 CONFIG_CMD_IMPORTENV=n 6 CONFIG_CMD_IMPORTENV=n
7 CONFIG_SYS_MALLOC_F_LEN=0x2000 7 CONFIG_SYS_MALLOC_F_LEN=0x2000
8 CONFIG_DM=y 8 CONFIG_DM=y
9 CONFIG_CMD_CACHE=y 9 CONFIG_CMD_CACHE=y
10 10
11 CONFIG_DM_SERIAL=y 11 CONFIG_DM_SERIAL=y
12 CONFIG_FSL_LPUART=y 12 CONFIG_FSL_LPUART=y
13 CONFIG_OF_CONTROL=y 13 CONFIG_OF_CONTROL=y
14 CONFIG_DM_I2C=y 14 CONFIG_DM_I2C=y
15 # CONFIG_DM_I2C_COMPAT is not set 15 # CONFIG_DM_I2C_COMPAT is not set
16 CONFIG_SYS_I2C_IMX_LPI2C=y 16 CONFIG_SYS_I2C_IMX_LPI2C=y
17 CONFIG_CMD_I2C=y 17 CONFIG_CMD_I2C=y
18 18
19 CONFIG_USB_XHCI_HCD=y 19 CONFIG_USB_XHCI_HCD=y
20 CONFIG_USB_XHCI_IMX8=y 20 CONFIG_USB_XHCI_IMX8=y
21 21
22 CONFIG_DM_USB=y 22 CONFIG_DM_USB=y
23 CONFIG_USB_EHCI_HCD=y 23 CONFIG_USB_EHCI_HCD=y
24 24
25 CONFIG_CMD_USB=y 25 CONFIG_CMD_USB=y
26 CONFIG_USB=y 26 CONFIG_USB=y
27 CONFIG_USB_STORAGE=y 27 CONFIG_USB_STORAGE=y
28 28
29 CONFIG_CMD_USB_MASS_STORAGE=y 29 CONFIG_CMD_USB_MASS_STORAGE=y
30 CONFIG_USB_GADGET=y 30 CONFIG_USB_GADGET=y
31 # CONFIG_CI_UDC=y 31 # CONFIG_CI_UDC=y
32 CONFIG_USB_GADGET_DOWNLOAD=y 32 CONFIG_USB_GADGET_DOWNLOAD=y
33 CONFIG_USB_GADGET_MANUFACTURER="FSL" 33 CONFIG_USB_GADGET_MANUFACTURER="FSL"
34 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 34 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
35 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 35 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
36 36
37 CONFIG_USB_CDNS3=y 37 CONFIG_USB_CDNS3=y
38 CONFIG_USB_CDNS3_GADGET=y 38 CONFIG_USB_CDNS3_GADGET=y
39 CONFIG_USB_GADGET_DUALSPEED=y 39 CONFIG_USB_GADGET_DUALSPEED=y
40 40
41 CONFIG_CMD_GPIO=y 41 CONFIG_CMD_GPIO=y
42 CONFIG_DM_GPIO=y 42 CONFIG_DM_GPIO=y
43 CONFIG_DM_PCA953X=y 43 CONFIG_DM_PCA953X=y
44 CONFIG_BOOTDELAY=3 44 CONFIG_BOOTDELAY=3
45 CONFIG_IMX_BOOTAUX=y 45 CONFIG_IMX_BOOTAUX=y
46 CONFIG_FS_FAT=y 46 CONFIG_FS_FAT=y
47 CONFIG_CMD_FAT=y 47 CONFIG_CMD_FAT=y
48 CONFIG_CMD_MMC=y 48 CONFIG_CMD_MMC=y
49 CONFIG_DM_MMC=y 49 CONFIG_DM_MMC=y
50 CONFIG_MMC_IO_VOLTAGE=y 50 CONFIG_MMC_IO_VOLTAGE=y
51 CONFIG_MMC_UHS_SUPPORT=y 51 CONFIG_MMC_UHS_SUPPORT=y
52 CONFIG_MMC_HS400_SUPPORT=y 52 CONFIG_MMC_HS400_SUPPORT=y
53 CONFIG_QSPI_BOOT=y 53 CONFIG_QSPI_BOOT=y
54 CONFIG_FSL_FSPI=y 54 CONFIG_FSL_FSPI=y
55 CONFIG_DM_SPI=y 55 CONFIG_DM_SPI=y
56 CONFIG_DM_SPI_FLASH=y 56 CONFIG_DM_SPI_FLASH=y
57 CONFIG_SPI_FLASH=y 57 CONFIG_SPI_FLASH=y
58 CONFIG_SPI_FLASH_4BYTES_ADDR=y 58 CONFIG_SPI_FLASH_4BYTES_ADDR=y
59 CONFIG_SPI_FLASH_STMICRO=y 59 CONFIG_SPI_FLASH_STMICRO=y
60 CONFIG_CMD_SF=y 60 CONFIG_CMD_SF=y
61 61
62 CONFIG_CMD_PING=y 62 CONFIG_CMD_PING=y
63 CONFIG_CMD_DHCP=y 63 CONFIG_CMD_DHCP=y
64 CONFIG_CMD_MII=y 64 CONFIG_CMD_MII=y
65 CONFIG_DM_ETH=y 65 CONFIG_DM_ETH=y
66 # CONFIG_EFI_LOADER is not set 66 # CONFIG_EFI_LOADER is not set
67 67
68 CONFIG_DM_REGULATOR=y 68 CONFIG_DM_REGULATOR=y
69 CONFIG_DM_REGULATOR_FIXED=y 69 CONFIG_DM_REGULATOR_FIXED=y
70 CONFIG_DM_REGULATOR_GPIO=y 70 CONFIG_DM_REGULATOR_GPIO=y
71 71
72 CONFIG_VIDEO=y 72 CONFIG_VIDEO=y
73 CONFIG_VIDEO_IMX_HDP_LOAD=y 73 CONFIG_VIDEO_IMX_HDP_LOAD=y
74 74
75 CONFIG_PINCTRL=y 75 CONFIG_PINCTRL=y
76 CONFIG_PINCTRL_IMX8=y 76 CONFIG_PINCTRL_IMX8=y
77 77
78 CONFIG_POWER_DOMAIN=y 78 CONFIG_POWER_DOMAIN=y
79 CONFIG_IMX8_POWER_DOMAIN=y 79 CONFIG_IMX8_POWER_DOMAIN=y
80 80
81 CONFIG_DM_THERMAL=y 81 CONFIG_DM_THERMAL=y
82 CONFIG_IMX_SC_THERMAL=y 82 CONFIG_IMX_SC_THERMAL=y
83 83
84 CONFIG_ENV_IS_IN_SPI_FLASH=y 84 CONFIG_ENV_IS_IN_SPI_FLASH=y
85 85
86 CONFIG_SMC_FUSE=y 86 CONFIG_SMC_FUSE=y
87 CONFIG_CMD_MEMTEST=y 87 CONFIG_CMD_MEMTEST=y
88
89 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
90 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
88 91
configs/imx8qm_lpddr4_arm2_spl_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-lpddr4-arm2" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-lpddr4-arm2"
4 CONFIG_TARGET_IMX8QM_LPDDR4_ARM2=y 4 CONFIG_TARGET_IMX8QM_LPDDR4_ARM2=y
5 CONFIG_SYS_TEXT_BASE=0x80020000 5 CONFIG_SYS_TEXT_BASE=0x80020000
6 CONFIG_CMD_IMPORTENV=n 6 CONFIG_CMD_IMPORTENV=n
7 CONFIG_SYS_MALLOC_F_LEN=0x2000 7 CONFIG_SYS_MALLOC_F_LEN=0x2000
8 CONFIG_DM=y 8 CONFIG_DM=y
9 CONFIG_CMD_CACHE=y 9 CONFIG_CMD_CACHE=y
10 10
11 CONFIG_DM_SERIAL=y 11 CONFIG_DM_SERIAL=y
12 CONFIG_FSL_LPUART=y 12 CONFIG_FSL_LPUART=y
13 CONFIG_OF_CONTROL=y 13 CONFIG_OF_CONTROL=y
14 CONFIG_DM_I2C=y 14 CONFIG_DM_I2C=y
15 # CONFIG_DM_I2C_COMPAT is not set 15 # CONFIG_DM_I2C_COMPAT is not set
16 CONFIG_SYS_I2C_IMX_LPI2C=y 16 CONFIG_SYS_I2C_IMX_LPI2C=y
17 CONFIG_CMD_I2C=y 17 CONFIG_CMD_I2C=y
18 18
19 CONFIG_SPL=y 19 CONFIG_SPL=y
20 CONFIG_SPL_GPIO_SUPPORT=y 20 CONFIG_SPL_GPIO_SUPPORT=y
21 CONFIG_SPL_MMC_SUPPORT=y 21 CONFIG_SPL_MMC_SUPPORT=y
22 CONFIG_SPL_BOARD_INIT=y 22 CONFIG_SPL_BOARD_INIT=y
23 CONFIG_SPL_SYS_MALLOC_SIMPLE=y 23 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
24 CONFIG_SPL_TINY_MEMSET=y 24 CONFIG_SPL_TINY_MEMSET=y
25 CONFIG_SPL_OF_CONTROL=y 25 CONFIG_SPL_OF_CONTROL=y
26 26
27 CONFIG_USB_XHCI_HCD=y 27 CONFIG_USB_XHCI_HCD=y
28 CONFIG_USB_XHCI_IMX8=y 28 CONFIG_USB_XHCI_IMX8=y
29 29
30 CONFIG_DM_USB=y 30 CONFIG_DM_USB=y
31 CONFIG_USB_EHCI_HCD=y 31 CONFIG_USB_EHCI_HCD=y
32 32
33 CONFIG_CMD_USB=y 33 CONFIG_CMD_USB=y
34 CONFIG_USB=y 34 CONFIG_USB=y
35 CONFIG_USB_STORAGE=y 35 CONFIG_USB_STORAGE=y
36 36
37 CONFIG_CMD_USB_MASS_STORAGE=y 37 CONFIG_CMD_USB_MASS_STORAGE=y
38 CONFIG_USB_GADGET=y 38 CONFIG_USB_GADGET=y
39 # CONFIG_CI_UDC=y 39 # CONFIG_CI_UDC=y
40 CONFIG_USB_GADGET_DOWNLOAD=y 40 CONFIG_USB_GADGET_DOWNLOAD=y
41 CONFIG_USB_GADGET_MANUFACTURER="FSL" 41 CONFIG_USB_GADGET_MANUFACTURER="FSL"
42 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 42 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
43 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 43 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
44 44
45 CONFIG_USB_CDNS3=y 45 CONFIG_USB_CDNS3=y
46 CONFIG_USB_CDNS3_GADGET=y 46 CONFIG_USB_CDNS3_GADGET=y
47 CONFIG_USB_GADGET_DUALSPEED=y 47 CONFIG_USB_GADGET_DUALSPEED=y
48 48
49 CONFIG_CMD_GPIO=y 49 CONFIG_CMD_GPIO=y
50 CONFIG_DM_GPIO=y 50 CONFIG_DM_GPIO=y
51 CONFIG_DM_PCA953X=y 51 CONFIG_DM_PCA953X=y
52 CONFIG_BOOTDELAY=3 52 CONFIG_BOOTDELAY=3
53 CONFIG_IMX_BOOTAUX=y 53 CONFIG_IMX_BOOTAUX=y
54 CONFIG_FS_FAT=y 54 CONFIG_FS_FAT=y
55 CONFIG_CMD_FAT=y 55 CONFIG_CMD_FAT=y
56 CONFIG_CMD_MMC=y 56 CONFIG_CMD_MMC=y
57 CONFIG_DM_MMC=y 57 CONFIG_DM_MMC=y
58 CONFIG_MMC_IO_VOLTAGE=y 58 CONFIG_MMC_IO_VOLTAGE=y
59 CONFIG_MMC_UHS_SUPPORT=y 59 CONFIG_MMC_UHS_SUPPORT=y
60 CONFIG_MMC_HS400_SUPPORT=y 60 CONFIG_MMC_HS400_SUPPORT=y
61 CONFIG_FSL_FSPI=y 61 CONFIG_FSL_FSPI=y
62 CONFIG_DM_SPI=y 62 CONFIG_DM_SPI=y
63 CONFIG_DM_SPI_FLASH=y 63 CONFIG_DM_SPI_FLASH=y
64 CONFIG_SPI_FLASH=y 64 CONFIG_SPI_FLASH=y
65 CONFIG_SPI_FLASH_4BYTES_ADDR=y 65 CONFIG_SPI_FLASH_4BYTES_ADDR=y
66 CONFIG_SPI_FLASH_STMICRO=y 66 CONFIG_SPI_FLASH_STMICRO=y
67 CONFIG_CMD_SF=y 67 CONFIG_CMD_SF=y
68 68
69 CONFIG_CMD_PING=y 69 CONFIG_CMD_PING=y
70 CONFIG_CMD_DHCP=y 70 CONFIG_CMD_DHCP=y
71 CONFIG_CMD_MII=y 71 CONFIG_CMD_MII=y
72 CONFIG_DM_ETH=y 72 CONFIG_DM_ETH=y
73 # CONFIG_EFI_LOADER is not set 73 # CONFIG_EFI_LOADER is not set
74 74
75 CONFIG_DM_REGULATOR=y 75 CONFIG_DM_REGULATOR=y
76 CONFIG_DM_REGULATOR_FIXED=y 76 CONFIG_DM_REGULATOR_FIXED=y
77 CONFIG_DM_REGULATOR_GPIO=y 77 CONFIG_DM_REGULATOR_GPIO=y
78 78
79 CONFIG_VIDEO=y 79 CONFIG_VIDEO=y
80 CONFIG_VIDEO_IMX_HDP_LOAD=y 80 CONFIG_VIDEO_IMX_HDP_LOAD=y
81 81
82 CONFIG_PINCTRL=y 82 CONFIG_PINCTRL=y
83 CONFIG_PINCTRL_IMX8=y 83 CONFIG_PINCTRL_IMX8=y
84 84
85 CONFIG_POWER_DOMAIN=y 85 CONFIG_POWER_DOMAIN=y
86 CONFIG_IMX8_POWER_DOMAIN=y 86 CONFIG_IMX8_POWER_DOMAIN=y
87 87
88 CONFIG_DM_THERMAL=y 88 CONFIG_DM_THERMAL=y
89 CONFIG_IMX_SC_THERMAL=y 89 CONFIG_IMX_SC_THERMAL=y
90 90
91 CONFIG_ENV_IS_IN_MMC=y 91 CONFIG_ENV_IS_IN_MMC=y
92 92
93 CONFIG_SMC_FUSE=y 93 CONFIG_SMC_FUSE=y
94 CONFIG_CMD_MEMTEST=y 94 CONFIG_CMD_MEMTEST=y
95
96 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
97 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
95 98
configs/imx8qm_mek_android_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT" 4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT"
5 CONFIG_TARGET_IMX8QM_MEK=y 5 CONFIG_TARGET_IMX8QM_MEK=y
6 CONFIG_SYS_TEXT_BASE=0x80020000 6 CONFIG_SYS_TEXT_BASE=0x80020000
7 CONFIG_EFI_PARTITION=y 7 CONFIG_EFI_PARTITION=y
8 CONFIG_CMD_IMPORTENV=n 8 CONFIG_CMD_IMPORTENV=n
9 CONFIG_SYS_MALLOC_F_LEN=0x2000 9 CONFIG_SYS_MALLOC_F_LEN=0x2000
10 CONFIG_DM=y 10 CONFIG_DM=y
11 CONFIG_CMD_CACHE=y 11 CONFIG_CMD_CACHE=y
12 12
13 CONFIG_DM_SERIAL=y 13 CONFIG_DM_SERIAL=y
14 CONFIG_FSL_LPUART=y 14 CONFIG_FSL_LPUART=y
15 CONFIG_OF_CONTROL=y 15 CONFIG_OF_CONTROL=y
16 CONFIG_DM_I2C=y 16 CONFIG_DM_I2C=y
17 # CONFIG_DM_I2C_COMPAT is not set 17 # CONFIG_DM_I2C_COMPAT is not set
18 CONFIG_SYS_I2C_IMX_LPI2C=y 18 CONFIG_SYS_I2C_IMX_LPI2C=y
19 CONFIG_CMD_I2C=y 19 CONFIG_CMD_I2C=y
20 20
21 CONFIG_USB_XHCI_HCD=y 21 CONFIG_USB_XHCI_HCD=y
22 CONFIG_USB_XHCI_IMX8=y 22 CONFIG_USB_XHCI_IMX8=y
23 23
24 CONFIG_DM_USB=y 24 CONFIG_DM_USB=y
25 25
26 CONFIG_USB=y 26 CONFIG_USB=y
27 CONFIG_USB_TCPC=y 27 CONFIG_USB_TCPC=y
28 28
29 CONFIG_USB_GADGET=y 29 CONFIG_USB_GADGET=y
30 # CONFIG_CI_UDC=y 30 # CONFIG_CI_UDC=y
31 CONFIG_USB_GADGET_DOWNLOAD=y 31 CONFIG_USB_GADGET_DOWNLOAD=y
32 CONFIG_USB_GADGET_MANUFACTURER="FSL" 32 CONFIG_USB_GADGET_MANUFACTURER="FSL"
33 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 33 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
34 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 34 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02
35 35
36 CONFIG_USB_CDNS3=y 36 CONFIG_USB_CDNS3=y
37 CONFIG_USB_CDNS3_GADGET=y 37 CONFIG_USB_CDNS3_GADGET=y
38 CONFIG_USB_GADGET_DUALSPEED=y 38 CONFIG_USB_GADGET_DUALSPEED=y
39 39
40 CONFIG_CMD_GPIO=y 40 CONFIG_CMD_GPIO=y
41 CONFIG_DM_GPIO=y 41 CONFIG_DM_GPIO=y
42 CONFIG_DM_PCA953X=y 42 CONFIG_DM_PCA953X=y
43 CONFIG_BOOTDELAY=1 43 CONFIG_BOOTDELAY=1
44 CONFIG_IMX_BOOTAUX=y 44 CONFIG_IMX_BOOTAUX=y
45 CONFIG_FS_FAT=y 45 CONFIG_FS_FAT=y
46 CONFIG_CMD_FAT=y 46 CONFIG_CMD_FAT=y
47 CONFIG_CMD_MMC=y 47 CONFIG_CMD_MMC=y
48 CONFIG_DM_MMC=y 48 CONFIG_DM_MMC=y
49 CONFIG_MMC_IO_VOLTAGE=y 49 CONFIG_MMC_IO_VOLTAGE=y
50 CONFIG_MMC_UHS_SUPPORT=y 50 CONFIG_MMC_UHS_SUPPORT=y
51 CONFIG_MMC_HS400_SUPPORT=y 51 CONFIG_MMC_HS400_SUPPORT=y
52 CONFIG_FSL_FSPI=y 52 CONFIG_FSL_FSPI=y
53 CONFIG_DM_SPI=y 53 CONFIG_DM_SPI=y
54 CONFIG_DM_SPI_FLASH=y 54 CONFIG_DM_SPI_FLASH=y
55 CONFIG_SPI_FLASH=y 55 CONFIG_SPI_FLASH=y
56 CONFIG_SPI_FLASH_4BYTES_ADDR=y 56 CONFIG_SPI_FLASH_4BYTES_ADDR=y
57 CONFIG_SPI_FLASH_STMICRO=y 57 CONFIG_SPI_FLASH_STMICRO=y
58 CONFIG_CMD_SF=y 58 CONFIG_CMD_SF=y
59 59
60 CONFIG_CMD_PING=y 60 CONFIG_CMD_PING=y
61 CONFIG_CMD_DHCP=y 61 CONFIG_CMD_DHCP=y
62 CONFIG_CMD_MII=y 62 CONFIG_CMD_MII=y
63 CONFIG_DM_ETH=y 63 CONFIG_DM_ETH=y
64 # CONFIG_EFI_LOADER is not set 64 # CONFIG_EFI_LOADER is not set
65 65
66 CONFIG_DM_REGULATOR=y 66 CONFIG_DM_REGULATOR=y
67 CONFIG_DM_REGULATOR_FIXED=y 67 CONFIG_DM_REGULATOR_FIXED=y
68 CONFIG_DM_REGULATOR_GPIO=y 68 CONFIG_DM_REGULATOR_GPIO=y
69 69
70 CONFIG_VIDEO=y 70 CONFIG_VIDEO=y
71 CONFIG_VIDEO_IMX_HDP_LOAD=y 71 CONFIG_VIDEO_IMX_HDP_LOAD=y
72 72
73 CONFIG_PINCTRL=y 73 CONFIG_PINCTRL=y
74 CONFIG_PINCTRL_IMX8=y 74 CONFIG_PINCTRL_IMX8=y
75 75
76 CONFIG_POWER_DOMAIN=y 76 CONFIG_POWER_DOMAIN=y
77 CONFIG_IMX8_POWER_DOMAIN=y 77 CONFIG_IMX8_POWER_DOMAIN=y
78 78
79 CONFIG_DM_THERMAL=y 79 CONFIG_DM_THERMAL=y
80 CONFIG_IMX_SC_THERMAL=y 80 CONFIG_IMX_SC_THERMAL=y
81 81
82 CONFIG_ENV_IS_IN_MMC=y 82 CONFIG_ENV_IS_IN_MMC=y
83 CONFIG_LZ4=y 83 CONFIG_LZ4=y
84 84
85 CONFIG_SMC_FUSE=y 85 CONFIG_SMC_FUSE=y
86 CONFIG_CMD_MEMTEST=y 86 CONFIG_CMD_MEMTEST=y
87 87
88 CONFIG_SPL=y 88 CONFIG_SPL=y
89 CONFIG_SPL_MMC_SUPPORT=y 89 CONFIG_SPL_MMC_SUPPORT=y
90 CONFIG_SPL_GPIO_SUPPORT=y 90 CONFIG_SPL_GPIO_SUPPORT=y
91 91
92 CONFIG_NOT_UUU_BUILD=y 92 CONFIG_NOT_UUU_BUILD=y
93 CONFIG_APPEND_BOOTARGS=y 93 CONFIG_APPEND_BOOTARGS=y
94
95 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
96 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000
94 97
configs/imx8qm_mek_android_uuu_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT" 4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT"
5 CONFIG_TARGET_IMX8QM_MEK=y 5 CONFIG_TARGET_IMX8QM_MEK=y
6 CONFIG_SYS_TEXT_BASE=0x80020000 6 CONFIG_SYS_TEXT_BASE=0x80020000
7 CONFIG_EFI_PARTITION=y 7 CONFIG_EFI_PARTITION=y
8 CONFIG_CMD_IMPORTENV=n 8 CONFIG_CMD_IMPORTENV=n
9 CONFIG_SYS_MALLOC_F_LEN=0x2000 9 CONFIG_SYS_MALLOC_F_LEN=0x2000
10 CONFIG_DM=y 10 CONFIG_DM=y
11 CONFIG_CMD_CACHE=y 11 CONFIG_CMD_CACHE=y
12 12
13 CONFIG_DM_SERIAL=y 13 CONFIG_DM_SERIAL=y
14 CONFIG_FSL_LPUART=y 14 CONFIG_FSL_LPUART=y
15 CONFIG_OF_CONTROL=y 15 CONFIG_OF_CONTROL=y
16 CONFIG_DM_I2C=y 16 CONFIG_DM_I2C=y
17 # CONFIG_DM_I2C_COMPAT is not set 17 # CONFIG_DM_I2C_COMPAT is not set
18 CONFIG_SYS_I2C_IMX_LPI2C=y 18 CONFIG_SYS_I2C_IMX_LPI2C=y
19 CONFIG_CMD_I2C=y 19 CONFIG_CMD_I2C=y
20 20
21 CONFIG_USB_XHCI_HCD=y 21 CONFIG_USB_XHCI_HCD=y
22 CONFIG_USB_XHCI_IMX8=y 22 CONFIG_USB_XHCI_IMX8=y
23 23
24 CONFIG_DM_USB=y 24 CONFIG_DM_USB=y
25 25
26 CONFIG_USB=y 26 CONFIG_USB=y
27 CONFIG_USB_TCPC=y 27 CONFIG_USB_TCPC=y
28 28
29 CONFIG_USB_GADGET=y 29 CONFIG_USB_GADGET=y
30 # CONFIG_CI_UDC=y 30 # CONFIG_CI_UDC=y
31 CONFIG_USB_GADGET_DOWNLOAD=y 31 CONFIG_USB_GADGET_DOWNLOAD=y
32 CONFIG_USB_GADGET_MANUFACTURER="FSL" 32 CONFIG_USB_GADGET_MANUFACTURER="FSL"
33 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 33 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
34 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 34 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02
35 35
36 CONFIG_USB_CDNS3=y 36 CONFIG_USB_CDNS3=y
37 CONFIG_USB_CDNS3_GADGET=y 37 CONFIG_USB_CDNS3_GADGET=y
38 CONFIG_USB_GADGET_DUALSPEED=y 38 CONFIG_USB_GADGET_DUALSPEED=y
39 39
40 CONFIG_CMD_GPIO=y 40 CONFIG_CMD_GPIO=y
41 CONFIG_DM_GPIO=y 41 CONFIG_DM_GPIO=y
42 CONFIG_DM_PCA953X=y 42 CONFIG_DM_PCA953X=y
43 CONFIG_BOOTDELAY=1 43 CONFIG_BOOTDELAY=1
44 CONFIG_IMX_BOOTAUX=y 44 CONFIG_IMX_BOOTAUX=y
45 CONFIG_FS_FAT=y 45 CONFIG_FS_FAT=y
46 CONFIG_CMD_FAT=y 46 CONFIG_CMD_FAT=y
47 CONFIG_CMD_MMC=y 47 CONFIG_CMD_MMC=y
48 CONFIG_DM_MMC=y 48 CONFIG_DM_MMC=y
49 CONFIG_MMC_IO_VOLTAGE=y 49 CONFIG_MMC_IO_VOLTAGE=y
50 CONFIG_MMC_UHS_SUPPORT=y 50 CONFIG_MMC_UHS_SUPPORT=y
51 CONFIG_MMC_HS400_SUPPORT=y 51 CONFIG_MMC_HS400_SUPPORT=y
52 CONFIG_FSL_FSPI=y 52 CONFIG_FSL_FSPI=y
53 CONFIG_DM_SPI=y 53 CONFIG_DM_SPI=y
54 CONFIG_DM_SPI_FLASH=y 54 CONFIG_DM_SPI_FLASH=y
55 CONFIG_SPI_FLASH=y 55 CONFIG_SPI_FLASH=y
56 CONFIG_SPI_FLASH_4BYTES_ADDR=y 56 CONFIG_SPI_FLASH_4BYTES_ADDR=y
57 CONFIG_SPI_FLASH_STMICRO=y 57 CONFIG_SPI_FLASH_STMICRO=y
58 CONFIG_CMD_SF=y 58 CONFIG_CMD_SF=y
59 59
60 CONFIG_CMD_PING=y 60 CONFIG_CMD_PING=y
61 CONFIG_CMD_DHCP=y 61 CONFIG_CMD_DHCP=y
62 CONFIG_CMD_MII=y 62 CONFIG_CMD_MII=y
63 CONFIG_DM_ETH=y 63 CONFIG_DM_ETH=y
64 # CONFIG_EFI_LOADER is not set 64 # CONFIG_EFI_LOADER is not set
65 65
66 CONFIG_DM_REGULATOR=y 66 CONFIG_DM_REGULATOR=y
67 CONFIG_DM_REGULATOR_FIXED=y 67 CONFIG_DM_REGULATOR_FIXED=y
68 CONFIG_DM_REGULATOR_GPIO=y 68 CONFIG_DM_REGULATOR_GPIO=y
69 69
70 CONFIG_VIDEO=y 70 CONFIG_VIDEO=y
71 CONFIG_VIDEO_IMX_HDP_LOAD=y 71 CONFIG_VIDEO_IMX_HDP_LOAD=y
72 72
73 CONFIG_PINCTRL=y 73 CONFIG_PINCTRL=y
74 CONFIG_PINCTRL_IMX8=y 74 CONFIG_PINCTRL_IMX8=y
75 75
76 CONFIG_POWER_DOMAIN=y 76 CONFIG_POWER_DOMAIN=y
77 CONFIG_IMX8_POWER_DOMAIN=y 77 CONFIG_IMX8_POWER_DOMAIN=y
78 78
79 CONFIG_DM_THERMAL=y 79 CONFIG_DM_THERMAL=y
80 CONFIG_IMX_SC_THERMAL=y 80 CONFIG_IMX_SC_THERMAL=y
81 81
82 CONFIG_ENV_IS_IN_MMC=y 82 CONFIG_ENV_IS_IN_MMC=y
83 CONFIG_LZ4=y 83 CONFIG_LZ4=y
84 84
85 CONFIG_SMC_FUSE=y 85 CONFIG_SMC_FUSE=y
86 CONFIG_CMD_MEMTEST=y 86 CONFIG_CMD_MEMTEST=y
87
88 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
89 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
87 90
configs/imx8qm_mek_androidauto2_trusty_defconfig
Diff comments   View file @ 57fa56f
File was created 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-auto"
4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT"
5 CONFIG_TARGET_IMX8QM_MEK=y
6 CONFIG_SYS_TEXT_BASE=0x80020000
7 CONFIG_EFI_PARTITION=y
8 CONFIG_CMD_IMPORTENV=n
9 CONFIG_SYS_MALLOC_F_LEN=0x2000
10 CONFIG_DM=y
11 CONFIG_DM_WARN=n
12 CONFIG_DM_DEVICE_REMOVE=n
13 CONFIG_IMX_TRUSTY_OS=y
14
15 CONFIG_DM_SERIAL=y
16 CONFIG_FSL_LPUART=y
17 CONFIG_OF_CONTROL=y
18 CONFIG_DM_I2C=y
19 # CONFIG_DM_I2C_COMPAT is not set
20 CONFIG_SYS_I2C_IMX_LPI2C=y
21 CONFIG_CMD_I2C=n
22
23 CONFIG_USB_XHCI_HCD=y
24 CONFIG_USB_XHCI_IMX8=y
25
26 CONFIG_DM_USB=y
27
28 CONFIG_USB=y
29
30 CONFIG_USB_GADGET=y
31 #CONFIG_CI_UDC=y
32 CONFIG_USB_GADGET_DOWNLOAD=y
33 CONFIG_USB_GADGET_MANUFACTURER="FSL"
34 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
35 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02
36
37 CONFIG_USB_CDNS3=y
38 CONFIG_USB_CDNS3_GADGET=y
39 CONFIG_USB_GADGET_DUALSPEED=y
40
41 CONFIG_DM_GPIO=y
42 CONFIG_DM_PCA953X=y
43 CONFIG_BOOTDELAY=1
44 CONFIG_CMD_MMC=y
45 CONFIG_DM_MMC=y
46 CONFIG_MMC_IO_VOLTAGE=y
47 CONFIG_MMC_UHS_SUPPORT=y
48 CONFIG_MMC_HS400_SUPPORT=y
49 CONFIG_FSL_FSPI=y
50 CONFIG_DM_SPI=y
51 CONFIG_DM_SPI_FLASH=y
52 CONFIG_SPI_FLASH=y
53 CONFIG_SPI_FLASH_4BYTES_ADDR=y
54 CONFIG_SPI_FLASH_STMICRO=y
55
56 CONFIG_DM_REGULATOR=y
57 CONFIG_DM_REGULATOR_FIXED=y
58 CONFIG_DM_REGULATOR_GPIO=y
59
60 CONFIG_PINCTRL=y
61 CONFIG_PINCTRL_IMX8=y
62
63 CONFIG_CMD_NET=n
64 CONFIG_CMD_NFS=n
65 CONFIG_CMD_BDI=n
66 CONFIG_CMD_CONSOLE=n
67 CONFIG_CMD_BOOTD=n
68 CONFIG_CMD_BOOTEFI=n
69 CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n
70 CONFIG_CMD_ELF=n
71 CONFIG_CMD_GO=n
72 CONFIG_CMD_RUN=n
73 CONFIG_CMD_IMI=n
74 CONFIG_CMD_IMLS=n
75 CONFIG_CMD_XIMG=n
76 CONFIG_CMD_EXPORTENV=n
77 CONFIG_CMD_IMPORTENV=n
78 CONFIG_CMD_EDITENV=n
79 CONFIG_CMD_ENV_EXISTS=n
80 CONFIG_CMD_CRC32=n
81 CONFIG_CMD_DM=n
82 CONFIG_CMD_LOADB=n
83 CONFIG_CMD_LOADS=n
84 CONFIG_CMD_FLASH=n
85 CONFIG_CMD_GPT=n
86 CONFIG_CMD_FPGA=n
87 CONFIG_CMD_ECHO=n
88 CONFIG_CMD_ITEST=n
89 CONFIG_CMD_SOURCE=n
90 CONFIG_CMD_SETEXPR=n
91 CONFIG_CMD_MISC=n
92 CONFIG_CMD_UNZIP=n
93 CONFIG_CMD_LZMADEC=n
94 CONFIG_CMD_SAVEENV=n
95
96 CONFIG_DISPLAY_CPUINFO=n
97 CONFIG_DISPLAY_BOARDINFO=n
98 CONFIG_EFI_LOADER=n
99
100 CONFIG_POWER_DOMAIN=y
101 CONFIG_IMX8_POWER_DOMAIN=y
102
103 CONFIG_DM_THERMAL=y
104 CONFIG_IMX_SC_THERMAL=y
105
106 CONFIG_ENV_IS_IN_MMC=y
107 CONFIG_LZ4=y
108
109 CONFIG_SMC_FUSE=y
110 CONFIG_CMD_MEMTEST=y
111
112 CONFIG_SPL=y
113 CONFIG_SPL_MMC_SUPPORT=y
114 CONFIG_SPL_GPIO_SUPPORT=y
115
116 CONFIG_SPL_ENV_SUPPORT=y
117 CONFIG_SPL_LIBDISK_SUPPORT=y
118
119 CONFIG_NOT_UUU_BUILD=y
120 CONFIG_SHA256=y
121 CONFIG_SPL_MMC_WRITE=y
122 CONFIG_DUAL_BOOTLOADER=y
123 CONFIG_APPEND_BOOTARGS=y
124
125 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
126 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000
127
configs/imx8qm_mek_androidauto_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-auto" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-auto"
4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT" 4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT"
5 CONFIG_TARGET_IMX8QM_MEK=y 5 CONFIG_TARGET_IMX8QM_MEK=y
6 CONFIG_SYS_TEXT_BASE=0x80020000 6 CONFIG_SYS_TEXT_BASE=0x80020000
7 CONFIG_EFI_PARTITION=y 7 CONFIG_EFI_PARTITION=y
8 CONFIG_CMD_IMPORTENV=n 8 CONFIG_CMD_IMPORTENV=n
9 CONFIG_SYS_MALLOC_F_LEN=0x2000 9 CONFIG_SYS_MALLOC_F_LEN=0x2000
10 CONFIG_DM=y 10 CONFIG_DM=y
11 CONFIG_DM_WARN=n 11 CONFIG_DM_WARN=n
12 CONFIG_DM_DEVICE_REMOVE=n 12 CONFIG_DM_DEVICE_REMOVE=n
13 13
14 CONFIG_DM_SERIAL=y 14 CONFIG_DM_SERIAL=y
15 CONFIG_FSL_LPUART=y 15 CONFIG_FSL_LPUART=y
16 CONFIG_OF_CONTROL=y 16 CONFIG_OF_CONTROL=y
17 CONFIG_DM_I2C=y 17 CONFIG_DM_I2C=y
18 # CONFIG_DM_I2C_COMPAT is not set 18 # CONFIG_DM_I2C_COMPAT is not set
19 CONFIG_SYS_I2C_IMX_LPI2C=y 19 CONFIG_SYS_I2C_IMX_LPI2C=y
20 CONFIG_CMD_I2C=n 20 CONFIG_CMD_I2C=n
21 21
22 CONFIG_USB_XHCI_HCD=y 22 CONFIG_USB_XHCI_HCD=y
23 CONFIG_USB_XHCI_IMX8=y 23 CONFIG_USB_XHCI_IMX8=y
24 24
25 CONFIG_DM_USB=y 25 CONFIG_DM_USB=y
26 26
27 CONFIG_USB=y 27 CONFIG_USB=y
28 28
29 CONFIG_USB_GADGET=y 29 CONFIG_USB_GADGET=y
30 #CONFIG_CI_UDC=y 30 #CONFIG_CI_UDC=y
31 CONFIG_USB_GADGET_DOWNLOAD=y 31 CONFIG_USB_GADGET_DOWNLOAD=y
32 CONFIG_USB_GADGET_MANUFACTURER="FSL" 32 CONFIG_USB_GADGET_MANUFACTURER="FSL"
33 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 33 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
34 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 34 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02
35 35
36 CONFIG_USB_CDNS3=y 36 CONFIG_USB_CDNS3=y
37 CONFIG_USB_CDNS3_GADGET=y 37 CONFIG_USB_CDNS3_GADGET=y
38 CONFIG_USB_GADGET_DUALSPEED=y 38 CONFIG_USB_GADGET_DUALSPEED=y
39 39
40 CONFIG_DM_GPIO=y 40 CONFIG_DM_GPIO=y
41 CONFIG_DM_PCA953X=y 41 CONFIG_DM_PCA953X=y
42 CONFIG_BOOTDELAY=1 42 CONFIG_BOOTDELAY=1
43 CONFIG_CMD_MMC=y 43 CONFIG_CMD_MMC=y
44 CONFIG_DM_MMC=y 44 CONFIG_DM_MMC=y
45 CONFIG_MMC_IO_VOLTAGE=y 45 CONFIG_MMC_IO_VOLTAGE=y
46 CONFIG_MMC_UHS_SUPPORT=y 46 CONFIG_MMC_UHS_SUPPORT=y
47 CONFIG_MMC_HS400_SUPPORT=y 47 CONFIG_MMC_HS400_SUPPORT=y
48 CONFIG_FSL_FSPI=y 48 CONFIG_FSL_FSPI=y
49 CONFIG_DM_SPI=y 49 CONFIG_DM_SPI=y
50 CONFIG_DM_SPI_FLASH=y 50 CONFIG_DM_SPI_FLASH=y
51 CONFIG_SPI_FLASH=y 51 CONFIG_SPI_FLASH=y
52 CONFIG_SPI_FLASH_4BYTES_ADDR=y 52 CONFIG_SPI_FLASH_4BYTES_ADDR=y
53 CONFIG_SPI_FLASH_STMICRO=y 53 CONFIG_SPI_FLASH_STMICRO=y
54 54
55 CONFIG_DM_REGULATOR=y 55 CONFIG_DM_REGULATOR=y
56 CONFIG_DM_REGULATOR_FIXED=y 56 CONFIG_DM_REGULATOR_FIXED=y
57 CONFIG_DM_REGULATOR_GPIO=y 57 CONFIG_DM_REGULATOR_GPIO=y
58 58
59 CONFIG_PINCTRL=y 59 CONFIG_PINCTRL=y
60 CONFIG_PINCTRL_IMX8=y 60 CONFIG_PINCTRL_IMX8=y
61 61
62 CONFIG_CMD_NET=n 62 CONFIG_CMD_NET=n
63 CONFIG_CMD_NFS=n 63 CONFIG_CMD_NFS=n
64 CONFIG_CMD_BDI=n 64 CONFIG_CMD_BDI=n
65 CONFIG_CMD_CONSOLE=n 65 CONFIG_CMD_CONSOLE=n
66 CONFIG_CMD_BOOTD=n 66 CONFIG_CMD_BOOTD=n
67 CONFIG_CMD_BOOTEFI=n 67 CONFIG_CMD_BOOTEFI=n
68 CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n 68 CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n
69 CONFIG_CMD_ELF=n 69 CONFIG_CMD_ELF=n
70 CONFIG_CMD_GO=n 70 CONFIG_CMD_GO=n
71 CONFIG_CMD_RUN=n 71 CONFIG_CMD_RUN=n
72 CONFIG_CMD_IMI=n 72 CONFIG_CMD_IMI=n
73 CONFIG_CMD_IMLS=n 73 CONFIG_CMD_IMLS=n
74 CONFIG_CMD_XIMG=n 74 CONFIG_CMD_XIMG=n
75 CONFIG_CMD_EXPORTENV=n 75 CONFIG_CMD_EXPORTENV=n
76 CONFIG_CMD_IMPORTENV=n 76 CONFIG_CMD_IMPORTENV=n
77 CONFIG_CMD_EDITENV=n 77 CONFIG_CMD_EDITENV=n
78 CONFIG_CMD_ENV_EXISTS=n 78 CONFIG_CMD_ENV_EXISTS=n
79 CONFIG_CMD_CRC32=n 79 CONFIG_CMD_CRC32=n
80 CONFIG_CMD_DM=n 80 CONFIG_CMD_DM=n
81 CONFIG_CMD_LOADB=n 81 CONFIG_CMD_LOADB=n
82 CONFIG_CMD_LOADS=n 82 CONFIG_CMD_LOADS=n
83 CONFIG_CMD_FLASH=n 83 CONFIG_CMD_FLASH=n
84 CONFIG_CMD_GPT=n 84 CONFIG_CMD_GPT=n
85 CONFIG_CMD_FPGA=n 85 CONFIG_CMD_FPGA=n
86 CONFIG_CMD_ECHO=n 86 CONFIG_CMD_ECHO=n
87 CONFIG_CMD_ITEST=n 87 CONFIG_CMD_ITEST=n
88 CONFIG_CMD_SOURCE=n 88 CONFIG_CMD_SOURCE=n
89 CONFIG_CMD_SETEXPR=n 89 CONFIG_CMD_SETEXPR=n
90 CONFIG_CMD_MISC=n 90 CONFIG_CMD_MISC=n
91 CONFIG_CMD_UNZIP=n 91 CONFIG_CMD_UNZIP=n
92 CONFIG_CMD_LZMADEC=n 92 CONFIG_CMD_LZMADEC=n
93 CONFIG_CMD_SAVEENV=n 93 CONFIG_CMD_SAVEENV=n
94 94
95 CONFIG_DISPLAY_CPUINFO=n 95 CONFIG_DISPLAY_CPUINFO=n
96 CONFIG_DISPLAY_BOARDINFO=n 96 CONFIG_DISPLAY_BOARDINFO=n
97 CONFIG_EFI_LOADER=n 97 CONFIG_EFI_LOADER=n
98 98
99 CONFIG_POWER_DOMAIN=y 99 CONFIG_POWER_DOMAIN=y
100 CONFIG_IMX8_POWER_DOMAIN=y 100 CONFIG_IMX8_POWER_DOMAIN=y
101 101
102 CONFIG_DM_THERMAL=y 102 CONFIG_DM_THERMAL=y
103 CONFIG_IMX_SC_THERMAL=y 103 CONFIG_IMX_SC_THERMAL=y
104 104
105 CONFIG_ENV_IS_IN_MMC=y 105 CONFIG_ENV_IS_IN_MMC=y
106 CONFIG_LZ4=y 106 CONFIG_LZ4=y
107 107
108 CONFIG_SMC_FUSE=y 108 CONFIG_SMC_FUSE=y
109 CONFIG_CMD_MEMTEST=y 109 CONFIG_CMD_MEMTEST=y
110 110
111 CONFIG_SPL=y 111 CONFIG_SPL=y
112 CONFIG_SPL_MMC_SUPPORT=y 112 CONFIG_SPL_MMC_SUPPORT=y
113 CONFIG_SPL_GPIO_SUPPORT=y 113 CONFIG_SPL_GPIO_SUPPORT=y
114
115 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
116 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
114 117
configs/imx8qm_mek_androidauto_trusty_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-auto" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-auto"
4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT" 4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT"
5 CONFIG_TARGET_IMX8QM_MEK=y 5 CONFIG_TARGET_IMX8QM_MEK=y
6 CONFIG_SYS_TEXT_BASE=0x80020000 6 CONFIG_SYS_TEXT_BASE=0x80020000
7 CONFIG_EFI_PARTITION=y 7 CONFIG_EFI_PARTITION=y
8 CONFIG_CMD_IMPORTENV=n 8 CONFIG_CMD_IMPORTENV=n
9 CONFIG_SYS_MALLOC_F_LEN=0x2000 9 CONFIG_SYS_MALLOC_F_LEN=0x2000
10 CONFIG_DM=y 10 CONFIG_DM=y
11 CONFIG_DM_WARN=n 11 CONFIG_DM_WARN=n
12 CONFIG_DM_DEVICE_REMOVE=n 12 CONFIG_DM_DEVICE_REMOVE=n
13 CONFIG_IMX_TRUSTY_OS=y 13 CONFIG_IMX_TRUSTY_OS=y
14 14
15 CONFIG_DM_SERIAL=y 15 CONFIG_DM_SERIAL=y
16 CONFIG_FSL_LPUART=y 16 CONFIG_FSL_LPUART=y
17 CONFIG_OF_CONTROL=y 17 CONFIG_OF_CONTROL=y
18 CONFIG_DM_I2C=y 18 CONFIG_DM_I2C=y
19 # CONFIG_DM_I2C_COMPAT is not set 19 # CONFIG_DM_I2C_COMPAT is not set
20 CONFIG_SYS_I2C_IMX_LPI2C=y 20 CONFIG_SYS_I2C_IMX_LPI2C=y
21 CONFIG_CMD_I2C=n 21 CONFIG_CMD_I2C=n
22 22
23 CONFIG_USB_XHCI_HCD=y 23 CONFIG_USB_XHCI_HCD=y
24 CONFIG_USB_XHCI_IMX8=y 24 CONFIG_USB_XHCI_IMX8=y
25 25
26 CONFIG_DM_USB=y 26 CONFIG_DM_USB=y
27 27
28 CONFIG_USB=y 28 CONFIG_USB=y
29 29
30 CONFIG_USB_GADGET=y 30 CONFIG_USB_GADGET=y
31 #CONFIG_CI_UDC=y 31 #CONFIG_CI_UDC=y
32 CONFIG_USB_GADGET_DOWNLOAD=y 32 CONFIG_USB_GADGET_DOWNLOAD=y
33 CONFIG_USB_GADGET_MANUFACTURER="FSL" 33 CONFIG_USB_GADGET_MANUFACTURER="FSL"
34 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 34 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
35 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 35 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02
36 36
37 CONFIG_USB_CDNS3=y 37 CONFIG_USB_CDNS3=y
38 CONFIG_USB_CDNS3_GADGET=y 38 CONFIG_USB_CDNS3_GADGET=y
39 CONFIG_USB_GADGET_DUALSPEED=y 39 CONFIG_USB_GADGET_DUALSPEED=y
40 40
41 CONFIG_DM_GPIO=y 41 CONFIG_DM_GPIO=y
42 CONFIG_DM_PCA953X=y 42 CONFIG_DM_PCA953X=y
43 CONFIG_BOOTDELAY=1 43 CONFIG_BOOTDELAY=1
44 CONFIG_CMD_MMC=y 44 CONFIG_CMD_MMC=y
45 CONFIG_DM_MMC=y 45 CONFIG_DM_MMC=y
46 CONFIG_MMC_IO_VOLTAGE=y 46 CONFIG_MMC_IO_VOLTAGE=y
47 CONFIG_MMC_UHS_SUPPORT=y 47 CONFIG_MMC_UHS_SUPPORT=y
48 CONFIG_MMC_HS400_SUPPORT=y 48 CONFIG_MMC_HS400_SUPPORT=y
49 CONFIG_FSL_FSPI=y 49 CONFIG_FSL_FSPI=y
50 CONFIG_DM_SPI=y 50 CONFIG_DM_SPI=y
51 CONFIG_DM_SPI_FLASH=y 51 CONFIG_DM_SPI_FLASH=y
52 CONFIG_SPI_FLASH=y 52 CONFIG_SPI_FLASH=y
53 CONFIG_SPI_FLASH_4BYTES_ADDR=y 53 CONFIG_SPI_FLASH_4BYTES_ADDR=y
54 CONFIG_SPI_FLASH_STMICRO=y 54 CONFIG_SPI_FLASH_STMICRO=y
55 55
56 CONFIG_DM_REGULATOR=y 56 CONFIG_DM_REGULATOR=y
57 CONFIG_DM_REGULATOR_FIXED=y 57 CONFIG_DM_REGULATOR_FIXED=y
58 CONFIG_DM_REGULATOR_GPIO=y 58 CONFIG_DM_REGULATOR_GPIO=y
59 59
60 CONFIG_PINCTRL=y 60 CONFIG_PINCTRL=y
61 CONFIG_PINCTRL_IMX8=y 61 CONFIG_PINCTRL_IMX8=y
62 62
63 CONFIG_CMD_NET=n 63 CONFIG_CMD_NET=n
64 CONFIG_CMD_NFS=n 64 CONFIG_CMD_NFS=n
65 CONFIG_CMD_BDI=n 65 CONFIG_CMD_BDI=n
66 CONFIG_CMD_CONSOLE=n 66 CONFIG_CMD_CONSOLE=n
67 CONFIG_CMD_BOOTD=n 67 CONFIG_CMD_BOOTD=n
68 CONFIG_CMD_BOOTEFI=n 68 CONFIG_CMD_BOOTEFI=n
69 CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n 69 CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n
70 CONFIG_CMD_ELF=n 70 CONFIG_CMD_ELF=n
71 CONFIG_CMD_GO=n 71 CONFIG_CMD_GO=n
72 CONFIG_CMD_RUN=n 72 CONFIG_CMD_RUN=n
73 CONFIG_CMD_IMI=n 73 CONFIG_CMD_IMI=n
74 CONFIG_CMD_IMLS=n 74 CONFIG_CMD_IMLS=n
75 CONFIG_CMD_XIMG=n 75 CONFIG_CMD_XIMG=n
76 CONFIG_CMD_EXPORTENV=n 76 CONFIG_CMD_EXPORTENV=n
77 CONFIG_CMD_IMPORTENV=n 77 CONFIG_CMD_IMPORTENV=n
78 CONFIG_CMD_EDITENV=n 78 CONFIG_CMD_EDITENV=n
79 CONFIG_CMD_ENV_EXISTS=n 79 CONFIG_CMD_ENV_EXISTS=n
80 CONFIG_CMD_CRC32=n 80 CONFIG_CMD_CRC32=n
81 CONFIG_CMD_DM=n 81 CONFIG_CMD_DM=n
82 CONFIG_CMD_LOADB=n 82 CONFIG_CMD_LOADB=n
83 CONFIG_CMD_LOADS=n 83 CONFIG_CMD_LOADS=n
84 CONFIG_CMD_FLASH=n 84 CONFIG_CMD_FLASH=n
85 CONFIG_CMD_GPT=n 85 CONFIG_CMD_GPT=n
86 CONFIG_CMD_FPGA=n 86 CONFIG_CMD_FPGA=n
87 CONFIG_CMD_ECHO=n 87 CONFIG_CMD_ECHO=n
88 CONFIG_CMD_ITEST=n 88 CONFIG_CMD_ITEST=n
89 CONFIG_CMD_SOURCE=n 89 CONFIG_CMD_SOURCE=n
90 CONFIG_CMD_SETEXPR=n 90 CONFIG_CMD_SETEXPR=n
91 CONFIG_CMD_MISC=n 91 CONFIG_CMD_MISC=n
92 CONFIG_CMD_UNZIP=n 92 CONFIG_CMD_UNZIP=n
93 CONFIG_CMD_LZMADEC=n 93 CONFIG_CMD_LZMADEC=n
94 CONFIG_CMD_SAVEENV=n 94 CONFIG_CMD_SAVEENV=n
95 95
96 CONFIG_DISPLAY_CPUINFO=n 96 CONFIG_DISPLAY_CPUINFO=n
97 CONFIG_DISPLAY_BOARDINFO=n 97 CONFIG_DISPLAY_BOARDINFO=n
98 CONFIG_EFI_LOADER=n 98 CONFIG_EFI_LOADER=n
99 99
100 CONFIG_POWER_DOMAIN=y 100 CONFIG_POWER_DOMAIN=y
101 CONFIG_IMX8_POWER_DOMAIN=y 101 CONFIG_IMX8_POWER_DOMAIN=y
102 102
103 CONFIG_DM_THERMAL=y 103 CONFIG_DM_THERMAL=y
104 CONFIG_IMX_SC_THERMAL=y 104 CONFIG_IMX_SC_THERMAL=y
105 105
106 CONFIG_ENV_IS_IN_MMC=y 106 CONFIG_ENV_IS_IN_MMC=y
107 CONFIG_LZ4=y 107 CONFIG_LZ4=y
108 108
109 CONFIG_SMC_FUSE=y 109 CONFIG_SMC_FUSE=y
110 CONFIG_CMD_MEMTEST=y 110 CONFIG_CMD_MEMTEST=y
111 111
112 CONFIG_SPL=y 112 CONFIG_SPL=y
113 CONFIG_SPL_MMC_SUPPORT=y 113 CONFIG_SPL_MMC_SUPPORT=y
114 CONFIG_SPL_GPIO_SUPPORT=y 114 CONFIG_SPL_GPIO_SUPPORT=y
115 115
116 CONFIG_SPL_ENV_SUPPORT=y 116 CONFIG_SPL_ENV_SUPPORT=y
117 CONFIG_SPL_LIBDISK_SUPPORT=y 117 CONFIG_SPL_LIBDISK_SUPPORT=y
118 118
119 CONFIG_NOT_UUU_BUILD=y 119 CONFIG_NOT_UUU_BUILD=y
120 CONFIG_SHA256=y 120 CONFIG_SHA256=y
121 CONFIG_SPL_MMC_WRITE=y 121 CONFIG_SPL_MMC_WRITE=y
122 CONFIG_DUAL_BOOTLOADER=y 122 CONFIG_DUAL_BOOTLOADER=y
123 CONFIG_APPEND_BOOTARGS=y 123 CONFIG_APPEND_BOOTARGS=y
124
125 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88800000
126 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x02000000
124 127
configs/imx8qm_mek_androidauto_xen_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-xen" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-xen"
4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT" 4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT"
5 CONFIG_TARGET_IMX8QM_MEK=y 5 CONFIG_TARGET_IMX8QM_MEK=y
6 CONFIG_SYS_TEXT_BASE=0x80080000 6 CONFIG_SYS_TEXT_BASE=0x80080000
7 CONFIG_EFI_PARTITION=y 7 CONFIG_EFI_PARTITION=y
8 CONFIG_SYS_MALLOC_F_LEN=0x2000 8 CONFIG_SYS_MALLOC_F_LEN=0x2000
9 CONFIG_DM=y 9 CONFIG_DM=y
10 CONFIG_DM_WARN=n 10 CONFIG_DM_WARN=n
11 CONFIG_DM_DEVICE_REMOVE=n 11 CONFIG_DM_DEVICE_REMOVE=n
12 CONFIG_IMX_TRUSTY_OS=n 12 CONFIG_IMX_TRUSTY_OS=n
13 13
14 CONFIG_DM_SERIAL=y 14 CONFIG_DM_SERIAL=y
15 CONFIG_FSL_LPUART=n 15 CONFIG_FSL_LPUART=n
16 CONFIG_OF_CONTROL=y 16 CONFIG_OF_CONTROL=y
17 CONFIG_DM_I2C=n 17 CONFIG_DM_I2C=n
18 # CONFIG_DM_I2C_COMPAT is not set 18 # CONFIG_DM_I2C_COMPAT is not set
19 CONFIG_SYS_I2C_IMX_LPI2C=n 19 CONFIG_SYS_I2C_IMX_LPI2C=n
20 CONFIG_CMD_I2C=n 20 CONFIG_CMD_I2C=n
21 21
22 CONFIG_USB_XHCI_HCD=n 22 CONFIG_USB_XHCI_HCD=n
23 CONFIG_USB_XHCI_IMX8=n 23 CONFIG_USB_XHCI_IMX8=n
24 24
25 CONFIG_DM_USB=y 25 CONFIG_DM_USB=y
26 26
27 CONFIG_USB=y 27 CONFIG_USB=y
28 CONFIG_USB_TCPC=n 28 CONFIG_USB_TCPC=n
29 29
30 CONFIG_USB_GADGET=y 30 CONFIG_USB_GADGET=y
31 CONFIG_CI_UDC=y 31 CONFIG_CI_UDC=y
32 CONFIG_USB_GADGET_DOWNLOAD=y 32 CONFIG_USB_GADGET_DOWNLOAD=y
33 CONFIG_USB_GADGET_MANUFACTURER="FSL" 33 CONFIG_USB_GADGET_MANUFACTURER="FSL"
34 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 34 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
35 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 35 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02
36 36
37 CONFIG_USB_CDNS3=n 37 CONFIG_USB_CDNS3=n
38 CONFIG_USB_CDNS3_GADGET=n 38 CONFIG_USB_CDNS3_GADGET=n
39 CONFIG_USB_GADGET_DUALSPEED=y 39 CONFIG_USB_GADGET_DUALSPEED=y
40 40
41 CONFIG_DM_GPIO=n 41 CONFIG_DM_GPIO=n
42 CONFIG_DM_PCA953X=n 42 CONFIG_DM_PCA953X=n
43 CONFIG_BOOTDELAY=1 43 CONFIG_BOOTDELAY=1
44 CONFIG_CMD_MMC=y 44 CONFIG_CMD_MMC=y
45 CONFIG_DM_MMC=y 45 CONFIG_DM_MMC=y
46 CONFIG_MMC_IO_VOLTAGE=y 46 CONFIG_MMC_IO_VOLTAGE=y
47 CONFIG_MMC_UHS_SUPPORT=y 47 CONFIG_MMC_UHS_SUPPORT=y
48 CONFIG_MMC_HS400_SUPPORT=y 48 CONFIG_MMC_HS400_SUPPORT=y
49 CONFIG_FSL_FSPI=n 49 CONFIG_FSL_FSPI=n
50 CONFIG_DM_SPI=n 50 CONFIG_DM_SPI=n
51 CONFIG_DM_SPI_FLASH=n 51 CONFIG_DM_SPI_FLASH=n
52 CONFIG_SPI_FLASH=n 52 CONFIG_SPI_FLASH=n
53 CONFIG_SPI_FLASH_4BYTES_ADDR=n 53 CONFIG_SPI_FLASH_4BYTES_ADDR=n
54 CONFIG_SPI_FLASH_STMICRO=n 54 CONFIG_SPI_FLASH_STMICRO=n
55 55
56 CONFIG_DM_REGULATOR=y 56 CONFIG_DM_REGULATOR=y
57 CONFIG_DM_REGULATOR_FIXED=n 57 CONFIG_DM_REGULATOR_FIXED=n
58 CONFIG_DM_REGULATOR_GPIO=n 58 CONFIG_DM_REGULATOR_GPIO=n
59 59
60 CONFIG_PINCTRL=y 60 CONFIG_PINCTRL=y
61 CONFIG_PINCTRL_IMX8=y 61 CONFIG_PINCTRL_IMX8=y
62 62
63 CONFIG_CMD_NET=n 63 CONFIG_CMD_NET=n
64 CONFIG_CMD_NFS=n 64 CONFIG_CMD_NFS=n
65 CONFIG_CMD_BDI=n 65 CONFIG_CMD_BDI=n
66 CONFIG_CMD_CONSOLE=n 66 CONFIG_CMD_CONSOLE=n
67 CONFIG_CMD_BOOTD=n 67 CONFIG_CMD_BOOTD=n
68 CONFIG_CMD_BOOTEFI=n 68 CONFIG_CMD_BOOTEFI=n
69 CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n 69 CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n
70 CONFIG_CMD_ELF=n 70 CONFIG_CMD_ELF=n
71 CONFIG_CMD_GO=n 71 CONFIG_CMD_GO=n
72 CONFIG_CMD_RUN=n 72 CONFIG_CMD_RUN=n
73 CONFIG_CMD_IMI=n 73 CONFIG_CMD_IMI=n
74 CONFIG_CMD_IMLS=n 74 CONFIG_CMD_IMLS=n
75 CONFIG_CMD_XIMG=n 75 CONFIG_CMD_XIMG=n
76 CONFIG_CMD_EXPORTENV=n 76 CONFIG_CMD_EXPORTENV=n
77 CONFIG_CMD_IMPORTENV=n 77 CONFIG_CMD_IMPORTENV=n
78 CONFIG_CMD_EDITENV=n 78 CONFIG_CMD_EDITENV=n
79 CONFIG_CMD_ENV_EXISTS=n 79 CONFIG_CMD_ENV_EXISTS=n
80 CONFIG_CMD_MEMORY=y 80 CONFIG_CMD_MEMORY=y
81 CONFIG_CMD_CRC32=n 81 CONFIG_CMD_CRC32=n
82 CONFIG_CMD_DM=n 82 CONFIG_CMD_DM=n
83 CONFIG_CMD_LOADB=n 83 CONFIG_CMD_LOADB=n
84 CONFIG_CMD_LOADS=n 84 CONFIG_CMD_LOADS=n
85 CONFIG_CMD_FLASH=n 85 CONFIG_CMD_FLASH=n
86 CONFIG_CMD_GPT=n 86 CONFIG_CMD_GPT=n
87 CONFIG_CMD_FPGA=n 87 CONFIG_CMD_FPGA=n
88 CONFIG_CMD_ECHO=n 88 CONFIG_CMD_ECHO=n
89 CONFIG_CMD_ITEST=n 89 CONFIG_CMD_ITEST=n
90 CONFIG_CMD_SOURCE=n 90 CONFIG_CMD_SOURCE=n
91 CONFIG_CMD_SETEXPR=n 91 CONFIG_CMD_SETEXPR=n
92 CONFIG_CMD_MISC=n 92 CONFIG_CMD_MISC=n
93 CONFIG_CMD_UNZIP=n 93 CONFIG_CMD_UNZIP=n
94 CONFIG_CMD_LZMADEC=n 94 CONFIG_CMD_LZMADEC=n
95 CONFIG_CMD_SAVEENV=n 95 CONFIG_CMD_SAVEENV=n
96 96
97 CONFIG_DISPLAY_CPUINFO=n 97 CONFIG_DISPLAY_CPUINFO=n
98 CONFIG_DISPLAY_BOARDINFO=n 98 CONFIG_DISPLAY_BOARDINFO=n
99 CONFIG_EFI_LOADER=n 99 CONFIG_EFI_LOADER=n
100 100
101 CONFIG_POWER_DOMAIN=y 101 CONFIG_POWER_DOMAIN=y
102 CONFIG_IMX8_POWER_DOMAIN=y 102 CONFIG_IMX8_POWER_DOMAIN=y
103 103
104 CONFIG_DM_THERMAL=n 104 CONFIG_DM_THERMAL=n
105 CONFIG_IMX_SC_THERMAL=n 105 CONFIG_IMX_SC_THERMAL=n
106 106
107 CONFIG_ENV_IS_IN_MMC=y 107 CONFIG_ENV_IS_IN_MMC=y
108 CONFIG_LZ4=y 108 CONFIG_LZ4=y
109 CONFIG_XEN=y 109 CONFIG_XEN=y
110 CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y 110 CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
111 CONFIG_XEN_DEBUG_SERIAL=y 111 CONFIG_XEN_DEBUG_SERIAL=y
112 112
113 CONFIG_SMC_FUSE=y 113 CONFIG_SMC_FUSE=y
114 CONFIG_CMD_MEMTEST=y 114 CONFIG_CMD_MEMTEST=y
115 115
116 CONFIG_FIT=y 116 CONFIG_FIT=y
117 CONFIG_SPL=y 117 CONFIG_SPL=y
118 CONFIG_SPL_FIT=y 118 CONFIG_SPL_FIT=y
119 CONFIG_SPL_LOAD_FIT=y 119 CONFIG_SPL_LOAD_FIT=y
120 CONFIG_SPL_MMC_SUPPORT=y 120 CONFIG_SPL_MMC_SUPPORT=y
121 CONFIG_SPL_GPIO_SUPPORT=y 121 CONFIG_SPL_GPIO_SUPPORT=y
122 122
123 CONFIG_SPL_ENV_SUPPORT=y 123 CONFIG_SPL_ENV_SUPPORT=y
124 CONFIG_SPL_LIBDISK_SUPPORT=y 124 CONFIG_SPL_LIBDISK_SUPPORT=y
125 CONFIG_APPEND_BOOTARGS=y 125 CONFIG_APPEND_BOOTARGS=y
126
127 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
128 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
126 129
configs/imx8qm_mek_androidauto_xen_dual_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-xen" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-xen"
4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT" 4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT"
5 CONFIG_TARGET_IMX8QM_MEK=y 5 CONFIG_TARGET_IMX8QM_MEK=y
6 CONFIG_SYS_TEXT_BASE=0x81080000 6 CONFIG_SYS_TEXT_BASE=0x81080000
7 CONFIG_EFI_PARTITION=y 7 CONFIG_EFI_PARTITION=y
8 CONFIG_SYS_MALLOC_F_LEN=0x2000 8 CONFIG_SYS_MALLOC_F_LEN=0x2000
9 CONFIG_DM=y 9 CONFIG_DM=y
10 CONFIG_DM_WARN=n 10 CONFIG_DM_WARN=n
11 CONFIG_DM_DEVICE_REMOVE=n 11 CONFIG_DM_DEVICE_REMOVE=n
12 CONFIG_IMX_TRUSTY_OS=n 12 CONFIG_IMX_TRUSTY_OS=n
13 13
14 CONFIG_DM_SERIAL=y 14 CONFIG_DM_SERIAL=y
15 CONFIG_FSL_LPUART=n 15 CONFIG_FSL_LPUART=n
16 CONFIG_OF_CONTROL=y 16 CONFIG_OF_CONTROL=y
17 CONFIG_DM_I2C=n 17 CONFIG_DM_I2C=n
18 # CONFIG_DM_I2C_COMPAT is not set 18 # CONFIG_DM_I2C_COMPAT is not set
19 CONFIG_SYS_I2C_IMX_LPI2C=n 19 CONFIG_SYS_I2C_IMX_LPI2C=n
20 CONFIG_CMD_I2C=n 20 CONFIG_CMD_I2C=n
21 21
22 CONFIG_USB_XHCI_HCD=n 22 CONFIG_USB_XHCI_HCD=n
23 CONFIG_USB_XHCI_IMX8=n 23 CONFIG_USB_XHCI_IMX8=n
24 24
25 CONFIG_DM_USB=y 25 CONFIG_DM_USB=y
26 26
27 CONFIG_USB=y 27 CONFIG_USB=y
28 CONFIG_USB_TCPC=n 28 CONFIG_USB_TCPC=n
29 29
30 CONFIG_USB_GADGET=y 30 CONFIG_USB_GADGET=y
31 CONFIG_CI_UDC=y 31 CONFIG_CI_UDC=y
32 CONFIG_USB_GADGET_DOWNLOAD=y 32 CONFIG_USB_GADGET_DOWNLOAD=y
33 CONFIG_USB_GADGET_MANUFACTURER="FSL" 33 CONFIG_USB_GADGET_MANUFACTURER="FSL"
34 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 34 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
35 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 35 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02
36 36
37 CONFIG_USB_CDNS3=n 37 CONFIG_USB_CDNS3=n
38 CONFIG_USB_CDNS3_GADGET=n 38 CONFIG_USB_CDNS3_GADGET=n
39 CONFIG_USB_GADGET_DUALSPEED=y 39 CONFIG_USB_GADGET_DUALSPEED=y
40 40
41 CONFIG_DM_GPIO=n 41 CONFIG_DM_GPIO=n
42 CONFIG_DM_PCA953X=n 42 CONFIG_DM_PCA953X=n
43 CONFIG_BOOTDELAY=1 43 CONFIG_BOOTDELAY=1
44 CONFIG_CMD_MMC=y 44 CONFIG_CMD_MMC=y
45 CONFIG_DM_MMC=y 45 CONFIG_DM_MMC=y
46 CONFIG_MMC_IO_VOLTAGE=y 46 CONFIG_MMC_IO_VOLTAGE=y
47 CONFIG_MMC_UHS_SUPPORT=y 47 CONFIG_MMC_UHS_SUPPORT=y
48 CONFIG_MMC_HS400_SUPPORT=y 48 CONFIG_MMC_HS400_SUPPORT=y
49 CONFIG_FSL_FSPI=n 49 CONFIG_FSL_FSPI=n
50 CONFIG_DM_SPI=n 50 CONFIG_DM_SPI=n
51 CONFIG_DM_SPI_FLASH=n 51 CONFIG_DM_SPI_FLASH=n
52 CONFIG_SPI_FLASH=n 52 CONFIG_SPI_FLASH=n
53 CONFIG_SPI_FLASH_4BYTES_ADDR=n 53 CONFIG_SPI_FLASH_4BYTES_ADDR=n
54 CONFIG_SPI_FLASH_STMICRO=n 54 CONFIG_SPI_FLASH_STMICRO=n
55 55
56 CONFIG_DM_REGULATOR=y 56 CONFIG_DM_REGULATOR=y
57 CONFIG_DM_REGULATOR_FIXED=n 57 CONFIG_DM_REGULATOR_FIXED=n
58 CONFIG_DM_REGULATOR_GPIO=n 58 CONFIG_DM_REGULATOR_GPIO=n
59 59
60 CONFIG_PINCTRL=y 60 CONFIG_PINCTRL=y
61 CONFIG_PINCTRL_IMX8=y 61 CONFIG_PINCTRL_IMX8=y
62 62
63 CONFIG_CMD_NET=n 63 CONFIG_CMD_NET=n
64 CONFIG_CMD_NFS=n 64 CONFIG_CMD_NFS=n
65 CONFIG_CMD_BDI=n 65 CONFIG_CMD_BDI=n
66 CONFIG_CMD_CONSOLE=n 66 CONFIG_CMD_CONSOLE=n
67 CONFIG_CMD_BOOTD=n 67 CONFIG_CMD_BOOTD=n
68 CONFIG_CMD_BOOTEFI=n 68 CONFIG_CMD_BOOTEFI=n
69 CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n 69 CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n
70 CONFIG_CMD_ELF=n 70 CONFIG_CMD_ELF=n
71 CONFIG_CMD_GO=n 71 CONFIG_CMD_GO=n
72 CONFIG_CMD_RUN=n 72 CONFIG_CMD_RUN=n
73 CONFIG_CMD_IMI=n 73 CONFIG_CMD_IMI=n
74 CONFIG_CMD_IMLS=n 74 CONFIG_CMD_IMLS=n
75 CONFIG_CMD_XIMG=n 75 CONFIG_CMD_XIMG=n
76 CONFIG_CMD_EXPORTENV=n 76 CONFIG_CMD_EXPORTENV=n
77 CONFIG_CMD_IMPORTENV=n 77 CONFIG_CMD_IMPORTENV=n
78 CONFIG_CMD_EDITENV=n 78 CONFIG_CMD_EDITENV=n
79 CONFIG_CMD_ENV_EXISTS=n 79 CONFIG_CMD_ENV_EXISTS=n
80 CONFIG_CMD_MEMORY=y 80 CONFIG_CMD_MEMORY=y
81 CONFIG_CMD_CRC32=n 81 CONFIG_CMD_CRC32=n
82 CONFIG_CMD_DM=n 82 CONFIG_CMD_DM=n
83 CONFIG_CMD_LOADB=n 83 CONFIG_CMD_LOADB=n
84 CONFIG_CMD_LOADS=n 84 CONFIG_CMD_LOADS=n
85 CONFIG_CMD_FLASH=n 85 CONFIG_CMD_FLASH=n
86 CONFIG_CMD_GPT=n 86 CONFIG_CMD_GPT=n
87 CONFIG_CMD_FPGA=n 87 CONFIG_CMD_FPGA=n
88 CONFIG_CMD_ECHO=n 88 CONFIG_CMD_ECHO=n
89 CONFIG_CMD_ITEST=n 89 CONFIG_CMD_ITEST=n
90 CONFIG_CMD_SOURCE=n 90 CONFIG_CMD_SOURCE=n
91 CONFIG_CMD_SETEXPR=n 91 CONFIG_CMD_SETEXPR=n
92 CONFIG_CMD_MISC=n 92 CONFIG_CMD_MISC=n
93 CONFIG_CMD_UNZIP=n 93 CONFIG_CMD_UNZIP=n
94 CONFIG_CMD_LZMADEC=n 94 CONFIG_CMD_LZMADEC=n
95 CONFIG_CMD_SAVEENV=n 95 CONFIG_CMD_SAVEENV=n
96 96
97 CONFIG_DISPLAY_CPUINFO=n 97 CONFIG_DISPLAY_CPUINFO=n
98 CONFIG_DISPLAY_BOARDINFO=n 98 CONFIG_DISPLAY_BOARDINFO=n
99 CONFIG_EFI_LOADER=n 99 CONFIG_EFI_LOADER=n
100 100
101 CONFIG_POWER_DOMAIN=y 101 CONFIG_POWER_DOMAIN=y
102 CONFIG_IMX8_POWER_DOMAIN=y 102 CONFIG_IMX8_POWER_DOMAIN=y
103 103
104 CONFIG_DM_THERMAL=n 104 CONFIG_DM_THERMAL=n
105 CONFIG_IMX_SC_THERMAL=n 105 CONFIG_IMX_SC_THERMAL=n
106 106
107 CONFIG_ENV_IS_IN_MMC=y 107 CONFIG_ENV_IS_IN_MMC=y
108 CONFIG_LZ4=y 108 CONFIG_LZ4=y
109 CONFIG_XEN=y 109 CONFIG_XEN=y
110 CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y 110 CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
111 CONFIG_XEN_DEBUG_SERIAL=y 111 CONFIG_XEN_DEBUG_SERIAL=y
112 112
113 CONFIG_SMC_FUSE=y 113 CONFIG_SMC_FUSE=y
114 CONFIG_CMD_MEMTEST=y 114 CONFIG_CMD_MEMTEST=y
115 115
116 CONFIG_SPL=y 116 CONFIG_SPL=y
117 CONFIG_SPL_MMC_SUPPORT=y 117 CONFIG_SPL_MMC_SUPPORT=y
118 CONFIG_SPL_GPIO_SUPPORT=y 118 CONFIG_SPL_GPIO_SUPPORT=y
119 119
120 CONFIG_SPL_ENV_SUPPORT=y 120 CONFIG_SPL_ENV_SUPPORT=y
121 CONFIG_SPL_LIBDISK_SUPPORT=y 121 CONFIG_SPL_LIBDISK_SUPPORT=y
122 122
123 CONFIG_NOT_UUU_BUILD=y 123 CONFIG_NOT_UUU_BUILD=y
124 CONFIG_SHA256=y 124 CONFIG_SHA256=y
125 CONFIG_SPL_MMC_WRITE=y 125 CONFIG_SPL_MMC_WRITE=y
126 CONFIG_DUAL_BOOTLOADER=y 126 CONFIG_DUAL_BOOTLOADER=y
127 CONFIG_APPEND_BOOTARGS=y 127 CONFIG_APPEND_BOOTARGS=y
128
129 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88800000
130 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x02000000
128 131
configs/imx8qm_mek_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
4 CONFIG_TARGET_IMX8QM_MEK=y 4 CONFIG_TARGET_IMX8QM_MEK=y
5 CONFIG_SYS_TEXT_BASE=0x80020000 5 CONFIG_SYS_TEXT_BASE=0x80020000
6 CONFIG_CMD_IMPORTENV=n 6 CONFIG_CMD_IMPORTENV=n
7 CONFIG_SYS_MALLOC_F_LEN=0x2000 7 CONFIG_SYS_MALLOC_F_LEN=0x2000
8 CONFIG_DM=y 8 CONFIG_DM=y
9 CONFIG_CMD_CACHE=y 9 CONFIG_CMD_CACHE=y
10 10
11 CONFIG_DM_SERIAL=y 11 CONFIG_DM_SERIAL=y
12 CONFIG_FSL_LPUART=y 12 CONFIG_FSL_LPUART=y
13 CONFIG_OF_CONTROL=y 13 CONFIG_OF_CONTROL=y
14 CONFIG_DM_I2C=y 14 CONFIG_DM_I2C=y
15 # CONFIG_DM_I2C_COMPAT is not set 15 # CONFIG_DM_I2C_COMPAT is not set
16 CONFIG_SYS_I2C_IMX_LPI2C=y 16 CONFIG_SYS_I2C_IMX_LPI2C=y
17 CONFIG_CMD_I2C=y 17 CONFIG_CMD_I2C=y
18 18
19 CONFIG_FASTBOOT=y 19 CONFIG_FASTBOOT=y
20 CONFIG_USB_FUNCTION_FASTBOOT=y 20 CONFIG_USB_FUNCTION_FASTBOOT=y
21 CONFIG_CMD_FASTBOOT=y 21 CONFIG_CMD_FASTBOOT=y
22 CONFIG_ANDROID_BOOT_IMAGE=y 22 CONFIG_ANDROID_BOOT_IMAGE=y
23 CONFIG_FSL_FASTBOOT=y 23 CONFIG_FSL_FASTBOOT=y
24 CONFIG_FASTBOOT_BUF_ADDR=0x82800000 24 CONFIG_FASTBOOT_BUF_ADDR=0x82800000
25 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 25 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
26 CONFIG_FASTBOOT_FLASH=y 26 CONFIG_FASTBOOT_FLASH=y
27 CONFIG_FASTBOOT_FLASH_MMC_DEV=0 27 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
28 CONFIG_FASTBOOT_USB_DEV=1 28 CONFIG_FASTBOOT_USB_DEV=1
29 29
30 CONFIG_USB_XHCI_HCD=y 30 CONFIG_USB_XHCI_HCD=y
31 CONFIG_USB_XHCI_IMX8=y 31 CONFIG_USB_XHCI_IMX8=y
32 32
33 CONFIG_DM_USB=y 33 CONFIG_DM_USB=y
34 34
35 CONFIG_USB=y 35 CONFIG_USB=y
36 CONFIG_USB_TCPC=y 36 CONFIG_USB_TCPC=y
37 37
38 CONFIG_USB_GADGET=y 38 CONFIG_USB_GADGET=y
39 # CONFIG_CI_UDC=y 39 # CONFIG_CI_UDC=y
40 CONFIG_USB_GADGET_DOWNLOAD=y 40 CONFIG_USB_GADGET_DOWNLOAD=y
41 CONFIG_USB_GADGET_MANUFACTURER="FSL" 41 CONFIG_USB_GADGET_MANUFACTURER="FSL"
42 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 42 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
43 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 43 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
44 44
45 CONFIG_USB_CDNS3=y 45 CONFIG_USB_CDNS3=y
46 CONFIG_USB_CDNS3_GADGET=y 46 CONFIG_USB_CDNS3_GADGET=y
47 CONFIG_USB_GADGET_DUALSPEED=y 47 CONFIG_USB_GADGET_DUALSPEED=y
48 48
49 CONFIG_CMD_GPIO=y 49 CONFIG_CMD_GPIO=y
50 CONFIG_DM_GPIO=y 50 CONFIG_DM_GPIO=y
51 CONFIG_DM_PCA953X=y 51 CONFIG_DM_PCA953X=y
52 CONFIG_BOOTDELAY=3 52 CONFIG_BOOTDELAY=3
53 CONFIG_IMX_BOOTAUX=y 53 CONFIG_IMX_BOOTAUX=y
54 CONFIG_FS_FAT=y 54 CONFIG_FS_FAT=y
55 CONFIG_CMD_FAT=y 55 CONFIG_CMD_FAT=y
56 CONFIG_CMD_MMC=y 56 CONFIG_CMD_MMC=y
57 CONFIG_DM_MMC=y 57 CONFIG_DM_MMC=y
58 CONFIG_MMC_IO_VOLTAGE=y 58 CONFIG_MMC_IO_VOLTAGE=y
59 CONFIG_MMC_UHS_SUPPORT=y 59 CONFIG_MMC_UHS_SUPPORT=y
60 CONFIG_MMC_HS400_SUPPORT=y 60 CONFIG_MMC_HS400_SUPPORT=y
61 CONFIG_EFI_PARTITION=y 61 CONFIG_EFI_PARTITION=y
62 CONFIG_FSL_FSPI=y 62 CONFIG_FSL_FSPI=y
63 CONFIG_DM_SPI=y 63 CONFIG_DM_SPI=y
64 CONFIG_DM_SPI_FLASH=y 64 CONFIG_DM_SPI_FLASH=y
65 CONFIG_SPI_FLASH=y 65 CONFIG_SPI_FLASH=y
66 CONFIG_SPI_FLASH_4BYTES_ADDR=y 66 CONFIG_SPI_FLASH_4BYTES_ADDR=y
67 CONFIG_SPI_FLASH_STMICRO=y 67 CONFIG_SPI_FLASH_STMICRO=y
68 CONFIG_CMD_SF=y 68 CONFIG_CMD_SF=y
69 69
70 CONFIG_CMD_PING=y 70 CONFIG_CMD_PING=y
71 CONFIG_CMD_DHCP=y 71 CONFIG_CMD_DHCP=y
72 CONFIG_CMD_MII=y 72 CONFIG_CMD_MII=y
73 CONFIG_DM_ETH=y 73 CONFIG_DM_ETH=y
74 # CONFIG_EFI_LOADER is not set 74 # CONFIG_EFI_LOADER is not set
75 75
76 CONFIG_DM_REGULATOR=y 76 CONFIG_DM_REGULATOR=y
77 CONFIG_DM_REGULATOR_FIXED=y 77 CONFIG_DM_REGULATOR_FIXED=y
78 CONFIG_DM_REGULATOR_GPIO=y 78 CONFIG_DM_REGULATOR_GPIO=y
79 79
80 CONFIG_VIDEO=y 80 CONFIG_VIDEO=y
81 CONFIG_VIDEO_IMX_HDP_LOAD=y 81 CONFIG_VIDEO_IMX_HDP_LOAD=y
82 82
83 CONFIG_PINCTRL=y 83 CONFIG_PINCTRL=y
84 CONFIG_PINCTRL_IMX8=y 84 CONFIG_PINCTRL_IMX8=y
85 85
86 CONFIG_POWER_DOMAIN=y 86 CONFIG_POWER_DOMAIN=y
87 CONFIG_IMX8_POWER_DOMAIN=y 87 CONFIG_IMX8_POWER_DOMAIN=y
88 88
89 CONFIG_DM_THERMAL=y 89 CONFIG_DM_THERMAL=y
90 CONFIG_IMX_SC_THERMAL=y 90 CONFIG_IMX_SC_THERMAL=y
91 91
92 CONFIG_ENV_IS_IN_MMC=y 92 CONFIG_ENV_IS_IN_MMC=y
93 93
94 CONFIG_SMC_FUSE=y 94 CONFIG_SMC_FUSE=y
95 CONFIG_CMD_MEMTEST=y 95 CONFIG_CMD_MEMTEST=y
96
97 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
98 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
96 99
configs/imx8qm_mek_fspi_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
4 CONFIG_TARGET_IMX8QM_MEK=y 4 CONFIG_TARGET_IMX8QM_MEK=y
5 CONFIG_SYS_TEXT_BASE=0x80020000 5 CONFIG_SYS_TEXT_BASE=0x80020000
6 CONFIG_CMD_IMPORTENV=n 6 CONFIG_CMD_IMPORTENV=n
7 CONFIG_SYS_MALLOC_F_LEN=0x2000 7 CONFIG_SYS_MALLOC_F_LEN=0x2000
8 CONFIG_DM=y 8 CONFIG_DM=y
9 CONFIG_CMD_CACHE=y 9 CONFIG_CMD_CACHE=y
10 10
11 CONFIG_DM_SERIAL=y 11 CONFIG_DM_SERIAL=y
12 CONFIG_FSL_LPUART=y 12 CONFIG_FSL_LPUART=y
13 CONFIG_OF_CONTROL=y 13 CONFIG_OF_CONTROL=y
14 CONFIG_DM_I2C=y 14 CONFIG_DM_I2C=y
15 # CONFIG_DM_I2C_COMPAT is not set 15 # CONFIG_DM_I2C_COMPAT is not set
16 CONFIG_SYS_I2C_IMX_LPI2C=y 16 CONFIG_SYS_I2C_IMX_LPI2C=y
17 CONFIG_CMD_I2C=y 17 CONFIG_CMD_I2C=y
18 18
19 CONFIG_FASTBOOT=y 19 CONFIG_FASTBOOT=y
20 CONFIG_USB_FUNCTION_FASTBOOT=y 20 CONFIG_USB_FUNCTION_FASTBOOT=y
21 CONFIG_CMD_FASTBOOT=y 21 CONFIG_CMD_FASTBOOT=y
22 CONFIG_ANDROID_BOOT_IMAGE=y 22 CONFIG_ANDROID_BOOT_IMAGE=y
23 CONFIG_FSL_FASTBOOT=y 23 CONFIG_FSL_FASTBOOT=y
24 CONFIG_FASTBOOT_BUF_ADDR=0x82800000 24 CONFIG_FASTBOOT_BUF_ADDR=0x82800000
25 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 25 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
26 CONFIG_FASTBOOT_FLASH=y 26 CONFIG_FASTBOOT_FLASH=y
27 CONFIG_FASTBOOT_FLASH_MMC_DEV=0 27 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
28 CONFIG_FASTBOOT_USB_DEV=1 28 CONFIG_FASTBOOT_USB_DEV=1
29 29
30 CONFIG_USB_XHCI_HCD=y 30 CONFIG_USB_XHCI_HCD=y
31 CONFIG_USB_XHCI_IMX8=y 31 CONFIG_USB_XHCI_IMX8=y
32 32
33 CONFIG_DM_USB=y 33 CONFIG_DM_USB=y
34 34
35 CONFIG_USB=y 35 CONFIG_USB=y
36 CONFIG_USB_TCPC=y 36 CONFIG_USB_TCPC=y
37 37
38 CONFIG_USB_GADGET=y 38 CONFIG_USB_GADGET=y
39 # CONFIG_CI_UDC=y 39 # CONFIG_CI_UDC=y
40 CONFIG_USB_GADGET_DOWNLOAD=y 40 CONFIG_USB_GADGET_DOWNLOAD=y
41 CONFIG_USB_GADGET_MANUFACTURER="FSL" 41 CONFIG_USB_GADGET_MANUFACTURER="FSL"
42 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 42 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
43 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 43 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
44 44
45 CONFIG_USB_CDNS3=y 45 CONFIG_USB_CDNS3=y
46 CONFIG_USB_CDNS3_GADGET=y 46 CONFIG_USB_CDNS3_GADGET=y
47 CONFIG_USB_GADGET_DUALSPEED=y 47 CONFIG_USB_GADGET_DUALSPEED=y
48 48
49 CONFIG_CMD_GPIO=y 49 CONFIG_CMD_GPIO=y
50 CONFIG_DM_GPIO=y 50 CONFIG_DM_GPIO=y
51 CONFIG_DM_PCA953X=y 51 CONFIG_DM_PCA953X=y
52 CONFIG_BOOTDELAY=3 52 CONFIG_BOOTDELAY=3
53 CONFIG_IMX_BOOTAUX=y 53 CONFIG_IMX_BOOTAUX=y
54 CONFIG_FS_FAT=y 54 CONFIG_FS_FAT=y
55 CONFIG_CMD_FAT=y 55 CONFIG_CMD_FAT=y
56 CONFIG_CMD_MMC=y 56 CONFIG_CMD_MMC=y
57 CONFIG_DM_MMC=y 57 CONFIG_DM_MMC=y
58 CONFIG_MMC_IO_VOLTAGE=y 58 CONFIG_MMC_IO_VOLTAGE=y
59 CONFIG_MMC_UHS_SUPPORT=y 59 CONFIG_MMC_UHS_SUPPORT=y
60 CONFIG_MMC_HS400_SUPPORT=y 60 CONFIG_MMC_HS400_SUPPORT=y
61 CONFIG_EFI_PARTITION=y 61 CONFIG_EFI_PARTITION=y
62 CONFIG_QSPI_BOOT=y 62 CONFIG_QSPI_BOOT=y
63 CONFIG_FSL_FSPI=y 63 CONFIG_FSL_FSPI=y
64 CONFIG_DM_SPI=y 64 CONFIG_DM_SPI=y
65 CONFIG_DM_SPI_FLASH=y 65 CONFIG_DM_SPI_FLASH=y
66 CONFIG_SPI_FLASH=y 66 CONFIG_SPI_FLASH=y
67 CONFIG_SPI_FLASH_4BYTES_ADDR=y 67 CONFIG_SPI_FLASH_4BYTES_ADDR=y
68 CONFIG_SPI_FLASH_STMICRO=y 68 CONFIG_SPI_FLASH_STMICRO=y
69 CONFIG_CMD_SF=y 69 CONFIG_CMD_SF=y
70 70
71 CONFIG_CMD_PING=y 71 CONFIG_CMD_PING=y
72 CONFIG_CMD_DHCP=y 72 CONFIG_CMD_DHCP=y
73 CONFIG_CMD_MII=y 73 CONFIG_CMD_MII=y
74 CONFIG_DM_ETH=y 74 CONFIG_DM_ETH=y
75 # CONFIG_EFI_LOADER is not set 75 # CONFIG_EFI_LOADER is not set
76 76
77 CONFIG_DM_REGULATOR=y 77 CONFIG_DM_REGULATOR=y
78 CONFIG_DM_REGULATOR_FIXED=y 78 CONFIG_DM_REGULATOR_FIXED=y
79 CONFIG_DM_REGULATOR_GPIO=y 79 CONFIG_DM_REGULATOR_GPIO=y
80 80
81 CONFIG_VIDEO=y 81 CONFIG_VIDEO=y
82 CONFIG_VIDEO_IMX_HDP_LOAD=y 82 CONFIG_VIDEO_IMX_HDP_LOAD=y
83 83
84 CONFIG_PINCTRL=y 84 CONFIG_PINCTRL=y
85 CONFIG_PINCTRL_IMX8=y 85 CONFIG_PINCTRL_IMX8=y
86 86
87 CONFIG_POWER_DOMAIN=y 87 CONFIG_POWER_DOMAIN=y
88 CONFIG_IMX8_POWER_DOMAIN=y 88 CONFIG_IMX8_POWER_DOMAIN=y
89 89
90 CONFIG_DM_THERMAL=y 90 CONFIG_DM_THERMAL=y
91 CONFIG_IMX_SC_THERMAL=y 91 CONFIG_IMX_SC_THERMAL=y
92 92
93 CONFIG_ENV_IS_IN_SPI_FLASH=y 93 CONFIG_ENV_IS_IN_SPI_FLASH=y
94 94
95 CONFIG_SMC_FUSE=y 95 CONFIG_SMC_FUSE=y
96 CONFIG_CMD_MEMTEST=y 96 CONFIG_CMD_MEMTEST=y
97
98 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
99 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
97 100
configs/imx8qm_mek_spl_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
4 CONFIG_TARGET_IMX8QM_MEK=y 4 CONFIG_TARGET_IMX8QM_MEK=y
5 CONFIG_SYS_TEXT_BASE=0x80020000 5 CONFIG_SYS_TEXT_BASE=0x80020000
6 CONFIG_CMD_IMPORTENV=n 6 CONFIG_CMD_IMPORTENV=n
7 CONFIG_SYS_MALLOC_F_LEN=0x2000 7 CONFIG_SYS_MALLOC_F_LEN=0x2000
8 CONFIG_DM=y 8 CONFIG_DM=y
9 CONFIG_CMD_CACHE=y 9 CONFIG_CMD_CACHE=y
10 10
11 CONFIG_DM_SERIAL=y 11 CONFIG_DM_SERIAL=y
12 CONFIG_FSL_LPUART=y 12 CONFIG_FSL_LPUART=y
13 CONFIG_OF_CONTROL=y 13 CONFIG_OF_CONTROL=y
14 CONFIG_DM_I2C=y 14 CONFIG_DM_I2C=y
15 # CONFIG_DM_I2C_COMPAT is not set 15 # CONFIG_DM_I2C_COMPAT is not set
16 CONFIG_SYS_I2C_IMX_LPI2C=y 16 CONFIG_SYS_I2C_IMX_LPI2C=y
17 CONFIG_CMD_I2C=y 17 CONFIG_CMD_I2C=y
18 18
19 CONFIG_SPL=y 19 CONFIG_SPL=y
20 CONFIG_SPL_GPIO_SUPPORT=y 20 CONFIG_SPL_GPIO_SUPPORT=y
21 CONFIG_SPL_MMC_SUPPORT=y 21 CONFIG_SPL_MMC_SUPPORT=y
22 CONFIG_FIT=y 22 CONFIG_FIT=y
23 CONFIG_SPL_LOAD_FIT=y 23 CONFIG_SPL_LOAD_FIT=y
24 CONFIG_SPL_BOARD_INIT=y 24 CONFIG_SPL_BOARD_INIT=y
25 CONFIG_SPL_TINY_MEMSET=y 25 CONFIG_SPL_TINY_MEMSET=y
26 CONFIG_SPL_OF_CONTROL=y 26 CONFIG_SPL_OF_CONTROL=y
27 27
28 CONFIG_FASTBOOT=y 28 CONFIG_FASTBOOT=y
29 CONFIG_USB_FUNCTION_FASTBOOT=y 29 CONFIG_USB_FUNCTION_FASTBOOT=y
30 CONFIG_CMD_FASTBOOT=y 30 CONFIG_CMD_FASTBOOT=y
31 CONFIG_ANDROID_BOOT_IMAGE=y 31 CONFIG_ANDROID_BOOT_IMAGE=y
32 CONFIG_FSL_FASTBOOT=y 32 CONFIG_FSL_FASTBOOT=y
33 CONFIG_FASTBOOT_BUF_ADDR=0x82800000 33 CONFIG_FASTBOOT_BUF_ADDR=0x82800000
34 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 34 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
35 CONFIG_FASTBOOT_FLASH=y 35 CONFIG_FASTBOOT_FLASH=y
36 CONFIG_FASTBOOT_FLASH_MMC_DEV=0 36 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
37 CONFIG_FASTBOOT_USB_DEV=1 37 CONFIG_FASTBOOT_USB_DEV=1
38 38
39 CONFIG_USB_XHCI_HCD=y 39 CONFIG_USB_XHCI_HCD=y
40 CONFIG_USB_XHCI_IMX8=y 40 CONFIG_USB_XHCI_IMX8=y
41 41
42 CONFIG_DM_USB=y 42 CONFIG_DM_USB=y
43 43
44 CONFIG_USB=y 44 CONFIG_USB=y
45 CONFIG_USB_TCPC=y 45 CONFIG_USB_TCPC=y
46 46
47 CONFIG_USB_GADGET=y 47 CONFIG_USB_GADGET=y
48 # CONFIG_CI_UDC=y 48 # CONFIG_CI_UDC=y
49 CONFIG_USB_GADGET_DOWNLOAD=y 49 CONFIG_USB_GADGET_DOWNLOAD=y
50 CONFIG_USB_GADGET_MANUFACTURER="FSL" 50 CONFIG_USB_GADGET_MANUFACTURER="FSL"
51 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 51 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
52 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 52 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
53 53
54 CONFIG_USB_CDNS3=y 54 CONFIG_USB_CDNS3=y
55 CONFIG_USB_CDNS3_GADGET=y 55 CONFIG_USB_CDNS3_GADGET=y
56 CONFIG_USB_GADGET_DUALSPEED=y 56 CONFIG_USB_GADGET_DUALSPEED=y
57 57
58 CONFIG_CMD_GPIO=y 58 CONFIG_CMD_GPIO=y
59 CONFIG_DM_GPIO=y 59 CONFIG_DM_GPIO=y
60 CONFIG_DM_PCA953X=y 60 CONFIG_DM_PCA953X=y
61 CONFIG_BOOTDELAY=3 61 CONFIG_BOOTDELAY=3
62 CONFIG_IMX_BOOTAUX=y 62 CONFIG_IMX_BOOTAUX=y
63 CONFIG_FS_FAT=y 63 CONFIG_FS_FAT=y
64 CONFIG_CMD_FAT=y 64 CONFIG_CMD_FAT=y
65 CONFIG_CMD_MMC=y 65 CONFIG_CMD_MMC=y
66 CONFIG_DM_MMC=y 66 CONFIG_DM_MMC=y
67 CONFIG_MMC_IO_VOLTAGE=y 67 CONFIG_MMC_IO_VOLTAGE=y
68 CONFIG_MMC_UHS_SUPPORT=y 68 CONFIG_MMC_UHS_SUPPORT=y
69 CONFIG_MMC_HS400_SUPPORT=y 69 CONFIG_MMC_HS400_SUPPORT=y
70 CONFIG_EFI_PARTITION=y 70 CONFIG_EFI_PARTITION=y
71 CONFIG_FSL_FSPI=y 71 CONFIG_FSL_FSPI=y
72 CONFIG_DM_SPI=y 72 CONFIG_DM_SPI=y
73 CONFIG_DM_SPI_FLASH=y 73 CONFIG_DM_SPI_FLASH=y
74 CONFIG_SPI_FLASH=y 74 CONFIG_SPI_FLASH=y
75 CONFIG_SPI_FLASH_4BYTES_ADDR=y 75 CONFIG_SPI_FLASH_4BYTES_ADDR=y
76 CONFIG_SPI_FLASH_STMICRO=y 76 CONFIG_SPI_FLASH_STMICRO=y
77 CONFIG_CMD_SF=y 77 CONFIG_CMD_SF=y
78 78
79 CONFIG_CMD_PING=y 79 CONFIG_CMD_PING=y
80 CONFIG_CMD_DHCP=y 80 CONFIG_CMD_DHCP=y
81 CONFIG_CMD_MII=y 81 CONFIG_CMD_MII=y
82 CONFIG_DM_ETH=y 82 CONFIG_DM_ETH=y
83 # CONFIG_EFI_LOADER is not set 83 # CONFIG_EFI_LOADER is not set
84 84
85 CONFIG_DM_REGULATOR=y 85 CONFIG_DM_REGULATOR=y
86 CONFIG_DM_REGULATOR_FIXED=y 86 CONFIG_DM_REGULATOR_FIXED=y
87 CONFIG_DM_REGULATOR_GPIO=y 87 CONFIG_DM_REGULATOR_GPIO=y
88 88
89 CONFIG_VIDEO=y 89 CONFIG_VIDEO=y
90 CONFIG_VIDEO_IMX_HDP_LOAD=y 90 CONFIG_VIDEO_IMX_HDP_LOAD=y
91 91
92 CONFIG_PINCTRL=y 92 CONFIG_PINCTRL=y
93 CONFIG_PINCTRL_IMX8=y 93 CONFIG_PINCTRL_IMX8=y
94 94
95 CONFIG_POWER_DOMAIN=y 95 CONFIG_POWER_DOMAIN=y
96 CONFIG_IMX8_POWER_DOMAIN=y 96 CONFIG_IMX8_POWER_DOMAIN=y
97 97
98 CONFIG_DM_THERMAL=y 98 CONFIG_DM_THERMAL=y
99 CONFIG_IMX_SC_THERMAL=y 99 CONFIG_IMX_SC_THERMAL=y
100 100
101 CONFIG_ENV_IS_IN_MMC=y 101 CONFIG_ENV_IS_IN_MMC=y
102 102
103 CONFIG_SMC_FUSE=y 103 CONFIG_SMC_FUSE=y
104 CONFIG_CMD_MEMTEST=y 104 CONFIG_CMD_MEMTEST=y
105 105
106 CONFIG_SPL_USB_HOST_SUPPORT=y 106 CONFIG_SPL_USB_HOST_SUPPORT=y
107 CONFIG_SPL_USB_GADGET_SUPPORT=y 107 CONFIG_SPL_USB_GADGET_SUPPORT=y
108 CONFIG_SPL_USB_SDP_SUPPORT=y 108 CONFIG_SPL_USB_SDP_SUPPORT=y
109 CONFIG_SPL_SDP_USB_DEV=1 109 CONFIG_SPL_SDP_USB_DEV=1
110 CONFIG_SDP_LOADADDR=0x80400000 110 CONFIG_SDP_LOADADDR=0x80400000
111
112 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
113 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
111 114
configs/imx8qm_mek_spl_fspi_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
4 CONFIG_TARGET_IMX8QM_MEK=y 4 CONFIG_TARGET_IMX8QM_MEK=y
5 CONFIG_SYS_TEXT_BASE=0x80020000 5 CONFIG_SYS_TEXT_BASE=0x80020000
6 CONFIG_CMD_IMPORTENV=n 6 CONFIG_CMD_IMPORTENV=n
7 CONFIG_SYS_MALLOC_F_LEN=0x2000 7 CONFIG_SYS_MALLOC_F_LEN=0x2000
8 CONFIG_DM=y 8 CONFIG_DM=y
9 CONFIG_CMD_CACHE=y 9 CONFIG_CMD_CACHE=y
10 10
11 CONFIG_DM_SERIAL=y 11 CONFIG_DM_SERIAL=y
12 CONFIG_FSL_LPUART=y 12 CONFIG_FSL_LPUART=y
13 CONFIG_OF_CONTROL=y 13 CONFIG_OF_CONTROL=y
14 CONFIG_DM_I2C=y 14 CONFIG_DM_I2C=y
15 # CONFIG_DM_I2C_COMPAT is not set 15 # CONFIG_DM_I2C_COMPAT is not set
16 CONFIG_SYS_I2C_IMX_LPI2C=y 16 CONFIG_SYS_I2C_IMX_LPI2C=y
17 CONFIG_CMD_I2C=y 17 CONFIG_CMD_I2C=y
18 18
19 CONFIG_SPL=y 19 CONFIG_SPL=y
20 CONFIG_SPL_GPIO_SUPPORT=y 20 CONFIG_SPL_GPIO_SUPPORT=y
21 CONFIG_SPL_MMC_SUPPORT=y 21 CONFIG_SPL_MMC_SUPPORT=y
22 CONFIG_FIT=y 22 CONFIG_FIT=y
23 CONFIG_SPL_LOAD_FIT=y 23 CONFIG_SPL_LOAD_FIT=y
24 CONFIG_SPL_BOARD_INIT=y 24 CONFIG_SPL_BOARD_INIT=y
25 CONFIG_SPL_TINY_MEMSET=y 25 CONFIG_SPL_TINY_MEMSET=y
26 CONFIG_SPL_MTD_SUPPORT=y 26 CONFIG_SPL_MTD_SUPPORT=y
27 CONFIG_SPL_OF_CONTROL=y 27 CONFIG_SPL_OF_CONTROL=y
28 CONFIG_SPL_SPI_FLASH_SUPPORT=y 28 CONFIG_SPL_SPI_FLASH_SUPPORT=y
29 CONFIG_SPL_SPI_SUPPORT=y 29 CONFIG_SPL_SPI_SUPPORT=y
30 CONFIG_SPL_NOR_SUPPORT=y 30 CONFIG_SPL_NOR_SUPPORT=y
31 CONFIG_PANIC_HANG=y 31 CONFIG_PANIC_HANG=y
32 CONFIG_FASTBOOT=y 32 CONFIG_FASTBOOT=y
33 CONFIG_USB_FUNCTION_FASTBOOT=y 33 CONFIG_USB_FUNCTION_FASTBOOT=y
34 CONFIG_CMD_FASTBOOT=y 34 CONFIG_CMD_FASTBOOT=y
35 CONFIG_ANDROID_BOOT_IMAGE=y 35 CONFIG_ANDROID_BOOT_IMAGE=y
36 CONFIG_FSL_FASTBOOT=y 36 CONFIG_FSL_FASTBOOT=y
37 CONFIG_FASTBOOT_BUF_ADDR=0x82800000 37 CONFIG_FASTBOOT_BUF_ADDR=0x82800000
38 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 38 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
39 CONFIG_FASTBOOT_FLASH=y 39 CONFIG_FASTBOOT_FLASH=y
40 CONFIG_FASTBOOT_FLASH_MMC_DEV=0 40 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
41 CONFIG_FASTBOOT_USB_DEV=1 41 CONFIG_FASTBOOT_USB_DEV=1
42 42
43 CONFIG_USB_XHCI_HCD=y 43 CONFIG_USB_XHCI_HCD=y
44 CONFIG_USB_XHCI_IMX8=y 44 CONFIG_USB_XHCI_IMX8=y
45 45
46 CONFIG_DM_USB=y 46 CONFIG_DM_USB=y
47 47
48 CONFIG_USB=y 48 CONFIG_USB=y
49 CONFIG_USB_TCPC=y 49 CONFIG_USB_TCPC=y
50 50
51 CONFIG_USB_GADGET=y 51 CONFIG_USB_GADGET=y
52 # CONFIG_CI_UDC=y 52 # CONFIG_CI_UDC=y
53 CONFIG_USB_GADGET_DOWNLOAD=y 53 CONFIG_USB_GADGET_DOWNLOAD=y
54 CONFIG_USB_GADGET_MANUFACTURER="FSL" 54 CONFIG_USB_GADGET_MANUFACTURER="FSL"
55 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 55 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
56 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 56 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
57 57
58 CONFIG_USB_CDNS3=y 58 CONFIG_USB_CDNS3=y
59 CONFIG_USB_CDNS3_GADGET=y 59 CONFIG_USB_CDNS3_GADGET=y
60 CONFIG_USB_GADGET_DUALSPEED=y 60 CONFIG_USB_GADGET_DUALSPEED=y
61 61
62 CONFIG_CMD_GPIO=y 62 CONFIG_CMD_GPIO=y
63 CONFIG_DM_GPIO=y 63 CONFIG_DM_GPIO=y
64 CONFIG_DM_PCA953X=y 64 CONFIG_DM_PCA953X=y
65 CONFIG_BOOTDELAY=3 65 CONFIG_BOOTDELAY=3
66 CONFIG_IMX_BOOTAUX=y 66 CONFIG_IMX_BOOTAUX=y
67 CONFIG_FS_FAT=y 67 CONFIG_FS_FAT=y
68 CONFIG_CMD_FAT=y 68 CONFIG_CMD_FAT=y
69 CONFIG_CMD_MMC=y 69 CONFIG_CMD_MMC=y
70 CONFIG_DM_MMC=y 70 CONFIG_DM_MMC=y
71 CONFIG_MMC_IO_VOLTAGE=y 71 CONFIG_MMC_IO_VOLTAGE=y
72 CONFIG_MMC_UHS_SUPPORT=y 72 CONFIG_MMC_UHS_SUPPORT=y
73 CONFIG_MMC_HS400_SUPPORT=y 73 CONFIG_MMC_HS400_SUPPORT=y
74 CONFIG_EFI_PARTITION=y 74 CONFIG_EFI_PARTITION=y
75 CONFIG_FSL_FSPI=y 75 CONFIG_FSL_FSPI=y
76 CONFIG_DM_SPI=y 76 CONFIG_DM_SPI=y
77 CONFIG_DM_SPI_FLASH=y 77 CONFIG_DM_SPI_FLASH=y
78 CONFIG_SPI_FLASH=y 78 CONFIG_SPI_FLASH=y
79 CONFIG_SPI_FLASH_4BYTES_ADDR=y 79 CONFIG_SPI_FLASH_4BYTES_ADDR=y
80 CONFIG_SPI_FLASH_STMICRO=y 80 CONFIG_SPI_FLASH_STMICRO=y
81 CONFIG_CMD_SF=y 81 CONFIG_CMD_SF=y
82 82
83 CONFIG_CMD_PING=y 83 CONFIG_CMD_PING=y
84 CONFIG_CMD_DHCP=y 84 CONFIG_CMD_DHCP=y
85 CONFIG_CMD_MII=y 85 CONFIG_CMD_MII=y
86 CONFIG_DM_ETH=y 86 CONFIG_DM_ETH=y
87 # CONFIG_EFI_LOADER is not set 87 # CONFIG_EFI_LOADER is not set
88 88
89 CONFIG_DM_REGULATOR=y 89 CONFIG_DM_REGULATOR=y
90 CONFIG_DM_REGULATOR_FIXED=y 90 CONFIG_DM_REGULATOR_FIXED=y
91 CONFIG_DM_REGULATOR_GPIO=y 91 CONFIG_DM_REGULATOR_GPIO=y
92 92
93 CONFIG_VIDEO=y 93 CONFIG_VIDEO=y
94 CONFIG_VIDEO_IMX_HDP_LOAD=y 94 CONFIG_VIDEO_IMX_HDP_LOAD=y
95 95
96 CONFIG_PINCTRL=y 96 CONFIG_PINCTRL=y
97 CONFIG_PINCTRL_IMX8=y 97 CONFIG_PINCTRL_IMX8=y
98 98
99 CONFIG_POWER_DOMAIN=y 99 CONFIG_POWER_DOMAIN=y
100 CONFIG_IMX8_POWER_DOMAIN=y 100 CONFIG_IMX8_POWER_DOMAIN=y
101 101
102 CONFIG_DM_THERMAL=y 102 CONFIG_DM_THERMAL=y
103 CONFIG_IMX_SC_THERMAL=y 103 CONFIG_IMX_SC_THERMAL=y
104 104
105 CONFIG_ENV_IS_IN_MMC=y 105 CONFIG_ENV_IS_IN_MMC=y
106 106
107 CONFIG_SMC_FUSE=y 107 CONFIG_SMC_FUSE=y
108 CONFIG_CMD_MEMTEST=y 108 CONFIG_CMD_MEMTEST=y
109 109
110 CONFIG_SPL_USB_HOST_SUPPORT=y 110 CONFIG_SPL_USB_HOST_SUPPORT=y
111 CONFIG_SPL_USB_GADGET_SUPPORT=y 111 CONFIG_SPL_USB_GADGET_SUPPORT=y
112 CONFIG_SPL_USB_SDP_SUPPORT=y 112 CONFIG_SPL_USB_SDP_SUPPORT=y
113 CONFIG_SPL_SDP_USB_DEV=1 113 CONFIG_SPL_SDP_USB_DEV=1
114 CONFIG_SDP_LOADADDR=0x80400000 114 CONFIG_SDP_LOADADDR=0x80400000
115
116 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
117 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
115 118
configs/imx8qm_mek_spl_trusty_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
4 CONFIG_TARGET_IMX8QM_MEK=y 4 CONFIG_TARGET_IMX8QM_MEK=y
5 CONFIG_SYS_TEXT_BASE=0x80020000 5 CONFIG_SYS_TEXT_BASE=0x80020000
6 CONFIG_CMD_IMPORTENV=n 6 CONFIG_CMD_IMPORTENV=n
7 CONFIG_SYS_MALLOC_F_LEN=0x2000 7 CONFIG_SYS_MALLOC_F_LEN=0x2000
8 CONFIG_DM=y 8 CONFIG_DM=y
9 CONFIG_CMD_CACHE=y 9 CONFIG_CMD_CACHE=y
10 10
11 CONFIG_DM_SERIAL=y 11 CONFIG_DM_SERIAL=y
12 CONFIG_FSL_LPUART=y 12 CONFIG_FSL_LPUART=y
13 CONFIG_OF_CONTROL=y 13 CONFIG_OF_CONTROL=y
14 CONFIG_DM_I2C=y 14 CONFIG_DM_I2C=y
15 # CONFIG_DM_I2C_COMPAT is not set 15 # CONFIG_DM_I2C_COMPAT is not set
16 CONFIG_SYS_I2C_IMX_LPI2C=y 16 CONFIG_SYS_I2C_IMX_LPI2C=y
17 CONFIG_CMD_I2C=y 17 CONFIG_CMD_I2C=y
18 18
19 CONFIG_SPL=y 19 CONFIG_SPL=y
20 CONFIG_SPL_GPIO_SUPPORT=y 20 CONFIG_SPL_GPIO_SUPPORT=y
21 CONFIG_SPL_MMC_SUPPORT=y 21 CONFIG_SPL_MMC_SUPPORT=y
22 CONFIG_FIT=y 22 CONFIG_FIT=y
23 CONFIG_SPL_LOAD_FIT=y 23 CONFIG_SPL_LOAD_FIT=y
24 CONFIG_SPL_BOARD_INIT=y 24 CONFIG_SPL_BOARD_INIT=y
25 CONFIG_SPL_TINY_MEMSET=y 25 CONFIG_SPL_TINY_MEMSET=y
26 CONFIG_SPL_OF_CONTROL=y 26 CONFIG_SPL_OF_CONTROL=y
27 27
28 CONFIG_USB_XHCI_HCD=y 28 CONFIG_USB_XHCI_HCD=y
29 CONFIG_USB_XHCI_IMX8=y 29 CONFIG_USB_XHCI_IMX8=y
30 30
31 CONFIG_DM_USB=y 31 CONFIG_DM_USB=y
32 32
33 CONFIG_USB=y 33 CONFIG_USB=y
34 CONFIG_USB_TCPC=y 34 CONFIG_USB_TCPC=y
35 35
36 CONFIG_USB_GADGET=y 36 CONFIG_USB_GADGET=y
37 #CONFIG_CI_UDC=y 37 #CONFIG_CI_UDC=y
38 CONFIG_USB_GADGET_DOWNLOAD=y 38 CONFIG_USB_GADGET_DOWNLOAD=y
39 CONFIG_USB_GADGET_MANUFACTURER="FSL" 39 CONFIG_USB_GADGET_MANUFACTURER="FSL"
40 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 40 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
41 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 41 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
42 42
43 CONFIG_USB_CDNS3=y 43 CONFIG_USB_CDNS3=y
44 CONFIG_USB_CDNS3_GADGET=y 44 CONFIG_USB_CDNS3_GADGET=y
45 CONFIG_USB_GADGET_DUALSPEED=y 45 CONFIG_USB_GADGET_DUALSPEED=y
46 46
47 CONFIG_CMD_GPIO=y 47 CONFIG_CMD_GPIO=y
48 CONFIG_DM_GPIO=y 48 CONFIG_DM_GPIO=y
49 CONFIG_DM_PCA953X=y 49 CONFIG_DM_PCA953X=y
50 CONFIG_BOOTDELAY=3 50 CONFIG_BOOTDELAY=3
51 CONFIG_IMX_BOOTAUX=y 51 CONFIG_IMX_BOOTAUX=y
52 CONFIG_FS_FAT=y 52 CONFIG_FS_FAT=y
53 CONFIG_CMD_FAT=y 53 CONFIG_CMD_FAT=y
54 CONFIG_CMD_MMC=y 54 CONFIG_CMD_MMC=y
55 CONFIG_DM_MMC=y 55 CONFIG_DM_MMC=y
56 CONFIG_MMC_IO_VOLTAGE=y 56 CONFIG_MMC_IO_VOLTAGE=y
57 CONFIG_MMC_UHS_SUPPORT=y 57 CONFIG_MMC_UHS_SUPPORT=y
58 CONFIG_MMC_HS400_SUPPORT=y 58 CONFIG_MMC_HS400_SUPPORT=y
59 CONFIG_EFI_PARTITION=y 59 CONFIG_EFI_PARTITION=y
60 CONFIG_FSL_FSPI=y 60 CONFIG_FSL_FSPI=y
61 CONFIG_DM_SPI=y 61 CONFIG_DM_SPI=y
62 CONFIG_DM_SPI_FLASH=y 62 CONFIG_DM_SPI_FLASH=y
63 CONFIG_SPI_FLASH=y 63 CONFIG_SPI_FLASH=y
64 CONFIG_SPI_FLASH_4BYTES_ADDR=y 64 CONFIG_SPI_FLASH_4BYTES_ADDR=y
65 CONFIG_SPI_FLASH_STMICRO=y 65 CONFIG_SPI_FLASH_STMICRO=y
66 CONFIG_CMD_SF=y 66 CONFIG_CMD_SF=y
67 67
68 CONFIG_CMD_PING=y 68 CONFIG_CMD_PING=y
69 CONFIG_CMD_DHCP=y 69 CONFIG_CMD_DHCP=y
70 CONFIG_CMD_MII=y 70 CONFIG_CMD_MII=y
71 CONFIG_DM_ETH=y 71 CONFIG_DM_ETH=y
72 # CONFIG_EFI_LOADER is not set 72 # CONFIG_EFI_LOADER is not set
73 73
74 CONFIG_DM_REGULATOR=y 74 CONFIG_DM_REGULATOR=y
75 CONFIG_DM_REGULATOR_FIXED=y 75 CONFIG_DM_REGULATOR_FIXED=y
76 CONFIG_DM_REGULATOR_GPIO=y 76 CONFIG_DM_REGULATOR_GPIO=y
77 77
78 CONFIG_VIDEO=y 78 CONFIG_VIDEO=y
79 CONFIG_VIDEO_IMX_HDP_LOAD=y 79 CONFIG_VIDEO_IMX_HDP_LOAD=y
80 80
81 CONFIG_PINCTRL=y 81 CONFIG_PINCTRL=y
82 CONFIG_PINCTRL_IMX8=y 82 CONFIG_PINCTRL_IMX8=y
83 83
84 CONFIG_POWER_DOMAIN=y 84 CONFIG_POWER_DOMAIN=y
85 CONFIG_IMX8_POWER_DOMAIN=y 85 CONFIG_IMX8_POWER_DOMAIN=y
86 86
87 CONFIG_DM_THERMAL=y 87 CONFIG_DM_THERMAL=y
88 CONFIG_IMX_SC_THERMAL=y 88 CONFIG_IMX_SC_THERMAL=y
89 89
90 CONFIG_ENV_IS_IN_MMC=y 90 CONFIG_ENV_IS_IN_MMC=y
91 91
92 CONFIG_SMC_FUSE=y 92 CONFIG_SMC_FUSE=y
93 CONFIG_CMD_MEMTEST=y 93 CONFIG_CMD_MEMTEST=y
94 CONFIG_IMX8_TRUSTY_XEN=y 94 CONFIG_IMX8_TRUSTY_XEN=y
95 95
96 CONFIG_SPL_ENV_SUPPORT=y 96 CONFIG_SPL_ENV_SUPPORT=y
97 CONFIG_SPL_LIBDISK_SUPPORT=y 97 CONFIG_SPL_LIBDISK_SUPPORT=y
98
99 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
100 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
98 101
configs/imx8qxp_17x17_val_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-17x17-val" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-17x17-val"
4 CONFIG_TARGET_IMX8X_17X17_VAL=y 4 CONFIG_TARGET_IMX8X_17X17_VAL=y
5 CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-17x17-val.dtb" 5 CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-17x17-val.dtb"
6 CONFIG_SYS_TEXT_BASE=0x80020000 6 CONFIG_SYS_TEXT_BASE=0x80020000
7 CONFIG_CMD_IMPORTENV=n 7 CONFIG_CMD_IMPORTENV=n
8 CONFIG_SYS_MALLOC_F_LEN=0x2000 8 CONFIG_SYS_MALLOC_F_LEN=0x2000
9 CONFIG_DM=y 9 CONFIG_DM=y
10 CONFIG_CMD_CACHE=y 10 CONFIG_CMD_CACHE=y
11 11
12 CONFIG_DM_SERIAL=y 12 CONFIG_DM_SERIAL=y
13 CONFIG_FSL_LPUART=y 13 CONFIG_FSL_LPUART=y
14 CONFIG_OF_CONTROL=y 14 CONFIG_OF_CONTROL=y
15 CONFIG_DM_I2C=y 15 CONFIG_DM_I2C=y
16 # CONFIG_DM_I2C_COMPAT is not set 16 # CONFIG_DM_I2C_COMPAT is not set
17 CONFIG_SYS_I2C_IMX_LPI2C=y 17 CONFIG_SYS_I2C_IMX_LPI2C=y
18 CONFIG_CMD_I2C=y 18 CONFIG_CMD_I2C=y
19 19
20 CONFIG_FASTBOOT=y 20 CONFIG_FASTBOOT=y
21 CONFIG_USB_FUNCTION_FASTBOOT=y 21 CONFIG_USB_FUNCTION_FASTBOOT=y
22 CONFIG_CMD_FASTBOOT=y 22 CONFIG_CMD_FASTBOOT=y
23 CONFIG_ANDROID_BOOT_IMAGE=y 23 CONFIG_ANDROID_BOOT_IMAGE=y
24 CONFIG_FSL_FASTBOOT=y 24 CONFIG_FSL_FASTBOOT=y
25 CONFIG_FASTBOOT_BUF_ADDR=0x82800000 25 CONFIG_FASTBOOT_BUF_ADDR=0x82800000
26 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 26 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
27 CONFIG_FASTBOOT_FLASH=y 27 CONFIG_FASTBOOT_FLASH=y
28 CONFIG_FASTBOOT_FLASH_MMC_DEV=0 28 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
29 CONFIG_FASTBOOT_USB_DEV=0 29 CONFIG_FASTBOOT_USB_DEV=0
30 30
31 CONFIG_USB_XHCI_HCD=y 31 CONFIG_USB_XHCI_HCD=y
32 CONFIG_USB_XHCI_IMX8=y 32 CONFIG_USB_XHCI_IMX8=y
33 33
34 CONFIG_DM_USB=y 34 CONFIG_DM_USB=y
35 CONFIG_USB_EHCI_HCD=y 35 CONFIG_USB_EHCI_HCD=y
36 36
37 CONFIG_CMD_USB=y 37 CONFIG_CMD_USB=y
38 CONFIG_USB=y 38 CONFIG_USB=y
39 CONFIG_USB_STORAGE=y 39 CONFIG_USB_STORAGE=y
40 40
41 CONFIG_CMD_USB_MASS_STORAGE=y 41 CONFIG_CMD_USB_MASS_STORAGE=y
42 CONFIG_USB_GADGET=y 42 CONFIG_USB_GADGET=y
43 CONFIG_CI_UDC=y 43 CONFIG_CI_UDC=y
44 CONFIG_USB_GADGET_DOWNLOAD=y 44 CONFIG_USB_GADGET_DOWNLOAD=y
45 CONFIG_USB_GADGET_MANUFACTURER="FSL" 45 CONFIG_USB_GADGET_MANUFACTURER="FSL"
46 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 46 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
47 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 47 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
48 48
49 # CONFIG_USB_CDNS3=y 49 # CONFIG_USB_CDNS3=y
50 # CONFIG_USB_CDNS3_GADGET=y 50 # CONFIG_USB_CDNS3_GADGET=y
51 # CONFIG_USB_GADGET_DUALSPEED=y 51 # CONFIG_USB_GADGET_DUALSPEED=y
52 52
53 CONFIG_CMD_GPIO=y 53 CONFIG_CMD_GPIO=y
54 CONFIG_DM_GPIO=y 54 CONFIG_DM_GPIO=y
55 CONFIG_DM_PCA953X=y 55 CONFIG_DM_PCA953X=y
56 CONFIG_BOOTDELAY=3 56 CONFIG_BOOTDELAY=3
57 CONFIG_IMX_BOOTAUX=y 57 CONFIG_IMX_BOOTAUX=y
58 CONFIG_FS_FAT=y 58 CONFIG_FS_FAT=y
59 CONFIG_CMD_FAT=y 59 CONFIG_CMD_FAT=y
60 CONFIG_CMD_MMC=y 60 CONFIG_CMD_MMC=y
61 CONFIG_DM_MMC=y 61 CONFIG_DM_MMC=y
62 CONFIG_MMC_IO_VOLTAGE=y 62 CONFIG_MMC_IO_VOLTAGE=y
63 CONFIG_MMC_UHS_SUPPORT=y 63 CONFIG_MMC_UHS_SUPPORT=y
64 CONFIG_MMC_HS400_ES_SUPPORT=y 64 CONFIG_MMC_HS400_ES_SUPPORT=y
65 CONFIG_EFI_PARTITION=y 65 CONFIG_EFI_PARTITION=y
66 66
67 CONFIG_FSL_FSPI=y 67 CONFIG_FSL_FSPI=y
68 CONFIG_DM_SPI=y 68 CONFIG_DM_SPI=y
69 CONFIG_DM_SPI_FLASH=y 69 CONFIG_DM_SPI_FLASH=y
70 CONFIG_SPI_FLASH=y 70 CONFIG_SPI_FLASH=y
71 CONFIG_SPI_FLASH_4BYTES_ADDR=y 71 CONFIG_SPI_FLASH_4BYTES_ADDR=y
72 CONFIG_SPI_FLASH_STMICRO=y 72 CONFIG_SPI_FLASH_STMICRO=y
73 CONFIG_CMD_SF=y 73 CONFIG_CMD_SF=y
74 74
75 CONFIG_CMD_PING=y 75 CONFIG_CMD_PING=y
76 CONFIG_CMD_DHCP=y 76 CONFIG_CMD_DHCP=y
77 CONFIG_CMD_MII=y 77 CONFIG_CMD_MII=y
78 CONFIG_DM_ETH=y 78 CONFIG_DM_ETH=y
79 # CONFIG_EFI_LOADER is not set 79 # CONFIG_EFI_LOADER is not set
80 80
81 CONFIG_DM_REGULATOR=y 81 CONFIG_DM_REGULATOR=y
82 CONFIG_DM_REGULATOR_FIXED=y 82 CONFIG_DM_REGULATOR_FIXED=y
83 CONFIG_DM_REGULATOR_GPIO=y 83 CONFIG_DM_REGULATOR_GPIO=y
84 84
85 CONFIG_VIDEO=y 85 CONFIG_VIDEO=y
86 86
87 CONFIG_PINCTRL=y 87 CONFIG_PINCTRL=y
88 CONFIG_PINCTRL_IMX8=y 88 CONFIG_PINCTRL_IMX8=y
89 89
90 CONFIG_POWER_DOMAIN=y 90 CONFIG_POWER_DOMAIN=y
91 CONFIG_IMX8_POWER_DOMAIN=y 91 CONFIG_IMX8_POWER_DOMAIN=y
92 92
93 CONFIG_DM_THERMAL=y 93 CONFIG_DM_THERMAL=y
94 CONFIG_IMX_SC_THERMAL=y 94 CONFIG_IMX_SC_THERMAL=y
95 95
96 CONFIG_ENV_IS_IN_MMC=y 96 CONFIG_ENV_IS_IN_MMC=y
97 97
98 CONFIG_SMC_FUSE=y 98 CONFIG_SMC_FUSE=y
99 CONFIG_CMD_MEMTEST=y 99 CONFIG_CMD_MEMTEST=y
100
101 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
102 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
100 103
configs/imx8qxp_ddr3_arm2_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2"
4 CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-ddr3l-val.dtb" 4 CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-ddr3l-val.dtb"
5 CONFIG_TARGET_IMX8QXP_DDR3_ARM2=y 5 CONFIG_TARGET_IMX8QXP_DDR3_ARM2=y
6 CONFIG_SYS_TEXT_BASE=0x80020000 6 CONFIG_SYS_TEXT_BASE=0x80020000
7 CONFIG_CMD_IMPORTENV=n 7 CONFIG_CMD_IMPORTENV=n
8 CONFIG_SYS_MALLOC_F_LEN=0x2000 8 CONFIG_SYS_MALLOC_F_LEN=0x2000
9 CONFIG_DM=y 9 CONFIG_DM=y
10 CONFIG_CMD_CACHE=y 10 CONFIG_CMD_CACHE=y
11 11
12 CONFIG_DM_SERIAL=y 12 CONFIG_DM_SERIAL=y
13 CONFIG_FSL_LPUART=y 13 CONFIG_FSL_LPUART=y
14 CONFIG_OF_CONTROL=y 14 CONFIG_OF_CONTROL=y
15 CONFIG_DM_I2C=y 15 CONFIG_DM_I2C=y
16 # CONFIG_DM_I2C_COMPAT is not set 16 # CONFIG_DM_I2C_COMPAT is not set
17 CONFIG_SYS_I2C_IMX_LPI2C=y 17 CONFIG_SYS_I2C_IMX_LPI2C=y
18 CONFIG_CMD_I2C=y 18 CONFIG_CMD_I2C=y
19 19
20 CONFIG_USB_XHCI_HCD=y 20 CONFIG_USB_XHCI_HCD=y
21 CONFIG_USB_XHCI_IMX8=y 21 CONFIG_USB_XHCI_IMX8=y
22 22
23 CONFIG_DM_USB=y 23 CONFIG_DM_USB=y
24 CONFIG_USB_EHCI_HCD=y 24 CONFIG_USB_EHCI_HCD=y
25 25
26 CONFIG_CMD_USB=y 26 CONFIG_CMD_USB=y
27 CONFIG_USB=y 27 CONFIG_USB=y
28 CONFIG_USB_STORAGE=y 28 CONFIG_USB_STORAGE=y
29 29
30 CONFIG_CMD_USB_MASS_STORAGE=y 30 CONFIG_CMD_USB_MASS_STORAGE=y
31 CONFIG_USB_GADGET=y 31 CONFIG_USB_GADGET=y
32 # CONFIG_CI_UDC=y 32 # CONFIG_CI_UDC=y
33 CONFIG_USB_GADGET_DOWNLOAD=y 33 CONFIG_USB_GADGET_DOWNLOAD=y
34 CONFIG_USB_GADGET_MANUFACTURER="FSL" 34 CONFIG_USB_GADGET_MANUFACTURER="FSL"
35 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 35 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
36 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 36 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
37 37
38 CONFIG_USB_CDNS3=y 38 CONFIG_USB_CDNS3=y
39 CONFIG_USB_CDNS3_GADGET=y 39 CONFIG_USB_CDNS3_GADGET=y
40 CONFIG_USB_GADGET_DUALSPEED=y 40 CONFIG_USB_GADGET_DUALSPEED=y
41 41
42 CONFIG_CMD_GPIO=y 42 CONFIG_CMD_GPIO=y
43 CONFIG_DM_GPIO=y 43 CONFIG_DM_GPIO=y
44 CONFIG_DM_PCA953X=y 44 CONFIG_DM_PCA953X=y
45 CONFIG_BOOTDELAY=3 45 CONFIG_BOOTDELAY=3
46 CONFIG_IMX_BOOTAUX=y 46 CONFIG_IMX_BOOTAUX=y
47 CONFIG_FS_FAT=y 47 CONFIG_FS_FAT=y
48 CONFIG_CMD_FAT=y 48 CONFIG_CMD_FAT=y
49 CONFIG_CMD_MMC=y 49 CONFIG_CMD_MMC=y
50 CONFIG_DM_MMC=y 50 CONFIG_DM_MMC=y
51 CONFIG_MMC_IO_VOLTAGE=y 51 CONFIG_MMC_IO_VOLTAGE=y
52 CONFIG_MMC_UHS_SUPPORT=y 52 CONFIG_MMC_UHS_SUPPORT=y
53 CONFIG_MMC_HS400_ES_SUPPORT=y 53 CONFIG_MMC_HS400_ES_SUPPORT=y
54 54
55 CONFIG_FSL_FSPI=y 55 CONFIG_FSL_FSPI=y
56 CONFIG_DM_SPI=y 56 CONFIG_DM_SPI=y
57 CONFIG_DM_SPI_FLASH=y 57 CONFIG_DM_SPI_FLASH=y
58 CONFIG_SPI_FLASH=y 58 CONFIG_SPI_FLASH=y
59 CONFIG_SPI_FLASH_4BYTES_ADDR=y 59 CONFIG_SPI_FLASH_4BYTES_ADDR=y
60 CONFIG_SPI_FLASH_STMICRO=y 60 CONFIG_SPI_FLASH_STMICRO=y
61 CONFIG_CMD_SF=y 61 CONFIG_CMD_SF=y
62 62
63 CONFIG_CMD_PING=y 63 CONFIG_CMD_PING=y
64 CONFIG_CMD_DHCP=y 64 CONFIG_CMD_DHCP=y
65 CONFIG_CMD_MII=y 65 CONFIG_CMD_MII=y
66 CONFIG_DM_ETH=y 66 CONFIG_DM_ETH=y
67 # CONFIG_EFI_LOADER is not set 67 # CONFIG_EFI_LOADER is not set
68 68
69 CONFIG_DM_REGULATOR=y 69 CONFIG_DM_REGULATOR=y
70 CONFIG_DM_REGULATOR_FIXED=y 70 CONFIG_DM_REGULATOR_FIXED=y
71 CONFIG_DM_REGULATOR_GPIO=y 71 CONFIG_DM_REGULATOR_GPIO=y
72 72
73 CONFIG_VIDEO=y 73 CONFIG_VIDEO=y
74 74
75 CONFIG_PINCTRL=y 75 CONFIG_PINCTRL=y
76 CONFIG_PINCTRL_IMX8=y 76 CONFIG_PINCTRL_IMX8=y
77 77
78 CONFIG_POWER_DOMAIN=y 78 CONFIG_POWER_DOMAIN=y
79 CONFIG_IMX8_POWER_DOMAIN=y 79 CONFIG_IMX8_POWER_DOMAIN=y
80 80
81 CONFIG_DM_THERMAL=y 81 CONFIG_DM_THERMAL=y
82 CONFIG_IMX_SC_THERMAL=y 82 CONFIG_IMX_SC_THERMAL=y
83 83
84 CONFIG_ENV_IS_IN_MMC=y 84 CONFIG_ENV_IS_IN_MMC=y
85 85
86 CONFIG_SMC_FUSE=y 86 CONFIG_SMC_FUSE=y
87 CONFIG_CMD_MEMTEST=y 87 CONFIG_CMD_MEMTEST=y
88
89 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
90 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
88 91
configs/imx8qxp_lpddr4_arm2_android_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2"
4 CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb" 4 CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb"
5 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT" 5 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT"
6 CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y 6 CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y
7 CONFIG_SYS_TEXT_BASE=0x80020000 7 CONFIG_SYS_TEXT_BASE=0x80020000
8 CONFIG_EFI_PARTITION=y 8 CONFIG_EFI_PARTITION=y
9 CONFIG_CMD_IMPORTENV=n 9 CONFIG_CMD_IMPORTENV=n
10 CONFIG_SYS_MALLOC_F_LEN=0x2000 10 CONFIG_SYS_MALLOC_F_LEN=0x2000
11 CONFIG_DM=y 11 CONFIG_DM=y
12 CONFIG_CMD_CACHE=y 12 CONFIG_CMD_CACHE=y
13 13
14 CONFIG_DM_SERIAL=y 14 CONFIG_DM_SERIAL=y
15 CONFIG_FSL_LPUART=y 15 CONFIG_FSL_LPUART=y
16 CONFIG_OF_CONTROL=y 16 CONFIG_OF_CONTROL=y
17 CONFIG_DM_I2C=y 17 CONFIG_DM_I2C=y
18 # CONFIG_DM_I2C_COMPAT is not set 18 # CONFIG_DM_I2C_COMPAT is not set
19 CONFIG_SYS_I2C_IMX_LPI2C=y 19 CONFIG_SYS_I2C_IMX_LPI2C=y
20 CONFIG_CMD_I2C=y 20 CONFIG_CMD_I2C=y
21 21
22 CONFIG_USB_XHCI_HCD=y 22 CONFIG_USB_XHCI_HCD=y
23 CONFIG_USB_XHCI_IMX8=y 23 CONFIG_USB_XHCI_IMX8=y
24 24
25 CONFIG_DM_USB=y 25 CONFIG_DM_USB=y
26 CONFIG_USB_EHCI_HCD=y 26 CONFIG_USB_EHCI_HCD=y
27 27
28 CONFIG_CMD_USB=y 28 CONFIG_CMD_USB=y
29 CONFIG_USB=y 29 CONFIG_USB=y
30 CONFIG_USB_STORAGE=y 30 CONFIG_USB_STORAGE=y
31 31
32 CONFIG_CMD_USB_MASS_STORAGE=y 32 CONFIG_CMD_USB_MASS_STORAGE=y
33 CONFIG_USB_GADGET=y 33 CONFIG_USB_GADGET=y
34 # CONFIG_CI_UDC=y 34 # CONFIG_CI_UDC=y
35 CONFIG_USB_GADGET_DOWNLOAD=y 35 CONFIG_USB_GADGET_DOWNLOAD=y
36 CONFIG_USB_GADGET_MANUFACTURER="FSL" 36 CONFIG_USB_GADGET_MANUFACTURER="FSL"
37 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 37 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
38 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 38 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02
39 39
40 CONFIG_USB_CDNS3=y 40 CONFIG_USB_CDNS3=y
41 CONFIG_USB_CDNS3_GADGET=y 41 CONFIG_USB_CDNS3_GADGET=y
42 CONFIG_USB_GADGET_DUALSPEED=y 42 CONFIG_USB_GADGET_DUALSPEED=y
43 43
44 CONFIG_CMD_GPIO=y 44 CONFIG_CMD_GPIO=y
45 CONFIG_DM_GPIO=y 45 CONFIG_DM_GPIO=y
46 CONFIG_DM_PCA953X=y 46 CONFIG_DM_PCA953X=y
47 CONFIG_BOOTDELAY=1 47 CONFIG_BOOTDELAY=1
48 CONFIG_IMX_BOOTAUX=y 48 CONFIG_IMX_BOOTAUX=y
49 CONFIG_FS_FAT=y 49 CONFIG_FS_FAT=y
50 CONFIG_CMD_FAT=y 50 CONFIG_CMD_FAT=y
51 CONFIG_CMD_MMC=y 51 CONFIG_CMD_MMC=y
52 CONFIG_DM_MMC=y 52 CONFIG_DM_MMC=y
53 CONFIG_MMC_IO_VOLTAGE=y 53 CONFIG_MMC_IO_VOLTAGE=y
54 CONFIG_MMC_UHS_SUPPORT=y 54 CONFIG_MMC_UHS_SUPPORT=y
55 CONFIG_MMC_HS400_ES_SUPPORT=y 55 CONFIG_MMC_HS400_ES_SUPPORT=y
56 56
57 CONFIG_FSL_FSPI=y 57 CONFIG_FSL_FSPI=y
58 CONFIG_DM_SPI=y 58 CONFIG_DM_SPI=y
59 CONFIG_DM_SPI_FLASH=y 59 CONFIG_DM_SPI_FLASH=y
60 CONFIG_SPI_FLASH=y 60 CONFIG_SPI_FLASH=y
61 CONFIG_SPI_FLASH_4BYTES_ADDR=y 61 CONFIG_SPI_FLASH_4BYTES_ADDR=y
62 CONFIG_SPI_FLASH_STMICRO=y 62 CONFIG_SPI_FLASH_STMICRO=y
63 CONFIG_CMD_SF=y 63 CONFIG_CMD_SF=y
64 64
65 CONFIG_CMD_PING=y 65 CONFIG_CMD_PING=y
66 CONFIG_CMD_DHCP=y 66 CONFIG_CMD_DHCP=y
67 CONFIG_CMD_MII=y 67 CONFIG_CMD_MII=y
68 CONFIG_DM_ETH=y 68 CONFIG_DM_ETH=y
69 # CONFIG_EFI_LOADER is not set 69 # CONFIG_EFI_LOADER is not set
70 70
71 CONFIG_DM_REGULATOR=y 71 CONFIG_DM_REGULATOR=y
72 CONFIG_DM_REGULATOR_FIXED=y 72 CONFIG_DM_REGULATOR_FIXED=y
73 CONFIG_DM_REGULATOR_GPIO=y 73 CONFIG_DM_REGULATOR_GPIO=y
74 74
75 CONFIG_VIDEO=y 75 CONFIG_VIDEO=y
76 76
77 CONFIG_PINCTRL=y 77 CONFIG_PINCTRL=y
78 CONFIG_PINCTRL_IMX8=y 78 CONFIG_PINCTRL_IMX8=y
79 79
80 CONFIG_POWER_DOMAIN=y 80 CONFIG_POWER_DOMAIN=y
81 CONFIG_IMX8_POWER_DOMAIN=y 81 CONFIG_IMX8_POWER_DOMAIN=y
82 82
83 CONFIG_DM_THERMAL=y 83 CONFIG_DM_THERMAL=y
84 CONFIG_IMX_SC_THERMAL=y 84 CONFIG_IMX_SC_THERMAL=y
85 85
86 CONFIG_ENV_IS_IN_MMC=y 86 CONFIG_ENV_IS_IN_MMC=y
87 87
88 CONFIG_SMC_FUSE=y 88 CONFIG_SMC_FUSE=y
89 CONFIG_CMD_MEMTEST=y 89 CONFIG_CMD_MEMTEST=y
90
91 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
92 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
90 93
configs/imx8qxp_lpddr4_arm2_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2"
4 CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb" 4 CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb"
5 CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y 5 CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y
6 CONFIG_SYS_TEXT_BASE=0x80020000 6 CONFIG_SYS_TEXT_BASE=0x80020000
7 CONFIG_CMD_IMPORTENV=n 7 CONFIG_CMD_IMPORTENV=n
8 CONFIG_SYS_MALLOC_F_LEN=0x2000 8 CONFIG_SYS_MALLOC_F_LEN=0x2000
9 CONFIG_DM=y 9 CONFIG_DM=y
10 CONFIG_CMD_CACHE=y 10 CONFIG_CMD_CACHE=y
11 11
12 CONFIG_DM_SERIAL=y 12 CONFIG_DM_SERIAL=y
13 CONFIG_FSL_LPUART=y 13 CONFIG_FSL_LPUART=y
14 CONFIG_OF_CONTROL=y 14 CONFIG_OF_CONTROL=y
15 CONFIG_DM_I2C=y 15 CONFIG_DM_I2C=y
16 # CONFIG_DM_I2C_COMPAT is not set 16 # CONFIG_DM_I2C_COMPAT is not set
17 CONFIG_SYS_I2C_IMX_LPI2C=y 17 CONFIG_SYS_I2C_IMX_LPI2C=y
18 CONFIG_CMD_I2C=y 18 CONFIG_CMD_I2C=y
19 19
20 CONFIG_USB_XHCI_HCD=y 20 CONFIG_USB_XHCI_HCD=y
21 CONFIG_USB_XHCI_IMX8=y 21 CONFIG_USB_XHCI_IMX8=y
22 22
23 CONFIG_DM_USB=y 23 CONFIG_DM_USB=y
24 CONFIG_USB_EHCI_HCD=y 24 CONFIG_USB_EHCI_HCD=y
25 25
26 CONFIG_CMD_USB=y 26 CONFIG_CMD_USB=y
27 CONFIG_USB=y 27 CONFIG_USB=y
28 CONFIG_USB_STORAGE=y 28 CONFIG_USB_STORAGE=y
29 29
30 CONFIG_CMD_USB_MASS_STORAGE=y 30 CONFIG_CMD_USB_MASS_STORAGE=y
31 CONFIG_USB_GADGET=y 31 CONFIG_USB_GADGET=y
32 # CONFIG_CI_UDC=y 32 # CONFIG_CI_UDC=y
33 CONFIG_USB_GADGET_DOWNLOAD=y 33 CONFIG_USB_GADGET_DOWNLOAD=y
34 CONFIG_USB_GADGET_MANUFACTURER="FSL" 34 CONFIG_USB_GADGET_MANUFACTURER="FSL"
35 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 35 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
36 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 36 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
37 37
38 CONFIG_USB_CDNS3=y 38 CONFIG_USB_CDNS3=y
39 CONFIG_USB_CDNS3_GADGET=y 39 CONFIG_USB_CDNS3_GADGET=y
40 CONFIG_USB_GADGET_DUALSPEED=y 40 CONFIG_USB_GADGET_DUALSPEED=y
41 41
42 CONFIG_CMD_GPIO=y 42 CONFIG_CMD_GPIO=y
43 CONFIG_DM_GPIO=y 43 CONFIG_DM_GPIO=y
44 CONFIG_DM_PCA953X=y 44 CONFIG_DM_PCA953X=y
45 CONFIG_BOOTDELAY=3 45 CONFIG_BOOTDELAY=3
46 CONFIG_IMX_BOOTAUX=y 46 CONFIG_IMX_BOOTAUX=y
47 CONFIG_FS_FAT=y 47 CONFIG_FS_FAT=y
48 CONFIG_CMD_FAT=y 48 CONFIG_CMD_FAT=y
49 CONFIG_CMD_MMC=y 49 CONFIG_CMD_MMC=y
50 CONFIG_DM_MMC=y 50 CONFIG_DM_MMC=y
51 CONFIG_MMC_IO_VOLTAGE=y 51 CONFIG_MMC_IO_VOLTAGE=y
52 CONFIG_MMC_UHS_SUPPORT=y 52 CONFIG_MMC_UHS_SUPPORT=y
53 CONFIG_MMC_HS400_ES_SUPPORT=y 53 CONFIG_MMC_HS400_ES_SUPPORT=y
54 54
55 CONFIG_FSL_FSPI=y 55 CONFIG_FSL_FSPI=y
56 CONFIG_DM_SPI=y 56 CONFIG_DM_SPI=y
57 CONFIG_DM_SPI_FLASH=y 57 CONFIG_DM_SPI_FLASH=y
58 CONFIG_SPI_FLASH=y 58 CONFIG_SPI_FLASH=y
59 CONFIG_SPI_FLASH_4BYTES_ADDR=y 59 CONFIG_SPI_FLASH_4BYTES_ADDR=y
60 CONFIG_SPI_FLASH_STMICRO=y 60 CONFIG_SPI_FLASH_STMICRO=y
61 CONFIG_CMD_SF=y 61 CONFIG_CMD_SF=y
62 62
63 CONFIG_CMD_PING=y 63 CONFIG_CMD_PING=y
64 CONFIG_CMD_DHCP=y 64 CONFIG_CMD_DHCP=y
65 CONFIG_CMD_MII=y 65 CONFIG_CMD_MII=y
66 CONFIG_DM_ETH=y 66 CONFIG_DM_ETH=y
67 # CONFIG_EFI_LOADER is not set 67 # CONFIG_EFI_LOADER is not set
68 68
69 CONFIG_DM_REGULATOR=y 69 CONFIG_DM_REGULATOR=y
70 CONFIG_DM_REGULATOR_FIXED=y 70 CONFIG_DM_REGULATOR_FIXED=y
71 CONFIG_DM_REGULATOR_GPIO=y 71 CONFIG_DM_REGULATOR_GPIO=y
72 72
73 CONFIG_VIDEO=y 73 CONFIG_VIDEO=y
74 74
75 CONFIG_PINCTRL=y 75 CONFIG_PINCTRL=y
76 CONFIG_PINCTRL_IMX8=y 76 CONFIG_PINCTRL_IMX8=y
77 77
78 CONFIG_POWER_DOMAIN=y 78 CONFIG_POWER_DOMAIN=y
79 CONFIG_IMX8_POWER_DOMAIN=y 79 CONFIG_IMX8_POWER_DOMAIN=y
80 80
81 CONFIG_DM_THERMAL=y 81 CONFIG_DM_THERMAL=y
82 CONFIG_IMX_SC_THERMAL=y 82 CONFIG_IMX_SC_THERMAL=y
83 83
84 CONFIG_ENV_IS_IN_MMC=y 84 CONFIG_ENV_IS_IN_MMC=y
85 85
86 CONFIG_SMC_FUSE=y 86 CONFIG_SMC_FUSE=y
87 CONFIG_CMD_MEMTEST=y 87 CONFIG_CMD_MEMTEST=y
88 88
89 CONFIG_FASTBOOT=y 89 CONFIG_FASTBOOT=y
90 CONFIG_USB_FUNCTION_FASTBOOT=y 90 CONFIG_USB_FUNCTION_FASTBOOT=y
91 CONFIG_CMD_FASTBOOT=y 91 CONFIG_CMD_FASTBOOT=y
92 CONFIG_ANDROID_BOOT_IMAGE=y 92 CONFIG_ANDROID_BOOT_IMAGE=y
93 CONFIG_FSL_FASTBOOT=y 93 CONFIG_FSL_FASTBOOT=y
94 CONFIG_FASTBOOT_BUF_ADDR=0x82800000 94 CONFIG_FASTBOOT_BUF_ADDR=0x82800000
95 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 95 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
96 CONFIG_FASTBOOT_FLASH=y 96 CONFIG_FASTBOOT_FLASH=y
97 CONFIG_FASTBOOT_FLASH_MMC_DEV=0 97 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
98 CONFIG_FASTBOOT_USB_DEV=1 98 CONFIG_FASTBOOT_USB_DEV=1
99 CONFIG_EFI_PARTITION=y 99 CONFIG_EFI_PARTITION=y
100
101 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
102 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
100 103
configs/imx8qxp_lpddr4_arm2_fspi_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2"
4 CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb" 4 CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb"
5 CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y 5 CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y
6 CONFIG_SYS_TEXT_BASE=0x80020000 6 CONFIG_SYS_TEXT_BASE=0x80020000
7 CONFIG_CMD_IMPORTENV=n 7 CONFIG_CMD_IMPORTENV=n
8 CONFIG_SYS_MALLOC_F_LEN=0x2000 8 CONFIG_SYS_MALLOC_F_LEN=0x2000
9 CONFIG_DM=y 9 CONFIG_DM=y
10 CONFIG_CMD_CACHE=y 10 CONFIG_CMD_CACHE=y
11 11
12 CONFIG_DM_SERIAL=y 12 CONFIG_DM_SERIAL=y
13 CONFIG_FSL_LPUART=y 13 CONFIG_FSL_LPUART=y
14 CONFIG_OF_CONTROL=y 14 CONFIG_OF_CONTROL=y
15 CONFIG_DM_I2C=y 15 CONFIG_DM_I2C=y
16 # CONFIG_DM_I2C_COMPAT is not set 16 # CONFIG_DM_I2C_COMPAT is not set
17 CONFIG_SYS_I2C_IMX_LPI2C=y 17 CONFIG_SYS_I2C_IMX_LPI2C=y
18 CONFIG_CMD_I2C=y 18 CONFIG_CMD_I2C=y
19 19
20 CONFIG_USB_XHCI_HCD=y 20 CONFIG_USB_XHCI_HCD=y
21 CONFIG_USB_XHCI_IMX8=y 21 CONFIG_USB_XHCI_IMX8=y
22 22
23 CONFIG_DM_USB=y 23 CONFIG_DM_USB=y
24 CONFIG_USB_EHCI_HCD=y 24 CONFIG_USB_EHCI_HCD=y
25 25
26 CONFIG_CMD_USB=y 26 CONFIG_CMD_USB=y
27 CONFIG_USB=y 27 CONFIG_USB=y
28 CONFIG_USB_STORAGE=y 28 CONFIG_USB_STORAGE=y
29 29
30 CONFIG_CMD_USB_MASS_STORAGE=y 30 CONFIG_CMD_USB_MASS_STORAGE=y
31 CONFIG_USB_GADGET=y 31 CONFIG_USB_GADGET=y
32 # CONFIG_CI_UDC=y 32 # CONFIG_CI_UDC=y
33 CONFIG_USB_GADGET_DOWNLOAD=y 33 CONFIG_USB_GADGET_DOWNLOAD=y
34 CONFIG_USB_GADGET_MANUFACTURER="FSL" 34 CONFIG_USB_GADGET_MANUFACTURER="FSL"
35 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 35 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
36 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 36 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
37 37
38 CONFIG_USB_CDNS3=y 38 CONFIG_USB_CDNS3=y
39 CONFIG_USB_CDNS3_GADGET=y 39 CONFIG_USB_CDNS3_GADGET=y
40 CONFIG_USB_GADGET_DUALSPEED=y 40 CONFIG_USB_GADGET_DUALSPEED=y
41 41
42 CONFIG_CMD_GPIO=y 42 CONFIG_CMD_GPIO=y
43 CONFIG_DM_GPIO=y 43 CONFIG_DM_GPIO=y
44 CONFIG_DM_PCA953X=y 44 CONFIG_DM_PCA953X=y
45 CONFIG_BOOTDELAY=3 45 CONFIG_BOOTDELAY=3
46 CONFIG_IMX_BOOTAUX=y 46 CONFIG_IMX_BOOTAUX=y
47 CONFIG_FS_FAT=y 47 CONFIG_FS_FAT=y
48 CONFIG_CMD_FAT=y 48 CONFIG_CMD_FAT=y
49 CONFIG_CMD_MMC=y 49 CONFIG_CMD_MMC=y
50 CONFIG_DM_MMC=y 50 CONFIG_DM_MMC=y
51 CONFIG_MMC_IO_VOLTAGE=y 51 CONFIG_MMC_IO_VOLTAGE=y
52 CONFIG_MMC_UHS_SUPPORT=y 52 CONFIG_MMC_UHS_SUPPORT=y
53 CONFIG_MMC_HS400_ES_SUPPORT=y 53 CONFIG_MMC_HS400_ES_SUPPORT=y
54 CONFIG_QSPI_BOOT=y 54 CONFIG_QSPI_BOOT=y
55 CONFIG_FSL_FSPI=y 55 CONFIG_FSL_FSPI=y
56 CONFIG_DM_SPI=y 56 CONFIG_DM_SPI=y
57 CONFIG_DM_SPI_FLASH=y 57 CONFIG_DM_SPI_FLASH=y
58 CONFIG_SPI_FLASH=y 58 CONFIG_SPI_FLASH=y
59 CONFIG_SPI_FLASH_4BYTES_ADDR=y 59 CONFIG_SPI_FLASH_4BYTES_ADDR=y
60 CONFIG_SPI_FLASH_STMICRO=y 60 CONFIG_SPI_FLASH_STMICRO=y
61 CONFIG_CMD_SF=y 61 CONFIG_CMD_SF=y
62 62
63 CONFIG_CMD_PING=y 63 CONFIG_CMD_PING=y
64 CONFIG_CMD_DHCP=y 64 CONFIG_CMD_DHCP=y
65 CONFIG_CMD_MII=y 65 CONFIG_CMD_MII=y
66 CONFIG_DM_ETH=y 66 CONFIG_DM_ETH=y
67 # CONFIG_EFI_LOADER is not set 67 # CONFIG_EFI_LOADER is not set
68 68
69 CONFIG_DM_REGULATOR=y 69 CONFIG_DM_REGULATOR=y
70 CONFIG_DM_REGULATOR_FIXED=y 70 CONFIG_DM_REGULATOR_FIXED=y
71 CONFIG_DM_REGULATOR_GPIO=y 71 CONFIG_DM_REGULATOR_GPIO=y
72 72
73 CONFIG_VIDEO=y 73 CONFIG_VIDEO=y
74 74
75 CONFIG_PINCTRL=y 75 CONFIG_PINCTRL=y
76 CONFIG_PINCTRL_IMX8=y 76 CONFIG_PINCTRL_IMX8=y
77 77
78 CONFIG_POWER_DOMAIN=y 78 CONFIG_POWER_DOMAIN=y
79 CONFIG_IMX8_POWER_DOMAIN=y 79 CONFIG_IMX8_POWER_DOMAIN=y
80 80
81 CONFIG_DM_THERMAL=y 81 CONFIG_DM_THERMAL=y
82 CONFIG_IMX_SC_THERMAL=y 82 CONFIG_IMX_SC_THERMAL=y
83 83
84 CONFIG_ENV_IS_IN_SPI_FLASH=y 84 CONFIG_ENV_IS_IN_SPI_FLASH=y
85 85
86 CONFIG_SMC_FUSE=y 86 CONFIG_SMC_FUSE=y
87 CONFIG_CMD_MEMTEST=y 87 CONFIG_CMD_MEMTEST=y
88
89 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
90 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
88 91
configs/imx8qxp_lpddr4_arm2_nand_defconfig
Diff comments   View file @ 57fa56f
1 1
2 CONFIG_ARM=y 2 CONFIG_ARM=y
3 CONFIG_ARCH_IMX8=y 3 CONFIG_ARCH_IMX8=y
4 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2" 4 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2"
5 CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb" 5 CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb"
6 CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y 6 CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y
7 CONFIG_SYS_TEXT_BASE=0x80020000 7 CONFIG_SYS_TEXT_BASE=0x80020000
8 CONFIG_CMD_IMPORTENV=n 8 CONFIG_CMD_IMPORTENV=n
9 CONFIG_SYS_MALLOC_F_LEN=0x2000 9 CONFIG_SYS_MALLOC_F_LEN=0x2000
10 CONFIG_DM=y 10 CONFIG_DM=y
11 CONFIG_CMD_CACHE=y 11 CONFIG_CMD_CACHE=y
12 12
13 CONFIG_DM_SERIAL=y 13 CONFIG_DM_SERIAL=y
14 CONFIG_FSL_LPUART=y 14 CONFIG_FSL_LPUART=y
15 CONFIG_OF_CONTROL=y 15 CONFIG_OF_CONTROL=y
16 CONFIG_DM_I2C=y 16 CONFIG_DM_I2C=y
17 # CONFIG_DM_I2C_COMPAT is not set 17 # CONFIG_DM_I2C_COMPAT is not set
18 CONFIG_SYS_I2C_IMX_LPI2C=y 18 CONFIG_SYS_I2C_IMX_LPI2C=y
19 CONFIG_CMD_I2C=y 19 CONFIG_CMD_I2C=y
20 20
21 CONFIG_USB_XHCI_HCD=y 21 CONFIG_USB_XHCI_HCD=y
22 CONFIG_USB_XHCI_IMX8=y 22 CONFIG_USB_XHCI_IMX8=y
23 23
24 CONFIG_DM_USB=y 24 CONFIG_DM_USB=y
25 CONFIG_USB_EHCI_HCD=y 25 CONFIG_USB_EHCI_HCD=y
26 26
27 CONFIG_CMD_USB=y 27 CONFIG_CMD_USB=y
28 CONFIG_USB=y 28 CONFIG_USB=y
29 CONFIG_USB_STORAGE=y 29 CONFIG_USB_STORAGE=y
30 30
31 CONFIG_CMD_USB_MASS_STORAGE=y 31 CONFIG_CMD_USB_MASS_STORAGE=y
32 CONFIG_USB_GADGET=y 32 CONFIG_USB_GADGET=y
33 # CONFIG_CI_UDC=y 33 # CONFIG_CI_UDC=y
34 CONFIG_USB_GADGET_DOWNLOAD=y 34 CONFIG_USB_GADGET_DOWNLOAD=y
35 CONFIG_USB_GADGET_MANUFACTURER="FSL" 35 CONFIG_USB_GADGET_MANUFACTURER="FSL"
36 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 36 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
37 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 37 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
38 38
39 CONFIG_USB_CDNS3=y 39 CONFIG_USB_CDNS3=y
40 CONFIG_USB_CDNS3_GADGET=y 40 CONFIG_USB_CDNS3_GADGET=y
41 CONFIG_USB_GADGET_DUALSPEED=y 41 CONFIG_USB_GADGET_DUALSPEED=y
42 42
43 CONFIG_CMD_GPIO=y 43 CONFIG_CMD_GPIO=y
44 CONFIG_DM_GPIO=y 44 CONFIG_DM_GPIO=y
45 CONFIG_DM_PCA953X=y 45 CONFIG_DM_PCA953X=y
46 CONFIG_BOOTDELAY=3 46 CONFIG_BOOTDELAY=3
47 CONFIG_IMX_BOOTAUX=y 47 CONFIG_IMX_BOOTAUX=y
48 CONFIG_FS_FAT=y 48 CONFIG_FS_FAT=y
49 CONFIG_CMD_FAT=y 49 CONFIG_CMD_FAT=y
50 CONFIG_NAND_BOOT=y 50 CONFIG_NAND_BOOT=y
51 CONFIG_CMD_NAND=y 51 CONFIG_CMD_NAND=y
52 CONFIG_FSL_FSPI=y 52 CONFIG_FSL_FSPI=y
53 CONFIG_DM_SPI=y 53 CONFIG_DM_SPI=y
54 CONFIG_DM_SPI_FLASH=y 54 CONFIG_DM_SPI_FLASH=y
55 CONFIG_SPI_FLASH=y 55 CONFIG_SPI_FLASH=y
56 CONFIG_SPI_FLASH_4BYTES_ADDR=y 56 CONFIG_SPI_FLASH_4BYTES_ADDR=y
57 CONFIG_SPI_FLASH_STMICRO=y 57 CONFIG_SPI_FLASH_STMICRO=y
58 CONFIG_CMD_SF=y 58 CONFIG_CMD_SF=y
59 59
60 CONFIG_CMD_PING=y 60 CONFIG_CMD_PING=y
61 CONFIG_CMD_DHCP=y 61 CONFIG_CMD_DHCP=y
62 CONFIG_CMD_MII=y 62 CONFIG_CMD_MII=y
63 CONFIG_DM_ETH=y 63 CONFIG_DM_ETH=y
64 # CONFIG_EFI_LOADER is not set 64 # CONFIG_EFI_LOADER is not set
65 65
66 CONFIG_DM_REGULATOR=y 66 CONFIG_DM_REGULATOR=y
67 CONFIG_DM_REGULATOR_FIXED=y 67 CONFIG_DM_REGULATOR_FIXED=y
68 CONFIG_DM_REGULATOR_GPIO=y 68 CONFIG_DM_REGULATOR_GPIO=y
69 69
70 CONFIG_VIDEO=y 70 CONFIG_VIDEO=y
71 71
72 CONFIG_PINCTRL=y 72 CONFIG_PINCTRL=y
73 CONFIG_PINCTRL_IMX8=y 73 CONFIG_PINCTRL_IMX8=y
74 74
75 CONFIG_POWER_DOMAIN=y 75 CONFIG_POWER_DOMAIN=y
76 CONFIG_IMX8_POWER_DOMAIN=y 76 CONFIG_IMX8_POWER_DOMAIN=y
77 77
78 CONFIG_DM_THERMAL=y 78 CONFIG_DM_THERMAL=y
79 CONFIG_IMX_SC_THERMAL=y 79 CONFIG_IMX_SC_THERMAL=y
80 80
81 CONFIG_ENV_IS_IN_NAND=y 81 CONFIG_ENV_IS_IN_NAND=y
82 82
83 CONFIG_SMC_FUSE=y 83 CONFIG_SMC_FUSE=y
84 CONFIG_CMD_MEMTEST=y 84 CONFIG_CMD_MEMTEST=y
85 85
86 CONFIG_FASTBOOT=y 86 CONFIG_FASTBOOT=y
87 CONFIG_USB_FUNCTION_FASTBOOT=y 87 CONFIG_USB_FUNCTION_FASTBOOT=y
88 CONFIG_CMD_FASTBOOT=y 88 CONFIG_CMD_FASTBOOT=y
89 CONFIG_ANDROID_BOOT_IMAGE=y 89 CONFIG_ANDROID_BOOT_IMAGE=y
90 CONFIG_FSL_FASTBOOT=y 90 CONFIG_FSL_FASTBOOT=y
91 CONFIG_FASTBOOT_BUF_ADDR=0x82800000 91 CONFIG_FASTBOOT_BUF_ADDR=0x82800000
92 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 92 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
93 CONFIG_FASTBOOT_FLASH=y 93 CONFIG_FASTBOOT_FLASH=y
94 CONFIG_FASTBOOT_FLASH_MMC_DEV=0 94 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
95 CONFIG_FASTBOOT_USB_DEV=1 95 CONFIG_FASTBOOT_USB_DEV=1
96 CONFIG_EFI_PARTITION=y 96 CONFIG_EFI_PARTITION=y
97
98 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
99 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
97 100
configs/imx8qxp_lpddr4_arm2_spl_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2"
4 CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb" 4 CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb"
5 CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y 5 CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y
6 CONFIG_SYS_TEXT_BASE=0x80020000 6 CONFIG_SYS_TEXT_BASE=0x80020000
7 CONFIG_CMD_IMPORTENV=n 7 CONFIG_CMD_IMPORTENV=n
8 CONFIG_SYS_MALLOC_F_LEN=0x2000 8 CONFIG_SYS_MALLOC_F_LEN=0x2000
9 CONFIG_DM=y 9 CONFIG_DM=y
10 CONFIG_CMD_CACHE=y 10 CONFIG_CMD_CACHE=y
11 11
12 CONFIG_DM_SERIAL=y 12 CONFIG_DM_SERIAL=y
13 CONFIG_FSL_LPUART=y 13 CONFIG_FSL_LPUART=y
14 CONFIG_OF_CONTROL=y 14 CONFIG_OF_CONTROL=y
15 CONFIG_DM_I2C=y 15 CONFIG_DM_I2C=y
16 # CONFIG_DM_I2C_COMPAT is not set 16 # CONFIG_DM_I2C_COMPAT is not set
17 CONFIG_SYS_I2C_IMX_LPI2C=y 17 CONFIG_SYS_I2C_IMX_LPI2C=y
18 CONFIG_CMD_I2C=y 18 CONFIG_CMD_I2C=y
19 19
20 CONFIG_SPL=y 20 CONFIG_SPL=y
21 CONFIG_SPL_GPIO_SUPPORT=y 21 CONFIG_SPL_GPIO_SUPPORT=y
22 CONFIG_SPL_MMC_SUPPORT=y 22 CONFIG_SPL_MMC_SUPPORT=y
23 CONFIG_SPL_BOARD_INIT=y 23 CONFIG_SPL_BOARD_INIT=y
24 CONFIG_SPL_SYS_MALLOC_SIMPLE=y 24 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
25 CONFIG_SPL_TINY_MEMSET=y 25 CONFIG_SPL_TINY_MEMSET=y
26 CONFIG_SPL_OF_CONTROL=y 26 CONFIG_SPL_OF_CONTROL=y
27 27
28 CONFIG_USB_XHCI_HCD=y 28 CONFIG_USB_XHCI_HCD=y
29 CONFIG_USB_XHCI_IMX8=y 29 CONFIG_USB_XHCI_IMX8=y
30 30
31 CONFIG_DM_USB=y 31 CONFIG_DM_USB=y
32 CONFIG_USB_EHCI_HCD=y 32 CONFIG_USB_EHCI_HCD=y
33 33
34 CONFIG_CMD_USB=y 34 CONFIG_CMD_USB=y
35 CONFIG_USB=y 35 CONFIG_USB=y
36 CONFIG_USB_STORAGE=y 36 CONFIG_USB_STORAGE=y
37 37
38 CONFIG_CMD_USB_MASS_STORAGE=y 38 CONFIG_CMD_USB_MASS_STORAGE=y
39 CONFIG_USB_GADGET=y 39 CONFIG_USB_GADGET=y
40 # CONFIG_CI_UDC=y 40 # CONFIG_CI_UDC=y
41 CONFIG_USB_GADGET_DOWNLOAD=y 41 CONFIG_USB_GADGET_DOWNLOAD=y
42 CONFIG_USB_GADGET_MANUFACTURER="FSL" 42 CONFIG_USB_GADGET_MANUFACTURER="FSL"
43 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 43 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
44 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 44 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
45 45
46 CONFIG_USB_CDNS3=y 46 CONFIG_USB_CDNS3=y
47 CONFIG_USB_CDNS3_GADGET=y 47 CONFIG_USB_CDNS3_GADGET=y
48 CONFIG_USB_GADGET_DUALSPEED=y 48 CONFIG_USB_GADGET_DUALSPEED=y
49 49
50 CONFIG_CMD_GPIO=y 50 CONFIG_CMD_GPIO=y
51 CONFIG_DM_GPIO=y 51 CONFIG_DM_GPIO=y
52 CONFIG_DM_PCA953X=y 52 CONFIG_DM_PCA953X=y
53 CONFIG_BOOTDELAY=3 53 CONFIG_BOOTDELAY=3
54 CONFIG_IMX_BOOTAUX=y 54 CONFIG_IMX_BOOTAUX=y
55 CONFIG_FS_FAT=y 55 CONFIG_FS_FAT=y
56 CONFIG_CMD_FAT=y 56 CONFIG_CMD_FAT=y
57 CONFIG_CMD_MMC=y 57 CONFIG_CMD_MMC=y
58 CONFIG_DM_MMC=y 58 CONFIG_DM_MMC=y
59 CONFIG_MMC_IO_VOLTAGE=y 59 CONFIG_MMC_IO_VOLTAGE=y
60 CONFIG_MMC_UHS_SUPPORT=y 60 CONFIG_MMC_UHS_SUPPORT=y
61 CONFIG_MMC_HS400_ES_SUPPORT=y 61 CONFIG_MMC_HS400_ES_SUPPORT=y
62 62
63 CONFIG_FSL_FSPI=y 63 CONFIG_FSL_FSPI=y
64 CONFIG_DM_SPI=y 64 CONFIG_DM_SPI=y
65 CONFIG_DM_SPI_FLASH=y 65 CONFIG_DM_SPI_FLASH=y
66 CONFIG_SPI_FLASH=y 66 CONFIG_SPI_FLASH=y
67 CONFIG_SPI_FLASH_4BYTES_ADDR=y 67 CONFIG_SPI_FLASH_4BYTES_ADDR=y
68 CONFIG_SPI_FLASH_STMICRO=y 68 CONFIG_SPI_FLASH_STMICRO=y
69 CONFIG_CMD_SF=y 69 CONFIG_CMD_SF=y
70 70
71 CONFIG_CMD_PING=y 71 CONFIG_CMD_PING=y
72 CONFIG_CMD_DHCP=y 72 CONFIG_CMD_DHCP=y
73 CONFIG_CMD_MII=y 73 CONFIG_CMD_MII=y
74 CONFIG_DM_ETH=y 74 CONFIG_DM_ETH=y
75 # CONFIG_EFI_LOADER is not set 75 # CONFIG_EFI_LOADER is not set
76 76
77 CONFIG_DM_REGULATOR=y 77 CONFIG_DM_REGULATOR=y
78 CONFIG_DM_REGULATOR_FIXED=y 78 CONFIG_DM_REGULATOR_FIXED=y
79 CONFIG_DM_REGULATOR_GPIO=y 79 CONFIG_DM_REGULATOR_GPIO=y
80 80
81 CONFIG_VIDEO=y 81 CONFIG_VIDEO=y
82 82
83 CONFIG_PINCTRL=y 83 CONFIG_PINCTRL=y
84 CONFIG_PINCTRL_IMX8=y 84 CONFIG_PINCTRL_IMX8=y
85 85
86 CONFIG_POWER_DOMAIN=y 86 CONFIG_POWER_DOMAIN=y
87 CONFIG_IMX8_POWER_DOMAIN=y 87 CONFIG_IMX8_POWER_DOMAIN=y
88 88
89 CONFIG_DM_THERMAL=y 89 CONFIG_DM_THERMAL=y
90 CONFIG_IMX_SC_THERMAL=y 90 CONFIG_IMX_SC_THERMAL=y
91 91
92 CONFIG_ENV_IS_IN_MMC=y 92 CONFIG_ENV_IS_IN_MMC=y
93 CONFIG_DM_DEVICE_REMOVE=n 93 CONFIG_DM_DEVICE_REMOVE=n
94 94
95 CONFIG_SMC_FUSE=y 95 CONFIG_SMC_FUSE=y
96 CONFIG_CMD_MEMTEST=y 96 CONFIG_CMD_MEMTEST=y
97 97
98 CONFIG_FASTBOOT=y 98 CONFIG_FASTBOOT=y
99 CONFIG_USB_FUNCTION_FASTBOOT=y 99 CONFIG_USB_FUNCTION_FASTBOOT=y
100 CONFIG_CMD_FASTBOOT=y 100 CONFIG_CMD_FASTBOOT=y
101 CONFIG_ANDROID_BOOT_IMAGE=y 101 CONFIG_ANDROID_BOOT_IMAGE=y
102 CONFIG_FSL_FASTBOOT=y 102 CONFIG_FSL_FASTBOOT=y
103 CONFIG_FASTBOOT_BUF_ADDR=0x82800000 103 CONFIG_FASTBOOT_BUF_ADDR=0x82800000
104 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 104 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
105 CONFIG_FASTBOOT_FLASH=y 105 CONFIG_FASTBOOT_FLASH=y
106 CONFIG_FASTBOOT_FLASH_MMC_DEV=0 106 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
107 CONFIG_FASTBOOT_USB_DEV=1 107 CONFIG_FASTBOOT_USB_DEV=1
108 CONFIG_EFI_PARTITION=y 108 CONFIG_EFI_PARTITION=y
109
110 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
111 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
109 112
configs/imx8qxp_lpddr4_arm2_spl_nand_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2"
4 CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb" 4 CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-lpddr4-arm2.dtb"
5 CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y 5 CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y
6 CONFIG_SYS_TEXT_BASE=0x80020000 6 CONFIG_SYS_TEXT_BASE=0x80020000
7 CONFIG_CMD_IMPORTENV=n 7 CONFIG_CMD_IMPORTENV=n
8 CONFIG_SYS_MALLOC_F_LEN=0x20000 8 CONFIG_SYS_MALLOC_F_LEN=0x20000
9 CONFIG_DM=y 9 CONFIG_DM=y
10 CONFIG_CMD_CACHE=y 10 CONFIG_CMD_CACHE=y
11 11
12 CONFIG_DM_SERIAL=y 12 CONFIG_DM_SERIAL=y
13 CONFIG_FSL_LPUART=y 13 CONFIG_FSL_LPUART=y
14 CONFIG_OF_CONTROL=y 14 CONFIG_OF_CONTROL=y
15 CONFIG_DM_I2C=y 15 CONFIG_DM_I2C=y
16 # CONFIG_DM_I2C_COMPAT is not set 16 # CONFIG_DM_I2C_COMPAT is not set
17 CONFIG_SYS_I2C_IMX_LPI2C=y 17 CONFIG_SYS_I2C_IMX_LPI2C=y
18 CONFIG_CMD_I2C=y 18 CONFIG_CMD_I2C=y
19 19
20 CONFIG_SPL=y 20 CONFIG_SPL=y
21 CONFIG_SPL_GPIO_SUPPORT=y 21 CONFIG_SPL_GPIO_SUPPORT=y
22 CONFIG_SPL_MMC_SUPPORT=y 22 CONFIG_SPL_MMC_SUPPORT=y
23 CONFIG_SPL_BOARD_INIT=y 23 CONFIG_SPL_BOARD_INIT=y
24 CONFIG_SPL_TINY_MEMSET=y 24 CONFIG_SPL_TINY_MEMSET=y
25 CONFIG_SPL_OF_CONTROL=y 25 CONFIG_SPL_OF_CONTROL=y
26 26
27 CONFIG_USB_XHCI_HCD=y 27 CONFIG_USB_XHCI_HCD=y
28 CONFIG_USB_XHCI_IMX8=y 28 CONFIG_USB_XHCI_IMX8=y
29 29
30 CONFIG_DM_USB=y 30 CONFIG_DM_USB=y
31 CONFIG_USB_EHCI_HCD=y 31 CONFIG_USB_EHCI_HCD=y
32 32
33 CONFIG_CMD_USB=y 33 CONFIG_CMD_USB=y
34 CONFIG_USB=y 34 CONFIG_USB=y
35 CONFIG_USB_STORAGE=y 35 CONFIG_USB_STORAGE=y
36 36
37 CONFIG_CMD_USB_MASS_STORAGE=y 37 CONFIG_CMD_USB_MASS_STORAGE=y
38 CONFIG_USB_GADGET=y 38 CONFIG_USB_GADGET=y
39 # CONFIG_CI_UDC=y 39 # CONFIG_CI_UDC=y
40 CONFIG_USB_GADGET_DOWNLOAD=y 40 CONFIG_USB_GADGET_DOWNLOAD=y
41 CONFIG_USB_GADGET_MANUFACTURER="FSL" 41 CONFIG_USB_GADGET_MANUFACTURER="FSL"
42 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 42 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
43 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 43 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
44 44
45 CONFIG_USB_CDNS3=y 45 CONFIG_USB_CDNS3=y
46 CONFIG_USB_CDNS3_GADGET=y 46 CONFIG_USB_CDNS3_GADGET=y
47 CONFIG_USB_GADGET_DUALSPEED=y 47 CONFIG_USB_GADGET_DUALSPEED=y
48 48
49 CONFIG_CMD_GPIO=y 49 CONFIG_CMD_GPIO=y
50 CONFIG_DM_GPIO=y 50 CONFIG_DM_GPIO=y
51 CONFIG_DM_PCA953X=y 51 CONFIG_DM_PCA953X=y
52 CONFIG_BOOTDELAY=3 52 CONFIG_BOOTDELAY=3
53 CONFIG_IMX_BOOTAUX=y 53 CONFIG_IMX_BOOTAUX=y
54 CONFIG_FS_FAT=y 54 CONFIG_FS_FAT=y
55 CONFIG_CMD_FAT=y 55 CONFIG_CMD_FAT=y
56 CONFIG_NAND_BOOT=y 56 CONFIG_NAND_BOOT=y
57 CONFIG_CMD_NAND=y 57 CONFIG_CMD_NAND=y
58 58
59 CONFIG_FSL_FSPI=y 59 CONFIG_FSL_FSPI=y
60 CONFIG_DM_SPI=y 60 CONFIG_DM_SPI=y
61 CONFIG_DM_SPI_FLASH=y 61 CONFIG_DM_SPI_FLASH=y
62 CONFIG_SPI_FLASH=y 62 CONFIG_SPI_FLASH=y
63 CONFIG_SPI_FLASH_4BYTES_ADDR=y 63 CONFIG_SPI_FLASH_4BYTES_ADDR=y
64 CONFIG_SPI_FLASH_STMICRO=y 64 CONFIG_SPI_FLASH_STMICRO=y
65 CONFIG_CMD_SF=y 65 CONFIG_CMD_SF=y
66 66
67 CONFIG_CMD_PING=y 67 CONFIG_CMD_PING=y
68 CONFIG_CMD_DHCP=y 68 CONFIG_CMD_DHCP=y
69 CONFIG_CMD_MII=y 69 CONFIG_CMD_MII=y
70 CONFIG_DM_ETH=y 70 CONFIG_DM_ETH=y
71 # CONFIG_EFI_LOADER is not set 71 # CONFIG_EFI_LOADER is not set
72 72
73 CONFIG_DM_REGULATOR=y 73 CONFIG_DM_REGULATOR=y
74 CONFIG_DM_REGULATOR_FIXED=y 74 CONFIG_DM_REGULATOR_FIXED=y
75 CONFIG_DM_REGULATOR_GPIO=y 75 CONFIG_DM_REGULATOR_GPIO=y
76 76
77 CONFIG_VIDEO=y 77 CONFIG_VIDEO=y
78 78
79 CONFIG_PINCTRL=y 79 CONFIG_PINCTRL=y
80 CONFIG_PINCTRL_IMX8=y 80 CONFIG_PINCTRL_IMX8=y
81 81
82 CONFIG_POWER_DOMAIN=y 82 CONFIG_POWER_DOMAIN=y
83 CONFIG_IMX8_POWER_DOMAIN=y 83 CONFIG_IMX8_POWER_DOMAIN=y
84 84
85 CONFIG_DM_THERMAL=y 85 CONFIG_DM_THERMAL=y
86 CONFIG_IMX_SC_THERMAL=y 86 CONFIG_IMX_SC_THERMAL=y
87 87
88 CONFIG_ENV_IS_IN_NAND=y 88 CONFIG_ENV_IS_IN_NAND=y
89 89
90 CONFIG_SMC_FUSE=y 90 CONFIG_SMC_FUSE=y
91 CONFIG_CMD_MEMTEST=y 91 CONFIG_CMD_MEMTEST=y
92 92
93 CONFIG_FASTBOOT=y 93 CONFIG_FASTBOOT=y
94 CONFIG_USB_FUNCTION_FASTBOOT=y 94 CONFIG_USB_FUNCTION_FASTBOOT=y
95 CONFIG_CMD_FASTBOOT=y 95 CONFIG_CMD_FASTBOOT=y
96 CONFIG_ANDROID_BOOT_IMAGE=y 96 CONFIG_ANDROID_BOOT_IMAGE=y
97 CONFIG_FSL_FASTBOOT=y 97 CONFIG_FSL_FASTBOOT=y
98 CONFIG_FASTBOOT_BUF_ADDR=0x82800000 98 CONFIG_FASTBOOT_BUF_ADDR=0x82800000
99 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 99 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
100 CONFIG_FASTBOOT_FLASH=y 100 CONFIG_FASTBOOT_FLASH=y
101 CONFIG_FASTBOOT_FLASH_MMC_DEV=0 101 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
102 CONFIG_FASTBOOT_USB_DEV=1 102 CONFIG_FASTBOOT_USB_DEV=1
103 CONFIG_EFI_PARTITION=y 103 CONFIG_EFI_PARTITION=y
104
105 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
106 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
104 107
configs/imx8qxp_mek_android_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT" 4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT"
5 CONFIG_TARGET_IMX8QXP_MEK=y 5 CONFIG_TARGET_IMX8QXP_MEK=y
6 CONFIG_SYS_TEXT_BASE=0x80020000 6 CONFIG_SYS_TEXT_BASE=0x80020000
7 CONFIG_EFI_PARTITION=y 7 CONFIG_EFI_PARTITION=y
8 CONFIG_CMD_IMPORTENV=n 8 CONFIG_CMD_IMPORTENV=n
9 CONFIG_SYS_MALLOC_F_LEN=0x2000 9 CONFIG_SYS_MALLOC_F_LEN=0x2000
10 CONFIG_DM=y 10 CONFIG_DM=y
11 CONFIG_CMD_CACHE=y 11 CONFIG_CMD_CACHE=y
12 12
13 CONFIG_DM_SERIAL=y 13 CONFIG_DM_SERIAL=y
14 CONFIG_FSL_LPUART=y 14 CONFIG_FSL_LPUART=y
15 CONFIG_OF_CONTROL=y 15 CONFIG_OF_CONTROL=y
16 CONFIG_DM_I2C=y 16 CONFIG_DM_I2C=y
17 # CONFIG_DM_I2C_COMPAT is not set 17 # CONFIG_DM_I2C_COMPAT is not set
18 CONFIG_SYS_I2C_IMX_LPI2C=y 18 CONFIG_SYS_I2C_IMX_LPI2C=y
19 CONFIG_CMD_I2C=y 19 CONFIG_CMD_I2C=y
20 CONFIG_I2C_MUX=y 20 CONFIG_I2C_MUX=y
21 CONFIG_I2C_MUX_PCA954x=y 21 CONFIG_I2C_MUX_PCA954x=y
22 22
23 CONFIG_USB_XHCI_HCD=y 23 CONFIG_USB_XHCI_HCD=y
24 CONFIG_USB_XHCI_IMX8=y 24 CONFIG_USB_XHCI_IMX8=y
25 25
26 CONFIG_DM_USB=y 26 CONFIG_DM_USB=y
27 27
28 CONFIG_USB=y 28 CONFIG_USB=y
29 CONFIG_USB_TCPC=y 29 CONFIG_USB_TCPC=y
30 30
31 CONFIG_USB_GADGET=y 31 CONFIG_USB_GADGET=y
32 # CONFIG_CI_UDC=y 32 # CONFIG_CI_UDC=y
33 CONFIG_USB_GADGET_DOWNLOAD=y 33 CONFIG_USB_GADGET_DOWNLOAD=y
34 CONFIG_USB_GADGET_MANUFACTURER="FSL" 34 CONFIG_USB_GADGET_MANUFACTURER="FSL"
35 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 35 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
36 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 36 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02
37 37
38 CONFIG_USB_CDNS3=y 38 CONFIG_USB_CDNS3=y
39 CONFIG_USB_CDNS3_GADGET=y 39 CONFIG_USB_CDNS3_GADGET=y
40 CONFIG_USB_GADGET_DUALSPEED=y 40 CONFIG_USB_GADGET_DUALSPEED=y
41 41
42 CONFIG_CMD_GPIO=y 42 CONFIG_CMD_GPIO=y
43 CONFIG_DM_GPIO=y 43 CONFIG_DM_GPIO=y
44 CONFIG_DM_PCA953X=y 44 CONFIG_DM_PCA953X=y
45 CONFIG_BOOTDELAY=1 45 CONFIG_BOOTDELAY=1
46 CONFIG_IMX_BOOTAUX=y 46 CONFIG_IMX_BOOTAUX=y
47 CONFIG_FS_FAT=y 47 CONFIG_FS_FAT=y
48 CONFIG_CMD_FAT=y 48 CONFIG_CMD_FAT=y
49 CONFIG_CMD_MMC=y 49 CONFIG_CMD_MMC=y
50 CONFIG_DM_MMC=y 50 CONFIG_DM_MMC=y
51 CONFIG_MMC_IO_VOLTAGE=y 51 CONFIG_MMC_IO_VOLTAGE=y
52 CONFIG_MMC_UHS_SUPPORT=y 52 CONFIG_MMC_UHS_SUPPORT=y
53 CONFIG_MMC_HS400_SUPPORT=y 53 CONFIG_MMC_HS400_SUPPORT=y
54 CONFIG_FSL_FSPI=y 54 CONFIG_FSL_FSPI=y
55 CONFIG_DM_SPI=y 55 CONFIG_DM_SPI=y
56 CONFIG_DM_SPI_FLASH=y 56 CONFIG_DM_SPI_FLASH=y
57 CONFIG_SPI_FLASH=y 57 CONFIG_SPI_FLASH=y
58 CONFIG_SPI_FLASH_4BYTES_ADDR=y 58 CONFIG_SPI_FLASH_4BYTES_ADDR=y
59 CONFIG_SPI_FLASH_STMICRO=y 59 CONFIG_SPI_FLASH_STMICRO=y
60 CONFIG_CMD_SF=y 60 CONFIG_CMD_SF=y
61 61
62 CONFIG_CMD_PING=y 62 CONFIG_CMD_PING=y
63 CONFIG_CMD_DHCP=y 63 CONFIG_CMD_DHCP=y
64 CONFIG_CMD_MII=y 64 CONFIG_CMD_MII=y
65 CONFIG_DM_ETH=y 65 CONFIG_DM_ETH=y
66 # CONFIG_EFI_LOADER is not set 66 # CONFIG_EFI_LOADER is not set
67 67
68 CONFIG_DM_REGULATOR=y 68 CONFIG_DM_REGULATOR=y
69 CONFIG_DM_REGULATOR_FIXED=y 69 CONFIG_DM_REGULATOR_FIXED=y
70 CONFIG_DM_REGULATOR_GPIO=y 70 CONFIG_DM_REGULATOR_GPIO=y
71 CONFIG_VIDEO=y 71 CONFIG_VIDEO=y
72 72
73 CONFIG_PINCTRL=y 73 CONFIG_PINCTRL=y
74 CONFIG_PINCTRL_IMX8=y 74 CONFIG_PINCTRL_IMX8=y
75 75
76 CONFIG_POWER_DOMAIN=y 76 CONFIG_POWER_DOMAIN=y
77 CONFIG_IMX8_POWER_DOMAIN=y 77 CONFIG_IMX8_POWER_DOMAIN=y
78 78
79 CONFIG_DM_THERMAL=y 79 CONFIG_DM_THERMAL=y
80 CONFIG_IMX_SC_THERMAL=y 80 CONFIG_IMX_SC_THERMAL=y
81 81
82 CONFIG_ENV_IS_IN_MMC=y 82 CONFIG_ENV_IS_IN_MMC=y
83 CONFIG_LZ4=y 83 CONFIG_LZ4=y
84 84
85 CONFIG_SMC_FUSE=y 85 CONFIG_SMC_FUSE=y
86 CONFIG_CMD_MEMTEST=y 86 CONFIG_CMD_MEMTEST=y
87 87
88 CONFIG_SPL=y 88 CONFIG_SPL=y
89 CONFIG_SPL_MMC_SUPPORT=y 89 CONFIG_SPL_MMC_SUPPORT=y
90 CONFIG_SPL_GPIO_SUPPORT=y 90 CONFIG_SPL_GPIO_SUPPORT=y
91 91
92 CONFIG_NOT_UUU_BUILD=y 92 CONFIG_NOT_UUU_BUILD=y
93 CONFIG_APPEND_BOOTARGS=y 93 CONFIG_APPEND_BOOTARGS=y
94 94
95 CONFIG_SYS_I2C_IMX_VIRT_I2C=y 95 CONFIG_SYS_I2C_IMX_VIRT_I2C=y
96 CONFIG_I2C_MUX_IMX_VIRT=y 96 CONFIG_I2C_MUX_IMX_VIRT=y
97 CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000 97 CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000
98
99 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
100 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000
98 101
configs/imx8qxp_mek_android_uuu_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT" 4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_SUPPORT"
5 CONFIG_TARGET_IMX8QXP_MEK=y 5 CONFIG_TARGET_IMX8QXP_MEK=y
6 CONFIG_SYS_TEXT_BASE=0x80020000 6 CONFIG_SYS_TEXT_BASE=0x80020000
7 CONFIG_EFI_PARTITION=y 7 CONFIG_EFI_PARTITION=y
8 CONFIG_CMD_IMPORTENV=n 8 CONFIG_CMD_IMPORTENV=n
9 CONFIG_SYS_MALLOC_F_LEN=0x2000 9 CONFIG_SYS_MALLOC_F_LEN=0x2000
10 CONFIG_DM=y 10 CONFIG_DM=y
11 CONFIG_CMD_CACHE=y 11 CONFIG_CMD_CACHE=y
12 12
13 CONFIG_DM_SERIAL=y 13 CONFIG_DM_SERIAL=y
14 CONFIG_FSL_LPUART=y 14 CONFIG_FSL_LPUART=y
15 CONFIG_OF_CONTROL=y 15 CONFIG_OF_CONTROL=y
16 CONFIG_DM_I2C=y 16 CONFIG_DM_I2C=y
17 # CONFIG_DM_I2C_COMPAT is not set 17 # CONFIG_DM_I2C_COMPAT is not set
18 CONFIG_SYS_I2C_IMX_LPI2C=y 18 CONFIG_SYS_I2C_IMX_LPI2C=y
19 CONFIG_CMD_I2C=y 19 CONFIG_CMD_I2C=y
20 CONFIG_I2C_MUX=y 20 CONFIG_I2C_MUX=y
21 CONFIG_I2C_MUX_PCA954x=y 21 CONFIG_I2C_MUX_PCA954x=y
22 22
23 CONFIG_USB_XHCI_HCD=y 23 CONFIG_USB_XHCI_HCD=y
24 CONFIG_USB_XHCI_IMX8=y 24 CONFIG_USB_XHCI_IMX8=y
25 25
26 CONFIG_DM_USB=y 26 CONFIG_DM_USB=y
27 27
28 CONFIG_USB=y 28 CONFIG_USB=y
29 CONFIG_USB_TCPC=y 29 CONFIG_USB_TCPC=y
30 30
31 CONFIG_USB_GADGET=y 31 CONFIG_USB_GADGET=y
32 # CONFIG_CI_UDC=y 32 # CONFIG_CI_UDC=y
33 CONFIG_USB_GADGET_DOWNLOAD=y 33 CONFIG_USB_GADGET_DOWNLOAD=y
34 CONFIG_USB_GADGET_MANUFACTURER="FSL" 34 CONFIG_USB_GADGET_MANUFACTURER="FSL"
35 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 35 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
36 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 36 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02
37 37
38 CONFIG_USB_CDNS3=y 38 CONFIG_USB_CDNS3=y
39 CONFIG_USB_CDNS3_GADGET=y 39 CONFIG_USB_CDNS3_GADGET=y
40 CONFIG_USB_GADGET_DUALSPEED=y 40 CONFIG_USB_GADGET_DUALSPEED=y
41 41
42 CONFIG_CMD_GPIO=y 42 CONFIG_CMD_GPIO=y
43 CONFIG_DM_GPIO=y 43 CONFIG_DM_GPIO=y
44 CONFIG_DM_PCA953X=y 44 CONFIG_DM_PCA953X=y
45 CONFIG_BOOTDELAY=1 45 CONFIG_BOOTDELAY=1
46 CONFIG_IMX_BOOTAUX=y 46 CONFIG_IMX_BOOTAUX=y
47 CONFIG_FS_FAT=y 47 CONFIG_FS_FAT=y
48 CONFIG_CMD_FAT=y 48 CONFIG_CMD_FAT=y
49 CONFIG_CMD_MMC=y 49 CONFIG_CMD_MMC=y
50 CONFIG_DM_MMC=y 50 CONFIG_DM_MMC=y
51 CONFIG_MMC_IO_VOLTAGE=y 51 CONFIG_MMC_IO_VOLTAGE=y
52 CONFIG_MMC_UHS_SUPPORT=y 52 CONFIG_MMC_UHS_SUPPORT=y
53 CONFIG_MMC_HS400_SUPPORT=y 53 CONFIG_MMC_HS400_SUPPORT=y
54 CONFIG_FSL_FSPI=y 54 CONFIG_FSL_FSPI=y
55 CONFIG_DM_SPI=y 55 CONFIG_DM_SPI=y
56 CONFIG_DM_SPI_FLASH=y 56 CONFIG_DM_SPI_FLASH=y
57 CONFIG_SPI_FLASH=y 57 CONFIG_SPI_FLASH=y
58 CONFIG_SPI_FLASH_4BYTES_ADDR=y 58 CONFIG_SPI_FLASH_4BYTES_ADDR=y
59 CONFIG_SPI_FLASH_STMICRO=y 59 CONFIG_SPI_FLASH_STMICRO=y
60 CONFIG_CMD_SF=y 60 CONFIG_CMD_SF=y
61 61
62 CONFIG_CMD_PING=y 62 CONFIG_CMD_PING=y
63 CONFIG_CMD_DHCP=y 63 CONFIG_CMD_DHCP=y
64 CONFIG_CMD_MII=y 64 CONFIG_CMD_MII=y
65 CONFIG_DM_ETH=y 65 CONFIG_DM_ETH=y
66 # CONFIG_EFI_LOADER is not set 66 # CONFIG_EFI_LOADER is not set
67 67
68 CONFIG_DM_REGULATOR=y 68 CONFIG_DM_REGULATOR=y
69 CONFIG_DM_REGULATOR_FIXED=y 69 CONFIG_DM_REGULATOR_FIXED=y
70 CONFIG_DM_REGULATOR_GPIO=y 70 CONFIG_DM_REGULATOR_GPIO=y
71 CONFIG_VIDEO=y 71 CONFIG_VIDEO=y
72 72
73 CONFIG_PINCTRL=y 73 CONFIG_PINCTRL=y
74 CONFIG_PINCTRL_IMX8=y 74 CONFIG_PINCTRL_IMX8=y
75 75
76 CONFIG_POWER_DOMAIN=y 76 CONFIG_POWER_DOMAIN=y
77 CONFIG_IMX8_POWER_DOMAIN=y 77 CONFIG_IMX8_POWER_DOMAIN=y
78 78
79 CONFIG_DM_THERMAL=y 79 CONFIG_DM_THERMAL=y
80 CONFIG_IMX_SC_THERMAL=y 80 CONFIG_IMX_SC_THERMAL=y
81 81
82 CONFIG_ENV_IS_IN_MMC=y 82 CONFIG_ENV_IS_IN_MMC=y
83 CONFIG_LZ4=y 83 CONFIG_LZ4=y
84 84
85 CONFIG_SMC_FUSE=y 85 CONFIG_SMC_FUSE=y
86 CONFIG_CMD_MEMTEST=y 86 CONFIG_CMD_MEMTEST=y
87
88 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
89 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
87 90
configs/imx8qxp_mek_androidauto2_trusty_defconfig
Diff comments   View file @ 57fa56f
File was created 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek-auto"
4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT"
5 CONFIG_TARGET_IMX8QXP_MEK=y
6 CONFIG_SYS_TEXT_BASE=0x80020000
7 CONFIG_EFI_PARTITION=y
8 CONFIG_SYS_MALLOC_F_LEN=0x2000
9 CONFIG_DM=y
10 CONFIG_DM_WARN=n
11 CONFIG_DM_DEVICE_REMOVE=n
12 CONFIG_IMX_TRUSTY_OS=y
13
14 CONFIG_DM_SERIAL=y
15 CONFIG_FSL_LPUART=y
16 CONFIG_OF_CONTROL=y
17 CONFIG_DM_I2C=y
18 # CONFIG_DM_I2C_COMPAT is not set
19 CONFIG_SYS_I2C_IMX_LPI2C=y
20 CONFIG_CMD_I2C=n
21 CONFIG_I2C_MUX=y
22 CONFIG_I2C_MUX_PCA954x=y
23
24 CONFIG_USB_XHCI_HCD=y
25 CONFIG_USB_XHCI_IMX8=y
26
27 CONFIG_DM_USB=y
28
29 CONFIG_USB=y
30
31 CONFIG_USB_GADGET=y
32 #CONFIG_CI_UDC=y
33 CONFIG_USB_GADGET_DOWNLOAD=y
34 CONFIG_USB_GADGET_MANUFACTURER="FSL"
35 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
36 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02
37
38 CONFIG_USB_CDNS3=y
39 CONFIG_USB_CDNS3_GADGET=y
40 CONFIG_USB_GADGET_DUALSPEED=y
41
42 CONFIG_DM_GPIO=y
43 CONFIG_DM_PCA953X=y
44 CONFIG_BOOTDELAY=1
45 CONFIG_CMD_MMC=y
46 CONFIG_DM_MMC=y
47 CONFIG_MMC_IO_VOLTAGE=y
48 CONFIG_MMC_UHS_SUPPORT=y
49 CONFIG_MMC_HS400_SUPPORT=y
50 CONFIG_FSL_FSPI=y
51 CONFIG_DM_SPI=y
52 CONFIG_DM_SPI_FLASH=y
53 CONFIG_SPI_FLASH=y
54 CONFIG_SPI_FLASH_4BYTES_ADDR=y
55 CONFIG_SPI_FLASH_STMICRO=y
56
57 CONFIG_DM_REGULATOR=y
58 CONFIG_DM_REGULATOR_FIXED=y
59 CONFIG_DM_REGULATOR_GPIO=y
60
61 CONFIG_PINCTRL=y
62 CONFIG_PINCTRL_IMX8=y
63
64 CONFIG_CMD_NET=n
65 CONFIG_CMD_NFS=n
66 CONFIG_CMD_BDI=n
67 CONFIG_CMD_CONSOLE=n
68 CONFIG_CMD_BOOTD=n
69 CONFIG_CMD_BOOTEFI=n
70 CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n
71 CONFIG_CMD_ELF=n
72 CONFIG_CMD_GO=n
73 CONFIG_CMD_RUN=n
74 CONFIG_CMD_IMI=n
75 CONFIG_CMD_IMLS=n
76 CONFIG_CMD_XIMG=n
77 CONFIG_CMD_EXPORTENV=n
78 CONFIG_CMD_IMPORTENV=n
79 CONFIG_CMD_EDITENV=n
80 CONFIG_CMD_ENV_EXISTS=n
81 CONFIG_CMD_CRC32=n
82 CONFIG_CMD_DM=n
83 CONFIG_CMD_LOADB=n
84 CONFIG_CMD_LOADS=n
85 CONFIG_CMD_FLASH=n
86 CONFIG_CMD_GPT=n
87 CONFIG_CMD_FPGA=n
88 CONFIG_CMD_ECHO=n
89 CONFIG_CMD_ITEST=n
90 CONFIG_CMD_SOURCE=n
91 CONFIG_CMD_SETEXPR=n
92 CONFIG_CMD_MISC=n
93 CONFIG_CMD_UNZIP=n
94 CONFIG_CMD_LZMADEC=n
95 CONFIG_CMD_SAVEENV=n
96
97 CONFIG_DISPLAY_CPUINFO=n
98 CONFIG_DISPLAY_BOARDINFO=n
99 CONFIG_EFI_LOADER=n
100
101 CONFIG_POWER_DOMAIN=y
102 CONFIG_IMX8_POWER_DOMAIN=y
103
104 CONFIG_DM_THERMAL=y
105 CONFIG_IMX_SC_THERMAL=y
106
107 CONFIG_ENV_IS_IN_MMC=y
108 CONFIG_LZ4=y
109
110 CONFIG_SMC_FUSE=y
111 CONFIG_CMD_MEMTEST=y
112
113 CONFIG_SPL=y
114 CONFIG_SPL_MMC_SUPPORT=y
115 CONFIG_SPL_GPIO_SUPPORT=y
116
117 CONFIG_SPL_ENV_SUPPORT=y
118 CONFIG_SPL_LIBDISK_SUPPORT=y
119
120 CONFIG_NOT_UUU_BUILD=y
121 CONFIG_SHA256=y
122 CONFIG_SPL_MMC_WRITE=y
123 CONFIG_DUAL_BOOTLOADER=y
124 CONFIG_APPEND_BOOTARGS=y
125
126 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
127 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000
128
configs/imx8qxp_mek_androidauto_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek-auto" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek-auto"
4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT" 4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT"
5 CONFIG_TARGET_IMX8QXP_MEK=y 5 CONFIG_TARGET_IMX8QXP_MEK=y
6 CONFIG_SYS_TEXT_BASE=0x80020000 6 CONFIG_SYS_TEXT_BASE=0x80020000
7 CONFIG_EFI_PARTITION=y 7 CONFIG_EFI_PARTITION=y
8 CONFIG_SYS_MALLOC_F_LEN=0x2000 8 CONFIG_SYS_MALLOC_F_LEN=0x2000
9 CONFIG_DM=y 9 CONFIG_DM=y
10 CONFIG_DM_WARN=n 10 CONFIG_DM_WARN=n
11 CONFIG_DM_DEVICE_REMOVE=n 11 CONFIG_DM_DEVICE_REMOVE=n
12 12
13 CONFIG_DM_SERIAL=y 13 CONFIG_DM_SERIAL=y
14 CONFIG_FSL_LPUART=y 14 CONFIG_FSL_LPUART=y
15 CONFIG_OF_CONTROL=y 15 CONFIG_OF_CONTROL=y
16 CONFIG_DM_I2C=y 16 CONFIG_DM_I2C=y
17 # CONFIG_DM_I2C_COMPAT is not set 17 # CONFIG_DM_I2C_COMPAT is not set
18 CONFIG_SYS_I2C_IMX_LPI2C=y 18 CONFIG_SYS_I2C_IMX_LPI2C=y
19 CONFIG_CMD_I2C=n 19 CONFIG_CMD_I2C=n
20 CONFIG_I2C_MUX=y 20 CONFIG_I2C_MUX=y
21 CONFIG_I2C_MUX_PCA954x=y 21 CONFIG_I2C_MUX_PCA954x=y
22 22
23 CONFIG_USB_XHCI_HCD=y 23 CONFIG_USB_XHCI_HCD=y
24 CONFIG_USB_XHCI_IMX8=y 24 CONFIG_USB_XHCI_IMX8=y
25 25
26 CONFIG_DM_USB=y 26 CONFIG_DM_USB=y
27 27
28 CONFIG_USB=y 28 CONFIG_USB=y
29 29
30 CONFIG_USB_GADGET=y 30 CONFIG_USB_GADGET=y
31 #CONFIG_CI_UDC=y 31 #CONFIG_CI_UDC=y
32 CONFIG_USB_GADGET_DOWNLOAD=y 32 CONFIG_USB_GADGET_DOWNLOAD=y
33 CONFIG_USB_GADGET_MANUFACTURER="FSL" 33 CONFIG_USB_GADGET_MANUFACTURER="FSL"
34 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 34 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
35 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 35 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02
36 36
37 CONFIG_USB_CDNS3=y 37 CONFIG_USB_CDNS3=y
38 CONFIG_USB_CDNS3_GADGET=y 38 CONFIG_USB_CDNS3_GADGET=y
39 CONFIG_USB_GADGET_DUALSPEED=y 39 CONFIG_USB_GADGET_DUALSPEED=y
40 40
41 CONFIG_DM_GPIO=y 41 CONFIG_DM_GPIO=y
42 CONFIG_DM_PCA953X=y 42 CONFIG_DM_PCA953X=y
43 CONFIG_BOOTDELAY=1 43 CONFIG_BOOTDELAY=1
44 CONFIG_CMD_MMC=y 44 CONFIG_CMD_MMC=y
45 CONFIG_DM_MMC=y 45 CONFIG_DM_MMC=y
46 CONFIG_MMC_IO_VOLTAGE=y 46 CONFIG_MMC_IO_VOLTAGE=y
47 CONFIG_MMC_UHS_SUPPORT=y 47 CONFIG_MMC_UHS_SUPPORT=y
48 CONFIG_MMC_HS400_SUPPORT=y 48 CONFIG_MMC_HS400_SUPPORT=y
49 CONFIG_FSL_FSPI=y 49 CONFIG_FSL_FSPI=y
50 CONFIG_DM_SPI=y 50 CONFIG_DM_SPI=y
51 CONFIG_DM_SPI_FLASH=y 51 CONFIG_DM_SPI_FLASH=y
52 CONFIG_SPI_FLASH=y 52 CONFIG_SPI_FLASH=y
53 CONFIG_SPI_FLASH_4BYTES_ADDR=y 53 CONFIG_SPI_FLASH_4BYTES_ADDR=y
54 CONFIG_SPI_FLASH_STMICRO=y 54 CONFIG_SPI_FLASH_STMICRO=y
55 55
56 CONFIG_DM_REGULATOR=y 56 CONFIG_DM_REGULATOR=y
57 CONFIG_DM_REGULATOR_FIXED=y 57 CONFIG_DM_REGULATOR_FIXED=y
58 CONFIG_DM_REGULATOR_GPIO=y 58 CONFIG_DM_REGULATOR_GPIO=y
59 59
60 CONFIG_PINCTRL=y 60 CONFIG_PINCTRL=y
61 CONFIG_PINCTRL_IMX8=y 61 CONFIG_PINCTRL_IMX8=y
62 62
63 CONFIG_CMD_NET=n 63 CONFIG_CMD_NET=n
64 CONFIG_CMD_NFS=n 64 CONFIG_CMD_NFS=n
65 CONFIG_CMD_BDI=n 65 CONFIG_CMD_BDI=n
66 CONFIG_CMD_CONSOLE=n 66 CONFIG_CMD_CONSOLE=n
67 CONFIG_CMD_BOOTD=n 67 CONFIG_CMD_BOOTD=n
68 CONFIG_CMD_BOOTEFI=n 68 CONFIG_CMD_BOOTEFI=n
69 CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n 69 CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n
70 CONFIG_CMD_ELF=n 70 CONFIG_CMD_ELF=n
71 CONFIG_CMD_GO=n 71 CONFIG_CMD_GO=n
72 CONFIG_CMD_RUN=n 72 CONFIG_CMD_RUN=n
73 CONFIG_CMD_IMI=n 73 CONFIG_CMD_IMI=n
74 CONFIG_CMD_IMLS=n 74 CONFIG_CMD_IMLS=n
75 CONFIG_CMD_XIMG=n 75 CONFIG_CMD_XIMG=n
76 CONFIG_CMD_EXPORTENV=n 76 CONFIG_CMD_EXPORTENV=n
77 CONFIG_CMD_IMPORTENV=n 77 CONFIG_CMD_IMPORTENV=n
78 CONFIG_CMD_EDITENV=n 78 CONFIG_CMD_EDITENV=n
79 CONFIG_CMD_ENV_EXISTS=n 79 CONFIG_CMD_ENV_EXISTS=n
80 CONFIG_CMD_CRC32=n 80 CONFIG_CMD_CRC32=n
81 CONFIG_CMD_DM=n 81 CONFIG_CMD_DM=n
82 CONFIG_CMD_LOADB=n 82 CONFIG_CMD_LOADB=n
83 CONFIG_CMD_LOADS=n 83 CONFIG_CMD_LOADS=n
84 CONFIG_CMD_FLASH=n 84 CONFIG_CMD_FLASH=n
85 CONFIG_CMD_GPT=n 85 CONFIG_CMD_GPT=n
86 CONFIG_CMD_FPGA=n 86 CONFIG_CMD_FPGA=n
87 CONFIG_CMD_ECHO=n 87 CONFIG_CMD_ECHO=n
88 CONFIG_CMD_ITEST=n 88 CONFIG_CMD_ITEST=n
89 CONFIG_CMD_SOURCE=n 89 CONFIG_CMD_SOURCE=n
90 CONFIG_CMD_SETEXPR=n 90 CONFIG_CMD_SETEXPR=n
91 CONFIG_CMD_MISC=n 91 CONFIG_CMD_MISC=n
92 CONFIG_CMD_UNZIP=n 92 CONFIG_CMD_UNZIP=n
93 CONFIG_CMD_LZMADEC=n 93 CONFIG_CMD_LZMADEC=n
94 CONFIG_CMD_SAVEENV=n 94 CONFIG_CMD_SAVEENV=n
95 95
96 CONFIG_DISPLAY_CPUINFO=n 96 CONFIG_DISPLAY_CPUINFO=n
97 CONFIG_DISPLAY_BOARDINFO=n 97 CONFIG_DISPLAY_BOARDINFO=n
98 CONFIG_EFI_LOADER=n 98 CONFIG_EFI_LOADER=n
99 99
100 CONFIG_POWER_DOMAIN=y 100 CONFIG_POWER_DOMAIN=y
101 CONFIG_IMX8_POWER_DOMAIN=y 101 CONFIG_IMX8_POWER_DOMAIN=y
102 102
103 CONFIG_DM_THERMAL=y 103 CONFIG_DM_THERMAL=y
104 CONFIG_IMX_SC_THERMAL=y 104 CONFIG_IMX_SC_THERMAL=y
105 105
106 CONFIG_ENV_IS_IN_MMC=y 106 CONFIG_ENV_IS_IN_MMC=y
107 CONFIG_LZ4=y 107 CONFIG_LZ4=y
108 108
109 CONFIG_SMC_FUSE=y 109 CONFIG_SMC_FUSE=y
110 CONFIG_CMD_MEMTEST=y 110 CONFIG_CMD_MEMTEST=y
111 111
112 CONFIG_SPL=y 112 CONFIG_SPL=y
113 CONFIG_SPL_MMC_SUPPORT=y 113 CONFIG_SPL_MMC_SUPPORT=y
114 CONFIG_SPL_GPIO_SUPPORT=y 114 CONFIG_SPL_GPIO_SUPPORT=y
115
116 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
117 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
115 118
configs/imx8qxp_mek_androidauto_trusty_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek-auto" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek-auto"
4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT" 4 CONFIG_SYS_EXTRA_OPTIONS="ANDROID_AUTO_SUPPORT"
5 CONFIG_TARGET_IMX8QXP_MEK=y 5 CONFIG_TARGET_IMX8QXP_MEK=y
6 CONFIG_SYS_TEXT_BASE=0x80020000 6 CONFIG_SYS_TEXT_BASE=0x80020000
7 CONFIG_EFI_PARTITION=y 7 CONFIG_EFI_PARTITION=y
8 CONFIG_SYS_MALLOC_F_LEN=0x2000 8 CONFIG_SYS_MALLOC_F_LEN=0x2000
9 CONFIG_DM=y 9 CONFIG_DM=y
10 CONFIG_DM_WARN=n 10 CONFIG_DM_WARN=n
11 CONFIG_DM_DEVICE_REMOVE=n 11 CONFIG_DM_DEVICE_REMOVE=n
12 CONFIG_IMX_TRUSTY_OS=y 12 CONFIG_IMX_TRUSTY_OS=y
13 13
14 CONFIG_DM_SERIAL=y 14 CONFIG_DM_SERIAL=y
15 CONFIG_FSL_LPUART=y 15 CONFIG_FSL_LPUART=y
16 CONFIG_OF_CONTROL=y 16 CONFIG_OF_CONTROL=y
17 CONFIG_DM_I2C=y 17 CONFIG_DM_I2C=y
18 # CONFIG_DM_I2C_COMPAT is not set 18 # CONFIG_DM_I2C_COMPAT is not set
19 CONFIG_SYS_I2C_IMX_LPI2C=y 19 CONFIG_SYS_I2C_IMX_LPI2C=y
20 CONFIG_CMD_I2C=n 20 CONFIG_CMD_I2C=n
21 CONFIG_I2C_MUX=y 21 CONFIG_I2C_MUX=y
22 CONFIG_I2C_MUX_PCA954x=y 22 CONFIG_I2C_MUX_PCA954x=y
23 23
24 CONFIG_USB_XHCI_HCD=y 24 CONFIG_USB_XHCI_HCD=y
25 CONFIG_USB_XHCI_IMX8=y 25 CONFIG_USB_XHCI_IMX8=y
26 26
27 CONFIG_DM_USB=y 27 CONFIG_DM_USB=y
28 28
29 CONFIG_USB=y 29 CONFIG_USB=y
30 30
31 CONFIG_USB_GADGET=y 31 CONFIG_USB_GADGET=y
32 #CONFIG_CI_UDC=y 32 #CONFIG_CI_UDC=y
33 CONFIG_USB_GADGET_DOWNLOAD=y 33 CONFIG_USB_GADGET_DOWNLOAD=y
34 CONFIG_USB_GADGET_MANUFACTURER="FSL" 34 CONFIG_USB_GADGET_MANUFACTURER="FSL"
35 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 35 CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
36 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02 36 CONFIG_USB_GADGET_PRODUCT_NUM=0x0d02
37 37
38 CONFIG_USB_CDNS3=y 38 CONFIG_USB_CDNS3=y
39 CONFIG_USB_CDNS3_GADGET=y 39 CONFIG_USB_CDNS3_GADGET=y
40 CONFIG_USB_GADGET_DUALSPEED=y 40 CONFIG_USB_GADGET_DUALSPEED=y
41 41
42 CONFIG_DM_GPIO=y 42 CONFIG_DM_GPIO=y
43 CONFIG_DM_PCA953X=y 43 CONFIG_DM_PCA953X=y
44 CONFIG_BOOTDELAY=1 44 CONFIG_BOOTDELAY=1
45 CONFIG_CMD_MMC=y 45 CONFIG_CMD_MMC=y
46 CONFIG_DM_MMC=y 46 CONFIG_DM_MMC=y
47 CONFIG_MMC_IO_VOLTAGE=y 47 CONFIG_MMC_IO_VOLTAGE=y
48 CONFIG_MMC_UHS_SUPPORT=y 48 CONFIG_MMC_UHS_SUPPORT=y
49 CONFIG_MMC_HS400_SUPPORT=y 49 CONFIG_MMC_HS400_SUPPORT=y
50 CONFIG_FSL_FSPI=y 50 CONFIG_FSL_FSPI=y
51 CONFIG_DM_SPI=y 51 CONFIG_DM_SPI=y
52 CONFIG_DM_SPI_FLASH=y 52 CONFIG_DM_SPI_FLASH=y
53 CONFIG_SPI_FLASH=y 53 CONFIG_SPI_FLASH=y
54 CONFIG_SPI_FLASH_4BYTES_ADDR=y 54 CONFIG_SPI_FLASH_4BYTES_ADDR=y
55 CONFIG_SPI_FLASH_STMICRO=y 55 CONFIG_SPI_FLASH_STMICRO=y
56 56
57 CONFIG_DM_REGULATOR=y 57 CONFIG_DM_REGULATOR=y
58 CONFIG_DM_REGULATOR_FIXED=y 58 CONFIG_DM_REGULATOR_FIXED=y
59 CONFIG_DM_REGULATOR_GPIO=y 59 CONFIG_DM_REGULATOR_GPIO=y
60 60
61 CONFIG_PINCTRL=y 61 CONFIG_PINCTRL=y
62 CONFIG_PINCTRL_IMX8=y 62 CONFIG_PINCTRL_IMX8=y
63 63
64 CONFIG_CMD_NET=n 64 CONFIG_CMD_NET=n
65 CONFIG_CMD_NFS=n 65 CONFIG_CMD_NFS=n
66 CONFIG_CMD_BDI=n 66 CONFIG_CMD_BDI=n
67 CONFIG_CMD_CONSOLE=n 67 CONFIG_CMD_CONSOLE=n
68 CONFIG_CMD_BOOTD=n 68 CONFIG_CMD_BOOTD=n
69 CONFIG_CMD_BOOTEFI=n 69 CONFIG_CMD_BOOTEFI=n
70 CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n 70 CONFIG_CMD_BOOTEFI_HELLO_COMPILE=n
71 CONFIG_CMD_ELF=n 71 CONFIG_CMD_ELF=n
72 CONFIG_CMD_GO=n 72 CONFIG_CMD_GO=n
73 CONFIG_CMD_RUN=n 73 CONFIG_CMD_RUN=n
74 CONFIG_CMD_IMI=n 74 CONFIG_CMD_IMI=n
75 CONFIG_CMD_IMLS=n 75 CONFIG_CMD_IMLS=n
76 CONFIG_CMD_XIMG=n 76 CONFIG_CMD_XIMG=n
77 CONFIG_CMD_EXPORTENV=n 77 CONFIG_CMD_EXPORTENV=n
78 CONFIG_CMD_IMPORTENV=n 78 CONFIG_CMD_IMPORTENV=n
79 CONFIG_CMD_EDITENV=n 79 CONFIG_CMD_EDITENV=n
80 CONFIG_CMD_ENV_EXISTS=n 80 CONFIG_CMD_ENV_EXISTS=n
81 CONFIG_CMD_CRC32=n 81 CONFIG_CMD_CRC32=n
82 CONFIG_CMD_DM=n 82 CONFIG_CMD_DM=n
83 CONFIG_CMD_LOADB=n 83 CONFIG_CMD_LOADB=n
84 CONFIG_CMD_LOADS=n 84 CONFIG_CMD_LOADS=n
85 CONFIG_CMD_FLASH=n 85 CONFIG_CMD_FLASH=n
86 CONFIG_CMD_GPT=n 86 CONFIG_CMD_GPT=n
87 CONFIG_CMD_FPGA=n 87 CONFIG_CMD_FPGA=n
88 CONFIG_CMD_ECHO=n 88 CONFIG_CMD_ECHO=n
89 CONFIG_CMD_ITEST=n 89 CONFIG_CMD_ITEST=n
90 CONFIG_CMD_SOURCE=n 90 CONFIG_CMD_SOURCE=n
91 CONFIG_CMD_SETEXPR=n 91 CONFIG_CMD_SETEXPR=n
92 CONFIG_CMD_MISC=n 92 CONFIG_CMD_MISC=n
93 CONFIG_CMD_UNZIP=n 93 CONFIG_CMD_UNZIP=n
94 CONFIG_CMD_LZMADEC=n 94 CONFIG_CMD_LZMADEC=n
95 CONFIG_CMD_SAVEENV=n 95 CONFIG_CMD_SAVEENV=n
96 96
97 CONFIG_DISPLAY_CPUINFO=n 97 CONFIG_DISPLAY_CPUINFO=n
98 CONFIG_DISPLAY_BOARDINFO=n 98 CONFIG_DISPLAY_BOARDINFO=n
99 CONFIG_EFI_LOADER=n 99 CONFIG_EFI_LOADER=n
100 100
101 CONFIG_POWER_DOMAIN=y 101 CONFIG_POWER_DOMAIN=y
102 CONFIG_IMX8_POWER_DOMAIN=y 102 CONFIG_IMX8_POWER_DOMAIN=y
103 103
104 CONFIG_DM_THERMAL=y 104 CONFIG_DM_THERMAL=y
105 CONFIG_IMX_SC_THERMAL=y 105 CONFIG_IMX_SC_THERMAL=y
106 106
107 CONFIG_ENV_IS_IN_MMC=y 107 CONFIG_ENV_IS_IN_MMC=y
108 CONFIG_LZ4=y 108 CONFIG_LZ4=y
109 109
110 CONFIG_SMC_FUSE=y 110 CONFIG_SMC_FUSE=y
111 CONFIG_CMD_MEMTEST=y 111 CONFIG_CMD_MEMTEST=y
112 112
113 CONFIG_SPL=y 113 CONFIG_SPL=y
114 CONFIG_SPL_MMC_SUPPORT=y 114 CONFIG_SPL_MMC_SUPPORT=y
115 CONFIG_SPL_GPIO_SUPPORT=y 115 CONFIG_SPL_GPIO_SUPPORT=y
116 116
117 CONFIG_SPL_ENV_SUPPORT=y 117 CONFIG_SPL_ENV_SUPPORT=y
118 CONFIG_SPL_LIBDISK_SUPPORT=y 118 CONFIG_SPL_LIBDISK_SUPPORT=y
119 119
120 CONFIG_NOT_UUU_BUILD=y 120 CONFIG_NOT_UUU_BUILD=y
121 CONFIG_SHA256=y 121 CONFIG_SHA256=y
122 CONFIG_SPL_MMC_WRITE=y 122 CONFIG_SPL_MMC_WRITE=y
123 CONFIG_DUAL_BOOTLOADER=y 123 CONFIG_DUAL_BOOTLOADER=y
124 CONFIG_APPEND_BOOTARGS=y 124 CONFIG_APPEND_BOOTARGS=y
125
126 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
127 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x02000000
125 128
configs/imx8qxp_mek_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
4 CONFIG_TARGET_IMX8QXP_MEK=y 4 CONFIG_TARGET_IMX8QXP_MEK=y
5 CONFIG_SYS_TEXT_BASE=0x80020000 5 CONFIG_SYS_TEXT_BASE=0x80020000
6 CONFIG_CMD_IMPORTENV=n 6 CONFIG_CMD_IMPORTENV=n
7 CONFIG_SYS_MALLOC_F_LEN=0x2000 7 CONFIG_SYS_MALLOC_F_LEN=0x2000
8 CONFIG_DM=y 8 CONFIG_DM=y
9 CONFIG_CMD_CACHE=y 9 CONFIG_CMD_CACHE=y
10 10
11 CONFIG_DM_SERIAL=y 11 CONFIG_DM_SERIAL=y
12 CONFIG_FSL_LPUART=y 12 CONFIG_FSL_LPUART=y
13 CONFIG_OF_CONTROL=y 13 CONFIG_OF_CONTROL=y
14 CONFIG_DM_I2C=y 14 CONFIG_DM_I2C=y
15 # CONFIG_DM_I2C_COMPAT is not set 15 # CONFIG_DM_I2C_COMPAT is not set
16 CONFIG_SYS_I2C_IMX_LPI2C=y 16 CONFIG_SYS_I2C_IMX_LPI2C=y
17 CONFIG_CMD_I2C=y 17 CONFIG_CMD_I2C=y
18 CONFIG_I2C_MUX=y 18 CONFIG_I2C_MUX=y
19 CONFIG_I2C_MUX_PCA954x=y 19 CONFIG_I2C_MUX_PCA954x=y
20 20
21 CONFIG_FASTBOOT=y 21 CONFIG_FASTBOOT=y
22 CONFIG_USB_FUNCTION_FASTBOOT=y 22 CONFIG_USB_FUNCTION_FASTBOOT=y
23 CONFIG_CMD_FASTBOOT=y 23 CONFIG_CMD_FASTBOOT=y
24 CONFIG_ANDROID_BOOT_IMAGE=y 24 CONFIG_ANDROID_BOOT_IMAGE=y
25 CONFIG_FSL_FASTBOOT=y 25 CONFIG_FSL_FASTBOOT=y
26 CONFIG_FASTBOOT_BUF_ADDR=0x82800000 26 CONFIG_FASTBOOT_BUF_ADDR=0x82800000
27 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 27 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
28 CONFIG_FASTBOOT_FLASH=y 28 CONFIG_FASTBOOT_FLASH=y
29 CONFIG_FASTBOOT_FLASH_MMC_DEV=0 29 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
30 CONFIG_FASTBOOT_USB_DEV=1 30 CONFIG_FASTBOOT_USB_DEV=1
31 31
32 CONFIG_USB_XHCI_HCD=y 32 CONFIG_USB_XHCI_HCD=y
33 CONFIG_USB_XHCI_IMX8=y 33 CONFIG_USB_XHCI_IMX8=y
34 34
35 CONFIG_DM_USB=y 35 CONFIG_DM_USB=y
36 36
37 CONFIG_USB=y 37 CONFIG_USB=y
38 CONFIG_USB_TCPC=y 38 CONFIG_USB_TCPC=y
39 39
40 CONFIG_USB_GADGET=y 40 CONFIG_USB_GADGET=y
41 # CONFIG_CI_UDC=y 41 # CONFIG_CI_UDC=y
42 CONFIG_USB_GADGET_DOWNLOAD=y 42 CONFIG_USB_GADGET_DOWNLOAD=y
43 CONFIG_USB_GADGET_MANUFACTURER="FSL" 43 CONFIG_USB_GADGET_MANUFACTURER="FSL"
44 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 44 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
45 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 45 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
46 46
47 CONFIG_USB_CDNS3=y 47 CONFIG_USB_CDNS3=y
48 CONFIG_USB_CDNS3_GADGET=y 48 CONFIG_USB_CDNS3_GADGET=y
49 CONFIG_USB_GADGET_DUALSPEED=y 49 CONFIG_USB_GADGET_DUALSPEED=y
50 50
51 CONFIG_CMD_GPIO=y 51 CONFIG_CMD_GPIO=y
52 CONFIG_DM_GPIO=y 52 CONFIG_DM_GPIO=y
53 CONFIG_DM_PCA953X=y 53 CONFIG_DM_PCA953X=y
54 CONFIG_BOOTDELAY=3 54 CONFIG_BOOTDELAY=3
55 CONFIG_IMX_BOOTAUX=y 55 CONFIG_IMX_BOOTAUX=y
56 CONFIG_FS_FAT=y 56 CONFIG_FS_FAT=y
57 CONFIG_CMD_FAT=y 57 CONFIG_CMD_FAT=y
58 CONFIG_CMD_MMC=y 58 CONFIG_CMD_MMC=y
59 CONFIG_DM_MMC=y 59 CONFIG_DM_MMC=y
60 CONFIG_MMC_IO_VOLTAGE=y 60 CONFIG_MMC_IO_VOLTAGE=y
61 CONFIG_MMC_UHS_SUPPORT=y 61 CONFIG_MMC_UHS_SUPPORT=y
62 CONFIG_MMC_HS400_SUPPORT=y 62 CONFIG_MMC_HS400_SUPPORT=y
63 CONFIG_EFI_PARTITION=y 63 CONFIG_EFI_PARTITION=y
64 CONFIG_FSL_FSPI=y 64 CONFIG_FSL_FSPI=y
65 CONFIG_DM_SPI=y 65 CONFIG_DM_SPI=y
66 CONFIG_DM_SPI_FLASH=y 66 CONFIG_DM_SPI_FLASH=y
67 CONFIG_SPI_FLASH=y 67 CONFIG_SPI_FLASH=y
68 CONFIG_SPI_FLASH_4BYTES_ADDR=y 68 CONFIG_SPI_FLASH_4BYTES_ADDR=y
69 CONFIG_SPI_FLASH_STMICRO=y 69 CONFIG_SPI_FLASH_STMICRO=y
70 CONFIG_CMD_SF=y 70 CONFIG_CMD_SF=y
71 71
72 CONFIG_CMD_PING=y 72 CONFIG_CMD_PING=y
73 CONFIG_CMD_DHCP=y 73 CONFIG_CMD_DHCP=y
74 CONFIG_CMD_MII=y 74 CONFIG_CMD_MII=y
75 CONFIG_DM_ETH=y 75 CONFIG_DM_ETH=y
76 # CONFIG_EFI_LOADER is not set 76 # CONFIG_EFI_LOADER is not set
77 77
78 CONFIG_DM_REGULATOR=y 78 CONFIG_DM_REGULATOR=y
79 CONFIG_DM_REGULATOR_FIXED=y 79 CONFIG_DM_REGULATOR_FIXED=y
80 CONFIG_DM_REGULATOR_GPIO=y 80 CONFIG_DM_REGULATOR_GPIO=y
81 81
82 CONFIG_VIDEO=y 82 CONFIG_VIDEO=y
83 83
84 CONFIG_PINCTRL=y 84 CONFIG_PINCTRL=y
85 CONFIG_PINCTRL_IMX8=y 85 CONFIG_PINCTRL_IMX8=y
86 86
87 CONFIG_POWER_DOMAIN=y 87 CONFIG_POWER_DOMAIN=y
88 CONFIG_IMX8_POWER_DOMAIN=y 88 CONFIG_IMX8_POWER_DOMAIN=y
89 89
90 CONFIG_DM_THERMAL=y 90 CONFIG_DM_THERMAL=y
91 CONFIG_IMX_SC_THERMAL=y 91 CONFIG_IMX_SC_THERMAL=y
92 92
93 CONFIG_ENV_IS_IN_MMC=y 93 CONFIG_ENV_IS_IN_MMC=y
94 94
95 CONFIG_SMC_FUSE=y 95 CONFIG_SMC_FUSE=y
96 CONFIG_CMD_MEMTEST=y 96 CONFIG_CMD_MEMTEST=y
97 97
98 CONFIG_SYS_I2C_IMX_VIRT_I2C=y 98 CONFIG_SYS_I2C_IMX_VIRT_I2C=y
99 CONFIG_I2C_MUX_IMX_VIRT=y 99 CONFIG_I2C_MUX_IMX_VIRT=y
100 CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000 100 CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000
101
102 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
103 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
101 104
configs/imx8qxp_mek_fspi_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
4 CONFIG_TARGET_IMX8QXP_MEK=y 4 CONFIG_TARGET_IMX8QXP_MEK=y
5 CONFIG_SYS_TEXT_BASE=0x80020000 5 CONFIG_SYS_TEXT_BASE=0x80020000
6 CONFIG_CMD_IMPORTENV=n 6 CONFIG_CMD_IMPORTENV=n
7 CONFIG_SYS_MALLOC_F_LEN=0x2000 7 CONFIG_SYS_MALLOC_F_LEN=0x2000
8 CONFIG_DM=y 8 CONFIG_DM=y
9 CONFIG_CMD_CACHE=y 9 CONFIG_CMD_CACHE=y
10 10
11 CONFIG_DM_SERIAL=y 11 CONFIG_DM_SERIAL=y
12 CONFIG_FSL_LPUART=y 12 CONFIG_FSL_LPUART=y
13 CONFIG_OF_CONTROL=y 13 CONFIG_OF_CONTROL=y
14 CONFIG_DM_I2C=y 14 CONFIG_DM_I2C=y
15 # CONFIG_DM_I2C_COMPAT is not set 15 # CONFIG_DM_I2C_COMPAT is not set
16 CONFIG_SYS_I2C_IMX_LPI2C=y 16 CONFIG_SYS_I2C_IMX_LPI2C=y
17 CONFIG_CMD_I2C=y 17 CONFIG_CMD_I2C=y
18 CONFIG_I2C_MUX=y 18 CONFIG_I2C_MUX=y
19 CONFIG_I2C_MUX_PCA954x=y 19 CONFIG_I2C_MUX_PCA954x=y
20 20
21 CONFIG_FASTBOOT=y 21 CONFIG_FASTBOOT=y
22 CONFIG_USB_FUNCTION_FASTBOOT=y 22 CONFIG_USB_FUNCTION_FASTBOOT=y
23 CONFIG_CMD_FASTBOOT=y 23 CONFIG_CMD_FASTBOOT=y
24 CONFIG_ANDROID_BOOT_IMAGE=y 24 CONFIG_ANDROID_BOOT_IMAGE=y
25 CONFIG_FSL_FASTBOOT=y 25 CONFIG_FSL_FASTBOOT=y
26 CONFIG_FASTBOOT_BUF_ADDR=0x82800000 26 CONFIG_FASTBOOT_BUF_ADDR=0x82800000
27 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 27 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
28 CONFIG_FASTBOOT_FLASH=y 28 CONFIG_FASTBOOT_FLASH=y
29 CONFIG_FASTBOOT_FLASH_MMC_DEV=0 29 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
30 CONFIG_FASTBOOT_USB_DEV=1 30 CONFIG_FASTBOOT_USB_DEV=1
31 31
32 CONFIG_USB_XHCI_HCD=y 32 CONFIG_USB_XHCI_HCD=y
33 CONFIG_USB_XHCI_IMX8=y 33 CONFIG_USB_XHCI_IMX8=y
34 34
35 CONFIG_DM_USB=y 35 CONFIG_DM_USB=y
36 36
37 CONFIG_USB=y 37 CONFIG_USB=y
38 CONFIG_USB_TCPC=y 38 CONFIG_USB_TCPC=y
39 39
40 CONFIG_USB_GADGET=y 40 CONFIG_USB_GADGET=y
41 # CONFIG_CI_UDC=y 41 # CONFIG_CI_UDC=y
42 CONFIG_USB_GADGET_DOWNLOAD=y 42 CONFIG_USB_GADGET_DOWNLOAD=y
43 CONFIG_USB_GADGET_MANUFACTURER="FSL" 43 CONFIG_USB_GADGET_MANUFACTURER="FSL"
44 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 44 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
45 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 45 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
46 46
47 CONFIG_USB_CDNS3=y 47 CONFIG_USB_CDNS3=y
48 CONFIG_USB_CDNS3_GADGET=y 48 CONFIG_USB_CDNS3_GADGET=y
49 CONFIG_USB_GADGET_DUALSPEED=y 49 CONFIG_USB_GADGET_DUALSPEED=y
50 50
51 CONFIG_CMD_GPIO=y 51 CONFIG_CMD_GPIO=y
52 CONFIG_DM_GPIO=y 52 CONFIG_DM_GPIO=y
53 CONFIG_DM_PCA953X=y 53 CONFIG_DM_PCA953X=y
54 CONFIG_BOOTDELAY=3 54 CONFIG_BOOTDELAY=3
55 CONFIG_IMX_BOOTAUX=y 55 CONFIG_IMX_BOOTAUX=y
56 CONFIG_FS_FAT=y 56 CONFIG_FS_FAT=y
57 CONFIG_CMD_FAT=y 57 CONFIG_CMD_FAT=y
58 CONFIG_CMD_MMC=y 58 CONFIG_CMD_MMC=y
59 CONFIG_DM_MMC=y 59 CONFIG_DM_MMC=y
60 CONFIG_MMC_IO_VOLTAGE=y 60 CONFIG_MMC_IO_VOLTAGE=y
61 CONFIG_MMC_UHS_SUPPORT=y 61 CONFIG_MMC_UHS_SUPPORT=y
62 CONFIG_MMC_HS400_SUPPORT=y 62 CONFIG_MMC_HS400_SUPPORT=y
63 CONFIG_EFI_PARTITION=y 63 CONFIG_EFI_PARTITION=y
64 CONFIG_QSPI_BOOT=y 64 CONFIG_QSPI_BOOT=y
65 CONFIG_FSL_FSPI=y 65 CONFIG_FSL_FSPI=y
66 CONFIG_DM_SPI=y 66 CONFIG_DM_SPI=y
67 CONFIG_DM_SPI_FLASH=y 67 CONFIG_DM_SPI_FLASH=y
68 CONFIG_SPI_FLASH=y 68 CONFIG_SPI_FLASH=y
69 CONFIG_SPI_FLASH_4BYTES_ADDR=y 69 CONFIG_SPI_FLASH_4BYTES_ADDR=y
70 CONFIG_SPI_FLASH_STMICRO=y 70 CONFIG_SPI_FLASH_STMICRO=y
71 CONFIG_CMD_SF=y 71 CONFIG_CMD_SF=y
72 72
73 CONFIG_CMD_PING=y 73 CONFIG_CMD_PING=y
74 CONFIG_CMD_DHCP=y 74 CONFIG_CMD_DHCP=y
75 CONFIG_CMD_MII=y 75 CONFIG_CMD_MII=y
76 CONFIG_DM_ETH=y 76 CONFIG_DM_ETH=y
77 # CONFIG_EFI_LOADER is not set 77 # CONFIG_EFI_LOADER is not set
78 78
79 CONFIG_DM_REGULATOR=y 79 CONFIG_DM_REGULATOR=y
80 CONFIG_DM_REGULATOR_FIXED=y 80 CONFIG_DM_REGULATOR_FIXED=y
81 CONFIG_DM_REGULATOR_GPIO=y 81 CONFIG_DM_REGULATOR_GPIO=y
82 82
83 CONFIG_VIDEO=y 83 CONFIG_VIDEO=y
84 84
85 CONFIG_PINCTRL=y 85 CONFIG_PINCTRL=y
86 CONFIG_PINCTRL_IMX8=y 86 CONFIG_PINCTRL_IMX8=y
87 87
88 CONFIG_POWER_DOMAIN=y 88 CONFIG_POWER_DOMAIN=y
89 CONFIG_IMX8_POWER_DOMAIN=y 89 CONFIG_IMX8_POWER_DOMAIN=y
90 90
91 CONFIG_DM_THERMAL=y 91 CONFIG_DM_THERMAL=y
92 CONFIG_IMX_SC_THERMAL=y 92 CONFIG_IMX_SC_THERMAL=y
93 93
94 CONFIG_ENV_IS_IN_SPI_FLASH=y 94 CONFIG_ENV_IS_IN_SPI_FLASH=y
95 95
96 CONFIG_SMC_FUSE=y 96 CONFIG_SMC_FUSE=y
97 CONFIG_CMD_MEMTEST=y 97 CONFIG_CMD_MEMTEST=y
98 98
99 CONFIG_SYS_I2C_IMX_VIRT_I2C=y 99 CONFIG_SYS_I2C_IMX_VIRT_I2C=y
100 CONFIG_I2C_MUX_IMX_VIRT=y 100 CONFIG_I2C_MUX_IMX_VIRT=y
101 CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000 101 CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000
102
103 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
104 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
102 105
configs/imx8qxp_mek_spl_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
4 CONFIG_TARGET_IMX8QXP_MEK=y 4 CONFIG_TARGET_IMX8QXP_MEK=y
5 CONFIG_SYS_TEXT_BASE=0x80020000 5 CONFIG_SYS_TEXT_BASE=0x80020000
6 CONFIG_CMD_IMPORTENV=n 6 CONFIG_CMD_IMPORTENV=n
7 CONFIG_SYS_MALLOC_F_LEN=0x2000 7 CONFIG_SYS_MALLOC_F_LEN=0x2000
8 CONFIG_DM=y 8 CONFIG_DM=y
9 CONFIG_CMD_CACHE=y 9 CONFIG_CMD_CACHE=y
10 10
11 CONFIG_DM_SERIAL=y 11 CONFIG_DM_SERIAL=y
12 CONFIG_FSL_LPUART=y 12 CONFIG_FSL_LPUART=y
13 CONFIG_OF_CONTROL=y 13 CONFIG_OF_CONTROL=y
14 CONFIG_DM_I2C=y 14 CONFIG_DM_I2C=y
15 # CONFIG_DM_I2C_COMPAT is not set 15 # CONFIG_DM_I2C_COMPAT is not set
16 CONFIG_SYS_I2C_IMX_LPI2C=y 16 CONFIG_SYS_I2C_IMX_LPI2C=y
17 CONFIG_CMD_I2C=y 17 CONFIG_CMD_I2C=y
18 CONFIG_I2C_MUX=y 18 CONFIG_I2C_MUX=y
19 CONFIG_I2C_MUX_PCA954x=y 19 CONFIG_I2C_MUX_PCA954x=y
20 20
21 CONFIG_SPL=y 21 CONFIG_SPL=y
22 CONFIG_SPL_GPIO_SUPPORT=y 22 CONFIG_SPL_GPIO_SUPPORT=y
23 CONFIG_SPL_MMC_SUPPORT=y 23 CONFIG_SPL_MMC_SUPPORT=y
24 CONFIG_FIT=y 24 CONFIG_FIT=y
25 CONFIG_SPL_LOAD_FIT=y 25 CONFIG_SPL_LOAD_FIT=y
26 CONFIG_SPL_BOARD_INIT=y 26 CONFIG_SPL_BOARD_INIT=y
27 CONFIG_SPL_TINY_MEMSET=y 27 CONFIG_SPL_TINY_MEMSET=y
28 CONFIG_SPL_OF_CONTROL=y 28 CONFIG_SPL_OF_CONTROL=y
29 29
30 CONFIG_FASTBOOT=y 30 CONFIG_FASTBOOT=y
31 CONFIG_USB_FUNCTION_FASTBOOT=y 31 CONFIG_USB_FUNCTION_FASTBOOT=y
32 CONFIG_CMD_FASTBOOT=y 32 CONFIG_CMD_FASTBOOT=y
33 CONFIG_ANDROID_BOOT_IMAGE=y 33 CONFIG_ANDROID_BOOT_IMAGE=y
34 CONFIG_FSL_FASTBOOT=y 34 CONFIG_FSL_FASTBOOT=y
35 CONFIG_FASTBOOT_BUF_ADDR=0x82800000 35 CONFIG_FASTBOOT_BUF_ADDR=0x82800000
36 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 36 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
37 CONFIG_FASTBOOT_FLASH=y 37 CONFIG_FASTBOOT_FLASH=y
38 CONFIG_FASTBOOT_FLASH_MMC_DEV=0 38 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
39 CONFIG_FASTBOOT_USB_DEV=1 39 CONFIG_FASTBOOT_USB_DEV=1
40 40
41 CONFIG_USB_XHCI_HCD=y 41 CONFIG_USB_XHCI_HCD=y
42 CONFIG_USB_XHCI_IMX8=y 42 CONFIG_USB_XHCI_IMX8=y
43 43
44 CONFIG_DM_USB=y 44 CONFIG_DM_USB=y
45 45
46 CONFIG_USB=y 46 CONFIG_USB=y
47 CONFIG_USB_TCPC=y 47 CONFIG_USB_TCPC=y
48 48
49 CONFIG_USB_GADGET=y 49 CONFIG_USB_GADGET=y
50 # CONFIG_CI_UDC=y 50 # CONFIG_CI_UDC=y
51 CONFIG_USB_GADGET_DOWNLOAD=y 51 CONFIG_USB_GADGET_DOWNLOAD=y
52 CONFIG_USB_GADGET_MANUFACTURER="FSL" 52 CONFIG_USB_GADGET_MANUFACTURER="FSL"
53 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 53 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
54 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 54 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
55 55
56 CONFIG_USB_CDNS3=y 56 CONFIG_USB_CDNS3=y
57 CONFIG_USB_CDNS3_GADGET=y 57 CONFIG_USB_CDNS3_GADGET=y
58 CONFIG_USB_GADGET_DUALSPEED=y 58 CONFIG_USB_GADGET_DUALSPEED=y
59 59
60 CONFIG_CMD_GPIO=y 60 CONFIG_CMD_GPIO=y
61 CONFIG_DM_GPIO=y 61 CONFIG_DM_GPIO=y
62 CONFIG_DM_PCA953X=y 62 CONFIG_DM_PCA953X=y
63 CONFIG_BOOTDELAY=3 63 CONFIG_BOOTDELAY=3
64 CONFIG_IMX_BOOTAUX=y 64 CONFIG_IMX_BOOTAUX=y
65 CONFIG_FS_FAT=y 65 CONFIG_FS_FAT=y
66 CONFIG_CMD_FAT=y 66 CONFIG_CMD_FAT=y
67 CONFIG_CMD_MMC=y 67 CONFIG_CMD_MMC=y
68 CONFIG_DM_MMC=y 68 CONFIG_DM_MMC=y
69 CONFIG_MMC_IO_VOLTAGE=y 69 CONFIG_MMC_IO_VOLTAGE=y
70 CONFIG_MMC_UHS_SUPPORT=y 70 CONFIG_MMC_UHS_SUPPORT=y
71 CONFIG_MMC_HS400_SUPPORT=y 71 CONFIG_MMC_HS400_SUPPORT=y
72 CONFIG_EFI_PARTITION=y 72 CONFIG_EFI_PARTITION=y
73 CONFIG_FSL_FSPI=y 73 CONFIG_FSL_FSPI=y
74 CONFIG_DM_SPI=y 74 CONFIG_DM_SPI=y
75 CONFIG_DM_SPI_FLASH=y 75 CONFIG_DM_SPI_FLASH=y
76 CONFIG_SPI_FLASH=y 76 CONFIG_SPI_FLASH=y
77 CONFIG_SPI_FLASH_4BYTES_ADDR=y 77 CONFIG_SPI_FLASH_4BYTES_ADDR=y
78 CONFIG_SPI_FLASH_STMICRO=y 78 CONFIG_SPI_FLASH_STMICRO=y
79 CONFIG_CMD_SF=y 79 CONFIG_CMD_SF=y
80 80
81 CONFIG_CMD_PING=y 81 CONFIG_CMD_PING=y
82 CONFIG_CMD_DHCP=y 82 CONFIG_CMD_DHCP=y
83 CONFIG_CMD_MII=y 83 CONFIG_CMD_MII=y
84 CONFIG_DM_ETH=y 84 CONFIG_DM_ETH=y
85 # CONFIG_EFI_LOADER is not set 85 # CONFIG_EFI_LOADER is not set
86 86
87 CONFIG_DM_REGULATOR=y 87 CONFIG_DM_REGULATOR=y
88 CONFIG_DM_REGULATOR_FIXED=y 88 CONFIG_DM_REGULATOR_FIXED=y
89 CONFIG_DM_REGULATOR_GPIO=y 89 CONFIG_DM_REGULATOR_GPIO=y
90 90
91 CONFIG_VIDEO=y 91 CONFIG_VIDEO=y
92 92
93 CONFIG_PINCTRL=y 93 CONFIG_PINCTRL=y
94 CONFIG_PINCTRL_IMX8=y 94 CONFIG_PINCTRL_IMX8=y
95 95
96 CONFIG_POWER_DOMAIN=y 96 CONFIG_POWER_DOMAIN=y
97 CONFIG_IMX8_POWER_DOMAIN=y 97 CONFIG_IMX8_POWER_DOMAIN=y
98 98
99 CONFIG_DM_THERMAL=y 99 CONFIG_DM_THERMAL=y
100 CONFIG_IMX_SC_THERMAL=y 100 CONFIG_IMX_SC_THERMAL=y
101 101
102 CONFIG_ENV_IS_IN_MMC=y 102 CONFIG_ENV_IS_IN_MMC=y
103 103
104 CONFIG_SMC_FUSE=y 104 CONFIG_SMC_FUSE=y
105 CONFIG_CMD_MEMTEST=y 105 CONFIG_CMD_MEMTEST=y
106 106
107 CONFIG_SPL_USB_HOST_SUPPORT=y 107 CONFIG_SPL_USB_HOST_SUPPORT=y
108 CONFIG_SPL_USB_GADGET_SUPPORT=y 108 CONFIG_SPL_USB_GADGET_SUPPORT=y
109 CONFIG_SPL_USB_SDP_SUPPORT=y 109 CONFIG_SPL_USB_SDP_SUPPORT=y
110 CONFIG_SPL_SDP_USB_DEV=1 110 CONFIG_SPL_SDP_USB_DEV=1
111 CONFIG_SDP_LOADADDR=0x80400000 111 CONFIG_SDP_LOADADDR=0x80400000
112 112
113 CONFIG_SYS_I2C_IMX_VIRT_I2C=y 113 CONFIG_SYS_I2C_IMX_VIRT_I2C=y
114 CONFIG_I2C_MUX_IMX_VIRT=y 114 CONFIG_I2C_MUX_IMX_VIRT=y
115 CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000 115 CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000
116
117 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
118 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
116 119
configs/imx8qxp_mek_spl_fspi_defconfig
Diff comments   View file @ 57fa56f
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8=y 2 CONFIG_ARCH_IMX8=y
3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" 3 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
4 CONFIG_TARGET_IMX8QXP_MEK=y 4 CONFIG_TARGET_IMX8QXP_MEK=y
5 CONFIG_SYS_TEXT_BASE=0x80020000 5 CONFIG_SYS_TEXT_BASE=0x80020000
6 CONFIG_CMD_IMPORTENV=n 6 CONFIG_CMD_IMPORTENV=n
7 CONFIG_SYS_MALLOC_F_LEN=0x2000 7 CONFIG_SYS_MALLOC_F_LEN=0x2000
8 CONFIG_DM=y 8 CONFIG_DM=y
9 CONFIG_CMD_CACHE=y 9 CONFIG_CMD_CACHE=y
10 10
11 CONFIG_DM_SERIAL=y 11 CONFIG_DM_SERIAL=y
12 CONFIG_FSL_LPUART=y 12 CONFIG_FSL_LPUART=y
13 CONFIG_OF_CONTROL=y 13 CONFIG_OF_CONTROL=y
14 CONFIG_DM_I2C=y 14 CONFIG_DM_I2C=y
15 # CONFIG_DM_I2C_COMPAT is not set 15 # CONFIG_DM_I2C_COMPAT is not set
16 CONFIG_SYS_I2C_IMX_LPI2C=y 16 CONFIG_SYS_I2C_IMX_LPI2C=y
17 CONFIG_CMD_I2C=y 17 CONFIG_CMD_I2C=y
18 CONFIG_I2C_MUX=y 18 CONFIG_I2C_MUX=y
19 CONFIG_I2C_MUX_PCA954x=y 19 CONFIG_I2C_MUX_PCA954x=y
20 20
21 CONFIG_SPL=y 21 CONFIG_SPL=y
22 CONFIG_SPL_GPIO_SUPPORT=y 22 CONFIG_SPL_GPIO_SUPPORT=y
23 CONFIG_SPL_MMC_SUPPORT=y 23 CONFIG_SPL_MMC_SUPPORT=y
24 CONFIG_FIT=y 24 CONFIG_FIT=y
25 CONFIG_SPL_LOAD_FIT=y 25 CONFIG_SPL_LOAD_FIT=y
26 CONFIG_SPL_BOARD_INIT=y 26 CONFIG_SPL_BOARD_INIT=y
27 CONFIG_SPL_TINY_MEMSET=y 27 CONFIG_SPL_TINY_MEMSET=y
28 CONFIG_SPL_MTD_SUPPORT=y 28 CONFIG_SPL_MTD_SUPPORT=y
29 CONFIG_SPL_OF_CONTROL=y 29 CONFIG_SPL_OF_CONTROL=y
30 CONFIG_SPL_SPI_FLASH_SUPPORT=y 30 CONFIG_SPL_SPI_FLASH_SUPPORT=y
31 CONFIG_SPL_SPI_SUPPORT=y 31 CONFIG_SPL_SPI_SUPPORT=y
32 CONFIG_SPL_NOR_SUPPORT=y 32 CONFIG_SPL_NOR_SUPPORT=y
33 CONFIG_PANIC_HANG=y 33 CONFIG_PANIC_HANG=y
34 CONFIG_FASTBOOT=y 34 CONFIG_FASTBOOT=y
35 CONFIG_USB_FUNCTION_FASTBOOT=y 35 CONFIG_USB_FUNCTION_FASTBOOT=y
36 CONFIG_CMD_FASTBOOT=y 36 CONFIG_CMD_FASTBOOT=y
37 CONFIG_ANDROID_BOOT_IMAGE=y 37 CONFIG_ANDROID_BOOT_IMAGE=y
38 CONFIG_FSL_FASTBOOT=y 38 CONFIG_FSL_FASTBOOT=y
39 CONFIG_FASTBOOT_BUF_ADDR=0x82800000 39 CONFIG_FASTBOOT_BUF_ADDR=0x82800000
40 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 40 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
41 CONFIG_FASTBOOT_FLASH=y 41 CONFIG_FASTBOOT_FLASH=y
42 CONFIG_FASTBOOT_FLASH_MMC_DEV=0 42 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
43 CONFIG_FASTBOOT_USB_DEV=1 43 CONFIG_FASTBOOT_USB_DEV=1
44 44
45 CONFIG_USB_XHCI_HCD=y 45 CONFIG_USB_XHCI_HCD=y
46 CONFIG_USB_XHCI_IMX8=y 46 CONFIG_USB_XHCI_IMX8=y
47 47
48 CONFIG_DM_USB=y 48 CONFIG_DM_USB=y
49 49
50 CONFIG_USB=y 50 CONFIG_USB=y
51 CONFIG_USB_TCPC=y 51 CONFIG_USB_TCPC=y
52 52
53 CONFIG_USB_GADGET=y 53 CONFIG_USB_GADGET=y
54 # CONFIG_CI_UDC=y 54 # CONFIG_CI_UDC=y
55 CONFIG_USB_GADGET_DOWNLOAD=y 55 CONFIG_USB_GADGET_DOWNLOAD=y
56 CONFIG_USB_GADGET_MANUFACTURER="FSL" 56 CONFIG_USB_GADGET_MANUFACTURER="FSL"
57 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 57 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
58 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 58 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
59 59
60 CONFIG_USB_CDNS3=y 60 CONFIG_USB_CDNS3=y
61 CONFIG_USB_CDNS3_GADGET=y 61 CONFIG_USB_CDNS3_GADGET=y
62 CONFIG_USB_GADGET_DUALSPEED=y 62 CONFIG_USB_GADGET_DUALSPEED=y
63 63
64 CONFIG_CMD_GPIO=y 64 CONFIG_CMD_GPIO=y
65 CONFIG_DM_GPIO=y 65 CONFIG_DM_GPIO=y
66 CONFIG_DM_PCA953X=y 66 CONFIG_DM_PCA953X=y
67 CONFIG_BOOTDELAY=3 67 CONFIG_BOOTDELAY=3
68 CONFIG_IMX_BOOTAUX=y 68 CONFIG_IMX_BOOTAUX=y
69 CONFIG_FS_FAT=y 69 CONFIG_FS_FAT=y
70 CONFIG_CMD_FAT=y 70 CONFIG_CMD_FAT=y
71 CONFIG_CMD_MMC=y 71 CONFIG_CMD_MMC=y
72 CONFIG_DM_MMC=y 72 CONFIG_DM_MMC=y
73 CONFIG_MMC_IO_VOLTAGE=y 73 CONFIG_MMC_IO_VOLTAGE=y
74 CONFIG_MMC_UHS_SUPPORT=y 74 CONFIG_MMC_UHS_SUPPORT=y
75 CONFIG_MMC_HS400_SUPPORT=y 75 CONFIG_MMC_HS400_SUPPORT=y
76 CONFIG_EFI_PARTITION=y 76 CONFIG_EFI_PARTITION=y
77 CONFIG_FSL_FSPI=y 77 CONFIG_FSL_FSPI=y
78 CONFIG_DM_SPI=y 78 CONFIG_DM_SPI=y
79 CONFIG_DM_SPI_FLASH=y 79 CONFIG_DM_SPI_FLASH=y
80 CONFIG_SPI_FLASH=y 80 CONFIG_SPI_FLASH=y
81 CONFIG_SPI_FLASH_4BYTES_ADDR=y 81 CONFIG_SPI_FLASH_4BYTES_ADDR=y
82 CONFIG_SPI_FLASH_STMICRO=y 82 CONFIG_SPI_FLASH_STMICRO=y
83 CONFIG_CMD_SF=y 83 CONFIG_CMD_SF=y
84 84
85 CONFIG_CMD_PING=y 85 CONFIG_CMD_PING=y
86 CONFIG_CMD_DHCP=y 86 CONFIG_CMD_DHCP=y
87 CONFIG_CMD_MII=y 87 CONFIG_CMD_MII=y
88 CONFIG_DM_ETH=y 88 CONFIG_DM_ETH=y
89 # CONFIG_EFI_LOADER is not set 89 # CONFIG_EFI_LOADER is not set
90 90
91 CONFIG_DM_REGULATOR=y 91 CONFIG_DM_REGULATOR=y
92 CONFIG_DM_REGULATOR_FIXED=y 92 CONFIG_DM_REGULATOR_FIXED=y
93 CONFIG_DM_REGULATOR_GPIO=y 93 CONFIG_DM_REGULATOR_GPIO=y
94 94
95 CONFIG_VIDEO=y 95 CONFIG_VIDEO=y
96 96
97 CONFIG_PINCTRL=y 97 CONFIG_PINCTRL=y
98 CONFIG_PINCTRL_IMX8=y 98 CONFIG_PINCTRL_IMX8=y
99 99
100 CONFIG_POWER_DOMAIN=y 100 CONFIG_POWER_DOMAIN=y
101 CONFIG_IMX8_POWER_DOMAIN=y 101 CONFIG_IMX8_POWER_DOMAIN=y
102 102
103 CONFIG_DM_THERMAL=y 103 CONFIG_DM_THERMAL=y
104 CONFIG_IMX_SC_THERMAL=y 104 CONFIG_IMX_SC_THERMAL=y
105 105
106 CONFIG_ENV_IS_IN_MMC=y 106 CONFIG_ENV_IS_IN_MMC=y
107 107
108 CONFIG_SMC_FUSE=y 108 CONFIG_SMC_FUSE=y
109 CONFIG_CMD_MEMTEST=y 109 CONFIG_CMD_MEMTEST=y
110 110
111 CONFIG_SPL_USB_HOST_SUPPORT=y 111 CONFIG_SPL_USB_HOST_SUPPORT=y
112 CONFIG_SPL_USB_GADGET_SUPPORT=y 112 CONFIG_SPL_USB_GADGET_SUPPORT=y
113 CONFIG_SPL_USB_SDP_SUPPORT=y 113 CONFIG_SPL_USB_SDP_SUPPORT=y
114 CONFIG_SPL_SDP_USB_DEV=1 114 CONFIG_SPL_SDP_USB_DEV=1
115 CONFIG_SDP_LOADADDR=0x80400000 115 CONFIG_SDP_LOADADDR=0x80400000
116 116
117 CONFIG_SYS_I2C_IMX_VIRT_I2C=y 117 CONFIG_SYS_I2C_IMX_VIRT_I2C=y
118 CONFIG_I2C_MUX_IMX_VIRT=y 118 CONFIG_I2C_MUX_IMX_VIRT=y
119 CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000 119 CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000
120
121 CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
122 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
120 123
include/configs/imx8qm_arm2.h
Diff comments   View file @ 57fa56f
1 /* 1 /*
2 * Copyright 2017-2018 NXP 2 * Copyright 2017-2018 NXP
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __IMX8QM_ARM2_H 7 #ifndef __IMX8QM_ARM2_H
8 #define __IMX8QM_ARM2_H 8 #define __IMX8QM_ARM2_H
9 9
10 #include <linux/sizes.h> 10 #include <linux/sizes.h>
11 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/imx-regs.h>
12 12
13 #ifdef CONFIG_SPL_BUILD 13 #ifdef CONFIG_SPL_BUILD
14 14
15 #define CONFIG_PARSE_CONTAINER 15 #define CONFIG_PARSE_CONTAINER
16 #define CONFIG_SPL_TEXT_BASE 0x0 16 #define CONFIG_SPL_TEXT_BASE 0x0
17 #define CONFIG_SPL_MAX_SIZE (124 * 1024) 17 #define CONFIG_SPL_MAX_SIZE (124 * 1024)
18 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) 18 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
19 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR 19 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
20 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (flash.bin_offset + 2Mb)/sector_size */ 20 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (flash.bin_offset + 2Mb)/sector_size */
21 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 21 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
22 #define CONFIG_SYS_UBOOT_BASE 0x08281000 22 #define CONFIG_SYS_UBOOT_BASE 0x08281000
23 23
24 #define CONFIG_SPL_WATCHDOG_SUPPORT 24 #define CONFIG_SPL_WATCHDOG_SUPPORT
25 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 25 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
26 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 26 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
27 #define CONFIG_SPL_STACK 0x013E000 27 #define CONFIG_SPL_STACK 0x013E000
28 #define CONFIG_SPL_LIBCOMMON_SUPPORT 28 #define CONFIG_SPL_LIBCOMMON_SUPPORT
29 #define CONFIG_SPL_LIBGENERIC_SUPPORT 29 #define CONFIG_SPL_LIBGENERIC_SUPPORT
30 #define CONFIG_SPL_SERIAL_SUPPORT 30 #define CONFIG_SPL_SERIAL_SUPPORT
31 #define CONFIG_SPL_BSS_START_ADDR 0x00128000 31 #define CONFIG_SPL_BSS_START_ADDR 0x00128000
32 #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ 32 #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
33 #define CONFIG_SYS_SPL_MALLOC_START 0x00120000 33 #define CONFIG_SYS_SPL_MALLOC_START 0x00120000
34 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x18000 /* 12 KB */ 34 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x18000 /* 12 KB */
35 #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 35 #define CONFIG_SERIAL_LPUART_BASE 0x5a060000
36 #define CONFIG_SYS_ICACHE_OFF 36 #define CONFIG_SYS_ICACHE_OFF
37 #define CONFIG_SYS_DCACHE_OFF 37 #define CONFIG_SYS_DCACHE_OFF
38 #define CONFIG_MALLOC_F_ADDR 0x00120000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ 38 #define CONFIG_MALLOC_F_ADDR 0x00120000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
39 39
40 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE 40 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
41 41
42 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ 42 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
43 43
44 #define CONFIG_OF_EMBED 44 #define CONFIG_OF_EMBED
45 #define CONFIG_ATF_TEXT_BASE 0x80000000 45 #define CONFIG_ATF_TEXT_BASE 0x80000000
46 #define CONFIG_SYS_ATF_START 0x80000000 46 #define CONFIG_SYS_ATF_START 0x80000000
47 /* #define CONFIG_FIT */ 47 /* #define CONFIG_FIT */
48 48
49 /* Since the SPL runs before ATF, MU1 will not be started yet, so use MU0 */ 49 /* Since the SPL runs before ATF, MU1 will not be started yet, so use MU0 */
50 #define SC_IPC_CH SC_IPC_AP_CH0 50 #define SC_IPC_CH SC_IPC_AP_CH0
51 51
52 #endif 52 #endif
53 53
54 54
55 #define CONFIG_REMAKE_ELF 55 #define CONFIG_REMAKE_ELF
56 56
57 #define CONFIG_BOARD_EARLY_INIT_F 57 #define CONFIG_BOARD_EARLY_INIT_F
58 #define CONFIG_ARCH_MISC_INIT 58 #define CONFIG_ARCH_MISC_INIT
59 59
60 /* Flat Device Tree Definitions */ 60 /* Flat Device Tree Definitions */
61 #define CONFIG_OF_BOARD_SETUP 61 #define CONFIG_OF_BOARD_SETUP
62 62
63 #undef CONFIG_CMD_EXPORTENV 63 #undef CONFIG_CMD_EXPORTENV
64 #undef CONFIG_CMD_IMPORTENV 64 #undef CONFIG_CMD_IMPORTENV
65 #undef CONFIG_CMD_IMLS 65 #undef CONFIG_CMD_IMLS
66 66
67 #undef CONFIG_CMD_CRC32 67 #undef CONFIG_CMD_CRC32
68 #undef CONFIG_BOOTM_NETBSD 68 #undef CONFIG_BOOTM_NETBSD
69 69
70 #define CONFIG_FSL_ESDHC 70 #define CONFIG_FSL_ESDHC
71 #define CONFIG_FSL_USDHC 71 #define CONFIG_FSL_USDHC
72 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 72 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
73 #define USDHC1_BASE_ADDR 0x5B010000 73 #define USDHC1_BASE_ADDR 0x5B010000
74 #define USDHC2_BASE_ADDR 0x5B020000 74 #define USDHC2_BASE_ADDR 0x5B020000
75 #define USDHC3_BASE_ADDR 0x5B030000 75 #define USDHC3_BASE_ADDR 0x5B030000
76 #ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2 76 #ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
77 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ 77 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
78 #endif 78 #endif
79 79
80 #define CONFIG_ENV_OVERWRITE 80 #define CONFIG_ENV_OVERWRITE
81 81
82 #define CONFIG_SCSI 82 #define CONFIG_SCSI
83 #define CONFIG_SCSI_AHCI 83 #define CONFIG_SCSI_AHCI
84 #define CONFIG_SCSI_AHCI_PLAT 84 #define CONFIG_SCSI_AHCI_PLAT
85 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 85 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
86 #define CONFIG_CMD_SCSI 86 #define CONFIG_CMD_SCSI
87 #define CONFIG_LIBATA 87 #define CONFIG_LIBATA
88 #define CONFIG_SYS_SCSI_MAX_LUN 1 88 #define CONFIG_SYS_SCSI_MAX_LUN 1
89 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 89 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
90 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 90 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
91 #define CONFIG_SYS_SATA_MAX_DEVICE 1 91 #define CONFIG_SYS_SATA_MAX_DEVICE 1
92 #define CONFIG_SATA_IMX 92 #define CONFIG_SATA_IMX
93 93
94 #define CONFIG_FSL_HSIO 94 #define CONFIG_FSL_HSIO
95 #define CONFIG_PCIE_IMX8X 95 #define CONFIG_PCIE_IMX8X
96 #define CONFIG_CMD_PCI 96 #define CONFIG_CMD_PCI
97 #define CONFIG_PCI 97 #define CONFIG_PCI
98 #define CONFIG_PCI_PNP 98 #define CONFIG_PCI_PNP
99 #define CONFIG_PCI_SCAN_SHOW 99 #define CONFIG_PCI_SCAN_SHOW
100 100
101 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 101 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
102 /* FUSE command */ 102 /* FUSE command */
103 #define CONFIG_CMD_FUSE 103 #define CONFIG_CMD_FUSE
104 104
105 /* GPIO configs */ 105 /* GPIO configs */
106 #define CONFIG_MXC_GPIO 106 #define CONFIG_MXC_GPIO
107 107
108 /* ENET Config */ 108 /* ENET Config */
109 #define CONFIG_MII 109 #define CONFIG_MII
110 110
111 #define CONFIG_FEC_MXC 111 #define CONFIG_FEC_MXC
112 #define CONFIG_FEC_XCV_TYPE RGMII 112 #define CONFIG_FEC_XCV_TYPE RGMII
113 #define FEC_QUIRK_ENET_MAC 113 #define FEC_QUIRK_ENET_MAC
114 114
115 #define CONFIG_PHY_GIGE /* Support for 1000BASE-X */ 115 #define CONFIG_PHY_GIGE /* Support for 1000BASE-X */
116 #define CONFIG_PHYLIB 116 #define CONFIG_PHYLIB
117 #define CONFIG_PHY_ATHEROS 117 #define CONFIG_PHY_ATHEROS
118 118
119 /* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */ 119 /* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */
120 #define CONFIG_FEC_ENET_DEV 0 120 #define CONFIG_FEC_ENET_DEV 0
121 121
122 #if (CONFIG_FEC_ENET_DEV == 0) 122 #if (CONFIG_FEC_ENET_DEV == 0)
123 #define IMX_FEC_BASE 0x5B040000 123 #define IMX_FEC_BASE 0x5B040000
124 #define CONFIG_FEC_MXC_PHYADDR 0x0 124 #define CONFIG_FEC_MXC_PHYADDR 0x0
125 #define CONFIG_ETHPRIME "eth0" 125 #define CONFIG_ETHPRIME "eth0"
126 #elif (CONFIG_FEC_ENET_DEV == 1) 126 #elif (CONFIG_FEC_ENET_DEV == 1)
127 #define IMX_FEC_BASE 0x5B050000 127 #define IMX_FEC_BASE 0x5B050000
128 #define CONFIG_FEC_MXC_PHYADDR 0x1 128 #define CONFIG_FEC_MXC_PHYADDR 0x1
129 #define CONFIG_FEC_ENABLE_MAX7322 129 #define CONFIG_FEC_ENABLE_MAX7322
130 #define CONFIG_ETHPRIME "eth1" 130 #define CONFIG_ETHPRIME "eth1"
131 #endif 131 #endif
132 132
133 /* ENET0 MDIO are shared */ 133 /* ENET0 MDIO are shared */
134 #define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000 134 #define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000
135 135
136 #define CONFIG_LIB_RAND 136 #define CONFIG_LIB_RAND
137 #define CONFIG_NET_RANDOM_ETHADDR 137 #define CONFIG_NET_RANDOM_ETHADDR
138 138
139 /* MAX7322 */ 139 /* MAX7322 */
140 #ifdef CONFIG_FEC_ENABLE_MAX7322 140 #ifdef CONFIG_FEC_ENABLE_MAX7322
141 #define CONFIG_MAX7322_I2C_ADDR 0x68 141 #define CONFIG_MAX7322_I2C_ADDR 0x68
142 #define CONFIG_MAX7322_I2C_BUS 2 /* I2C2 */ 142 #define CONFIG_MAX7322_I2C_BUS 2 /* I2C2 */
143 #endif 143 #endif
144 144
145 #ifdef CONFIG_AHAB_BOOT 145 #ifdef CONFIG_AHAB_BOOT
146 #define AHAB_ENV "sec_boot=yes\0" 146 #define AHAB_ENV "sec_boot=yes\0"
147 #else 147 #else
148 #define AHAB_ENV "sec_boot=no\0" 148 #define AHAB_ENV "sec_boot=no\0"
149 #endif 149 #endif
150 150
151 /* Boot M4 */ 151 /* Boot M4 */
152 #define M4_BOOT_ENV \ 152 #define M4_BOOT_ENV \
153 "m4_0_image=m4_0.bin\0" \ 153 "m4_0_image=m4_0.bin\0" \
154 "m4_1_image=m4_1.bin\0" \ 154 "m4_1_image=m4_1.bin\0" \
155 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ 155 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
156 "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \ 156 "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
157 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ 157 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
158 "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \ 158 "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
159 159
160 #ifdef CONFIG_NAND_BOOT 160 #ifdef CONFIG_NAND_BOOT
161 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " 161 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
162 #else 162 #else
163 #define MFG_NAND_PARTITION "" 163 #define MFG_NAND_PARTITION ""
164 #endif 164 #endif
165 165
166 #define CONFIG_MFG_ENV_SETTINGS \ 166 #define CONFIG_MFG_ENV_SETTINGS \
167 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ 167 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
168 "rdinit=/linuxrc " \ 168 "rdinit=/linuxrc " \
169 "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ 169 "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
170 "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ 170 "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
171 "g_mass_storage.iSerialNumber=\"\" "\ 171 "g_mass_storage.iSerialNumber=\"\" "\
172 MFG_NAND_PARTITION \ 172 MFG_NAND_PARTITION \
173 "clk_ignore_unused "\ 173 "clk_ignore_unused "\
174 "\0" \ 174 "\0" \
175 "initrd_addr=0x83100000\0" \ 175 "initrd_addr=0x83100000\0" \
176 "initrd_high=0xffffffffffffffff\0" \ 176 "initrd_high=0xffffffffffffffff\0" \
177 "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ 177 "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
178 178
179 #define XEN_BOOT_ENV \ 179 #define XEN_BOOT_ENV \
180 "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=2048M dom0_max_vcpus=2 dom0_vcpus_pin=true hmp-unsafe=true\0" \ 180 "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=2048M dom0_max_vcpus=2 dom0_vcpus_pin=true hmp-unsafe=true\0" \
181 "xenlinux_bootargs= \0" \ 181 "xenlinux_bootargs= \0" \
182 "xenlinux_console=hvc0 earlycon=xen\0" \ 182 "xenlinux_console=hvc0 earlycon=xen\0" \
183 "xenlinux_addr=0x85000000\0" \ 183 "xenlinux_addr=0x85000000\0" \
184 "dom0fdt_file=fsl-imx8qm-lpddr4-arm2-dom0.dtb\0" \ 184 "dom0fdt_file=fsl-imx8qm-lpddr4-arm2-dom0.dtb\0" \
185 "xenboot_common=" \ 185 "xenboot_common=" \
186 "${get_cmd} ${loadaddr} xen;" \ 186 "${get_cmd} ${loadaddr} xen;" \
187 "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \ 187 "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \
188 "${get_cmd} ${xenlinux_addr} ${image};" \ 188 "${get_cmd} ${xenlinux_addr} ${image};" \
189 "fdt addr ${fdt_addr};" \ 189 "fdt addr ${fdt_addr};" \
190 "fdt resize 256;" \ 190 "fdt resize 256;" \
191 "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \ 191 "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \
192 "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \ 192 "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \
193 "setenv bootargs ${xenhyper_bootargs};" \ 193 "setenv bootargs ${xenhyper_bootargs};" \
194 "scu_rm dtb ${fdt_addr};" \ 194 "scu_rm dtb ${fdt_addr};" \
195 "booti ${loadaddr} - ${fdt_addr};" \ 195 "booti ${loadaddr} - ${fdt_addr};" \
196 "\0" \ 196 "\0" \
197 "xennetboot=" \ 197 "xennetboot=" \
198 "setenv get_cmd dhcp;" \ 198 "setenv get_cmd dhcp;" \
199 "setenv console ${xenlinux_console};" \ 199 "setenv console ${xenlinux_console};" \
200 "run netargs;" \ 200 "run netargs;" \
201 "run xenboot_common;" \ 201 "run xenboot_common;" \
202 "\0" \ 202 "\0" \
203 "xenmmcboot=" \ 203 "xenmmcboot=" \
204 "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \ 204 "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \
205 "setenv console ${xenlinux_console};" \ 205 "setenv console ${xenlinux_console};" \
206 "run mmcargs;" \ 206 "run mmcargs;" \
207 "run xenboot_common;" \ 207 "run xenboot_common;" \
208 "\0" \ 208 "\0" \
209 209
210 /* Initial environment variables */ 210 /* Initial environment variables */
211 #define CONFIG_EXTRA_ENV_SETTINGS \ 211 #define CONFIG_EXTRA_ENV_SETTINGS \
212 CONFIG_MFG_ENV_SETTINGS \ 212 CONFIG_MFG_ENV_SETTINGS \
213 XEN_BOOT_ENV \ 213 XEN_BOOT_ENV \
214 M4_BOOT_ENV \ 214 M4_BOOT_ENV \
215 AHAB_ENV \ 215 AHAB_ENV \
216 "script=boot.scr\0" \ 216 "script=boot.scr\0" \
217 "image=Image\0" \ 217 "image=Image\0" \
218 "panel=NULL\0" \ 218 "panel=NULL\0" \
219 "console=ttyLP0\0" \ 219 "console=ttyLP0\0" \
220 "earlycon=lpuart32,0x5a060000\0" \ 220 "earlycon=lpuart32,0x5a060000\0" \
221 "fdt_addr=0x83000000\0" \ 221 "fdt_addr=0x83000000\0" \
222 "fdt_high=0xffffffffffffffff\0" \ 222 "fdt_high=0xffffffffffffffff\0" \
223 "cntr_addr=0x98000000\0" \ 223 "cntr_addr=0x98000000\0" \
224 "cntr_file=os_cntr_signed.bin\0" \ 224 "cntr_file=os_cntr_signed.bin\0" \
225 "boot_fdt=try\0" \ 225 "boot_fdt=try\0" \
226 "fdt_file="__stringify(CONFIG_DEFAULT_DEVICE_TREE)".dtb\0" \ 226 "fdt_file="__stringify(CONFIG_DEFAULT_DEVICE_TREE)".dtb\0" \
227 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ 227 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
228 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ 228 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
229 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 229 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
230 "mmcautodetect=yes\0" \ 230 "mmcautodetect=yes\0" \
231 "mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \ 231 "mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \
232 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 232 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
233 "bootscript=echo Running bootscript from mmc ...; " \ 233 "bootscript=echo Running bootscript from mmc ...; " \
234 "source\0" \ 234 "source\0" \
235 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 235 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
236 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 236 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
237 "hdp_addr=0x84000000\0" \ 237 "hdp_addr=0x84000000\0" \
238 "hdp_file=dpfw.bin\0" \ 238 "hdp_file=dpfw.bin\0" \
239 "loadhdp=fatload mmc ${mmcdev}:${mmcpart} ${hdp_addr} ${hdp_file}\0" \ 239 "loadhdp=fatload mmc ${mmcdev}:${mmcpart} ${hdp_addr} ${hdp_file}\0" \
240 "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ 240 "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
241 "auth_os=auth_cntr ${cntr_addr}\0" \ 241 "auth_os=auth_cntr ${cntr_addr}\0" \
242 "mmcboot=echo Booting from mmc ...; " \ 242 "mmcboot=echo Booting from mmc ...; " \
243 "if run loadhdp; then; hdp load ${hdp_addr}; fi;" \ 243 "if run loadhdp; then; hdp load ${hdp_addr}; fi;" \
244 "run mmcargs; " \ 244 "run mmcargs; " \
245 "if test ${sec_boot} = yes; then " \ 245 "if test ${sec_boot} = yes; then " \
246 "if run auth_os; then " \ 246 "if run auth_os; then " \
247 "booti ${loadaddr} - ${fdt_addr}; " \ 247 "booti ${loadaddr} - ${fdt_addr}; " \
248 "else " \ 248 "else " \
249 "echo ERR: failed to authenticate; " \ 249 "echo ERR: failed to authenticate; " \
250 "fi; " \ 250 "fi; " \
251 "else " \ 251 "else " \
252 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 252 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
253 "if run loadfdt; then " \ 253 "if run loadfdt; then " \
254 "booti ${loadaddr} - ${fdt_addr}; " \ 254 "booti ${loadaddr} - ${fdt_addr}; " \
255 "else " \ 255 "else " \
256 "echo WARN: Cannot load the DT; " \ 256 "echo WARN: Cannot load the DT; " \
257 "fi; " \ 257 "fi; " \
258 "else " \ 258 "else " \
259 "echo wait for boot; " \ 259 "echo wait for boot; " \
260 "fi;" \ 260 "fi;" \
261 "fi;\0" \ 261 "fi;\0" \
262 "netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \ 262 "netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \
263 "root=/dev/nfs " \ 263 "root=/dev/nfs " \
264 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 264 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
265 "netboot=echo Booting from net ...; " \ 265 "netboot=echo Booting from net ...; " \
266 "run netargs; " \ 266 "run netargs; " \
267 "if test ${ip_dyn} = yes; then " \ 267 "if test ${ip_dyn} = yes; then " \
268 "setenv get_cmd dhcp; " \ 268 "setenv get_cmd dhcp; " \
269 "else " \ 269 "else " \
270 "setenv get_cmd tftp; " \ 270 "setenv get_cmd tftp; " \
271 "fi; " \ 271 "fi; " \
272 "if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \ 272 "if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \
273 "if test ${sec_boot} = yes; then " \ 273 "if test ${sec_boot} = yes; then " \
274 "${get_cmd} ${cntr_addr} ${cntr_file}; " \ 274 "${get_cmd} ${cntr_addr} ${cntr_file}; " \
275 "if run auth_os; then " \ 275 "if run auth_os; then " \
276 "booti ${loadaddr} - ${fdt_addr}; " \ 276 "booti ${loadaddr} - ${fdt_addr}; " \
277 "else " \ 277 "else " \
278 "echo ERR: failed to authenticate; " \ 278 "echo ERR: failed to authenticate; " \
279 "fi; " \ 279 "fi; " \
280 "else " \ 280 "else " \
281 "${get_cmd} ${loadaddr} ${image}; " \ 281 "${get_cmd} ${loadaddr} ${image}; " \
282 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 282 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
283 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 283 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
284 "booti ${loadaddr} - ${fdt_addr}; " \ 284 "booti ${loadaddr} - ${fdt_addr}; " \
285 "else " \ 285 "else " \
286 "echo WARN: Cannot load the DT; " \ 286 "echo WARN: Cannot load the DT; " \
287 "fi; " \ 287 "fi; " \
288 "else " \ 288 "else " \
289 "booti; " \ 289 "booti; " \
290 "fi;" \ 290 "fi;" \
291 "fi;\0" 291 "fi;\0"
292 292
293 #define CONFIG_BOOTCOMMAND \ 293 #define CONFIG_BOOTCOMMAND \
294 "mmc dev ${mmcdev}; if mmc rescan; then " \ 294 "mmc dev ${mmcdev}; if mmc rescan; then " \
295 "if run loadbootscript; then " \ 295 "if run loadbootscript; then " \
296 "run bootscript; " \ 296 "run bootscript; " \
297 "else " \ 297 "else " \
298 "if test ${sec_boot} = yes; then " \ 298 "if test ${sec_boot} = yes; then " \
299 "if run loadcntr; then " \ 299 "if run loadcntr; then " \
300 "run mmcboot; " \ 300 "run mmcboot; " \
301 "else run netboot; " \ 301 "else run netboot; " \
302 "fi; " \ 302 "fi; " \
303 "else " \ 303 "else " \
304 "if run loadimage; then " \ 304 "if run loadimage; then " \
305 "run mmcboot; " \ 305 "run mmcboot; " \
306 "else run netboot; " \ 306 "else run netboot; " \
307 "fi; " \ 307 "fi; " \
308 "fi; " \ 308 "fi; " \
309 "fi; " \ 309 "fi; " \
310 "else booti ${loadaddr} - ${fdt_addr}; fi" 310 "else booti ${loadaddr} - ${fdt_addr}; fi"
311 311
312 /* Link Definitions */ 312 /* Link Definitions */
313 #define CONFIG_LOADADDR 0x80280000 313 #define CONFIG_LOADADDR 0x80280000
314 314
315 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 315 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
316 316
317 #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 317 #define CONFIG_SYS_INIT_SP_ADDR 0x80200000
318 318
319 319
320 /* Default environment is in SD */ 320 /* Default environment is in SD */
321 #define CONFIG_ENV_SIZE 0x2000 321 #define CONFIG_ENV_SIZE 0x2000
322 322
323 #ifdef CONFIG_QSPI_BOOT 323 #ifdef CONFIG_QSPI_BOOT
324 #define CONFIG_ENV_OFFSET (4 * 1024 * 1024) 324 #define CONFIG_ENV_OFFSET (4 * 1024 * 1024)
325 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 325 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
326 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 326 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
327 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 327 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
328 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 328 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
329 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 329 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
330 #else 330 #else
331 #define CONFIG_ENV_OFFSET (64 * SZ_64K) 331 #define CONFIG_ENV_OFFSET (64 * SZ_64K)
332 #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ 332 #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
333 #endif 333 #endif
334 334
335 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 335 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
336 336
337 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board, USDHC3 is for SD on base board 337 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board, USDHC3 is for SD on base board
338 * On DDR4 board, USDHC1 is mux for NAND, USDHC2 is for SD, USDHC3 is for SD on base board 338 * On DDR4 board, USDHC1 is mux for NAND, USDHC2 is for SD, USDHC3 is for SD on base board
339 */ 339 */
340 #ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2 340 #ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
341 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC1 */ 341 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC1 */
342 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC1 */ 342 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC1 */
343 #define CONFIG_SYS_FSL_USDHC_NUM 3 343 #define CONFIG_SYS_FSL_USDHC_NUM 3
344 344
345 #else 345 #else
346 346
347 #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */ 347 #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */
348 #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC2 */ 348 #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC2 */
349 #define CONFIG_SYS_FSL_USDHC_NUM 1 349 #define CONFIG_SYS_FSL_USDHC_NUM 1
350 350
351 #endif 351 #endif
352 352
353 /* Size of malloc() pool */ 353 /* Size of malloc() pool */
354 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024) 354 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024)
355 355
356 #define CONFIG_SYS_SDRAM_BASE 0x80000000 356 #define CONFIG_SYS_SDRAM_BASE 0x80000000
357 #define CONFIG_NR_DRAM_BANKS 4 357 #define CONFIG_NR_DRAM_BANKS 4
358 #define PHYS_SDRAM_1 0x80000000 358 #define PHYS_SDRAM_1 0x80000000
359 #define PHYS_SDRAM_2 0x880000000 359 #define PHYS_SDRAM_2 0x880000000
360 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ 360 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
361 /* LPDDR4 board total DDR is 6GB, DDR4 board total DDR is 4GB */ 361 /* LPDDR4 board total DDR is 6GB, DDR4 board total DDR is 4GB */
362 #ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2 362 #ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
363 #define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ 363 #define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
364 #else 364 #else
365 #define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ 365 #define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */
366 #endif 366 #endif
367 367
368 #define CONFIG_SYS_MEMTEST_START 0xA0000000 368 #define CONFIG_SYS_MEMTEST_START 0xA0000000
369 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2)) 369 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2))
370 370
371 /* Serial */ 371 /* Serial */
372 #define CONFIG_BAUDRATE 115200 372 #define CONFIG_BAUDRATE 115200
373 373
374 /* Monitor Command Prompt */ 374 /* Monitor Command Prompt */
375 #define CONFIG_HUSH_PARSER 375 #define CONFIG_HUSH_PARSER
376 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 376 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
377 #define CONFIG_SYS_CBSIZE 1024 377 #define CONFIG_SYS_CBSIZE 1024
378 #define CONFIG_SYS_MAXARGS 64 378 #define CONFIG_SYS_MAXARGS 64
379 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 379 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
380 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 380 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
381 sizeof(CONFIG_SYS_PROMPT) + 16) 381 sizeof(CONFIG_SYS_PROMPT) + 16)
382 382
383 /* Generic Timer Definitions */ 383 /* Generic Timer Definitions */
384 #define COUNTER_FREQUENCY 8000000 /* 8MHz */ 384 #define COUNTER_FREQUENCY 8000000 /* 8MHz */
385 385
386 #ifndef CONFIG_DM_PCA953X 386 #ifndef CONFIG_DM_PCA953X
387 #define CONFIG_PCA953X 387 #define CONFIG_PCA953X
388 #define CONFIG_CMD_PCA953X 388 #define CONFIG_CMD_PCA953X
389 #define CONFIG_CMD_PCA953X_INFO 389 #define CONFIG_CMD_PCA953X_INFO
390 #endif 390 #endif
391 391
392 #define CONFIG_IMX_SMMU 392 #define CONFIG_IMX_SMMU
393 393
394 /* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */ 394 /* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */
395 #ifdef CONFIG_FSL_FSPI 395 #ifdef CONFIG_FSL_FSPI
396 #define CONFIG_SF_DEFAULT_BUS 0 396 #define CONFIG_SF_DEFAULT_BUS 0
397 #define CONFIG_SF_DEFAULT_CS 0 397 #define CONFIG_SF_DEFAULT_CS 0
398 #define CONFIG_SF_DEFAULT_SPEED 40000000 398 #define CONFIG_SF_DEFAULT_SPEED 40000000
399 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 399 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
400 #define FSL_FSPI_FLASH_SIZE SZ_64M 400 #define FSL_FSPI_FLASH_SIZE SZ_64M
401 #define FSL_FSPI_FLASH_NUM 1 401 #define FSL_FSPI_FLASH_NUM 1
402 #define FSPI0_BASE_ADDR 0x5d120000 402 #define FSPI0_BASE_ADDR 0x5d120000
403 #define FSPI0_AMBA_BASE 0 403 #define FSPI0_AMBA_BASE 0
404 #define CONFIG_SYS_FSL_FSPI_AHB 404 #define CONFIG_SYS_FSL_FSPI_AHB
405 #endif 405 #endif
406 406
407 /* USB Config */ 407 /* USB Config */
408 #ifdef CONFIG_CMD_USB 408 #ifdef CONFIG_CMD_USB
409 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 409 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
410 410
411 /* USB OTG controller configs */ 411 /* USB OTG controller configs */
412 #ifdef CONFIG_USB_EHCI_HCD 412 #ifdef CONFIG_USB_EHCI_HCD
413 #define CONFIG_USB_HOST_ETHER 413 #define CONFIG_USB_HOST_ETHER
414 #define CONFIG_USB_ETHER_ASIX 414 #define CONFIG_USB_ETHER_ASIX
415 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 415 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
416 #endif 416 #endif
417 #endif /* CONFIG_CMD_USB */ 417 #endif /* CONFIG_CMD_USB */
418 418
419 #ifdef CONFIG_USB_GADGET 419 #ifdef CONFIG_USB_GADGET
420 #define CONFIG_USBD_HS 420 #define CONFIG_USBD_HS
421 #endif 421 #endif
422 422
423 #if defined(CONFIG_ANDROID_SUPPORT) 423 #if defined(CONFIG_ANDROID_SUPPORT)
424 #include "imx8qm_arm2_android.h" 424 #include "imx8qm_arm2_android.h"
425 #endif 425 #endif
426 426
427 /* Framebuffer */ 427 /* Framebuffer */
428 #ifdef CONFIG_VIDEO 428 #ifdef CONFIG_VIDEO
429 #define CONFIG_VIDEO_IMXDPUV1 429 #define CONFIG_VIDEO_IMXDPUV1
430 #define CONFIG_VIDEO_BMP_RLE8 430 #define CONFIG_VIDEO_BMP_RLE8
431 #define CONFIG_SPLASH_SCREEN 431 #define CONFIG_SPLASH_SCREEN
432 #define CONFIG_SPLASH_SCREEN_ALIGN 432 #define CONFIG_SPLASH_SCREEN_ALIGN
433 #define CONFIG_BMP_16BPP 433 #define CONFIG_BMP_16BPP
434 #define CONFIG_VIDEO_LOGO 434 #define CONFIG_VIDEO_LOGO
435 #define CONFIG_VIDEO_BMP_LOGO 435 #define CONFIG_VIDEO_BMP_LOGO
436 #define CONFIG_IMX_VIDEO_SKIP 436 #define CONFIG_IMX_VIDEO_SKIP
437 #endif 437 #endif
438 438
439 #define CONFIG_OF_SYSTEM_SETUP 439 #define CONFIG_OF_SYSTEM_SETUP
440 #define BOOTAUX_RESERVED_MEM_BASE 0x88000000
441 #define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from second 128MB */
442 440
443 #endif /* __IMX8QM_ARM2_H */ 441 #endif /* __IMX8QM_ARM2_H */
444 442
include/configs/imx8qm_mek.h
Diff comments   View file @ 57fa56f
1 /* 1 /*
2 * Copyright 2017-2019 NXP 2 * Copyright 2017-2019 NXP
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __IMX8QM_MEK_H 7 #ifndef __IMX8QM_MEK_H
8 #define __IMX8QM_MEK_H 8 #define __IMX8QM_MEK_H
9 9
10 #include <linux/sizes.h> 10 #include <linux/sizes.h>
11 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/imx-regs.h>
12 #include "imx_env.h" 12 #include "imx_env.h"
13 13
14 #ifdef CONFIG_SPL_BUILD 14 #ifdef CONFIG_SPL_BUILD
15 15
16 #ifdef CONFIG_SPL_SPI_SUPPORT 16 #ifdef CONFIG_SPL_SPI_SUPPORT
17 #define CONFIG_SPL_SPI_LOAD 17 #define CONFIG_SPL_SPI_LOAD
18 #endif 18 #endif
19 19
20 #define CONFIG_PARSE_CONTAINER 20 #define CONFIG_PARSE_CONTAINER
21 #define CONFIG_SPL_TEXT_BASE 0x0 21 #define CONFIG_SPL_TEXT_BASE 0x0
22 #define CONFIG_SPL_MAX_SIZE (124 * 1024) 22 #define CONFIG_SPL_MAX_SIZE (124 * 1024)
23 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) 23 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
24 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR 24 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
25 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (flash.bin_offset + 2Mb)/sector_size */ 25 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (flash.bin_offset + 2Mb)/sector_size */
26 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x200000 26 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x200000
27 27
28 /* 28 /*
29 * 0x08081000 - 0x08180FFF is for m4_0 xip image, 29 * 0x08081000 - 0x08180FFF is for m4_0 xip image,
30 * 0x08181000 - 0x008280FFF is for m4_1 xip image 30 * 0x08181000 - 0x008280FFF is for m4_1 xip image
31 * So 3rd container image may start from 0x8281000 31 * So 3rd container image may start from 0x8281000
32 */ 32 */
33 #define CONFIG_SYS_UBOOT_BASE 0x08281000 33 #define CONFIG_SYS_UBOOT_BASE 0x08281000
34 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 34 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
35 35
36 36
37 #define CONFIG_SPL_WATCHDOG_SUPPORT 37 #define CONFIG_SPL_WATCHDOG_SUPPORT
38 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 38 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
39 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 39 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
40 #define CONFIG_SPL_STACK 0x013E000 40 #define CONFIG_SPL_STACK 0x013E000
41 #define CONFIG_SPL_LIBCOMMON_SUPPORT 41 #define CONFIG_SPL_LIBCOMMON_SUPPORT
42 #define CONFIG_SPL_LIBGENERIC_SUPPORT 42 #define CONFIG_SPL_LIBGENERIC_SUPPORT
43 #define CONFIG_SPL_SERIAL_SUPPORT 43 #define CONFIG_SPL_SERIAL_SUPPORT
44 #define CONFIG_SPL_BSS_START_ADDR 0x00138000 44 #define CONFIG_SPL_BSS_START_ADDR 0x00138000
45 #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ 45 #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
46 #define CONFIG_SYS_SPL_MALLOC_START 0x00120000 46 #define CONFIG_SYS_SPL_MALLOC_START 0x00120000
47 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x18000 /* 12 KB */ 47 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x18000 /* 12 KB */
48 #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 48 #define CONFIG_SERIAL_LPUART_BASE 0x5a060000
49 #define CONFIG_SYS_ICACHE_OFF 49 #define CONFIG_SYS_ICACHE_OFF
50 #define CONFIG_SYS_DCACHE_OFF 50 #define CONFIG_SYS_DCACHE_OFF
51 #define CONFIG_MALLOC_F_ADDR 0x00120000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ 51 #define CONFIG_MALLOC_F_ADDR 0x00120000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
52 52
53 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE 53 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
54 54
55 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ 55 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
56 56
57 #define CONFIG_OF_EMBED 57 #define CONFIG_OF_EMBED
58 #define CONFIG_ATF_TEXT_BASE 0x80000000 58 #define CONFIG_ATF_TEXT_BASE 0x80000000
59 #define CONFIG_SYS_ATF_START 0x80000000 59 #define CONFIG_SYS_ATF_START 0x80000000
60 /* #define CONFIG_FIT */ 60 /* #define CONFIG_FIT */
61 61
62 /* Since the SPL runs before ATF, MU1 will not be started yet, so use MU0 */ 62 /* Since the SPL runs before ATF, MU1 will not be started yet, so use MU0 */
63 #define SC_IPC_CH SC_IPC_AP_CH0 63 #define SC_IPC_CH SC_IPC_AP_CH0
64 64
65 #endif 65 #endif
66 66
67 67
68 #define CONFIG_REMAKE_ELF 68 #define CONFIG_REMAKE_ELF
69 69
70 #define CONFIG_BOARD_EARLY_INIT_F 70 #define CONFIG_BOARD_EARLY_INIT_F
71 #define CONFIG_ARCH_MISC_INIT 71 #define CONFIG_ARCH_MISC_INIT
72 72
73 #define CONFIG_CMD_READ 73 #define CONFIG_CMD_READ
74 74
75 /* Flat Device Tree Definitions */ 75 /* Flat Device Tree Definitions */
76 #define CONFIG_OF_BOARD_SETUP 76 #define CONFIG_OF_BOARD_SETUP
77 77
78 #undef CONFIG_CMD_EXPORTENV 78 #undef CONFIG_CMD_EXPORTENV
79 #undef CONFIG_CMD_IMPORTENV 79 #undef CONFIG_CMD_IMPORTENV
80 #undef CONFIG_CMD_IMLS 80 #undef CONFIG_CMD_IMLS
81 81
82 #undef CONFIG_CMD_CRC32 82 #undef CONFIG_CMD_CRC32
83 #undef CONFIG_BOOTM_NETBSD 83 #undef CONFIG_BOOTM_NETBSD
84 84
85 #define CONFIG_FSL_ESDHC 85 #define CONFIG_FSL_ESDHC
86 #define CONFIG_FSL_USDHC 86 #define CONFIG_FSL_USDHC
87 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 87 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
88 #define USDHC1_BASE_ADDR 0x5B010000 88 #define USDHC1_BASE_ADDR 0x5B010000
89 #define USDHC2_BASE_ADDR 0x5B020000 89 #define USDHC2_BASE_ADDR 0x5B020000
90 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ 90 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
91 91
92 #define CONFIG_ENV_OVERWRITE 92 #define CONFIG_ENV_OVERWRITE
93 93
94 #define CONFIG_SCSI 94 #define CONFIG_SCSI
95 #define CONFIG_SCSI_AHCI 95 #define CONFIG_SCSI_AHCI
96 #define CONFIG_SCSI_AHCI_PLAT 96 #define CONFIG_SCSI_AHCI_PLAT
97 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 97 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
98 #define CONFIG_CMD_SCSI 98 #define CONFIG_CMD_SCSI
99 #define CONFIG_LIBATA 99 #define CONFIG_LIBATA
100 #define CONFIG_SYS_SCSI_MAX_LUN 1 100 #define CONFIG_SYS_SCSI_MAX_LUN 1
101 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 101 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
102 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 102 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
103 #define CONFIG_SYS_SATA_MAX_DEVICE 1 103 #define CONFIG_SYS_SATA_MAX_DEVICE 1
104 #define CONFIG_SATA_IMX 104 #define CONFIG_SATA_IMX
105 105
106 #define CONFIG_FSL_HSIO 106 #define CONFIG_FSL_HSIO
107 #define CONFIG_PCIE_IMX8X 107 #define CONFIG_PCIE_IMX8X
108 #define CONFIG_CMD_PCI 108 #define CONFIG_CMD_PCI
109 #define CONFIG_PCI 109 #define CONFIG_PCI
110 #define CONFIG_PCI_PNP 110 #define CONFIG_PCI_PNP
111 #define CONFIG_PCI_SCAN_SHOW 111 #define CONFIG_PCI_SCAN_SHOW
112 112
113 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 113 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
114 /* FUSE command */ 114 /* FUSE command */
115 #define CONFIG_CMD_FUSE 115 #define CONFIG_CMD_FUSE
116 116
117 /* GPIO configs */ 117 /* GPIO configs */
118 #define CONFIG_MXC_GPIO 118 #define CONFIG_MXC_GPIO
119 119
120 /* ENET Config */ 120 /* ENET Config */
121 #define CONFIG_MII 121 #define CONFIG_MII
122 122
123 #define CONFIG_FEC_MXC 123 #define CONFIG_FEC_MXC
124 #define CONFIG_FEC_XCV_TYPE RGMII 124 #define CONFIG_FEC_XCV_TYPE RGMII
125 #define FEC_QUIRK_ENET_MAC 125 #define FEC_QUIRK_ENET_MAC
126 126
127 #define CONFIG_PHY_GIGE /* Support for 1000BASE-X */ 127 #define CONFIG_PHY_GIGE /* Support for 1000BASE-X */
128 #define CONFIG_PHYLIB 128 #define CONFIG_PHYLIB
129 #define CONFIG_PHY_ATHEROS 129 #define CONFIG_PHY_ATHEROS
130 130
131 /* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */ 131 /* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */
132 #define CONFIG_FEC_ENET_DEV 0 132 #define CONFIG_FEC_ENET_DEV 0
133 133
134 #if (CONFIG_FEC_ENET_DEV == 0) 134 #if (CONFIG_FEC_ENET_DEV == 0)
135 #define IMX_FEC_BASE 0x5B040000 135 #define IMX_FEC_BASE 0x5B040000
136 #define CONFIG_FEC_MXC_PHYADDR 0x0 136 #define CONFIG_FEC_MXC_PHYADDR 0x0
137 #define CONFIG_ETHPRIME "eth0" 137 #define CONFIG_ETHPRIME "eth0"
138 #elif (CONFIG_FEC_ENET_DEV == 1) 138 #elif (CONFIG_FEC_ENET_DEV == 1)
139 #define IMX_FEC_BASE 0x5B050000 139 #define IMX_FEC_BASE 0x5B050000
140 #define CONFIG_FEC_MXC_PHYADDR 0x1 140 #define CONFIG_FEC_MXC_PHYADDR 0x1
141 #define CONFIG_ETHPRIME "eth1" 141 #define CONFIG_ETHPRIME "eth1"
142 #endif 142 #endif
143 143
144 /* ENET0 MDIO are shared */ 144 /* ENET0 MDIO are shared */
145 #define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000 145 #define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000
146 146
147 #define CONFIG_LIB_RAND 147 #define CONFIG_LIB_RAND
148 #define CONFIG_NET_RANDOM_ETHADDR 148 #define CONFIG_NET_RANDOM_ETHADDR
149 149
150 #ifdef CONFIG_AHAB_BOOT 150 #ifdef CONFIG_AHAB_BOOT
151 #define AHAB_ENV "sec_boot=yes\0" 151 #define AHAB_ENV "sec_boot=yes\0"
152 #else 152 #else
153 #define AHAB_ENV "sec_boot=no\0" 153 #define AHAB_ENV "sec_boot=no\0"
154 #endif 154 #endif
155 155
156 #define JAILHOUSE_ENV \ 156 #define JAILHOUSE_ENV \
157 "jh_mmcboot=" \ 157 "jh_mmcboot=" \
158 "setenv fdt_file fsl-imx8qm-mek-root.dtb;"\ 158 "setenv fdt_file fsl-imx8qm-mek-root.dtb;"\
159 "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ 159 "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \
160 "run mmcboot; \0" \ 160 "run mmcboot; \0" \
161 "jh_netboot=" \ 161 "jh_netboot=" \
162 "setenv fdt_file fsl-imx8qm-mek-root.dtb;"\ 162 "setenv fdt_file fsl-imx8qm-mek-root.dtb;"\
163 "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ 163 "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \
164 "run netboot; \0" 164 "run netboot; \0"
165 165
166 #define XEN_BOOT_ENV \ 166 #define XEN_BOOT_ENV \
167 "domu-android-auto=no\0" \ 167 "domu-android-auto=no\0" \
168 "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=2048M dom0_max_vcpus=2 dom0_vcpus_pin=true hmp-unsafe=true\0" \ 168 "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=2048M dom0_max_vcpus=2 dom0_vcpus_pin=true hmp-unsafe=true\0" \
169 "xenlinux_bootargs= \0" \ 169 "xenlinux_bootargs= \0" \
170 "xenlinux_console=hvc0 earlycon=xen\0" \ 170 "xenlinux_console=hvc0 earlycon=xen\0" \
171 "xenlinux_addr=0x92000000\0" \ 171 "xenlinux_addr=0x92000000\0" \
172 "dom0fdt_file=fsl-imx8qm-mek-dom0.dtb\0" \ 172 "dom0fdt_file=fsl-imx8qm-mek-dom0.dtb\0" \
173 "xenboot_common=" \ 173 "xenboot_common=" \
174 "${get_cmd} ${loadaddr} xen;" \ 174 "${get_cmd} ${loadaddr} xen;" \
175 "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \ 175 "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \
176 "if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \ 176 "if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \
177 "if ${get_cmd} ${hdprx_addr} ${hdprx_file}; then; hdprx load ${hdprx_addr}; fi;" \ 177 "if ${get_cmd} ${hdprx_addr} ${hdprx_file}; then; hdprx load ${hdprx_addr}; fi;" \
178 "${get_cmd} ${xenlinux_addr} ${image};" \ 178 "${get_cmd} ${xenlinux_addr} ${image};" \
179 "fdt addr ${fdt_addr};" \ 179 "fdt addr ${fdt_addr};" \
180 "fdt resize 256;" \ 180 "fdt resize 256;" \
181 "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \ 181 "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \
182 "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \ 182 "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \
183 "if test ${domu-android-auto} = yes; then; " \ 183 "if test ${domu-android-auto} = yes; then; " \
184 "fdt set /domu/doma android-auto <1>;" \ 184 "fdt set /domu/doma android-auto <1>;" \
185 "fdt rm /gpio@5d090000 power-domains;" \ 185 "fdt rm /gpio@5d090000 power-domains;" \
186 "fi;" \ 186 "fi;" \
187 "setenv bootargs ${xenhyper_bootargs};" \ 187 "setenv bootargs ${xenhyper_bootargs};" \
188 "booti ${loadaddr} - ${fdt_addr};" \ 188 "booti ${loadaddr} - ${fdt_addr};" \
189 "\0" \ 189 "\0" \
190 "xennetboot=" \ 190 "xennetboot=" \
191 "setenv get_cmd dhcp;" \ 191 "setenv get_cmd dhcp;" \
192 "setenv console ${xenlinux_console};" \ 192 "setenv console ${xenlinux_console};" \
193 "run netargs;" \ 193 "run netargs;" \
194 "run xenboot_common;" \ 194 "run xenboot_common;" \
195 "\0" \ 195 "\0" \
196 "xenmmcboot=" \ 196 "xenmmcboot=" \
197 "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \ 197 "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \
198 "setenv console ${xenlinux_console};" \ 198 "setenv console ${xenlinux_console};" \
199 "run mmcargs;" \ 199 "run mmcargs;" \
200 "run xenboot_common;" \ 200 "run xenboot_common;" \
201 "\0" \ 201 "\0" \
202 /* Boot M4 */ 202 /* Boot M4 */
203 #define M4_BOOT_ENV \ 203 #define M4_BOOT_ENV \
204 "m4_0_image=m4_0.bin\0" \ 204 "m4_0_image=m4_0.bin\0" \
205 "m4_1_image=m4_1.bin\0" \ 205 "m4_1_image=m4_1.bin\0" \
206 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ 206 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
207 "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \ 207 "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
208 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ 208 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
209 "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \ 209 "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
210 210
211 #ifdef CONFIG_NAND_BOOT 211 #ifdef CONFIG_NAND_BOOT
212 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " 212 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
213 #else 213 #else
214 #define MFG_NAND_PARTITION "" 214 #define MFG_NAND_PARTITION ""
215 #endif 215 #endif
216 216
217 #define CONFIG_MFG_ENV_SETTINGS \ 217 #define CONFIG_MFG_ENV_SETTINGS \
218 CONFIG_MFG_ENV_SETTINGS_DEFAULT \ 218 CONFIG_MFG_ENV_SETTINGS_DEFAULT \
219 "initrd_addr=0x83100000\0" \ 219 "initrd_addr=0x83100000\0" \
220 "initrd_high=0xffffffffffffffff\0" \ 220 "initrd_high=0xffffffffffffffff\0" \
221 "emmc_dev=0\0" \ 221 "emmc_dev=0\0" \
222 "sd_dev=1\0" \ 222 "sd_dev=1\0" \
223 223
224 /* Initial environment variables */ 224 /* Initial environment variables */
225 #define CONFIG_EXTRA_ENV_SETTINGS \ 225 #define CONFIG_EXTRA_ENV_SETTINGS \
226 CONFIG_MFG_ENV_SETTINGS \ 226 CONFIG_MFG_ENV_SETTINGS \
227 M4_BOOT_ENV \ 227 M4_BOOT_ENV \
228 XEN_BOOT_ENV \ 228 XEN_BOOT_ENV \
229 JAILHOUSE_ENV\ 229 JAILHOUSE_ENV\
230 AHAB_ENV \ 230 AHAB_ENV \
231 "script=boot.scr\0" \ 231 "script=boot.scr\0" \
232 "image=Image\0" \ 232 "image=Image\0" \
233 "panel=NULL\0" \ 233 "panel=NULL\0" \
234 "console=ttyLP0\0" \ 234 "console=ttyLP0\0" \
235 "earlycon=lpuart32,0x5a060000\0" \ 235 "earlycon=lpuart32,0x5a060000\0" \
236 "fdt_addr=0x83000000\0" \ 236 "fdt_addr=0x83000000\0" \
237 "fdt_high=0xffffffffffffffff\0" \ 237 "fdt_high=0xffffffffffffffff\0" \
238 "cntr_addr=0x98000000\0" \ 238 "cntr_addr=0x98000000\0" \
239 "cntr_file=os_cntr_signed.bin\0" \ 239 "cntr_file=os_cntr_signed.bin\0" \
240 "boot_fdt=try\0" \ 240 "boot_fdt=try\0" \
241 "fdt_file=undefined\0" \ 241 "fdt_file=undefined\0" \
242 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ 242 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
243 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ 243 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
244 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 244 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
245 "mmcautodetect=yes\0" \ 245 "mmcautodetect=yes\0" \
246 "mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \ 246 "mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \
247 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 247 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
248 "bootscript=echo Running bootscript from mmc ...; " \ 248 "bootscript=echo Running bootscript from mmc ...; " \
249 "source\0" \ 249 "source\0" \
250 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 250 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
251 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 251 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
252 "hdp_addr=0x84000000\0" \ 252 "hdp_addr=0x84000000\0" \
253 "hdprx_addr=0x84800000\0" \ 253 "hdprx_addr=0x84800000\0" \
254 "hdp_file=hdmitxfw.bin\0" \ 254 "hdp_file=hdmitxfw.bin\0" \
255 "hdprx_file=hdmirxfw.bin\0" \ 255 "hdprx_file=hdmirxfw.bin\0" \
256 "loadhdp=fatload mmc ${mmcdev}:${mmcpart} ${hdp_addr} ${hdp_file}\0" \ 256 "loadhdp=fatload mmc ${mmcdev}:${mmcpart} ${hdp_addr} ${hdp_file}\0" \
257 "loadhdprx=fatload mmc ${mmcdev}:${mmcpart} ${hdprx_addr} ${hdprx_file}\0" \ 257 "loadhdprx=fatload mmc ${mmcdev}:${mmcpart} ${hdprx_addr} ${hdprx_file}\0" \
258 "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \ 258 "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \
259 "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ 259 "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
260 "auth_os=auth_cntr ${cntr_addr}\0" \ 260 "auth_os=auth_cntr ${cntr_addr}\0" \
261 "mmcboot=echo Booting from mmc ...; " \ 261 "mmcboot=echo Booting from mmc ...; " \
262 "if run loadhdp; then; hdp load ${hdp_addr}; fi;" \ 262 "if run loadhdp; then; hdp load ${hdp_addr}; fi;" \
263 "if run loadhdprx; then; hdprx load ${hdprx_addr}; fi;" \ 263 "if run loadhdprx; then; hdprx load ${hdprx_addr}; fi;" \
264 "run mmcargs; " \ 264 "run mmcargs; " \
265 "if test ${sec_boot} = yes; then " \ 265 "if test ${sec_boot} = yes; then " \
266 "if run auth_os; then " \ 266 "if run auth_os; then " \
267 "run boot_os; " \ 267 "run boot_os; " \
268 "else " \ 268 "else " \
269 "echo ERR: failed to authenticate; " \ 269 "echo ERR: failed to authenticate; " \
270 "fi; " \ 270 "fi; " \
271 "else " \ 271 "else " \
272 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 272 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
273 "if run loadfdt; then " \ 273 "if run loadfdt; then " \
274 "run boot_os; " \ 274 "run boot_os; " \
275 "else " \ 275 "else " \
276 "echo WARN: Cannot load the DT; " \ 276 "echo WARN: Cannot load the DT; " \
277 "fi; " \ 277 "fi; " \
278 "else " \ 278 "else " \
279 "echo wait for boot; " \ 279 "echo wait for boot; " \
280 "fi;" \ 280 "fi;" \
281 "fi;\0" \ 281 "fi;\0" \
282 "netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \ 282 "netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \
283 "root=/dev/nfs " \ 283 "root=/dev/nfs " \
284 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 284 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
285 "netboot=echo Booting from net ...; " \ 285 "netboot=echo Booting from net ...; " \
286 "run netargs; " \ 286 "run netargs; " \
287 "if test ${ip_dyn} = yes; then " \ 287 "if test ${ip_dyn} = yes; then " \
288 "setenv get_cmd dhcp; " \ 288 "setenv get_cmd dhcp; " \
289 "else " \ 289 "else " \
290 "setenv get_cmd tftp; " \ 290 "setenv get_cmd tftp; " \
291 "fi; " \ 291 "fi; " \
292 "if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \ 292 "if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \
293 "if ${get_cmd} ${hdprx_addr} ${hdprx_file}; then; hdprx load ${hdprx_addr}; fi;" \ 293 "if ${get_cmd} ${hdprx_addr} ${hdprx_file}; then; hdprx load ${hdprx_addr}; fi;" \
294 "if test ${sec_boot} = yes; then " \ 294 "if test ${sec_boot} = yes; then " \
295 "${get_cmd} ${cntr_addr} ${cntr_file}; " \ 295 "${get_cmd} ${cntr_addr} ${cntr_file}; " \
296 "if run auth_os; then " \ 296 "if run auth_os; then " \
297 "run boot_os; " \ 297 "run boot_os; " \
298 "else " \ 298 "else " \
299 "echo ERR: failed to authenticate; " \ 299 "echo ERR: failed to authenticate; " \
300 "fi; " \ 300 "fi; " \
301 "else " \ 301 "else " \
302 "${get_cmd} ${loadaddr} ${image}; " \ 302 "${get_cmd} ${loadaddr} ${image}; " \
303 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 303 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
304 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 304 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
305 "run boot_os; " \ 305 "run boot_os; " \
306 "else " \ 306 "else " \
307 "echo WARN: Cannot load the DT; " \ 307 "echo WARN: Cannot load the DT; " \
308 "fi; " \ 308 "fi; " \
309 "else " \ 309 "else " \
310 "booti; " \ 310 "booti; " \
311 "fi;" \ 311 "fi;" \
312 "fi;\0" 312 "fi;\0"
313 313
314 #define CONFIG_BOOTCOMMAND \ 314 #define CONFIG_BOOTCOMMAND \
315 "mmc dev ${mmcdev}; if mmc rescan; then " \ 315 "mmc dev ${mmcdev}; if mmc rescan; then " \
316 "if run loadbootscript; then " \ 316 "if run loadbootscript; then " \
317 "run bootscript; " \ 317 "run bootscript; " \
318 "else " \ 318 "else " \
319 "if test ${sec_boot} = yes; then " \ 319 "if test ${sec_boot} = yes; then " \
320 "if run loadcntr; then " \ 320 "if run loadcntr; then " \
321 "run mmcboot; " \ 321 "run mmcboot; " \
322 "else run netboot; " \ 322 "else run netboot; " \
323 "fi; " \ 323 "fi; " \
324 "else " \ 324 "else " \
325 "if run loadimage; then " \ 325 "if run loadimage; then " \
326 "run mmcboot; " \ 326 "run mmcboot; " \
327 "else run netboot; " \ 327 "else run netboot; " \
328 "fi; " \ 328 "fi; " \
329 "fi; " \ 329 "fi; " \
330 "fi; " \ 330 "fi; " \
331 "else booti ${loadaddr} - ${fdt_addr}; fi" 331 "else booti ${loadaddr} - ${fdt_addr}; fi"
332 332
333 /* Link Definitions */ 333 /* Link Definitions */
334 #define CONFIG_LOADADDR 0x80280000 334 #define CONFIG_LOADADDR 0x80280000
335 335
336 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 336 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
337 337
338 #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 338 #define CONFIG_SYS_INIT_SP_ADDR 0x80200000
339 339
340 340
341 /* Default environment is in SD */ 341 /* Default environment is in SD */
342 #define CONFIG_ENV_SIZE 0x2000 342 #define CONFIG_ENV_SIZE 0x2000
343 343
344 #ifdef CONFIG_QSPI_BOOT 344 #ifdef CONFIG_QSPI_BOOT
345 #define CONFIG_ENV_OFFSET (4 * 1024 * 1024) 345 #define CONFIG_ENV_OFFSET (4 * 1024 * 1024)
346 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 346 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
347 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 347 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
348 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 348 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
349 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 349 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
350 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 350 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
351 #else 351 #else
352 #define CONFIG_ENV_OFFSET (64 * SZ_64K) 352 #define CONFIG_ENV_OFFSET (64 * SZ_64K)
353 #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ 353 #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
354 #endif 354 #endif
355 355
356 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 356 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
357 357
358 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ 358 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
359 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ 359 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
360 #define CONFIG_SYS_FSL_USDHC_NUM 2 360 #define CONFIG_SYS_FSL_USDHC_NUM 2
361 361
362 362
363 /* Size of malloc() pool */ 363 /* Size of malloc() pool */
364 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024) 364 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024)
365 365
366 #define CONFIG_SYS_SDRAM_BASE 0x80000000 366 #define CONFIG_SYS_SDRAM_BASE 0x80000000
367 #define CONFIG_NR_DRAM_BANKS 4 367 #define CONFIG_NR_DRAM_BANKS 4
368 #define PHYS_SDRAM_1 0x80000000 368 #define PHYS_SDRAM_1 0x80000000
369 #define PHYS_SDRAM_2 0x880000000 369 #define PHYS_SDRAM_2 0x880000000
370 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ 370 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
371 #define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ 371 #define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
372 372
373 #define CONFIG_SYS_MEMTEST_START 0xA0000000 373 #define CONFIG_SYS_MEMTEST_START 0xA0000000
374 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2)) 374 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2))
375 375
376 /* Serial */ 376 /* Serial */
377 #define CONFIG_BAUDRATE 115200 377 #define CONFIG_BAUDRATE 115200
378 378
379 /* Monitor Command Prompt */ 379 /* Monitor Command Prompt */
380 #define CONFIG_HUSH_PARSER 380 #define CONFIG_HUSH_PARSER
381 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 381 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
382 #define CONFIG_SYS_CBSIZE 2048 382 #define CONFIG_SYS_CBSIZE 2048
383 #define CONFIG_SYS_MAXARGS 64 383 #define CONFIG_SYS_MAXARGS 64
384 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 384 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
385 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 385 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
386 sizeof(CONFIG_SYS_PROMPT) + 16) 386 sizeof(CONFIG_SYS_PROMPT) + 16)
387 387
388 /* Generic Timer Definitions */ 388 /* Generic Timer Definitions */
389 #define COUNTER_FREQUENCY 8000000 /* 8MHz */ 389 #define COUNTER_FREQUENCY 8000000 /* 8MHz */
390 390
391 #define CONFIG_IMX_SMMU 391 #define CONFIG_IMX_SMMU
392 392
393 /* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */ 393 /* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */
394 #ifdef CONFIG_FSL_FSPI 394 #ifdef CONFIG_FSL_FSPI
395 #define CONFIG_SF_DEFAULT_BUS 0 395 #define CONFIG_SF_DEFAULT_BUS 0
396 #define CONFIG_SF_DEFAULT_CS 0 396 #define CONFIG_SF_DEFAULT_CS 0
397 #define CONFIG_SF_DEFAULT_SPEED 40000000 397 #define CONFIG_SF_DEFAULT_SPEED 40000000
398 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 398 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
399 #define FSL_FSPI_FLASH_SIZE SZ_64M 399 #define FSL_FSPI_FLASH_SIZE SZ_64M
400 #define FSL_FSPI_FLASH_NUM 1 400 #define FSL_FSPI_FLASH_NUM 1
401 #define FSPI0_BASE_ADDR 0x5d120000 401 #define FSPI0_BASE_ADDR 0x5d120000
402 #define FSPI0_AMBA_BASE 0 402 #define FSPI0_AMBA_BASE 0
403 #define CONFIG_SYS_FSL_FSPI_AHB 403 #define CONFIG_SYS_FSL_FSPI_AHB
404 #endif 404 #endif
405 405
406 #define CONFIG_SERIAL_TAG 406 #define CONFIG_SERIAL_TAG
407 407
408 /* USB Config */ 408 /* USB Config */
409 #ifndef CONFIG_SPL_BUILD 409 #ifndef CONFIG_SPL_BUILD
410 #define CONFIG_CMD_USB 410 #define CONFIG_CMD_USB
411 #define CONFIG_USB_STORAGE 411 #define CONFIG_USB_STORAGE
412 #define CONFIG_USBD_HS 412 #define CONFIG_USBD_HS
413 413
414 #define CONFIG_CMD_USB_MASS_STORAGE 414 #define CONFIG_CMD_USB_MASS_STORAGE
415 #define CONFIG_USB_GADGET_MASS_STORAGE 415 #define CONFIG_USB_GADGET_MASS_STORAGE
416 #define CONFIG_USB_FUNCTION_MASS_STORAGE 416 #define CONFIG_USB_FUNCTION_MASS_STORAGE
417 417
418 #define CONFIG_USB_EHCI_HCD 418 #define CONFIG_USB_EHCI_HCD
419 #endif 419 #endif
420 420
421 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 421 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
422 422
423 /* USB OTG controller configs */ 423 /* USB OTG controller configs */
424 #ifdef CONFIG_USB_EHCI_HCD 424 #ifdef CONFIG_USB_EHCI_HCD
425 #define CONFIG_USB_EHCI_MX6 425 #define CONFIG_USB_EHCI_MX6
426 #define CONFIG_USB_HOST_ETHER 426 #define CONFIG_USB_HOST_ETHER
427 #define CONFIG_USB_ETHER_ASIX 427 #define CONFIG_USB_ETHER_ASIX
428 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 428 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
429 #endif 429 #endif
430 430
431 /* Framebuffer */ 431 /* Framebuffer */
432 #ifdef CONFIG_VIDEO 432 #ifdef CONFIG_VIDEO
433 #define CONFIG_VIDEO_IMXDPUV1 433 #define CONFIG_VIDEO_IMXDPUV1
434 #define CONFIG_VIDEO_BMP_RLE8 434 #define CONFIG_VIDEO_BMP_RLE8
435 #define CONFIG_SPLASH_SCREEN 435 #define CONFIG_SPLASH_SCREEN
436 #define CONFIG_SPLASH_SCREEN_ALIGN 436 #define CONFIG_SPLASH_SCREEN_ALIGN
437 #define CONFIG_BMP_16BPP 437 #define CONFIG_BMP_16BPP
438 #define CONFIG_VIDEO_LOGO 438 #define CONFIG_VIDEO_LOGO
439 #define CONFIG_VIDEO_BMP_LOGO 439 #define CONFIG_VIDEO_BMP_LOGO
440 #define CONFIG_IMX_VIDEO_SKIP 440 #define CONFIG_IMX_VIDEO_SKIP
441 #endif 441 #endif
442 442
443 #define CONFIG_OF_SYSTEM_SETUP 443 #define CONFIG_OF_SYSTEM_SETUP
444 #define BOOTAUX_RESERVED_MEM_BASE 0x88000000
445 #define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from second 128MB */
446 444
447 #if defined(CONFIG_ANDROID_SUPPORT) 445 #if defined(CONFIG_ANDROID_SUPPORT)
448 #include "imx8qm_mek_android.h" 446 #include "imx8qm_mek_android.h"
449 #elif defined (CONFIG_ANDROID_AUTO_SUPPORT) 447 #elif defined (CONFIG_ANDROID_AUTO_SUPPORT)
450 #include "imx8qm_mek_android_auto.h" 448 #include "imx8qm_mek_android_auto.h"
451 #elif defined (CONFIG_IMX8_TRUSTY_XEN) 449 #elif defined (CONFIG_IMX8_TRUSTY_XEN)
452 #include "imx8qm_mek_trusty_xen.h" 450 #include "imx8qm_mek_trusty_xen.h"
453 #endif 451 #endif
454 452
455 #endif /* __IMX8QM_MEK_H */ 453 #endif /* __IMX8QM_MEK_H */
456 454
include/configs/imx8qxp_arm2.h
Diff comments   View file @ 57fa56f
1 /* 1 /*
2 * Copyright 2017-2018 NXP 2 * Copyright 2017-2018 NXP
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __IMX8QXP_ARM2_H 7 #ifndef __IMX8QXP_ARM2_H
8 #define __IMX8QXP_ARM2_H 8 #define __IMX8QXP_ARM2_H
9 9
10 #include <linux/sizes.h> 10 #include <linux/sizes.h>
11 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/imx-regs.h>
12 12
13 #include "imx_env.h" 13 #include "imx_env.h"
14 14
15 #ifdef CONFIG_SPL_BUILD 15 #ifdef CONFIG_SPL_BUILD
16 16
17 #define CONFIG_PARSE_CONTAINER 17 #define CONFIG_PARSE_CONTAINER
18 18
19 #ifdef CONFIG_QSPI_BOOT 19 #ifdef CONFIG_QSPI_BOOT
20 #define CONFIG_SPL_SPI_LOAD 20 #define CONFIG_SPL_SPI_LOAD
21 #endif 21 #endif
22 22
23 #define CONFIG_SPL_TEXT_BASE 0x0 23 #define CONFIG_SPL_TEXT_BASE 0x0
24 #define CONFIG_SPL_MAX_SIZE (124 * 1024) 24 #define CONFIG_SPL_MAX_SIZE (124 * 1024)
25 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) 25 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
26 26
27 #ifdef CONFIG_NAND_BOOT 27 #ifdef CONFIG_NAND_BOOT
28 #ifndef CONFIG_PARSE_CONTAINER 28 #ifndef CONFIG_PARSE_CONTAINER
29 #define CONFIG_SPL_NAND_RAW_ONLY 29 #define CONFIG_SPL_NAND_RAW_ONLY
30 #endif 30 #endif
31 #define CONFIG_SPL_NAND_SUPPORT 31 #define CONFIG_SPL_NAND_SUPPORT
32 #define CONFIG_SPL_DMA_SUPPORT 32 #define CONFIG_SPL_DMA_SUPPORT
33 #define CONFIG_SPL_NAND_MXS 33 #define CONFIG_SPL_NAND_MXS
34 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0x8000000) /*Put the FIT out of first 128MB boot area */ 34 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0x8000000) /*Put the FIT out of first 128MB boot area */
35 #define CONFIG_SPL_NAND_BOOT 35 #define CONFIG_SPL_NAND_BOOT
36 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80000000 36 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80000000
37 #define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 * 1024 ) 37 #define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 * 1024 )
38 38
39 #define CONFIG_SYS_NAND_U_BOOT_START 0x80000000 39 #define CONFIG_SYS_NAND_U_BOOT_START 0x80000000
40 #endif 40 #endif
41 41
42 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR 42 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
43 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (32K + 2Mb)/sector_size */ 43 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (32K + 2Mb)/sector_size */
44 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 44 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
45 45
46 46
47 #define CONFIG_SPL_WATCHDOG_SUPPORT 47 #define CONFIG_SPL_WATCHDOG_SUPPORT
48 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 48 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
49 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 49 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
50 #define CONFIG_SPL_STACK 0x013E000 50 #define CONFIG_SPL_STACK 0x013E000
51 #define CONFIG_SPL_LIBCOMMON_SUPPORT 51 #define CONFIG_SPL_LIBCOMMON_SUPPORT
52 #define CONFIG_SPL_LIBGENERIC_SUPPORT 52 #define CONFIG_SPL_LIBGENERIC_SUPPORT
53 #define CONFIG_SPL_SERIAL_SUPPORT 53 #define CONFIG_SPL_SERIAL_SUPPORT
54 #define CONFIG_SPL_BSS_START_ADDR 0x00138000 54 #define CONFIG_SPL_BSS_START_ADDR 0x00138000
55 #define CONFIG_SPL_BSS_MAX_SIZE 0x8000 /* 20 KB */ 55 #define CONFIG_SPL_BSS_MAX_SIZE 0x8000 /* 20 KB */
56 #define CONFIG_SYS_SPL_MALLOC_START 0x00120000 56 #define CONFIG_SYS_SPL_MALLOC_START 0x00120000
57 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x18000 /* 60 KB */ 57 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x18000 /* 60 KB */
58 #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 58 #define CONFIG_SERIAL_LPUART_BASE 0x5a060000
59 #define CONFIG_SYS_ICACHE_OFF 59 #define CONFIG_SYS_ICACHE_OFF
60 #define CONFIG_SYS_DCACHE_OFF 60 #define CONFIG_SYS_DCACHE_OFF
61 #define CONFIG_MALLOC_F_ADDR 0x00120000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ 61 #define CONFIG_MALLOC_F_ADDR 0x00120000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
62 62
63 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE 63 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
64 64
65 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ 65 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
66 66
67 #define CONFIG_OF_EMBED 67 #define CONFIG_OF_EMBED
68 #define CONFIG_ATF_TEXT_BASE 0x80000000 68 #define CONFIG_ATF_TEXT_BASE 0x80000000
69 #define CONFIG_SYS_ATF_START 0x80000000 69 #define CONFIG_SYS_ATF_START 0x80000000
70 /* #define CONFIG_FIT */ 70 /* #define CONFIG_FIT */
71 71
72 /* Since the SPL runs before ATF, MU1 will not be started yet, so use MU0 */ 72 /* Since the SPL runs before ATF, MU1 will not be started yet, so use MU0 */
73 #define SC_IPC_CH SC_IPC_AP_CH0 73 #define SC_IPC_CH SC_IPC_AP_CH0
74 74
75 #endif 75 #endif
76 76
77 #define CONFIG_REMAKE_ELF 77 #define CONFIG_REMAKE_ELF
78 78
79 #define CONFIG_BOARD_EARLY_INIT_F 79 #define CONFIG_BOARD_EARLY_INIT_F
80 #define CONFIG_ARCH_MISC_INIT 80 #define CONFIG_ARCH_MISC_INIT
81 81
82 /* Flat Device Tree Definitions */ 82 /* Flat Device Tree Definitions */
83 #define CONFIG_OF_BOARD_SETUP 83 #define CONFIG_OF_BOARD_SETUP
84 84
85 #undef CONFIG_CMD_EXPORTENV 85 #undef CONFIG_CMD_EXPORTENV
86 #undef CONFIG_CMD_IMPORTENV 86 #undef CONFIG_CMD_IMPORTENV
87 #undef CONFIG_CMD_IMLS 87 #undef CONFIG_CMD_IMLS
88 88
89 #undef CONFIG_CMD_CRC32 89 #undef CONFIG_CMD_CRC32
90 #undef CONFIG_BOOTM_NETBSD 90 #undef CONFIG_BOOTM_NETBSD
91 91
92 #define CONFIG_FSL_ESDHC 92 #define CONFIG_FSL_ESDHC
93 #define CONFIG_FSL_USDHC 93 #define CONFIG_FSL_USDHC
94 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 94 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
95 #define USDHC1_BASE_ADDR 0x5B010000 95 #define USDHC1_BASE_ADDR 0x5B010000
96 #define USDHC2_BASE_ADDR 0x5B020000 96 #define USDHC2_BASE_ADDR 0x5B020000
97 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ 97 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
98 98
99 #define CONFIG_ENV_OVERWRITE 99 #define CONFIG_ENV_OVERWRITE
100 100
101 101
102 #define CONFIG_FSL_HSIO 102 #define CONFIG_FSL_HSIO
103 #ifdef CONFIG_FSL_HSIO 103 #ifdef CONFIG_FSL_HSIO
104 #define CONFIG_PCIE_IMX8X 104 #define CONFIG_PCIE_IMX8X
105 #define CONFIG_CMD_PCI 105 #define CONFIG_CMD_PCI
106 #define CONFIG_PCI 106 #define CONFIG_PCI
107 #define CONFIG_PCI_PNP 107 #define CONFIG_PCI_PNP
108 #define CONFIG_PCI_SCAN_SHOW 108 #define CONFIG_PCI_SCAN_SHOW
109 #endif 109 #endif
110 110
111 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 111 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
112 112
113 /* FUSE command */ 113 /* FUSE command */
114 #define CONFIG_CMD_FUSE 114 #define CONFIG_CMD_FUSE
115 115
116 /* GPIO configs */ 116 /* GPIO configs */
117 #define CONFIG_MXC_GPIO 117 #define CONFIG_MXC_GPIO
118 118
119 /* ENET Config */ 119 /* ENET Config */
120 #define CONFIG_MII 120 #define CONFIG_MII
121 121
122 #define CONFIG_FEC_MXC 122 #define CONFIG_FEC_MXC
123 #define CONFIG_FEC_XCV_TYPE RGMII 123 #define CONFIG_FEC_XCV_TYPE RGMII
124 #define FEC_QUIRK_ENET_MAC 124 #define FEC_QUIRK_ENET_MAC
125 125
126 #define CONFIG_PHY_GIGE /* Support for 1000BASE-X */ 126 #define CONFIG_PHY_GIGE /* Support for 1000BASE-X */
127 #define CONFIG_PHYLIB 127 #define CONFIG_PHYLIB
128 #define CONFIG_PHY_ATHEROS 128 #define CONFIG_PHY_ATHEROS
129 129
130 /* ENET0 connects AR8031 on CPU board, ENET1 connects to base board and MUX with ESAI, default is ESAI */ 130 /* ENET0 connects AR8031 on CPU board, ENET1 connects to base board and MUX with ESAI, default is ESAI */
131 #define CONFIG_FEC_ENET_DEV 0 131 #define CONFIG_FEC_ENET_DEV 0
132 132
133 #if (CONFIG_FEC_ENET_DEV == 0) 133 #if (CONFIG_FEC_ENET_DEV == 0)
134 #define IMX_FEC_BASE 0x5B040000 134 #define IMX_FEC_BASE 0x5B040000
135 #define CONFIG_FEC_MXC_PHYADDR 0x0 135 #define CONFIG_FEC_MXC_PHYADDR 0x0
136 #define CONFIG_ETHPRIME "eth0" 136 #define CONFIG_ETHPRIME "eth0"
137 #elif (CONFIG_FEC_ENET_DEV == 1) 137 #elif (CONFIG_FEC_ENET_DEV == 1)
138 #define IMX_FEC_BASE 0x5B050000 138 #define IMX_FEC_BASE 0x5B050000
139 #define CONFIG_FEC_MXC_PHYADDR 0x1 139 #define CONFIG_FEC_MXC_PHYADDR 0x1
140 #define CONFIG_FEC_ENABLE_MAX7322 140 #define CONFIG_FEC_ENABLE_MAX7322
141 #define CONFIG_ETHPRIME "eth1" 141 #define CONFIG_ETHPRIME "eth1"
142 #endif 142 #endif
143 143
144 /* ENET0 MDIO are shared */ 144 /* ENET0 MDIO are shared */
145 #define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000 145 #define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000
146 146
147 #define CONFIG_LIB_RAND 147 #define CONFIG_LIB_RAND
148 #define CONFIG_NET_RANDOM_ETHADDR 148 #define CONFIG_NET_RANDOM_ETHADDR
149 149
150 /* MAX7322 */ 150 /* MAX7322 */
151 #ifdef CONFIG_FEC_ENABLE_MAX7322 151 #ifdef CONFIG_FEC_ENABLE_MAX7322
152 #define CONFIG_MAX7322_I2C_ADDR 0x68 152 #define CONFIG_MAX7322_I2C_ADDR 0x68
153 #define CONFIG_MAX7322_I2C_BUS 0 /* I2C1 */ 153 #define CONFIG_MAX7322_I2C_BUS 0 /* I2C1 */
154 #endif 154 #endif
155 155
156 #ifdef CONFIG_AHAB_BOOT 156 #ifdef CONFIG_AHAB_BOOT
157 #define AHAB_ENV "sec_boot=yes\0" 157 #define AHAB_ENV "sec_boot=yes\0"
158 #else 158 #else
159 #define AHAB_ENV "sec_boot=no\0" 159 #define AHAB_ENV "sec_boot=no\0"
160 #endif 160 #endif
161 161
162 /* Boot M4 */ 162 /* Boot M4 */
163 #define M4_BOOT_ENV \ 163 #define M4_BOOT_ENV \
164 "m4_0_image=m4_0.bin\0" \ 164 "m4_0_image=m4_0.bin\0" \
165 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ 165 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
166 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ 166 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
167 167
168 #ifdef CONFIG_NAND_BOOT 168 #ifdef CONFIG_NAND_BOOT
169 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) " 169 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) "
170 #endif 170 #endif
171 171
172 #define CONFIG_MFG_ENV_SETTINGS \ 172 #define CONFIG_MFG_ENV_SETTINGS \
173 CONFIG_MFG_ENV_SETTINGS_DEFAULT \ 173 CONFIG_MFG_ENV_SETTINGS_DEFAULT \
174 "clk_ignore_unused "\ 174 "clk_ignore_unused "\
175 "\0" \ 175 "\0" \
176 "initrd_addr=0x83100000\0" \ 176 "initrd_addr=0x83100000\0" \
177 "initrd_high=0xffffffffffffffff\0" \ 177 "initrd_high=0xffffffffffffffff\0" \
178 "emmc_dev=0\0" \ 178 "emmc_dev=0\0" \
179 "sd_dev=1\0" \ 179 "sd_dev=1\0" \
180 180
181 /* Initial environment variables */ 181 /* Initial environment variables */
182 #ifdef CONFIG_NAND_BOOT 182 #ifdef CONFIG_NAND_BOOT
183 #define CONFIG_EXTRA_ENV_SETTINGS \ 183 #define CONFIG_EXTRA_ENV_SETTINGS \
184 CONFIG_MFG_ENV_SETTINGS \ 184 CONFIG_MFG_ENV_SETTINGS \
185 "bootargs=console=ttyLP0,115200 ubi.mtd=6 " \ 185 "bootargs=console=ttyLP0,115200 ubi.mtd=6 " \
186 "root=ubi0:nandrootfs rootfstype=ubifs " \ 186 "root=ubi0:nandrootfs rootfstype=ubifs " \
187 MFG_NAND_PARTITION \ 187 MFG_NAND_PARTITION \
188 "\0"\ 188 "\0"\
189 "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200\0" \ 189 "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200\0" \
190 "mtdparts=" MFG_NAND_PARTITION "\0" \ 190 "mtdparts=" MFG_NAND_PARTITION "\0" \
191 "fdt_addr=0x83000000\0" 191 "fdt_addr=0x83000000\0"
192 #else 192 #else
193 #define CONFIG_EXTRA_ENV_SETTINGS \ 193 #define CONFIG_EXTRA_ENV_SETTINGS \
194 CONFIG_MFG_ENV_SETTINGS \ 194 CONFIG_MFG_ENV_SETTINGS \
195 M4_BOOT_ENV \ 195 M4_BOOT_ENV \
196 AHAB_ENV \ 196 AHAB_ENV \
197 "script=boot.scr\0" \ 197 "script=boot.scr\0" \
198 "image=Image\0" \ 198 "image=Image\0" \
199 "panel=NULL\0" \ 199 "panel=NULL\0" \
200 "console=ttyLP0\0" \ 200 "console=ttyLP0\0" \
201 "earlycon=lpuart32,0x5a060000\0" \ 201 "earlycon=lpuart32,0x5a060000\0" \
202 "fdt_addr=0x83000000\0" \ 202 "fdt_addr=0x83000000\0" \
203 "fdt_high=0xffffffffffffffff\0" \ 203 "fdt_high=0xffffffffffffffff\0" \
204 "cntr_addr=0x98000000\0" \ 204 "cntr_addr=0x98000000\0" \
205 "cntr_file=os_cntr_signed.bin\0" \ 205 "cntr_file=os_cntr_signed.bin\0" \
206 "boot_fdt=try\0" \ 206 "boot_fdt=try\0" \
207 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ 207 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
208 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ 208 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
209 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ 209 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
210 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 210 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
211 "mmcautodetect=yes\0" \ 211 "mmcautodetect=yes\0" \
212 "mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \ 212 "mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \
213 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 213 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
214 "bootscript=echo Running bootscript from mmc ...; " \ 214 "bootscript=echo Running bootscript from mmc ...; " \
215 "source\0" \ 215 "source\0" \
216 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 216 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
217 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 217 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
218 "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ 218 "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
219 "auth_os=auth_cntr ${cntr_addr}\0" \ 219 "auth_os=auth_cntr ${cntr_addr}\0" \
220 "mmcboot=echo Booting from mmc ...; " \ 220 "mmcboot=echo Booting from mmc ...; " \
221 "run mmcargs; " \ 221 "run mmcargs; " \
222 "if test ${sec_boot} = yes; then " \ 222 "if test ${sec_boot} = yes; then " \
223 "if run auth_os; then " \ 223 "if run auth_os; then " \
224 "booti ${loadaddr} - ${fdt_addr}; " \ 224 "booti ${loadaddr} - ${fdt_addr}; " \
225 "else " \ 225 "else " \
226 "echo ERR: failed to authenticate; " \ 226 "echo ERR: failed to authenticate; " \
227 "fi; " \ 227 "fi; " \
228 "else " \ 228 "else " \
229 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 229 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
230 "if run loadfdt; then " \ 230 "if run loadfdt; then " \
231 "booti ${loadaddr} - ${fdt_addr}; " \ 231 "booti ${loadaddr} - ${fdt_addr}; " \
232 "else " \ 232 "else " \
233 "echo WARN: Cannot load the DT; " \ 233 "echo WARN: Cannot load the DT; " \
234 "fi; " \ 234 "fi; " \
235 "else " \ 235 "else " \
236 "echo wait for boot; " \ 236 "echo wait for boot; " \
237 "fi;" \ 237 "fi;" \
238 "fi;\0" \ 238 "fi;\0" \
239 "netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \ 239 "netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \
240 "root=/dev/nfs " \ 240 "root=/dev/nfs " \
241 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 241 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
242 "netboot=echo Booting from net ...; " \ 242 "netboot=echo Booting from net ...; " \
243 "run netargs; " \ 243 "run netargs; " \
244 "if test ${ip_dyn} = yes; then " \ 244 "if test ${ip_dyn} = yes; then " \
245 "setenv get_cmd dhcp; " \ 245 "setenv get_cmd dhcp; " \
246 "else " \ 246 "else " \
247 "setenv get_cmd tftp; " \ 247 "setenv get_cmd tftp; " \
248 "fi; " \ 248 "fi; " \
249 "if test ${sec_boot} = yes; then " \ 249 "if test ${sec_boot} = yes; then " \
250 "${get_cmd} ${cntr_addr} ${cntr_file}; " \ 250 "${get_cmd} ${cntr_addr} ${cntr_file}; " \
251 "if run auth_os; then " \ 251 "if run auth_os; then " \
252 "booti ${loadaddr} - ${fdt_addr}; " \ 252 "booti ${loadaddr} - ${fdt_addr}; " \
253 "else " \ 253 "else " \
254 "echo ERR: failed to authenticate; " \ 254 "echo ERR: failed to authenticate; " \
255 "fi; " \ 255 "fi; " \
256 "else " \ 256 "else " \
257 "${get_cmd} ${loadaddr} ${image}; " \ 257 "${get_cmd} ${loadaddr} ${image}; " \
258 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 258 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
259 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 259 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
260 "booti ${loadaddr} - ${fdt_addr}; " \ 260 "booti ${loadaddr} - ${fdt_addr}; " \
261 "else " \ 261 "else " \
262 "echo WARN: Cannot load the DT; " \ 262 "echo WARN: Cannot load the DT; " \
263 "fi; " \ 263 "fi; " \
264 "else " \ 264 "else " \
265 "booti; " \ 265 "booti; " \
266 "fi;" \ 266 "fi;" \
267 "fi;\0" 267 "fi;\0"
268 #endif 268 #endif
269 269
270 #ifdef CONFIG_NAND_BOOT 270 #ifdef CONFIG_NAND_BOOT
271 #define CONFIG_BOOTCOMMAND \ 271 #define CONFIG_BOOTCOMMAND \
272 "nand read ${loadaddr} 0x9000000 0x2000000;"\ 272 "nand read ${loadaddr} 0x9000000 0x2000000;"\
273 "nand read ${fdt_addr} 0xB000000 0x100000;"\ 273 "nand read ${fdt_addr} 0xB000000 0x100000;"\
274 "booti ${loadaddr} - ${fdt_addr}" 274 "booti ${loadaddr} - ${fdt_addr}"
275 #else 275 #else
276 #define CONFIG_BOOTCOMMAND \ 276 #define CONFIG_BOOTCOMMAND \
277 "mmc dev ${mmcdev}; if mmc rescan; then " \ 277 "mmc dev ${mmcdev}; if mmc rescan; then " \
278 "if run loadbootscript; then " \ 278 "if run loadbootscript; then " \
279 "run bootscript; " \ 279 "run bootscript; " \
280 "else " \ 280 "else " \
281 "if test ${sec_boot} = yes; then " \ 281 "if test ${sec_boot} = yes; then " \
282 "if run loadcntr; then " \ 282 "if run loadcntr; then " \
283 "run mmcboot; " \ 283 "run mmcboot; " \
284 "else run netboot; " \ 284 "else run netboot; " \
285 "fi; " \ 285 "fi; " \
286 "else " \ 286 "else " \
287 "if run loadimage; then " \ 287 "if run loadimage; then " \
288 "run mmcboot; " \ 288 "run mmcboot; " \
289 "else run netboot; " \ 289 "else run netboot; " \
290 "fi; " \ 290 "fi; " \
291 "fi; " \ 291 "fi; " \
292 "fi; " \ 292 "fi; " \
293 "else booti ${loadaddr} - ${fdt_addr}; fi" 293 "else booti ${loadaddr} - ${fdt_addr}; fi"
294 #endif 294 #endif
295 295
296 /* Link Definitions */ 296 /* Link Definitions */
297 #define CONFIG_LOADADDR 0x80280000 297 #define CONFIG_LOADADDR 0x80280000
298 298
299 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 299 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
300 300
301 #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 301 #define CONFIG_SYS_INIT_SP_ADDR 0x80200000
302 302
303 303
304 /* Default environment is in SD */ 304 /* Default environment is in SD */
305 #define CONFIG_ENV_SIZE 0x2000 305 #define CONFIG_ENV_SIZE 0x2000
306 306
307 #ifdef CONFIG_NAND_BOOT 307 #ifdef CONFIG_NAND_BOOT
308 #define CONFIG_ENV_OFFSET (120 << 20) 308 #define CONFIG_ENV_OFFSET (120 << 20)
309 #elif defined(CONFIG_QSPI_BOOT) 309 #elif defined(CONFIG_QSPI_BOOT)
310 #define CONFIG_ENV_OFFSET (4 * 1024 * 1024) 310 #define CONFIG_ENV_OFFSET (4 * 1024 * 1024)
311 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 311 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
312 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 312 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
313 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 313 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
314 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 314 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
315 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 315 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
316 #else 316 #else
317 #define CONFIG_ENV_OFFSET (64 * SZ_64K) 317 #define CONFIG_ENV_OFFSET (64 * SZ_64K)
318 #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ 318 #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
319 #endif 319 #endif
320 320
321 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 321 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
322 322
323 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board 323 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board
324 */ 324 */
325 #ifdef CONFIG_TARGET_IMX8X_17X17_VAL 325 #ifdef CONFIG_TARGET_IMX8X_17X17_VAL
326 #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ 326 #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
327 #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ 327 #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
328 #define CONFIG_SYS_FSL_USDHC_NUM 1 328 #define CONFIG_SYS_FSL_USDHC_NUM 1
329 #else 329 #else
330 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ 330 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
331 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ 331 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
332 #define CONFIG_SYS_FSL_USDHC_NUM 2 332 #define CONFIG_SYS_FSL_USDHC_NUM 2
333 #endif 333 #endif
334 334
335 /* Size of malloc() pool */ 335 /* Size of malloc() pool */
336 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024) 336 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024)
337 337
338 #define CONFIG_SYS_SDRAM_BASE 0x80000000 338 #define CONFIG_SYS_SDRAM_BASE 0x80000000
339 #define CONFIG_NR_DRAM_BANKS 4 339 #define CONFIG_NR_DRAM_BANKS 4
340 #define PHYS_SDRAM_1 0x80000000 340 #define PHYS_SDRAM_1 0x80000000
341 #define PHYS_SDRAM_2 0x880000000 341 #define PHYS_SDRAM_2 0x880000000
342 #if defined(CONFIG_TARGET_IMX8QXP_DDR3_ARM2) || defined(CONFIG_TARGET_IMX8X_17X17_VAL) 342 #if defined(CONFIG_TARGET_IMX8QXP_DDR3_ARM2) || defined(CONFIG_TARGET_IMX8X_17X17_VAL)
343 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB totally */ 343 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB totally */
344 #define PHYS_SDRAM_2_SIZE 0x00000000 344 #define PHYS_SDRAM_2_SIZE 0x00000000
345 #else 345 #else
346 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ 346 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
347 /* LPDDR4 board total DDR is 3GB */ 347 /* LPDDR4 board total DDR is 3GB */
348 #define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ 348 #define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */
349 #endif 349 #endif
350 350
351 #define CONFIG_SYS_MEMTEST_START 0xA0000000 351 #define CONFIG_SYS_MEMTEST_START 0xA0000000
352 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2)) 352 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2))
353 353
354 /* Serial */ 354 /* Serial */
355 #define CONFIG_BAUDRATE 115200 355 #define CONFIG_BAUDRATE 115200
356 356
357 /* Monitor Command Prompt */ 357 /* Monitor Command Prompt */
358 #define CONFIG_HUSH_PARSER 358 #define CONFIG_HUSH_PARSER
359 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 359 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
360 #define CONFIG_SYS_CBSIZE 1024 360 #define CONFIG_SYS_CBSIZE 1024
361 #define CONFIG_SYS_MAXARGS 64 361 #define CONFIG_SYS_MAXARGS 64
362 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 362 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
363 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 363 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
364 sizeof(CONFIG_SYS_PROMPT) + 16) 364 sizeof(CONFIG_SYS_PROMPT) + 16)
365 365
366 /* Generic Timer Definitions */ 366 /* Generic Timer Definitions */
367 #define COUNTER_FREQUENCY 8000000 /* 8MHz */ 367 #define COUNTER_FREQUENCY 8000000 /* 8MHz */
368 368
369 #ifndef CONFIG_DM_PCA953X 369 #ifndef CONFIG_DM_PCA953X
370 #define CONFIG_PCA953X 370 #define CONFIG_PCA953X
371 #define CONFIG_CMD_PCA953X 371 #define CONFIG_CMD_PCA953X
372 #define CONFIG_CMD_PCA953X_INFO 372 #define CONFIG_CMD_PCA953X_INFO
373 #endif 373 #endif
374 374
375 #define CONFIG_IMX_SMMU 375 #define CONFIG_IMX_SMMU
376 376
377 /* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */ 377 /* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */
378 #ifdef CONFIG_FSL_FSPI 378 #ifdef CONFIG_FSL_FSPI
379 #define CONFIG_SF_DEFAULT_BUS 0 379 #define CONFIG_SF_DEFAULT_BUS 0
380 #define CONFIG_SF_DEFAULT_CS 0 380 #define CONFIG_SF_DEFAULT_CS 0
381 #define CONFIG_SF_DEFAULT_SPEED 40000000 381 #define CONFIG_SF_DEFAULT_SPEED 40000000
382 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 382 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
383 #define FSL_FSPI_FLASH_SIZE SZ_64M 383 #define FSL_FSPI_FLASH_SIZE SZ_64M
384 #define FSL_FSPI_FLASH_NUM 1 384 #define FSL_FSPI_FLASH_NUM 1
385 #define FSPI0_BASE_ADDR 0x5d120000 385 #define FSPI0_BASE_ADDR 0x5d120000
386 #define FSPI0_AMBA_BASE 0 386 #define FSPI0_AMBA_BASE 0
387 #define CONFIG_SYS_FSL_FSPI_AHB 387 #define CONFIG_SYS_FSL_FSPI_AHB
388 #endif 388 #endif
389 389
390 #ifdef CONFIG_CMD_NAND 390 #ifdef CONFIG_CMD_NAND
391 #define CONFIG_NAND_MXS 391 #define CONFIG_NAND_MXS
392 #define CONFIG_CMD_NAND_TRIMFFS 392 #define CONFIG_CMD_NAND_TRIMFFS
393 393
394 /* NAND stuff */ 394 /* NAND stuff */
395 #define CONFIG_SYS_MAX_NAND_DEVICE 1 395 #define CONFIG_SYS_MAX_NAND_DEVICE 1
396 #define CONFIG_SYS_NAND_BASE 0x40000000 396 #define CONFIG_SYS_NAND_BASE 0x40000000
397 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 397 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
398 #define CONFIG_SYS_NAND_ONFI_DETECTION 398 #define CONFIG_SYS_NAND_ONFI_DETECTION
399 399
400 /* DMA stuff, needed for GPMI/MXS NAND support */ 400 /* DMA stuff, needed for GPMI/MXS NAND support */
401 #define CONFIG_APBH_DMA 401 #define CONFIG_APBH_DMA
402 #define CONFIG_APBH_DMA_BURST 402 #define CONFIG_APBH_DMA_BURST
403 #define CONFIG_APBH_DMA_BURST8 403 #define CONFIG_APBH_DMA_BURST8
404 #endif 404 #endif
405 405
406 /* USB Config */ 406 /* USB Config */
407 #ifdef CONFIG_CMD_USB 407 #ifdef CONFIG_CMD_USB
408 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 408 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
409 409
410 /* USB OTG controller configs */ 410 /* USB OTG controller configs */
411 #ifdef CONFIG_USB_EHCI_HCD 411 #ifdef CONFIG_USB_EHCI_HCD
412 #define CONFIG_USB_HOST_ETHER 412 #define CONFIG_USB_HOST_ETHER
413 #define CONFIG_USB_ETHER_ASIX 413 #define CONFIG_USB_ETHER_ASIX
414 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 414 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
415 #endif 415 #endif
416 #endif /* CONFIG_CMD_USB */ 416 #endif /* CONFIG_CMD_USB */
417 417
418 #ifdef CONFIG_USB_GADGET 418 #ifdef CONFIG_USB_GADGET
419 #define CONFIG_USBD_HS 419 #define CONFIG_USBD_HS
420 #endif 420 #endif
421 421
422 #if defined(CONFIG_ANDROID_SUPPORT) 422 #if defined(CONFIG_ANDROID_SUPPORT)
423 #include "imx8qxp_arm2_android.h" 423 #include "imx8qxp_arm2_android.h"
424 #endif 424 #endif
425 425
426 /* Framebuffer */ 426 /* Framebuffer */
427 #ifdef CONFIG_VIDEO 427 #ifdef CONFIG_VIDEO
428 #define CONFIG_VIDEO_IMXDPUV1 428 #define CONFIG_VIDEO_IMXDPUV1
429 #define CONFIG_VIDEO_BMP_RLE8 429 #define CONFIG_VIDEO_BMP_RLE8
430 #define CONFIG_SPLASH_SCREEN 430 #define CONFIG_SPLASH_SCREEN
431 #define CONFIG_SPLASH_SCREEN_ALIGN 431 #define CONFIG_SPLASH_SCREEN_ALIGN
432 #define CONFIG_BMP_16BPP 432 #define CONFIG_BMP_16BPP
433 #define CONFIG_VIDEO_LOGO 433 #define CONFIG_VIDEO_LOGO
434 #define CONFIG_VIDEO_BMP_LOGO 434 #define CONFIG_VIDEO_BMP_LOGO
435 #define CONFIG_IMX_VIDEO_SKIP 435 #define CONFIG_IMX_VIDEO_SKIP
436 #endif 436 #endif
437 437
438 #define CONFIG_OF_SYSTEM_SETUP 438 #define CONFIG_OF_SYSTEM_SETUP
439 #define BOOTAUX_RESERVED_MEM_BASE 0x88000000
440 #define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from second 128MB */
441 439
442 #define CONFIG_CMD_READ 440 #define CONFIG_CMD_READ
443 #define CONFIG_SERIAL_TAG 441 #define CONFIG_SERIAL_TAG
444 442
445 #endif /* __IMX8QXP_ARM2_H */ 443 #endif /* __IMX8QXP_ARM2_H */
446 444
include/configs/imx8qxp_mek.h
Diff comments   View file @ 57fa56f
1 /* 1 /*
2 * Copyright 2017-2019 NXP 2 * Copyright 2017-2019 NXP
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __IMX8QXP_MEK_H 7 #ifndef __IMX8QXP_MEK_H
8 #define __IMX8QXP_MEK_H 8 #define __IMX8QXP_MEK_H
9 9
10 #include <linux/sizes.h> 10 #include <linux/sizes.h>
11 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/imx-regs.h>
12 12
13 #include "imx_env.h" 13 #include "imx_env.h"
14 14
15 #ifdef CONFIG_SPL_BUILD 15 #ifdef CONFIG_SPL_BUILD
16 16
17 #ifdef CONFIG_SPL_SPI_SUPPORT 17 #ifdef CONFIG_SPL_SPI_SUPPORT
18 #define CONFIG_SPL_SPI_LOAD 18 #define CONFIG_SPL_SPI_LOAD
19 #endif 19 #endif
20 20
21 #define CONFIG_PARSE_CONTAINER 21 #define CONFIG_PARSE_CONTAINER
22 #define CONFIG_SPL_TEXT_BASE 0x0 22 #define CONFIG_SPL_TEXT_BASE 0x0
23 #define CONFIG_SPL_MAX_SIZE (124 * 1024) 23 #define CONFIG_SPL_MAX_SIZE (124 * 1024)
24 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) 24 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
25 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR 25 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
26 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (32K + 2Mb)/sector_size */ 26 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (32K + 2Mb)/sector_size */
27 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x200000 27 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x200000
28 28
29 /* 29 /*
30 * 0x08081000 - 0x08180FFF is for m4_0 xip image, 30 * 0x08081000 - 0x08180FFF is for m4_0 xip image,
31 * So 3rd container image may start from 0x8181000 31 * So 3rd container image may start from 0x8181000
32 */ 32 */
33 #define CONFIG_SYS_UBOOT_BASE 0x08181000 33 #define CONFIG_SYS_UBOOT_BASE 0x08181000
34 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 34 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
35 35
36 36
37 #define CONFIG_SPL_WATCHDOG_SUPPORT 37 #define CONFIG_SPL_WATCHDOG_SUPPORT
38 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 38 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
39 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 39 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
40 #define CONFIG_SPL_STACK 0x013E000 40 #define CONFIG_SPL_STACK 0x013E000
41 #define CONFIG_SPL_LIBCOMMON_SUPPORT 41 #define CONFIG_SPL_LIBCOMMON_SUPPORT
42 #define CONFIG_SPL_LIBGENERIC_SUPPORT 42 #define CONFIG_SPL_LIBGENERIC_SUPPORT
43 #define CONFIG_SPL_SERIAL_SUPPORT 43 #define CONFIG_SPL_SERIAL_SUPPORT
44 #define CONFIG_SPL_BSS_START_ADDR 0x00138000 44 #define CONFIG_SPL_BSS_START_ADDR 0x00138000
45 #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ 45 #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
46 #define CONFIG_SYS_SPL_MALLOC_START 0x00120000 46 #define CONFIG_SYS_SPL_MALLOC_START 0x00120000
47 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x18000 /* 12 KB */ 47 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x18000 /* 12 KB */
48 #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 48 #define CONFIG_SERIAL_LPUART_BASE 0x5a060000
49 #define CONFIG_SYS_ICACHE_OFF 49 #define CONFIG_SYS_ICACHE_OFF
50 #define CONFIG_SYS_DCACHE_OFF 50 #define CONFIG_SYS_DCACHE_OFF
51 #define CONFIG_MALLOC_F_ADDR 0x00120000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ 51 #define CONFIG_MALLOC_F_ADDR 0x00120000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
52 52
53 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE 53 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
54 54
55 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ 55 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
56 56
57 #define CONFIG_OF_EMBED 57 #define CONFIG_OF_EMBED
58 #define CONFIG_ATF_TEXT_BASE 0x80000000 58 #define CONFIG_ATF_TEXT_BASE 0x80000000
59 #define CONFIG_SYS_ATF_START 0x80000000 59 #define CONFIG_SYS_ATF_START 0x80000000
60 /* #define CONFIG_FIT */ 60 /* #define CONFIG_FIT */
61 61
62 /* Since the SPL runs before ATF, MU1 will not be started yet, so use MU0 */ 62 /* Since the SPL runs before ATF, MU1 will not be started yet, so use MU0 */
63 #define SC_IPC_CH SC_IPC_AP_CH0 63 #define SC_IPC_CH SC_IPC_AP_CH0
64 64
65 #endif 65 #endif
66 66
67 #define CONFIG_REMAKE_ELF 67 #define CONFIG_REMAKE_ELF
68 68
69 #define CONFIG_BOARD_EARLY_INIT_F 69 #define CONFIG_BOARD_EARLY_INIT_F
70 #define CONFIG_ARCH_MISC_INIT 70 #define CONFIG_ARCH_MISC_INIT
71 71
72 #define CONFIG_CMD_READ 72 #define CONFIG_CMD_READ
73 73
74 /* Flat Device Tree Definitions */ 74 /* Flat Device Tree Definitions */
75 #define CONFIG_OF_BOARD_SETUP 75 #define CONFIG_OF_BOARD_SETUP
76 76
77 #undef CONFIG_CMD_EXPORTENV 77 #undef CONFIG_CMD_EXPORTENV
78 #undef CONFIG_CMD_IMPORTENV 78 #undef CONFIG_CMD_IMPORTENV
79 #undef CONFIG_CMD_IMLS 79 #undef CONFIG_CMD_IMLS
80 80
81 #undef CONFIG_CMD_CRC32 81 #undef CONFIG_CMD_CRC32
82 #undef CONFIG_BOOTM_NETBSD 82 #undef CONFIG_BOOTM_NETBSD
83 83
84 #define CONFIG_FSL_ESDHC 84 #define CONFIG_FSL_ESDHC
85 #define CONFIG_FSL_USDHC 85 #define CONFIG_FSL_USDHC
86 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 86 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
87 #define USDHC1_BASE_ADDR 0x5B010000 87 #define USDHC1_BASE_ADDR 0x5B010000
88 #define USDHC2_BASE_ADDR 0x5B020000 88 #define USDHC2_BASE_ADDR 0x5B020000
89 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ 89 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
90 90
91 #define CONFIG_ENV_OVERWRITE 91 #define CONFIG_ENV_OVERWRITE
92 92
93 93
94 #define CONFIG_FSL_HSIO 94 #define CONFIG_FSL_HSIO
95 #ifdef CONFIG_FSL_HSIO 95 #ifdef CONFIG_FSL_HSIO
96 #define CONFIG_PCIE_IMX8X 96 #define CONFIG_PCIE_IMX8X
97 #define CONFIG_CMD_PCI 97 #define CONFIG_CMD_PCI
98 #define CONFIG_PCI 98 #define CONFIG_PCI
99 #define CONFIG_PCI_PNP 99 #define CONFIG_PCI_PNP
100 #define CONFIG_PCI_SCAN_SHOW 100 #define CONFIG_PCI_SCAN_SHOW
101 #endif 101 #endif
102 102
103 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 103 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
104 104
105 /* FUSE command */ 105 /* FUSE command */
106 #define CONFIG_CMD_FUSE 106 #define CONFIG_CMD_FUSE
107 107
108 /* GPIO configs */ 108 /* GPIO configs */
109 #define CONFIG_MXC_GPIO 109 #define CONFIG_MXC_GPIO
110 110
111 /* ENET Config */ 111 /* ENET Config */
112 #define CONFIG_MII 112 #define CONFIG_MII
113 113
114 #define CONFIG_FEC_MXC 114 #define CONFIG_FEC_MXC
115 #define CONFIG_FEC_XCV_TYPE RGMII 115 #define CONFIG_FEC_XCV_TYPE RGMII
116 #define FEC_QUIRK_ENET_MAC 116 #define FEC_QUIRK_ENET_MAC
117 117
118 #define CONFIG_PHY_GIGE /* Support for 1000BASE-X */ 118 #define CONFIG_PHY_GIGE /* Support for 1000BASE-X */
119 #define CONFIG_PHYLIB 119 #define CONFIG_PHYLIB
120 #define CONFIG_PHY_ATHEROS 120 #define CONFIG_PHY_ATHEROS
121 121
122 /* ENET0 connects AR8031 on CPU board, ENET1 connects to base board and MUX with ESAI, default is ESAI */ 122 /* ENET0 connects AR8031 on CPU board, ENET1 connects to base board and MUX with ESAI, default is ESAI */
123 #define CONFIG_FEC_ENET_DEV 0 123 #define CONFIG_FEC_ENET_DEV 0
124 124
125 #if (CONFIG_FEC_ENET_DEV == 0) 125 #if (CONFIG_FEC_ENET_DEV == 0)
126 #define IMX_FEC_BASE 0x5B040000 126 #define IMX_FEC_BASE 0x5B040000
127 #define CONFIG_FEC_MXC_PHYADDR 0x0 127 #define CONFIG_FEC_MXC_PHYADDR 0x0
128 #define CONFIG_ETHPRIME "eth0" 128 #define CONFIG_ETHPRIME "eth0"
129 #elif (CONFIG_FEC_ENET_DEV == 1) 129 #elif (CONFIG_FEC_ENET_DEV == 1)
130 #define IMX_FEC_BASE 0x5B050000 130 #define IMX_FEC_BASE 0x5B050000
131 #define CONFIG_FEC_MXC_PHYADDR 0x1 131 #define CONFIG_FEC_MXC_PHYADDR 0x1
132 #define CONFIG_ETHPRIME "eth1" 132 #define CONFIG_ETHPRIME "eth1"
133 #endif 133 #endif
134 134
135 /* ENET0 MDIO are shared */ 135 /* ENET0 MDIO are shared */
136 #define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000 136 #define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000
137 137
138 #define CONFIG_LIB_RAND 138 #define CONFIG_LIB_RAND
139 #define CONFIG_NET_RANDOM_ETHADDR 139 #define CONFIG_NET_RANDOM_ETHADDR
140 140
141 #ifdef CONFIG_AHAB_BOOT 141 #ifdef CONFIG_AHAB_BOOT
142 #define AHAB_ENV "sec_boot=yes\0" 142 #define AHAB_ENV "sec_boot=yes\0"
143 #else 143 #else
144 #define AHAB_ENV "sec_boot=no\0" 144 #define AHAB_ENV "sec_boot=no\0"
145 #endif 145 #endif
146 146
147 /* Boot M4 */ 147 /* Boot M4 */
148 #define M4_BOOT_ENV \ 148 #define M4_BOOT_ENV \
149 "m4_0_image=m4_0.bin\0" \ 149 "m4_0_image=m4_0.bin\0" \
150 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ 150 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
151 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ 151 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
152 152
153 #ifdef CONFIG_NAND_BOOT 153 #ifdef CONFIG_NAND_BOOT
154 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " 154 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
155 #else 155 #else
156 #define MFG_NAND_PARTITION "" 156 #define MFG_NAND_PARTITION ""
157 #endif 157 #endif
158 158
159 #define CONFIG_MFG_ENV_SETTINGS \ 159 #define CONFIG_MFG_ENV_SETTINGS \
160 CONFIG_MFG_ENV_SETTINGS_DEFAULT \ 160 CONFIG_MFG_ENV_SETTINGS_DEFAULT \
161 "initrd_addr=0x83100000\0" \ 161 "initrd_addr=0x83100000\0" \
162 "initrd_high=0xffffffffffffffff\0" \ 162 "initrd_high=0xffffffffffffffff\0" \
163 "emmc_dev=0\0" \ 163 "emmc_dev=0\0" \
164 "sd_dev=1\0" \ 164 "sd_dev=1\0" \
165 165
166 #define JAILHOUSE_ENV \ 166 #define JAILHOUSE_ENV \
167 "jh_mmcboot=" \ 167 "jh_mmcboot=" \
168 "setenv fdt_file fsl-imx8qxp-mek-root.dtb;"\ 168 "setenv fdt_file fsl-imx8qxp-mek-root.dtb;"\
169 "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ 169 "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \
170 "run mmcboot; \0" \ 170 "run mmcboot; \0" \
171 "jh_netboot=" \ 171 "jh_netboot=" \
172 "setenv fdt_file fsl-imx8qxp-mek-root.dtb;"\ 172 "setenv fdt_file fsl-imx8qxp-mek-root.dtb;"\
173 "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ 173 "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \
174 "run netboot; \0" 174 "run netboot; \0"
175 175
176 #define XEN_BOOT_ENV \ 176 #define XEN_BOOT_ENV \
177 "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=2048M dom0_max_vcpus=2 dom0_vcpus_pin=true\0" \ 177 "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=2048M dom0_max_vcpus=2 dom0_vcpus_pin=true\0" \
178 "xenlinux_bootargs= \0" \ 178 "xenlinux_bootargs= \0" \
179 "xenlinux_console=hvc0 earlycon=xen\0" \ 179 "xenlinux_console=hvc0 earlycon=xen\0" \
180 "xenlinux_addr=0x92000000\0" \ 180 "xenlinux_addr=0x92000000\0" \
181 "dom0fdt_file=fsl-imx8qxp-mek-dom0.dtb\0" \ 181 "dom0fdt_file=fsl-imx8qxp-mek-dom0.dtb\0" \
182 "xenboot_common=" \ 182 "xenboot_common=" \
183 "${get_cmd} ${loadaddr} xen;" \ 183 "${get_cmd} ${loadaddr} xen;" \
184 "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \ 184 "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \
185 "${get_cmd} ${xenlinux_addr} ${image};" \ 185 "${get_cmd} ${xenlinux_addr} ${image};" \
186 "fdt addr ${fdt_addr};" \ 186 "fdt addr ${fdt_addr};" \
187 "fdt resize 256;" \ 187 "fdt resize 256;" \
188 "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \ 188 "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \
189 "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \ 189 "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \
190 "setenv bootargs ${xenhyper_bootargs};" \ 190 "setenv bootargs ${xenhyper_bootargs};" \
191 "booti ${loadaddr} - ${fdt_addr};" \ 191 "booti ${loadaddr} - ${fdt_addr};" \
192 "\0" \ 192 "\0" \
193 "xennetboot=" \ 193 "xennetboot=" \
194 "setenv get_cmd dhcp;" \ 194 "setenv get_cmd dhcp;" \
195 "setenv console ${xenlinux_console};" \ 195 "setenv console ${xenlinux_console};" \
196 "run netargs;" \ 196 "run netargs;" \
197 "run xenboot_common;" \ 197 "run xenboot_common;" \
198 "\0" \ 198 "\0" \
199 "xenmmcboot=" \ 199 "xenmmcboot=" \
200 "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \ 200 "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \
201 "setenv console ${xenlinux_console};" \ 201 "setenv console ${xenlinux_console};" \
202 "run mmcargs;" \ 202 "run mmcargs;" \
203 "run xenboot_common;" \ 203 "run xenboot_common;" \
204 "\0" \ 204 "\0" \
205 205
206 /* Initial environment variables */ 206 /* Initial environment variables */
207 #define CONFIG_EXTRA_ENV_SETTINGS \ 207 #define CONFIG_EXTRA_ENV_SETTINGS \
208 CONFIG_MFG_ENV_SETTINGS \ 208 CONFIG_MFG_ENV_SETTINGS \
209 M4_BOOT_ENV \ 209 M4_BOOT_ENV \
210 XEN_BOOT_ENV \ 210 XEN_BOOT_ENV \
211 JAILHOUSE_ENV\ 211 JAILHOUSE_ENV\
212 AHAB_ENV \ 212 AHAB_ENV \
213 "script=boot.scr\0" \ 213 "script=boot.scr\0" \
214 "image=Image\0" \ 214 "image=Image\0" \
215 "panel=NULL\0" \ 215 "panel=NULL\0" \
216 "console=ttyLP0\0" \ 216 "console=ttyLP0\0" \
217 "earlycon=lpuart32,0x5a060000\0" \ 217 "earlycon=lpuart32,0x5a060000\0" \
218 "fdt_addr=0x83000000\0" \ 218 "fdt_addr=0x83000000\0" \
219 "fdt_high=0xffffffffffffffff\0" \ 219 "fdt_high=0xffffffffffffffff\0" \
220 "cntr_addr=0x98000000\0" \ 220 "cntr_addr=0x98000000\0" \
221 "cntr_file=os_cntr_signed.bin\0" \ 221 "cntr_file=os_cntr_signed.bin\0" \
222 "boot_fdt=try\0" \ 222 "boot_fdt=try\0" \
223 "fdt_file=undefined\0" \ 223 "fdt_file=undefined\0" \
224 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ 224 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
225 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ 225 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
226 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 226 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
227 "mmcautodetect=yes\0" \ 227 "mmcautodetect=yes\0" \
228 "mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \ 228 "mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \
229 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 229 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
230 "bootscript=echo Running bootscript from mmc ...; " \ 230 "bootscript=echo Running bootscript from mmc ...; " \
231 "source\0" \ 231 "source\0" \
232 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 232 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
233 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 233 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
234 "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ 234 "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
235 "auth_os=auth_cntr ${cntr_addr}\0" \ 235 "auth_os=auth_cntr ${cntr_addr}\0" \
236 "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \ 236 "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \
237 "mmcboot=echo Booting from mmc ...; " \ 237 "mmcboot=echo Booting from mmc ...; " \
238 "run mmcargs; " \ 238 "run mmcargs; " \
239 "if test ${sec_boot} = yes; then " \ 239 "if test ${sec_boot} = yes; then " \
240 "if run auth_os; then " \ 240 "if run auth_os; then " \
241 "run boot_os; " \ 241 "run boot_os; " \
242 "else " \ 242 "else " \
243 "echo ERR: failed to authenticate; " \ 243 "echo ERR: failed to authenticate; " \
244 "fi; " \ 244 "fi; " \
245 "else " \ 245 "else " \
246 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 246 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
247 "if run loadfdt; then " \ 247 "if run loadfdt; then " \
248 "run boot_os; " \ 248 "run boot_os; " \
249 "else " \ 249 "else " \
250 "echo WARN: Cannot load the DT; " \ 250 "echo WARN: Cannot load the DT; " \
251 "fi; " \ 251 "fi; " \
252 "else " \ 252 "else " \
253 "echo wait for boot; " \ 253 "echo wait for boot; " \
254 "fi;" \ 254 "fi;" \
255 "fi;\0" \ 255 "fi;\0" \
256 "netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \ 256 "netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \
257 "root=/dev/nfs " \ 257 "root=/dev/nfs " \
258 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 258 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
259 "netboot=echo Booting from net ...; " \ 259 "netboot=echo Booting from net ...; " \
260 "run netargs; " \ 260 "run netargs; " \
261 "if test ${ip_dyn} = yes; then " \ 261 "if test ${ip_dyn} = yes; then " \
262 "setenv get_cmd dhcp; " \ 262 "setenv get_cmd dhcp; " \
263 "else " \ 263 "else " \
264 "setenv get_cmd tftp; " \ 264 "setenv get_cmd tftp; " \
265 "fi; " \ 265 "fi; " \
266 "if test ${sec_boot} = yes; then " \ 266 "if test ${sec_boot} = yes; then " \
267 "${get_cmd} ${cntr_addr} ${cntr_file}; " \ 267 "${get_cmd} ${cntr_addr} ${cntr_file}; " \
268 "if run auth_os; then " \ 268 "if run auth_os; then " \
269 "run boot_os; " \ 269 "run boot_os; " \
270 "else " \ 270 "else " \
271 "echo ERR: failed to authenticate; " \ 271 "echo ERR: failed to authenticate; " \
272 "fi; " \ 272 "fi; " \
273 "else " \ 273 "else " \
274 "${get_cmd} ${loadaddr} ${image}; " \ 274 "${get_cmd} ${loadaddr} ${image}; " \
275 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 275 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
276 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 276 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
277 "run boot_os; " \ 277 "run boot_os; " \
278 "else " \ 278 "else " \
279 "echo WARN: Cannot load the DT; " \ 279 "echo WARN: Cannot load the DT; " \
280 "fi; " \ 280 "fi; " \
281 "else " \ 281 "else " \
282 "booti; " \ 282 "booti; " \
283 "fi;" \ 283 "fi;" \
284 "fi;\0" 284 "fi;\0"
285 285
286 #define CONFIG_BOOTCOMMAND \ 286 #define CONFIG_BOOTCOMMAND \
287 "mmc dev ${mmcdev}; if mmc rescan; then " \ 287 "mmc dev ${mmcdev}; if mmc rescan; then " \
288 "if run loadbootscript; then " \ 288 "if run loadbootscript; then " \
289 "run bootscript; " \ 289 "run bootscript; " \
290 "else " \ 290 "else " \
291 "if test ${sec_boot} = yes; then " \ 291 "if test ${sec_boot} = yes; then " \
292 "if run loadcntr; then " \ 292 "if run loadcntr; then " \
293 "run mmcboot; " \ 293 "run mmcboot; " \
294 "else run netboot; " \ 294 "else run netboot; " \
295 "fi; " \ 295 "fi; " \
296 "else " \ 296 "else " \
297 "if run loadimage; then " \ 297 "if run loadimage; then " \
298 "run mmcboot; " \ 298 "run mmcboot; " \
299 "else run netboot; " \ 299 "else run netboot; " \
300 "fi; " \ 300 "fi; " \
301 "fi; " \ 301 "fi; " \
302 "fi; " \ 302 "fi; " \
303 "else booti ${loadaddr} - ${fdt_addr}; fi" 303 "else booti ${loadaddr} - ${fdt_addr}; fi"
304 304
305 /* Link Definitions */ 305 /* Link Definitions */
306 #define CONFIG_LOADADDR 0x80280000 306 #define CONFIG_LOADADDR 0x80280000
307 307
308 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 308 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
309 309
310 #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 310 #define CONFIG_SYS_INIT_SP_ADDR 0x80200000
311 311
312 312
313 /* Default environment is in SD */ 313 /* Default environment is in SD */
314 #define CONFIG_ENV_SIZE 0x2000 314 #define CONFIG_ENV_SIZE 0x2000
315 #ifdef CONFIG_QSPI_BOOT 315 #ifdef CONFIG_QSPI_BOOT
316 #define CONFIG_ENV_OFFSET (4 * 1024 * 1024) 316 #define CONFIG_ENV_OFFSET (4 * 1024 * 1024)
317 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 317 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
318 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 318 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
319 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 319 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
320 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 320 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
321 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 321 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
322 #else 322 #else
323 #define CONFIG_ENV_OFFSET (64 * SZ_64K) 323 #define CONFIG_ENV_OFFSET (64 * SZ_64K)
324 #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ 324 #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
325 #endif 325 #endif
326 326
327 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 327 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
328 328
329 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board 329 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board
330 */ 330 */
331 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ 331 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
332 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ 332 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
333 #define CONFIG_SYS_FSL_USDHC_NUM 2 333 #define CONFIG_SYS_FSL_USDHC_NUM 2
334 334
335 /* Size of malloc() pool */ 335 /* Size of malloc() pool */
336 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024) 336 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024)
337 337
338 #define CONFIG_SYS_SDRAM_BASE 0x80000000 338 #define CONFIG_SYS_SDRAM_BASE 0x80000000
339 #define CONFIG_NR_DRAM_BANKS 4 339 #define CONFIG_NR_DRAM_BANKS 4
340 #define PHYS_SDRAM_1 0x80000000 340 #define PHYS_SDRAM_1 0x80000000
341 #define PHYS_SDRAM_2 0x880000000 341 #define PHYS_SDRAM_2 0x880000000
342 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ 342 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
343 /* LPDDR4 board total DDR is 3GB */ 343 /* LPDDR4 board total DDR is 3GB */
344 #define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ 344 #define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */
345 345
346 #define CONFIG_SYS_MEMTEST_START 0xA0000000 346 #define CONFIG_SYS_MEMTEST_START 0xA0000000
347 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2)) 347 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2))
348 348
349 /* Serial */ 349 /* Serial */
350 #define CONFIG_BAUDRATE 115200 350 #define CONFIG_BAUDRATE 115200
351 351
352 /* Monitor Command Prompt */ 352 /* Monitor Command Prompt */
353 #define CONFIG_HUSH_PARSER 353 #define CONFIG_HUSH_PARSER
354 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 354 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
355 #define CONFIG_SYS_CBSIZE 2048 355 #define CONFIG_SYS_CBSIZE 2048
356 #define CONFIG_SYS_MAXARGS 64 356 #define CONFIG_SYS_MAXARGS 64
357 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 357 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
358 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 358 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
359 sizeof(CONFIG_SYS_PROMPT) + 16) 359 sizeof(CONFIG_SYS_PROMPT) + 16)
360 360
361 /* Generic Timer Definitions */ 361 /* Generic Timer Definitions */
362 #define COUNTER_FREQUENCY 8000000 /* 8MHz */ 362 #define COUNTER_FREQUENCY 8000000 /* 8MHz */
363 363
364 #ifndef CONFIG_DM_PCA953X 364 #ifndef CONFIG_DM_PCA953X
365 #define CONFIG_PCA953X 365 #define CONFIG_PCA953X
366 #define CONFIG_CMD_PCA953X 366 #define CONFIG_CMD_PCA953X
367 #define CONFIG_CMD_PCA953X_INFO 367 #define CONFIG_CMD_PCA953X_INFO
368 #endif 368 #endif
369 369
370 #define CONFIG_IMX_SMMU 370 #define CONFIG_IMX_SMMU
371 371
372 /* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */ 372 /* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */
373 #ifdef CONFIG_FSL_FSPI 373 #ifdef CONFIG_FSL_FSPI
374 #define CONFIG_SF_DEFAULT_BUS 0 374 #define CONFIG_SF_DEFAULT_BUS 0
375 #define CONFIG_SF_DEFAULT_CS 0 375 #define CONFIG_SF_DEFAULT_CS 0
376 #define CONFIG_SF_DEFAULT_SPEED 40000000 376 #define CONFIG_SF_DEFAULT_SPEED 40000000
377 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 377 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
378 #define FSL_FSPI_FLASH_SIZE SZ_64M 378 #define FSL_FSPI_FLASH_SIZE SZ_64M
379 #define FSL_FSPI_FLASH_NUM 1 379 #define FSL_FSPI_FLASH_NUM 1
380 #define FSPI0_BASE_ADDR 0x5d120000 380 #define FSPI0_BASE_ADDR 0x5d120000
381 #define FSPI0_AMBA_BASE 0 381 #define FSPI0_AMBA_BASE 0
382 #define CONFIG_SYS_FSL_FSPI_AHB 382 #define CONFIG_SYS_FSL_FSPI_AHB
383 #endif 383 #endif
384 384
385 #define CONFIG_SERIAL_TAG 385 #define CONFIG_SERIAL_TAG
386 386
387 /* USB Config */ 387 /* USB Config */
388 #ifndef CONFIG_SPL_BUILD 388 #ifndef CONFIG_SPL_BUILD
389 #define CONFIG_CMD_USB 389 #define CONFIG_CMD_USB
390 #define CONFIG_USB_STORAGE 390 #define CONFIG_USB_STORAGE
391 #define CONFIG_USBD_HS 391 #define CONFIG_USBD_HS
392 392
393 #define CONFIG_CMD_USB_MASS_STORAGE 393 #define CONFIG_CMD_USB_MASS_STORAGE
394 #define CONFIG_USB_GADGET_MASS_STORAGE 394 #define CONFIG_USB_GADGET_MASS_STORAGE
395 #define CONFIG_USB_FUNCTION_MASS_STORAGE 395 #define CONFIG_USB_FUNCTION_MASS_STORAGE
396 396
397 #define CONFIG_USB_EHCI_HCD 397 #define CONFIG_USB_EHCI_HCD
398 #endif 398 #endif
399 399
400 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 400 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
401 401
402 /* USB OTG controller configs */ 402 /* USB OTG controller configs */
403 #ifdef CONFIG_USB_EHCI_HCD 403 #ifdef CONFIG_USB_EHCI_HCD
404 #define CONFIG_USB_EHCI_MX6 404 #define CONFIG_USB_EHCI_MX6
405 #define CONFIG_USB_HOST_ETHER 405 #define CONFIG_USB_HOST_ETHER
406 #define CONFIG_USB_ETHER_ASIX 406 #define CONFIG_USB_ETHER_ASIX
407 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 407 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
408 #endif 408 #endif
409 409
410 /* Framebuffer */ 410 /* Framebuffer */
411 #ifdef CONFIG_VIDEO 411 #ifdef CONFIG_VIDEO
412 #define CONFIG_VIDEO_IMXDPUV1 412 #define CONFIG_VIDEO_IMXDPUV1
413 #define CONFIG_VIDEO_BMP_RLE8 413 #define CONFIG_VIDEO_BMP_RLE8
414 #define CONFIG_SPLASH_SCREEN 414 #define CONFIG_SPLASH_SCREEN
415 #define CONFIG_SPLASH_SCREEN_ALIGN 415 #define CONFIG_SPLASH_SCREEN_ALIGN
416 #define CONFIG_BMP_16BPP 416 #define CONFIG_BMP_16BPP
417 #define CONFIG_VIDEO_LOGO 417 #define CONFIG_VIDEO_LOGO
418 #define CONFIG_VIDEO_BMP_LOGO 418 #define CONFIG_VIDEO_BMP_LOGO
419 #define CONFIG_IMX_VIDEO_SKIP 419 #define CONFIG_IMX_VIDEO_SKIP
420 #endif 420 #endif
421 421
422 #define CONFIG_OF_SYSTEM_SETUP 422 #define CONFIG_OF_SYSTEM_SETUP
423 #define BOOTAUX_RESERVED_MEM_BASE 0x88000000
424 #define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from second 128MB */
425 423
426 #if defined(CONFIG_ANDROID_SUPPORT) 424 #if defined(CONFIG_ANDROID_SUPPORT)
427 #include "imx8qxp_mek_android.h" 425 #include "imx8qxp_mek_android.h"
428 #elif defined (CONFIG_ANDROID_AUTO_SUPPORT) 426 #elif defined (CONFIG_ANDROID_AUTO_SUPPORT)
429 #include "imx8qxp_mek_android_auto.h" 427 #include "imx8qxp_mek_android_auto.h"
430 #endif 428 #endif
431 429
432 #endif /* __IMX8QXP_MEK_H */ 430 #endif /* __IMX8QXP_MEK_H */
433 431