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Commit 58b2e4326195be2e5fa13feb6b986214e4bbcf0e

Authored by Zhang Bo
1 parent 7f1d172785
Exists in smarc_8mm-imx_v2019.04_4.19.35_1.1.0 and in 1 other branch smarc_8m-imx_v2019.04_4.19.35_1.1.0

MA-15724: hdp: move macro IMX_LOAD_HDMI_FIMRWARE to Kconfig 

Move the macro IMX_LOAD_HDMI_FIMRWARE to Kconfig, so it can be enable or
disable in different defconfig.

Change-Id: I2e1291d3bc2d6efb29309525b33b84ba8f9b83da
Signed-off-by: Zhang Bo <bo.zhang@nxp.com>

Showing 3 changed files with 10 additions and 2 deletions Inline Diff

arch/arm/mach-imx/imx8/Kconfig
Diff comments   View file @ 58b2e43
1 if ARCH_IMX8 1 if ARCH_IMX8
2 2
3 config RECOVER_SPL_DATA_SECTION 3 config RECOVER_SPL_DATA_SECTION
4 bool 4 bool
5 help 5 help
6 Save SPL DATA section for cold boot, restore at warm boot 6 Save SPL DATA section for cold boot, restore at warm boot
7 7
8 config IMX_SMMU 8 config IMX_SMMU
9 bool "Enable SMMU on i.MX8" 9 bool "Enable SMMU on i.MX8"
10 help 10 help
11 Enable the SMMU for peripherals on i.MX8 11 Enable the SMMU for peripherals on i.MX8
12 12
13 config AHAB_BOOT 13 config AHAB_BOOT
14 bool "Support i.MX8 AHAB features" 14 bool "Support i.MX8 AHAB features"
15 imply CMD_DEKBLOB 15 imply CMD_DEKBLOB
16 help 16 help
17 This option enables the support for AHAB secure boot. 17 This option enables the support for AHAB secure boot.
18 18
19 config BOOTAUX_RESERVED_MEM_BASE 19 config BOOTAUX_RESERVED_MEM_BASE
20 hex "Define the reserved memory base address" 20 hex "Define the reserved memory base address"
21 default 0x0 21 default 0x0
22 help 22 help
23 reserve DDR memory for bootaux 23 reserve DDR memory for bootaux
24 24
25 config BOOTAUX_RESERVED_MEM_SIZE 25 config BOOTAUX_RESERVED_MEM_SIZE
26 hex "Define the reserved memory size" 26 hex "Define the reserved memory size"
27 default 0x0 27 default 0x0
28 help 28 help
29 This memory will be reserved by system and linux cannot access. 29 This memory will be reserved by system and linux cannot access.
30 30
31 config IMX_LOAD_HDMI_FIMRWARE
32 bool "Enable HDMI firmware loading"
33 depends on ARCH_IMX8 || VIDEO_IMX_HDP_LOAD
34 help
35 This enable the hdmi firmware loading. It depends on the "hdp" and
36 "hdprx" commands.
37
31 config IMX8 38 config IMX8
32 bool 39 bool
33 40
34 config MU_BASE_SPL 41 config MU_BASE_SPL
35 hex "MU base address used in SPL" 42 hex "MU base address used in SPL"
36 default 0x5d1b0000 43 default 0x5d1b0000
37 help 44 help
38 SPL runs in EL3 mode, it use MU0_A to communicate with SCU. 45 SPL runs in EL3 mode, it use MU0_A to communicate with SCU.
39 So we could not reuse the one in dts which is for normal U-Boot. 46 So we could not reuse the one in dts which is for normal U-Boot.
40 47
41 config IMX8QM 48 config IMX8QM
42 select IMX8 49 select IMX8
43 select SUPPORT_SPL 50 select SUPPORT_SPL
44 select RECOVER_SPL_DATA_SECTION 51 select RECOVER_SPL_DATA_SECTION
45 bool 52 bool
46 53
47 config IMX8QXP 54 config IMX8QXP
48 select IMX8 55 select IMX8
49 select SUPPORT_SPL 56 select SUPPORT_SPL
50 select RECOVER_SPL_DATA_SECTION 57 select RECOVER_SPL_DATA_SECTION
51 bool 58 bool
52 59
53 config SYS_SOC 60 config SYS_SOC
54 default "imx8" 61 default "imx8"
55 62
56 config SMC_FUSE 63 config SMC_FUSE
57 bool "Call fuse commands through SMC" 64 bool "Call fuse commands through SMC"
58 65
59 config IMX8_TRUSTY_XEN 66 config IMX8_TRUSTY_XEN
60 bool "Support Trusty Xen feature" 67 bool "Support Trusty Xen feature"
61 68
62 choice 69 choice
63 prompt "i.MX8 board select" 70 prompt "i.MX8 board select"
64 optional 71 optional
65 72
66 config TARGET_IMX8QXP_MEK 73 config TARGET_IMX8QXP_MEK
67 bool "Support i.MX8QXP MEK board" 74 bool "Support i.MX8QXP MEK board"
68 select BOARD_LATE_INIT 75 select BOARD_LATE_INIT
69 select IMX8QXP 76 select IMX8QXP
70 77
71 config TARGET_IMX8QM_MEK 78 config TARGET_IMX8QM_MEK
72 bool "Support i.MX8QM MEK board" 79 bool "Support i.MX8QM MEK board"
73 select BOARD_LATE_INIT 80 select BOARD_LATE_INIT
74 select IMX8QM 81 select IMX8QM
75 82
76 config TARGET_IMX8QM_LPDDR4_ARM2 83 config TARGET_IMX8QM_LPDDR4_ARM2
77 bool "Support i.MX8QM lpddr4 validation board" 84 bool "Support i.MX8QM lpddr4 validation board"
78 select BOARD_LATE_INIT 85 select BOARD_LATE_INIT
79 select IMX8QM 86 select IMX8QM
80 87
81 config TARGET_IMX8QM_DDR4_ARM2 88 config TARGET_IMX8QM_DDR4_ARM2
82 bool "Support i.MX8QM ddr4 validation board" 89 bool "Support i.MX8QM ddr4 validation board"
83 select BOARD_LATE_INIT 90 select BOARD_LATE_INIT
84 select IMX8QM 91 select IMX8QM
85 92
86 config TARGET_IMX8QXP_LPDDR4_ARM2 93 config TARGET_IMX8QXP_LPDDR4_ARM2
87 bool "Support i.MX8QXP lpddr4 validation board" 94 bool "Support i.MX8QXP lpddr4 validation board"
88 select BOARD_LATE_INIT 95 select BOARD_LATE_INIT
89 select IMX8QXP 96 select IMX8QXP
90 97
91 config TARGET_IMX8QXP_DDR3_ARM2 98 config TARGET_IMX8QXP_DDR3_ARM2
92 bool "Support i.MX8QXP ddr3 validation board" 99 bool "Support i.MX8QXP ddr3 validation board"
93 select BOARD_LATE_INIT 100 select BOARD_LATE_INIT
94 select IMX8QXP 101 select IMX8QXP
95 102
96 config TARGET_IMX8X_17X17_VAL 103 config TARGET_IMX8X_17X17_VAL
97 bool "Support i.MX8QXP/DX 17x17 validation board" 104 bool "Support i.MX8QXP/DX 17x17 validation board"
98 select BOARD_LATE_INIT 105 select BOARD_LATE_INIT
99 select IMX8QXP 106 select IMX8QXP
100 107
101 config TARGET_IMX8DXL_PHANTOM_MEK 108 config TARGET_IMX8DXL_PHANTOM_MEK
102 bool "Support i.MX8DXL PHANTOM MEK board" 109 bool "Support i.MX8DXL PHANTOM MEK board"
103 select BOARD_LATE_INIT 110 select BOARD_LATE_INIT
104 select IMX8QXP 111 select IMX8QXP
105 112
106 endchoice 113 endchoice
107 114
108 source "board/freescale/imx8qxp_mek/Kconfig" 115 source "board/freescale/imx8qxp_mek/Kconfig"
109 source "board/freescale/imx8qm_mek/Kconfig" 116 source "board/freescale/imx8qm_mek/Kconfig"
110 source "board/freescale/imx8qxp_arm2/Kconfig" 117 source "board/freescale/imx8qxp_arm2/Kconfig"
111 source "board/freescale/imx8qm_arm2/Kconfig" 118 source "board/freescale/imx8qm_arm2/Kconfig"
112 source "board/freescale/imx8dxl_phantom_mek/Kconfig" 119 source "board/freescale/imx8dxl_phantom_mek/Kconfig"
113 120
114 endif 121 endif
115 122
board/freescale/imx8qm_mek/imx8qm_mek.c
Diff comments   View file @ 58b2e43
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2017-2018 NXP 3 * Copyright 2017-2018 NXP
4 */ 4 */
5 #include <common.h> 5 #include <common.h>
6 #include <malloc.h> 6 #include <malloc.h>
7 #include <errno.h> 7 #include <errno.h>
8 #include <netdev.h> 8 #include <netdev.h>
9 #include <fsl_ifc.h> 9 #include <fsl_ifc.h>
10 #include <fdt_support.h> 10 #include <fdt_support.h>
11 #include <linux/libfdt.h> 11 #include <linux/libfdt.h>
12 #include <environment.h> 12 #include <environment.h>
13 #include <fsl_esdhc.h> 13 #include <fsl_esdhc.h>
14 #include <i2c.h> 14 #include <i2c.h>
15 15
16 #include <asm/io.h> 16 #include <asm/io.h>
17 #include <asm/gpio.h> 17 #include <asm/gpio.h>
18 #include <asm/arch/clock.h> 18 #include <asm/arch/clock.h>
19 #include <asm/arch/sci/sci.h> 19 #include <asm/arch/sci/sci.h>
20 #include <asm/arch/imx8-pins.h> 20 #include <asm/arch/imx8-pins.h>
21 #include <dm.h> 21 #include <dm.h>
22 #include <imx8_hsio.h> 22 #include <imx8_hsio.h>
23 #include <usb.h> 23 #include <usb.h>
24 #include <asm/arch/iomux.h> 24 #include <asm/arch/iomux.h>
25 #include <asm/arch/sys_proto.h> 25 #include <asm/arch/sys_proto.h>
26 #include <asm/mach-imx/video.h> 26 #include <asm/mach-imx/video.h>
27 #include <asm/arch/video_common.h> 27 #include <asm/arch/video_common.h>
28 #include <power-domain.h> 28 #include <power-domain.h>
29 #include "../common/tcpc.h" 29 #include "../common/tcpc.h"
30 #include <cdns3-uboot.h> 30 #include <cdns3-uboot.h>
31 #include <asm/arch/lpcg.h> 31 #include <asm/arch/lpcg.h>
32 #include <bootm.h> 32 #include <bootm.h>
33 33
34 DECLARE_GLOBAL_DATA_PTR; 34 DECLARE_GLOBAL_DATA_PTR;
35 35
36 #define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ 36 #define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
37 | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) 37 | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
38 38
39 #define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ 39 #define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
40 | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) 40 | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
41 41
42 42
43 #define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ 43 #define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
44 | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) 44 | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
45 45
46 46
47 #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ 47 #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
48 | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) 48 | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
49 49
50 static iomux_cfg_t uart0_pads[] = { 50 static iomux_cfg_t uart0_pads[] = {
51 SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 51 SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
52 SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 52 SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
53 }; 53 };
54 54
55 static void setup_iomux_uart(void) 55 static void setup_iomux_uart(void)
56 { 56 {
57 imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); 57 imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
58 } 58 }
59 59
60 int board_early_init_f(void) 60 int board_early_init_f(void)
61 { 61 {
62 int ret; 62 int ret;
63 63
64 /* When start u-boot in XEN VM, directly return */ 64 /* When start u-boot in XEN VM, directly return */
65 if (IS_ENABLED(CONFIG_XEN)) { 65 if (IS_ENABLED(CONFIG_XEN)) {
66 writel(0xF53535F5, (void __iomem *)0x80000000); 66 writel(0xF53535F5, (void __iomem *)0x80000000);
67 return 0; 67 return 0;
68 } 68 }
69 69
70 /* Set UART0 clock root to 80 MHz */ 70 /* Set UART0 clock root to 80 MHz */
71 sc_pm_clock_rate_t rate = 80000000; 71 sc_pm_clock_rate_t rate = 80000000;
72 72
73 /* Power up UART0 */ 73 /* Power up UART0 */
74 ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON); 74 ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
75 if (ret) 75 if (ret)
76 return ret; 76 return ret;
77 77
78 ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); 78 ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
79 if (ret) 79 if (ret)
80 return ret; 80 return ret;
81 81
82 /* Enable UART0 clock root */ 82 /* Enable UART0 clock root */
83 ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); 83 ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
84 if (ret) 84 if (ret)
85 return ret; 85 return ret;
86 86
87 lpcg_all_clock_on(LPUART_0_LPCG); 87 lpcg_all_clock_on(LPUART_0_LPCG);
88 88
89 setup_iomux_uart(); 89 setup_iomux_uart();
90 90
91 /* Dual bootloader feature will require CAAM access, but JR0 and JR1 will be 91 /* Dual bootloader feature will require CAAM access, but JR0 and JR1 will be
92 * assigned to seco for imx8, use JR3 instead. 92 * assigned to seco for imx8, use JR3 instead.
93 */ 93 */
94 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_DUAL_BOOTLOADER) 94 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_DUAL_BOOTLOADER)
95 sc_pm_set_resource_power_mode(-1, SC_R_CAAM_JR3, SC_PM_PW_MODE_ON); 95 sc_pm_set_resource_power_mode(-1, SC_R_CAAM_JR3, SC_PM_PW_MODE_ON);
96 sc_pm_set_resource_power_mode(-1, SC_R_CAAM_JR3_OUT, SC_PM_PW_MODE_ON); 96 sc_pm_set_resource_power_mode(-1, SC_R_CAAM_JR3_OUT, SC_PM_PW_MODE_ON);
97 #endif 97 #endif
98 98
99 return 0; 99 return 0;
100 } 100 }
101 101
102 #if IS_ENABLED(CONFIG_FEC_MXC) 102 #if IS_ENABLED(CONFIG_FEC_MXC)
103 #include <miiphy.h> 103 #include <miiphy.h>
104 104
105 #ifndef CONFIG_DM_ETH 105 #ifndef CONFIG_DM_ETH
106 static iomux_cfg_t pad_enet1[] = { 106 static iomux_cfg_t pad_enet1[] = {
107 SC_P_ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), 107 SC_P_ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
108 SC_P_ENET1_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), 108 SC_P_ENET1_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
109 SC_P_ENET1_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), 109 SC_P_ENET1_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
110 SC_P_ENET1_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), 110 SC_P_ENET1_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
111 SC_P_ENET1_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), 111 SC_P_ENET1_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
112 SC_P_ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), 112 SC_P_ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
113 SC_P_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), 113 SC_P_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
114 SC_P_ENET1_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), 114 SC_P_ENET1_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
115 SC_P_ENET1_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), 115 SC_P_ENET1_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
116 SC_P_ENET1_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), 116 SC_P_ENET1_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
117 SC_P_ENET1_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), 117 SC_P_ENET1_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
118 SC_P_ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), 118 SC_P_ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
119 119
120 /* Shared MDIO */ 120 /* Shared MDIO */
121 SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), 121 SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
122 SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), 122 SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
123 }; 123 };
124 124
125 static iomux_cfg_t pad_enet0[] = { 125 static iomux_cfg_t pad_enet0[] = {
126 SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), 126 SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
127 SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), 127 SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
128 SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), 128 SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
129 SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), 129 SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
130 SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), 130 SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
131 SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), 131 SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
132 SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), 132 SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
133 SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), 133 SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
134 SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), 134 SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
135 SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), 135 SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
136 SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), 136 SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
137 SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), 137 SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
138 138
139 /* Shared MDIO */ 139 /* Shared MDIO */
140 SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), 140 SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
141 SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), 141 SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
142 }; 142 };
143 143
144 static void setup_iomux_fec(void) 144 static void setup_iomux_fec(void)
145 { 145 {
146 if (0 == CONFIG_FEC_ENET_DEV) 146 if (0 == CONFIG_FEC_ENET_DEV)
147 imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0)); 147 imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0));
148 else 148 else
149 imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1)); 149 imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1));
150 } 150 }
151 151
152 int board_eth_init(bd_t *bis) 152 int board_eth_init(bd_t *bis)
153 { 153 {
154 int ret; 154 int ret;
155 struct power_domain pd; 155 struct power_domain pd;
156 156
157 printf("[%s] %d\n", __func__, __LINE__); 157 printf("[%s] %d\n", __func__, __LINE__);
158 158
159 if (CONFIG_FEC_ENET_DEV) { 159 if (CONFIG_FEC_ENET_DEV) {
160 if (!power_domain_lookup_name("conn_enet1", &pd)) 160 if (!power_domain_lookup_name("conn_enet1", &pd))
161 power_domain_on(&pd); 161 power_domain_on(&pd);
162 } else { 162 } else {
163 if (!power_domain_lookup_name("conn_enet0", &pd)) 163 if (!power_domain_lookup_name("conn_enet0", &pd))
164 power_domain_on(&pd); 164 power_domain_on(&pd);
165 } 165 }
166 166
167 setup_iomux_fec(); 167 setup_iomux_fec();
168 168
169 ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, 169 ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
170 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 170 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
171 if (ret) 171 if (ret)
172 printf("FEC1 MXC: %s:failed\n", __func__); 172 printf("FEC1 MXC: %s:failed\n", __func__);
173 173
174 return ret; 174 return ret;
175 } 175 }
176 #endif 176 #endif
177 177
178 int board_phy_config(struct phy_device *phydev) 178 int board_phy_config(struct phy_device *phydev)
179 { 179 {
180 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); 180 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
181 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); 181 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
182 182
183 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); 183 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
184 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); 184 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
185 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); 185 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
186 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 186 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
187 187
188 if (phydev->drv->config) 188 if (phydev->drv->config)
189 phydev->drv->config(phydev); 189 phydev->drv->config(phydev);
190 190
191 return 0; 191 return 0;
192 } 192 }
193 #endif 193 #endif
194 194
195 #define LVDS_ENABLE IMX_GPIO_NR(1, 6) 195 #define LVDS_ENABLE IMX_GPIO_NR(1, 6)
196 #define MIPI_ENABLE IMX_GPIO_NR(1, 7) 196 #define MIPI_ENABLE IMX_GPIO_NR(1, 7)
197 197
198 #define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20) 198 #define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20)
199 #define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24) 199 #define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24)
200 #define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23) 200 #define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23)
201 201
202 static void board_gpio_init(void) 202 static void board_gpio_init(void)
203 { 203 {
204 /* Enable BB 3V3 */ 204 /* Enable BB 3V3 */
205 gpio_request(BB_GPIO_3V3_1, "bb_3v3_1"); 205 gpio_request(BB_GPIO_3V3_1, "bb_3v3_1");
206 gpio_direction_output(BB_GPIO_3V3_1, 1); 206 gpio_direction_output(BB_GPIO_3V3_1, 1);
207 gpio_request(BB_GPIO_3V3_2, "bb_3v3_2"); 207 gpio_request(BB_GPIO_3V3_2, "bb_3v3_2");
208 gpio_direction_output(BB_GPIO_3V3_2, 1); 208 gpio_direction_output(BB_GPIO_3V3_2, 1);
209 gpio_request(BB_GPIO_3V3_3, "bb_3v3_3"); 209 gpio_request(BB_GPIO_3V3_3, "bb_3v3_3");
210 gpio_direction_output(BB_GPIO_3V3_3, 1); 210 gpio_direction_output(BB_GPIO_3V3_3, 1);
211 211
212 /* enable LVDS SAS boards */ 212 /* enable LVDS SAS boards */
213 gpio_request(LVDS_ENABLE, "lvds_enable"); 213 gpio_request(LVDS_ENABLE, "lvds_enable");
214 gpio_direction_output(LVDS_ENABLE, 1); 214 gpio_direction_output(LVDS_ENABLE, 1);
215 215
216 /* enable MIPI SAS boards */ 216 /* enable MIPI SAS boards */
217 gpio_request(MIPI_ENABLE, "mipi_enable"); 217 gpio_request(MIPI_ENABLE, "mipi_enable");
218 gpio_direction_output(MIPI_ENABLE, 1); 218 gpio_direction_output(MIPI_ENABLE, 1);
219 } 219 }
220 220
221 int checkboard(void) 221 int checkboard(void)
222 { 222 {
223 puts("Board: iMX8QM MEK\n"); 223 puts("Board: iMX8QM MEK\n");
224 224
225 print_bootinfo(); 225 print_bootinfo();
226 226
227 return 0; 227 return 0;
228 } 228 }
229 229
230 #ifdef CONFIG_FSL_HSIO 230 #ifdef CONFIG_FSL_HSIO
231 231
232 #define PCIE_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT)) 232 #define PCIE_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT))
233 static iomux_cfg_t board_pcie_pins[] = { 233 static iomux_cfg_t board_pcie_pins[] = {
234 SC_P_PCIE_CTRL0_CLKREQ_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), 234 SC_P_PCIE_CTRL0_CLKREQ_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
235 SC_P_PCIE_CTRL0_WAKE_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), 235 SC_P_PCIE_CTRL0_WAKE_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
236 SC_P_PCIE_CTRL0_PERST_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), 236 SC_P_PCIE_CTRL0_PERST_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
237 }; 237 };
238 238
239 static void imx8qm_hsio_initialize(void) 239 static void imx8qm_hsio_initialize(void)
240 { 240 {
241 struct power_domain pd; 241 struct power_domain pd;
242 int ret; 242 int ret;
243 243
244 if (!power_domain_lookup_name("hsio_sata0", &pd)) { 244 if (!power_domain_lookup_name("hsio_sata0", &pd)) {
245 ret = power_domain_on(&pd); 245 ret = power_domain_on(&pd);
246 if (ret) 246 if (ret)
247 printf("hsio_sata0 Power up failed! (error = %d)\n", ret); 247 printf("hsio_sata0 Power up failed! (error = %d)\n", ret);
248 } 248 }
249 249
250 if (!power_domain_lookup_name("hsio_pcie0", &pd)) { 250 if (!power_domain_lookup_name("hsio_pcie0", &pd)) {
251 ret = power_domain_on(&pd); 251 ret = power_domain_on(&pd);
252 if (ret) 252 if (ret)
253 printf("hsio_pcie0 Power up failed! (error = %d)\n", ret); 253 printf("hsio_pcie0 Power up failed! (error = %d)\n", ret);
254 } 254 }
255 255
256 if (!power_domain_lookup_name("hsio_pcie1", &pd)) { 256 if (!power_domain_lookup_name("hsio_pcie1", &pd)) {
257 ret = power_domain_on(&pd); 257 ret = power_domain_on(&pd);
258 if (ret) 258 if (ret)
259 printf("hsio_pcie1 Power up failed! (error = %d)\n", ret); 259 printf("hsio_pcie1 Power up failed! (error = %d)\n", ret);
260 } 260 }
261 261
262 if (!power_domain_lookup_name("hsio_gpio", &pd)) { 262 if (!power_domain_lookup_name("hsio_gpio", &pd)) {
263 ret = power_domain_on(&pd); 263 ret = power_domain_on(&pd);
264 if (ret) 264 if (ret)
265 printf("hsio_gpio Power up failed! (error = %d)\n", ret); 265 printf("hsio_gpio Power up failed! (error = %d)\n", ret);
266 } 266 }
267 267
268 lpcg_all_clock_on(HSIO_PCIE_X2_LPCG); 268 lpcg_all_clock_on(HSIO_PCIE_X2_LPCG);
269 lpcg_all_clock_on(HSIO_PCIE_X1_LPCG); 269 lpcg_all_clock_on(HSIO_PCIE_X1_LPCG);
270 lpcg_all_clock_on(HSIO_PHY_X2_LPCG); 270 lpcg_all_clock_on(HSIO_PHY_X2_LPCG);
271 lpcg_all_clock_on(HSIO_PHY_X1_LPCG); 271 lpcg_all_clock_on(HSIO_PHY_X1_LPCG);
272 lpcg_all_clock_on(HSIO_PCIE_X2_CRR2_LPCG); 272 lpcg_all_clock_on(HSIO_PCIE_X2_CRR2_LPCG);
273 lpcg_all_clock_on(HSIO_PCIE_X1_CRR3_LPCG); 273 lpcg_all_clock_on(HSIO_PCIE_X1_CRR3_LPCG);
274 lpcg_all_clock_on(HSIO_MISC_LPCG); 274 lpcg_all_clock_on(HSIO_MISC_LPCG);
275 lpcg_all_clock_on(HSIO_GPIO_LPCG); 275 lpcg_all_clock_on(HSIO_GPIO_LPCG);
276 276
277 imx8_iomux_setup_multiple_pads(board_pcie_pins, ARRAY_SIZE(board_pcie_pins)); 277 imx8_iomux_setup_multiple_pads(board_pcie_pins, ARRAY_SIZE(board_pcie_pins));
278 } 278 }
279 279
280 void pci_init_board(void) 280 void pci_init_board(void)
281 { 281 {
282 /* test the 1 lane mode of the PCIe A controller */ 282 /* test the 1 lane mode of the PCIe A controller */
283 mx8qm_pcie_init(); 283 mx8qm_pcie_init();
284 } 284 }
285 #endif 285 #endif
286 286
287 #ifdef CONFIG_USB 287 #ifdef CONFIG_USB
288 288
289 #ifdef CONFIG_USB_TCPC 289 #ifdef CONFIG_USB_TCPC
290 #define USB_TYPEC_SEL IMX_GPIO_NR(4, 6) 290 #define USB_TYPEC_SEL IMX_GPIO_NR(4, 6)
291 #define USB_TYPEC_EN IMX_GPIO_NR(4, 19) 291 #define USB_TYPEC_EN IMX_GPIO_NR(4, 19)
292 292
293 static iomux_cfg_t ss_mux_gpio[] = { 293 static iomux_cfg_t ss_mux_gpio[] = {
294 SC_P_USB_SS3_TC3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), 294 SC_P_USB_SS3_TC3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
295 SC_P_QSPI1A_SS0_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), 295 SC_P_QSPI1A_SS0_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
296 }; 296 };
297 297
298 struct tcpc_port port; 298 struct tcpc_port port;
299 struct tcpc_port_config port_config = { 299 struct tcpc_port_config port_config = {
300 .i2c_bus = 0, 300 .i2c_bus = 0,
301 .addr = 0x51, 301 .addr = 0x51,
302 .port_type = TYPEC_PORT_DFP, 302 .port_type = TYPEC_PORT_DFP,
303 }; 303 };
304 304
305 void ss_mux_select(enum typec_cc_polarity pol) 305 void ss_mux_select(enum typec_cc_polarity pol)
306 { 306 {
307 if (pol == TYPEC_POLARITY_CC1) 307 if (pol == TYPEC_POLARITY_CC1)
308 gpio_direction_output(USB_TYPEC_SEL, 0); 308 gpio_direction_output(USB_TYPEC_SEL, 0);
309 else 309 else
310 gpio_direction_output(USB_TYPEC_SEL, 1); 310 gpio_direction_output(USB_TYPEC_SEL, 1);
311 } 311 }
312 312
313 static void setup_typec(void) 313 static void setup_typec(void)
314 { 314 {
315 imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); 315 imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
316 gpio_request(USB_TYPEC_SEL, "typec_sel"); 316 gpio_request(USB_TYPEC_SEL, "typec_sel");
317 gpio_request(USB_TYPEC_EN, "typec_en"); 317 gpio_request(USB_TYPEC_EN, "typec_en");
318 318
319 gpio_direction_output(USB_TYPEC_EN, 1); 319 gpio_direction_output(USB_TYPEC_EN, 1);
320 320
321 tcpc_init(&port, port_config, &ss_mux_select); 321 tcpc_init(&port, port_config, &ss_mux_select);
322 } 322 }
323 #endif 323 #endif
324 324
325 int board_usb_init(int index, enum usb_init_type init) 325 int board_usb_init(int index, enum usb_init_type init)
326 { 326 {
327 int ret = 0; 327 int ret = 0;
328 328
329 if (index == 1) { 329 if (index == 1) {
330 if (init == USB_INIT_HOST) { 330 if (init == USB_INIT_HOST) {
331 #ifdef CONFIG_USB_TCPC 331 #ifdef CONFIG_USB_TCPC
332 ret = tcpc_setup_dfp_mode(&port); 332 ret = tcpc_setup_dfp_mode(&port);
333 #endif 333 #endif
334 #ifdef CONFIG_USB_CDNS3_GADGET 334 #ifdef CONFIG_USB_CDNS3_GADGET
335 } else { 335 } else {
336 #ifdef CONFIG_USB_TCPC 336 #ifdef CONFIG_USB_TCPC
337 ret = tcpc_setup_ufp_mode(&port); 337 ret = tcpc_setup_ufp_mode(&port);
338 printf("%d setufp mode %d\n", index, ret); 338 printf("%d setufp mode %d\n", index, ret);
339 #endif 339 #endif
340 #endif 340 #endif
341 } 341 }
342 } 342 }
343 343
344 return ret; 344 return ret;
345 345
346 } 346 }
347 347
348 int board_usb_cleanup(int index, enum usb_init_type init) 348 int board_usb_cleanup(int index, enum usb_init_type init)
349 { 349 {
350 int ret = 0; 350 int ret = 0;
351 351
352 if (index == 1) { 352 if (index == 1) {
353 if (init == USB_INIT_HOST) { 353 if (init == USB_INIT_HOST) {
354 #ifdef CONFIG_USB_TCPC 354 #ifdef CONFIG_USB_TCPC
355 ret = tcpc_disable_src_vbus(&port); 355 ret = tcpc_disable_src_vbus(&port);
356 #endif 356 #endif
357 } 357 }
358 } 358 }
359 359
360 return ret; 360 return ret;
361 } 361 }
362 #endif 362 #endif
363 363
364 int board_init(void) 364 int board_init(void)
365 { 365 {
366 board_gpio_init(); 366 board_gpio_init();
367 367
368 #ifdef CONFIG_FSL_HSIO 368 #ifdef CONFIG_FSL_HSIO
369 imx8qm_hsio_initialize(); 369 imx8qm_hsio_initialize();
370 #endif 370 #endif
371 371
372 #if defined(CONFIG_USB) && defined(CONFIG_USB_TCPC) 372 #if defined(CONFIG_USB) && defined(CONFIG_USB_TCPC)
373 setup_typec(); 373 setup_typec();
374 #endif 374 #endif
375 375
376 return 0; 376 return 0;
377 } 377 }
378 378
379 void board_quiesce_devices(void) 379 void board_quiesce_devices(void)
380 { 380 {
381 const char *power_on_devices[] = { 381 const char *power_on_devices[] = {
382 "dma_lpuart0", 382 "dma_lpuart0",
383 }; 383 };
384 384
385 if (IS_ENABLED(CONFIG_XEN)) { 385 if (IS_ENABLED(CONFIG_XEN)) {
386 /* Clear magic number to let xen know uboot is over */ 386 /* Clear magic number to let xen know uboot is over */
387 writel(0x0, (void __iomem *)0x80000000); 387 writel(0x0, (void __iomem *)0x80000000);
388 return; 388 return;
389 } 389 }
390 390
391 power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices)); 391 power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices));
392 } 392 }
393 393
394 void detail_board_ddr_info(void) 394 void detail_board_ddr_info(void)
395 { 395 {
396 puts("\nDDR "); 396 puts("\nDDR ");
397 } 397 }
398 398
399 /* 399 /*
400 * Board specific reset that is system reset. 400 * Board specific reset that is system reset.
401 */ 401 */
402 void reset_cpu(ulong addr) 402 void reset_cpu(ulong addr)
403 { 403 {
404 /* TODO */ 404 /* TODO */
405 } 405 }
406 406
407 #ifdef CONFIG_OF_BOARD_SETUP 407 #ifdef CONFIG_OF_BOARD_SETUP
408 int ft_board_setup(void *blob, bd_t *bd) 408 int ft_board_setup(void *blob, bd_t *bd)
409 { 409 {
410 return 0; 410 return 0;
411 } 411 }
412 #endif 412 #endif
413 413
414 extern uint32_t _end_ofs; 414 extern uint32_t _end_ofs;
415 int board_late_init(void) 415 int board_late_init(void)
416 { 416 {
417 char *fdt_file; 417 char *fdt_file;
418 bool m4_boot; 418 bool m4_boot;
419 419
420 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 420 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
421 env_set("board_name", "MEK"); 421 env_set("board_name", "MEK");
422 env_set("board_rev", "iMX8QM"); 422 env_set("board_rev", "iMX8QM");
423 #endif 423 #endif
424 424
425 env_set("sec_boot", "no"); 425 env_set("sec_boot", "no");
426 #ifdef CONFIG_AHAB_BOOT 426 #ifdef CONFIG_AHAB_BOOT
427 env_set("sec_boot", "yes"); 427 env_set("sec_boot", "yes");
428 #endif 428 #endif
429 429
430 fdt_file = env_get("fdt_file"); 430 fdt_file = env_get("fdt_file");
431 m4_boot = check_m4_parts_boot(); 431 m4_boot = check_m4_parts_boot();
432 432
433 if (fdt_file && !strcmp(fdt_file, "undefined")) { 433 if (fdt_file && !strcmp(fdt_file, "undefined")) {
434 if (m4_boot) 434 if (m4_boot)
435 env_set("fdt_file", "fsl-imx8qm-mek-rpmsg.dtb"); 435 env_set("fdt_file", "fsl-imx8qm-mek-rpmsg.dtb");
436 else 436 else
437 env_set("fdt_file", "fsl-imx8qm-mek.dtb"); 437 env_set("fdt_file", "fsl-imx8qm-mek.dtb");
438 } 438 }
439 439
440 #ifdef CONFIG_ENV_IS_IN_MMC 440 #ifdef CONFIG_ENV_IS_IN_MMC
441 board_late_mmc_env_init(); 441 board_late_mmc_env_init();
442 #endif 442 #endif
443 443
444 #ifdef IMX_LOAD_HDMI_FIMRWARE 444 #ifdef CONFIG_IMX_LOAD_HDMI_FIMRWARE
445 char *end_of_uboot; 445 char *end_of_uboot;
446 char command[256]; 446 char command[256];
447 end_of_uboot = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs + fdt_totalsize(gd->fdt_blob)); 447 end_of_uboot = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs + fdt_totalsize(gd->fdt_blob));
448 end_of_uboot += 9; 448 end_of_uboot += 9;
449 449
450 /* load hdmitxfw.bin and hdmirxfw.bin*/ 450 /* load hdmitxfw.bin and hdmirxfw.bin*/
451 memcpy((void *)IMX_HDMI_FIRMWARE_LOAD_ADDR, end_of_uboot, 451 memcpy((void *)IMX_HDMI_FIRMWARE_LOAD_ADDR, end_of_uboot,
452 IMX_HDMITX_FIRMWARE_SIZE + IMX_HDMIRX_FIRMWARE_SIZE); 452 IMX_HDMITX_FIRMWARE_SIZE + IMX_HDMIRX_FIRMWARE_SIZE);
453 453
454 sprintf(command, "hdp load 0x%x", IMX_HDMI_FIRMWARE_LOAD_ADDR); 454 sprintf(command, "hdp load 0x%x", IMX_HDMI_FIRMWARE_LOAD_ADDR);
455 run_command(command, 0); 455 run_command(command, 0);
456 456
457 sprintf(command, "hdprx load 0x%x", 457 sprintf(command, "hdprx load 0x%x",
458 IMX_HDMI_FIRMWARE_LOAD_ADDR + IMX_HDMITX_FIRMWARE_SIZE); 458 IMX_HDMI_FIRMWARE_LOAD_ADDR + IMX_HDMITX_FIRMWARE_SIZE);
459 run_command(command, 0); 459 run_command(command, 0);
460 #endif 460 #endif
461 461
462 return 0; 462 return 0;
463 } 463 }
464 464
465 #ifdef CONFIG_FSL_FASTBOOT 465 #ifdef CONFIG_FSL_FASTBOOT
466 #ifdef CONFIG_ANDROID_RECOVERY 466 #ifdef CONFIG_ANDROID_RECOVERY
467 int is_recovery_key_pressing(void) 467 int is_recovery_key_pressing(void)
468 { 468 {
469 return 0; /*TODO*/ 469 return 0; /*TODO*/
470 } 470 }
471 #endif /*CONFIG_ANDROID_RECOVERY*/ 471 #endif /*CONFIG_ANDROID_RECOVERY*/
472 #endif /*CONFIG_FSL_FASTBOOT*/ 472 #endif /*CONFIG_FSL_FASTBOOT*/
473 473
474 #if defined(CONFIG_VIDEO_IMXDPUV1) 474 #if defined(CONFIG_VIDEO_IMXDPUV1)
475 static void enable_lvds(struct display_info_t const *dev) 475 static void enable_lvds(struct display_info_t const *dev)
476 { 476 {
477 display_controller_setup((PS2KHZ(dev->mode.pixclock) * 1000)); 477 display_controller_setup((PS2KHZ(dev->mode.pixclock) * 1000));
478 lvds_soc_setup(dev->bus, (PS2KHZ(dev->mode.pixclock) * 1000)); 478 lvds_soc_setup(dev->bus, (PS2KHZ(dev->mode.pixclock) * 1000));
479 lvds_configure(dev->bus); 479 lvds_configure(dev->bus);
480 lvds2hdmi_setup(6); 480 lvds2hdmi_setup(6);
481 } 481 }
482 482
483 struct display_info_t const displays[] = {{ 483 struct display_info_t const displays[] = {{
484 .bus = 0, /* LVDS0 */ 484 .bus = 0, /* LVDS0 */
485 .addr = 0, /* Unused */ 485 .addr = 0, /* Unused */
486 .pixfmt = IMXDPUV1_PIX_FMT_BGRA32, 486 .pixfmt = IMXDPUV1_PIX_FMT_BGRA32,
487 .detect = NULL, 487 .detect = NULL,
488 .enable = enable_lvds, 488 .enable = enable_lvds,
489 .mode = { 489 .mode = {
490 .name = "IT6263", /* 720P60 */ 490 .name = "IT6263", /* 720P60 */
491 .refresh = 60, 491 .refresh = 60,
492 .xres = 1280, 492 .xres = 1280,
493 .yres = 720, 493 .yres = 720,
494 .pixclock = 13468, /* 74250000 */ 494 .pixclock = 13468, /* 74250000 */
495 .left_margin = 110, 495 .left_margin = 110,
496 .right_margin = 220, 496 .right_margin = 220,
497 .upper_margin = 5, 497 .upper_margin = 5,
498 .lower_margin = 20, 498 .lower_margin = 20,
499 .hsync_len = 40, 499 .hsync_len = 40,
500 .vsync_len = 5, 500 .vsync_len = 5,
501 .sync = FB_SYNC_EXT, 501 .sync = FB_SYNC_EXT,
502 .vmode = FB_VMODE_NONINTERLACED 502 .vmode = FB_VMODE_NONINTERLACED
503 } } }; 503 } } };
504 size_t display_count = ARRAY_SIZE(displays); 504 size_t display_count = ARRAY_SIZE(displays);
505 505
506 #endif /* CONFIG_VIDEO_IMXDPUV1 */ 506 #endif /* CONFIG_VIDEO_IMXDPUV1 */
507 507
include/configs/imx8qm_mek_android.h
Diff comments   View file @ 58b2e43
1 /* 1 /*
2 * Copyright 2017 NXP 2 * Copyright 2017 NXP
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef IMX8QM_MEK_ANDROID_H 7 #ifndef IMX8QM_MEK_ANDROID_H
8 #define IMX8QM_MEK_ANDROID_H 8 #define IMX8QM_MEK_ANDROID_H
9 9
10 #define CONFIG_USBD_HS 10 #define CONFIG_USBD_HS
11 11
12 #define CONFIG_BCB_SUPPORT 12 #define CONFIG_BCB_SUPPORT
13 #define CONFIG_CMD_READ 13 #define CONFIG_CMD_READ
14 #define CONFIG_USB_GADGET_VBUS_DRAW 2 14 #define CONFIG_USB_GADGET_VBUS_DRAW 2
15 15
16 #ifdef CONFIG_IMX_TRUSTY_OS 16 #ifdef CONFIG_IMX_TRUSTY_OS
17 #define NS_ARCH_ARM64 1 17 #define NS_ARCH_ARM64 1
18 #endif 18 #endif
19 19
20 #define CONFIG_ANDROID_AB_SUPPORT 20 #define CONFIG_ANDROID_AB_SUPPORT
21 #define CONFIG_AVB_SUPPORT 21 #define CONFIG_AVB_SUPPORT
22 #define CONFIG_SUPPORT_EMMC_RPMB 22 #define CONFIG_SUPPORT_EMMC_RPMB
23 #ifdef CONFIG_ANDROID_AB_SUPPORT 23 #ifdef CONFIG_ANDROID_AB_SUPPORT
24 #define CONFIG_SYSTEM_RAMDISK_SUPPORT 24 #define CONFIG_SYSTEM_RAMDISK_SUPPORT
25 #endif 25 #endif
26 #define CONFIG_AVB_FUSE_BANK_SIZEW 0 26 #define CONFIG_AVB_FUSE_BANK_SIZEW 0
27 #define CONFIG_AVB_FUSE_BANK_START 0 27 #define CONFIG_AVB_FUSE_BANK_START 0
28 #define CONFIG_AVB_FUSE_BANK_END 0 28 #define CONFIG_AVB_FUSE_BANK_END 0
29 #define CONFIG_FASTBOOT_LOCK 29 #define CONFIG_FASTBOOT_LOCK
30 #define FSL_FASTBOOT_FB_DEV "mmc" 30 #define FSL_FASTBOOT_FB_DEV "mmc"
31 31
32 #define KEYSLOT_HWPARTITION_ID 2 32 #define KEYSLOT_HWPARTITION_ID 2
33 #define KEYSLOT_BLKS 0x3FFF 33 #define KEYSLOT_BLKS 0x3FFF
34 34
35 #define IMX_LOAD_HDMI_FIMRWARE 35 #ifdef CONFIG_IMX_LOAD_HDMI_FIMRWARE
36 #define IMX_HDMI_FIRMWARE_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_64M) 36 #define IMX_HDMI_FIRMWARE_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_64M)
37 #define IMX_HDMITX_FIRMWARE_SIZE 0x20000 37 #define IMX_HDMITX_FIRMWARE_SIZE 0x20000
38 #define IMX_HDMIRX_FIRMWARE_SIZE 0x20000 38 #define IMX_HDMIRX_FIRMWARE_SIZE 0x20000
39 #endif
39 40
40 #ifdef CONFIG_SYS_MALLOC_LEN 41 #ifdef CONFIG_SYS_MALLOC_LEN
41 #undef CONFIG_SYS_MALLOC_LEN 42 #undef CONFIG_SYS_MALLOC_LEN
42 #define CONFIG_SYS_MALLOC_LEN (90 * SZ_1M) 43 #define CONFIG_SYS_MALLOC_LEN (90 * SZ_1M)
43 #endif 44 #endif
44 45
45 46
46 47
47 #define CONFIG_FASTBOOT_USB_DEV 1 48 #define CONFIG_FASTBOOT_USB_DEV 1
48 #define CONFIG_ANDROID_RECOVERY 49 #define CONFIG_ANDROID_RECOVERY
49 50
50 #define CONFIG_CMD_BOOTA 51 #define CONFIG_CMD_BOOTA
51 #define CONFIG_SUPPORT_RAW_INITRD 52 #define CONFIG_SUPPORT_RAW_INITRD
52 #define CONFIG_SERIAL_TAG 53 #define CONFIG_SERIAL_TAG
53 54
54 #undef CONFIG_EXTRA_ENV_SETTINGS 55 #undef CONFIG_EXTRA_ENV_SETTINGS
55 #undef CONFIG_BOOTCOMMAND 56 #undef CONFIG_BOOTCOMMAND
56 57
57 #define CONFIG_EXTRA_ENV_SETTINGS \ 58 #define CONFIG_EXTRA_ENV_SETTINGS \
58 "splashpos=m,m\0" \ 59 "splashpos=m,m\0" \
59 "fdt_high=0xffffffffffffffff\0" \ 60 "fdt_high=0xffffffffffffffff\0" \
60 "initrd_high=0xffffffffffffffff\0" \ 61 "initrd_high=0xffffffffffffffff\0" \
61 "panel=NULL\0" \ 62 "panel=NULL\0" \
62 63
63 #ifdef CONFIG_IMX_TRUSTY_OS 64 #ifdef CONFIG_IMX_TRUSTY_OS
64 #define AVB_RPMB 65 #define AVB_RPMB
65 66
66 #ifdef CONFIG_SPL_BUILD 67 #ifdef CONFIG_SPL_BUILD
67 #undef CONFIG_BLK 68 #undef CONFIG_BLK
68 #define CONFIG_FSL_CAAM_KB 69 #define CONFIG_FSL_CAAM_KB
69 #define CONFIG_SPL_CRYPTO_SUPPORT 70 #define CONFIG_SPL_CRYPTO_SUPPORT
70 #define CONFIG_SYS_FSL_SEC_LE 71 #define CONFIG_SYS_FSL_SEC_LE
71 #endif 72 #endif
72 #endif 73 #endif
73 74
74 #define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED 75 #define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED
75 76
76 #endif /* IMX8QM_MEK_ANDROID_H */ 77 #endif /* IMX8QM_MEK_ANDROID_H */
77 78