Eric Lee / smarc-uboot

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Commit 58c76e63f17f87afdc45ec32a84c5e86fc2b6fdd

Authored by Lukasz Majewski
Committed by Stefano Babic
1 parent 309ce98fcb
Exists in smarc_8mq_lf_v2020.04 and in 10 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

imx: tpc70: Add board_boot_order() to distinguish between eMMC and SD boot 

The TPC70 can boot from SD card (debug/development) and eMMC (production).
The board_boot_order() function provides a run time check for the device
from which one wants to boot (it is selected by GPIO pins setup).

Moreover, a fallback to SD card is provided if the detection is not
possible or working properly.

Signed-off-by: Lukasz Majewski <lukma@denx.de>

Showing 1 changed file with 20 additions and 0 deletions Inline Diff

board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
Diff comments   View file @ 58c76e6
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * K+P iMX6Q KP_IMX6Q_TPC board configuration 3 * K+P iMX6Q KP_IMX6Q_TPC board configuration
4 * 4 *
5 * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de> 5 * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <asm/arch/clock.h> 9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h> 10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux.h> 12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-ddr.h> 13 #include <asm/arch/mx6-ddr.h>
14 #include <asm/arch/mx6-pins.h> 14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/sys_proto.h> 15 #include <asm/arch/sys_proto.h>
16 #include <asm/gpio.h> 16 #include <asm/gpio.h>
17 #include <asm/mach-imx/boot_mode.h> 17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/mach-imx/iomux-v3.h> 18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/mxc_i2c.h> 19 #include <asm/mach-imx/mxc_i2c.h>
20 #include <asm/io.h> 20 #include <asm/io.h>
21 #include <errno.h> 21 #include <errno.h>
22 #include <fuse.h> 22 #include <fuse.h>
23 #include <fsl_esdhc_imx.h> 23 #include <fsl_esdhc_imx.h>
24 #include <i2c.h> 24 #include <i2c.h>
25 #include <mmc.h> 25 #include <mmc.h>
26 #include <spl.h> 26 #include <spl.h>
27 27
28 #define UART_PAD_CTRL \ 28 #define UART_PAD_CTRL \
29 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 29 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
30 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 30 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
31 31
32 #define USDHC_PAD_CTRL \ 32 #define USDHC_PAD_CTRL \
33 (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 33 (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
34 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 34 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
35 35
36 DECLARE_GLOBAL_DATA_PTR; 36 DECLARE_GLOBAL_DATA_PTR;
37 37
38 static void ccgr_init(void) 38 static void ccgr_init(void)
39 { 39 {
40 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 40 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
41 41
42 writel(0x00C03F3F, &ccm->CCGR0); 42 writel(0x00C03F3F, &ccm->CCGR0);
43 writel(0x0030FC03, &ccm->CCGR1); 43 writel(0x0030FC03, &ccm->CCGR1);
44 writel(0x0FFFC000, &ccm->CCGR2); 44 writel(0x0FFFC000, &ccm->CCGR2);
45 writel(0x3FF00000, &ccm->CCGR3); 45 writel(0x3FF00000, &ccm->CCGR3);
46 writel(0x00FFF300, &ccm->CCGR4); 46 writel(0x00FFF300, &ccm->CCGR4);
47 writel(0x0F0000C3, &ccm->CCGR5); 47 writel(0x0F0000C3, &ccm->CCGR5);
48 writel(0x000003FF, &ccm->CCGR6); 48 writel(0x000003FF, &ccm->CCGR6);
49 } 49 }
50 50
51 /* onboard microSD */ 51 /* onboard microSD */
52 static iomux_v3_cfg_t const usdhc2_pads[] = { 52 static iomux_v3_cfg_t const usdhc2_pads[] = {
53 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 53 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
54 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 54 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
55 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 55 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
56 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 56 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
57 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 57 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
58 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 58 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
59 IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), 59 IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
60 }; 60 };
61 61
62 /* eMMC */ 62 /* eMMC */
63 static iomux_v3_cfg_t const usdhc4_pads[] = { 63 static iomux_v3_cfg_t const usdhc4_pads[] = {
64 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 64 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
65 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 65 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
66 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 66 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
67 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 67 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
68 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 68 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
69 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 69 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
70 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 70 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
71 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 71 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
72 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 72 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
73 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 73 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
74 }; 74 };
75 75
76 /* SD */ 76 /* SD */
77 static void setup_iomux_sd(void) 77 static void setup_iomux_sd(void)
78 { 78 {
79 SETUP_IOMUX_PADS(usdhc2_pads); 79 SETUP_IOMUX_PADS(usdhc2_pads);
80 SETUP_IOMUX_PADS(usdhc4_pads); 80 SETUP_IOMUX_PADS(usdhc4_pads);
81 } 81 }
82 82
83 /* UART */ 83 /* UART */
84 static iomux_v3_cfg_t const uart1_pads[] = { 84 static iomux_v3_cfg_t const uart1_pads[] = {
85 IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 85 IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
86 IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 86 IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
87 }; 87 };
88 88
89 static void setup_iomux_uart(void) 89 static void setup_iomux_uart(void)
90 { 90 {
91 SETUP_IOMUX_PADS(uart1_pads); 91 SETUP_IOMUX_PADS(uart1_pads);
92 } 92 }
93 93
94 /* USB */ 94 /* USB */
95 static iomux_v3_cfg_t const usb_pads[] = { 95 static iomux_v3_cfg_t const usb_pads[] = {
96 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), 96 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
97 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), 97 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
98 }; 98 };
99 99
100 static void setup_iomux_usb(void) 100 static void setup_iomux_usb(void)
101 { 101 {
102 SETUP_IOMUX_PADS(usb_pads); 102 SETUP_IOMUX_PADS(usb_pads);
103 } 103 }
104 104
105 /* DDR3 */ 105 /* DDR3 */
106 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { 106 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
107 .dram_sdclk_0 = 0x00000030, 107 .dram_sdclk_0 = 0x00000030,
108 .dram_sdclk_1 = 0x00000030, 108 .dram_sdclk_1 = 0x00000030,
109 .dram_cas = 0x00000030, 109 .dram_cas = 0x00000030,
110 .dram_ras = 0x00000030, 110 .dram_ras = 0x00000030,
111 .dram_reset = 0x00000030, 111 .dram_reset = 0x00000030,
112 .dram_sdcke0 = 0x00003000, 112 .dram_sdcke0 = 0x00003000,
113 .dram_sdcke1 = 0x00003000, 113 .dram_sdcke1 = 0x00003000,
114 .dram_sdba2 = 0x00000000, 114 .dram_sdba2 = 0x00000000,
115 .dram_sdodt0 = 0x00000030, 115 .dram_sdodt0 = 0x00000030,
116 .dram_sdodt1 = 0x00000030, 116 .dram_sdodt1 = 0x00000030,
117 117
118 .dram_sdqs0 = 0x00000018, 118 .dram_sdqs0 = 0x00000018,
119 .dram_sdqs1 = 0x00000018, 119 .dram_sdqs1 = 0x00000018,
120 .dram_sdqs2 = 0x00000018, 120 .dram_sdqs2 = 0x00000018,
121 .dram_sdqs3 = 0x00000018, 121 .dram_sdqs3 = 0x00000018,
122 .dram_sdqs4 = 0x00000018, 122 .dram_sdqs4 = 0x00000018,
123 .dram_sdqs5 = 0x00000018, 123 .dram_sdqs5 = 0x00000018,
124 .dram_sdqs6 = 0x00000018, 124 .dram_sdqs6 = 0x00000018,
125 .dram_sdqs7 = 0x00000018, 125 .dram_sdqs7 = 0x00000018,
126 126
127 .dram_dqm0 = 0x00000018, 127 .dram_dqm0 = 0x00000018,
128 .dram_dqm1 = 0x00000018, 128 .dram_dqm1 = 0x00000018,
129 .dram_dqm2 = 0x00000018, 129 .dram_dqm2 = 0x00000018,
130 .dram_dqm3 = 0x00000018, 130 .dram_dqm3 = 0x00000018,
131 .dram_dqm4 = 0x00000018, 131 .dram_dqm4 = 0x00000018,
132 .dram_dqm5 = 0x00000018, 132 .dram_dqm5 = 0x00000018,
133 .dram_dqm6 = 0x00000018, 133 .dram_dqm6 = 0x00000018,
134 .dram_dqm7 = 0x00000018, 134 .dram_dqm7 = 0x00000018,
135 }; 135 };
136 136
137 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { 137 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
138 .grp_ddr_type = 0x000c0000, 138 .grp_ddr_type = 0x000c0000,
139 .grp_ddrmode_ctl = 0x00020000, 139 .grp_ddrmode_ctl = 0x00020000,
140 .grp_ddrpke = 0x00000000, 140 .grp_ddrpke = 0x00000000,
141 .grp_addds = 0x00000030, 141 .grp_addds = 0x00000030,
142 .grp_ctlds = 0x00000030, 142 .grp_ctlds = 0x00000030,
143 .grp_ddrmode = 0x00020000, 143 .grp_ddrmode = 0x00020000,
144 .grp_b0ds = 0x00000018, 144 .grp_b0ds = 0x00000018,
145 .grp_b1ds = 0x00000018, 145 .grp_b1ds = 0x00000018,
146 .grp_b2ds = 0x00000018, 146 .grp_b2ds = 0x00000018,
147 .grp_b3ds = 0x00000018, 147 .grp_b3ds = 0x00000018,
148 .grp_b4ds = 0x00000018, 148 .grp_b4ds = 0x00000018,
149 .grp_b5ds = 0x00000018, 149 .grp_b5ds = 0x00000018,
150 .grp_b6ds = 0x00000018, 150 .grp_b6ds = 0x00000018,
151 .grp_b7ds = 0x00000018, 151 .grp_b7ds = 0x00000018,
152 }; 152 };
153 153
154 static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = { 154 static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
155 .p0_mpwldectrl0 = 0x001F001F, 155 .p0_mpwldectrl0 = 0x001F001F,
156 .p0_mpwldectrl1 = 0x001F001F, 156 .p0_mpwldectrl1 = 0x001F001F,
157 .p1_mpwldectrl0 = 0x001F001F, 157 .p1_mpwldectrl0 = 0x001F001F,
158 .p1_mpwldectrl1 = 0x001F001F, 158 .p1_mpwldectrl1 = 0x001F001F,
159 .p0_mpdgctrl0 = 0x43270338, 159 .p0_mpdgctrl0 = 0x43270338,
160 .p0_mpdgctrl1 = 0x03200314, 160 .p0_mpdgctrl1 = 0x03200314,
161 .p1_mpdgctrl0 = 0x431A032F, 161 .p1_mpdgctrl0 = 0x431A032F,
162 .p1_mpdgctrl1 = 0x03200263, 162 .p1_mpdgctrl1 = 0x03200263,
163 .p0_mprddlctl = 0x4B434748, 163 .p0_mprddlctl = 0x4B434748,
164 .p1_mprddlctl = 0x4445404C, 164 .p1_mprddlctl = 0x4445404C,
165 .p0_mpwrdlctl = 0x38444542, 165 .p0_mpwrdlctl = 0x38444542,
166 .p1_mpwrdlctl = 0x4935493A, 166 .p1_mpwrdlctl = 0x4935493A,
167 }; 167 };
168 168
169 /* MT41K256M16 (4Gb density) */ 169 /* MT41K256M16 (4Gb density) */
170 static const struct mx6_ddr3_cfg mt41k256m16 = { 170 static const struct mx6_ddr3_cfg mt41k256m16 = {
171 .mem_speed = 1600, 171 .mem_speed = 1600,
172 .density = 4, 172 .density = 4,
173 .width = 16, 173 .width = 16,
174 .banks = 8, 174 .banks = 8,
175 .rowaddr = 15, 175 .rowaddr = 15,
176 .coladdr = 10, 176 .coladdr = 10,
177 .pagesz = 2, 177 .pagesz = 2,
178 .trcd = 1375, 178 .trcd = 1375,
179 .trcmin = 4875, 179 .trcmin = 4875,
180 .trasmin = 3500, 180 .trasmin = 3500,
181 }; 181 };
182 182
183 #ifdef CONFIG_MX6_DDRCAL 183 #ifdef CONFIG_MX6_DDRCAL
184 static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo) 184 static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
185 { 185 {
186 struct mx6_mmdc_calibration calibration = {0}; 186 struct mx6_mmdc_calibration calibration = {0};
187 187
188 mmdc_read_calibration(sysinfo, &calibration); 188 mmdc_read_calibration(sysinfo, &calibration);
189 189
190 debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0); 190 debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
191 debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1); 191 debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
192 debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl); 192 debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
193 debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl); 193 debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
194 debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0); 194 debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
195 debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1); 195 debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
196 debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0); 196 debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
197 debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1); 197 debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
198 debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl); 198 debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
199 debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl); 199 debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
200 debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0); 200 debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
201 debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1); 201 debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
202 } 202 }
203 203
204 static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo) 204 static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
205 { 205 {
206 int ret; 206 int ret;
207 207
208 /* Perform DDR DRAM calibration */ 208 /* Perform DDR DRAM calibration */
209 udelay(100); 209 udelay(100);
210 ret = mmdc_do_write_level_calibration(sysinfo); 210 ret = mmdc_do_write_level_calibration(sysinfo);
211 if (ret) { 211 if (ret) {
212 printf("DDR: Write level calibration error [%d]\n", ret); 212 printf("DDR: Write level calibration error [%d]\n", ret);
213 return; 213 return;
214 } 214 }
215 215
216 ret = mmdc_do_dqs_calibration(sysinfo); 216 ret = mmdc_do_dqs_calibration(sysinfo);
217 if (ret) { 217 if (ret) {
218 printf("DDR: DQS calibration error [%d]\n", ret); 218 printf("DDR: DQS calibration error [%d]\n", ret);
219 return; 219 return;
220 } 220 }
221 221
222 spl_dram_print_cal(sysinfo); 222 spl_dram_print_cal(sysinfo);
223 } 223 }
224 #endif /* CONFIG_MX6_DDRCAL */ 224 #endif /* CONFIG_MX6_DDRCAL */
225 225
226 static void spl_dram_init(void) 226 static void spl_dram_init(void)
227 { 227 {
228 struct mx6_ddr_sysinfo sysinfo = { 228 struct mx6_ddr_sysinfo sysinfo = {
229 /* width of data bus:0=16,1=32,2=64 */ 229 /* width of data bus:0=16,1=32,2=64 */
230 .dsize = 2, 230 .dsize = 2,
231 /* config for full 4GB range so that get_mem_size() works */ 231 /* config for full 4GB range so that get_mem_size() works */
232 .cs_density = 32, /* 32Gb per CS */ 232 .cs_density = 32, /* 32Gb per CS */
233 /* single chip select */ 233 /* single chip select */
234 .ncs = 1, 234 .ncs = 1,
235 .cs1_mirror = 0, 235 .cs1_mirror = 0,
236 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 236 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
237 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ 237 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
238 .walat = 1, /* Write additional latency */ 238 .walat = 1, /* Write additional latency */
239 .ralat = 5, /* Read additional latency */ 239 .ralat = 5, /* Read additional latency */
240 .mif3_mode = 3, /* Command prediction working mode */ 240 .mif3_mode = 3, /* Command prediction working mode */
241 .bi_on = 1, /* Bank interleaving enabled */ 241 .bi_on = 1, /* Bank interleaving enabled */
242 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 242 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
243 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 243 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
244 .pd_fast_exit = 1, /* enable precharge power-down fast exit */ 244 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
245 .ddr_type = DDR_TYPE_DDR3, 245 .ddr_type = DDR_TYPE_DDR3,
246 .refsel = 1, /* Refresh cycles at 32KHz */ 246 .refsel = 1, /* Refresh cycles at 32KHz */
247 .refr = 7, /* 8 refresh commands per refresh cycle */ 247 .refr = 7, /* 8 refresh commands per refresh cycle */
248 }; 248 };
249 249
250 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); 250 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
251 mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16); 251 mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16);
252 252
253 #ifdef CONFIG_MX6_DDRCAL 253 #ifdef CONFIG_MX6_DDRCAL
254 spl_dram_perform_cal(&sysinfo); 254 spl_dram_perform_cal(&sysinfo);
255 #endif 255 #endif
256 } 256 }
257 257
258 struct fsl_esdhc_cfg usdhc_cfg[] = { 258 struct fsl_esdhc_cfg usdhc_cfg[] = {
259 {USDHC2_BASE_ADDR}, 259 {USDHC2_BASE_ADDR},
260 {USDHC4_BASE_ADDR}, 260 {USDHC4_BASE_ADDR},
261 }; 261 };
262 262
263 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) 263 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
264 int board_mmc_getcd(struct mmc *mmc) 264 int board_mmc_getcd(struct mmc *mmc)
265 { 265 {
266 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 266 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
267 int ret = 0; 267 int ret = 0;
268 268
269 switch (cfg->esdhc_base) { 269 switch (cfg->esdhc_base) {
270 case USDHC2_BASE_ADDR: 270 case USDHC2_BASE_ADDR:
271 ret = !gpio_get_value(USDHC2_CD_GPIO); 271 ret = !gpio_get_value(USDHC2_CD_GPIO);
272 break; 272 break;
273 case USDHC4_BASE_ADDR: 273 case USDHC4_BASE_ADDR:
274 ret = 1; /* eMMC/uSDHC4 is always present */ 274 ret = 1; /* eMMC/uSDHC4 is always present */
275 break; 275 break;
276 } 276 }
277 277
278 return ret; 278 return ret;
279 } 279 }
280 280
281 int board_mmc_init(bd_t *bd) 281 int board_mmc_init(bd_t *bd)
282 { 282 {
283 struct src *psrc = (struct src *)SRC_BASE_ADDR; 283 struct src *psrc = (struct src *)SRC_BASE_ADDR;
284 unsigned int reg = readl(&psrc->sbmr1) >> 11; 284 unsigned int reg = readl(&psrc->sbmr1) >> 11;
285 /* 285 /*
286 * Upon reading BOOT_CFG register the following map is done: 286 * Upon reading BOOT_CFG register the following map is done:
287 * Bit 11 and 12 of BOOT_CFG register can determine the current 287 * Bit 11 and 12 of BOOT_CFG register can determine the current
288 * mmc port 288 * mmc port
289 * 0x1 SD1 289 * 0x1 SD1
290 * 0x3 SD4 290 * 0x3 SD4
291 */ 291 */
292 292
293 switch (reg & 0x3) { 293 switch (reg & 0x3) {
294 case 0x1: 294 case 0x1:
295 SETUP_IOMUX_PADS(usdhc2_pads); 295 SETUP_IOMUX_PADS(usdhc2_pads);
296 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; 296 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
297 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 297 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
298 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 298 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
299 break; 299 break;
300 case 0x3: 300 case 0x3:
301 SETUP_IOMUX_PADS(usdhc4_pads); 301 SETUP_IOMUX_PADS(usdhc4_pads);
302 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; 302 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
303 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 303 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
304 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 304 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
305 break; 305 break;
306 } 306 }
307 307
308 return fsl_esdhc_initialize(bd, &usdhc_cfg[0]); 308 return fsl_esdhc_initialize(bd, &usdhc_cfg[0]);
309 } 309 }
310 310
311 void board_boot_order(u32 *spl_boot_list)
312 {
313 u32 boot_device = spl_boot_device();
314 u32 reg = imx6_src_get_boot_mode();
315
316 reg = (reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT;
317
318 debug("%s: boot device: 0x%x (0x4 SD, 0x6 eMMC)\n", __func__, reg);
319 if (boot_device == BOOT_DEVICE_MMC1)
320 if (reg == IMX6_BMODE_MMC || reg == IMX6_BMODE_EMMC)
321 boot_device = BOOT_DEVICE_MMC2;
322
323 spl_boot_list[0] = boot_device;
324 /*
325 * Below boot device is a 'fallback' - it shall always be possible to
326 * boot from SD card
327 */
328 spl_boot_list[1] = BOOT_DEVICE_MMC1;
329 }
330
311 void board_init_f(ulong dummy) 331 void board_init_f(ulong dummy)
312 { 332 {
313 /* setup AIPS and disable watchdog */ 333 /* setup AIPS and disable watchdog */
314 arch_cpu_init(); 334 arch_cpu_init();
315 335
316 ccgr_init(); 336 ccgr_init();
317 gpr_init(); 337 gpr_init();
318 338
319 /* setup GP timer */ 339 /* setup GP timer */
320 timer_init(); 340 timer_init();
321 341
322 setup_iomux_sd(); 342 setup_iomux_sd();
323 setup_iomux_uart(); 343 setup_iomux_uart();
324 setup_iomux_usb(); 344 setup_iomux_usb();
325 345
326 /* UART clocks enabled and gd valid - init serial console */ 346 /* UART clocks enabled and gd valid - init serial console */
327 preloader_console_init(); 347 preloader_console_init();
328 348
329 /* DDR initialization */ 349 /* DDR initialization */
330 spl_dram_init(); 350 spl_dram_init();
331 351
332 /* Clear the BSS. */ 352 /* Clear the BSS. */
333 memset(__bss_start, 0, __bss_end - __bss_start); 353 memset(__bss_start, 0, __bss_end - __bss_start);
334 354
335 /* load/boot image from boot device */ 355 /* load/boot image from boot device */
336 board_init_r(NULL, 0); 356 board_init_r(NULL, 0);
337 } 357 }
338 358