Eric Lee / smarc-uboot

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Commit 59ca4318ab4e1cfd39e6c1343e87eda481226552

Authored by Ye.Li
1 parent 3f66148f3d
Exists in smarc-imx-l5.0.0_1.0.0-ga

MLK-9706 imx: mx6sx19x19arm2: Fix ENET card MAX7322 reset issue 

The MAX7322 will fail to work on 19x19 arm2 revB board. This failure
is caused by the MAX7322 reset pin is not released when calling the
setup_fec function.

The MAX7322 reset pin is same as PHY reset pin. This patch fixes the issue
by moving the PHY reset from setup_iomux_fec1 to setup_fec.

Signed-off-by: Ye.Li <B37916@freescale.com>

Showing 1 changed file with 5 additions and 5 deletions Inline Diff

board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c
Diff comments   View file @ 59ca431
1 /* 1 /*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc. 2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <asm/arch/clock.h> 7 #include <asm/arch/clock.h>
8 #include <asm/arch/iomux.h> 8 #include <asm/arch/iomux.h>
9 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/mx6-pins.h> 10 #include <asm/arch/mx6-pins.h>
11 #include <asm/arch/sys_proto.h> 11 #include <asm/arch/sys_proto.h>
12 #include <asm/gpio.h> 12 #include <asm/gpio.h>
13 #include <asm/imx-common/iomux-v3.h> 13 #include <asm/imx-common/iomux-v3.h>
14 #include <asm/imx-common/boot_mode.h> 14 #include <asm/imx-common/boot_mode.h>
15 #include <asm/io.h> 15 #include <asm/io.h>
16 #include <linux/sizes.h> 16 #include <linux/sizes.h>
17 #include <common.h> 17 #include <common.h>
18 #include <fsl_esdhc.h> 18 #include <fsl_esdhc.h>
19 #include <mmc.h> 19 #include <mmc.h>
20 #include <miiphy.h> 20 #include <miiphy.h>
21 #include <netdev.h> 21 #include <netdev.h>
22 #ifdef CONFIG_SYS_I2C_MXC 22 #ifdef CONFIG_SYS_I2C_MXC
23 #include <i2c.h> 23 #include <i2c.h>
24 #include <asm/imx-common/mxc_i2c.h> 24 #include <asm/imx-common/mxc_i2c.h>
25 #endif 25 #endif
26 #include <asm/arch/crm_regs.h> 26 #include <asm/arch/crm_regs.h>
27 27
28 #ifdef CONFIG_VIDEO_MXS 28 #ifdef CONFIG_VIDEO_MXS
29 #include <linux/fb.h> 29 #include <linux/fb.h>
30 #include <mxsfb.h> 30 #include <mxsfb.h>
31 #endif 31 #endif
32 32
33 DECLARE_GLOBAL_DATA_PTR; 33 DECLARE_GLOBAL_DATA_PTR;
34 34
35 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 35 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
36 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 36 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
37 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 37 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38 38
39 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 39 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
40 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 40 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
41 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 41 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42 42
43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
44 PAD_CTL_SPEED_MED | \ 44 PAD_CTL_SPEED_MED | \
45 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 45 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
46 46
47 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 47 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
48 PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST) 48 PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
49 49
50 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 50 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
51 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 51 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
52 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 52 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
53 PAD_CTL_ODE) 53 PAD_CTL_ODE)
54 54
55 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 55 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
56 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) 56 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
57 57
58 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) 58 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
59 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ 59 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
60 PAD_CTL_SRE_FAST) 60 PAD_CTL_SRE_FAST)
61 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) 61 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
62 62
63 #define SPI_PAD_CTRL (PAD_CTL_HYS | \ 63 #define SPI_PAD_CTRL (PAD_CTL_HYS | \
64 PAD_CTL_SPEED_MED | \ 64 PAD_CTL_SPEED_MED | \
65 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 65 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
66 66
67 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 67 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
68 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 68 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
69 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 69 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
70 70
71 #define WEIM_NOR_PAD_CTRL2 (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ 71 #define WEIM_NOR_PAD_CTRL2 (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
72 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 72 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
73 PAD_CTL_DSE_40ohm) 73 PAD_CTL_DSE_40ohm)
74 74
75 75
76 #ifdef CONFIG_SYS_I2C_MXC 76 #ifdef CONFIG_SYS_I2C_MXC
77 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 77 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
78 /* I2C1 for PMIC */ 78 /* I2C1 for PMIC */
79 struct i2c_pads_info i2c_pad_info1 = { 79 struct i2c_pads_info i2c_pad_info1 = {
80 .scl = { 80 .scl = {
81 .i2c_mode = MX6SX_PAD_GPIO1_IO00__I2C1_SCL | PC, 81 .i2c_mode = MX6SX_PAD_GPIO1_IO00__I2C1_SCL | PC,
82 .gpio_mode = MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, 82 .gpio_mode = MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
83 .gp = IMX_GPIO_NR(1, 0), 83 .gp = IMX_GPIO_NR(1, 0),
84 }, 84 },
85 .sda = { 85 .sda = {
86 .i2c_mode = MX6SX_PAD_GPIO1_IO01__I2C1_SDA | PC, 86 .i2c_mode = MX6SX_PAD_GPIO1_IO01__I2C1_SDA | PC,
87 .gpio_mode = MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, 87 .gpio_mode = MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
88 .gp = IMX_GPIO_NR(1, 1), 88 .gp = IMX_GPIO_NR(1, 1),
89 }, 89 },
90 }; 90 };
91 91
92 /* I2C2 */ 92 /* I2C2 */
93 struct i2c_pads_info i2c_pad_info2 = { 93 struct i2c_pads_info i2c_pad_info2 = {
94 .scl = { 94 .scl = {
95 .i2c_mode = MX6SX_PAD_GPIO1_IO02__I2C2_SCL | PC, 95 .i2c_mode = MX6SX_PAD_GPIO1_IO02__I2C2_SCL | PC,
96 .gpio_mode = MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 | PC, 96 .gpio_mode = MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
97 .gp = IMX_GPIO_NR(1, 2), 97 .gp = IMX_GPIO_NR(1, 2),
98 }, 98 },
99 .sda = { 99 .sda = {
100 .i2c_mode = MX6SX_PAD_GPIO1_IO03__I2C2_SDA | PC, 100 .i2c_mode = MX6SX_PAD_GPIO1_IO03__I2C2_SDA | PC,
101 .gpio_mode = MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 | PC, 101 .gpio_mode = MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
102 .gp = IMX_GPIO_NR(1, 3), 102 .gp = IMX_GPIO_NR(1, 3),
103 }, 103 },
104 }; 104 };
105 #endif 105 #endif
106 106
107 int dram_init(void) 107 int dram_init(void)
108 { 108 {
109 gd->ram_size = PHYS_SDRAM_SIZE; 109 gd->ram_size = PHYS_SDRAM_SIZE;
110 110
111 return 0; 111 return 0;
112 } 112 }
113 113
114 static iomux_v3_cfg_t const uart1_pads[] = { 114 static iomux_v3_cfg_t const uart1_pads[] = {
115 MX6SX_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 115 MX6SX_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
116 MX6SX_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 116 MX6SX_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
117 }; 117 };
118 118
119 static iomux_v3_cfg_t const usdhc1_pads[] = { 119 static iomux_v3_cfg_t const usdhc1_pads[] = {
120 MX6SX_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 120 MX6SX_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 MX6SX_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 121 MX6SX_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 122 MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 123 MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124 MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 124 MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 125 MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 }; 126 };
127 127
128 #ifdef CONFIG_VIDEO_MXS 128 #ifdef CONFIG_VIDEO_MXS
129 static iomux_v3_cfg_t const lvds_ctrl_pads[] = { 129 static iomux_v3_cfg_t const lvds_ctrl_pads[] = {
130 /* CABC enable */ 130 /* CABC enable */
131 MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), 131 MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
132 132
133 /* Use GPIO for Brightness adjustment, duty cycle = period */ 133 /* Use GPIO for Brightness adjustment, duty cycle = period */
134 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 | MUX_PAD_CTRL(NO_PAD_CTRL), 134 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
135 }; 135 };
136 136
137 static iomux_v3_cfg_t const lcd_pads[] = { 137 static iomux_v3_cfg_t const lcd_pads[] = {
138 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 138 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
139 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 139 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
140 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 140 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
141 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 141 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
142 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL), 142 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
143 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL), 143 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
144 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL), 144 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
145 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL), 145 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
146 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 146 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
147 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL), 147 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
148 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL), 148 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
149 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL), 149 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
150 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL), 150 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
151 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL), 151 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
152 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 152 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
153 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 153 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
154 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 154 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
155 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 155 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
156 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 156 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
157 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 157 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
158 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 158 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
159 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 159 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
160 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL), 160 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
161 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL), 161 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
162 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL), 162 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
163 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL), 163 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
164 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL), 164 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
165 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL), 165 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
166 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL), 166 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
167 167
168 /* Use GPIO for Brightness adjustment, duty cycle = period */ 168 /* Use GPIO for Brightness adjustment, duty cycle = period */
169 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 | MUX_PAD_CTRL(NO_PAD_CTRL), 169 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
170 }; 170 };
171 171
172 172
173 struct lcd_panel_info_t { 173 struct lcd_panel_info_t {
174 unsigned int lcdif_base_addr; 174 unsigned int lcdif_base_addr;
175 int depth; 175 int depth;
176 void (*enable)(struct lcd_panel_info_t const *dev); 176 void (*enable)(struct lcd_panel_info_t const *dev);
177 struct fb_videomode mode; 177 struct fb_videomode mode;
178 }; 178 };
179 179
180 void do_enable_lvds(struct lcd_panel_info_t const *dev) 180 void do_enable_lvds(struct lcd_panel_info_t const *dev)
181 { 181 {
182 enable_lcdif_clock(dev->lcdif_base_addr); 182 enable_lcdif_clock(dev->lcdif_base_addr);
183 enable_lvds(dev->lcdif_base_addr); 183 enable_lvds(dev->lcdif_base_addr);
184 184
185 imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads, 185 imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads,
186 ARRAY_SIZE(lvds_ctrl_pads)); 186 ARRAY_SIZE(lvds_ctrl_pads));
187 187
188 /* Enable CABC */ 188 /* Enable CABC */
189 gpio_direction_output(IMX_GPIO_NR(2, 16) , 1); 189 gpio_direction_output(IMX_GPIO_NR(2, 16) , 1);
190 190
191 /* Set Brightness to high */ 191 /* Set Brightness to high */
192 gpio_direction_output(IMX_GPIO_NR(1, 12) , 1); 192 gpio_direction_output(IMX_GPIO_NR(1, 12) , 1);
193 } 193 }
194 194
195 void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev) 195 void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev)
196 { 196 {
197 enable_lcdif_clock(dev->lcdif_base_addr); 197 enable_lcdif_clock(dev->lcdif_base_addr);
198 198
199 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 199 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
200 200
201 /* Power up the LCD */ 201 /* Power up the LCD */
202 gpio_direction_output(IMX_GPIO_NR(3, 27) , 1); 202 gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
203 203
204 /* Set Brightness to high */ 204 /* Set Brightness to high */
205 gpio_direction_output(IMX_GPIO_NR(1, 12) , 1); 205 gpio_direction_output(IMX_GPIO_NR(1, 12) , 1);
206 } 206 }
207 207
208 static struct lcd_panel_info_t const displays[] = {{ 208 static struct lcd_panel_info_t const displays[] = {{
209 .lcdif_base_addr = LCDIF2_BASE_ADDR, 209 .lcdif_base_addr = LCDIF2_BASE_ADDR,
210 .depth = 18, 210 .depth = 18,
211 .enable = do_enable_lvds, 211 .enable = do_enable_lvds,
212 .mode = { 212 .mode = {
213 .name = "Hannstar-XGA", 213 .name = "Hannstar-XGA",
214 .xres = 1024, 214 .xres = 1024,
215 .yres = 768, 215 .yres = 768,
216 .pixclock = 15385, 216 .pixclock = 15385,
217 .left_margin = 220, 217 .left_margin = 220,
218 .right_margin = 40, 218 .right_margin = 40,
219 .upper_margin = 21, 219 .upper_margin = 21,
220 .lower_margin = 7, 220 .lower_margin = 7,
221 .hsync_len = 60, 221 .hsync_len = 60,
222 .vsync_len = 10, 222 .vsync_len = 10,
223 .sync = 0, 223 .sync = 0,
224 .vmode = FB_VMODE_NONINTERLACED 224 .vmode = FB_VMODE_NONINTERLACED
225 } }, { 225 } }, {
226 .lcdif_base_addr = LCDIF1_BASE_ADDR, 226 .lcdif_base_addr = LCDIF1_BASE_ADDR,
227 .depth = 24, 227 .depth = 24,
228 .enable = do_enable_parallel_lcd, 228 .enable = do_enable_parallel_lcd,
229 .mode = { 229 .mode = {
230 .name = "MCIMX28LCD", 230 .name = "MCIMX28LCD",
231 .xres = 800, 231 .xres = 800,
232 .yres = 480, 232 .yres = 480,
233 .pixclock = 29850, 233 .pixclock = 29850,
234 .left_margin = 89, 234 .left_margin = 89,
235 .right_margin = 164, 235 .right_margin = 164,
236 .upper_margin = 23, 236 .upper_margin = 23,
237 .lower_margin = 10, 237 .lower_margin = 10,
238 .hsync_len = 10, 238 .hsync_len = 10,
239 .vsync_len = 10, 239 .vsync_len = 10,
240 .sync = 0, 240 .sync = 0,
241 .vmode = FB_VMODE_NONINTERLACED 241 .vmode = FB_VMODE_NONINTERLACED
242 } } }; 242 } } };
243 243
244 int board_video_skip(void) 244 int board_video_skip(void)
245 { 245 {
246 int i; 246 int i;
247 int ret; 247 int ret;
248 char const *panel = getenv("panel"); 248 char const *panel = getenv("panel");
249 if (!panel) { 249 if (!panel) {
250 panel = displays[0].mode.name; 250 panel = displays[0].mode.name;
251 printf("No panel detected: default to %s\n", panel); 251 printf("No panel detected: default to %s\n", panel);
252 i = 0; 252 i = 0;
253 } else { 253 } else {
254 for (i = 0; i < ARRAY_SIZE(displays); i++) { 254 for (i = 0; i < ARRAY_SIZE(displays); i++) {
255 if (!strcmp(panel, displays[i].mode.name)) 255 if (!strcmp(panel, displays[i].mode.name))
256 break; 256 break;
257 } 257 }
258 } 258 }
259 if (i < ARRAY_SIZE(displays)) { 259 if (i < ARRAY_SIZE(displays)) {
260 ret = mxs_lcd_panel_setup(displays[i].mode, displays[i].depth, 260 ret = mxs_lcd_panel_setup(displays[i].mode, displays[i].depth,
261 displays[i].lcdif_base_addr); 261 displays[i].lcdif_base_addr);
262 if (!ret) { 262 if (!ret) {
263 if (displays[i].enable) 263 if (displays[i].enable)
264 displays[i].enable(displays+i); 264 displays[i].enable(displays+i);
265 printf("Display: %s (%ux%u)\n", 265 printf("Display: %s (%ux%u)\n",
266 displays[i].mode.name, 266 displays[i].mode.name,
267 displays[i].mode.xres, 267 displays[i].mode.xres,
268 displays[i].mode.yres); 268 displays[i].mode.yres);
269 } else 269 } else
270 printf("LCD %s cannot be configured: %d\n", 270 printf("LCD %s cannot be configured: %d\n",
271 displays[i].mode.name, ret); 271 displays[i].mode.name, ret);
272 } else { 272 } else {
273 printf("unsupported panel %s\n", panel); 273 printf("unsupported panel %s\n", panel);
274 return -EINVAL; 274 return -EINVAL;
275 } 275 }
276 276
277 return 0; 277 return 0;
278 } 278 }
279 #endif 279 #endif
280 280
281 #ifdef CONFIG_FEC_MXC 281 #ifdef CONFIG_FEC_MXC
282 static iomux_v3_cfg_t const fec1_pads[] = { 282 static iomux_v3_cfg_t const fec1_pads[] = {
283 MX6SX_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 283 MX6SX_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
284 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 284 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
285 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 285 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
286 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 286 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
287 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 287 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
288 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 288 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
289 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 289 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
290 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 290 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
291 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 291 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
292 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 292 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
293 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 293 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
294 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 294 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
295 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 295 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
296 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 296 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
297 MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 297 MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
298 298
299 /* AR8031 PHY Reset. For arm2 board, silder the resistance */ 299 /* AR8031 PHY Reset. For arm2 board, silder the resistance */
300 MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL), 300 MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
301 }; 301 };
302 302
303 static void setup_iomux_fec1(void) 303 static void setup_iomux_fec1(void)
304 { 304 {
305 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 305 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
306
307 /* Reset AR8031 PHY */
308 gpio_direction_output(IMX_GPIO_NR(6, 18) , 0);
309 udelay(500);
310 gpio_set_value(IMX_GPIO_NR(6, 18), 1);
311 } 306 }
312 #endif 307 #endif
313 308
314 static void setup_iomux_uart(void) 309 static void setup_iomux_uart(void)
315 { 310 {
316 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 311 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
317 } 312 }
318 313
319 #ifdef CONFIG_QSPI 314 #ifdef CONFIG_QSPI
320 315
321 #define QSPI_PAD_CTRL1 \ 316 #define QSPI_PAD_CTRL1 \
322 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ 317 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
323 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_34ohm) 318 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_34ohm)
324 319
325 #define QSPI_PAD_CTRL2 (QSPI_PAD_CTRL1 | PAD_CTL_DSE_34ohm) 320 #define QSPI_PAD_CTRL2 (QSPI_PAD_CTRL1 | PAD_CTL_DSE_34ohm)
326 321
327 static iomux_v3_cfg_t const quadspi_pads[] = { 322 static iomux_v3_cfg_t const quadspi_pads[] = {
328 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 323 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
329 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 324 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
330 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 325 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
331 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 326 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
332 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 327 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
333 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 328 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
334 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 329 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
335 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 330 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
336 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 331 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
337 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 332 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
338 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 333 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
339 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 334 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
340 335
341 }; 336 };
342 337
343 int board_qspi_init(void) 338 int board_qspi_init(void)
344 { 339 {
345 /* Set the iomux */ 340 /* Set the iomux */
346 imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); 341 imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
347 342
348 /* Set the clock */ 343 /* Set the clock */
349 enable_qspi_clk(1); 344 enable_qspi_clk(1);
350 345
351 return 0; 346 return 0;
352 } 347 }
353 #endif 348 #endif
354 349
355 #ifdef CONFIG_FSL_ESDHC 350 #ifdef CONFIG_FSL_ESDHC
356 static struct fsl_esdhc_cfg usdhc_cfg[1] = { 351 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
357 {USDHC1_BASE_ADDR, 0, 4}, 352 {USDHC1_BASE_ADDR, 0, 4},
358 }; 353 };
359 354
360 int mmc_get_env_devno(void) 355 int mmc_get_env_devno(void)
361 { 356 {
362 u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); 357 u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
363 u32 dev_no; 358 u32 dev_no;
364 u32 bootsel; 359 u32 bootsel;
365 360
366 bootsel = (soc_sbmr & 0x000000FF) >> 6 ; 361 bootsel = (soc_sbmr & 0x000000FF) >> 6 ;
367 362
368 /* If not boot from sd/mmc, use default value */ 363 /* If not boot from sd/mmc, use default value */
369 if (bootsel != 1) 364 if (bootsel != 1)
370 return CONFIG_SYS_MMC_ENV_DEV; 365 return CONFIG_SYS_MMC_ENV_DEV;
371 366
372 /* BOOT_CFG2[3] and BOOT_CFG2[4] */ 367 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
373 dev_no = (soc_sbmr & 0x00001800) >> 11; 368 dev_no = (soc_sbmr & 0x00001800) >> 11;
374 369
375 return dev_no; 370 return dev_no;
376 } 371 }
377 372
378 int mmc_map_to_kernel_blk(int dev_no) 373 int mmc_map_to_kernel_blk(int dev_no)
379 { 374 {
380 return dev_no; 375 return dev_no;
381 } 376 }
382 377
383 int board_mmc_getcd(struct mmc *mmc) 378 int board_mmc_getcd(struct mmc *mmc)
384 { 379 {
385 return 1; /* Assume boot SD always present */ 380 return 1; /* Assume boot SD always present */
386 } 381 }
387 int board_mmc_init(bd_t *bis) 382 int board_mmc_init(bd_t *bis)
388 { 383 {
389 /* 384 /*
390 * According to the board_mmc_init() the following map is done: 385 * According to the board_mmc_init() the following map is done:
391 * (U-boot device node) (Physical Port) 386 * (U-boot device node) (Physical Port)
392 * mmc0 USDHC1 (SDA) 387 * mmc0 USDHC1 (SDA)
393 */ 388 */
394 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 389 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
395 390
396 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 391 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
397 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 392 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
398 } 393 }
399 394
400 int check_mmc_autodetect(void) 395 int check_mmc_autodetect(void)
401 { 396 {
402 char *autodetect_str = getenv("mmcautodetect"); 397 char *autodetect_str = getenv("mmcautodetect");
403 398
404 if ((autodetect_str != NULL) && 399 if ((autodetect_str != NULL) &&
405 (strcmp(autodetect_str, "yes") == 0)) { 400 (strcmp(autodetect_str, "yes") == 0)) {
406 return 1; 401 return 1;
407 } 402 }
408 403
409 return 0; 404 return 0;
410 } 405 }
411 406
412 void board_late_mmc_init(void) 407 void board_late_mmc_init(void)
413 { 408 {
414 char cmd[32]; 409 char cmd[32];
415 char mmcblk[32]; 410 char mmcblk[32];
416 u32 dev_no = mmc_get_env_devno(); 411 u32 dev_no = mmc_get_env_devno();
417 412
418 if (!check_mmc_autodetect()) 413 if (!check_mmc_autodetect())
419 return; 414 return;
420 415
421 setenv_ulong("mmcdev", dev_no); 416 setenv_ulong("mmcdev", dev_no);
422 417
423 /* Set mmcblk env */ 418 /* Set mmcblk env */
424 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", 419 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
425 mmc_map_to_kernel_blk(dev_no)); 420 mmc_map_to_kernel_blk(dev_no));
426 setenv("mmcroot", mmcblk); 421 setenv("mmcroot", mmcblk);
427 422
428 sprintf(cmd, "mmc dev %d", dev_no); 423 sprintf(cmd, "mmc dev %d", dev_no);
429 run_command(cmd, 0); 424 run_command(cmd, 0);
430 } 425 }
431 426
432 #endif 427 #endif
433 428
434 #ifdef CONFIG_SYS_USE_SPINOR 429 #ifdef CONFIG_SYS_USE_SPINOR
435 iomux_v3_cfg_t const ecspi4_pads[] = { 430 iomux_v3_cfg_t const ecspi4_pads[] = {
436 MX6SX_PAD_SD2_CLK__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 431 MX6SX_PAD_SD2_CLK__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
437 MX6SX_PAD_SD2_DATA3__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 432 MX6SX_PAD_SD2_DATA3__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
438 MX6SX_PAD_SD2_CMD__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 433 MX6SX_PAD_SD2_CMD__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
439 MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), 434 MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
440 }; 435 };
441 436
442 void setup_spinor(void) 437 void setup_spinor(void)
443 { 438 {
444 imx_iomux_v3_setup_multiple_pads(ecspi4_pads, 439 imx_iomux_v3_setup_multiple_pads(ecspi4_pads,
445 ARRAY_SIZE(ecspi4_pads)); 440 ARRAY_SIZE(ecspi4_pads));
446 gpio_direction_output(IMX_GPIO_NR(6, 10), 0); 441 gpio_direction_output(IMX_GPIO_NR(6, 10), 0);
447 } 442 }
448 #endif 443 #endif
449 444
450 #ifdef CONFIG_SYS_USE_EIMNOR 445 #ifdef CONFIG_SYS_USE_EIMNOR
451 iomux_v3_cfg_t eimnor_pads[] = { 446 iomux_v3_cfg_t eimnor_pads[] = {
452 MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), 447 MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
453 MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), 448 MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
454 MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), 449 MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
455 MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), 450 MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
456 MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), 451 MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
457 MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), 452 MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
458 MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), 453 MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
459 MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), 454 MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
460 MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), 455 MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
461 MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), 456 MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
462 MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), 457 MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
463 MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), 458 MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
464 MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), 459 MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
465 MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), 460 MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
466 MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), 461 MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
467 MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), 462 MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
468 463
469 MX6SX_PAD_NAND_DATA00__WEIM_AD_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 464 MX6SX_PAD_NAND_DATA00__WEIM_AD_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
470 MX6SX_PAD_NAND_DATA01__WEIM_AD_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 465 MX6SX_PAD_NAND_DATA01__WEIM_AD_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
471 MX6SX_PAD_NAND_DATA02__WEIM_AD_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 466 MX6SX_PAD_NAND_DATA02__WEIM_AD_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
472 MX6SX_PAD_NAND_DATA03__WEIM_AD_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 467 MX6SX_PAD_NAND_DATA03__WEIM_AD_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
473 MX6SX_PAD_NAND_DATA04__WEIM_AD_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 468 MX6SX_PAD_NAND_DATA04__WEIM_AD_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
474 MX6SX_PAD_NAND_DATA05__WEIM_AD_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 469 MX6SX_PAD_NAND_DATA05__WEIM_AD_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
475 MX6SX_PAD_NAND_DATA06__WEIM_AD_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 470 MX6SX_PAD_NAND_DATA06__WEIM_AD_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
476 MX6SX_PAD_NAND_DATA07__WEIM_AD_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 471 MX6SX_PAD_NAND_DATA07__WEIM_AD_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
477 MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 472 MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
478 MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 473 MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
479 MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 474 MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
480 MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) , 475 MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
481 MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 476 MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
482 MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 477 MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
483 MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 478 MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
484 MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 479 MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
485 MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 480 MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
486 MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 481 MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
487 MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 482 MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
488 MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 483 MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
489 MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 484 MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
490 MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 485 MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
491 MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 486 MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
492 MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 487 MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
493 MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 488 MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
494 MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 489 MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
495 MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 490 MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
496 491
497 MX6SX_PAD_NAND_CE1_B__WEIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 492 MX6SX_PAD_NAND_CE1_B__WEIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
498 MX6SX_PAD_NAND_RE_B__WEIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 493 MX6SX_PAD_NAND_RE_B__WEIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
499 MX6SX_PAD_NAND_WE_B__WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL), 494 MX6SX_PAD_NAND_WE_B__WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL),
500 495
501 MX6SX_PAD_NAND_ALE__WEIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 496 MX6SX_PAD_NAND_ALE__WEIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
502 }; 497 };
503 static void eimnor_cs_setup(void) 498 static void eimnor_cs_setup(void)
504 { 499 {
505 writel(0x00000120, WEIM_BASE_ADDR + 0x090); 500 writel(0x00000120, WEIM_BASE_ADDR + 0x090);
506 writel(0x00010181, WEIM_BASE_ADDR + 0x000); 501 writel(0x00010181, WEIM_BASE_ADDR + 0x000);
507 writel(0x00000001, WEIM_BASE_ADDR + 0x004); 502 writel(0x00000001, WEIM_BASE_ADDR + 0x004);
508 writel(0x0a020000, WEIM_BASE_ADDR + 0x008); 503 writel(0x0a020000, WEIM_BASE_ADDR + 0x008);
509 writel(0x0000c000, WEIM_BASE_ADDR + 0x00c); 504 writel(0x0000c000, WEIM_BASE_ADDR + 0x00c);
510 writel(0x0804a240, WEIM_BASE_ADDR + 0x010); 505 writel(0x0804a240, WEIM_BASE_ADDR + 0x010);
511 } 506 }
512 507
513 static void setup_eimnor(void) 508 static void setup_eimnor(void)
514 { 509 {
515 imx_iomux_v3_setup_multiple_pads(eimnor_pads, 510 imx_iomux_v3_setup_multiple_pads(eimnor_pads,
516 ARRAY_SIZE(eimnor_pads)); 511 ARRAY_SIZE(eimnor_pads));
517 512
518 eimnor_cs_setup(); 513 eimnor_cs_setup();
519 } 514 }
520 #endif 515 #endif
521 516
522 517
523 #ifdef CONFIG_SYS_USE_NAND 518 #ifdef CONFIG_SYS_USE_NAND
524 iomux_v3_cfg_t gpmi_pads[] = { 519 iomux_v3_cfg_t gpmi_pads[] = {
525 MX6SX_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 520 MX6SX_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
526 MX6SX_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 521 MX6SX_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
527 MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 522 MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
528 MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0), 523 MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
529 MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 524 MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
530 MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 525 MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
531 MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 526 MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
532 MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 527 MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
533 MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 528 MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
534 MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 529 MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
535 MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 530 MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
536 MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 531 MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
537 MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 532 MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
538 MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 533 MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
539 MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 534 MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
540 }; 535 };
541 536
542 static void setup_gpmi_nand(void) 537 static void setup_gpmi_nand(void)
543 { 538 {
544 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 539 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
545 540
546 /* config gpmi nand iomux */ 541 /* config gpmi nand iomux */
547 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); 542 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
548 543
549 /* config gpmi and bch clock to 100 MHz */ 544 /* config gpmi and bch clock to 100 MHz */
550 clrsetbits_le32(&mxc_ccm->cs2cdr, 545 clrsetbits_le32(&mxc_ccm->cs2cdr,
551 MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | 546 MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
552 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | 547 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
553 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK, 548 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
554 MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) | 549 MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
555 MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) | 550 MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
556 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)); 551 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3));
557 552
558 /* enable gpmi and bch clock gating */ 553 /* enable gpmi and bch clock gating */
559 setbits_le32(&mxc_ccm->CCGR4, 554 setbits_le32(&mxc_ccm->CCGR4,
560 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 555 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
561 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 556 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
562 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 557 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
563 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 558 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
564 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); 559 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
565 560
566 /* enable apbh clock gating */ 561 /* enable apbh clock gating */
567 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 562 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
568 } 563 }
569 #endif 564 #endif
570 565
571 #ifdef CONFIG_FEC_MXC 566 #ifdef CONFIG_FEC_MXC
572 int board_eth_init(bd_t *bis) 567 int board_eth_init(bd_t *bis)
573 { 568 {
574 int ret; 569 int ret;
575 570
576 setup_iomux_fec1(); 571 setup_iomux_fec1();
577 572
578 ret = fecmxc_initialize_multi(bis, 0, 573 ret = fecmxc_initialize_multi(bis, 0,
579 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 574 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
580 if (ret) 575 if (ret)
581 printf("FEC1 MXC: %s:failed\n", __func__); 576 printf("FEC1 MXC: %s:failed\n", __func__);
582 577
583 return 0; 578 return 0;
584 } 579 }
585 580
586 static int setup_fec(void) 581 static int setup_fec(void)
587 { 582 {
588 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 583 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
589 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; 584 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
590 int ret; 585 int ret;
591 unsigned char value = 1; 586 unsigned char value = 1;
592 587
593 /* clear gpr1[13], gpr1[17] to select anatop clock */ 588 /* clear gpr1[13], gpr1[17] to select anatop clock */
594 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); 589 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
595 590
596 ret = enable_fec_anatop_clock(0, ENET_125MHz); 591 ret = enable_fec_anatop_clock(0, ENET_125MHz);
597 if (ret) 592 if (ret)
598 return ret; 593 return ret;
599 594
600 enable_enet_clock(); 595 enable_enet_clock();
596
597 /* Reset AR8031 PHY */
598 gpio_direction_output(IMX_GPIO_NR(6, 18) , 0);
599 udelay(500);
600 gpio_set_value(IMX_GPIO_NR(6, 18), 1);
601 601
602 #ifdef CONFIG_FEC_ENABLE_MAX7322 602 #ifdef CONFIG_FEC_ENABLE_MAX7322
603 /* This is needed to drive the pads to 1.8V instead of 1.5V */ 603 /* This is needed to drive the pads to 1.8V instead of 1.5V */
604 i2c_set_bus_num(CONFIG_MAX7322_I2C_BUS); 604 i2c_set_bus_num(CONFIG_MAX7322_I2C_BUS);
605 605
606 if (!i2c_probe(CONFIG_MAX7322_I2C_ADDR)) { 606 if (!i2c_probe(CONFIG_MAX7322_I2C_ADDR)) {
607 /* Write 0x1 to enable O0 output, this device has no addr */ 607 /* Write 0x1 to enable O0 output, this device has no addr */
608 /* hence addr length is 0 */ 608 /* hence addr length is 0 */
609 value = 0x1; 609 value = 0x1;
610 if (i2c_write(CONFIG_MAX7322_I2C_ADDR, 0, 0, &value, 1)) 610 if (i2c_write(CONFIG_MAX7322_I2C_ADDR, 0, 0, &value, 1))
611 printf("MAX7322 write failed\n"); 611 printf("MAX7322 write failed\n");
612 } else { 612 } else {
613 printf("MAX7322 Not found\n"); 613 printf("MAX7322 Not found\n");
614 } 614 }
615 #endif 615 #endif
616 616
617 return 0; 617 return 0;
618 } 618 }
619 619
620 int board_phy_config(struct phy_device *phydev) 620 int board_phy_config(struct phy_device *phydev)
621 { 621 {
622 #ifdef CONFIG_FEC_ENABLE_MAX7322 622 #ifdef CONFIG_FEC_ENABLE_MAX7322
623 /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on 623 /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
624 Phy control debug reg 0 */ 624 Phy control debug reg 0 */
625 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); 625 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
626 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); 626 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
627 #endif 627 #endif
628 628
629 /* rgmii tx clock delay enable */ 629 /* rgmii tx clock delay enable */
630 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); 630 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
631 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 631 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
632 632
633 if (phydev->drv->config) 633 if (phydev->drv->config)
634 phydev->drv->config(phydev); 634 phydev->drv->config(phydev);
635 635
636 return 0; 636 return 0;
637 } 637 }
638 #endif 638 #endif
639 639
640 #ifdef CONFIG_PFUZE100_PMIC_I2C 640 #ifdef CONFIG_PFUZE100_PMIC_I2C
641 #define PFUZE100_DEVICEID 0x0 641 #define PFUZE100_DEVICEID 0x0
642 #define PFUZE100_REVID 0x3 642 #define PFUZE100_REVID 0x3
643 #define PFUZE100_FABID 0x4 643 #define PFUZE100_FABID 0x4
644 644
645 #define PFUZE100_SW1ABVOL 0x20 645 #define PFUZE100_SW1ABVOL 0x20
646 #define PFUZE100_SW1ABSTBY 0x21 646 #define PFUZE100_SW1ABSTBY 0x21
647 #define PFUZE100_SW1ABCONF 0x24 647 #define PFUZE100_SW1ABCONF 0x24
648 #define PFUZE100_SW1CVOL 0x2e 648 #define PFUZE100_SW1CVOL 0x2e
649 #define PFUZE100_SW1CSTBY 0x2f 649 #define PFUZE100_SW1CSTBY 0x2f
650 #define PFUZE100_SW1CCONF 0x32 650 #define PFUZE100_SW1CCONF 0x32
651 #define PFUZE100_SW1ABC_SETP(x) ((x-3000)/250) 651 #define PFUZE100_SW1ABC_SETP(x) ((x-3000)/250)
652 652
653 /* set all switches APS in normal and PFM mode in standby */ 653 /* set all switches APS in normal and PFM mode in standby */
654 static int setup_pmic_mode(int chip) 654 static int setup_pmic_mode(int chip)
655 { 655 {
656 unsigned char offset, i, switch_num, value; 656 unsigned char offset, i, switch_num, value;
657 657
658 if (!chip) { 658 if (!chip) {
659 /* pfuze100 */ 659 /* pfuze100 */
660 switch_num = 6; 660 switch_num = 6;
661 offset = 0x31; 661 offset = 0x31;
662 } else { 662 } else {
663 /* pfuze200 */ 663 /* pfuze200 */
664 switch_num = 4; 664 switch_num = 4;
665 offset = 0x38; 665 offset = 0x38;
666 } 666 }
667 667
668 value = 0xc; 668 value = 0xc;
669 if (i2c_write(0x8, 0x23, 1, &value, 1)) { 669 if (i2c_write(0x8, 0x23, 1, &value, 1)) {
670 printf("Set SW1AB mode error!\n"); 670 printf("Set SW1AB mode error!\n");
671 return -1; 671 return -1;
672 } 672 }
673 673
674 for (i = 0; i < switch_num - 1; i++) { 674 for (i = 0; i < switch_num - 1; i++) {
675 if (i2c_write(0x8, offset + i * 7, 1, &value, 1)) { 675 if (i2c_write(0x8, offset + i * 7, 1, &value, 1)) {
676 printf("Set switch%x mode error!\n", offset); 676 printf("Set switch%x mode error!\n", offset);
677 return -1; 677 return -1;
678 } 678 }
679 } 679 }
680 680
681 return 0; 681 return 0;
682 } 682 }
683 683
684 static int setup_pmic_voltages(void) 684 static int setup_pmic_voltages(void)
685 { 685 {
686 unsigned char value, rev_id = 0; 686 unsigned char value, rev_id = 0;
687 687
688 i2c_set_bus_num(CONFIG_PMIC_I2C_BUS); 688 i2c_set_bus_num(CONFIG_PMIC_I2C_BUS);
689 689
690 if (!i2c_probe(CONFIG_PMIC_I2C_SLAVE)) { 690 if (!i2c_probe(CONFIG_PMIC_I2C_SLAVE)) {
691 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_DEVICEID, 1, &value, 1)) { 691 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_DEVICEID, 1, &value, 1)) {
692 printf("Read device ID error!\n"); 692 printf("Read device ID error!\n");
693 return -1; 693 return -1;
694 } 694 }
695 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_REVID, 1, &rev_id, 1)) { 695 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_REVID, 1, &rev_id, 1)) {
696 printf("Read Rev ID error!\n"); 696 printf("Read Rev ID error!\n");
697 return -1; 697 return -1;
698 } 698 }
699 printf("Found PFUZE%s deviceid=%x,revid=%x\n", 699 printf("Found PFUZE%s deviceid=%x,revid=%x\n",
700 ((value & 0xf) == 0) ? "100" : "200", value, rev_id); 700 ((value & 0xf) == 0) ? "100" : "200", value, rev_id);
701 701
702 if (setup_pmic_mode(value & 0xf)) { 702 if (setup_pmic_mode(value & 0xf)) {
703 printf("setup pmic mode error!\n"); 703 printf("setup pmic mode error!\n");
704 return -1; 704 return -1;
705 } 705 }
706 /* set SW1AB staby volatage 0.975V */ 706 /* set SW1AB staby volatage 0.975V */
707 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABSTBY, 1, &value, 1)) { 707 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABSTBY, 1, &value, 1)) {
708 printf("Read SW1ABSTBY error!\n"); 708 printf("Read SW1ABSTBY error!\n");
709 return -1; 709 return -1;
710 } 710 }
711 value &= ~0x3f; 711 value &= ~0x3f;
712 value |= PFUZE100_SW1ABC_SETP(9750); 712 value |= PFUZE100_SW1ABC_SETP(9750);
713 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABSTBY, 1, &value, 1)) { 713 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABSTBY, 1, &value, 1)) {
714 printf("Set SW1ABSTBY error!\n"); 714 printf("Set SW1ABSTBY error!\n");
715 return -1; 715 return -1;
716 } 716 }
717 717
718 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ 718 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
719 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABCONF, 1, &value, 1)) { 719 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABCONF, 1, &value, 1)) {
720 printf("Read SW1ABCONFIG error!\n"); 720 printf("Read SW1ABCONFIG error!\n");
721 return -1; 721 return -1;
722 } 722 }
723 value &= ~0xc0; 723 value &= ~0xc0;
724 value |= 0x40; 724 value |= 0x40;
725 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABCONF, 1, &value, 1)) { 725 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABCONF, 1, &value, 1)) {
726 printf("Set SW1ABCONFIG error!\n"); 726 printf("Set SW1ABCONFIG error!\n");
727 return -1; 727 return -1;
728 } 728 }
729 729
730 /* set SW1C staby volatage 0.975V */ 730 /* set SW1C staby volatage 0.975V */
731 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CSTBY, 1, &value, 1)) { 731 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CSTBY, 1, &value, 1)) {
732 printf("Read SW1CSTBY error!\n"); 732 printf("Read SW1CSTBY error!\n");
733 return -1; 733 return -1;
734 } 734 }
735 value &= ~0x3f; 735 value &= ~0x3f;
736 value |= PFUZE100_SW1ABC_SETP(9750); 736 value |= PFUZE100_SW1ABC_SETP(9750);
737 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CSTBY, 1, &value, 1)) { 737 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CSTBY, 1, &value, 1)) {
738 printf("Set SW1CSTBY error!\n"); 738 printf("Set SW1CSTBY error!\n");
739 return -1; 739 return -1;
740 } 740 }
741 741
742 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ 742 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
743 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CCONF, 1, &value, 1)) { 743 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CCONF, 1, &value, 1)) {
744 printf("Read SW1CCONFIG error!\n"); 744 printf("Read SW1CCONFIG error!\n");
745 return -1; 745 return -1;
746 } 746 }
747 value &= ~0xc0; 747 value &= ~0xc0;
748 value |= 0x40; 748 value |= 0x40;
749 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CCONF, 1, &value, 1)) { 749 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CCONF, 1, &value, 1)) {
750 printf("Set SW1CCONFIG error!\n"); 750 printf("Set SW1CCONFIG error!\n");
751 return -1; 751 return -1;
752 } 752 }
753 } 753 }
754 754
755 return 0; 755 return 0;
756 } 756 }
757 757
758 #ifdef CONFIG_LDO_BYPASS_CHECK 758 #ifdef CONFIG_LDO_BYPASS_CHECK
759 void ldo_mode_set(int ldo_bypass) 759 void ldo_mode_set(int ldo_bypass)
760 { 760 {
761 unsigned char value; 761 unsigned char value;
762 int is_400M; 762 int is_400M;
763 u32 vddarm; 763 u32 vddarm;
764 /* swith to ldo_bypass mode */ 764 /* swith to ldo_bypass mode */
765 if (ldo_bypass) { 765 if (ldo_bypass) {
766 prep_anatop_bypass(); 766 prep_anatop_bypass();
767 /* decrease VDDARM to 1.275V */ 767 /* decrease VDDARM to 1.275V */
768 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) { 768 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) {
769 printf("Read SW1AB error!\n"); 769 printf("Read SW1AB error!\n");
770 return; 770 return;
771 } 771 }
772 value &= ~0x3f; 772 value &= ~0x3f;
773 value |= PFUZE100_SW1ABC_SETP(12750); 773 value |= PFUZE100_SW1ABC_SETP(12750);
774 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) { 774 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) {
775 printf("Set SW1AB error!\n"); 775 printf("Set SW1AB error!\n");
776 return; 776 return;
777 } 777 }
778 /* decrease VDDSOC to 1.3V */ 778 /* decrease VDDSOC to 1.3V */
779 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) { 779 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) {
780 printf("Read SW1C error!\n"); 780 printf("Read SW1C error!\n");
781 return; 781 return;
782 } 782 }
783 value &= ~0x3f; 783 value &= ~0x3f;
784 value |= PFUZE100_SW1ABC_SETP(13000); 784 value |= PFUZE100_SW1ABC_SETP(13000);
785 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) { 785 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) {
786 printf("Set SW1C error!\n"); 786 printf("Set SW1C error!\n");
787 return; 787 return;
788 } 788 }
789 789
790 is_400M = set_anatop_bypass(1); 790 is_400M = set_anatop_bypass(1);
791 if (is_400M) 791 if (is_400M)
792 vddarm = PFUZE100_SW1ABC_SETP(10750); 792 vddarm = PFUZE100_SW1ABC_SETP(10750);
793 else 793 else
794 vddarm = PFUZE100_SW1ABC_SETP(11750); 794 vddarm = PFUZE100_SW1ABC_SETP(11750);
795 795
796 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) { 796 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) {
797 printf("Read SW1AB error!\n"); 797 printf("Read SW1AB error!\n");
798 return; 798 return;
799 } 799 }
800 value &= ~0x3f; 800 value &= ~0x3f;
801 value |= vddarm; 801 value |= vddarm;
802 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) { 802 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) {
803 printf("Set SW1AB error!\n"); 803 printf("Set SW1AB error!\n");
804 return; 804 return;
805 } 805 }
806 806
807 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) { 807 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) {
808 printf("Read SW1C error!\n"); 808 printf("Read SW1C error!\n");
809 return; 809 return;
810 } 810 }
811 value &= ~0x3f; 811 value &= ~0x3f;
812 value |= PFUZE100_SW1ABC_SETP(11750); 812 value |= PFUZE100_SW1ABC_SETP(11750);
813 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) { 813 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) {
814 printf("Set SW1C error!\n"); 814 printf("Set SW1C error!\n");
815 return; 815 return;
816 } 816 }
817 817
818 finish_anatop_bypass(); 818 finish_anatop_bypass();
819 printf("switch to ldo_bypass mode!\n"); 819 printf("switch to ldo_bypass mode!\n");
820 } 820 }
821 821
822 } 822 }
823 #endif 823 #endif
824 #endif 824 #endif
825 825
826 int board_early_init_f(void) 826 int board_early_init_f(void)
827 { 827 {
828 setup_iomux_uart(); 828 setup_iomux_uart();
829 return 0; 829 return 0;
830 } 830 }
831 831
832 int board_init(void) 832 int board_init(void)
833 { 833 {
834 /* address of boot parameters */ 834 /* address of boot parameters */
835 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 835 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
836 836
837 #ifdef CONFIG_SYS_I2C_MXC 837 #ifdef CONFIG_SYS_I2C_MXC
838 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 838 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
839 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 839 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
840 #endif 840 #endif
841 841
842 #ifdef CONFIG_FEC_MXC 842 #ifdef CONFIG_FEC_MXC
843 setup_fec(); 843 setup_fec();
844 #endif 844 #endif
845 845
846 #ifdef CONFIG_SYS_USE_SPINOR 846 #ifdef CONFIG_SYS_USE_SPINOR
847 setup_spinor(); 847 setup_spinor();
848 #endif 848 #endif
849 849
850 #ifdef CONFIG_SYS_USE_EIMNOR 850 #ifdef CONFIG_SYS_USE_EIMNOR
851 setup_eimnor(); 851 setup_eimnor();
852 #endif 852 #endif
853 853
854 #ifdef CONFIG_SYS_USE_NAND 854 #ifdef CONFIG_SYS_USE_NAND
855 setup_gpmi_nand(); 855 setup_gpmi_nand();
856 #endif 856 #endif
857 857
858 #ifdef CONFIG_QSPI 858 #ifdef CONFIG_QSPI
859 board_qspi_init(); 859 board_qspi_init();
860 #endif 860 #endif
861 861
862 return 0; 862 return 0;
863 } 863 }
864 864
865 #ifdef CONFIG_CMD_BMODE 865 #ifdef CONFIG_CMD_BMODE
866 static const struct boot_mode board_boot_modes[] = { 866 static const struct boot_mode board_boot_modes[] = {
867 /* 4 bit bus width */ 867 /* 4 bit bus width */
868 {"sd1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, 868 {"sd1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
869 {"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)}, 869 {"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)},
870 {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0B)}, 870 {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0B)},
871 {"eimnor", MAKE_CFGVAL(0x00, 0x80, 0x00, 0x00)}, 871 {"eimnor", MAKE_CFGVAL(0x00, 0x80, 0x00, 0x00)},
872 {NULL, 0}, 872 {NULL, 0},
873 }; 873 };
874 #endif 874 #endif
875 875
876 int board_late_init(void) 876 int board_late_init(void)
877 { 877 {
878 #ifdef CONFIG_CMD_BMODE 878 #ifdef CONFIG_CMD_BMODE
879 add_board_boot_modes(board_boot_modes); 879 add_board_boot_modes(board_boot_modes);
880 #endif 880 #endif
881 881
882 #ifdef CONFIG_PFUZE100_PMIC_I2C 882 #ifdef CONFIG_PFUZE100_PMIC_I2C
883 int ret = 0; 883 int ret = 0;
884 884
885 ret = setup_pmic_voltages(); 885 ret = setup_pmic_voltages();
886 if (ret) 886 if (ret)
887 return -1; 887 return -1;
888 #endif 888 #endif
889 889
890 #ifdef CONFIG_ENV_IS_IN_MMC 890 #ifdef CONFIG_ENV_IS_IN_MMC
891 board_late_mmc_init(); 891 board_late_mmc_init();
892 #endif 892 #endif
893 893
894 return 0; 894 return 0;
895 } 895 }
896 896
897 u32 get_board_rev(void) 897 u32 get_board_rev(void)
898 { 898 {
899 return get_cpu_rev(); 899 return get_cpu_rev();
900 } 900 }
901 901
902 int checkboard(void) 902 int checkboard(void)
903 { 903 {
904 puts("Board: MX6SX 19x19 ARM2\n"); 904 puts("Board: MX6SX 19x19 ARM2\n");
905 905
906 return 0; 906 return 0;
907 } 907 }
908 908
909 #ifdef CONFIG_USB_EHCI_MX6 909 #ifdef CONFIG_USB_EHCI_MX6
910 iomux_v3_cfg_t const usb_otg1_pads[] = { 910 iomux_v3_cfg_t const usb_otg1_pads[] = {
911 MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 911 MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
912 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL) 912 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL)
913 }; 913 };
914 914
915 iomux_v3_cfg_t const usb_otg2_pads[] = { 915 iomux_v3_cfg_t const usb_otg2_pads[] = {
916 MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 916 MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
917 }; 917 };
918 918
919 int board_ehci_hcd_init(int port) 919 int board_ehci_hcd_init(int port)
920 { 920 {
921 switch (port) { 921 switch (port) {
922 case 0: 922 case 0:
923 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, 923 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
924 ARRAY_SIZE(usb_otg1_pads)); 924 ARRAY_SIZE(usb_otg1_pads));
925 break; 925 break;
926 case 1: 926 case 1:
927 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, 927 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
928 ARRAY_SIZE(usb_otg2_pads)); 928 ARRAY_SIZE(usb_otg2_pads));
929 break; 929 break;
930 default: 930 default:
931 printf("MXC USB port %d not yet supported\n", port); 931 printf("MXC USB port %d not yet supported\n", port);
932 return 1; 932 return 1;