Commit 5a1d0ad3ee1ba98ca273c4b35c68618f107ccadd
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d8540a1619
Exists in
v2017.01-smarct4x
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arm: socfpga: Use EMAC1 on SoCDK
The SoCDK uses EMAC1, not EMAC0. This patch fixes the issue. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
Showing 1 changed file with 1 additions and 1 deletions Inline Diff
include/configs/socfpga_cyclone5.h
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2014 Marek Vasut <marex@denx.de> | 2 | * Copyright (C) 2014 Marek Vasut <marex@denx.de> |
| 3 | * | 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ | 5 | */ |
| 6 | #ifndef __CONFIG_SOCFPGA_CYCLONE5_H__ | 6 | #ifndef __CONFIG_SOCFPGA_CYCLONE5_H__ |
| 7 | #define __CONFIG_SOCFPGA_CYCLONE5_H__ | 7 | #define __CONFIG_SOCFPGA_CYCLONE5_H__ |
| 8 | 8 | ||
| 9 | #include <asm/arch/socfpga_base_addrs.h> | 9 | #include <asm/arch/socfpga_base_addrs.h> |
| 10 | #include "../../board/altera/socfpga/pinmux_config.h" | 10 | #include "../../board/altera/socfpga/pinmux_config.h" |
| 11 | #include "../../board/altera/socfpga/iocsr_config.h" | 11 | #include "../../board/altera/socfpga/iocsr_config.h" |
| 12 | #include "../../board/altera/socfpga/pll_config.h" | 12 | #include "../../board/altera/socfpga/pll_config.h" |
| 13 | 13 | ||
| 14 | /* U-Boot Commands */ | 14 | /* U-Boot Commands */ |
| 15 | #define CONFIG_SYS_NO_FLASH | 15 | #define CONFIG_SYS_NO_FLASH |
| 16 | #include <config_cmd_default.h> | 16 | #include <config_cmd_default.h> |
| 17 | #define CONFIG_DOS_PARTITION | 17 | #define CONFIG_DOS_PARTITION |
| 18 | #define CONFIG_FAT_WRITE | 18 | #define CONFIG_FAT_WRITE |
| 19 | #define CONFIG_HW_WATCHDOG | 19 | #define CONFIG_HW_WATCHDOG |
| 20 | 20 | ||
| 21 | #define CONFIG_CMD_ASKENV | 21 | #define CONFIG_CMD_ASKENV |
| 22 | #define CONFIG_CMD_BOOTZ | 22 | #define CONFIG_CMD_BOOTZ |
| 23 | #define CONFIG_CMD_CACHE | 23 | #define CONFIG_CMD_CACHE |
| 24 | #define CONFIG_CMD_DHCP | 24 | #define CONFIG_CMD_DHCP |
| 25 | #define CONFIG_CMD_EXT4 | 25 | #define CONFIG_CMD_EXT4 |
| 26 | #define CONFIG_CMD_EXT4_WRITE | 26 | #define CONFIG_CMD_EXT4_WRITE |
| 27 | #define CONFIG_CMD_FAT | 27 | #define CONFIG_CMD_FAT |
| 28 | #define CONFIG_CMD_FPGA | 28 | #define CONFIG_CMD_FPGA |
| 29 | #define CONFIG_CMD_FS_GENERIC | 29 | #define CONFIG_CMD_FS_GENERIC |
| 30 | #define CONFIG_CMD_GREPENV | 30 | #define CONFIG_CMD_GREPENV |
| 31 | #define CONFIG_CMD_MII | 31 | #define CONFIG_CMD_MII |
| 32 | #define CONFIG_CMD_MMC | 32 | #define CONFIG_CMD_MMC |
| 33 | #define CONFIG_CMD_NET | 33 | #define CONFIG_CMD_NET |
| 34 | #define CONFIG_CMD_PING | 34 | #define CONFIG_CMD_PING |
| 35 | #define CONFIG_CMD_SETEXPR | 35 | #define CONFIG_CMD_SETEXPR |
| 36 | 36 | ||
| 37 | #define CONFIG_REGEX /* Enable regular expression support */ | 37 | #define CONFIG_REGEX /* Enable regular expression support */ |
| 38 | 38 | ||
| 39 | /* Memory configurations */ | 39 | /* Memory configurations */ |
| 40 | #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ | 40 | #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ |
| 41 | 41 | ||
| 42 | /* Booting Linux */ | 42 | /* Booting Linux */ |
| 43 | #define CONFIG_BOOTDELAY 3 | 43 | #define CONFIG_BOOTDELAY 3 |
| 44 | #define CONFIG_BOOTFILE "zImage" | 44 | #define CONFIG_BOOTFILE "zImage" |
| 45 | #define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE) | 45 | #define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE) |
| 46 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | 46 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
| 47 | #define CONFIG_BOOTCOMMAND "run ramboot" | 47 | #define CONFIG_BOOTCOMMAND "run ramboot" |
| 48 | #else | 48 | #else |
| 49 | #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" | 49 | #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" |
| 50 | #endif | 50 | #endif |
| 51 | #define CONFIG_LOADADDR 0x8000 | 51 | #define CONFIG_LOADADDR 0x8000 |
| 52 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | 52 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
| 53 | 53 | ||
| 54 | /* Ethernet on SoC (EMAC) */ | 54 | /* Ethernet on SoC (EMAC) */ |
| 55 | #if defined(CONFIG_CMD_NET) | 55 | #if defined(CONFIG_CMD_NET) |
| 56 | #define CONFIG_EMAC_BASE SOCFPGA_EMAC0_ADDRESS | 56 | #define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS |
| 57 | #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII | 57 | #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII |
| 58 | #define CONFIG_EPHY0_PHY_ADDR 0 | 58 | #define CONFIG_EPHY0_PHY_ADDR 0 |
| 59 | 59 | ||
| 60 | /* PHY */ | 60 | /* PHY */ |
| 61 | #define CONFIG_EPHY1_PHY_ADDR 4 | 61 | #define CONFIG_EPHY1_PHY_ADDR 4 |
| 62 | #define CONFIG_PHY_MICREL | 62 | #define CONFIG_PHY_MICREL |
| 63 | #define CONFIG_PHY_MICREL_KSZ9021 | 63 | #define CONFIG_PHY_MICREL_KSZ9021 |
| 64 | #define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" | 64 | #define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" |
| 65 | #define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 | 65 | #define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 |
| 66 | #define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" | 66 | #define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" |
| 67 | #define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 | 67 | #define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 |
| 68 | 68 | ||
| 69 | #endif | 69 | #endif |
| 70 | 70 | ||
| 71 | /* Extra Environment */ | 71 | /* Extra Environment */ |
| 72 | #define CONFIG_HOSTNAME socfpga_cyclone5 | 72 | #define CONFIG_HOSTNAME socfpga_cyclone5 |
| 73 | 73 | ||
| 74 | #define CONFIG_EXTRA_ENV_SETTINGS \ | 74 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 75 | "verify=n\0" \ | 75 | "verify=n\0" \ |
| 76 | "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ | 76 | "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ |
| 77 | "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ | 77 | "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ |
| 78 | "bootm ${loadaddr} - ${fdt_addr}\0" \ | 78 | "bootm ${loadaddr} - ${fdt_addr}\0" \ |
| 79 | "bootimage=zImage\0" \ | 79 | "bootimage=zImage\0" \ |
| 80 | "fdt_addr=100\0" \ | 80 | "fdt_addr=100\0" \ |
| 81 | "fdtimage=socfpga.dtb\0" \ | 81 | "fdtimage=socfpga.dtb\0" \ |
| 82 | "fsloadcmd=ext2load\0" \ | 82 | "fsloadcmd=ext2load\0" \ |
| 83 | "bootm ${loadaddr} - ${fdt_addr}\0" \ | 83 | "bootm ${loadaddr} - ${fdt_addr}\0" \ |
| 84 | "mmcroot=/dev/mmcblk0p2\0" \ | 84 | "mmcroot=/dev/mmcblk0p2\0" \ |
| 85 | "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ | 85 | "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ |
| 86 | " root=${mmcroot} rw rootwait;" \ | 86 | " root=${mmcroot} rw rootwait;" \ |
| 87 | "bootz ${loadaddr} - ${fdt_addr}\0" \ | 87 | "bootz ${loadaddr} - ${fdt_addr}\0" \ |
| 88 | "mmcload=mmc rescan;" \ | 88 | "mmcload=mmc rescan;" \ |
| 89 | "load mmc 0:1 ${loadaddr} ${bootimage};" \ | 89 | "load mmc 0:1 ${loadaddr} ${bootimage};" \ |
| 90 | "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ | 90 | "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ |
| 91 | "qspiroot=/dev/mtdblock0\0" \ | 91 | "qspiroot=/dev/mtdblock0\0" \ |
| 92 | "qspirootfstype=jffs2\0" \ | 92 | "qspirootfstype=jffs2\0" \ |
| 93 | "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ | 93 | "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ |
| 94 | " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ | 94 | " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ |
| 95 | "bootm ${loadaddr} - ${fdt_addr}\0" | 95 | "bootm ${loadaddr} - ${fdt_addr}\0" |
| 96 | 96 | ||
| 97 | /* The rest of the configuration is shared */ | 97 | /* The rest of the configuration is shared */ |
| 98 | #include <configs/socfpga_common.h> | 98 | #include <configs/socfpga_common.h> |
| 99 | 99 | ||
| 100 | #endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */ | 100 | #endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */ |
| 101 | 101 |