Eric Lee / smarc-uboot | Embedian Git Server

Commit 5fd6badbd265ef45d3e1faebe5868426ab69595c

Authored by Simon Glass 2016-01-22 10:43:31 +0800

Exists in v2017.01-smarct4x and in 30 other branches

dm: Add a power sequencing uclass

Some devices need special sequences to be used when starting up. Add a
uclass for this. Drivers can be added to provide specific features as
needed.

Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 5 changed files with 62 additions and 0 deletions Inline Diff

drivers/misc/Kconfig
drivers/misc/Makefile
drivers/misc/pwrseq-uclass.c
include/dm/uclass-id.h
include/pwrseq.h

drivers/misc/Kconfig

Diff comments View file @ 5fd6bad

 #
 # Multifunction miscellaneous devices
 #
 menu "Multifunction device drivers"
 config MISC
 	bool "Enable Driver Model for Misc drivers"
 	depends on DM
 	help
 	  Enable driver model for miscellaneous devices. This class is
 	  used only for those do not fit other more general classes. A
 	  set of generic read, write and ioctl methods may be used to
 	  access the device.
 config ALTERA_SYSID
 	bool "Altera Sysid support"
 	depends on MISC
 	help
 	  Select this to enable a sysid for Altera devices. Please find
 	  details on the "Embedded Peripherals IP User Guide" of Altera.
 config CMD_CROS_EC
 	bool "Enable crosec command"
 	depends on CROS_EC
 	help
 	  Enable command-line access to the Chrome OS EC (Embedded
 	  Controller). This provides the 'crosec' command which has
 	  a number of sub-commands for performing EC tasks such as
 	  updating its flash, accessing a small saved context area
 	  and talking to the I2C bus behind the EC (if there is one).
 config CROS_EC
 	bool "Enable Chrome OS EC"
 	help
 	  Enable access to the Chrome OS EC. This is a separate
 	  microcontroller typically available on a SPI bus on Chromebooks. It
 	  provides access to the keyboard, some internal storage and may
 	  control access to the battery and main PMIC depending on the
 	  device. You can use the 'crosec' command to access it.
 config CROS_EC_I2C
 	bool "Enable Chrome OS EC I2C driver"
 	depends on CROS_EC
 	help
 	  Enable I2C access to the Chrome OS EC. This is used on older
 	  ARM Chromebooks such as snow and spring before the standard bus
 	  changed to SPI. The EC will accept commands across the I2C using
 	  a special message protocol, and provide responses.
 config CROS_EC_LPC
 	bool "Enable Chrome OS EC LPC driver"
 	depends on CROS_EC
 	help
 	  Enable I2C access to the Chrome OS EC. This is used on x86
 	  Chromebooks such as link and falco. The keyboard is provided
 	  through a legacy port interface, so on x86 machines the main
 	  function of the EC is power and thermal management.
 config CROS_EC_SANDBOX
 	bool "Enable Chrome OS EC sandbox driver"
 	depends on CROS_EC && SANDBOX
 	help
 	  Enable a sandbox emulation of the Chrome OS EC. This supports
 	  keyboard (use the -l flag to enable the LCD), verified boot context,
 	  EC flash read/write/erase support and a few other things. It is
 	  enough to perform a Chrome OS verified boot on sandbox.
 config CROS_EC_SPI
 	bool "Enable Chrome OS EC SPI driver"
 	depends on CROS_EC
 	help
 	  Enable SPI access to the Chrome OS EC. This is used on newer
 	  ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
 	  provides a faster and more robust interface than I2C but the bugs
 	  are less interesting.
 config FSL_SEC_MON
 	bool "Enable FSL SEC_MON Driver"
 	help
 	  Freescale Security Monitor block is responsible for monitoring
 	  system states.
 	  Security Monitor can be transitioned on any security failures,
 	  like software violations or hardware security violations.
 config MXC_OCOTP
 	bool "Enable MXC OCOTP Driver"
 	help
 	  If you say Y here, you will get support for the One Time
 	  Programmable memory pages that are stored on the some
 	  Freescale i.MX processors.
+config PWRSEQ
+	bool "Enable power-sequencing drivers"
+	depends on DM
+	help
+	  Power-sequencing drivers provide support for controlling power for
+	  devices. They are typically referenced by a phandle from another
+	  device. When the device is started up, its power sequence can be
+	  initiated.
+config SPL_PWRSEQ
+	bool "Enable power-sequencing drivers for SPL"
+	depends on PWRSEQ
+	help
+	  Power-sequencing drivers provide support for controlling power for
+	  devices. They are typically referenced by a phandle from another
+	  device. When the device is started up, its power sequence can be
+	  initiated.
 config PCA9551_LED
 	bool "Enable PCA9551 LED driver"
 	help
 	  Enable driver for PCA9551 LED controller. This controller
 	  is connected via I2C. So I2C needs to be enabled.
 config PCA9551_I2C_ADDR
 	hex "I2C address of PCA9551 LED controller"
 	depends on PCA9551_LED
 	default 0x60
 	help
 	  The I2C address of the PCA9551 LED controller.
 config RESET
 	bool "Enable support for reset drivers"
 	depends on DM
 	help
 	  Enable reset drivers which can be used to reset the CPU or board.
 	  Each driver can provide a reset method which will be called to
 	  effect a reset. The uclass will try all available drivers when
 	  reset_walk() is called.
 endmenu

drivers/misc/Makefile

Diff comments View file @ 5fd6bad

 #
 # (C) Copyright 2000-2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 obj-$(CONFIG_MISC) += misc-uclass.o
 obj-$(CONFIG_ALI152X) += ali512x.o
 obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o
 obj-$(CONFIG_DS4510)  += ds4510.o
 obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
 obj-$(CONFIG_CROS_EC) += cros_ec.o
 obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o
 obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
 obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o
 obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
 obj-$(CONFIG_FSL_DEBUG_SERVER) += fsl_debug_server.o
 obj-$(CONFIG_FSL_IIM) += fsl_iim.o
 obj-$(CONFIG_GPIO_LED) += gpio_led.o
 obj-$(CONFIG_I2C_EEPROM) += i2c_eeprom.o
 obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
 obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
 obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
 obj-$(CONFIG_NS87308) += ns87308.o
 obj-$(CONFIG_PDSP188x) += pdsp188x.o
+obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
 obj-$(CONFIG_SANDBOX) += reset_sandbox.o
 ifdef CONFIG_DM_I2C
 obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
 endif
 obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
 obj-$(CONFIG_STATUS_LED) += status_led.o
 obj-$(CONFIG_SANDBOX) += swap_case.o
 obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
 obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
 obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
 obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
 obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
 obj-$(CONFIG_RESET) += reset-uclass.o
 obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o

drivers/misc/pwrseq-uclass.c

Diff comments View file @ 5fd6bad

File was created	1	/*
	2	* Copyright (c) 2015 Google, Inc
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <dm.h>
	9	#include <pwrseq.h>
	10
	11	int pwrseq_set_power(struct udevice *dev, bool enable)
	12	{
	13	struct pwrseq_ops *ops = pwrseq_get_ops(dev);
	14
	15	if (!ops->set_power)
	16	return -ENOSYS;
	17
	18	return ops->set_power(dev, enable);
	19	}
	20
	21	UCLASS_DRIVER(pwrseq) = {
	22	.id = UCLASS_PWRSEQ,
	23	.name = "pwrseq",
	24	};
	25

include/dm/uclass-id.h

Diff comments View file @ 5fd6bad

 /*
  * Copyright (c) 2013 Google, Inc
  *
  * (C) Copyright 2012
  * Pavel Herrmann <morpheus.ibis@gmail.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef _DM_UCLASS_ID_H
 #define _DM_UCLASS_ID_H
 /* TODO(sjg@chromium.org): this could be compile-time generated */
 enum uclass_id {
 	/* These are used internally by driver model */
 	UCLASS_ROOT = 0,
 	UCLASS_DEMO,
 	UCLASS_TEST,
 	UCLASS_TEST_FDT,
 	UCLASS_TEST_BUS,
 	UCLASS_SPI_EMUL,	/* sandbox SPI device emulator */
 	UCLASS_I2C_EMUL,	/* sandbox I2C device emulator */
 	UCLASS_PCI_EMUL,	/* sandbox PCI device emulator */
 	UCLASS_USB_EMUL,	/* sandbox USB bus device emulator */
 	UCLASS_SIMPLE_BUS,	/* bus with child devices */
 	/* U-Boot uclasses start here - in alphabetical order */
 	UCLASS_ADC,		/* Analog-to-digital converter */
 	UCLASS_CLK,		/* Clock source, e.g. used by peripherals */
 	UCLASS_CPU,		/* CPU, typically part of an SoC */
 	UCLASS_CROS_EC,		/* Chrome OS EC */
 	UCLASS_DISPLAY_PORT,	/* Display port video */
 	UCLASS_RAM,		/* RAM controller */
 	UCLASS_ETH,		/* Ethernet device */
 	UCLASS_GPIO,		/* Bank of general-purpose I/O pins */
 	UCLASS_I2C,		/* I2C bus */
 	UCLASS_I2C_EEPROM,	/* I2C EEPROM device */
 	UCLASS_I2C_GENERIC,	/* Generic I2C device */
 	UCLASS_I2C_MUX,		/* I2C multiplexer */
 	UCLASS_KEYBOARD,	/* Keyboard input device */
 	UCLASS_LED,		/* Light-emitting diode (LED) */
 	UCLASS_LPC,		/* x86 'low pin count' interface */
 	UCLASS_MASS_STORAGE,	/* Mass storage device */
 	UCLASS_MISC,		/* Miscellaneous device */
 	UCLASS_MMC,		/* SD / MMC card or chip */
 	UCLASS_MOD_EXP,		/* RSA Mod Exp device */
 	UCLASS_MTD,		/* Memory Technology Device (MTD) device */
 	UCLASS_PCH,		/* x86 platform controller hub */
 	UCLASS_PCI,		/* PCI bus */
 	UCLASS_PCI_GENERIC,	/* Generic PCI bus device */
 	UCLASS_PINCTRL,		/* Pinctrl (pin muxing/configuration) device */
 	UCLASS_PINCONFIG,	/* Pin configuration node device */
 	UCLASS_PMIC,		/* PMIC I/O device */
+	UCLASS_PWRSEQ,		/* Power sequence device */
 	UCLASS_REGULATOR,	/* Regulator device */
 	UCLASS_RESET,		/* Reset device */
 	UCLASS_REMOTEPROC,	/* Remote Processor device */
 	UCLASS_RTC,		/* Real time clock device */
 	UCLASS_SERIAL,		/* Serial UART */
 	UCLASS_SPI,		/* SPI bus */
 	UCLASS_SPI_FLASH,	/* SPI flash */
 	UCLASS_SPI_GENERIC,	/* Generic SPI flash target */
 	UCLASS_SYSCON,		/* System configuration device */
 	UCLASS_THERMAL,		/* Thermal sensor */
 	UCLASS_TIMER,		/* Timer device */
 	UCLASS_TPM,		/* Trusted Platform Module TIS interface */
 	UCLASS_USB,		/* USB bus */
 	UCLASS_USB_DEV_GENERIC,	/* USB generic device */
 	UCLASS_USB_HUB,		/* USB hub */
 	UCLASS_VIDEO,		/* Video or LCD device */
 	UCLASS_VIDEO_BRIDGE,	/* Video bridge, e.g. DisplayPort to LVDS */
 	UCLASS_VIDEO_CONSOLE,	/* Text console driver for video device */
 	UCLASS_COUNT,
 	UCLASS_INVALID = -1,
 };
 #endif

include/pwrseq.h

Diff comments View file @ 5fd6bad

File was created	1	/*
	2	* Copyright (c) 2013 Google, Inc
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __pwrseq_h
	8	#define __pwrseq_h
	9
	10	struct pwrseq_ops {
	11	int (set_power)(struct udevice dev, bool enable);
	12	};
	13
	14	#define pwrseq_get_ops(dev) ((struct pwrseq_ops *)(dev)->driver->ops)
	15
	16	int pwrseq_set_power(struct udevice *dev, bool enable);
	17
	18	#endif
	19