Eric Lee / smarc-uboot | Embedian Git Server

Commit 6001985f92e4a99504343485bfe2c18940a41011

Authored by Alexander Graf 2018-01-25 19:05:55 +0800

Committed by Tom Rini 2018-01-29 01:27:36 +0800

Exists in smarc_8mq_lf_v2020.04 and in 17 other branches

bcm2835_pl011_serial: Add BCM2835 specific serial driver

On bcm2835 we need to ensure we only access serial devices that are
muxed to the serial output pins of the pin header. To achieve this
for the pl011 device, add a bcm2835 specific pl011 wrapper device
that does this check but otherwise behaves like a pl011 device.

Signed-off-by: Alexander Graf <agraf@suse.de>

Showing 6 changed files with 101 additions and 9 deletions Inline Diff

MAINTAINERS
drivers/serial/Kconfig
drivers/serial/Makefile
drivers/serial/serial_bcm283x_pl011.c
drivers/serial/serial_pl01x.c
drivers/serial/serial_pl01x_internal.h

MAINTAINERS

Diff comments View file @ 6001985

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 	L: Mailing list that is relevant to this area
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 Note: For the hard of thinking, this list is meant to remain in alphabetical
 order. If you could add yourselves to it in alphabetical order that would be
 so much easier [Ed]
 Maintainers List (try to look for most precise areas first)
 		-----------------------------------
 ARC
 M:	Alexey Brodkin <alexey.brodkin@synopsys.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-arc.git
 F:	arch/arc/
 ARC HSDK CREG GPIO
 M:	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
 S:	Maintained
 L:	uboot-snps-arc@synopsys.com
 F:	drivers/gpio/hsdk-creg-gpio.c
 ARC HSDK CGU CLOCK
 M:	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
 S:	Maintained
 L:	uboot-snps-arc@synopsys.com
 F:	drivers/clk/clk-hsdk-cgu.c
 F:	include/dt-bindings/clock/snps,hsdk-cgu.h
 F:	doc/device-tree-bindings/clock/snps,hsdk-cgu.txt
 ARM
 M:	Albert Aribaud <albert.u.boot@aribaud.net>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-arm.git
 F:	arch/arm/
 ARM ALTERA SOCFPGA
 M:	Marek Vasut <marex@denx.de>
 S:	Maintainted
 T:	git git://git.denx.de/u-boot-socfpga.git
 F:	arch/arm/mach-socfpga/
 ARM ATMEL AT91
 M:	Andreas Bießmann <andreas@biessmann.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-atmel.git
 F:	arch/arm/mach-at91/
 ARM BROADCOM BCM283X
 M:	Alexander Graf <agraf@suse.de>
 S:	Maintained
 F:	arch/arm/mach-bcm283x/
 F:	drivers/gpio/bcm2835_gpio.c
 F:	drivers/mmc/bcm2835_sdhci.c
 F:	drivers/mmc/bcm2835_sdhost.c
 F:	drivers/serial/serial_bcm283x_mu.c
+F:	drivers/serial/serial_bcm283x_pl011.c
 F:	drivers/video/bcm2835.c
 F:	include/dm/platform_data/serial_bcm283x_mu.h
 F:	drivers/pinctrl/broadcom/
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 M:	Stefano Babic <sbabic@denx.de>
 M:	Fabio Estevam <fabio.estevam@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-imx.git
 F:	arch/arm/cpu/arm1136/mx*/
 F:	arch/arm/cpu/arm926ejs/mx*/
 F:	arch/arm/cpu/armv7/mx*/
 F:	arch/arm/cpu/armv7/vf610/
 F:	arch/arm/mach-imx/
 F:	arch/arm/include/asm/arch-imx/
 F:	arch/arm/include/asm/arch-mx*/
 F:	arch/arm/include/asm/arch-vf610/
 F:	arch/arm/include/asm/mach-imx/
 F:	board/freescale/*mx*/
 ARM HISILICON
 M:	Peter Griffin <peter.griffin@linaro.org>
 S:	Maintained
 F:	arch/arm/cpu/armv8/hisilicon
 F:	arm/include/asm/arch-hi6220/
 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X
 M:	Prafulla Wadaskar <prafulla@marvell.com>
 M:	Luka Perkov <luka.perkov@sartura.hr>
 M:	Stefan Roese <sr@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-marvell.git
 F:	arch/arm/mach-kirkwood/
 F:	arch/arm/mach-mvebu/
 ARM MARVELL PXA
 M:	Marek Vasut <marex@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-pxa.git
 F:	arch/arm/cpu/pxa/
 F:	arch/arm/include/asm/arch-pxa/
 ARM RENESAS RMOBILE/R-CAR
 M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 M:	Marek Vasut <marek.vasut+renesas@gmail.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-sh.git
 F:	arch/arm/mach-rmobile/
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 M:	Simon Glass <sjg@chromium.org>
 M:	Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-rockchip.git
 F:	arch/arm/include/asm/arch-rockchip/
 F:	arch/arm/mach-rockchip/
 F:	board/rockchip/
 F:	drivers/clk/rockchip/
 F:	drivers/gpio/rk_gpio.c
 F:	drivers/misc/rockchip-efuse.c
 F:	drivers/pinctrl/rockchip/
 F:	drivers/ram/rockchip/
 F:	drivers/sysreset/sysreset_rockchip.c
 F:	tools/rkcommon.c
 F:	tools/rkcommon.h
 F:	tools/rkimage.c
 F:	tools/rksd.c
 F:	tools/rkspi.c
 ARM SAMSUNG
 M:	Minkyu Kang <mk7.kang@samsung.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-samsung.git
 F:	arch/arm/cpu/arm920t/s3c24x0/
 F:	arch/arm/mach-exynos/
 F:	arch/arm/mach-s5pc1xx/
 F:	arch/arm/cpu/armv7/s5p-common/
 F:	arch/arm/include/asm/arch-s3c24x0/
 ARM SNAPDRAGON
 M:	Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
 S:	Maintained
 F:	arch/arm/mach-snapdragon/
 ARM STM SPEAR
 #M:	Vipin Kumar <vipin.kumar@st.com>
 S:	Orphaned (Since 2016-02)
 T:	git git://git.denx.de/u-boot-stm.git
 F:	arch/arm/cpu/arm926ejs/spear/
 F:	arch/arm/include/asm/arch-spear/
 ARM STM STV0991
 M:	Vikas Manocha <vikas.manocha@st.com>
 S:	Maintained
 F:	arch/arm/cpu/armv7/stv0991/
 F:	arch/arm/include/asm/arch-stv0991/
 ARM STI
 M:	Patrice Chotard <patrice.chotard@st.com>
 S:	Maintained
 F:	arch/arm/mach-sti/
 F:	arch/arm/include/asm/arch-sti*/
 ARM SUNXI
 M:	Jagan Teki <jagan@openedev.com>
 M:	Maxime Ripard <maxime.ripard@free-electrons.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-sunxi.git
 F:	arch/arm/cpu/armv7/sunxi/
 F:	arch/arm/include/asm/arch-sunxi/
 F:	arch/arm/mach-sunxi/
 F:	board/sunxi/
 ARM TEGRA
 M:	Tom Warren <twarren@nvidia.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-tegra.git
 F:	arch/arm/mach-tegra/
 F:	arch/arm/include/asm/arch-tegra*/
 ARM TI
 M:	Tom Rini <trini@konsulko.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-ti.git
 F:	arch/arm/mach-davinci/
 F:	arch/arm/mach-keystone/
 F:	arch/arm/cpu/arm926ejs/omap/
 F:	arch/arm/cpu/armv7/omap*/
 F:	arch/arm/include/asm/arch-omap*/
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 ARM UNIPHIER
 M:	Masahiro Yamada <yamada.masahiro@socionext.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-uniphier.git
 F:	arch/arm/mach-uniphier/
 F:	configs/uniphier_*_defconfig
 N:	uniphier
 ARM ZYNQ
 M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained
 F:	arch/arm/cpu/armv7/zynq/
 F:	arch/arm/include/asm/arch-zynq/
 ARM ZYNQMP
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
 F:	arch/arm/cpu/armv8/zynqmp/
 F:	arch/arm/include/asm/arch-zynqmp/
 BUILDMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	tools/buildman/
 CFI FLASH
 M:	Stefan Roese <sr@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-cfi-flash.git
 F:	drivers/mtd/cfi_flash.c
 F:	drivers/mtd/jedec_flash.c
 COLDFIRE
 M:	Huan Wang <alison.wang@freescale.com>
 M:	Angelo Dureghello <angelo@sysam.it>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-coldfire.git
 F:	arch/m68k/
 DFU
 M:	Lukasz Majewski <lukma@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-dfu.git
 F:	drivers/dfu/
 F:	drivers/usb/gadget/
 DRIVER MODEL
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-dm.git
 F:	drivers/core/
 F:	include/dm/
 F:	test/dm/
 EFI PAYLOAD
 M:	Alexander Graf <agraf@suse.de>
 S:	Maintained
 T:	git git://github.com/agraf/u-boot.git
 F:	include/efi*
 F:	lib/efi*/
 F:	test/py/tests/test_efi*
 F:	cmd/bootefi.c
 F:	tools/file2include.c
 FLATTENED DEVICE TREE
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-fdt.git
 F:	lib/fdtdec*
 F:	lib/libfdt/
 F:	include/fdt*
 F:	include/libfdt*
 F:	cmd/fdt.c
 F:	common/fdt_support.c
 FREEBSD
 M:	Rafal Jaworowski <raj@semihalf.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-freebsd.git
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 M:	York Sun <york.sun@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-fsl-qoriq.git
 I2C
 M:	Heiko Schocher <hs@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-i2c.git
 F:	drivers/i2c/
 LOGGING
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot.git
 F:	common/log.c
 F:	cmd/log.c
 F:	test/log/log_test.c
 F:	test/py/tests/test_log.py
 MICROBLAZE
 M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-microblaze.git
 F:	arch/microblaze/
 MIPS
 M:	Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mips.git
 F:	arch/mips/
 MMC
 M:	Jaehoon Chung <jh80.chung@samsung.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mmc.git
 F:	drivers/mmc/
 PATMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	tools/patman/
 POWERPC
 M:	Wolfgang Denk <wd@denx.de>
 S:	Maintained
 F:	arch/powerpc/
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 M:	Christophe Leroy <christophe.leroy@c-s.fr>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mpc8xx.git
 F:	arch/powerpc/cpu/mpc8xx/
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 M:	Mario Six <mario.six@gdsys.cc>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mpc83xx.git
 F:	arch/powerpc/cpu/mpc83xx/
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 POWERPC MPC85XX
 M:	York Sun <york.sun@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mpc85xx.git
 F:	arch/powerpc/cpu/mpc85xx/
 POWERPC MPC86XX
 M:	York Sun <york.sun@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mpc86xx.git
 F:	arch/powerpc/cpu/mpc86xx/
 POWERPC PPC4XX
 M:	Stefan Roese <sr@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-ppc4xx.git
 F:	arch/powerpc/cpu/ppc4xx/
 POWER
 M:	Jaehoon Chung <jh80.chung@samsung.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-pmic.git
 F:	drivers/power/
 NETWORK
 M:	Joe Hershberger <joe.hershberger@ni.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-net.git
 F:	drivers/net/
 F:	net/
 NAND FLASH
 M:	Scott Wood <oss@buserror.net>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-nand-flash.git
 F:	drivers/mtd/nand/
 NDS32
 M:	Macpaul Lin <macpaul@andestech.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-nds32.git
 F:	arch/nds32/
 NIOS
 M:	Thomas Chou <thomas@wytron.com.tw>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-nios.git
 F:	arch/nios2/
 ONENAND
 #M:	Lukasz Majewski <l.majewski@majess.pl>
 S:	Orphaned (Since 2017-01)
 T:	git git://git.denx.de/u-boot-onenand.git
 F:	drivers/mtd/onenand/
 RISC-V
 M:	Rick Chen <rick@andestech.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-riscv.git
 F:	arch/riscv/
 F:	tools/prelink-riscv.c
 SANDBOX
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	arch/sandbox/
 SH
 M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-sh.git
 F:	arch/sh/
 SPI
 M:	Jagan Teki <jagan@openedev.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-spi.git
 F:	drivers/mtd/spi/
 F:	drivers/spi/
 F:	include/spi*
 SPMI
 M:	Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
 S:	Maintained
 F:	drivers/spmi/
 F:	include/spmi/
 TI SYSTEM SECURITY
 M:	Andrew F. Davis <afd@ti.com>
 S:	Supported
 F:	arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
 F:	arch/arm/mach-omap2/omap5/sec-fxns.c
 F:	arch/arm/mach-omap2/sec-common.c
 F:	arch/arm/mach-omap2/config_secure.mk
 F:	configs/am335x_hs_evm_defconfig
 F:	configs/am335x_hs_evm_uart_defconfig
 F:	configs/am43xx_hs_evm_defconfig
 F:	configs/am57xx_hs_evm_defconfig
 F:	configs/dra7xx_hs_evm_defconfig
 F:	configs/k2hk_hs_evm_defconfig
 F:	configs/k2e_hs_evm_defconfig
 F:	configs/k2g_hs_evm_defconfig
 TQ GROUP
 #M:	Martin Krause <martin.krause@tq-systems.de>
 S:	Orphaned (Since 2016-02)
 T:	git git://git.denx.de/u-boot-tq-group.git
 UBI
 M:	Kyungmin Park <kmpark@infradead.org>
 M:	Heiko Schocher <hs@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-ubi.git
 F:	drivers/mtd/ubi/
 USB
 M:	Marek Vasut <marex@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-usb.git
 F:	drivers/usb/
 USB xHCI
 M:	Bin Meng <bmeng.cn@gmail.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-usb.git topic-xhci
 F:	drivers/usb/host/xhci*
 ROCKUSB
 M:	Eddie Cai <eddie.cai.linux@gmail.com>
 S:	Maintained
 F:	drivers/usb/gadget/f_rockusb.c
 F:	cmd/rockusb.c
 F:	doc/README.rockusb
 VIDEO
 M:	Anatolij Gustschin <agust@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-video.git
 F:	drivers/video/
 F:	common/lcd*.c
 F:	include/lcd*.h
 X86
 M:	Simon Glass <sjg@chromium.org>
 M:	Bin Meng <bmeng.cn@gmail.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-x86.git
 F:	arch/x86/
 XTENSA
 M:	Max Filippov <jcmvbkbc@gmail.com>
 S:	Maintained
 F:	arch/xtensa/
 THE REST
 M:	Tom Rini <trini@konsulko.com>
 L:	u-boot@lists.denx.de
 Q:	http://patchwork.ozlabs.org/project/uboot/list/
 S:	Maintained
 T:	git git://git.denx.de/u-boot.git
 F:	*
 F:	*/

drivers/serial/Kconfig

Diff comments View file @ 6001985

 #
 # Serial device configuration
 #
 menu "Serial drivers"
 config BAUDRATE
 	int "Default baudrate"
 	default 115200
 	help
 	  Select a default baudrate, where "default" has a driver-specific
 	  meaning of either setting the baudrate for the early debug UART
 	  in the SPL stage (most drivers) or for choosing a default baudrate
 	  in the absence of an environment setting (serial_mxc.c).
 config REQUIRE_SERIAL_CONSOLE
 	bool "Require a serial port for console"
 	# Running without a serial console is not supported by the
 	# non-dm serial code
 	depends on DM_SERIAL
 	default y
 	help
 	  Require a serial port for the console, and panic if none is found
 	  during serial port initialization (default y). Set this to n on
 	  boards which have no debug serial port whatsoever.
 config SERIAL_PRESENT
 	bool "Provide a serial driver"
 	depends on DM_SERIAL
 	default y
 	help
 	  In very space-constrained devices even the full UART driver is too
 	  large. In this case the debug UART can still be used in some cases.
 	  This option enables the full UART in U-Boot, so if is it disabled,
 	  the full UART driver will be omitted, thus saving space.
 config SPL_SERIAL_PRESENT
 	bool "Provide a serial driver in SPL"
 	depends on DM_SERIAL
 	default y
 	help
 	  In very space-constrained devices even the full UART driver is too
 	  large. In this case the debug UART can still be used in some cases.
 	  This option enables the full UART in SPL, so if is it disabled,
 	  the full UART driver will be omitted, thus saving space.
 config CONS_INDEX
 	int "UART used for console"
 	depends on ARCH_SUNXI
 	default 2 if MACH_SUN5I
 	default 5 if MACH_SUN8I_A23 || MACH_SUN8I_A33
 	default 1
 	help
 	  Configures the console index.
 	  For Allwinner SoC., default values are 2 for SUN5I and 5 for A23/A33.
 	  Otherwise, the index equals 1.
 config DM_SERIAL
 	bool "Enable Driver Model for serial drivers"
 	depends on DM
 	help
 	  Enable driver model for serial. This replaces
 	  drivers/serial/serial.c with the serial uclass, which
 	  implements serial_putc() etc. The uclass interface is
 	  defined in include/serial.h.
 config SERIAL_RX_BUFFER
 	bool "Enable RX buffer for serial input"
 	depends on DM_SERIAL
 	help
 	  Enable RX buffer support for the serial driver. This enables
 	  pasting longer strings, even when the RX FIFO of the UART is
 	  not big enough (e.g. 16 bytes on the normal NS16550).
 config SERIAL_RX_BUFFER_SIZE
 	int "RX buffer size"
 	depends on SERIAL_RX_BUFFER
 	default 256
 	help
 	  The size of the RX buffer (needs to be power of 2)
 config SPL_DM_SERIAL
 	bool "Enable Driver Model for serial drivers in SPL"
 	depends on DM_SERIAL
 	default y if SPL && DM_SERIAL
 	help
 	  Enable driver model for serial in SPL. This replaces
 	  drivers/serial/serial.c with the serial uclass, which
 	  implements serial_putc() etc. The uclass interface is
 	  defined in include/serial.h.
 config TPL_DM_SERIAL
 	bool "Enable Driver Model for serial drivers in TPL"
 	depends on DM_SERIAL
 	default y if TPL && DM_SERIAL
 	help
 	  Enable driver model for serial in TPL. This replaces
 	  drivers/serial/serial.c with the serial uclass, which
 	  implements serial_putc() etc. The uclass interface is
 	  defined in include/serial.h.
 config DEBUG_UART
 	bool "Enable an early debug UART for debugging"
 	help
 	  The debug UART is intended for use very early in U-Boot to debug
 	  problems when an ICE or other debug mechanism is not available.
 	  To use it you should:
 	  - Make sure your UART supports this interface
 	  - Enable CONFIG_DEBUG_UART
 	  - Enable the CONFIG for your UART to tell it to provide this interface
 	        (e.g. CONFIG_DEBUG_UART_NS16550)
 	  - Define the required settings as needed (see below)
 	  - Call debug_uart_init() before use
 	  - Call debug_uart_putc() to output a character
 	  Depending on your platform it may be possible to use this UART before
 	  a stack is available.
 	  If your UART does not support this interface you can probably add
 	  support quite easily. Remember that you cannot use driver model and
 	  it is preferred to use no stack.
 	  You must not use this UART once driver model is working and the
 	  serial drivers are up and running (done in serial_init()). Otherwise
 	  the drivers may conflict and you will get strange output.
 choice
 	prompt "Select which UART will provide the debug UART"
 	depends on DEBUG_UART
 	default DEBUG_UART_NS16550
 config DEBUG_UART_ALTERA_JTAGUART
 	bool "Altera JTAG UART"
 	help
 	  Select this to enable a debug UART using the altera_jtag_uart driver.
 	  You will need to provide parameters to make this work. The driver will
 	  be available until the real driver model serial is running.
 config DEBUG_UART_ALTERA_UART
 	bool "Altera UART"
 	help
 	  Select this to enable a debug UART using the altera_uart driver.
 	  You will need to provide parameters to make this work. The driver will
 	  be available until the real driver model serial is running.
 config DEBUG_UART_AR933X
 	bool "QCA/Atheros ar933x"
 	depends on AR933X_UART
 	help
 	  Select this to enable a debug UART using the ar933x uart driver.
 	  You will need to provide parameters to make this work. The
 	  driver will be available until the real driver model serial is
 	  running.
 config DEBUG_UART_ATMEL
 	bool "Atmel USART"
 	help
 	  Select this to enable a debug UART using the atmel usart driver. You
 	  will need to provide parameters to make this work. The driver will
 	  be available until the real driver-model serial is running.
 config DEBUG_UART_BCM6345
 	bool "BCM6345 UART"
 	depends on BCM6345_SERIAL
 	help
 	  Select this to enable a debug UART on BCM6345 SoCs. You
 	  will need to provide parameters to make this work. The driver will
 	  be available until the real driver model serial is running.
 config DEBUG_UART_NS16550
 	bool "ns16550"
 	help
 	  Select this to enable a debug UART using the ns16550 driver. You
 	  will need to provide parameters to make this work. The driver will
 	  be available until the real driver model serial is running.
 config DEBUG_EFI_CONSOLE
 	bool "EFI"
 	depends on EFI_APP
 	help
 	  Select this to enable a debug console which calls back to EFI to
 	  output to the console. This can be useful for early debugging of
 	  U-Boot when running on top of EFI (Extensive Firmware Interface).
 	  This is a type of BIOS used by PCs.
 config DEBUG_UART_S5P
 	bool "Samsung S5P"
 	help
 	  Select this to enable a debug UART using the serial_s5p driver. You
 	  will need to provide parameters to make this work. The driver will
 	  be available until the real driver-model serial is running.
 config DEBUG_UART_MESON
 	bool "Amlogic Meson"
 	depends on MESON_SERIAL
 	help
 	  Select this to enable a debug UART using the serial_meson driver. You
 	  will need to provide parameters to make this work. The driver will
 	  be available until the real driver-model serial is running.
 config DEBUG_UART_UARTLITE
 	bool "Xilinx Uartlite"
 	help
 	  Select this to enable a debug UART using the serial_uartlite driver.
 	  You will need to provide parameters to make this work. The driver will
 	  be available until the real driver-model serial is running.
 config DEBUG_UART_ARM_DCC
 	bool "ARM DCC"
 	help
 	  Select this to enable a debug UART using the ARM JTAG DCC port.
 	  The DCC port can be used for very early debugging and doesn't require
 	  any additional setting like address/baudrate/clock. On systems without
 	  any serial interface this is the easiest way how to get console.
 	  Every ARM core has own DCC port which is the part of debug interface.
 	  This port is available at least on ARMv6, ARMv7, ARMv8 and XScale
 	  architectures.
 config DEBUG_MVEBU_A3700_UART
 	bool "Marvell Armada 3700"
 	help
 	  Select this to enable a debug UART using the serial_mvebu driver. You
 	  will need to provide parameters to make this work. The driver will
 	  be available until the real driver-model serial is running.
 config DEBUG_UART_ZYNQ
 	bool "Xilinx Zynq"
 	help
 	  Select this to enable a debug UART using the serial_zynq driver. You
 	  will need to provide parameters to make this work. The driver will
 	  be available until the real driver-model serial is running.
 config DEBUG_UART_APBUART
 	depends on LEON3
 	bool "Gaisler APBUART"
 	help
 	  Select this to enable a debug UART using the serial_leon3 driver. You
 	  will need to provide parameters to make this work. The driver will
 	  be available until the real driver model serial is running.
 config DEBUG_UART_PL010
 	bool "pl010"
 	help
 	  Select this to enable a debug UART using the pl01x driver with the
 	  PL010 UART type. You will need to provide parameters to make this
 	  work. The driver will be available until the real driver model
 	  serial is running.
 config DEBUG_UART_PL011
 	bool "pl011"
 	help
 	  Select this to enable a debug UART using the pl01x driver with the
 	  PL011 UART type. You will need to provide parameters to make this
 	  work. The driver will be available until the real driver model
 	  serial is running.
 config DEBUG_UART_PIC32
 	bool "Microchip PIC32"
 	depends on PIC32_SERIAL
 	help
 	  Select this to enable a debug UART using the serial_pic32 driver. You
 	  will need to provide parameters to make this work. The driver will
 	  be available until the real driver model serial is running.
 config DEBUG_UART_MXC
 	bool "IMX Serial port"
 	depends on MXC_UART
 	help
 	  Select this to enable a debug UART using the serial_mxc driver. You
 	  will need to provide parameters to make this work. The driver will
 	  be available until the real driver model serial is running.
 config DEBUG_UART_UNIPHIER
 	bool "UniPhier on-chip UART"
 	depends on ARCH_UNIPHIER
 	help
 	  Select this to enable a debug UART using the UniPhier on-chip UART.
 	  You will need to provide DEBUG_UART_BASE to make this work.  The
 	  driver will be available until the real driver-model serial is
 	  running.
 config DEBUG_UART_OMAP
 	bool "OMAP uart"
 	help
 	  Select this to enable a debug UART using the omap ns16550 driver.
 	  You will need to provide parameters to make this work. The driver
 	  will be available until the real driver model serial is running.
 endchoice
 config DEBUG_UART_BASE
 	hex "Base address of UART"
 	depends on DEBUG_UART
 	help
 	  This is the base address of your UART for memory-mapped UARTs.
 	  A default should be provided by your board, but if not you will need
 	  to use the correct value here.
 config DEBUG_UART_CLOCK
 	int "UART input clock"
 	depends on DEBUG_UART
 	help
 	  The UART input clock determines the speed of the internal UART
 	  circuitry. The baud rate is derived from this by dividing the input
 	  clock down.
 	  A default should be provided by your board, but if not you will need
 	  to use the correct value here.
 config DEBUG_UART_SHIFT
 	int "UART register shift"
 	depends on DEBUG_UART
 	default 0 if DEBUG_UART
 	help
 	  Some UARTs (notably ns16550) support different register layouts
 	  where the registers are spaced either as bytes, words or some other
 	  value. Use this value to specify the shift to use, where 0=byte
 	  registers, 2=32-bit word registers, etc.
 config DEBUG_UART_BOARD_INIT
 	bool "Enable board-specific debug UART init"
 	depends on DEBUG_UART
 	help
 	  Some boards need to set things up before the debug UART can be used.
 	  On these boards a call to debug_uart_init() is insufficient. When
 	  this option is enabled, the function board_debug_uart_init() will
 	  be called when debug_uart_init() is called. You can put any code
 	  here that is needed to set up the UART ready for use, such as set
 	  pin multiplexing or enable clocks.
 config DEBUG_UART_ANNOUNCE
 	bool "Show a message when the debug UART starts up"
 	depends on DEBUG_UART
 	help
 	  Enable this option to show a message when the debug UART is ready
 	  for use. You will see a message like "<debug_uart> " as soon as
 	  U-Boot has the UART ready for use (i.e. your code calls
 	  debug_uart_init()). This can be useful just as a check that
 	  everything is working.
 config DEBUG_UART_SKIP_INIT
 	bool "Skip UART initialization"
 	help
 	  Select this if the UART you want to use for debug output is already
 	  initialized by the time U-Boot starts its execution.
 config ALTERA_JTAG_UART
 	bool "Altera JTAG UART support"
 	depends on DM_SERIAL
 	help
 	  Select this to enable an JTAG UART for Altera devices.The JTAG UART
 	  core implements a method to communicate serial character streams
 	  between a host PC and a Qsys system on an Altera FPGA. Please find
 	  details on the "Embedded Peripherals IP User Guide" of Altera.
 config ALTERA_JTAG_UART_BYPASS
 	bool "Bypass output when no connection"
 	depends on ALTERA_JTAG_UART
 	help
 	  Bypass console output and keep going even if there is no JTAG
 	  terminal connection with the host. The console output will resume
 	  once the JTAG terminal is connected. Without the bypass, the console
 	  output will wait forever until a JTAG terminal is connected. If you
 	  not are sure, say Y.
 config ALTERA_UART
 	bool "Altera UART support"
 	depends on DM_SERIAL
 	help
 	  Select this to enable an UART for Altera devices. Please find
 	  details on the "Embedded Peripherals IP User Guide" of Altera.
 config AR933X_UART
 	bool "QCA/Atheros ar933x UART support"
 	depends on DM_SERIAL && SOC_AR933X
 	help
 	  Select this to enable UART support for QCA/Atheros ar933x
 	  devices. This driver uses driver model and requires a device
 	  tree binding to operate, please refer to the document at
 	  doc/device-tree-bindings/serial/qca,ar9330-uart.txt.
 config ATMEL_USART
 	bool "Atmel USART support"
 	help
 	  Select this to enable USART support for Atmel SoCs. It can be
 	  configured in the device tree, and input clock frequency can
 	  be got from the clk node.
 config BCM283X_MU_SERIAL
 	bool "Support for BCM283x Mini-UART"
 	depends on DM_SERIAL && ARCH_BCM283X
 	default y
 	help
 	  Select this to enable Mini-UART support on BCM283X family of SoCs.
+config BCM283X_PL011_SERIAL
+	bool "Support for BCM283x PL011 UART"
+	depends on PL01X_SERIAL && ARCH_BCM283X
+	default y
+	help
+	  Select this to enable an overriding PL011 driver for BCM283X SoCs
+	  that supports automatic disable, so that it only gets used when
+	  the UART is actually muxed.
 config BCM6345_SERIAL
 	bool "Support for BCM6345 UART"
 	depends on DM_SERIAL && ARCH_BMIPS
 	help
 	  Select this to enable UART on BCM6345 SoCs.
 config FSL_LPUART
 	bool "Freescale LPUART support"
 	help
 	  Select this to enable a Low Power UART for Freescale VF610 and
 	  QorIQ Layerscape devices.
 config MVEBU_A3700_UART
 	bool "UART support for Armada 3700"
 	default n
 	help
 	  Choose this option to add support for UART driver on the Marvell
 	  Armada 3700 SoC. The base address is configured via DT.
 config MXC_UART
 	bool "IMX serial port support"
 	depends on MX5 || MX6
 	help
 	  If you have a machine based on a Motorola IMX CPU you
 	  can enable its onboard serial port by enabling this option.
 config NULLDEV_SERIAL
 	bool "Null serial device"
 	help
 	  Select this to enable null serial device support. A null serial
 	  device merely acts as a placeholder for a serial device and does
 	  nothing for all it's operation.
 config PIC32_SERIAL
 	bool "Support for Microchip PIC32 on-chip UART"
 	depends on DM_SERIAL && MACH_PIC32
 	default y
 	help
 	  Support for the UART found on Microchip PIC32 SoC's.
 config SYS_NS16550
 	bool "NS16550 UART or compatible"
 	help
 	  Support NS16550 UART or compatible. This can be enabled in the
 	  device tree with the correct input clock frequency. If the input
 	  clock frequency is not defined in the device tree, the macro
 	  CONFIG_SYS_NS16550_CLK defined in a legacy board header file will
 	  be used. It can be a constant or a function to get clock, eg,
 	  get_serial_clock().
 config INTEL_MID_SERIAL
 	bool "Intel MID platform UART support"
 	depends on DM_SERIAL && OF_CONTROL
 	depends on INTEL_MID
 	select SYS_NS16550
 	help
 	  Select this to enable a UART for Intel MID platforms.
 	  This uses the ns16550 driver as a library.
 config PL010_SERIAL
 	bool "ARM PL010 driver"
 	depends on !DM_SERIAL
 	help
 	  Select this to enable a UART for platforms using PL010.
 config PL011_SERIAL
 	bool "ARM PL011 driver"
 	depends on !DM_SERIAL
 	help
 	  Select this to enable a UART for platforms using PL011.
 config PL01X_SERIAL
 	bool "ARM PL010 and PL011 driver"
 	depends on DM_SERIAL
 	help
 	  Select this to enable a UART for platforms using PL010 or PL011.
 config ROCKCHIP_SERIAL
 	bool "Rockchip on-chip UART support"
 	depends on DM_SERIAL && SPL_OF_PLATDATA
 	help
 	  Select this to enable a debug UART for Rockchip devices when using
 	  CONFIG_SPL_OF_PLATDATA (i.e. a compiled-in device tree replacemenmt).
 	  This uses the ns16550 driver, converting the platdata from of-platdata
 	  to the ns16550 format.
 config SANDBOX_SERIAL
 	bool "Sandbox UART support"
 	depends on SANDBOX
 	help
 	  Select this to enable a seral UART for sandbox. This is required to
 	  operate correctly, otherwise you will see no serial output from
 	  sandbox. The emulated UART will display to the console and console
 	  input will be fed into the UART. This allows you to interact with
 	  U-Boot.
 	  The operation of the console is controlled by the -t command-line
 	  flag. In raw mode, U-Boot sees all characters from the terminal
 	  before they are processed, including Ctrl-C. In cooked mode, Ctrl-C
 	  is processed by the terminal, and terminates U-Boot. Valid options
 	  are:
 	     -t raw-with-sigs	Raw mode, Ctrl-C will terminate U-Boot
 	     -t raw		Raw mode, Ctrl-C is processed by U-Boot
 	     -t cooked		Cooked mode, Ctrl-C terminates
 config SCIF_CONSOLE
 	bool "Renesas SCIF UART support"
 	depends on SH || ARCH_RMOBILE
 	help
 	  Select this to enable Renesas SCIF UART. To operate serial ports
 	  on systems with RCar or SH SoCs, say Y to this option. If unsure,
 	  say N.
 config UNIPHIER_SERIAL
 	bool "Support for UniPhier on-chip UART"
 	depends on ARCH_UNIPHIER
 	default y
 	help
 	  If you have a UniPhier based board and want to use the on-chip
 	  serial ports, say Y to this option. If unsure, say N.
 config XILINX_UARTLITE
 	bool "Xilinx Uarlite support"
 	depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || 4xx)
 	help
 	  If you have a Xilinx based board and want to use the uartlite
 	  serial ports, say Y to this option. If unsure, say N.
 config MESON_SERIAL
 	bool "Support for Amlogic Meson UART"
 	depends on DM_SERIAL && ARCH_MESON
 	help
 	  If you have an Amlogic Meson based board and want to use the on-chip
 	  serial ports, say Y to this option. If unsure, say N.
 config MSM_SERIAL
 	bool "Qualcomm on-chip UART"
 	depends on DM_SERIAL
 	help
 	  Support Data Mover UART used on Qualcomm Snapdragon SoCs.
 	  It should support all Qualcomm devices with UARTDM version 1.4,
 	  for example APQ8016 and MSM8916.
 	  Single baudrate is supported in current implementation (115200).
 config PXA_SERIAL
 	bool "PXA serial port support"
 	help
 	  If you have a machine based on a Marvell XScale PXA2xx CPU you
 	  can enable its onboard serial ports by enabling this option.
 config STI_ASC_SERIAL
 	bool "STMicroelectronics on-chip UART"
 	depends on DM_SERIAL && ARCH_STI
 	help
 	  Select this to enable Asynchronous Serial Controller available
 	  on STiH410 SoC. This is a basic implementation,  it supports
 	  following baudrate 9600, 19200, 38400, 57600 and 115200.
 config STM32_SERIAL
 	bool "STMicroelectronics STM32 SoCs on-chip UART"
 	depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7)
 	help
 	  If you have a machine based on a STM32 F4, F7 or H7 SoC you can
 	  enable its onboard serial ports, say Y to this option.
 	  If unsure, say N.
 config ZYNQ_SERIAL
 	bool "Cadence (Xilinx Zynq) UART support"
 	depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
 	help
 	  This driver supports the Cadence UART. It is found e.g. in Xilinx
 	  Zynq/ZynqMP.
 config MPC8XX_CONS
 	bool "Console driver for MPC8XX"
 	depends on 8xx
 	default y
 choice
 	prompt "Console port"
 	default 8xx_CONS_SMC1
 	depends on MPC8XX_CONS
 	help
 	  Depending on board, select one serial port
 	  (CONFIG_8xx_CONS_SMC1 or CONFIG_8xx_CONS_SMC2)
 config 8xx_CONS_SMC1
 	bool "SMC1"
 config 8xx_CONS_SMC2
 	bool "SMC2"
 endchoice
 config SYS_SMC_RXBUFLEN
 	int "Console Rx buffer length"
 	depends on MPC8XX_CONS
 	default 1
 	help
 	  With CONFIG_SYS_SMC_RXBUFLEN it is possible to define
 	  the maximum receive buffer length for the SMC.
 	  This option is actual only for 8xx possible.
 	  If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE
 	  must be defined, to setup the maximum idle timeout for
 	  the SMC.
 config SYS_MAXIDLE
 	int "maximum idle timeout"
 	depends on MPC8XX_CONS
 	default 0
 config SYS_BRGCLK_PRESCALE
 	int "BRG Clock Prescale"
 	depends on MPC8XX_CONS
 	default 1
 config SYS_SDSR
 	hex "SDSR Value"
 	depends on MPC8XX_CONS
 	default 0x83
 config SYS_SDMR
 	hex "SDMR Value"
 	depends on MPC8XX_CONS
 	default 0
 endmenu

drivers/serial/Makefile

Diff comments View file @ 6001985

 #
 # (C) Copyright 2006-2009
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 ifdef CONFIG_DM_SERIAL
 obj-$(CONFIG_$(SPL_TPL_)DM_SERIAL) += serial-uclass.o
 obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
 else
 obj-y += serial.o
 obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
 obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
 obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
 endif
 obj-$(CONFIG_ALTERA_UART) += altera_uart.o
 obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
 obj-$(CONFIG_AR933X_UART) += serial_ar933x.o
 obj-$(CONFIG_ARM_DCC) += arm_dcc.o
 obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
 obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o
 obj-$(CONFIG_EFI_APP) += serial_efi.o
 obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
 obj-$(CONFIG_MCFUART) += mcfuart.o
 obj-$(CONFIG_SYS_NS16550) += ns16550.o
 obj-$(CONFIG_S5P) += serial_s5p.o
 obj-$(CONFIG_MXC_UART) += serial_mxc.o
 obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
 obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
 obj-$(CONFIG_INTEL_MID_SERIAL) += serial_intel_mid.o
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
 endif
 obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
 obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
 obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
 obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
 obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
 obj-$(CONFIG_FSL_LINFLEXUART) += serial_linflexuart.o
 obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
 obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
 obj-$(CONFIG_STI_ASC_SERIAL) += serial_sti_asc.o
 obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
 obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
 obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o
+obj-$(CONFIG_BCM283X_PL011_SERIAL) += serial_bcm283x_pl011.o
 obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
 obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
 obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o
 obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o
 endif

drivers/serial/serial_bcm283x_pl011.c

Diff comments View file @ 6001985

File was created	1	/*
	2	* Copyright (c) 2018 Alexander Graf <agraf@suse.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <dm.h>
	9	#include <asm/gpio.h>
	10	#include <dm/pinctrl.h>
	11	#include <dm/platform_data/serial_pl01x.h>
	12	#include "serial_pl01x_internal.h"
	13
	14	/*
	15	* Check if this serial device is muxed
	16	*
	17	* The serial device will only work properly if it has been muxed to the serial
	18	* pins by firmware. Check whether that happened here.
	19	*
	20	* @return true if serial device is muxed, false if not
	21	*/
	22	static bool bcm283x_is_serial_muxed(void)
	23	{
	24	int serial_gpio = 15;
	25	struct udevice *dev;
	26
	27	if (uclass_first_device(UCLASS_PINCTRL, &dev) \|\| !dev)
	28	return false;
	29
	30	if (pinctrl_get_gpio_mux(dev, 0, serial_gpio) != BCM2835_GPIO_ALT0)
	31	return false;
	32
	33	return true;
	34	}
	35
	36	static int bcm283x_pl011_serial_ofdata_to_platdata(struct udevice *dev)
	37	{
	38	struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
	39	int ret;
	40
	41	/* Don't spawn the device if it's not muxed */
	42	if (!bcm283x_is_serial_muxed())
	43	return -ENODEV;
	44
	45	ret = pl01x_serial_ofdata_to_platdata(dev);
	46	if (ret)
	47	return ret;
	48
	49	/*
	50	* TODO: Reinitialization doesn't always work for now, just skip
	51	* init always - we know we're already initialized
	52	*/
	53	plat->skip_init = true;
	54
	55	return 0;
	56	}
	57
	58	static const struct udevice_id bcm283x_pl011_serial_id[] = {
	59	{.compatible = "brcm,bcm2835-pl011", .data = TYPE_PL011},
	60	{}
	61	};
	62
	63	U_BOOT_DRIVER(bcm283x_pl011_uart) = {
	64	.name = "bcm283x_pl011",
	65	.id = UCLASS_SERIAL,
	66	.of_match = of_match_ptr(bcm283x_pl011_serial_id),
	67	.ofdata_to_platdata = of_match_ptr(bcm283x_pl011_serial_ofdata_to_platdata),
	68	.platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
	69	.probe = pl01x_serial_probe,
	70	.ops = &pl01x_serial_ops,
	71	.flags = DM_FLAG_PRE_RELOC,
	72	.priv_auto_alloc_size = sizeof(struct pl01x_priv),
	73	};
	74

drivers/serial/serial_pl01x.c

Diff comments View file @ 6001985

 /*
  * (C) Copyright 2000
  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
  *
  * (C) Copyright 2004
  * ARM Ltd.
  * Philippe Robin, <philippe.robin@arm.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
 #include <watchdog.h>
 #include <asm/io.h>
 #include <serial.h>
 #include <dm/platform_data/serial_pl01x.h>
 #include <linux/compiler.h>
 #include "serial_pl01x_internal.h"
 DECLARE_GLOBAL_DATA_PTR;
 #ifndef CONFIG_DM_SERIAL
 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
 static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
 static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
 #endif
 static int pl01x_putc(struct pl01x_regs *regs, char c)
 {
 	/* Wait until there is space in the FIFO */
 	if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
 		return -EAGAIN;
 	/* Send the character */
 	writel(c, &regs->dr);
 	return 0;
 }
 static int pl01x_getc(struct pl01x_regs *regs)
 {
 	unsigned int data;
 	/* Wait until there is data in the FIFO */
 	if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
 		return -EAGAIN;
 	data = readl(&regs->dr);
 	/* Check for an error flag */
 	if (data & 0xFFFFFF00) {
 		/* Clear the error */
 		writel(0xFFFFFFFF, &regs->ecr);
 		return -1;
 	}
 	return (int) data;
 }
 static int pl01x_tstc(struct pl01x_regs *regs)
 {
 	WATCHDOG_RESET();
 	return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
 }
 static int pl01x_generic_serial_init(struct pl01x_regs *regs,
 				     enum pl01x_type type)
 {
 	switch (type) {
 	case TYPE_PL010:
 		/* disable everything */
 		writel(0, &regs->pl010_cr);
 		break;
 	case TYPE_PL011:
 		/* disable everything */
 		writel(0, &regs->pl011_cr);
 		break;
 	default:
 		return -EINVAL;
 	}
 	return 0;
 }
 static int pl011_set_line_control(struct pl01x_regs *regs)
 {
 	unsigned int lcr;
 	/*
 	 * Internal update of baud rate register require line
 	 * control register write
 	 */
 	lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
 	writel(lcr, &regs->pl011_lcrh);
 	return 0;
 }
 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
 				int clock, int baudrate)
 {
 	switch (type) {
 	case TYPE_PL010: {
 		unsigned int divisor;
 		/* disable everything */
 		writel(0, &regs->pl010_cr);
 		switch (baudrate) {
 		case 9600:
 			divisor = UART_PL010_BAUD_9600;
 			break;
 		case 19200:
 			divisor = UART_PL010_BAUD_19200;
 			break;
 		case 38400:
 			divisor = UART_PL010_BAUD_38400;
 			break;
 		case 57600:
 			divisor = UART_PL010_BAUD_57600;
 			break;
 		case 115200:
 			divisor = UART_PL010_BAUD_115200;
 			break;
 		default:
 			divisor = UART_PL010_BAUD_38400;
 		}
 		writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
 		writel(divisor & 0xff, &regs->pl010_lcrl);
 		/*
 		 * Set line control for the PL010 to be 8 bits, 1 stop bit,
 		 * no parity, fifo enabled
 		 */
 		writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
 		       &regs->pl010_lcrh);
 		/* Finally, enable the UART */
 		writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
 		break;
 	}
 	case TYPE_PL011: {
 		unsigned int temp;
 		unsigned int divider;
 		unsigned int remainder;
 		unsigned int fraction;
 		/*
 		* Set baud rate
 		*
 		* IBRD = UART_CLK / (16 * BAUD_RATE)
 		* FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
 		*		/ (16 * BAUD_RATE))
 		*/
 		temp = 16 * baudrate;
 		divider = clock / temp;
 		remainder = clock % temp;
 		temp = (8 * remainder) / baudrate;
 		fraction = (temp >> 1) + (temp & 1);
 		writel(divider, &regs->pl011_ibrd);
 		writel(fraction, &regs->pl011_fbrd);
 		pl011_set_line_control(regs);
 		/* Finally, enable the UART */
 		writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
 		       UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
 		break;
 	}
 	default:
 		return -EINVAL;
 	}
 	return 0;
 }
 #ifndef CONFIG_DM_SERIAL
 static void pl01x_serial_init_baud(int baudrate)
 {
 	int clock = 0;
 #if defined(CONFIG_PL010_SERIAL)
 	pl01x_type = TYPE_PL010;
 #elif defined(CONFIG_PL011_SERIAL)
 	pl01x_type = TYPE_PL011;
 	clock = CONFIG_PL011_CLOCK;
 #endif
 	base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
 	pl01x_generic_serial_init(base_regs, pl01x_type);
 	pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
 }
 /*
  * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
  * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
  * Versatile PB has four UARTs.
  */
 int pl01x_serial_init(void)
 {
 	pl01x_serial_init_baud(CONFIG_BAUDRATE);
 	return 0;
 }
 static void pl01x_serial_putc(const char c)
 {
 	if (c == '\n')
 		while (pl01x_putc(base_regs, '\r') == -EAGAIN);
 	while (pl01x_putc(base_regs, c) == -EAGAIN);
 }
 static int pl01x_serial_getc(void)
 {
 	while (1) {
 		int ch = pl01x_getc(base_regs);
 		if (ch == -EAGAIN) {
 			WATCHDOG_RESET();
 			continue;
 		}
 		return ch;
 	}
 }
 static int pl01x_serial_tstc(void)
 {
 	return pl01x_tstc(base_regs);
 }
 static void pl01x_serial_setbrg(void)
 {
 	/*
 	 * Flush FIFO and wait for non-busy before changing baudrate to avoid
 	 * crap in console
 	 */
 	while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
 		WATCHDOG_RESET();
 	while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
 		WATCHDOG_RESET();
 	pl01x_serial_init_baud(gd->baudrate);
 }
 static struct serial_device pl01x_serial_drv = {
 	.name	= "pl01x_serial",
 	.start	= pl01x_serial_init,
 	.stop	= NULL,
 	.setbrg	= pl01x_serial_setbrg,
 	.putc	= pl01x_serial_putc,
 	.puts	= default_serial_puts,
 	.getc	= pl01x_serial_getc,
 	.tstc	= pl01x_serial_tstc,
 };
 void pl01x_serial_initialize(void)
 {
 	serial_register(&pl01x_serial_drv);
 }
 __weak struct serial_device *default_serial_console(void)
 {
 	return &pl01x_serial_drv;
 }
 #endif /* nCONFIG_DM_SERIAL */
 #ifdef CONFIG_DM_SERIAL
-struct pl01x_priv {
-	struct pl01x_regs *regs;
-	enum pl01x_type type;
-};
 static int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
 {
 	struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
 	struct pl01x_priv *priv = dev_get_priv(dev);
 	if (!plat->skip_init) {
 		pl01x_generic_setbrg(priv->regs, priv->type, plat->clock,
 				     baudrate);
 	}
 	return 0;
 }
-static int pl01x_serial_probe(struct udevice *dev)
+int pl01x_serial_probe(struct udevice *dev)
 {
 	struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
 	struct pl01x_priv *priv = dev_get_priv(dev);
 	priv->regs = (struct pl01x_regs *)plat->base;
 	priv->type = plat->type;
 	if (!plat->skip_init)
 		return pl01x_generic_serial_init(priv->regs, priv->type);
 	else
 		return 0;
 }
 static int pl01x_serial_getc(struct udevice *dev)
 {
 	struct pl01x_priv *priv = dev_get_priv(dev);
 	return pl01x_getc(priv->regs);
 }
 static int pl01x_serial_putc(struct udevice *dev, const char ch)
 {
 	struct pl01x_priv *priv = dev_get_priv(dev);
 	return pl01x_putc(priv->regs, ch);
 }
 static int pl01x_serial_pending(struct udevice *dev, bool input)
 {
 	struct pl01x_priv *priv = dev_get_priv(dev);
 	unsigned int fr = readl(&priv->regs->fr);
 	if (input)
 		return pl01x_tstc(priv->regs);
 	else
 		return fr & UART_PL01x_FR_TXFF ? 0 : 1;
 }
-static const struct dm_serial_ops pl01x_serial_ops = {
+const struct dm_serial_ops pl01x_serial_ops = {
 	.putc = pl01x_serial_putc,
 	.pending = pl01x_serial_pending,
 	.getc = pl01x_serial_getc,
 	.setbrg = pl01x_serial_setbrg,
 };
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct udevice_id pl01x_serial_id[] ={
 	{.compatible = "arm,pl011", .data = TYPE_PL011},
 	{.compatible = "arm,pl010", .data = TYPE_PL010},
 	{}
 };
-static int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
+int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
 {
 	struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
 	fdt_addr_t addr;
 	addr = devfdt_get_addr(dev);
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 	plat->base = addr;
 	plat->clock = dev_read_u32_default(dev, "clock", 1);
 	plat->type = dev_get_driver_data(dev);
 	plat->skip_init = dev_read_bool(dev, "skip-init");
 	return 0;
 }
 #endif
 U_BOOT_DRIVER(serial_pl01x) = {
 	.name	= "serial_pl01x",
 	.id	= UCLASS_SERIAL,
 	.of_match = of_match_ptr(pl01x_serial_id),
 	.ofdata_to_platdata = of_match_ptr(pl01x_serial_ofdata_to_platdata),
 	.platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
 	.probe = pl01x_serial_probe,
 	.ops	= &pl01x_serial_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 	.priv_auto_alloc_size = sizeof(struct pl01x_priv),
 };
 #endif
 #if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
 #include <debug_uart.h>
 static void _debug_uart_init(void)
 {
 #ifndef CONFIG_DEBUG_UART_SKIP_INIT
 	struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
 	enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ?
 				TYPE_PL011 : TYPE_PL010;
 	pl01x_generic_serial_init(regs, type);
 	pl01x_generic_setbrg(regs, type,
 			     CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
 #endif
 }
 static inline void _debug_uart_putc(int ch)
 {
 	struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
 	pl01x_putc(regs, ch);
 }
 DEBUG_UART_FUNCS
 #endif

drivers/serial/serial_pl01x_internal.h

Diff comments View file @ 6001985

1	/*	1	/*
2	* (C) Copyright 2003, 2004	2	* (C) Copyright 2003, 2004
3	* ARM Ltd.	3	* ARM Ltd.
4	* Philippe Robin, <philippe.robin@arm.com>	4	* Philippe Robin, <philippe.robin@arm.com>
5	*	5	*
6	* SPDX-License-Identifier: GPL-2.0+	6	* SPDX-License-Identifier: GPL-2.0+
7	*/	7	*/
8		8
9	/*	9	/*
10	* ARM PrimeCell UART's (PL010 & PL011)	10	* ARM PrimeCell UART's (PL010 & PL011)
11	* ------------------------------------	11	* ------------------------------------
12	*	12	*
13	* Definitions common to both PL010 & PL011	13	* Definitions common to both PL010 & PL011
14	*	14	*
15	*/	15	*/
16		16
17	#ifndef __ASSEMBLY__	17	#ifndef __ASSEMBLY__
18	/*	18	/*
19	* We can use a combined structure for PL010 and PL011, because they overlap	19	* We can use a combined structure for PL010 and PL011, because they overlap
20	* only in common registers.	20	* only in common registers.
21	*/	21	*/
22	struct pl01x_regs {	22	struct pl01x_regs {
23	u32 dr; /* 0x00 Data register */	23	u32 dr; /* 0x00 Data register */
24	u32 ecr; /* 0x04 Error clear register (Write) */	24	u32 ecr; /* 0x04 Error clear register (Write) */
25	u32 pl010_lcrh; /* 0x08 Line control register, high byte */	25	u32 pl010_lcrh; /* 0x08 Line control register, high byte */
26	u32 pl010_lcrm; /* 0x0C Line control register, middle byte */	26	u32 pl010_lcrm; /* 0x0C Line control register, middle byte */
27	u32 pl010_lcrl; /* 0x10 Line control register, low byte */	27	u32 pl010_lcrl; /* 0x10 Line control register, low byte */
28	u32 pl010_cr; /* 0x14 Control register */	28	u32 pl010_cr; /* 0x14 Control register */
29	u32 fr; /* 0x18 Flag register (Read only) */	29	u32 fr; /* 0x18 Flag register (Read only) */
30	#ifdef CONFIG_PL011_SERIAL_RLCR	30	#ifdef CONFIG_PL011_SERIAL_RLCR
31	u32 pl011_rlcr; /* 0x1c Receive line control register */	31	u32 pl011_rlcr; /* 0x1c Receive line control register */
32	#else	32	#else
33	u32 reserved;	33	u32 reserved;
34	#endif	34	#endif
35	u32 ilpr; /* 0x20 IrDA low-power counter register */	35	u32 ilpr; /* 0x20 IrDA low-power counter register */
36	u32 pl011_ibrd; /* 0x24 Integer baud rate register */	36	u32 pl011_ibrd; /* 0x24 Integer baud rate register */
37	u32 pl011_fbrd; /* 0x28 Fractional baud rate register */	37	u32 pl011_fbrd; /* 0x28 Fractional baud rate register */
38	u32 pl011_lcrh; /* 0x2C Line control register */	38	u32 pl011_lcrh; /* 0x2C Line control register */
39	u32 pl011_cr; /* 0x30 Control register */	39	u32 pl011_cr; /* 0x30 Control register */
40	};	40	};
41	#endif	41
		42	#ifdef CONFIG_DM_SERIAL
		43
		44	int pl01x_serial_ofdata_to_platdata(struct udevice *dev);
		45	int pl01x_serial_probe(struct udevice *dev);
		46	extern const struct dm_serial_ops pl01x_serial_ops;
		47
		48	struct pl01x_priv {
		49	struct pl01x_regs *regs;
		50	enum pl01x_type type;
		51	};
		52
		53	#endif /* CONFIG_DM_SERIAL */
		54	#endif /* !__ASSEMBLY__ */
42		55
43	#define UART_PL01x_RSR_OE 0x08	56	#define UART_PL01x_RSR_OE 0x08
44	#define UART_PL01x_RSR_BE 0x04	57	#define UART_PL01x_RSR_BE 0x04
45	#define UART_PL01x_RSR_PE 0x02	58	#define UART_PL01x_RSR_PE 0x02
46	#define UART_PL01x_RSR_FE 0x01	59	#define UART_PL01x_RSR_FE 0x01
47		60
48	#define UART_PL01x_FR_TXFE 0x80	61	#define UART_PL01x_FR_TXFE 0x80
49	#define UART_PL01x_FR_RXFF 0x40	62	#define UART_PL01x_FR_RXFF 0x40
50	#define UART_PL01x_FR_TXFF 0x20	63	#define UART_PL01x_FR_TXFF 0x20
51	#define UART_PL01x_FR_RXFE 0x10	64	#define UART_PL01x_FR_RXFE 0x10
52	#define UART_PL01x_FR_BUSY 0x08	65	#define UART_PL01x_FR_BUSY 0x08
53	#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)	66	#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)
54		67
55	/*	68	/*
56	* PL010 definitions	69	* PL010 definitions
57	*	70	*
58	*/	71	*/
59	#define UART_PL010_CR_LPE (1 << 7)	72	#define UART_PL010_CR_LPE (1 << 7)
60	#define UART_PL010_CR_RTIE (1 << 6)	73	#define UART_PL010_CR_RTIE (1 << 6)
61	#define UART_PL010_CR_TIE (1 << 5)	74	#define UART_PL010_CR_TIE (1 << 5)
62	#define UART_PL010_CR_RIE (1 << 4)	75	#define UART_PL010_CR_RIE (1 << 4)
63	#define UART_PL010_CR_MSIE (1 << 3)	76	#define UART_PL010_CR_MSIE (1 << 3)
64	#define UART_PL010_CR_IIRLP (1 << 2)	77	#define UART_PL010_CR_IIRLP (1 << 2)
65	#define UART_PL010_CR_SIREN (1 << 1)	78	#define UART_PL010_CR_SIREN (1 << 1)
66	#define UART_PL010_CR_UARTEN (1 << 0)	79	#define UART_PL010_CR_UARTEN (1 << 0)
67		80
68	#define UART_PL010_LCRH_WLEN_8 (3 << 5)	81	#define UART_PL010_LCRH_WLEN_8 (3 << 5)
69	#define UART_PL010_LCRH_WLEN_7 (2 << 5)	82	#define UART_PL010_LCRH_WLEN_7 (2 << 5)
70	#define UART_PL010_LCRH_WLEN_6 (1 << 5)	83	#define UART_PL010_LCRH_WLEN_6 (1 << 5)
71	#define UART_PL010_LCRH_WLEN_5 (0 << 5)	84	#define UART_PL010_LCRH_WLEN_5 (0 << 5)
72	#define UART_PL010_LCRH_FEN (1 << 4)	85	#define UART_PL010_LCRH_FEN (1 << 4)
73	#define UART_PL010_LCRH_STP2 (1 << 3)	86	#define UART_PL010_LCRH_STP2 (1 << 3)
74	#define UART_PL010_LCRH_EPS (1 << 2)	87	#define UART_PL010_LCRH_EPS (1 << 2)
75	#define UART_PL010_LCRH_PEN (1 << 1)	88	#define UART_PL010_LCRH_PEN (1 << 1)
76	#define UART_PL010_LCRH_BRK (1 << 0)	89	#define UART_PL010_LCRH_BRK (1 << 0)
77		90
78		91
79	#define UART_PL010_BAUD_460800 1	92	#define UART_PL010_BAUD_460800 1
80	#define UART_PL010_BAUD_230400 3	93	#define UART_PL010_BAUD_230400 3
81	#define UART_PL010_BAUD_115200 7	94	#define UART_PL010_BAUD_115200 7
82	#define UART_PL010_BAUD_57600 15	95	#define UART_PL010_BAUD_57600 15
83	#define UART_PL010_BAUD_38400 23	96	#define UART_PL010_BAUD_38400 23
84	#define UART_PL010_BAUD_19200 47	97	#define UART_PL010_BAUD_19200 47
85	#define UART_PL010_BAUD_14400 63	98	#define UART_PL010_BAUD_14400 63
86	#define UART_PL010_BAUD_9600 95	99	#define UART_PL010_BAUD_9600 95
87	#define UART_PL010_BAUD_4800 191	100	#define UART_PL010_BAUD_4800 191
88	#define UART_PL010_BAUD_2400 383	101	#define UART_PL010_BAUD_2400 383
89	#define UART_PL010_BAUD_1200 767	102	#define UART_PL010_BAUD_1200 767
90	/*	103	/*
91	* PL011 definitions	104	* PL011 definitions
92	*	105	*
93	*/	106	*/
94	#define UART_PL011_LCRH_SPS (1 << 7)	107	#define UART_PL011_LCRH_SPS (1 << 7)
95	#define UART_PL011_LCRH_WLEN_8 (3 << 5)	108	#define UART_PL011_LCRH_WLEN_8 (3 << 5)
96	#define UART_PL011_LCRH_WLEN_7 (2 << 5)	109	#define UART_PL011_LCRH_WLEN_7 (2 << 5)
97	#define UART_PL011_LCRH_WLEN_6 (1 << 5)	110	#define UART_PL011_LCRH_WLEN_6 (1 << 5)
98	#define UART_PL011_LCRH_WLEN_5 (0 << 5)	111	#define UART_PL011_LCRH_WLEN_5 (0 << 5)
99	#define UART_PL011_LCRH_FEN (1 << 4)	112	#define UART_PL011_LCRH_FEN (1 << 4)
100	#define UART_PL011_LCRH_STP2 (1 << 3)	113	#define UART_PL011_LCRH_STP2 (1 << 3)
101	#define UART_PL011_LCRH_EPS (1 << 2)	114	#define UART_PL011_LCRH_EPS (1 << 2)
102	#define UART_PL011_LCRH_PEN (1 << 1)	115	#define UART_PL011_LCRH_PEN (1 << 1)
103	#define UART_PL011_LCRH_BRK (1 << 0)	116	#define UART_PL011_LCRH_BRK (1 << 0)
104		117
105	#define UART_PL011_CR_CTSEN (1 << 15)	118	#define UART_PL011_CR_CTSEN (1 << 15)
106	#define UART_PL011_CR_RTSEN (1 << 14)	119	#define UART_PL011_CR_RTSEN (1 << 14)
107	#define UART_PL011_CR_OUT2 (1 << 13)	120	#define UART_PL011_CR_OUT2 (1 << 13)
108	#define UART_PL011_CR_OUT1 (1 << 12)	121	#define UART_PL011_CR_OUT1 (1 << 12)
109	#define UART_PL011_CR_RTS (1 << 11)	122	#define UART_PL011_CR_RTS (1 << 11)
110	#define UART_PL011_CR_DTR (1 << 10)	123	#define UART_PL011_CR_DTR (1 << 10)
111	#define UART_PL011_CR_RXE (1 << 9)	124	#define UART_PL011_CR_RXE (1 << 9)
112	#define UART_PL011_CR_TXE (1 << 8)	125	#define UART_PL011_CR_TXE (1 << 8)
113	#define UART_PL011_CR_LPE (1 << 7)	126	#define UART_PL011_CR_LPE (1 << 7)
114	#define UART_PL011_CR_IIRLP (1 << 2)	127	#define UART_PL011_CR_IIRLP (1 << 2)
115	#define UART_PL011_CR_SIREN (1 << 1)	128	#define UART_PL011_CR_SIREN (1 << 1)
116	#define UART_PL011_CR_UARTEN (1 << 0)	129	#define UART_PL011_CR_UARTEN (1 << 0)
117		130
118	#define UART_PL011_IMSC_OEIM (1 << 10)	131	#define UART_PL011_IMSC_OEIM (1 << 10)
119	#define UART_PL011_IMSC_BEIM (1 << 9)	132	#define UART_PL011_IMSC_BEIM (1 << 9)
120	#define UART_PL011_IMSC_PEIM (1 << 8)	133	#define UART_PL011_IMSC_PEIM (1 << 8)
121	#define UART_PL011_IMSC_FEIM (1 << 7)	134	#define UART_PL011_IMSC_FEIM (1 << 7)
122	#define UART_PL011_IMSC_RTIM (1 << 6)	135	#define UART_PL011_IMSC_RTIM (1 << 6)
123	#define UART_PL011_IMSC_TXIM (1 << 5)	136	#define UART_PL011_IMSC_TXIM (1 << 5)
124	#define UART_PL011_IMSC_RXIM (1 << 4)	137	#define UART_PL011_IMSC_RXIM (1 << 4)
125	#define UART_PL011_IMSC_DSRMIM (1 << 3)	138	#define UART_PL011_IMSC_DSRMIM (1 << 3)
126	#define UART_PL011_IMSC_DCDMIM (1 << 2)	139	#define UART_PL011_IMSC_DCDMIM (1 << 2)
127	#define UART_PL011_IMSC_CTSMIM (1 << 1)	140	#define UART_PL011_IMSC_CTSMIM (1 << 1)
128	#define UART_PL011_IMSC_RIMIM (1 << 0)	141	#define UART_PL011_IMSC_RIMIM (1 << 0)
129		142