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Commit 603058f4ab12af8d6662ddec579089361c060cfc

Authored by Álvaro Fernández Rojas
Committed by Daniel Schwierzeck
1 parent 5e14ce2f33
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

dm: cpu: bmips: add BCM3380 support 

As far as I know BCM3380 has a fixed CPU frequency since I couldn't find its
PLL registers in any documentation.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Showing 1 changed file with 14 additions and 0 deletions Inline Diff

drivers/cpu/bmips_cpu.c
Diff comments   View file @ 603058f
1 /* 1 /*
2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> 2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
3 * 3 *
4 * Derived from linux/arch/mips/bcm63xx/cpu.c: 4 * Derived from linux/arch/mips/bcm63xx/cpu.c:
5 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 5 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
6 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org> 6 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
7 * 7 *
8 * SPDX-License-Identifier: GPL-2.0+ 8 * SPDX-License-Identifier: GPL-2.0+
9 */ 9 */
10 10
11 #include <common.h> 11 #include <common.h>
12 #include <cpu.h> 12 #include <cpu.h>
13 #include <dm.h> 13 #include <dm.h>
14 #include <errno.h> 14 #include <errno.h>
15 #include <asm/io.h> 15 #include <asm/io.h>
16 16
17 DECLARE_GLOBAL_DATA_PTR; 17 DECLARE_GLOBAL_DATA_PTR;
18 18
19 #define REV_CHIPID_SHIFT 16 19 #define REV_CHIPID_SHIFT 16
20 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) 20 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
21 #define REV_LONG_CHIPID_SHIFT 12 21 #define REV_LONG_CHIPID_SHIFT 12
22 #define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT) 22 #define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT)
23 #define REV_REVID_SHIFT 0 23 #define REV_REVID_SHIFT 0
24 #define REV_REVID_MASK (0xff << REV_REVID_SHIFT) 24 #define REV_REVID_MASK (0xff << REV_REVID_SHIFT)
25 25
26 #define REG_BCM6328_OTP 0x62c 26 #define REG_BCM6328_OTP 0x62c
27 #define BCM6328_TP1_DISABLED BIT(9) 27 #define BCM6328_TP1_DISABLED BIT(9)
28 28
29 #define REG_BCM6328_MISC_STRAPBUS 0x1a40 29 #define REG_BCM6328_MISC_STRAPBUS 0x1a40
30 #define STRAPBUS_6328_FCVO_SHIFT 7 30 #define STRAPBUS_6328_FCVO_SHIFT 7
31 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) 31 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
32 32
33 #define REG_BCM6348_PERF_MIPSPLLCFG 0x34 33 #define REG_BCM6348_PERF_MIPSPLLCFG 0x34
34 #define MIPSPLLCFG_6348_M1CPU_SHIFT 6 34 #define MIPSPLLCFG_6348_M1CPU_SHIFT 6
35 #define MIPSPLLCFG_6348_M1CPU_MASK (0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT) 35 #define MIPSPLLCFG_6348_M1CPU_MASK (0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT)
36 #define MIPSPLLCFG_6348_N2_SHIFT 15 36 #define MIPSPLLCFG_6348_N2_SHIFT 15
37 #define MIPSPLLCFG_6348_N2_MASK (0x1F << MIPSPLLCFG_6348_N2_SHIFT) 37 #define MIPSPLLCFG_6348_N2_MASK (0x1F << MIPSPLLCFG_6348_N2_SHIFT)
38 #define MIPSPLLCFG_6348_N1_SHIFT 20 38 #define MIPSPLLCFG_6348_N1_SHIFT 20
39 #define MIPSPLLCFG_6348_N1_MASK (0x7 << MIPSPLLCFG_6348_N1_SHIFT) 39 #define MIPSPLLCFG_6348_N1_MASK (0x7 << MIPSPLLCFG_6348_N1_SHIFT)
40 40
41 #define REG_BCM6358_DDR_DMIPSPLLCFG 0x12b8 41 #define REG_BCM6358_DDR_DMIPSPLLCFG 0x12b8
42 #define DMIPSPLLCFG_6358_M1_SHIFT 0 42 #define DMIPSPLLCFG_6358_M1_SHIFT 0
43 #define DMIPSPLLCFG_6358_M1_MASK (0xff << DMIPSPLLCFG_6358_M1_SHIFT) 43 #define DMIPSPLLCFG_6358_M1_MASK (0xff << DMIPSPLLCFG_6358_M1_SHIFT)
44 #define DMIPSPLLCFG_6358_N1_SHIFT 23 44 #define DMIPSPLLCFG_6358_N1_SHIFT 23
45 #define DMIPSPLLCFG_6358_N1_MASK (0x3f << DMIPSPLLCFG_6358_N1_SHIFT) 45 #define DMIPSPLLCFG_6358_N1_MASK (0x3f << DMIPSPLLCFG_6358_N1_SHIFT)
46 #define DMIPSPLLCFG_6358_N2_SHIFT 29 46 #define DMIPSPLLCFG_6358_N2_SHIFT 29
47 #define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT) 47 #define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
48 48
49 #define REG_BCM63268_MISC_STRAPBUS 0x1814 49 #define REG_BCM63268_MISC_STRAPBUS 0x1814
50 #define STRAPBUS_63268_FCVO_SHIFT 21 50 #define STRAPBUS_63268_FCVO_SHIFT 21
51 #define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT) 51 #define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
52 52
53 struct bmips_cpu_priv; 53 struct bmips_cpu_priv;
54 54
55 struct bmips_cpu_hw { 55 struct bmips_cpu_hw {
56 int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size); 56 int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size);
57 ulong (*get_cpu_freq)(struct bmips_cpu_priv *); 57 ulong (*get_cpu_freq)(struct bmips_cpu_priv *);
58 int (*get_cpu_count)(struct bmips_cpu_priv *); 58 int (*get_cpu_count)(struct bmips_cpu_priv *);
59 }; 59 };
60 60
61 struct bmips_cpu_priv { 61 struct bmips_cpu_priv {
62 void __iomem *regs; 62 void __iomem *regs;
63 const struct bmips_cpu_hw *hw; 63 const struct bmips_cpu_hw *hw;
64 }; 64 };
65 65
66 /* Specific CPU Ops */ 66 /* Specific CPU Ops */
67 static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf, 67 static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
68 int size) 68 int size)
69 { 69 {
70 unsigned short cpu_id; 70 unsigned short cpu_id;
71 unsigned char cpu_rev; 71 unsigned char cpu_rev;
72 u32 val; 72 u32 val;
73 73
74 val = readl_be(priv->regs); 74 val = readl_be(priv->regs);
75 cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; 75 cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
76 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT; 76 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
77 77
78 snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev); 78 snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev);
79 79
80 return 0; 80 return 0;
81 } 81 }
82 82
83 static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf, 83 static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
84 int size) 84 int size)
85 { 85 {
86 unsigned int cpu_id; 86 unsigned int cpu_id;
87 unsigned char cpu_rev; 87 unsigned char cpu_rev;
88 u32 val; 88 u32 val;
89 89
90 val = readl_be(priv->regs); 90 val = readl_be(priv->regs);
91 cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT; 91 cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT;
92 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT; 92 cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
93 93
94 snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev); 94 snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev);
95 95
96 return 0; 96 return 0;
97 } 97 }
98 98
99 static ulong bcm3380_get_cpu_freq(struct bmips_cpu_priv *priv)
100 {
101 return 333000000;
102 }
103
99 static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv) 104 static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
100 { 105 {
101 unsigned int mips_pll_fcvo; 106 unsigned int mips_pll_fcvo;
102 107
103 mips_pll_fcvo = readl_be(priv->regs + REG_BCM6328_MISC_STRAPBUS); 108 mips_pll_fcvo = readl_be(priv->regs + REG_BCM6328_MISC_STRAPBUS);
104 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK) 109 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK)
105 >> STRAPBUS_6328_FCVO_SHIFT; 110 >> STRAPBUS_6328_FCVO_SHIFT;
106 111
107 switch (mips_pll_fcvo) { 112 switch (mips_pll_fcvo) {
108 case 0x12: 113 case 0x12:
109 case 0x14: 114 case 0x14:
110 case 0x19: 115 case 0x19:
111 return 160000000; 116 return 160000000;
112 case 0x1c: 117 case 0x1c:
113 return 192000000; 118 return 192000000;
114 case 0x13: 119 case 0x13:
115 case 0x15: 120 case 0x15:
116 return 200000000; 121 return 200000000;
117 case 0x1a: 122 case 0x1a:
118 return 384000000; 123 return 384000000;
119 case 0x16: 124 case 0x16:
120 return 400000000; 125 return 400000000;
121 default: 126 default:
122 return 320000000; 127 return 320000000;
123 } 128 }
124 } 129 }
125 130
126 static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv) 131 static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv)
127 { 132 {
128 unsigned int tmp, n1, n2, m1; 133 unsigned int tmp, n1, n2, m1;
129 134
130 tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG); 135 tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG);
131 n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT; 136 n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT;
132 n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT; 137 n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT;
133 m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT; 138 m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT;
134 139
135 return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1); 140 return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1);
136 } 141 }
137 142
138 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv) 143 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
139 { 144 {
140 unsigned int tmp, n1, n2, m1; 145 unsigned int tmp, n1, n2, m1;
141 146
142 tmp = readl_be(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG); 147 tmp = readl_be(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG);
143 n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT; 148 n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT;
144 n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT; 149 n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT;
145 m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT; 150 m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT;
146 151
147 return (16 * 1000000 * n1 * n2) / m1; 152 return (16 * 1000000 * n1 * n2) / m1;
148 } 153 }
149 154
150 static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv) 155 static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv)
151 { 156 {
152 unsigned int mips_pll_fcvo; 157 unsigned int mips_pll_fcvo;
153 158
154 mips_pll_fcvo = readl_be(priv->regs + REG_BCM63268_MISC_STRAPBUS); 159 mips_pll_fcvo = readl_be(priv->regs + REG_BCM63268_MISC_STRAPBUS);
155 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK) 160 mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK)
156 >> STRAPBUS_63268_FCVO_SHIFT; 161 >> STRAPBUS_63268_FCVO_SHIFT;
157 162
158 switch (mips_pll_fcvo) { 163 switch (mips_pll_fcvo) {
159 case 0x3: 164 case 0x3:
160 case 0xe: 165 case 0xe:
161 return 320000000; 166 return 320000000;
162 case 0xa: 167 case 0xa:
163 return 333000000; 168 return 333000000;
164 case 0x2: 169 case 0x2:
165 case 0xb: 170 case 0xb:
166 case 0xf: 171 case 0xf:
167 return 400000000; 172 return 400000000;
168 default: 173 default:
169 return 0; 174 return 0;
170 } 175 }
171 } 176 }
172 177
173 static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv) 178 static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
174 { 179 {
175 u32 val = readl_be(priv->regs + REG_BCM6328_OTP); 180 u32 val = readl_be(priv->regs + REG_BCM6328_OTP);
176 181
177 if (val & BCM6328_TP1_DISABLED) 182 if (val & BCM6328_TP1_DISABLED)
178 return 1; 183 return 1;
179 else 184 else
180 return 2; 185 return 2;
181 } 186 }
182 187
183 static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv) 188 static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv)
184 { 189 {
185 return 1; 190 return 1;
186 } 191 }
187 192
188 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv) 193 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
189 { 194 {
190 return 2; 195 return 2;
191 } 196 }
192 197
198 static const struct bmips_cpu_hw bmips_cpu_bcm3380 = {
199 .get_cpu_desc = bmips_short_cpu_desc,
200 .get_cpu_freq = bcm3380_get_cpu_freq,
201 .get_cpu_count = bcm6358_get_cpu_count,
202 };
203
193 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = { 204 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
194 .get_cpu_desc = bmips_long_cpu_desc, 205 .get_cpu_desc = bmips_long_cpu_desc,
195 .get_cpu_freq = bcm6328_get_cpu_freq, 206 .get_cpu_freq = bcm6328_get_cpu_freq,
196 .get_cpu_count = bcm6328_get_cpu_count, 207 .get_cpu_count = bcm6328_get_cpu_count,
197 }; 208 };
198 209
199 static const struct bmips_cpu_hw bmips_cpu_bcm6348 = { 210 static const struct bmips_cpu_hw bmips_cpu_bcm6348 = {
200 .get_cpu_desc = bmips_short_cpu_desc, 211 .get_cpu_desc = bmips_short_cpu_desc,
201 .get_cpu_freq = bcm6348_get_cpu_freq, 212 .get_cpu_freq = bcm6348_get_cpu_freq,
202 .get_cpu_count = bcm6345_get_cpu_count, 213 .get_cpu_count = bcm6345_get_cpu_count,
203 }; 214 };
204 215
205 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = { 216 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
206 .get_cpu_desc = bmips_short_cpu_desc, 217 .get_cpu_desc = bmips_short_cpu_desc,
207 .get_cpu_freq = bcm6358_get_cpu_freq, 218 .get_cpu_freq = bcm6358_get_cpu_freq,
208 .get_cpu_count = bcm6358_get_cpu_count, 219 .get_cpu_count = bcm6358_get_cpu_count,
209 }; 220 };
210 221
211 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = { 222 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
212 .get_cpu_desc = bmips_long_cpu_desc, 223 .get_cpu_desc = bmips_long_cpu_desc,
213 .get_cpu_freq = bcm63268_get_cpu_freq, 224 .get_cpu_freq = bcm63268_get_cpu_freq,
214 .get_cpu_count = bcm6358_get_cpu_count, 225 .get_cpu_count = bcm6358_get_cpu_count,
215 }; 226 };
216 227
217 /* Generic CPU Ops */ 228 /* Generic CPU Ops */
218 static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size) 229 static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size)
219 { 230 {
220 struct bmips_cpu_priv *priv = dev_get_priv(dev); 231 struct bmips_cpu_priv *priv = dev_get_priv(dev);
221 const struct bmips_cpu_hw *hw = priv->hw; 232 const struct bmips_cpu_hw *hw = priv->hw;
222 233
223 return hw->get_cpu_desc(priv, buf, size); 234 return hw->get_cpu_desc(priv, buf, size);
224 } 235 }
225 236
226 static int bmips_cpu_get_info(struct udevice *dev, struct cpu_info *info) 237 static int bmips_cpu_get_info(struct udevice *dev, struct cpu_info *info)
227 { 238 {
228 struct bmips_cpu_priv *priv = dev_get_priv(dev); 239 struct bmips_cpu_priv *priv = dev_get_priv(dev);
229 const struct bmips_cpu_hw *hw = priv->hw; 240 const struct bmips_cpu_hw *hw = priv->hw;
230 241
231 info->cpu_freq = hw->get_cpu_freq(priv); 242 info->cpu_freq = hw->get_cpu_freq(priv);
232 info->features = BIT(CPU_FEAT_L1_CACHE); 243 info->features = BIT(CPU_FEAT_L1_CACHE);
233 info->features |= BIT(CPU_FEAT_MMU); 244 info->features |= BIT(CPU_FEAT_MMU);
234 info->features |= BIT(CPU_FEAT_DEVICE_ID); 245 info->features |= BIT(CPU_FEAT_DEVICE_ID);
235 246
236 return 0; 247 return 0;
237 } 248 }
238 249
239 static int bmips_cpu_get_count(struct udevice *dev) 250 static int bmips_cpu_get_count(struct udevice *dev)
240 { 251 {
241 struct bmips_cpu_priv *priv = dev_get_priv(dev); 252 struct bmips_cpu_priv *priv = dev_get_priv(dev);
242 const struct bmips_cpu_hw *hw = priv->hw; 253 const struct bmips_cpu_hw *hw = priv->hw;
243 254
244 return hw->get_cpu_count(priv); 255 return hw->get_cpu_count(priv);
245 } 256 }
246 257
247 static int bmips_cpu_get_vendor(struct udevice *dev, char *buf, int size) 258 static int bmips_cpu_get_vendor(struct udevice *dev, char *buf, int size)
248 { 259 {
249 snprintf(buf, size, "Broadcom"); 260 snprintf(buf, size, "Broadcom");
250 261
251 return 0; 262 return 0;
252 } 263 }
253 264
254 static const struct cpu_ops bmips_cpu_ops = { 265 static const struct cpu_ops bmips_cpu_ops = {
255 .get_desc = bmips_cpu_get_desc, 266 .get_desc = bmips_cpu_get_desc,
256 .get_info = bmips_cpu_get_info, 267 .get_info = bmips_cpu_get_info,
257 .get_count = bmips_cpu_get_count, 268 .get_count = bmips_cpu_get_count,
258 .get_vendor = bmips_cpu_get_vendor, 269 .get_vendor = bmips_cpu_get_vendor,
259 }; 270 };
260 271
261 /* BMIPS CPU driver */ 272 /* BMIPS CPU driver */
262 int bmips_cpu_bind(struct udevice *dev) 273 int bmips_cpu_bind(struct udevice *dev)
263 { 274 {
264 struct cpu_platdata *plat = dev_get_parent_platdata(dev); 275 struct cpu_platdata *plat = dev_get_parent_platdata(dev);
265 276
266 plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 277 plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
267 "reg", -1); 278 "reg", -1);
268 plat->device_id = read_c0_prid(); 279 plat->device_id = read_c0_prid();
269 280
270 return 0; 281 return 0;
271 } 282 }
272 283
273 int bmips_cpu_probe(struct udevice *dev) 284 int bmips_cpu_probe(struct udevice *dev)
274 { 285 {
275 struct bmips_cpu_priv *priv = dev_get_priv(dev); 286 struct bmips_cpu_priv *priv = dev_get_priv(dev);
276 const struct bmips_cpu_hw *hw = 287 const struct bmips_cpu_hw *hw =
277 (const struct bmips_cpu_hw *)dev_get_driver_data(dev); 288 (const struct bmips_cpu_hw *)dev_get_driver_data(dev);
278 fdt_addr_t addr; 289 fdt_addr_t addr;
279 fdt_size_t size; 290 fdt_size_t size;
280 291
281 addr = dev_get_addr_size_index(dev_get_parent(dev), 0, &size); 292 addr = dev_get_addr_size_index(dev_get_parent(dev), 0, &size);
282 if (addr == FDT_ADDR_T_NONE) 293 if (addr == FDT_ADDR_T_NONE)
283 return -EINVAL; 294 return -EINVAL;
284 295
285 priv->regs = ioremap(addr, size); 296 priv->regs = ioremap(addr, size);
286 priv->hw = hw; 297 priv->hw = hw;
287 298
288 return 0; 299 return 0;
289 } 300 }
290 301
291 static const struct udevice_id bmips_cpu_ids[] = { 302 static const struct udevice_id bmips_cpu_ids[] = {
292 { 303 {
304 .compatible = "brcm,bcm3380-cpu",
305 .data = (ulong)&bmips_cpu_bcm3380,
306 }, {
293 .compatible = "brcm,bcm6328-cpu", 307 .compatible = "brcm,bcm6328-cpu",
294 .data = (ulong)&bmips_cpu_bcm6328, 308 .data = (ulong)&bmips_cpu_bcm6328,
295 }, { 309 }, {
296 .compatible = "brcm,bcm6348-cpu", 310 .compatible = "brcm,bcm6348-cpu",
297 .data = (ulong)&bmips_cpu_bcm6348, 311 .data = (ulong)&bmips_cpu_bcm6348,
298 }, { 312 }, {
299 .compatible = "brcm,bcm6358-cpu", 313 .compatible = "brcm,bcm6358-cpu",
300 .data = (ulong)&bmips_cpu_bcm6358, 314 .data = (ulong)&bmips_cpu_bcm6358,
301 }, { 315 }, {
302 .compatible = "brcm,bcm63268-cpu", 316 .compatible = "brcm,bcm63268-cpu",
303 .data = (ulong)&bmips_cpu_bcm63268, 317 .data = (ulong)&bmips_cpu_bcm63268,
304 }, 318 },
305 { /* sentinel */ } 319 { /* sentinel */ }
306 }; 320 };
307 321
308 U_BOOT_DRIVER(bmips_cpu_drv) = { 322 U_BOOT_DRIVER(bmips_cpu_drv) = {
309 .name = "bmips_cpu", 323 .name = "bmips_cpu",
310 .id = UCLASS_CPU, 324 .id = UCLASS_CPU,
311 .of_match = bmips_cpu_ids, 325 .of_match = bmips_cpu_ids,
312 .bind = bmips_cpu_bind, 326 .bind = bmips_cpu_bind,
313 .probe = bmips_cpu_probe, 327 .probe = bmips_cpu_probe,
314 .priv_auto_alloc_size = sizeof(struct bmips_cpu_priv), 328 .priv_auto_alloc_size = sizeof(struct bmips_cpu_priv),
315 .ops = &bmips_cpu_ops, 329 .ops = &bmips_cpu_ops,
316 .flags = DM_FLAG_PRE_RELOC, 330 .flags = DM_FLAG_PRE_RELOC,
317 }; 331 };
318 332
319 #ifdef CONFIG_DISPLAY_CPUINFO 333 #ifdef CONFIG_DISPLAY_CPUINFO
320 int print_cpuinfo(void) 334 int print_cpuinfo(void)
321 { 335 {
322 struct cpu_info cpu; 336 struct cpu_info cpu;
323 struct udevice *dev; 337 struct udevice *dev;
324 int err; 338 int err;
325 char desc[100]; 339 char desc[100];
326 340
327 err = uclass_get_device(UCLASS_CPU, 0, &dev); 341 err = uclass_get_device(UCLASS_CPU, 0, &dev);
328 if (err) 342 if (err)
329 return 0; 343 return 0;
330 344
331 err = cpu_get_info(dev, &cpu); 345 err = cpu_get_info(dev, &cpu);
332 if (err) 346 if (err)
333 return 0; 347 return 0;
334 348
335 err = cpu_get_desc(dev, desc, sizeof(desc)); 349 err = cpu_get_desc(dev, desc, sizeof(desc));
336 if (err) 350 if (err)
337 return 0; 351 return 0;
338 352
339 printf("Chip ID: %s, MIPS: ", desc); 353 printf("Chip ID: %s, MIPS: ", desc);
340 print_freq(cpu.cpu_freq, "\n"); 354 print_freq(cpu.cpu_freq, "\n");
341 355
342 return 0; 356 return 0;
343 } 357 }
344 #endif 358 #endif
345 359