Eric Lee / smarc-uboot

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Commit 63a40240b42d8835ff0cf6894b979ce82987ff6e

Authored by Ye Li
1 parent 31c500c421
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-18460-2 mx7d_12x12_arm2: Add LPDDR3 and DDR3 ARM2 support 

Porting the iMX7D 12x12 LPDDR3 and DDR3 ARM2 board codes from v2017.03.

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 16 changed files with 2661 additions and 0 deletions Inline Diff

arch/arm/mach-imx/mx7/Kconfig
Diff comments   View file @ 63a4024
1 if ARCH_MX7 1 if ARCH_MX7
2 2
3 config MX7 3 config MX7
4 bool 4 bool
5 select ROM_UNIFIED_SECTIONS 5 select ROM_UNIFIED_SECTIONS
6 select SYSCOUNTER_TIMER 6 select SYSCOUNTER_TIMER
7 select CPU_V7_HAS_VIRT 7 select CPU_V7_HAS_VIRT
8 select CPU_V7_HAS_NONSEC 8 select CPU_V7_HAS_NONSEC
9 select ARCH_SUPPORT_PSCI 9 select ARCH_SUPPORT_PSCI
10 imply CMD_FUSE 10 imply CMD_FUSE
11 default y 11 default y
12 12
13 config MX7D 13 config MX7D
14 select HAS_CAAM 14 select HAS_CAAM
15 select ROM_UNIFIED_SECTIONS 15 select ROM_UNIFIED_SECTIONS
16 imply CMD_FUSE 16 imply CMD_FUSE
17 bool 17 bool
18 18
19 choice 19 choice
20 prompt "MX7 board select" 20 prompt "MX7 board select"
21 optional 21 optional
22 22
23 config TARGET_CL_SOM_IMX7 23 config TARGET_CL_SOM_IMX7
24 bool "CL-SOM-iMX7" 24 bool "CL-SOM-iMX7"
25 select MX7D 25 select MX7D
26 select DM 26 select DM
27 select DM_THERMAL 27 select DM_THERMAL
28 select SUPPORT_SPL 28 select SUPPORT_SPL
29 29
30 config TARGET_MX7DSABRESD 30 config TARGET_MX7DSABRESD
31 bool "mx7dsabresd" 31 bool "mx7dsabresd"
32 select BOARD_LATE_INIT 32 select BOARD_LATE_INIT
33 select MX7D 33 select MX7D
34 select DM 34 select DM
35 select DM_THERMAL 35 select DM_THERMAL
36 36
37 config TARGET_MX7D_12X12_LPDDR3_ARM2
38 bool "Support mx7d_12x12_lpddr3_arm2"
39 select BOARD_LATE_INIT
40 select MX7D
41 select DM
42 select DM_THERMAL
43
44 config TARGET_MX7D_12X12_DDR3_ARM2
45 bool "Support mx7d_12x12_ddr3_arm2"
46 select BOARD_LATE_INIT
47 select MX7D
48 select DM
49 select DM_THERMAL
50
37 config TARGET_PICO_IMX7D 51 config TARGET_PICO_IMX7D
38 bool "pico-imx7d" 52 bool "pico-imx7d"
39 select BOARD_LATE_INIT 53 select BOARD_LATE_INIT
40 select MX7D 54 select MX7D
41 select DM 55 select DM
42 select DM_THERMAL 56 select DM_THERMAL
43 57
44 config TARGET_WARP7 58 config TARGET_WARP7
45 bool "warp7" 59 bool "warp7"
46 select BOARD_LATE_INIT 60 select BOARD_LATE_INIT
47 select MX7D 61 select MX7D
48 select DM 62 select DM
49 select DM_THERMAL 63 select DM_THERMAL
50 64
51 config TARGET_COLIBRI_IMX7 65 config TARGET_COLIBRI_IMX7
52 bool "Support Colibri iMX7S/iMX7D modules" 66 bool "Support Colibri iMX7S/iMX7D modules"
53 select BOARD_LATE_INIT 67 select BOARD_LATE_INIT
54 select DM 68 select DM
55 select DM_SERIAL 69 select DM_SERIAL
56 select DM_THERMAL 70 select DM_THERMAL
57 71
58 endchoice 72 endchoice
59 73
60 config SYS_SOC 74 config SYS_SOC
61 default "mx7" 75 default "mx7"
62 76
63 source "board/compulab/cl-som-imx7/Kconfig" 77 source "board/compulab/cl-som-imx7/Kconfig"
64 source "board/freescale/mx7dsabresd/Kconfig" 78 source "board/freescale/mx7dsabresd/Kconfig"
79 source "board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig"
80 source "board/freescale/mx7d_12x12_ddr3_arm2/Kconfig"
65 source "board/technexion/pico-imx7d/Kconfig" 81 source "board/technexion/pico-imx7d/Kconfig"
66 source "board/toradex/colibri_imx7/Kconfig" 82 source "board/toradex/colibri_imx7/Kconfig"
67 source "board/warp7/Kconfig" 83 source "board/warp7/Kconfig"
68 84
69 endif 85 endif
70 86
board/freescale/mx7d_12x12_ddr3_arm2/Kconfig
Diff comments   View file @ 63a4024
File was created 1 if TARGET_MX7D_12X12_DDR3_ARM2
2
3 config SYS_BOARD
4 default "mx7d_12x12_ddr3_arm2"
5
6 config SYS_VENDOR
7 default "freescale"
8
9 config SYS_CONFIG_NAME
10 default "mx7d_12x12_ddr3_arm2"
11
12 config SYS_TEXT_BASE
13 default 0x87800000
14 endif
15
board/freescale/mx7d_12x12_ddr3_arm2/Makefile
Diff comments   View file @ 63a4024
File was created 1 # (C) Copyright 2015 Freescale Semiconductor, Inc.
2 #
3 # SPDX-License-Identifier: GPL-2.0+
4 #
5
6 obj-y := mx7d_12x12_ddr3_arm2.o
7
board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg
Diff comments   View file @ 63a4024
File was created 1 /*
2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 *
7 * Refer doc/README.imxmage for more details about how-to configure
8 * and create imximage boot image
9 *
10 * The syntax is taken as close as possible with the kwbimage
11 */
12
13 #define __ASSEMBLY__
14 #include <config.h>
15
16 /* image version */
17
18 IMAGE_VERSION 2
19
20 /*
21 * Boot Device : one of
22 * sd/onenand, nor
23 */
24
25 BOOT_FROM sd
26
27 #ifdef CONFIG_USE_IMXIMG_PLUGIN
28 /*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
29 PLUGIN board/freescale/mx7d_12x12_ddr3_arm2/plugin.bin 0x00910000
30 #else
31
32 #ifdef CONFIG_SECURE_BOOT
33 CSF CONFIG_CSF_SIZE
34 #endif
35
36 /*
37 * Device Configuration Data (DCD)
38 *
39 * Each entry must have the format:
40 * Addr-type Address Value
41 *
42 * where:
43 * Addr-type register length (1,2 or 4 bytes)
44 * Address absolute address of the register
45 * value value to be stored in the register
46 */
47
48 DATA 4 0x30340004 0x4F400005
49 /* Clear then set bit30 to ensure exit from DDR retention */
50 DATA 4 0x30360388 0x40000000
51 DATA 4 0x30360384 0x40000000
52
53 DATA 4 0x30391000 0x00000002
54 DATA 4 0x307a0000 0x01040001
55 DATA 4 0x307a01a0 0x80400003
56 DATA 4 0x307a01a4 0x00100020
57 DATA 4 0x307a01a8 0x80100004
58 DATA 4 0x307a0064 0x00400046
59 DATA 4 0x307a0490 0x00000001
60 DATA 4 0x307a00d0 0x00020083
61 DATA 4 0x307a00d4 0x00690000
62 DATA 4 0x307a00dc 0x09300004
63 DATA 4 0x307a00e0 0x04080000
64 DATA 4 0x307a00e4 0x00100004
65 DATA 4 0x307a00f4 0x0000033f
66 DATA 4 0x307a0100 0x09081109
67 DATA 4 0x307a0104 0x0007020d
68 DATA 4 0x307a0108 0x03040407
69 DATA 4 0x307a010c 0x00002006
70 DATA 4 0x307a0110 0x04020205
71 DATA 4 0x307a0114 0x03030202
72 DATA 4 0x307a0120 0x00000803
73 DATA 4 0x307a0180 0x00800020
74 DATA 4 0x307a0184 0x02000100
75 DATA 4 0x307a0190 0x02098204
76 DATA 4 0x307a0194 0x00030303
77 DATA 4 0x307a0200 0x00000016
78 DATA 4 0x307a0204 0x00080808
79 DATA 4 0x307a0210 0x00000f0f
80 DATA 4 0x307a0214 0x07070707
81 DATA 4 0x307a0218 0x0f070707
82 DATA 4 0x307a0240 0x06000604
83 DATA 4 0x307a0244 0x00000001
84 DATA 4 0x30391000 0x00000000
85 DATA 4 0x30790000 0x17420f40
86 DATA 4 0x30790004 0x10210100
87 DATA 4 0x30790010 0x00060807
88 DATA 4 0x307900b0 0x1010007e
89 DATA 4 0x3079009c 0x00000b24
90 DATA 4 0x30790020 0x08080808
91 DATA 4 0x30790030 0x08080808
92 DATA 4 0x30790050 0x01000010
93 DATA 4 0x30790050 0x00000010
94
95 DATA 4 0x307900c0 0x0e407304
96 DATA 4 0x307900c0 0x0e447304
97 DATA 4 0x307900c0 0x0e447306
98
99 CHECK_BITS_SET 4 0x307900c4 0x1
100
101 DATA 4 0x307900c0 0x0e407304
102
103
104 DATA 4 0x30384130 0x00000000
105 DATA 4 0x30340020 0x00000178
106 DATA 4 0x30384130 0x00000002
107 DATA 4 0x30790018 0x0000000f
108
109 CHECK_BITS_SET 4 0x307a0004 0x1
110
111 #endif
112
board/freescale/mx7d_12x12_ddr3_arm2/imximage_TO_1_1.cfg
Diff comments   View file @ 63a4024
File was created 1 /*
2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 *
7 * Refer docs/README.imxmage for more details about how-to configure
8 * and create imximage boot image
9 *
10 * The syntax is taken as close as possible with the kwbimage
11 */
12
13 #define __ASSEMBLY__
14 #include <config.h>
15
16 /* image version */
17
18 IMAGE_VERSION 2
19
20 /*
21 * Boot Device : one of
22 * sd/onenand, nor
23 */
24
25 BOOT_FROM sd
26
27 #ifdef CONFIG_USE_IMXIMG_PLUGIN
28 /*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
29 PLUGIN board/freescale/mx7d_12x12_ddr3_arm2/plugin.bin 0x00910000
30 #else
31
32 #ifdef CONFIG_SECURE_BOOT
33 CSF CONFIG_CSF_SIZE
34 #endif
35
36 /*
37 * Device Configuration Data (DCD)
38 *
39 * Each entry must have the format:
40 * Addr-type Address Value
41 *
42 * where:
43 * Addr-type register length (1,2 or 4 bytes)
44 * Address absolute address of the register
45 * value value to be stored in the register
46 */
47
48 DATA 4 0x30360070 0x00703021
49 DATA 4 0x30360090 0x0
50 DATA 4 0x30360070 0x00603021
51 CHECK_BITS_SET 4 0x30360070 0x80000000
52 DATA 4 0x30389880 0x1
53
54 DATA 4 0x30340004 0x4F400005
55 /* Clear then set bit30 to ensure exit from DDR retention */
56 DATA 4 0x30360388 0x40000000
57 DATA 4 0x30360384 0x40000000
58
59 DATA 4 0x30391000 0x00000002
60 DATA 4 0x307a0000 0x01040001
61 DATA 4 0x307a01a0 0x80400003
62 DATA 4 0x307a01a4 0x00100020
63 DATA 4 0x307a01a8 0x80100004
64 DATA 4 0x307a0064 0x00400046
65 DATA 4 0x307a0490 0x00000001
66 DATA 4 0x307a00d0 0x00020083
67 DATA 4 0x307a00d4 0x00690000
68 DATA 4 0x307a00dc 0x09300004
69 DATA 4 0x307a00e0 0x04080000
70 DATA 4 0x307a00e4 0x00100004
71 DATA 4 0x307a00f4 0x0000033f
72 DATA 4 0x307a0100 0x09081109
73 DATA 4 0x307a0104 0x0007020d
74 DATA 4 0x307a0108 0x03040407
75 DATA 4 0x307a010c 0x00002006
76 DATA 4 0x307a0110 0x04020205
77 DATA 4 0x307a0114 0x03030202
78 DATA 4 0x307a0120 0x00000803
79 DATA 4 0x307a0180 0x00800020
80 DATA 4 0x307a0184 0x02000100
81 DATA 4 0x307a0190 0x02098204
82 DATA 4 0x307a0194 0x00030303
83 DATA 4 0x307a0200 0x00000016
84 DATA 4 0x307a0204 0x00080808
85 DATA 4 0x307a0210 0x00000f0f
86 DATA 4 0x307a0214 0x07070707
87 DATA 4 0x307a0218 0x0f070707
88 DATA 4 0x307a0240 0x06000604
89 DATA 4 0x307a0244 0x00000001
90 DATA 4 0x30391000 0x00000000
91 DATA 4 0x30790000 0x17420f40
92 DATA 4 0x30790004 0x10210100
93 DATA 4 0x30790010 0x00060807
94 DATA 4 0x307900b0 0x1010007e
95 DATA 4 0x3079009c 0x00000dee
96 DATA 4 0x3079007c 0x18181818
97 DATA 4 0x30790080 0x18181818
98 DATA 4 0x30790084 0x40401818
99 DATA 4 0x30790088 0x00000040
100 DATA 4 0x3079006c 0x40404040
101 DATA 4 0x30790020 0x08080808
102 DATA 4 0x30790030 0x08080808
103 DATA 4 0x30790050 0x01000010
104 DATA 4 0x30790050 0x00000010
105
106 DATA 4 0x307900c0 0x0e407304
107 DATA 4 0x307900c0 0x0e447304
108 DATA 4 0x307900c0 0x0e447306
109
110 CHECK_BITS_SET 4 0x307900c4 0x1
111
112 DATA 4 0x307900c0 0x0e407304
113
114
115 DATA 4 0x30384130 0x00000000
116 DATA 4 0x30340020 0x00000178
117 DATA 4 0x30384130 0x00000002
118 DATA 4 0x30790018 0x0000000f
119
120 CHECK_BITS_SET 4 0x307a0004 0x1
121
122 #endif
123
board/freescale/mx7d_12x12_ddr3_arm2/mx7d_12x12_ddr3_arm2.c
Diff comments   View file @ 63a4024
File was created 1 /*
2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <asm/arch/clock.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/mx7-pins.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/gpio.h>
13 #include <asm/mach-imx/iomux-v3.h>
14 #include <asm/mach-imx/boot_mode.h>
15 #include <asm/io.h>
16 #include <linux/sizes.h>
17 #include <common.h>
18 #include <fsl_esdhc.h>
19 #include <mmc.h>
20 #include <miiphy.h>
21 #include <netdev.h>
22 #include <power/pmic.h>
23 #include <power/pfuze3000_pmic.h>
24 #include "../common/pfuze.h"
25 #include <asm/arch/crm_regs.h>
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
30 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
31 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
32 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
33 #define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
34
35 int dram_init(void)
36 {
37 gd->ram_size = PHYS_SDRAM_SIZE;
38
39 return 0;
40 }
41
42 static iomux_v3_cfg_t const uart1_pads[] = {
43 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
44 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
45 };
46
47 static iomux_v3_cfg_t const wdog_pads[] = {
48 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
49 };
50
51 static void setup_iomux_uart(void)
52 {
53 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
54 }
55
56 #ifdef CONFIG_FSL_ESDHC
57 int board_mmc_get_env_dev(int devno)
58 {
59 return devno - 1;
60 }
61
62 int mmc_map_to_kernel_blk(int dev_no)
63 {
64 return dev_no + 1;
65 }
66 #endif
67
68 #ifdef CONFIG_MXC_SPI
69 iomux_v3_cfg_t const ecspi1_pads[] = {
70 MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
71 MX7D_PAD_SD1_WP__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
72 MX7D_PAD_SD1_CD_B__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
73 /* Chip selects CS0:CS3 */
74 MX7D_PAD_SD1_CLK__GPIO5_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
75 MX7D_PAD_SD1_CMD__GPIO5_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL),
76 MX7D_PAD_SD1_DATA0__GPIO5_IO5 | MUX_PAD_CTRL(NO_PAD_CTRL),
77 MX7D_PAD_SD1_DATA1__GPIO5_IO6 | MUX_PAD_CTRL(NO_PAD_CTRL),
78 };
79
80 void setup_spinor(void)
81 {
82 imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
83 ARRAY_SIZE(ecspi1_pads));
84 gpio_request(IMX_GPIO_NR(5, 3), "ecspi1_cs");
85 gpio_direction_output(IMX_GPIO_NR(5, 3), 0);
86 }
87
88 int board_spi_cs_gpio(unsigned bus, unsigned cs)
89 {
90 return (bus == 3 && cs == 0) ? (IMX_GPIO_NR(5, 3)) : -1;
91 }
92 #endif
93
94 int board_early_init_f(void)
95 {
96 setup_iomux_uart();
97
98 return 0;
99 }
100
101 int board_init(void)
102 {
103 /* address of boot parameters */
104 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
105
106 #ifdef CONFIG_MXC_SPI
107 setup_spinor();
108 #endif
109
110 return 0;
111 }
112
113 #ifdef CONFIG_CMD_BMODE
114 static const struct boot_mode board_boot_modes[] = {
115 /* 4 bit bus width */
116 {"emmc", MAKE_CFGVAL(0x10, 0x22, 0x00, 0x00)},
117 {"sd3", MAKE_CFGVAL(0x10, 0x1a, 0x00, 0x00)},
118 {NULL, 0},
119 };
120 #endif
121
122 #ifdef CONFIG_DM_PMIC
123 int power_init_board(void)
124 {
125 struct udevice *dev;
126 int ret, dev_id, rev_id, reg;
127
128 ret = pmic_get("pfuze3000", &dev);
129 if (ret == -ENODEV)
130 return 0;
131 if (ret != 0)
132 return ret;
133
134 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
135 rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
136 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
137
138 /* disable Low Power Mode during standby mode */
139 reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
140 reg |= 0x1;
141 pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
142
143 /* SW1A/1B mode set to APS/APS */
144 reg = 0x8;
145 pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
146 pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
147
148 /* SW1A/1B standby voltage set to 0.975V */
149 reg = 0xb;
150 pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
151 pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
152
153 /* set SW1B normal voltage to 0.975V */
154 reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
155 reg &= ~0x1f;
156 reg |= PFUZE3000_SW1AB_SETP(9750);
157 pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
158
159 return 0;
160 }
161 #endif
162
163 int board_late_init(void)
164 {
165 #ifdef CONFIG_CMD_BMODE
166 add_board_boot_modes(board_boot_modes);
167 #endif
168
169 #ifdef CONFIG_ENV_IS_IN_MMC
170 board_late_mmc_env_init();
171 #endif
172
173 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
174
175 set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
176
177 return 0;
178 }
179
180 u32 get_board_rev(void)
181 {
182 return get_cpu_rev();
183 }
184
185 int checkboard(void)
186 {
187 puts("Board: MX7D 12x12 DDR3 ARM2\n");
188
189 return 0;
190 }
191
board/freescale/mx7d_12x12_ddr3_arm2/plugin.S
Diff comments   View file @ 63a4024
File was created 1 /*
2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <config.h>
8
9 /* DDR script */
10 .macro imx7d_ddrphy_latency_setting
11 ldr r2, =ANATOP_BASE_ADDR
12 ldr r3, [r2, #0x800]
13 and r3, r3, #0xFF
14 cmp r3, #0x11
15 bne NO_DELAY
16
17 /*TO 1.1*/
18 ldr r1, =0x00000dee
19 str r1, [r0, #0x9c]
20 ldr r1, =0x18181818
21 str r1, [r0, #0x7c]
22 ldr r1, =0x18181818
23 str r1, [r0, #0x80]
24 ldr r1, =0x40401818
25 str r1, [r0, #0x84]
26 ldr r1, =0x00000040
27 str r1, [r0, #0x88]
28 ldr r1, =0x40404040
29 str r1, [r0, #0x6c]
30 b TUNE_END
31
32 NO_DELAY:
33 /*TO 1.0*/
34 ldr r1, =0x00000b24
35 str r1, [r0, #0x9c]
36
37 TUNE_END:
38 .endm
39
40 .macro imx7d_ddr_freq_setting
41 ldr r2, =ANATOP_BASE_ADDR
42 ldr r3, [r2, #0x800]
43 and r3, r3, #0xFF
44 cmp r3, #0x11
45 bne FREQ_DEFAULT_533
46
47 /* Change to 400Mhz for TO1.1 */
48 ldr r0, =ANATOP_BASE_ADDR
49 ldr r1, =0x70
50 ldr r2, =0x00703021
51 str r2, [r0, r1]
52 ldr r1, =0x90
53 ldr r2, =0x0
54 str r2, [r0, r1]
55 ldr r1, =0x70
56 ldr r2, =0x00603021
57 str r2, [r0, r1]
58
59 ldr r3, =0x80000000
60 wait_lock:
61 ldr r2, [r0, r1]
62 and r2, r3
63 cmp r2, r3
64 bne wait_lock
65
66 ldr r0, =CCM_BASE_ADDR
67 ldr r1, =0x9880
68 ldr r2, =0x1
69 str r2, [r0, r1]
70
71 FREQ_DEFAULT_533:
72 .endm
73
74 .macro imx7d_12x12_ddr3_arm2_ddr_setting
75 imx7d_ddr_freq_setting
76
77 /* Configure ocram_epdc */
78 ldr r0, =IOMUXC_GPR_BASE_ADDR
79 ldr r1, =0x4f400005
80 str r1, [r0, #0x4]
81
82 /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
83 ldr r0, =ANATOP_BASE_ADDR
84 ldr r1, =(0x1 << 30)
85 str r1, [r0, #0x388]
86 str r1, [r0, #0x384]
87
88 ldr r0, =SRC_BASE_ADDR
89 ldr r1, =0x2
90 ldr r2, =0x1000
91 str r1, [r0, r2]
92
93 ldr r0, =DDRC_IPS_BASE_ADDR
94 ldr r1, =0x01040001
95 str r1, [r0]
96 ldr r1, =0x80400003
97 str r1, [r0, #0x1a0]
98 ldr r1, =0x00100020
99 str r1, [r0, #0x1a4]
100 ldr r1, =0x80100004
101 str r1, [r0, #0x1a8]
102 ldr r1, =0x00400046
103 str r1, [r0, #0x64]
104 ldr r1, =0x1
105 str r1, [r0, #0x490]
106 ldr r1, =0x00020001
107 str r1, [r0, #0xd0]
108 ldr r1, =0x00690000
109 str r1, [r0, #0xd4]
110 ldr r1, =0x09300004
111 str r1, [r0, #0xdc]
112 ldr r1, =0x04080000
113 str r1, [r0, #0xe0]
114 ldr r1, =0x00100004
115 str r1, [r0, #0xe4]
116 ldr r1, =0x33f
117 str r1, [r0, #0xf4]
118 ldr r1, =0x09081109
119 str r1, [r0, #0x100]
120 ldr r1, =0x0007020d
121 str r1, [r0, #0x104]
122 ldr r1, =0x03040407
123 str r1, [r0, #0x108]
124 ldr r1, =0x00002006
125 str r1, [r0, #0x10c]
126 ldr r1, =0x04020205
127 str r1, [r0, #0x110]
128 ldr r1, =0x03030202
129 str r1, [r0, #0x114]
130 ldr r1, =0x00000803
131 str r1, [r0, #0x120]
132 ldr r1, =0x00800020
133 str r1, [r0, #0x180]
134 ldr r1, =0x02000100
135 str r1, [r0, #0x184]
136 ldr r1, =0x02098204
137 str r1, [r0, #0x190]
138 ldr r1, =0x00030303
139 str r1, [r0, #0x194]
140
141 ldr r1, =0x00000016
142 str r1, [r0, #0x200]
143 ldr r1, =0x00080808
144 str r1, [r0, #0x204]
145 ldr r1, =0x00000f0f
146 str r1, [r0, #0x210]
147 ldr r1, =0x07070707
148 str r1, [r0, #0x214]
149 ldr r1, =0x0f070707
150 str r1, [r0, #0x218]
151
152 ldr r1, =0x06000604
153 str r1, [r0, #0x240]
154 ldr r1, =0x00000001
155 str r1, [r0, #0x244]
156
157 ldr r0, =SRC_BASE_ADDR
158 mov r1, #0x0
159 ldr r2, =0x1000
160 str r1, [r0, r2]
161
162 ldr r0, =DDRPHY_IPS_BASE_ADDR
163 ldr r1, =0x17420f40
164 str r1, [r0]
165 ldr r1, =0x10210100
166 str r1, [r0, #0x4]
167 ldr r1, =0x00060807
168 str r1, [r0, #0x10]
169 ldr r1, =0x1010007e
170 str r1, [r0, #0xb0]
171 imx7d_ddrphy_latency_setting
172 ldr r1, =0x08080808
173 str r1, [r0, #0x20]
174 ldr r1, =0x08080808
175 str r1, [r0, #0x30]
176 ldr r1, =0x01000010
177 str r1, [r0, #0x50]
178
179 ldr r1, =0x0e407304
180 str r1, [r0, #0xc0]
181 ldr r1, =0x0e447304
182 str r1, [r0, #0xc0]
183 ldr r1, =0x0e447306
184 str r1, [r0, #0xc0]
185
186 wait_zq:
187 ldr r1, [r0, #0xc4]
188 tst r1, #0x1
189 beq wait_zq
190
191 ldr r1, =0x0e407304
192 str r1, [r0, #0xc0]
193
194 ldr r0, =CCM_BASE_ADDR
195 mov r1, #0x0
196 ldr r2, =0x4130
197 str r1, [r0, r2]
198 ldr r0, =IOMUXC_GPR_BASE_ADDR
199 mov r1, #0x178
200 str r1, [r0, #0x20]
201 ldr r0, =CCM_BASE_ADDR
202 mov r1, #0x2
203 ldr r2, =0x4130
204 str r1, [r0, r2]
205 ldr r0, =DDRPHY_IPS_BASE_ADDR
206 ldr r1, =0x0000000f
207 str r1, [r0, #0x18]
208
209 ldr r0, =DDRC_IPS_BASE_ADDR
210 wait_stat:
211 ldr r1, [r0, #0x4]
212 tst r1, #0x1
213 beq wait_stat
214 .endm
215
216 .macro imx7_clock_gating
217 .endm
218
219 .macro imx7_qos_setting
220 .endm
221
222 .macro imx7_ddr_setting
223 imx7d_12x12_ddr3_arm2_ddr_setting
224 .endm
225
226 /* include the common plugin code here */
227 #include <asm/arch/mx7_plugin.S>
228
board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig
Diff comments   View file @ 63a4024
File was created 1 if TARGET_MX7D_12X12_LPDDR3_ARM2
2
3 config SYS_BOARD
4 default "mx7d_12x12_lpddr3_arm2"
5
6 config SYS_VENDOR
7 default "freescale"
8
9 config SYS_CONFIG_NAME
10 default "mx7d_12x12_lpddr3_arm2"
11
12 config SYS_TEXT_BASE
13 default 0x87800000
14 endif
15
board/freescale/mx7d_12x12_lpddr3_arm2/Makefile
Diff comments   View file @ 63a4024
File was created 1 # (C) Copyright 2015 Freescale Semiconductor, Inc.
2 #
3 # SPDX-License-Identifier: GPL-2.0+
4 #
5
6 obj-y := mx7d_12x12_lpddr3_arm2.o
7
board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg
Diff comments   View file @ 63a4024
File was created 1 /*
2 * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 *
7 * Refer doc/README.imxmage for more details about how-to configure
8 * and create imximage boot image
9 *
10 * The syntax is taken as close as possible with the kwbimage
11 */
12
13 #define __ASSEMBLY__
14 #include <config.h>
15
16 /* image version */
17
18 IMAGE_VERSION 2
19
20 BOOT_FROM sd
21
22 #ifdef CONFIG_USE_IMXIMG_PLUGIN
23 /*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
24 PLUGIN board/freescale/mx7d_12x12_lpddr3_arm2/plugin.bin 0x00910000
25 #else
26
27 #ifdef CONFIG_SECURE_BOOT
28 CSF CONFIG_CSF_SIZE
29 #endif
30
31 /*
32 * Device Configuration Data (DCD)
33 *
34 * Each entry must have the format:
35 * Addr-type Address Value
36 *
37 * where:
38 * Addr-type register length (1,2 or 4 bytes)
39 * Address absolute address of the register
40 * value value to be stored in the register
41 */
42
43 DATA 4 0x30340004 0x4F400005
44 /* Clear then set bit30 to ensure exit from DDR retention */
45 DATA 4 0x30360388 0x40000000
46 DATA 4 0x30360384 0x40000000
47
48 DATA 4 0x30391000 0x00000002
49 DATA 4 0x307a0000 0x03040008
50 DATA 4 0x307a0064 0x00200038
51 DATA 4 0x307a0490 0x00000001
52 DATA 4 0x307a00d0 0x00350001
53 DATA 4 0x307a00dc 0x00c3000a
54 DATA 4 0x307a00e0 0x00010000
55 DATA 4 0x307a00e4 0x00110006
56 DATA 4 0x307a00f4 0x0000033f
57 DATA 4 0x307a0100 0x0a0e110b
58 DATA 4 0x307a0104 0x00020211
59 DATA 4 0x307a0108 0x03060708
60 DATA 4 0x307a010c 0x00a0500c
61 DATA 4 0x307a0110 0x05020307
62 DATA 4 0x307a0114 0x02020404
63 DATA 4 0x307a0118 0x02020003
64 DATA 4 0x307a011c 0x00000202
65 DATA 4 0x307a0120 0x00000202
66
67 DATA 4 0x307a0180 0x00600018
68 DATA 4 0x307a0184 0x00e00100
69 DATA 4 0x307a0190 0x02098205
70 DATA 4 0x307a0194 0x00060303
71 DATA 4 0x307a01a0 0x80400003
72 DATA 4 0x307a01a4 0x00100020
73 DATA 4 0x307a01a8 0x80100004
74
75 DATA 4 0x307a0200 0x00000016
76 DATA 4 0x307a0204 0x00090909
77 DATA 4 0x307a0210 0x00000f00
78 DATA 4 0x307a0214 0x08080808
79 DATA 4 0x307a0218 0x0f0f0808
80
81 DATA 4 0x307a0240 0x06000600
82 DATA 4 0x307a0244 0x00000000
83 DATA 4 0x30391000 0x00000000
84 DATA 4 0x30790000 0x17421e40
85 DATA 4 0x30790004 0x10210100
86 DATA 4 0x30790008 0x00010000
87 DATA 4 0x30790010 0x0007080c
88 DATA 4 0x307900b0 0x1010007e
89
90 DATA 4 0x3079001C 0x01010000
91 DATA 4 0x3079009c 0x00000b24
92
93 DATA 4 0x30790030 0x06060606
94 DATA 4 0x30790020 0x0a0a0a0a
95 DATA 4 0x30790050 0x01000008
96 DATA 4 0x30790050 0x00000008
97 DATA 4 0x30790018 0x0000000f
98 DATA 4 0x307900c0 0x0e487304
99 DATA 4 0x307900c0 0x0e4c7304
100 DATA 4 0x307900c0 0x0e4c7306
101 CHECK_BITS_SET 4 0x307900c4 0x1
102
103 DATA 4 0x307900c0 0x0e487304
104
105 DATA 4 0x30384130 0x00000000
106 DATA 4 0x30340020 0x00000178
107 DATA 4 0x30384130 0x00000002
108
109 CHECK_BITS_SET 4 0x307a0004 0x1
110 #endif
111
board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg
Diff comments   View file @ 63a4024
File was created 1 /*
2 * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 *
7 * Refer docs/README.imxmage for more details about how-to configure
8 * and create imximage boot image
9 *
10 * The syntax is taken as close as possible with the kwbimage
11 */
12
13 #define __ASSEMBLY__
14 #include <config.h>
15
16 /* image version */
17
18 IMAGE_VERSION 2
19
20 /*
21 * Boot Device : one of
22 * spi/sd/nand/onenand, qspi/nor
23 */
24
25 BOOT_FROM sd
26
27 #ifdef CONFIG_USE_IMXIMG_PLUGIN
28 /*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
29 PLUGIN board/freescale/mx7d_12x12_lpddr3_arm2/plugin.bin 0x00910000
30 #else
31
32 #ifdef CONFIG_SECURE_BOOT
33 CSF CONFIG_CSF_SIZE
34 #endif
35
36 /*
37 * Device Configuration Data (DCD)
38 *
39 * Each entry must have the format:
40 * Addr-type Address Value
41 *
42 * where:
43 * Addr-type register length (1,2 or 4 bytes)
44 * Address absolute address of the register
45 * value value to be stored in the register
46 */
47
48 DATA 4 0x30340004 0x4F400005
49 /* Clear then set bit30 to ensure exit from DDR retention */
50 DATA 4 0x30360388 0x40000000
51 DATA 4 0x30360384 0x40000000
52
53 DATA 4 0x30391000 0x00000002
54 DATA 4 0x307a0000 0x03040008
55 DATA 4 0x307a0064 0x00200038
56 DATA 4 0x307a0490 0x00000001
57 DATA 4 0x307a00d0 0x00350001
58 DATA 4 0x307a00dc 0x00c3000a
59 DATA 4 0x307a00e0 0x00010000
60 DATA 4 0x307a00e4 0x00110006
61 DATA 4 0x307a00f4 0x0000033f
62 DATA 4 0x307a0100 0x0a0e110b
63 DATA 4 0x307a0104 0x00020211
64 DATA 4 0x307a0108 0x03060708
65 DATA 4 0x307a010c 0x00a0500c
66 DATA 4 0x307a0110 0x05020307
67 DATA 4 0x307a0114 0x02020404
68 DATA 4 0x307a0118 0x02020003
69 DATA 4 0x307a011c 0x00000202
70 DATA 4 0x307a0120 0x00000202
71
72 DATA 4 0x307a0180 0x00600018
73 DATA 4 0x307a0184 0x00e00100
74 DATA 4 0x307a0190 0x02098205
75 DATA 4 0x307a0194 0x00060303
76 DATA 4 0x307a01a0 0x80400003
77 DATA 4 0x307a01a4 0x00100020
78 DATA 4 0x307a01a8 0x80100004
79
80 DATA 4 0x307a0200 0x00000016
81 DATA 4 0x307a0204 0x00090909
82 DATA 4 0x307a0210 0x00000f00
83 DATA 4 0x307a0214 0x08080808
84 DATA 4 0x307a0218 0x0f0f0808
85
86 DATA 4 0x307a0240 0x06000601
87 DATA 4 0x307a0244 0x00000000
88 DATA 4 0x30391000 0x00000000
89 DATA 4 0x30790000 0x17421e40
90 DATA 4 0x30790004 0x10210100
91 DATA 4 0x30790008 0x00010000
92 DATA 4 0x30790010 0x0007080c
93 DATA 4 0x3079007c 0x1c1c1c1c
94 DATA 4 0x30790080 0x1c1c1c1c
95 DATA 4 0x30790084 0x30301c1c
96 DATA 4 0x30790088 0x00000030
97 DATA 4 0x3079006c 0x30303030
98 DATA 4 0x307900b0 0x1010007e
99
100 DATA 4 0x3079001C 0x01010000
101 DATA 4 0x3079009c 0x0db60d6e
102
103 DATA 4 0x30790030 0x06060606
104 DATA 4 0x30790020 0x0a0a0a0a
105 DATA 4 0x30790050 0x01000008
106 DATA 4 0x30790050 0x00000008
107 DATA 4 0x30790018 0x0000000f
108 DATA 4 0x307900c0 0x1e487304
109 DATA 4 0x307900c0 0x1e487304
110 DATA 4 0x307900c0 0x1e487306
111 DATA 4 0x307900c0 0x1e4c7304
112 CHECK_BITS_SET 4 0x307900c4 0x1
113
114 DATA 4 0x307900c0 0x1e487304
115
116 DATA 4 0x30384130 0x00000000
117 DATA 4 0x30340020 0x00000178
118 DATA 4 0x30384130 0x00000002
119
120 CHECK_BITS_SET 4 0x307a0004 0x1
121 #endif
122
board/freescale/mx7d_12x12_lpddr3_arm2/mx7d_12x12_lpddr3_arm2.c
Diff comments   View file @ 63a4024
File was created 1 /*
2 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <asm/arch/clock.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/mx7-pins.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/gpio.h>
12 #include <asm/mach-imx/iomux-v3.h>
13 #include <asm/mach-imx/boot_mode.h>
14 #include <asm/io.h>
15 #include <linux/sizes.h>
16 #include <common.h>
17 #include <fsl_esdhc.h>
18 #include <mmc.h>
19 #include <miiphy.h>
20 #include <netdev.h>
21 #include <power/pmic.h>
22 #include <power/pfuze3000_pmic.h>
23 #include "../common/pfuze.h"
24 #include <asm/arch/crm_regs.h>
25 #include <asm/mach-imx/video.h>
26
27 #ifdef CONFIG_VIDEO_MXS
28 #include <linux/fb.h>
29 #endif
30 #if defined(CONFIG_MXC_EPDC)
31 #include <lcd.h>
32 #include <mxc_epdc_fb.h>
33 #endif
34
35 DECLARE_GLOBAL_DATA_PTR;
36
37 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
38 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
39
40 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
41 #define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
42
43 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
44
45 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
46 PAD_CTL_DSE_3P3V_49OHM)
47
48 #define QSPI_PAD_CTRL \
49 (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
50
51 #define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
52
53 #define EPDC_PAD_CTRL 0x0
54
55 int dram_init(void)
56 {
57 gd->ram_size = PHYS_SDRAM_SIZE;
58
59 return 0;
60 }
61
62 static iomux_v3_cfg_t const uart1_pads[] = {
63 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
64 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
65 };
66
67 #ifdef CONFIG_VIDEO_MXS
68 static iomux_v3_cfg_t const lcd_pads[] = {
69 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
70 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
71 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
72 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
73 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
74 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
75 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
76 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
77 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
78 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
79 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
80 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
81 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
82 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
83 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
84 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
85 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
86 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
87 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
88 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
89 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
90 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
91 MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
92 MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
93 MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
94 MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
95 MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
96 MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
97
98 MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
99 };
100
101 static iomux_v3_cfg_t const pwm_pads[] = {
102 /* Use GPIO for Brightness adjustment, duty cycle = period */
103 MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
104 };
105
106 void do_enable_parallel_lcd(struct display_info_t const *dev)
107 {
108 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
109
110 imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
111
112 /* Power up the LCD */
113 gpio_request(IMX_GPIO_NR(3, 4), "lcd_pwr");
114 gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
115
116 /* Set Brightness to high */
117 gpio_request(IMX_GPIO_NR(1, 1), "lcd_backlight");
118 gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
119 }
120
121 struct display_info_t const displays[] = {{
122 .bus = ELCDIF1_IPS_BASE_ADDR,
123 .addr = 0,
124 .pixfmt = 24,
125 .detect = NULL,
126 .enable = do_enable_parallel_lcd,
127 .mode = {
128 .name = "MCIMX28LCD",
129 .xres = 800,
130 .yres = 480,
131 .pixclock = 29850,
132 .left_margin = 89,
133 .right_margin = 164,
134 .upper_margin = 23,
135 .lower_margin = 10,
136 .hsync_len = 10,
137 .vsync_len = 10,
138 .sync = 0,
139 .vmode = FB_VMODE_NONINTERLACED
140 } } };
141 size_t display_count = ARRAY_SIZE(displays);
142 #endif
143
144
145 static iomux_v3_cfg_t const per_rst_pads[] = {
146 MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
147 };
148
149 static iomux_v3_cfg_t const wdog_pads[] = {
150 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
151 };
152
153 #ifdef CONFIG_FEC_MXC
154 static iomux_v3_cfg_t const fec1_pads[] = {
155 MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
156 MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
157 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
158 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
159 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
160 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
161 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
162 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
163 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
164 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
165 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
166 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
167 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
168 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
169 MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
170 };
171
172 static void setup_iomux_fec1(void)
173 {
174 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
175 }
176 #endif
177
178 static void setup_iomux_uart(void)
179 {
180 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
181 }
182
183 #ifdef CONFIG_FSL_QSPI
184 #ifndef CONFIG_DM_SPI
185 static iomux_v3_cfg_t const quadspi_pads[] = {
186 MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
187 MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
188 MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
189 MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
190 MX7D_PAD_EPDC_DATA04__QSPI_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL),
191 MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
192 MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
193 MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
194
195 MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
196 MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
197 MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
198 MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
199 MX7D_PAD_EPDC_DATA12__QSPI_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL),
200 MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
201 MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
202 MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
203
204 };
205 #endif
206
207 int board_qspi_init(void)
208 {
209 #ifndef CONFIG_DM_SPI
210 /* Set the iomux */
211 imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
212 #endif
213
214 /* Set the clock */
215 set_clk_qspi();
216
217 return 0;
218 }
219 #endif
220
221 #ifdef CONFIG_FSL_ESDHC
222 int mmc_map_to_kernel_blk(int dev_no)
223 {
224 return dev_no;
225 }
226
227 int board_mmc_get_env_dev(int devno)
228 {
229 return devno;
230 }
231 #endif
232
233 #ifdef CONFIG_FEC_MXC
234 int board_eth_init(bd_t *bis)
235 {
236 int ret;
237
238 setup_iomux_fec1();
239
240 ret = fecmxc_initialize_multi(bis, 0,
241 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
242 if (ret)
243 printf("FEC1 MXC: %s:failed\n", __func__);
244
245 return 0;
246 }
247
248 static int setup_fec(void)
249 {
250 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
251 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
252 int ret;
253
254 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
255 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
256 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
257 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
258
259 ret = set_clk_enet(ENET_125MHZ);
260 if (ret)
261 return ret;
262
263 return 0;
264 }
265
266
267 int board_phy_config(struct phy_device *phydev)
268 {
269 /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
270 Phy control debug reg 0 */
271 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
272 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
273
274 /* rgmii tx clock delay enable */
275 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
276 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
277
278 if (phydev->drv->config)
279 phydev->drv->config(phydev);
280
281 return 0;
282 }
283 #endif
284
285 #ifdef CONFIG_MXC_SPI
286 iomux_v3_cfg_t const ecspi1_pads[] = {
287 MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
288 MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
289 MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
290
291 /* CS0 */
292 MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
293 };
294
295 void setup_spinor(void)
296 {
297 imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
298 ARRAY_SIZE(ecspi1_pads));
299 gpio_request(IMX_GPIO_NR(4, 19), "ecspi1_cs");
300 gpio_direction_output(IMX_GPIO_NR(4, 19), 0);
301 }
302
303 int board_spi_cs_gpio(unsigned bus, unsigned cs)
304 {
305 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 19)) : -1;
306 }
307 #endif
308
309 int board_early_init_f(void)
310 {
311 setup_iomux_uart();
312
313 return 0;
314 }
315
316 #ifdef CONFIG_MXC_EPDC
317 static iomux_v3_cfg_t const epdc_enable_pads[] = {
318 MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
319 MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
320 MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
321 MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
322 MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
323 MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
324 MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
325 MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
326 MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
327 MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
328 MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
329 MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),
330 MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
331 MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
332 MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
333 MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
334 MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
335 MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
336 MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),
337 MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),
338 MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
339 MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
340 };
341
342 static iomux_v3_cfg_t const epdc_disable_pads[] = {
343 MX7D_PAD_EPDC_DATA00__GPIO2_IO0,
344 MX7D_PAD_EPDC_DATA01__GPIO2_IO1,
345 MX7D_PAD_EPDC_DATA02__GPIO2_IO2,
346 MX7D_PAD_EPDC_DATA03__GPIO2_IO3,
347 MX7D_PAD_EPDC_DATA04__GPIO2_IO4,
348 MX7D_PAD_EPDC_DATA05__GPIO2_IO5,
349 MX7D_PAD_EPDC_DATA06__GPIO2_IO6,
350 MX7D_PAD_EPDC_DATA07__GPIO2_IO7,
351 MX7D_PAD_EPDC_SDCLK__GPIO2_IO16,
352 MX7D_PAD_EPDC_SDLE__GPIO2_IO17,
353 MX7D_PAD_EPDC_SDOE__GPIO2_IO18,
354 MX7D_PAD_EPDC_SDSHR__GPIO2_IO19,
355 MX7D_PAD_EPDC_SDCE0__GPIO2_IO20,
356 MX7D_PAD_EPDC_SDCE1__GPIO2_IO21,
357 MX7D_PAD_EPDC_SDCE2__GPIO2_IO22,
358 MX7D_PAD_EPDC_SDCE3__GPIO2_IO23,
359 MX7D_PAD_EPDC_GDCLK__GPIO2_IO24,
360 MX7D_PAD_EPDC_GDOE__GPIO2_IO25,
361 MX7D_PAD_EPDC_GDRL__GPIO2_IO26,
362 MX7D_PAD_EPDC_GDSP__GPIO2_IO27,
363 MX7D_PAD_EPDC_BDR0__GPIO2_IO28,
364 MX7D_PAD_EPDC_BDR1__GPIO2_IO29,
365 };
366
367 vidinfo_t panel_info = {
368 .vl_refresh = 85,
369 .vl_col = 1024,
370 .vl_row = 758,
371 .vl_pixclock = 40000000,
372 .vl_left_margin = 12,
373 .vl_right_margin = 76,
374 .vl_upper_margin = 4,
375 .vl_lower_margin = 5,
376 .vl_hsync = 12,
377 .vl_vsync = 2,
378 .vl_sync = 0,
379 .vl_mode = 0,
380 .vl_flag = 0,
381 .vl_bpix = 3,
382 .cmap = 0,
383 };
384
385 struct epdc_timing_params panel_timings = {
386 .vscan_holdoff = 4,
387 .sdoed_width = 10,
388 .sdoed_delay = 20,
389 .sdoez_width = 10,
390 .sdoez_delay = 20,
391 .gdclk_hp_offs = 524,
392 .gdsp_offs = 327,
393 .gdoe_offs = 0,
394 .gdclk_offs = 19,
395 .num_ce = 1,
396 };
397
398 static void setup_epdc_power(void)
399 {
400 /* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */
401 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
402 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
403
404 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
405 IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0);
406
407 /* Setup epdc voltage */
408
409 /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
410 imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
411 MUX_PAD_CTRL(EPDC_PAD_CTRL));
412 gpio_request(IMX_GPIO_NR(2, 31), "epdc_pwrstat");
413 gpio_direction_input(IMX_GPIO_NR(2, 31));
414
415 /* EPDC_VCOM0 - GPIO4[14] for VCOM control */
416 imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
417 MUX_PAD_CTRL(EPDC_PAD_CTRL));
418
419 /* Set as output */
420 gpio_request(IMX_GPIO_NR(4, 14), "epdc_vcom0");
421 gpio_direction_output(IMX_GPIO_NR(4, 14), 1);
422
423 /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */
424 imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 |
425 MUX_PAD_CTRL(EPDC_PAD_CTRL));
426 /* Set as output */
427 gpio_request(IMX_GPIO_NR(4, 23), "epdc_pwrwakeup");
428 gpio_direction_output(IMX_GPIO_NR(4, 23), 1);
429
430 /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */
431 imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 |
432 MUX_PAD_CTRL(EPDC_PAD_CTRL));
433 /* Set as output */
434 gpio_request(IMX_GPIO_NR(4, 20), "epdc_pwrctrl0");
435 gpio_direction_output(IMX_GPIO_NR(4, 20), 1);
436 }
437
438 static void epdc_enable_pins(void)
439 {
440 /* epdc iomux settings */
441 imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
442 ARRAY_SIZE(epdc_enable_pads));
443 }
444
445 static void epdc_disable_pins(void)
446 {
447 /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */
448 imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
449 ARRAY_SIZE(epdc_disable_pads));
450 }
451
452 static void setup_epdc(void)
453 {
454 /*** epdc Maxim PMIC settings ***/
455
456 /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
457 imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
458 MUX_PAD_CTRL(EPDC_PAD_CTRL));
459
460 /* EPDC_VCOM0 - GPIO4[14] for VCOM control */
461 imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
462 MUX_PAD_CTRL(EPDC_PAD_CTRL));
463
464 /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */
465 imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 |
466 MUX_PAD_CTRL(EPDC_PAD_CTRL));
467
468 /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */
469 imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 |
470 MUX_PAD_CTRL(EPDC_PAD_CTRL));
471
472 /* Set pixel clock rates for EPDC in clock.c */
473
474 panel_info.epdc_data.wv_modes.mode_init = 0;
475 panel_info.epdc_data.wv_modes.mode_du = 1;
476 panel_info.epdc_data.wv_modes.mode_gc4 = 3;
477 panel_info.epdc_data.wv_modes.mode_gc8 = 2;
478 panel_info.epdc_data.wv_modes.mode_gc16 = 2;
479 panel_info.epdc_data.wv_modes.mode_gc32 = 2;
480
481 panel_info.epdc_data.epdc_timings = panel_timings;
482
483 setup_epdc_power();
484 }
485
486 void epdc_power_on(void)
487 {
488 unsigned int reg;
489 struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
490
491 /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
492 gpio_set_value(IMX_GPIO_NR(4, 20), 1);
493 udelay(1000);
494
495 /* Enable epdc signal pin */
496 epdc_enable_pins();
497
498 /* Set PMIC Wakeup to high - enable Display power */
499 gpio_set_value(IMX_GPIO_NR(4, 23), 1);
500
501 /* Wait for PWRGOOD == 1 */
502 while (1) {
503 reg = readl(&gpio_regs->gpio_psr);
504 if (!(reg & (1 << 31)))
505 break;
506
507 udelay(100);
508 }
509
510 /* Enable VCOM */
511 gpio_set_value(IMX_GPIO_NR(4, 14), 1);
512
513 udelay(500);
514 }
515
516 void epdc_power_off(void)
517 {
518 /* Set PMIC Wakeup to low - disable Display power */
519 gpio_set_value(IMX_GPIO_NR(4, 23), 0);
520
521 /* Disable VCOM */
522 gpio_set_value(IMX_GPIO_NR(4, 14), 0);
523
524 epdc_disable_pins();
525
526 /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
527 gpio_set_value(IMX_GPIO_NR(4, 20), 0);
528 }
529 #endif
530
531 int board_init(void)
532 {
533 /* address of boot parameters */
534 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
535
536 /* Reset peripherals */
537 imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads));
538
539 gpio_request(IMX_GPIO_NR(1, 3), "per_rst");
540 gpio_direction_output(IMX_GPIO_NR(1, 3) , 0);
541 udelay(500);
542 gpio_set_value(IMX_GPIO_NR(1, 3), 1);
543
544 #ifdef CONFIG_FEC_MXC
545 setup_fec();
546 #endif
547
548 #ifdef CONFIG_MXC_SPI
549 setup_spinor();
550 #endif
551
552 #ifdef CONFIG_FSL_QSPI
553 board_qspi_init();
554 #endif
555
556 #ifdef CONFIG_MXC_EPDC
557 setup_epdc();
558 #endif
559
560 return 0;
561 }
562
563 #ifdef CONFIG_CMD_BMODE
564 static const struct boot_mode board_boot_modes[] = {
565 /* 4 bit bus width */
566 {"sd1", MAKE_CFGVAL(0x10, 0x12, 0x00, 0x00)},
567 {"sd2", MAKE_CFGVAL(0x10, 0x16, 0x00, 0x00)},
568 {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)},
569 {"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},
570 {NULL, 0},
571 };
572 #endif
573
574 #ifdef CONFIG_DM_PMIC
575 int power_init_board(void)
576 {
577 struct udevice *dev;
578 int ret, dev_id, rev_id, reg;
579
580 ret = pmic_get("pfuze3000", &dev);
581 if (ret == -ENODEV)
582 return 0;
583 if (ret != 0)
584 return ret;
585
586 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
587 rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
588 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
589
590 /* disable Low Power Mode during standby mode */
591 reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
592 reg |= 0x1;
593 pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
594
595 /* SW1A/1B mode set to APS/APS */
596 reg = 0x8;
597 pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
598 pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
599
600 /* SW1A/1B standby voltage set to 0.975V */
601 reg = 0xb;
602 pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
603 pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
604
605 /* below are for LPSR mode support */
606 reg = pmic_reg_read(dev, PFUZE3000_SW3MODE);
607 reg |= 0x20;
608 pmic_reg_write(dev, PFUZE3000_SW3MODE, reg);
609
610 reg = pmic_reg_read(dev, PFUZE3000_VLDO1CTL);
611 reg |= 0x80;
612 pmic_reg_write(dev, PFUZE3000_VLDO1CTL, reg);
613
614 reg = pmic_reg_read(dev, PFUZE3000_VLDO3CTL);
615 reg |= 0x80;
616 pmic_reg_write(dev, PFUZE3000_VLDO3CTL, reg);
617
618 reg = pmic_reg_read(dev, PFUZE3000_SW2MODE);
619 reg |= 0x20;
620 pmic_reg_write(dev, PFUZE3000_SW2MODE, reg);
621
622 /* set SW1B normal voltage to 0.975V */
623 reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
624 reg &= ~0x1f;
625 reg |= PFUZE3000_SW1AB_SETP(9750);
626 pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
627
628 return 0;
629 }
630 #endif
631
632 int board_late_init(void)
633 {
634 #ifdef CONFIG_CMD_BMODE
635 add_board_boot_modes(board_boot_modes);
636 #endif
637
638 #ifdef CONFIG_ENV_IS_IN_MMC
639 board_late_mmc_env_init();
640 #endif
641
642 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
643
644 set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
645
646 return 0;
647 }
648
649 u32 get_board_rev(void)
650 {
651 return get_cpu_rev();
652 }
653
654 int checkboard(void)
655 {
656 puts("Board: MX7D 12x12 LPDDR3 ARM2\n");
657
658 return 0;
659 }
660
board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S
Diff comments   View file @ 63a4024
File was created 1 /*
2 * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <config.h>
9
10 /* DDR script */
11 .macro imx7d_ddrphy_latency_setting
12 ldr r2, =ANATOP_BASE_ADDR
13 ldr r3, [r2, #0x800]
14 and r3, r3, #0xFF
15 cmp r3, #0x11
16 bne TUNE_END
17
18 /*TO 1.1*/
19 ldr r1, =0x1c1c1c1c
20 str r1, [r0, #0x7c]
21 ldr r1, =0x1c1c1c1c
22 str r1, [r0, #0x80]
23 ldr r1, =0x30301c1c
24 str r1, [r0, #0x84]
25 ldr r1, =0x00000030
26 str r1, [r0, #0x88]
27 ldr r1, =0x30303030
28 str r1, [r0, #0x6c]
29
30 TUNE_END:
31 .endm
32
33 .macro imx7d_12x12_lpddr3_arm2_setting
34
35 /* check whether it is a LPSR resume */
36 ldr r1, =0x30270000
37 ldr r7, [r1]
38 cmp r7, #0
39 beq 16f
40
41 /* disable wdog powerdown counter */
42 ldr r0, =0x30280000
43 ldrh r1, =0x0
44 strh r1, [r0, #0x8]
45
46 /* initialize AIPs 1-3 port */
47 ldr r0, =0x301f0000
48 ldr r1, =0x77777777
49 str r1, [r0]
50 str r1, [r0, #0x4]
51 ldr r1, =0x0
52 str r1, [r0, #0x40]
53 str r1, [r0, #0x44]
54 str r1, [r0, #0x48]
55 str r1, [r0, #0x4c]
56 str r1, [r0, #0x50]
57
58 ldr r0, =0x305f0000
59 ldr r1, =0x77777777
60 str r1, [r0]
61 str r1, [r0, #0x4]
62 ldr r1, =0x0
63 str r1, [r0, #0x40]
64 str r1, [r0, #0x44]
65 str r1, [r0, #0x48]
66 str r1, [r0, #0x4c]
67 str r1, [r0, #0x50]
68
69 ldr r0, =0x309f0000
70 ldr r1, =0x77777777
71 str r1, [r0]
72 str r1, [r0, #0x4]
73 ldr r1, =0x0
74 str r1, [r0, #0x40]
75 str r1, [r0, #0x44]
76 str r1, [r0, #0x48]
77 str r1, [r0, #0x4c]
78 str r1, [r0, #0x50]
79
80 ldr r1, =0x30360000
81 ldr r2, =0x30390000
82 ldr r3, =0x307a0000
83 ldr r4, =0x30790000
84 ldr r10, =0x30380000
85 ldr r11, =0x30340000
86
87 /* turn on ddr power */
88 ldr r7, =(0x1 << 29)
89 str r7, [r1, #0x388]
90
91 ldr r6, =50
92 1:
93 subs r6, r6, #0x1
94 bne 1b
95
96 /* clear ddr_phy reset */
97 ldr r6, =0x1000
98 ldr r7, [r2, r6]
99 orr r7, r7, #0x3
100 str r7, [r2, r6]
101 ldr r7, [r2, r6]
102 bic r7, r7, #0x1
103 str r7, [r2, r6]
104
105 /* restore DDRC */
106 ldr r6, =0x0
107 ldr r7, =0x03040008
108 str r7, [r3, r6]
109
110 ldr r6, =0x1a0
111 ldr r7, =0x80400003
112 str r7, [r3, r6]
113
114 ldr r6, =0x1a4
115 ldr r7, =0x00100020
116 str r7, [r3, r6]
117
118 ldr r6, =0x1a8
119 ldr r7, =0x80100004
120 str r7, [r3, r6]
121
122 ldr r6, =0x64
123 ldr r7, =0x00200038
124 str r7, [r3, r6]
125
126 ldr r6, =0xd0
127 ldr r7, =0xc0350001
128 str r7, [r3, r6]
129
130 ldr r6, =0xdc
131 ldr r7, =0x00C3000A
132 str r7, [r3, r6]
133
134 ldr r6, =0xe0
135 ldr r7, =0x00010000
136 str r7, [r3, r6]
137
138 ldr r6, =0xe4
139 ldr r7, =0x00110006
140 str r7, [r3, r6]
141
142 ldr r6, =0xf4
143 ldr r7, =0x0000033F
144 str r7, [r3, r6]
145
146 ldr r6, =0x100
147 ldr r7, =0x0A0E110B
148 str r7, [r3, r6]
149
150 ldr r6, =0x104
151 ldr r7, =0x00020211
152 str r7, [r3, r6]
153
154 ldr r6, =0x108
155 ldr r7, =0x03060708
156 str r7, [r3, r6]
157
158 ldr r6, =0x10c
159 ldr r7, =0x00A0500C
160 str r7, [r3, r6]
161
162 ldr r6, =0x110
163 ldr r7, =0x05020307
164 str r7, [r3, r6]
165
166 ldr r6, =0x114
167 ldr r7, =0x02020404
168 str r7, [r3, r6]
169
170 ldr r6, =0x118
171 ldr r7, =0x02020003
172 str r7, [r3, r6]
173
174 ldr r6, =0x11c
175 ldr r7, =0x00000202
176 str r7, [r3, r6]
177
178 ldr r6, =0x120
179 ldr r7, =0x00000202
180 str r7, [r3, r6]
181
182 ldr r6, =0x180
183 ldr r7, =0x00600018
184 str r7, [r3, r6]
185
186 ldr r6, =0x184
187 ldr r7, =0x00e00100
188 str r7, [r3, r6]
189
190 ldr r6, =0x190
191 ldr r7, =0x02098205
192 str r7, [r3, r6]
193
194 ldr r6, =0x194
195 ldr r7, =0x00060303
196 str r7, [r3, r6]
197
198 ldr r6, =0x200
199 ldr r7, =0x00000016
200 str r7, [r3, r6]
201
202 ldr r6, =0x204
203 ldr r7, =0x00090909
204 str r7, [r3, r6]
205
206 ldr r6, =0x210
207 ldr r7, =0xF00
208 str r7, [r3, r6]
209
210 ldr r6, =0x214
211 ldr r7, =0x08080808
212 str r7, [r3, r6]
213
214 ldr r6, =0x218
215 ldr r7, =0x0f0f0808
216 str r7, [r3, r6]
217
218 ldr r6, =0x240
219 ldr r7, =0x06000600
220 str r7, [r3, r6]
221
222 ldr r6, =0x244
223 ldr r7, =0x00000000
224 str r7, [r3, r6]
225
226 ldr r7, =0x20
227 str r7, [r3, #0x30]
228 ldr r7, =0x0
229 str r7, [r3, #0x1b0]
230
231 /* do PHY, clear ddr_phy reset */
232 ldr r6, =0x1000
233 ldr r7, [r2, r6]
234 bic r7, r7, #0x2
235 str r7, [r2, r6]
236
237 ldr r7, [r1, #0x800]
238 and r7, r7, #0xFF
239 cmp r7, #0x11
240 bne 2f
241
242 /* for TO1.1 */
243 ldr r7, [r11]
244 bic r7, r7, #(1 << 27)
245 str r7, [r11]
246 ldr r7, [r11]
247 bic r7, r7, #(1 << 29)
248 str r7, [r11]
249 2:
250 /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
251 ldr r7, =(0x1 << 30)
252 str r7, [r1, #0x388]
253 ldr r7, =(0x1 << 30)
254 str r7, [r1, #0x384]
255
256 /* need to delay ~5mS */
257 ldr r6, =0x100000
258 3:
259 subs r6, r6, #0x1
260 bne 3b
261
262 /* restore DDR PHY */
263 ldr r6, =0x0
264 ldr r7, =0x17421E40
265 str r7, [r4, r6]
266
267 ldr r6, =0x4
268 ldr r7, =0x10210100
269 str r7, [r4, r6]
270
271 ldr r6, =0x8
272 ldr r7, =0x00010000
273 str r7, [r4, r6]
274
275 ldr r6, =0x10
276 ldr r7, =0x0007080C
277 str r7, [r4, r6]
278
279 ldr r6, =0xb0
280 ldr r7, =0x1010007e
281 str r7, [r4, r6]
282
283 ldr r7, [r1, #0x800]
284 and r7, r7, #0xFF
285 cmp r7, #0x11
286 bne 4f
287
288 ldr r6, =0x7c
289 ldr r7, =0x1c1c1c1c
290 str r7, [r4, r6]
291
292 ldr r6, =0x80
293 ldr r7, =0x1c1c1c1c
294 str r7, [r4, r6]
295
296 ldr r6, =0x84
297 ldr r7, =0x30301c1c
298 str r7, [r4, r6]
299
300 ldr r6, =0x88
301 ldr r7, =0x00000030
302 str r7, [r4, r6]
303
304 ldr r6, =0x6c
305 ldr r7, =0x30303030
306 str r7, [r4, r6]
307
308 ldr r6, =0x1c
309 ldr r7, =0x01010000
310 str r7, [r4, r6]
311
312 ldr r6, =0x9c
313 ldr r7, =0x0DB60D6E
314 str r7, [r4, r6]
315
316 b 5f
317
318 4:
319 ldr r6, =0x1c
320 ldr r7, =0x01010000
321 str r7, [r4, r6]
322
323 ldr r6, =0x9c
324 ldr r7, =0x00000b24
325 str r7, [r4, r6]
326
327 5:
328 ldr r6, =0x20
329 ldr r7, =0x0a0a0a0a
330 str r7, [r4, r6]
331
332 ldr r6, =0x30
333 ldr r7, =0x06060606
334 str r7, [r4, r6]
335
336 ldr r6, =0x50
337 ldr r7, =0x01000008
338 str r7, [r4, r6]
339
340 ldr r6, =0x50
341 ldr r7, =0x00000008
342 str r7, [r4, r6]
343
344 ldr r6, =0xc0
345 ldr r7, =0x0e487304
346 str r7, [r4, r6]
347
348 ldr r6, =0xc0
349 ldr r7, =0x0e4c7304
350 str r7, [r4, r6]
351
352 ldr r6, =0xc0
353 ldr r7, =0x0e4c7306
354 str r7, [r4, r6]
355
356 6:
357 ldr r7, [r4, #0xc4]
358 tst r7, #0x1
359 beq 6b
360
361 ldr r6, =0xc0
362 ldr r7, =0x0e487304
363 str r7, [r4, r6]
364
365 ldr r7, =0x0
366 add r9, r10, #0x4000
367 str r7, [r9, #0x130]
368
369 ldr r7, =0x170
370 orr r7, r7, #0x8
371 str r7, [r11, #0x20]
372
373 ldr r7, =0x2
374 add r9, r10, #0x4000
375 str r7, [r9, #0x130]
376
377 ldr r7, =0xf
378 str r7, [r4, #0x18]
379
380 /* wait until self-refresh mode entered */
381 11:
382 ldr r7, [r3, #0x4]
383 and r7, r7, #0x3
384 cmp r7, #0x3
385 bne 11b
386 ldr r7, =0x0
387 str r7, [r3, #0x320]
388 ldr r7, =0x1
389 str r7, [r3, #0x1b0]
390 ldr r7, =0x1
391 str r7, [r3, #0x320]
392 12:
393 ldr r7, [r3, #0x324]
394 and r7, r7, #0x1
395 cmp r7, #0x1
396 bne 12b
397 13:
398 ldr r7, [r3, #0x4]
399 and r7, r7, #0x20
400 cmp r7, #0x20
401 bne 13b
402
403 /* let DDR out of self-refresh */
404 ldr r7, =0x0
405 str r7, [r3, #0x30]
406 14:
407 ldr r7, [r3, #0x4]
408 and r7, r7, #0x30
409 cmp r7, #0x0
410 bne 14b
411
412 15:
413 ldr r7, [r3, #0x4]
414 and r7, r7, #0x3
415 cmp r7, #0x1
416 bne 15b
417
418 imx7_qos_setting
419
420 /* enable port */
421 ldr r7, =0x1
422 str r7, [r3, #0x490]
423
424 /* jump to kernel resume */
425 ldr r1, =0x30270000
426 ldr r7, [r1]
427
428 mov pc, r7
429 16:
430 /* Configure ocram_epdc */
431 ldr r0, =IOMUXC_GPR_BASE_ADDR
432 ldr r1, =0x4f400005
433 str r1, [r0, #0x4]
434
435 /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
436 ldr r0, =ANATOP_BASE_ADDR
437 ldr r1, =(0x1 << 30)
438 str r1, [r0, #0x388]
439 str r1, [r0, #0x384]
440
441 ldr r0, =SRC_BASE_ADDR
442 ldr r1, =0x2
443 ldr r2, =0x1000
444 str r1, [r0, r2]
445
446 ldr r0, =DDRC_IPS_BASE_ADDR
447 ldr r1, =0x03040008
448 str r1, [r0]
449 ldr r1, =0x00200038
450 str r1, [r0, #0x64]
451 ldr r1, =0x1
452 str r1, [r0, #0x490]
453 ldr r1, =0x00350001
454 str r1, [r0, #0xd0]
455 ldr r1, =0x00c3000a
456 str r1, [r0, #0xdc]
457 ldr r1, =0x00010000
458 str r1, [r0, #0xe0]
459 ldr r1, =0x00110006
460 str r1, [r0, #0xe4]
461 ldr r1, =0x33f
462 str r1, [r0, #0xf4]
463 ldr r1, =0x0a0e110b
464 str r1, [r0, #0x100]
465 ldr r1, =0x00020211
466 str r1, [r0, #0x104]
467 ldr r1, =0x03060708
468 str r1, [r0, #0x108]
469 ldr r1, =0x00a0500c
470 str r1, [r0, #0x10c]
471 ldr r1, =0x05020307
472 str r1, [r0, #0x110]
473 ldr r1, =0x02020404
474 str r1, [r0, #0x114]
475 ldr r1, =0x02020003
476 str r1, [r0, #0x118]
477 ldr r1, =0x00000202
478 str r1, [r0, #0x11c]
479 ldr r1, =0x00000202
480 str r1, [r0, #0x120]
481 ldr r1, =0x00600018
482 str r1, [r0, #0x180]
483 ldr r1, =0x00e00100
484 str r1, [r0, #0x184]
485 ldr r1, =0x02098205
486 str r1, [r0, #0x190]
487 ldr r1, =0x00060303
488 str r1, [r0, #0x194]
489 ldr r1, =0x80400003
490 str r1, [r0, #0x1a0]
491 ldr r1, =0x00100020
492 str r1, [r0, #0x1a4]
493 ldr r1, =0x80100004
494 str r1, [r0, #0x1a8]
495
496 ldr r1, =0x00000016
497 str r1, [r0, #0x200]
498 ldr r1, =0x00090909
499 str r1, [r0, #0x204]
500 ldr r1, =0x00000f00
501 str r1, [r0, #0x210]
502 ldr r1, =0x08080808
503 str r1, [r0, #0x214]
504 ldr r1, =0x0f0f0808
505 str r1, [r0, #0x218]
506
507 ldr r1, =0x06000600
508 str r1, [r0, #0x240]
509 mov r1, #0x0
510 str r1, [r0, #0x244]
511
512 ldr r0, =SRC_BASE_ADDR
513 mov r1, #0x0
514 ldr r2, =0x1000
515 str r1, [r0, r2]
516
517 ldr r0, =DDRPHY_IPS_BASE_ADDR
518 ldr r1, =0x17421e40
519 str r1, [r0]
520 ldr r1, =0x10210100
521 str r1, [r0, #0x4]
522 ldr r1, =0x00010000
523 str r1, [r0, #0x8]
524 ldr r1, =0x0007080c
525 str r1, [r0, #0x10]
526 imx7d_ddrphy_latency_setting
527 ldr r1, =0x1010007e
528 str r1, [r0, #0xb0]
529 ldr r1, =0x01010000
530 str r1, [r0, #0x1c]
531
532 ldr r2, =ANATOP_BASE_ADDR
533 ldr r3, [r2, #0x800]
534 and r3, r3, #0xFF
535 cmp r3, #0x11
536 bne 17f
537
538 ldr r1, =0x0db60d6e
539 str r1, [r0, #0x9c]
540 b 18f
541 17:
542 ldr r1, =0x00000b24
543 str r1, [r0, #0x9c]
544 18:
545 ldr r1, =0x06060606
546 str r1, [r0, #0x30]
547 ldr r1, =0x0a0a0a0a
548 str r1, [r0, #0x20]
549 ldr r1, =0x01000008
550 str r1, [r0, #0x50]
551 ldr r1, =0x00000008
552 str r1, [r0, #0x50]
553
554 ldr r1, =0x0000000f
555 str r1, [r0, #0x18]
556 ldr r1, =0x0e487304
557 str r1, [r0, #0xc0]
558 ldr r1, =0x0e4c7304
559 str r1, [r0, #0xc0]
560 ldr r1, =0x0e4c7306
561 str r1, [r0, #0xc0]
562
563 wait_zq:
564 ldr r1, [r0, #0xc4]
565 tst r1, #0x1
566 beq wait_zq
567
568 ldr r1, =0x0e487304
569 str r1, [r0, #0xc0]
570
571 ldr r0, =CCM_BASE_ADDR
572 mov r1, #0x0
573 ldr r2, =0x4130
574 str r1, [r0, r2]
575 ldr r0, =IOMUXC_GPR_BASE_ADDR
576 mov r1, #0x178
577 str r1, [r0, #0x20]
578 ldr r0, =CCM_BASE_ADDR
579 mov r1, #0x2
580 ldr r2, =0x4130
581 str r1, [r0, r2]
582
583 ldr r0, =DDRC_IPS_BASE_ADDR
584 wait_stat:
585 ldr r1, [r0, #0x4]
586 tst r1, #0x1
587 beq wait_stat
588 .endm
589
590 .macro imx7_clock_gating
591 #ifdef CONFIG_IMX_OPTEE
592 ldr r0, =0x30340024
593 ldr r1, =0x1
594 str r1, [r0]
595 #endif
596 .endm
597
598 .macro imx7_qos_setting
599 ldr r0, =REGS_QOS_BASE
600 ldr r1, =0
601 str r1, [r0, #0]
602
603 ldr r1, =0
604 str r1, [r0, #0x60]
605
606 ldr r0, =REGS_QOS_EPDC
607 ldr r1, =0
608 str r1, [r0, #0]
609
610 ldr r0, =REGS_QOS_PXP0
611 ldr r1, =0
612 str r1, [r0, #0]
613
614 ldr r0, =REGS_QOS_PXP1
615 ldr r1, =0
616 str r1, [r0, #0]
617
618 ldr r0, =REGS_QOS_EPDC
619 ldr r1, =0x0f020f22
620 str r1, [r0, #0xd0]
621 str r1, [r0, #0xe0]
622
623 ldr r0, =REGS_QOS_PXP0
624 ldr r1, =0x1
625 str r1, [r0, #0]
626 ldr r0, =REGS_QOS_PXP1
627 str r1, [r0, #0]
628
629 ldr r0, =REGS_QOS_PXP0
630 ldr r1, =0x0f020222
631 str r1, [r0, #0x50]
632 ldr r0, =REGS_QOS_PXP1
633 str r1, [r0, #0x50]
634
635 ldr r0, =REGS_QOS_PXP0
636 ldr r1, =0x0f020222
637 str r1, [r0, #0x60]
638 ldr r0, =REGS_QOS_PXP1
639 str r1, [r0, #0x60]
640
641 ldr r0, =REGS_QOS_PXP0
642 ldr r1, =0x0f020422
643 str r1, [r0, #0x70]
644 ldr r0, =REGS_QOS_PXP1
645 str r1, [r0, #0x70]
646
647 ldr r0, =IOMUXC_GPR_BASE_ADDR
648 ldr r1, =0xe080
649 str r1, [r0, #0x34]
650 .endm
651
652 .macro imx7_ddr_setting
653 imx7d_12x12_lpddr3_arm2_setting
654 .endm
655
656 /* include the common plugin code here */
657 #include <asm/arch/mx7_plugin.S>
658
include/configs/mx7d_12x12_ddr3_arm2.h
Diff comments   View file @ 63a4024
File was created 1 /*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP
4 *
5 * Configuration settings for the Freescale i.MX7D 12x12 DDR3 ARM2 board.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #ifndef __MX7D_12X12_DDR3_ARM2_CONFIG_H
11 #define __MX7D_12X12_DDR3_ARM2_CONFIG_H
12
13 #define CONFIG_SYS_FSL_USDHC_NUM 2
14 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC3 */
15 #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
16 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC3 */
17
18 #define PHYS_SDRAM_SIZE SZ_1G
19
20 #ifdef CONFIG_SPI_BOOT
21 #define CONFIG_MXC_SPI
22 #endif
23
24 #ifdef CONFIG_MXC_SPI
25 #define CONFIG_CMD_SF
26 #define CONFIG_SPI_FLASH
27 #define CONFIG_SPI_FLASH_ATMEL
28 #define CONFIG_SF_DEFAULT_BUS 3
29 #define CONFIG_SF_DEFAULT_SPEED 20000000
30 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
31 #define CONFIG_SF_DEFAULT_CS 0
32 #endif
33
34 #include "mx7d_arm2.h"
35
36 #endif
37
include/configs/mx7d_12x12_lpddr3_arm2.h
Diff comments   View file @ 63a4024
File was created 1 /*
2 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
3 *
4 * Configuration settings for the Freescale i.MX7D 12x12 LPDDR3 ARM2 board.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #ifndef __MX7D_12X12_LPDDR3_ARM2_CONFIG_H
10 #define __MX7D_12X12_LPDDR3_ARM2_CONFIG_H
11
12 #define CONFIG_SYS_FSL_USDHC_NUM 3
13 #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
14 #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
15 #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
16
17 #define PHYS_SDRAM_SIZE SZ_2G
18
19 #define CONFIG_FEC_MXC
20 #define CONFIG_MII
21 #define CONFIG_FEC_XCV_TYPE RGMII
22 #ifdef CONFIG_DM_ETH
23 #define CONFIG_ETHPRIME "eth0"
24 #else
25 #define CONFIG_ETHPRIME "FEC"
26 #endif
27 #define CONFIG_FEC_MXC_PHYADDR 1
28
29 #define CONFIG_PHYLIB
30 #define CONFIG_PHY_ATHEROS
31
32 /* ENET1 */
33 #define IMX_FEC_BASE ENET_IPS_BASE_ADDR
34
35 #ifdef CONFIG_QSPI_BOOT
36 #define CONFIG_FSL_QSPI
37 #elif defined CONFIG_SPI_BOOT
38 #define CONFIG_MXC_SPI
39 #endif
40
41 #ifdef CONFIG_MXC_SPI
42 #define CONFIG_SF_DEFAULT_BUS 0
43 #define CONFIG_SF_DEFAULT_SPEED 20000000
44 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
45 #define CONFIG_SF_DEFAULT_CS 0
46 #endif
47
48 /* #define CONFIG_SPLASH_SCREEN*/
49 /* #define CONFIG_MXC_EPDC*/
50
51 #include "mx7d_arm2.h"
52
53 #endif
54
include/configs/mx7d_arm2.h
Diff comments   View file @ 63a4024
File was created 1 /*
2 * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
3 *
4 * Configuration settings for the Freescale i.MX7D ARM2 board.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #ifndef __MX7D_ARM2_CONFIG_H
10 #define __MX7D_ARM2_CONFIG_H
11
12 #include "mx7_common.h"
13
14 #define CONFIG_DBG_MONITOR
15
16 #define CONFIG_CMDLINE_TAG
17 #define CONFIG_SETUP_MEMORY_TAGS
18 #define CONFIG_INITRD_TAG
19 #define CONFIG_REVISION_TAG
20
21 /* Size of malloc() pool */
22 #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
23
24
25 #define CONFIG_MXC_UART
26 #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
27
28 #define CONFIG_IMX_THERMAL
29
30 /* MMC Configs */
31 #define CONFIG_FSL_ESDHC
32 #define CONFIG_FSL_USDHC
33 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
34
35 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
36
37 #define CONFIG_BAUDRATE 115200
38
39 #undef CONFIG_BOOTM_NETBSD
40 #undef CONFIG_BOOTM_PLAN9
41 #undef CONFIG_BOOTM_RTEMS
42
43 #undef CONFIG_CMD_EXPORTENV
44 #undef CONFIG_CMD_IMPORTENV
45
46 /* allow to overwrite serial and ethaddr */
47 #define CONFIG_ENV_OVERWRITE
48 #define CONFIG_CONS_INDEX 1
49
50 /* I2C configs */
51 #define CONFIG_SYS_I2C_MXC
52 #define CONFIG_SYS_I2C_SPEED 100000
53
54 #undef CONFIG_CMD_IMLS
55
56 #define CONFIG_LOADADDR 0x80800000
57 #define CONFIG_SYS_TEXT_BASE 0x87800000
58
59 #ifdef CONFIG_DM_SPI
60 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x68000000 /* Set to QSPI1 B flash at default */
61 #define SF_QSPI1_B_CS_NUM 2
62 #define SF_QSPI1_B_BUS_NUM 1
63 #else
64 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x62000000 /* Set to QSPI1 B flash at default */
65 #define SF_QSPI1_B_CS_NUM 1
66 #define SF_QSPI1_B_BUS_NUM 0
67 #endif
68
69 #ifdef CONFIG_IMX_BOOTAUX
70
71 #define UPDATE_M4_ENV \
72 "m4image=m4_qspi.bin\0" \
73 "m4_qspi_cs="__stringify(SF_QSPI1_B_CS_NUM)"\0" \
74 "m4_qspi_bus="__stringify(SF_QSPI1_B_BUS_NUM)"\0" \
75 "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
76 "update_m4_from_sd=" \
77 "if sf probe ${m4_qspi_bus}:${m4_qspi_cs}; then " \
78 "if run loadm4image; then " \
79 "setexpr fw_sz ${filesize} + 0xffff; " \
80 "setexpr fw_sz ${fw_sz} / 0x10000; " \
81 "setexpr fw_sz ${fw_sz} * 0x10000; " \
82 "sf erase 0x0 ${fw_sz}; " \
83 "sf write ${loadaddr} 0x0 ${filesize}; " \
84 "fi; " \
85 "fi\0" \
86 "m4boot=sf probe ${m4_qspi_bus}:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
87 #else
88 #define UPDATE_M4_ENV ""
89 #endif
90
91 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
92
93 #define CONFIG_MFG_ENV_SETTINGS \
94 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
95 "rdinit=/linuxrc " \
96 "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
97 "g_mass_storage.file=/fat g_mass_storage.ro=1 " \
98 "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
99 "g_mass_storage.iSerialNumber=\"\" "\
100 "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) " \
101 "clk_ignore_unused "\
102 "\0" \
103 "initrd_addr=0x83800000\0" \
104 "initrd_high=0xffffffff\0" \
105 "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
106
107 #if defined(CONFIG_NAND_BOOT)
108 #define CONFIG_EXTRA_ENV_SETTINGS \
109 CONFIG_MFG_ENV_SETTINGS \
110 "panel=MCIMX28LCD\0" \
111 "fdt_addr=0x83000000\0" \
112 "fdt_high=0xffffffff\0" \
113 "console=ttymxc0\0" \
114 "bootargs=console=ttymxc0,115200 ubi.mtd=5 " \
115 "root=ubi0:rootfs rootfstype=ubifs " \
116 "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\
117 "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
118 "nand read ${fdt_addr} 0x5000000 0x100000;"\
119 "bootz ${loadaddr} - ${fdt_addr}\0"
120
121 #else
122 #define CONFIG_EXTRA_ENV_SETTINGS \
123 CONFIG_MFG_ENV_SETTINGS \
124 UPDATE_M4_ENV \
125 "epdc_waveform=epdc_splash.bin\0" \
126 "panel=MCIMX28LCD\0" \
127 "script=boot.scr\0" \
128 "image=zImage\0" \
129 "console=ttymxc0\0" \
130 "fdt_high=0xffffffff\0" \
131 "initrd_high=0xffffffff\0" \
132 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
133 "fdt_addr=0x83000000\0" \
134 "boot_fdt=try\0" \
135 "ip_dyn=yes\0" \
136 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
137 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
138 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
139 "mmcautodetect=yes\0" \
140 "mmcargs=setenv bootargs console=${console},${baudrate} " \
141 "root=${mmcroot}\0" \
142 "loadbootscript=" \
143 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
144 "bootscript=echo Running bootscript from mmc ...; " \
145 "source\0" \
146 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
147 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
148 "mmcboot=echo Booting from mmc ...; " \
149 "run mmcargs; " \
150 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
151 "if run loadfdt; then " \
152 "bootz ${loadaddr} - ${fdt_addr}; " \
153 "else " \
154 "if test ${boot_fdt} = try; then " \
155 "bootz; " \
156 "else " \
157 "echo WARN: Cannot load the DT; " \
158 "fi; " \
159 "fi; " \
160 "else " \
161 "bootz; " \
162 "fi;\0" \
163 "netargs=setenv bootargs console=${console},${baudrate} " \
164 "root=/dev/nfs " \
165 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
166 "netboot=echo Booting from net ...; " \
167 "run netargs; " \
168 "if test ${ip_dyn} = yes; then " \
169 "setenv get_cmd dhcp; " \
170 "else " \
171 "setenv get_cmd tftp; " \
172 "fi; " \
173 "${get_cmd} ${image}; " \
174 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
175 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
176 "bootz ${loadaddr} - ${fdt_addr}; " \
177 "else " \
178 "if test ${boot_fdt} = try; then " \
179 "bootz; " \
180 "else " \
181 "echo WARN: Cannot load the DT; " \
182 "fi; " \
183 "fi; " \
184 "else " \
185 "bootz; " \
186 "fi;\0"
187
188 #define CONFIG_BOOTCOMMAND \
189 "mmc dev ${mmcdev};" \
190 "mmc dev ${mmcdev}; if mmc rescan; then " \
191 "if run loadbootscript; then " \
192 "run bootscript; " \
193 "else " \
194 "if run loadimage; then " \
195 "run mmcboot; " \
196 "else run netboot; " \
197 "fi; " \
198 "fi; " \
199 "else run netboot; fi"
200 #endif
201
202 #define CONFIG_SYS_MEMTEST_START 0x80000000
203 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x40000000)
204
205 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
206 #define CONFIG_SYS_HZ 1000
207
208 /* Physical Memory Map */
209 #define CONFIG_NR_DRAM_BANKS 1
210 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
211
212 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
213 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
214 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
215
216 #define CONFIG_SYS_INIT_SP_OFFSET \
217 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
218 #define CONFIG_SYS_INIT_SP_ADDR \
219 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
220
221 #define CONFIG_ENV_SIZE SZ_8K
222
223 #ifdef CONFIG_FSL_QSPI
224 #define CONFIG_SYS_FSL_QSPI_AHB
225 #define CONFIG_SF_DEFAULT_CS 0
226 #define CONFIG_SF_DEFAULT_SPEED 40000000
227 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
228 #ifdef CONFIG_DM_SPI
229 #define FSL_QSPI_FLASH_NUM 4
230 #define CONFIG_SF_DEFAULT_BUS 1 /* Have set the QSPI to SPI 1 in imx7d.dtsi alias*/
231 #else
232 #define FSL_QSPI_FLASH_NUM 2 /* Non-DM driver only supports 2 flash, one is on A port, another is on B port*/
233 #define CONFIG_SF_DEFAULT_BUS 0
234 #endif
235 #define FSL_QSPI_FLASH_SIZE SZ_64M
236 #define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR
237 #define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR
238 #endif
239
240 #ifdef CONFIG_MTD_NOR_FLASH
241 #define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
242 #define CONFIG_SYS_FLASH_SECT_SIZE (256 * 1024)
243 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
244 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
245 #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
246 #define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
247 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
248 #define CONFIG_SYS_FLASH_EMPTY_INFO
249 #define CONFIG_SYS_FLASH_PROTECTION
250 #endif
251
252 #ifdef CONFIG_NAND_MXS
253 #define CONFIG_CMD_NAND
254 #define CONFIG_CMD_NAND_TRIMFFS
255
256 /* NAND stuff */
257 #define CONFIG_SYS_MAX_NAND_DEVICE 1
258 #define CONFIG_SYS_NAND_BASE 0x40000000
259 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
260 #define CONFIG_SYS_NAND_ONFI_DETECTION
261
262 /* DMA stuff, needed for GPMI/MXS NAND support */
263 #define CONFIG_APBH_DMA
264 #define CONFIG_APBH_DMA_BURST
265 #define CONFIG_APBH_DMA_BURST8
266 #endif
267
268 #if defined(CONFIG_ENV_IS_IN_MMC)
269 #define CONFIG_ENV_OFFSET (14 * SZ_64K)
270 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
271 #define CONFIG_ENV_OFFSET (896 * 1024)
272 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
273 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
274 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
275 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
276 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
277 #elif defined(CONFIG_ENV_IS_IN_FLASH)
278 #undef CONFIG_ENV_SIZE
279 #define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SIZE
280 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE
281 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_FLASH_SECT_SIZE)
282 #elif defined(CONFIG_ENV_IS_IN_NAND)
283 #undef CONFIG_ENV_SIZE
284 #define CONFIG_ENV_OFFSET (60 << 20)
285 #define CONFIG_ENV_SECT_SIZE (128 << 10)
286 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
287 #endif
288
289 #ifdef CONFIG_VIDEO
290 #define CONFIG_VIDEO_MXS
291 #define CONFIG_VIDEO_LOGO
292 #define CONFIG_SPLASH_SCREEN
293 #define CONFIG_SPLASH_SCREEN_ALIGN
294 #define CONFIG_CMD_BMP
295 #define CONFIG_BMP_16BPP
296 #define CONFIG_VIDEO_BMP_RLE8
297 #define CONFIG_VIDEO_BMP_LOGO
298 #define CONFIG_IMX_VIDEO_SKIP
299 #endif
300
301 #if defined(CONFIG_MXC_EPDC)
302 /*
303 * Framebuffer and LCD
304 */
305 #define CONFIG_CMD_BMP
306 #define CONFIG_SPLASH_SCREEN
307
308 #undef LCD_TEST_PATTERN
309 /* #define CONFIG_SPLASH_IS_IN_MMC 1 */
310 #define LCD_BPP LCD_MONOCHROME
311 /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */
312
313 #define CONFIG_WAVEFORM_BUF_SIZE 0x400000
314 #endif
315
316 /* USB Configs */
317 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
318
319 #endif /* __CONFIG_H */
320