Eric Lee / smarc-uboot

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/*

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/*

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*

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*

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* SPDX-License-Identifier: GPL-2.0+

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* SPDX-License-Identifier: GPL-2.0+

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*/

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*/

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#include <asm/arch/clock.h>

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#include <asm/arch/clock.h>

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#include <asm/arch/imx-regs.h>

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#include <asm/arch/imx-regs.h>

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#include <asm/arch/mx7-pins.h>

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#include <asm/arch/mx7-pins.h>

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#include <asm/arch/sys_proto.h>

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#include <asm/arch/sys_proto.h>

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#include <asm/gpio.h>

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#include <asm/gpio.h>

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#include <asm/imx-common/iomux-v3.h>

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#include <asm/imx-common/iomux-v3.h>

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#include <asm/imx-common/boot_mode.h>

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#include <asm/imx-common/boot_mode.h>

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#include <asm/io.h>

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#include <asm/io.h>

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#include <linux/sizes.h>

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#include <linux/sizes.h>

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#include <common.h>

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#include <common.h>

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#include <fsl_esdhc.h>

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#include <fsl_esdhc.h>

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#include <mmc.h>

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#include <mmc.h>

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#include <miiphy.h>

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#include <miiphy.h>

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#include <netdev.h>

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#include <netdev.h>

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#include <power/pmic.h>

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#include <power/pmic.h>

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#include <power/pfuze3000_pmic.h>

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#include <power/pfuze3000_pmic.h>

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#include "pfuze.h"

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#include "pfuze.h"

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#include <pwm.h>

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#include <pwm.h>

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#include <i2c.h>

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#include <i2c.h>

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#include <asm/imx-common/mxc_i2c.h>

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#include <asm/imx-common/mxc_i2c.h>

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#include <asm/arch/crm_regs.h>

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#include <asm/arch/crm_regs.h>

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#include <usb.h>

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#include <usb.h>

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#include <usb/ehci-fsl.h>

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#include <usb/ehci-fsl.h>

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#if defined(CONFIG_MXC_EPDC)

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#if defined(CONFIG_MXC_EPDC)

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#include <lcd.h>

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#include <lcd.h>

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#include <mxc_epdc_fb.h>

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#include <mxc_epdc_fb.h>

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#endif

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#endif

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#include <asm/imx-common/video.h>

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#include <asm/imx-common/video.h>

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#include "smarcfimx7.h"

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#include "smarcfimx7.h"

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#ifdef CONFIG_FSL_FASTBOOT

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#ifdef CONFIG_FSL_FASTBOOT

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#include <fsl_fastboot.h>

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#include <fsl_fastboot.h>

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#ifdef CONFIG_ANDROID_RECOVERY

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#ifdef CONFIG_ANDROID_RECOVERY

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#include <recovery.h>

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#include <recovery.h>

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#endif

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#endif

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#endif /*CONFIG_FSL_FASTBOOT*/

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#endif /*CONFIG_FSL_FASTBOOT*/

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DECLARE_GLOBAL_DATA_PTR;

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DECLARE_GLOBAL_DATA_PTR;

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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \

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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \

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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)

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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)

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#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \

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#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \

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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)

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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)

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#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)

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#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)

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#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)

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#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)

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#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)

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#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)

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#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \

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#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \

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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)

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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)

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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \

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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \

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PAD_CTL_DSE_3P3V_49OHM)

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PAD_CTL_DSE_3P3V_49OHM)

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#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)

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#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)

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#define BUTTON_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_DSE_3P3V_98OHM)

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#define BUTTON_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_DSE_3P3V_98OHM)

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#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)

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#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)

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#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)

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#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)

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#define EPDC_PAD_CTRL 0x0

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#define EPDC_PAD_CTRL 0x0

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#define WEAK_PULLUP (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM | \

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#define WEAK_PULLUP (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM | \

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PAD_CTL_HYS | PAD_CTL_SRE_SLOW)

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PAD_CTL_HYS | PAD_CTL_SRE_SLOW)

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#ifdef CONFIG_SYS_I2C_MXC

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#ifdef CONFIG_SYS_I2C_MXC

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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)

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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)

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/*

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/*

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* Read header information from EEPROM into global structure.

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* Read header information from EEPROM into global structure.

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*/

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*/

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static int read_eeprom(struct smarcfimx7_id *header)

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static int read_eeprom(struct smarcfimx7_id *header)

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{

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{

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i2c_set_bus_num(1);

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i2c_set_bus_num(1);

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/* Check if baseboard eeprom is available */

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/* Check if baseboard eeprom is available */

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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {

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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {

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puts("Could not probe the EEPROM; something fundamentally "

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puts("Could not probe the EEPROM; something fundamentally "

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"wrong on the I2C bus.\n");

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"wrong on the I2C bus.\n");

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return -ENODEV;

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return -ENODEV;

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}

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}

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/* read the eeprom using i2c */

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/* read the eeprom using i2c */

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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,

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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,

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sizeof(struct smarcfimx7_id))) {

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sizeof(struct smarcfimx7_id))) {

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puts("Could not read the EEPROM; something fundamentally"

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puts("Could not read the EEPROM; something fundamentally"

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" wrong on the I2C bus.\n");

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" wrong on the I2C bus.\n");

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return -EIO;

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return -EIO;

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}

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}

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if (header->magic != 0xEE3355AA) {

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if (header->magic != 0xEE3355AA) {

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/*

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/*

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* read the eeprom using i2c again,

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* read the eeprom using i2c again,

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* but use only a 1 byte address

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* but use only a 1 byte address

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*/

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*/

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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,

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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,

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sizeof(struct smarcfimx7_id))) {

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sizeof(struct smarcfimx7_id))) {

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puts("Could not read the EEPROM; something "

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puts("Could not read the EEPROM; something "

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"fundamentally wrong on the I2C bus.\n");

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"fundamentally wrong on the I2C bus.\n");

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return -EIO;

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return -EIO;

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}

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}

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if (header->magic != 0xEE3355AA) {

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if (header->magic != 0xEE3355AA) {

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printf("Incorrect magic number (0x%x) in EEPROM\n",

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printf("Incorrect magic number (0x%x) in EEPROM\n",

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header->magic);

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header->magic);

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return -EINVAL;

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return -EINVAL;

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}

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}

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}

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}

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return 0;

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return 0;

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}

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}

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/* I2C1 for PMIC (I2C_PM)*/

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/* I2C1 for PMIC (I2C_PM)*/

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static struct i2c_pads_info i2c_pad_info1 = {

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static struct i2c_pads_info i2c_pad_info1 = {

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.scl = {

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.scl = {

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.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,

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.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,

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.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,

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.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,

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.gp = IMX_GPIO_NR(4, 8),

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.gp = IMX_GPIO_NR(4, 8),

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},

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},

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.sda = {

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.sda = {

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.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,

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.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,

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.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,

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.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,

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.gp = IMX_GPIO_NR(4, 9),

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.gp = IMX_GPIO_NR(4, 9),

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},

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},

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};

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};

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/* I2C2 for I2C_GP */

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/* I2C2 for I2C_GP */

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static struct i2c_pads_info i2c_pad_info2 = {

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static struct i2c_pads_info i2c_pad_info2 = {

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.scl = {

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.scl = {

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.i2c_mode = MX7D_PAD_I2C2_SCL__I2C2_SCL | PC,

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.i2c_mode = MX7D_PAD_I2C2_SCL__I2C2_SCL | PC,

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.gpio_mode = MX7D_PAD_I2C2_SCL__GPIO4_IO10 | PC,

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.gpio_mode = MX7D_PAD_I2C2_SCL__GPIO4_IO10 | PC,

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.gp = IMX_GPIO_NR(4, 10),

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.gp = IMX_GPIO_NR(4, 10),

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},

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},

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.sda = {

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.sda = {

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.i2c_mode = MX7D_PAD_I2C2_SDA__I2C2_SDA | PC,

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.i2c_mode = MX7D_PAD_I2C2_SDA__I2C2_SDA | PC,

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.gpio_mode = MX7D_PAD_I2C2_SDA__GPIO4_IO11 | PC,

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.gpio_mode = MX7D_PAD_I2C2_SDA__GPIO4_IO11 | PC,

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.gp = IMX_GPIO_NR(4, 11),

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.gp = IMX_GPIO_NR(4, 11),

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},

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},

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};

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};

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/* I2C3 for I2C_LCD */

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/* I2C3 for I2C_LCD */

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static struct i2c_pads_info i2c_pad_info3 = {

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static struct i2c_pads_info i2c_pad_info3 = {

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.scl = {

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.scl = {

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.i2c_mode = MX7D_PAD_I2C3_SCL__I2C3_SCL | PC,

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.i2c_mode = MX7D_PAD_I2C3_SCL__I2C3_SCL | PC,

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.gpio_mode = MX7D_PAD_I2C3_SCL__GPIO4_IO12 | PC,

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.gpio_mode = MX7D_PAD_I2C3_SCL__GPIO4_IO12 | PC,

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.gp = IMX_GPIO_NR(4, 12),

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.gp = IMX_GPIO_NR(4, 12),

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},

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},

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.sda = {

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.sda = {

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.i2c_mode = MX7D_PAD_I2C3_SDA__I2C3_SDA | PC,

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.i2c_mode = MX7D_PAD_I2C3_SDA__I2C3_SDA | PC,

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.gpio_mode = MX7D_PAD_I2C3_SDA__GPIO4_IO13 | PC,

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.gpio_mode = MX7D_PAD_I2C3_SDA__GPIO4_IO13 | PC,

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.gp = IMX_GPIO_NR(4, 13),

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.gp = IMX_GPIO_NR(4, 13),

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},

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},

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};

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};

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/* I2C4 for I2C_CAM1 */

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/* I2C4 for I2C_CAM1 */

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static struct i2c_pads_info i2c_pad_info4 = {

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static struct i2c_pads_info i2c_pad_info4 = {

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.scl = {

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.scl = {

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.i2c_mode = MX7D_PAD_I2C4_SCL__I2C4_SCL | PC,

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.i2c_mode = MX7D_PAD_I2C4_SCL__I2C4_SCL | PC,

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.gpio_mode = MX7D_PAD_I2C4_SCL__GPIO4_IO14 | PC,

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.gpio_mode = MX7D_PAD_I2C4_SCL__GPIO4_IO14 | PC,

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.gp = IMX_GPIO_NR(4, 14),

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.gp = IMX_GPIO_NR(4, 14),

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},

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},

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.sda = {

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.sda = {

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.i2c_mode = MX7D_PAD_I2C4_SDA__I2C4_SDA | PC,

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.i2c_mode = MX7D_PAD_I2C4_SDA__I2C4_SDA | PC,

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.gpio_mode = MX7D_PAD_I2C4_SDA__GPIO4_IO15 | PC,

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.gpio_mode = MX7D_PAD_I2C4_SDA__GPIO4_IO15 | PC,

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.gp = IMX_GPIO_NR(4, 15),

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.gp = IMX_GPIO_NR(4, 15),

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},

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},

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};

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};

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#endif

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#endif

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int dram_init(void)

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int dram_init(void)

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{

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{

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gd->ram_size = PHYS_SDRAM_SIZE;

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gd->ram_size = PHYS_SDRAM_SIZE;

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return 0;

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return 0;

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}

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}

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static iomux_v3_cfg_t const wdog_pads[] = {

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static iomux_v3_cfg_t const wdog_pads[] = {

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MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),

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MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),

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};

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};

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/* SER0/UART6 */

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/* SER0/UART6 */

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static iomux_v3_cfg_t const uart6_pads[] = {

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static iomux_v3_cfg_t const uart6_pads[] = {

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MX7D_PAD_EPDC_DATA09__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA09__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA08__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA08__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),

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};

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};

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/* SER1/UART2 */

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/* SER1/UART2 */

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static iomux_v3_cfg_t const uart2_pads[] = {

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static iomux_v3_cfg_t const uart2_pads[] = {

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MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),

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};

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};

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/* SER2/UART7 */

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/* SER2/UART7 */

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static iomux_v3_cfg_t const uart7_pads[] = {

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static iomux_v3_cfg_t const uart7_pads[] = {

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MX7D_PAD_EPDC_DATA13__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA13__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA12__UART7_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA12__UART7_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),

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};

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};

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/* SER3/UART3 Debug Port */

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/* SER3/UART3 Debug Port */

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static iomux_v3_cfg_t const uart3_pads[] = {

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static iomux_v3_cfg_t const uart3_pads[] = {

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MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),

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};

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};

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/* RESET_OUT# */

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/* RESET_OUT# */

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static iomux_v3_cfg_t const reset_out_pads[] = {

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static iomux_v3_cfg_t const reset_out_pads[] = {

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MX7D_PAD_EPDC_BDR1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),

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MX7D_PAD_EPDC_BDR1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),

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};

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};

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/* SD Card */

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/* SD Card */

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static iomux_v3_cfg_t const usdhc1_pads[] = {

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static iomux_v3_cfg_t const usdhc1_pads[] = {

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MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /*CD */

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MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /*CD */

232

MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */

232

MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */

233

MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* SDIO_PWR_EN */

233

MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* SDIO_PWR_EN */

234

};

234

};

235

236

/* eMMC */

236

/* eMMC */

237

static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {

237

static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {

238

MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

238

MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

239

MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

239

MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

240

MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

240

MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

241

MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

241

MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

242

MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

242

MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

243

MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

243

MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

244

MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

244

MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

245

MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

245

MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

246

MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

246

MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

247

MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

247

MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

248

MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),

248

MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),

249

MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

249

MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

250

};

250

};

251

252

/* SPI0 */

252

/* SPI0 */

253

static iomux_v3_cfg_t const ecspi1_pads[] = {

253

static iomux_v3_cfg_t const ecspi1_pads[] = {

254

MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

254

MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

255

MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

255

MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

256

MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

256

MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

257

MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/

257

MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/

258

MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/

258

MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/

259

};

259

};

260

261

/* ESPI */

261

/* ESPI */

262

static iomux_v3_cfg_t const ecspi3_pads[] = {

262

static iomux_v3_cfg_t const ecspi3_pads[] = {

263

MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

263

MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

264

MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

264

MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

265

MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

265

MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

266

MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/

266

MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/

267

MX7D_PAD_SD2_CD_B__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/

267

MX7D_PAD_SD2_CD_B__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/

268

};

268

};

269

270

/* CAN0/FLEXCAN1 */

270

/* CAN0/FLEXCAN1 */

271

static iomux_v3_cfg_t const flexcan1_pads[] = {

271

static iomux_v3_cfg_t const flexcan1_pads[] = {

272

MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX | MUX_PAD_CTRL(WEAK_PULLUP),

272

MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX | MUX_PAD_CTRL(WEAK_PULLUP),

273

MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX | MUX_PAD_CTRL(WEAK_PULLUP),

273

MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX | MUX_PAD_CTRL(WEAK_PULLUP),

274

};

274

};

275

276

/* CAN1/FLEXCAN2 */

276

/* CAN1/FLEXCAN2 */

277

static iomux_v3_cfg_t const flexcan2_pads[] = {

277

static iomux_v3_cfg_t const flexcan2_pads[] = {

278

MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX | MUX_PAD_CTRL(WEAK_PULLUP),

278

MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX | MUX_PAD_CTRL(WEAK_PULLUP),

279

MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX | MUX_PAD_CTRL(WEAK_PULLUP),

279

MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX | MUX_PAD_CTRL(WEAK_PULLUP),

280

};

280

};

281

282

/* GPIOs */

282

/* GPIOs */

283

static iomux_v3_cfg_t const gpios_pads[] = {

283

static iomux_v3_cfg_t const gpios_pads[] = {

284

MX7D_PAD_EPDC_DATA00__GPIO2_IO0 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO0 */

284

MX7D_PAD_EPDC_DATA00__GPIO2_IO0 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO0 */

285

MX7D_PAD_EPDC_DATA01__GPIO2_IO1 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO1 */

285

MX7D_PAD_EPDC_DATA01__GPIO2_IO1 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO1 */

286

MX7D_PAD_EPDC_DATA02__GPIO2_IO2 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO2 */

286

MX7D_PAD_EPDC_DATA02__GPIO2_IO2 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO2 */

287

MX7D_PAD_EPDC_DATA03__GPIO2_IO3 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO3 */

287

MX7D_PAD_EPDC_DATA03__GPIO2_IO3 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO3 */

288

MX7D_PAD_EPDC_DATA04__GPIO2_IO4 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO4 */

288

MX7D_PAD_EPDC_DATA04__GPIO2_IO4 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO4 */

289

MX7D_PAD_EPDC_DATA05__GPIO2_IO5 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO6 */

289

MX7D_PAD_EPDC_DATA05__GPIO2_IO5 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO6 */

290

MX7D_PAD_EPDC_DATA07__GPIO2_IO7 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO7 */

290

MX7D_PAD_EPDC_DATA07__GPIO2_IO7 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO7 */

291

MX7D_PAD_EPDC_DATA06__GPIO2_IO6 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO8 */

291

MX7D_PAD_EPDC_DATA06__GPIO2_IO6 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO8 */

292

MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO9 */

292

MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO9 */

293

MX7D_PAD_UART3_RTS_B__GPIO4_IO6 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO10 */

293

MX7D_PAD_UART3_RTS_B__GPIO4_IO6 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO10 */

294

MX7D_PAD_UART3_CTS_B__GPIO4_IO7 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO11 */

294

MX7D_PAD_UART3_CTS_B__GPIO4_IO7 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO11 */

295

};

295

};

296

297

/* LVDS channel selection, set low as single channel LVDS and high as dual channel LVDS */

297

/* LVDS channel selection, set low as single channel LVDS and high as dual channel LVDS */

298

static iomux_v3_cfg_t const lvds_ch_sel_pads[] = {

298

static iomux_v3_cfg_t const lvds_ch_sel_pads[] = {

299

MX7D_PAD_SD2_CMD__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), /* LVDS_CH_SEL */

299

MX7D_PAD_SD2_CMD__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), /* LVDS_CH_SEL */

300

};

300

};

301

302

/* Misc. pins */

302

/* Misc. pins */

303

static iomux_v3_cfg_t const misc_pads[] = {

303

static iomux_v3_cfg_t const misc_pads[] = {

304

MX7D_PAD_SD2_DATA0__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), /* SLEEP# */

304

MX7D_PAD_SD2_DATA0__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), /* SLEEP# */

305

MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), /* CHARGER_PRSNT# */

305

MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(WEAK_PULLUP), /* CHARGER_PRSNT# */

306

MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(WEAK_PULLUP), /* CHARGING# */

306

MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(WEAK_PULLUP), /* CHARGING# */

307

MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), /* CARRIER_STBY# */

307

MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), /* CARRIER_STBY# */

308

MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | MUX_PAD_CTRL(WEAK_PULLUP), /* CARRIER_PWR_ON# */

309

MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /* BATLOW# */

308

MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /* BATLOW# */

310

MX7D_PAD_EPDC_BDR0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe_RST# */

309

MX7D_PAD_EPDC_BDR0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe_RST# */

311

MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe_WAKE# */

310

MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe_WAKE# */

311

MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WDT_TIME_OUT# */

312

};

312

};

313

314

#ifdef CONFIG_VIDEO_MXS

314

#ifdef CONFIG_VIDEO_MXS

315

static iomux_v3_cfg_t const lcd_pads[] = {

315

static iomux_v3_cfg_t const lcd_pads[] = {

316

MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),

316

MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),

317

MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),

317

MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),

318

MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),

318

MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),

319

MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),

319

MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),

320

MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),

320

MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),

321

MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),

321

MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),

322

MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),

322

MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),

323

MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),

323

MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),

324

MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),

324

MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),

325

MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),

325

MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),

326

MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),

326

MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),

327

MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),

327

MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),

328

MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),

328

MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),

329

MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),

329

MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),

330

MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),

330

MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),

331

MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),

331

MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),

332

MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),

332

MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),

333

MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),

333

MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),

334

MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),

334

MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),

335

MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),

335

MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),

336

MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),

336

MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),

337

MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),

337

MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),

338

MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),

338

MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),

339

MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),

339

MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),

340

MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),

340

MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),

341

MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),

341

MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),

342

MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),

342

MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),

343

MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),

343

MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),

344

345

MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),

345

MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),

346

};

346

};

347

348

static iomux_v3_cfg_t const backlight_pads[] = {

348

static iomux_v3_cfg_t const backlight_pads[] = {

349

/* Backlight Enable for RGB: S127 */

349

/* Backlight Enable for RGB: S127 */

350

MX7D_PAD_GPIO1_IO02__GPIO1_IO2 | MUX_PAD_CTRL(WEAK_PULLUP),

350

MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | MUX_PAD_CTRL(WEAK_PULLUP),

351

352

/* PWM Backlight Control: S141. Use GPIO for Brightness adjustment, duty cycle = period */

352

/* PWM Backlight Control: S141. Use GPIO for Brightness adjustment, duty cycle = period */

353

MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),

353

MX7D_PAD_GPIO1_IO02__GPIO1_IO2 | MUX_PAD_CTRL(NO_PAD_CTRL),

354

};

354

};

355

356

void do_enable_parallel_lcd(struct display_info_t const *dev)

356

void do_enable_parallel_lcd(struct display_info_t const *dev)

357

{

357

{

358

imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));

358

imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));

359

360

imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));

360

imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));

361

362

/* Reset LCD */

362

/* Reset LCD */

363

gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);

363

gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);

364

365

/* Turn on Backlight */

365

/* Turn on Backlight */

366

gpio_direction_output(IMX_GPIO_NR(1, 2), 1);

366

gpio_direction_output(IMX_GPIO_NR(6, 17), 1);

367

368

/* Set Brightness to high */

368

/* Set Brightness to high */

369

gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);

369

gpio_direction_output(IMX_GPIO_NR(1, 2) , 1);

370

}

370

}

371

372

373

/* LVDS Panel for AUO G070VW01 V0 7-inch Color TFT 800x480 Panel Settings */

373

/* LVDS Panel for AUO G070VW01 V0 7-inch Color TFT 800x480 Panel Settings */

374

struct display_info_t const displays[] = {{

374

struct display_info_t const displays[] = {{

375

.bus = ELCDIF1_IPS_BASE_ADDR,

375

.bus = ELCDIF1_IPS_BASE_ADDR,

376

.addr = 0,

376

.addr = 0,

377

.pixfmt = 24,

377

.pixfmt = 24,

378

.detect = NULL,

378

.detect = NULL,

379

.enable = do_enable_parallel_lcd,

379

.enable = do_enable_parallel_lcd,

380

.mode = {

380

.mode = {

381

.name = "G070VW01",

381

.name = "G070VW01",

382

.xres = 800,

382

.xres = 800,

383

.yres = 480,

383

.yres = 480,

384

.pixclock = 31069,

384

.pixclock = 31069,

385

.left_margin = 64,

385

.left_margin = 64,

386

.right_margin = 64,

386

.right_margin = 64,

387

.upper_margin = 12,

387

.upper_margin = 12,

388

.lower_margin = 4,

388

.lower_margin = 4,

389

.hsync_len = 128,

389

.hsync_len = 128,

390

.vsync_len = 12,

390

.vsync_len = 12,

391

.sync = 0,

391

.sync = 0,

392

.vmode = FB_VMODE_NONINTERLACED

392

.vmode = FB_VMODE_NONINTERLACED

393

} } };

393

} } };

394

size_t display_count = ARRAY_SIZE(displays);

394

size_t display_count = ARRAY_SIZE(displays);

395

#endif

395

#endif

396

397

static void setup_iomux_uart6(void)

397

static void setup_iomux_uart6(void)

398

{

398

{

399

imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));

399

imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));

400

}

400

}

401

402

static void setup_iomux_uart2(void)

402

static void setup_iomux_uart2(void)

403

{

403

{

404

imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));

404

imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));

405

}

405

}

406

407

static void setup_iomux_uart7(void)

407

static void setup_iomux_uart7(void)

408

{

408

{

409

imx_iomux_v3_setup_multiple_pads(uart7_pads, ARRAY_SIZE(uart7_pads));

409

imx_iomux_v3_setup_multiple_pads(uart7_pads, ARRAY_SIZE(uart7_pads));

410

}

410

}

411

412

static void setup_iomux_uart3(void)

412

static void setup_iomux_uart3(void)

413

{

413

{

414

imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));

414

imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));

415

}

415

}

416

417

static void setup_iomux_reset_out(void)

417

static void setup_iomux_reset_out(void)

418

{

418

{

419

imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads));

419

imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads));

420

421

/* Set CPU RESET_OUT as Output */

421

/* Set CPU RESET_OUT as Output */

422

gpio_direction_output(IMX_GPIO_NR(2, 29) , 0);

422

gpio_direction_output(IMX_GPIO_NR(2, 29) , 0);

423

}

423

}

424

425

static void setup_iomux_spi1(void)

425

static void setup_iomux_spi1(void)

426

{

426

{

427

imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));

427

imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));

428

gpio_direction_output(IMX_GPIO_NR(4, 19), 0);

428

gpio_direction_output(IMX_GPIO_NR(4, 19), 0);

429

gpio_direction_output(IMX_GPIO_NR(4, 0), 0);

429

gpio_direction_output(IMX_GPIO_NR(4, 0), 0);

430

}

430

}

431

432

static void setup_iomux_spi3(void)

432

static void setup_iomux_spi3(void)

433

{

433

{

434

imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));

434

imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));

435

gpio_direction_output(IMX_GPIO_NR(6, 22), 0);

435

gpio_direction_output(IMX_GPIO_NR(6, 22), 0);

436

gpio_direction_output(IMX_GPIO_NR(5, 9), 0);

436

gpio_direction_output(IMX_GPIO_NR(5, 9), 0);

437

}

437

}

438

439

static void setup_iomux_gpios(void)

439

static void setup_iomux_gpios(void)

440

{

440

{

441

imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads));

441

imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads));

442

gpio_direction_output(IMX_GPIO_NR(2, 0), 0);

442

gpio_direction_output(IMX_GPIO_NR(2, 0), 0);

443

gpio_direction_output(IMX_GPIO_NR(2, 1), 0);

443

gpio_direction_output(IMX_GPIO_NR(2, 1), 0);

444

gpio_direction_output(IMX_GPIO_NR(2, 2), 0);

444

gpio_direction_output(IMX_GPIO_NR(2, 2), 0);

445

gpio_direction_output(IMX_GPIO_NR(2, 3), 0);

445

gpio_direction_output(IMX_GPIO_NR(2, 3), 0);

446

gpio_direction_output(IMX_GPIO_NR(2, 4), 0);

446

gpio_direction_output(IMX_GPIO_NR(2, 4), 0);

447

gpio_direction_input(IMX_GPIO_NR(2, 5));

447

gpio_direction_input(IMX_GPIO_NR(2, 5));

448

gpio_direction_input(IMX_GPIO_NR(2, 7));

448

gpio_direction_input(IMX_GPIO_NR(2, 7));

449

gpio_direction_input(IMX_GPIO_NR(2, 6));

449

gpio_direction_input(IMX_GPIO_NR(2, 6));

450

gpio_direction_input(IMX_GPIO_NR(4, 1));

450

gpio_direction_input(IMX_GPIO_NR(4, 1));

451

gpio_direction_input(IMX_GPIO_NR(4, 6));

451

gpio_direction_input(IMX_GPIO_NR(4, 6));

452

gpio_direction_input(IMX_GPIO_NR(4, 7));

452

gpio_direction_input(IMX_GPIO_NR(4, 7));

453

}

453

}

454

455

static void setup_iomux_lvds_ch_sel(void)

455

static void setup_iomux_lvds_ch_sel(void)

456

{

456

{

457

imx_iomux_v3_setup_multiple_pads(lvds_ch_sel_pads, ARRAY_SIZE(lvds_ch_sel_pads));

457

imx_iomux_v3_setup_multiple_pads(lvds_ch_sel_pads, ARRAY_SIZE(lvds_ch_sel_pads));

458

gpio_direction_output(IMX_GPIO_NR(5, 13), 0);

458

gpio_direction_output(IMX_GPIO_NR(5, 13), 0);

459

}

459

}

460

461

static void setup_iomux_misc(void)

461

static void setup_iomux_misc(void)

462

{

462

{

463

imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));

463

imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));

464

gpio_direction_input(IMX_GPIO_NR(5, 14));

464

gpio_direction_input(IMX_GPIO_NR(5, 14));

465

gpio_direction_input(IMX_GPIO_NR(1, 8));

465

gpio_direction_input(IMX_GPIO_NR(1, 8));

466

gpio_direction_input(IMX_GPIO_NR(1, 9));

466

gpio_direction_input(IMX_GPIO_NR(1, 9));

467

gpio_direction_input(IMX_GPIO_NR(5, 11));

467

gpio_direction_input(IMX_GPIO_NR(5, 11));

468

gpio_direction_output(IMX_GPIO_NR(6, 16), 0);

468

gpio_direction_output(IMX_GPIO_NR(6, 16), 0);

469

gpio_direction_output(IMX_GPIO_NR(6, 17), 0);

470

gpio_direction_output(IMX_GPIO_NR(2, 28), 0);

469

gpio_direction_output(IMX_GPIO_NR(2, 28), 0);

471

udelay(500);

470

udelay(500);

472

gpio_direction_output(IMX_GPIO_NR(2, 28), 1);

471

gpio_direction_output(IMX_GPIO_NR(2, 28), 1);

473

gpio_direction_input(IMX_GPIO_NR(2, 31));

472

gpio_direction_input(IMX_GPIO_NR(2, 31));

473

/* Set WDT_TIME_OUT# as Output High */

474

gpio_direction_output(IMX_GPIO_NR(7, 14), 1);

474

}

475

}

475

476

static void setup_iomux_flexcan1(void)

477

static void setup_iomux_flexcan1(void)

477

{

478

{

478

imx_iomux_v3_setup_multiple_pads(flexcan1_pads, ARRAY_SIZE(flexcan1_pads));

479

imx_iomux_v3_setup_multiple_pads(flexcan1_pads, ARRAY_SIZE(flexcan1_pads));

479

}

480

}

480

481

static void setup_iomux_flexcan2(void)

482

static void setup_iomux_flexcan2(void)

482

{

483

{

483

imx_iomux_v3_setup_multiple_pads(flexcan2_pads, ARRAY_SIZE(flexcan2_pads));

484

imx_iomux_v3_setup_multiple_pads(flexcan2_pads, ARRAY_SIZE(flexcan2_pads));

484

}

485

}

485

486

#ifdef CONFIG_FSL_ESDHC

487

#ifdef CONFIG_FSL_ESDHC

487

488

#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)

489

#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)

489

#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)

490

#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)

490

#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)

491

#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)

491

492

static struct fsl_esdhc_cfg usdhc_cfg[3] = {

493

static struct fsl_esdhc_cfg usdhc_cfg[3] = {

493

{USDHC1_BASE_ADDR, 0, 4},

494

{USDHC1_BASE_ADDR, 0, 4},

494

{USDHC3_BASE_ADDR},

495

{USDHC3_BASE_ADDR},

495

};

496

};

496

497

int board_mmc_get_env_dev(int devno)

498

int board_mmc_get_env_dev(int devno)

498

{

499

{

499

if (devno == 2)

500

if (devno == 2)

500

devno--;

501

devno--;

501

502

return devno;

503

return devno;

503

}

504

}

504

505

int mmc_map_to_kernel_blk(int dev_no)

506

int mmc_map_to_kernel_blk(int dev_no)

506

{

507

{

507

if (dev_no == 1)

508

if (dev_no == 1)

508

dev_no++;

509

dev_no++;

509

510

return dev_no;

511

return dev_no;

511

}

512

}

512

513

int board_mmc_getcd(struct mmc *mmc)

514

int board_mmc_getcd(struct mmc *mmc)

514

{

515

{

515

struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;

516

struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;

516

int ret = 0;

517

int ret = 0;

517

518

switch (cfg->esdhc_base) {

519

switch (cfg->esdhc_base) {

519

case USDHC1_BASE_ADDR:

520

case USDHC1_BASE_ADDR:

520

ret = !gpio_get_value(USDHC1_CD_GPIO);

521

ret = !gpio_get_value(USDHC1_CD_GPIO);

521

break;

522

break;

522

case USDHC3_BASE_ADDR:

523

case USDHC3_BASE_ADDR:

523

ret = 1; /* Assume uSDHC3 emmc is always present */

524

ret = 1; /* Assume uSDHC3 emmc is always present */

524

break;

525

break;

525

}

526

}

526

527

return ret;

528

return ret;

528

}

529

}

529

530

int board_mmc_init(bd_t *bis)

531

int board_mmc_init(bd_t *bis)

531

{

532

{

532

int i, ret;

533

int i, ret;

533

/*

534

/*

534

* According to the board_mmc_init() the following map is done:

535

* According to the board_mmc_init() the following map is done:

535

* (U-Boot device node) (Physical Port)

536

* (U-Boot device node) (Physical Port)

536

* mmc0 USDHC1

537

* mmc0 USDHC1

537

* mmc2 USDHC3 (eMMC)

538

* mmc2 USDHC3 (eMMC)

538

*/

539

*/

539

for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {

540

for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {

540

switch (i) {

541

switch (i) {

541

case 0:

542

case 0:

542

imx_iomux_v3_setup_multiple_pads(

543

imx_iomux_v3_setup_multiple_pads(

543

usdhc1_pads, ARRAY_SIZE(usdhc1_pads));

544

usdhc1_pads, ARRAY_SIZE(usdhc1_pads));

544

gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");

545

gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");

545

gpio_direction_input(USDHC1_CD_GPIO);

546

gpio_direction_input(USDHC1_CD_GPIO);

546

gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");

547

gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");

547

gpio_direction_output(USDHC1_PWR_GPIO, 0);

548

gpio_direction_output(USDHC1_PWR_GPIO, 0);

548

udelay(500);

549

udelay(500);

549

gpio_direction_output(USDHC1_PWR_GPIO, 1);

550

gpio_direction_output(USDHC1_PWR_GPIO, 1);

550

usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);

551

usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);

551

break;

552

break;

552

case 1:

553

case 1:

553

imx_iomux_v3_setup_multiple_pads(

554

imx_iomux_v3_setup_multiple_pads(

554

usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));

555

usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));

555

gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");

556

gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");

556

gpio_direction_output(USDHC3_PWR_GPIO, 0);

557

gpio_direction_output(USDHC3_PWR_GPIO, 0);

557

udelay(500);

558

udelay(500);

558

gpio_direction_output(USDHC3_PWR_GPIO, 1);

559

gpio_direction_output(USDHC3_PWR_GPIO, 1);

559

usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);

560

usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);

560

break;

561

break;

561

default:

562

default:

562

printf("Warning: you configured more USDHC controllers"

563

printf("Warning: you configured more USDHC controllers"

563

"(%d) than supported by the board\n", i + 1);

564

"(%d) than supported by the board\n", i + 1);

564

return -EINVAL;

565

return -EINVAL;

565

}

566

}

566

567

ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);

568

ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);

568

if (ret)

569

if (ret)

569

return ret;

570

return ret;

570

}

571

}

571

572

return 0;

573

return 0;

573

}

574

}

574

#endif

575

#endif

575

576

#ifdef CONFIG_FEC_MXC

577

#ifdef CONFIG_FEC_MXC

577

static iomux_v3_cfg_t const fec1_pads[] = {

578

static iomux_v3_cfg_t const fec1_pads[] = {

578

MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

579

MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

579

MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

580

MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

580

MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

581

MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

581

MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

582

MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

582

MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

583

MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

583

MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

584

MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

584

MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),

585

MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),

585

MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),

586

MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),

586

MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),

587

MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),

587

MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),

588

MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),

588

MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),

589

MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),

589

MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),

590

MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),

590

MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),

591

MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),

591

MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),

592

MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),

592

};

593

};

593

594

static iomux_v3_cfg_t const fec2_pads[] = {

595

static iomux_v3_cfg_t const fec2_pads[] = {

595

MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

596

MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

596

MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

597

MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

597

MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

598

MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

598

MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

599

MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

599

MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

600

MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

600

MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

601

MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),

601

MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),

602

MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),

602

MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),

603

MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),

603

MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),

604

MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),

604

MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),

605

MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),

605

MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),

606

MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),

606

MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),

607

MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),

607

MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),

608

MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),

608

MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),

609

MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),

609

};

610

};

610

611

static void setup_iomux_fec(void)

612

static void setup_iomux_fec(void)

612

{

613

{

613

if (0 == CONFIG_FEC_ENET_DEV) {

614

if (0 == CONFIG_FEC_ENET_DEV) {

614

imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));

615

imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));

615

gpio_direction_input(IMX_GPIO_NR(7, 15));

616

gpio_direction_input(IMX_GPIO_NR(7, 15));

616

} else {

617

} else {

617

imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));

618

imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));

618

gpio_direction_input(IMX_GPIO_NR(7, 14));

619

gpio_direction_input(IMX_GPIO_NR(7, 13));

619

}

620

}

620

}

621

}

621

622

int board_eth_init(bd_t *bis)

623

int board_eth_init(bd_t *bis)

623

{

624

{

624

#if defined(CONFIG_MAC_ADDR_IN_EEPROM)

625

#if defined(CONFIG_MAC_ADDR_IN_EEPROM)

625

626

uchar env_enetaddr[6];

627

uchar env_enetaddr[6];

627

int enetaddr_found;

628

int enetaddr_found;

628

629

enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr);

630

enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr);

630

631

uint8_t enetaddr[8];

632

uint8_t enetaddr[8];

632

int eeprom_mac_read;

633

int eeprom_mac_read;

633

634

/* Read Ethernet MAC address from EEPROM */

635

/* Read Ethernet MAC address from EEPROM */

635

eeprom_mac_read = smarcfimx7_read_mac_address(enetaddr);

636

eeprom_mac_read = smarcfimx7_read_mac_address(enetaddr);

636

637

/*

638

/*

638

* MAC address not present in the environment

639

* MAC address not present in the environment

639

* try and read the MAC address from EEPROM flash

640

* try and read the MAC address from EEPROM flash

640

* and set it.

641

* and set it.

641

*/

642

*/

642

if (!enetaddr_found) {

643

if (!enetaddr_found) {

643

if (eeprom_mac_read)

644

if (eeprom_mac_read)

644

/* Set Ethernet MAC address from EEPROM */

645

/* Set Ethernet MAC address from EEPROM */

645

smarcfimx7_sync_env_enetaddr(enetaddr);

646

smarcfimx7_sync_env_enetaddr(enetaddr);

646

} else {

647

} else {

647

/*

648

/*

648

* MAC address present in environment compare it with

649

* MAC address present in environment compare it with

649

* the MAC address in EEPROM and warn on mismatch

650

* the MAC address in EEPROM and warn on mismatch

650

*/

651

*/

651

if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))

652

if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))

652

printf("Warning: MAC address in EEPROM don't match "

653

printf("Warning: MAC address in EEPROM don't match "

653

"with the MAC address in the environment\n");

654

"with the MAC address in the environment\n");

654

printf("Default using MAC address from environment\n");

655

printf("Default using MAC address from environment\n");

655

}

656

}

656

657

uchar env_enet1addr[6];

658

uchar env_enet1addr[6];

658

int enet1addr_found;

659

int enet1addr_found;

659

660

enet1addr_found = eth_getenv_enetaddr("eth1addr", env_enet1addr);

661

enet1addr_found = eth_getenv_enetaddr("eth1addr", env_enet1addr);

661

662

uint8_t enet1addr[8];

663

uint8_t enet1addr[8];

663

int eeprom_mac1_read;

664

int eeprom_mac1_read;

664

665

/* Read Ethernet MAC address from EEPROM */

666

/* Read Ethernet MAC address from EEPROM */

666

eeprom_mac1_read = smarcfimx7_read_mac1_address(enet1addr);

667

eeprom_mac1_read = smarcfimx7_read_mac1_address(enet1addr);

667

668

/*

669

/*

669

* MAC address not present in the environment

670

* MAC address not present in the environment

670

* try and read the MAC address from EEPROM flash

671

* try and read the MAC address from EEPROM flash

671

* and set it.

672

* and set it.

672

*/

673

*/

673

if (!enet1addr_found) {

674

if (!enet1addr_found) {

674

if (eeprom_mac1_read)

675

if (eeprom_mac1_read)

675

/* Set Ethernet MAC address from EEPROM */

676

/* Set Ethernet MAC address from EEPROM */

676

smarcfimx7_sync_env_enet1addr(enet1addr);

677

smarcfimx7_sync_env_enet1addr(enet1addr);

677

} else {

678

} else {

678

/*

679

/*

679

* MAC address present in environment compare it with

680

* MAC address present in environment compare it with

680

* the MAC address in EEPROM and warn on mismatch

681

* the MAC address in EEPROM and warn on mismatch

681

*/

682

*/

682

if (eeprom_mac_read && memcmp(enet1addr, env_enet1addr, 6))

683

if (eeprom_mac_read && memcmp(enet1addr, env_enet1addr, 6))

683

printf("Warning: 2nd GBE MAC address in EEPROM don't match "

684

printf("Warning: 2nd GBE MAC address in EEPROM don't match "

684

"with the MAC address in the environment\n");

685

"with the MAC address in the environment\n");

685

printf("Default using 2nd GBE MAC address from environment\n");

686

printf("Default using 2nd GBE MAC address from environment\n");

686

}

687

}

687

688

#endif

689

#endif

689

690

int ret;

691

int ret;

691

692

setup_iomux_fec();

693

setup_iomux_fec();

693

694

ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,

695

ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,

695

CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);

696

CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);

696

if (ret)

697

if (ret)

697

printf("FEC1 MXC: %s:failed\n", __func__);

698

printf("FEC1 MXC: %s:failed\n", __func__);

698

699

return ret;

700

return ret;

700

}

701

}

701

702

static int setup_fec(int fec_id)

703

static int setup_fec(int fec_id)

703

{

704

{

704

struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs

705

struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs

705

= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;

706

= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;

706

707

if (0 == fec_id) {

708

if (0 == fec_id) {

708

/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/

709

/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/

709

clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],

710

clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],

710

(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |

711

(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |

711

IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);

712

IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);

712

} else {

713

} else {

713

/* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/

714

/* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/

714

clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],

715

clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],

715

(IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |

716

(IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |

716

IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);

717

IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);

717

}

718

}

718

719

return set_clk_enet(ENET_125MHz);

720

return set_clk_enet(ENET_125MHz);

720

721

}

722

}

722

723

int board_phy_config(struct phy_device *phydev)

724

int board_phy_config(struct phy_device *phydev)

724

{

725

{

725

/* enable rgmii rxc skew and phy mode select to RGMII copper */

726

/* enable rgmii rxc skew and phy mode select to RGMII copper */

726

/*phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);

727

/*phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);

727

phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);

728

phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);

728

phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);

729

phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);

729

phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);*/

730

phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);*/

730

731

if (phydev->drv->config)

732

if (phydev->drv->config)

732

phydev->drv->config(phydev);

733

phydev->drv->config(phydev);

733

return 0;

734

return 0;

734

}

735

}

735

#endif

736

#endif

736

737

#ifdef CONFIG_MXC_SPI

738

#ifdef CONFIG_MXC_SPI

738

/* SPI2 (SPINOR) */

739

/* SPI2 (SPINOR) */

739

static iomux_v3_cfg_t const ecspi2_pads[] = {

740

static iomux_v3_cfg_t const ecspi2_pads[] = {

740

MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

741

MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

741

MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

742

MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

742

MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

743

MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

743

MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/

744

MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/

744

};

745

};

745

746

static void setup_spinor(void)

747

static void setup_spinor(void)

747

{

748

{

748

imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));

749

imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));

749

gpio_direction_output(IMX_GPIO_NR(4, 23), 0);

750

gpio_direction_output(IMX_GPIO_NR(4, 23), 0);

750

}

751

}

751

752

int board_spi_cs_gpio(unsigned bus, unsigned cs)

753

int board_spi_cs_gpio(unsigned bus, unsigned cs)

753

{

754

{

754

return (bus == 1 && cs == 0) ? (IMX_GPIO_NR(4, 23)) : -1;

755

return (bus == 1 && cs == 0) ? (IMX_GPIO_NR(4, 23)) : -1;

755

}

756

}

756

#endif

757

#endif

757

758

#ifdef CONFIG_MXC_EPDC

759

#ifdef CONFIG_MXC_EPDC

759

static iomux_v3_cfg_t const epdc_enable_pads[] = {

760

static iomux_v3_cfg_t const epdc_enable_pads[] = {

760

MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

761

MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

761

MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

762

MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

762

MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

763

MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

763

MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

764

MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

764

MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

765

MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

765

MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

766

MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

766

MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

767

MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

767

MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

768

MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

768

MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),

769

MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),

769

MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

770

MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

770

MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

771

MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

771

MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),

772

MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),

772

MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

773

MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

773

MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

774

MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

774

MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),

775

MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),

775

MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

776

MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

776

MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),

777

MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),

777

MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),

778

MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),

778

MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

779

MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

779

MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

780

MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

780

};

781

};

781

782

static iomux_v3_cfg_t const epdc_disable_pads[] = {

783

static iomux_v3_cfg_t const epdc_disable_pads[] = {

783

MX7D_PAD_EPDC_DATA00__GPIO2_IO0,

784

MX7D_PAD_EPDC_DATA00__GPIO2_IO0,

784

MX7D_PAD_EPDC_DATA01__GPIO2_IO1,

785

MX7D_PAD_EPDC_DATA01__GPIO2_IO1,

785

MX7D_PAD_EPDC_DATA02__GPIO2_IO2,

786

MX7D_PAD_EPDC_DATA02__GPIO2_IO2,

786

MX7D_PAD_EPDC_DATA03__GPIO2_IO3,

787

MX7D_PAD_EPDC_DATA03__GPIO2_IO3,

787

MX7D_PAD_EPDC_DATA04__GPIO2_IO4,

788

MX7D_PAD_EPDC_DATA04__GPIO2_IO4,

788

MX7D_PAD_EPDC_DATA05__GPIO2_IO5,

789

MX7D_PAD_EPDC_DATA05__GPIO2_IO5,

789

MX7D_PAD_EPDC_DATA06__GPIO2_IO6,

790

MX7D_PAD_EPDC_DATA06__GPIO2_IO6,

790

MX7D_PAD_EPDC_DATA07__GPIO2_IO7,

791

MX7D_PAD_EPDC_DATA07__GPIO2_IO7,

791

MX7D_PAD_EPDC_SDCLK__GPIO2_IO16,

792

MX7D_PAD_EPDC_SDCLK__GPIO2_IO16,

792

MX7D_PAD_EPDC_SDLE__GPIO2_IO17,

793

MX7D_PAD_EPDC_SDLE__GPIO2_IO17,

793

MX7D_PAD_EPDC_SDOE__GPIO2_IO18,

794

MX7D_PAD_EPDC_SDOE__GPIO2_IO18,

794

MX7D_PAD_EPDC_SDSHR__GPIO2_IO19,

795

MX7D_PAD_EPDC_SDSHR__GPIO2_IO19,

795

MX7D_PAD_EPDC_SDCE0__GPIO2_IO20,

796

MX7D_PAD_EPDC_SDCE0__GPIO2_IO20,

796

MX7D_PAD_EPDC_SDCE1__GPIO2_IO21,

797

MX7D_PAD_EPDC_SDCE1__GPIO2_IO21,

797

MX7D_PAD_EPDC_GDCLK__GPIO2_IO24,

798

MX7D_PAD_EPDC_GDCLK__GPIO2_IO24,

798

MX7D_PAD_EPDC_GDOE__GPIO2_IO25,

799

MX7D_PAD_EPDC_GDOE__GPIO2_IO25,

799

MX7D_PAD_EPDC_GDRL__GPIO2_IO26,

800

MX7D_PAD_EPDC_GDRL__GPIO2_IO26,

800

MX7D_PAD_EPDC_GDSP__GPIO2_IO27,

801

MX7D_PAD_EPDC_GDSP__GPIO2_IO27,

801

MX7D_PAD_EPDC_BDR0__GPIO2_IO28,

802

MX7D_PAD_EPDC_BDR0__GPIO2_IO28,

802

MX7D_PAD_EPDC_BDR1__GPIO2_IO29,

803

MX7D_PAD_EPDC_BDR1__GPIO2_IO29,

803

};

804

};

804

805

vidinfo_t panel_info = {

806

vidinfo_t panel_info = {

806

.vl_refresh = 85,

807

.vl_refresh = 85,

807

.vl_col = 1024,

808

.vl_col = 1024,

808

.vl_row = 758,

809

.vl_row = 758,

809

.vl_pixclock = 40000000,

810

.vl_pixclock = 40000000,

810

.vl_left_margin = 12,

811

.vl_left_margin = 12,

811

.vl_right_margin = 76,

812

.vl_right_margin = 76,

812

.vl_upper_margin = 4,

813

.vl_upper_margin = 4,

813

.vl_lower_margin = 5,

814

.vl_lower_margin = 5,

814

.vl_hsync = 12,

815

.vl_hsync = 12,

815

.vl_vsync = 2,

816

.vl_vsync = 2,

816

.vl_sync = 0,

817

.vl_sync = 0,

817

.vl_mode = 0,

818

.vl_mode = 0,

818

.vl_flag = 0,

819

.vl_flag = 0,

819

.vl_bpix = 3,

820

.vl_bpix = 3,

820

.cmap = 0,

821

.cmap = 0,

821

};

822

};

822

823

struct epdc_timing_params panel_timings = {

824

struct epdc_timing_params panel_timings = {

824

.vscan_holdoff = 4,

825

.vscan_holdoff = 4,

825

.sdoed_width = 10,

826

.sdoed_width = 10,

826

.sdoed_delay = 20,

827

.sdoed_delay = 20,

827

.sdoez_width = 10,

828

.sdoez_width = 10,

828

.sdoez_delay = 20,

829

.sdoez_delay = 20,

829

.gdclk_hp_offs = 524,

830

.gdclk_hp_offs = 524,

830

.gdsp_offs = 327,

831

.gdsp_offs = 327,

831

.gdoe_offs = 0,

832

.gdoe_offs = 0,

832

.gdclk_offs = 19,

833

.gdclk_offs = 19,

833

.num_ce = 1,

834

.num_ce = 1,

834

};

835

};

835

836

static void setup_epdc_power(void)

837

static void setup_epdc_power(void)

837

{

838

{

838

/* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */

839

/* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */

839

struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs

840

struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs

840

= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;

841

= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;

841

842

clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],

843

clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],

843

IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0);

844

IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0);

844

845

/* Setup epdc voltage */

846

/* Setup epdc voltage */

846

847

/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */

848

/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */

848

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |

849

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |

849

MUX_PAD_CTRL(EPDC_PAD_CTRL));

850

MUX_PAD_CTRL(EPDC_PAD_CTRL));

850

gpio_direction_input(IMX_GPIO_NR(2, 31));

851

gpio_direction_input(IMX_GPIO_NR(2, 31));

851

852

/* EPDC_VCOM0 - GPIO4[14] for VCOM control */

853

/* EPDC_VCOM0 - GPIO4[14] for VCOM control */

853

imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |

854

imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |

854

MUX_PAD_CTRL(EPDC_PAD_CTRL));

855

MUX_PAD_CTRL(EPDC_PAD_CTRL));

855

856

/* Set as output */

857

/* Set as output */

857

gpio_direction_output(IMX_GPIO_NR(4, 14), 1);

858

gpio_direction_output(IMX_GPIO_NR(4, 14), 1);

858

859

/* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */

860

/* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */

860

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |

861

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |

861

MUX_PAD_CTRL(EPDC_PAD_CTRL));

862

MUX_PAD_CTRL(EPDC_PAD_CTRL));

862

/* Set as output */

863

/* Set as output */

863

gpio_direction_output(IMX_GPIO_NR(2, 23), 1);

864

gpio_direction_output(IMX_GPIO_NR(2, 23), 1);

864

865

/* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */

866

/* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */

866

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |

867

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |

867

MUX_PAD_CTRL(EPDC_PAD_CTRL));

868

MUX_PAD_CTRL(EPDC_PAD_CTRL));

868

/* Set as output */

869

/* Set as output */

869

gpio_direction_output(IMX_GPIO_NR(2, 30), 1);

870

gpio_direction_output(IMX_GPIO_NR(2, 30), 1);

870

}

871

}

871

872

static void epdc_enable_pins(void)

873

static void epdc_enable_pins(void)

873

{

874

{

874

/* epdc iomux settings */

875

/* epdc iomux settings */

875

imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,

876

imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,

876

ARRAY_SIZE(epdc_enable_pads));

877

ARRAY_SIZE(epdc_enable_pads));

877

}

878

}

878

879

static void epdc_disable_pins(void)

880

static void epdc_disable_pins(void)

880

{

881

{

881

/* Configure MUX settings for EPDC pins to GPIO and drive to 0 */

882

/* Configure MUX settings for EPDC pins to GPIO and drive to 0 */

882

imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,

883

imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,

883

ARRAY_SIZE(epdc_disable_pads));

884

ARRAY_SIZE(epdc_disable_pads));

884

}

885

}

885

886

static void setup_epdc(void)

887

static void setup_epdc(void)

887

{

888

{

888

/*** epdc Maxim PMIC settings ***/

889

/*** epdc Maxim PMIC settings ***/

889

890

/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */

891

/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */

891

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |

892

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |

892

MUX_PAD_CTRL(EPDC_PAD_CTRL));

893

MUX_PAD_CTRL(EPDC_PAD_CTRL));

893

894

/* EPDC_VCOM0 - GPIO4[14] for VCOM control */

895

/* EPDC_VCOM0 - GPIO4[14] for VCOM control */

895

imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |

896

imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |

896

MUX_PAD_CTRL(EPDC_PAD_CTRL));

897

MUX_PAD_CTRL(EPDC_PAD_CTRL));

897

898

/* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */

899

/* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */

899

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |

900

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |

900

MUX_PAD_CTRL(EPDC_PAD_CTRL));

901

MUX_PAD_CTRL(EPDC_PAD_CTRL));

901

902

/* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */

903

/* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */

903

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |

904

imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |

904

MUX_PAD_CTRL(EPDC_PAD_CTRL));

905

MUX_PAD_CTRL(EPDC_PAD_CTRL));

905

906

/* Set pixel clock rates for EPDC in clock.c */

907

/* Set pixel clock rates for EPDC in clock.c */

907

908

panel_info.epdc_data.wv_modes.mode_init = 0;

909

panel_info.epdc_data.wv_modes.mode_init = 0;

909

panel_info.epdc_data.wv_modes.mode_du = 1;

910

panel_info.epdc_data.wv_modes.mode_du = 1;

910

panel_info.epdc_data.wv_modes.mode_gc4 = 3;

911

panel_info.epdc_data.wv_modes.mode_gc4 = 3;

911

panel_info.epdc_data.wv_modes.mode_gc8 = 2;

912

panel_info.epdc_data.wv_modes.mode_gc8 = 2;

912

panel_info.epdc_data.wv_modes.mode_gc16 = 2;

913

panel_info.epdc_data.wv_modes.mode_gc16 = 2;

913

panel_info.epdc_data.wv_modes.mode_gc32 = 2;

914

panel_info.epdc_data.wv_modes.mode_gc32 = 2;

914

915

panel_info.epdc_data.epdc_timings = panel_timings;

916

panel_info.epdc_data.epdc_timings = panel_timings;

916

917

setup_epdc_power();

918

setup_epdc_power();

918

}

919

}

919

920

void epdc_power_on(void)

921

void epdc_power_on(void)

921

{

922

{

922

unsigned int reg;

923

unsigned int reg;

923

struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;

924

struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;

924

925

/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */

926

/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */

926

gpio_set_value(IMX_GPIO_NR(2, 30), 1);

927

gpio_set_value(IMX_GPIO_NR(2, 30), 1);

927

udelay(1000);

928

udelay(1000);

928

929

/* Enable epdc signal pin */

930

/* Enable epdc signal pin */

930

epdc_enable_pins();

931

epdc_enable_pins();

931

932

/* Set PMIC Wakeup to high - enable Display power */

933

/* Set PMIC Wakeup to high - enable Display power */

933

gpio_set_value(IMX_GPIO_NR(2, 23), 1);

934

gpio_set_value(IMX_GPIO_NR(2, 23), 1);

934

935

/* Wait for PWRGOOD == 1 */

936

/* Wait for PWRGOOD == 1 */

936

while (1) {

937

while (1) {

937

reg = readl(&gpio_regs->gpio_psr);

938

reg = readl(&gpio_regs->gpio_psr);

938

if (!(reg & (1 << 31)))

939

if (!(reg & (1 << 31)))

939

break;

940

break;

940

941

udelay(100);

942

udelay(100);

942

}

943

}

943

944

/* Enable VCOM */

945

/* Enable VCOM */

945

gpio_set_value(IMX_GPIO_NR(4, 14), 1);

946

gpio_set_value(IMX_GPIO_NR(4, 14), 1);

946

947

udelay(500);

948

udelay(500);

948

}

949

}

949

950

void epdc_power_off(void)

951

void epdc_power_off(void)

951

{

952

{

952

/* Set PMIC Wakeup to low - disable Display power */

953

/* Set PMIC Wakeup to low - disable Display power */

953

gpio_set_value(IMX_GPIO_NR(2, 23), 0);

954

gpio_set_value(IMX_GPIO_NR(2, 23), 0);

954

955

/* Disable VCOM */

956

/* Disable VCOM */

956

gpio_set_value(IMX_GPIO_NR(4, 14), 0);

957

gpio_set_value(IMX_GPIO_NR(4, 14), 0);

957

958

epdc_disable_pins();

959

epdc_disable_pins();

959

960

/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */

961

/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */

961

gpio_set_value(IMX_GPIO_NR(2, 30), 0);

962

gpio_set_value(IMX_GPIO_NR(2, 30), 0);

962

}

963

}

963

#endif

964

#endif

964

965

#ifdef CONFIG_USB_EHCI_MX7

966

#ifdef CONFIG_USB_EHCI_MX7

966

static iomux_v3_cfg_t const usb_otg1_pads[] = {

967

static iomux_v3_cfg_t const usb_otg1_pads[] = {

967

MX7D_PAD_GPIO1_IO12__USB_OTG1_ID | MUX_PAD_CTRL(WEAK_PULLUP),

968

MX7D_PAD_GPIO1_IO12__USB_OTG1_ID | MUX_PAD_CTRL(WEAK_PULLUP),

968

/* OTG1 Power Enable */

969

/* OTG1 Power Enable */

969

MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),

970

MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),

970

/* OTG1 Over Current */

971

/* OTG1 Over Current */

971

MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(WEAK_PULLUP),

972

MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(WEAK_PULLUP),

972

973

};

974

};

974

975

static iomux_v3_cfg_t const usb_otg2_pads[] = {

976

static iomux_v3_cfg_t const usb_otg2_pads[] = {

976

/* OTG2 Power Enable */

977

/* OTG2 Power Enable */

977

MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),

978

MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),

978

/* OTG2 Over Current */

979

/* OTG2 Over Current */

979

MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(WEAK_PULLUP),

980

MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(WEAK_PULLUP),

980

};

981

};

981

982

static void setup_usb(void)

983

static void setup_usb(void)

983

{

984

{

984

imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,

985

imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,

985

ARRAY_SIZE(usb_otg1_pads));

986

ARRAY_SIZE(usb_otg1_pads));

986

gpio_direction_input(IMX_GPIO_NR(1, 4));

987

gpio_direction_input(IMX_GPIO_NR(1, 4));

987

988

imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,

989

imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,

989

ARRAY_SIZE(usb_otg2_pads));

990

ARRAY_SIZE(usb_otg2_pads));

990

gpio_direction_input(IMX_GPIO_NR(1, 6));

991

gpio_direction_input(IMX_GPIO_NR(1, 6));

991

}

992

}

992

993

int board_usb_phy_mode(int port)

994

int board_usb_phy_mode(int port)

994

{

995

{

995

if (port == 0)

996

if (port == 0)

996

return usb_phy_mode(port);

997

return usb_phy_mode(port);

997

else

998

else

998

return USB_INIT_HOST;

999

return USB_INIT_HOST;

999

}

1000

}

1000

#endif

1001

#endif

1001

1002

int board_early_init_f(void)

1003

int board_early_init_f(void)

1003

{

1004

{

1004

setup_iomux_reset_out();

1005

setup_iomux_reset_out();

1005

setup_iomux_uart6();

1006

setup_iomux_uart6();

1006

setup_iomux_uart2();

1007

setup_iomux_uart2();

1007

setup_iomux_uart7();

1008

setup_iomux_uart7();

1008

setup_iomux_uart3();

1009

setup_iomux_uart3();

1009

1010

#ifdef CONFIG_SYS_I2C_MXC

1011

#ifdef CONFIG_SYS_I2C_MXC

1011

setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);

1012

setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);

1012

setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);

1013

setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);

1013

setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);

1014

setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);

1014

setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);

1015

setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);

1015

#endif

1016

#endif

1016

1017

#ifdef CONFIG_MXC_SPI

1018

#ifdef CONFIG_MXC_SPI

1018

setup_spinor();

1019

setup_spinor();

1019

#endif

1020

#endif

1020

1021

#ifdef CONFIG_USB_EHCI_MX7

1022

#ifdef CONFIG_USB_EHCI_MX7

1022

setup_usb();

1023

setup_usb();

1023

#endif

1024

#endif

1024

setup_iomux_spi1();

1025

setup_iomux_spi1();

1025

setup_iomux_spi3();

1026

setup_iomux_spi3();

1026

setup_iomux_flexcan1();

1027

setup_iomux_flexcan1();

1027

setup_iomux_flexcan2();

1028

setup_iomux_flexcan2();

1028

setup_iomux_gpios();

1029

setup_iomux_gpios();

1029

setup_iomux_lvds_ch_sel();

1030

setup_iomux_lvds_ch_sel();

1030

setup_iomux_misc();

1031

setup_iomux_misc();

1031

1032

return 0;

1033

return 0;

1033

}

1034

}

1034

1035

int board_init(void)

1036

int board_init(void)

1036

{

1037

{

1037

/* address of boot parameters */

1038

/* address of boot parameters */

1038

gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

1039

gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

1039

1040

#ifdef CONFIG_FEC_MXC

1041

#ifdef CONFIG_FEC_MXC

1041

setup_fec(CONFIG_FEC_ENET_DEV);

1042

setup_fec(CONFIG_FEC_ENET_DEV);

1042

#endif

1043

#endif

1043

1044

#ifdef CONFIG_NAND_MXS

1045

#ifdef CONFIG_NAND_MXS

1045

setup_gpmi_nand();

1046

setup_gpmi_nand();

1046

#endif

1047

#endif

1047

1048

#ifdef CONFIG_FSL_QSPI

1049

#ifdef CONFIG_FSL_QSPI

1049

board_qspi_init();

1050

board_qspi_init();

1050

#endif

1051

#endif

1051

1052

return 0;

1053

return 0;

1053

}

1054

}

1054

1055

#ifdef CONFIG_CMD_BMODE

1056

#ifdef CONFIG_CMD_BMODE

1056

static const struct boot_mode board_boot_modes[] = {

1057

static const struct boot_mode board_boot_modes[] = {

1057

/* 4 bit bus width */

1058

/* 4 bit bus width */

1058

{"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},

1059

{"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},

1059

{"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)},

1060

{"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)},

1060

/* TODO: Nand */

1061

/* TODO: Nand */

1061

{"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},

1062

{"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},

1062

{NULL, 0},

1063

{NULL, 0},

1063

};

1064

};

1064

#endif

1065

#endif

1065

1066

#ifdef CONFIG_POWER

1067

#ifdef CONFIG_POWER

1067

#define I2C_PMIC 0

1068

#define I2C_PMIC 0

1068

int power_init_board(void)

1069

int power_init_board(void)

1069

{

1070

{

1070

struct pmic *p;

1071

struct pmic *p;

1071

int ret;

1072

int ret;

1072

unsigned int reg, rev_id;

1073

unsigned int reg, rev_id;

1073

1074

ret = power_pfuze3000_init(I2C_PMIC);

1075

ret = power_pfuze3000_init(I2C_PMIC);

1075

if (ret)

1076

if (ret)

1076

return ret;

1077

return ret;

1077

1078

p = pmic_get("PFUZE3000");

1079

p = pmic_get("PFUZE3000");

1079

ret = pmic_probe(p);

1080

ret = pmic_probe(p);

1080

if (ret)

1081

if (ret)

1081

return ret;

1082

return ret;

1082

1083

pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);

1084

pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);

1084

pmic_reg_read(p, PFUZE3000_REVID, &rev_id);

1085

pmic_reg_read(p, PFUZE3000_REVID, &rev_id);

1085

printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);

1086

printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);

1086

1087

/* disable Low Power Mode during standby mode */

1088

/* disable Low Power Mode during standby mode */

1088

pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);

1089

pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);

1089

reg |= 0x1;

1090

reg |= 0x1;

1090

pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);

1091

pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);

1091

1092

/* SW1A/1B mode set to APS/APS */

1093

/* SW1A/1B mode set to APS/APS */

1093

reg = 0x8;

1094

reg = 0x8;

1094

pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);

1095

pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);

1095

pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);

1096

pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);

1096

1097

/* SW1A/1B standby voltage set to 0.975V */

1098

/* SW1A/1B standby voltage set to 0.975V */

1098

reg = 0xb;

1099

reg = 0xb;

1099

pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);

1100

pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);

1100

pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);

1101

pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);

1101

1102

/* decrease SW1B normal voltage to 0.975V */

1103

/* decrease SW1B normal voltage to 0.975V */

1103

pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);

1104

pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);

1104

reg &= ~0x1f;

1105

reg &= ~0x1f;

1105

reg |= PFUZE3000_SW1AB_SETP(975);

1106

reg |= PFUZE3000_SW1AB_SETP(975);

1106

pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);

1107

pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);

1107

1108

return 0;

1109

return 0;

1109

}

1110

}

1110

#endif

1111

#endif

1111

1112

int board_late_init(void)

1113

int board_late_init(void)

1113

{

1114

{

1114

struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;

1115

struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;

1115

#ifdef CONFIG_CMD_BMODE

1116

#ifdef CONFIG_CMD_BMODE

1116

add_board_boot_modes(board_boot_modes);

1117

add_board_boot_modes(board_boot_modes);

1117

#endif

1118

#endif

1118

1119

#ifdef CONFIG_ENV_IS_IN_MMC

1120

#ifdef CONFIG_ENV_IS_IN_MMC

1120

board_late_mmc_env_init();

1121

board_late_mmc_env_init();

1121

#endif

1122

#endif

1122

1123

imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));

1124

imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));

1124

1125

set_wdog_reset(wdog);

1126

set_wdog_reset(wdog);

1126

1127

/* Check Board Information */

1128

/* Check Board Information */

1128

setup_i2c(1, CONFIG_SYS_I2C_SPEED,

1129

setup_i2c(1, CONFIG_SYS_I2C_SPEED,

1129

0x50, &i2c_pad_info2);

1130

0x50, &i2c_pad_info2);

1130

1131

struct smarcfimx7_id header;

1132

struct smarcfimx7_id header;

1132

1133

if (read_eeprom(&header) < 0)

1134

if (read_eeprom(&header) < 0)

1134

puts("Could not get board ID.\n");

1135

puts("Could not get board ID.\n");

1135

1136

puts("---------Embedian SMARC-FiMX7------------\n");

1137

puts("---------Embedian SMARC-FiMX7------------\n");

1137

printf("Board ID: %.*s\n",

1138

printf("Board ID: %.*s\n",

1138

sizeof(header.name), header.name);

1139

sizeof(header.name), header.name);

1139

printf("Board Revision: %.*s\n",

1140

printf("Board Revision: %.*s\n",

1140

sizeof(header.version), header.version);

1141

sizeof(header.version), header.version);

1141

printf("Board Serial#: %.*s\n",

1142

printf("Board Serial#: %.*s\n",

1142

sizeof(header.serial), header.serial);

1143

sizeof(header.serial), header.serial);

1143

puts("-----------------------------------------\n");

1144

puts("-----------------------------------------\n");

1144

1145

/* SMARC BOOT_SEL*/

1146

/* SMARC BOOT_SEL*/

1146

if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {

1147

if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {

1147

puts("BOOT_SEL Detected: OFF OFF OFF, unsupported boot up device: SATA...\n");

1148

puts("BOOT_SEL Detected: OFF OFF OFF, unsupported boot up device: SATA...\n");

1148

hang();

1149

hang();

1149

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {

1150

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {

1150

puts("BOOT_SEL Detected: OFF OFF ON, unsupported boot up device: NAND...\n");

1151

puts("BOOT_SEL Detected: OFF OFF ON, unsupported boot up device: NAND...\n");

1151

hang();

1152

hang();

1152

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {

1153

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {

1153

puts("BOOT_SEL Detected: OFF ON OFF, unsupported boot up device: Carrier eSPI...\n");

1154

puts("BOOT_SEL Detected: OFF ON OFF, unsupported boot up device: Carrier eSPI...\n");

1154

hang();

1155

hang();

1155

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {

1156

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {

1156

puts("BOOT_SEL Detected: ON OFF OFF, Load zImage from Carrier SD Card...\n");

1157

puts("BOOT_SEL Detected: ON OFF OFF, Load zImage from Carrier SD Card...\n");

1157

setenv_ulong("mmcdev", 0);

1158

setenv_ulong("mmcdev", 0);

1158

setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");

1159

setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");

1159

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {

1160

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {

1160

puts("BOOT_SEL Detected: OFF ON ON, Load zImage from Module eMMC Flash...\n");

1161

puts("BOOT_SEL Detected: OFF ON ON, Load zImage from Module eMMC Flash...\n");

1161

setenv_ulong("mmcdev", 1);

1162

setenv_ulong("mmcdev", 1);

1162

setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");

1163

setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");

1163

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {

1164

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {

1164

puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n");

1165

puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n");

1165

setenv("bootcmd", "run netboot;");

1166

setenv("bootcmd", "run netboot;");

1166

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {

1167

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {

1167

puts("BOOT_SEL Detected: OFF ON OFF, unsupported boot up device: Carrier SPI...\n");

1168

puts("BOOT_SEL Detected: OFF ON OFF, unsupported boot up device: Carrier SPI...\n");

1168

hang();

1169

hang();

1169

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {

1170

} else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {

1170

puts("BOOT_SEL Detected: ON ON ON, MOdule SPI Boot up is Default, Load zImage from Module eMMC...\n");

1171

puts("BOOT_SEL Detected: ON ON ON, MOdule SPI Boot up is Default, Load zImage from Module eMMC...\n");

1171

setenv_ulong("mmcdev", 1);

1172

setenv_ulong("mmcdev", 1);

1172

setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");

1173

setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");

1173

} else {

1174

} else {

1174

puts("unsupported boot devices\n");

1175

puts("unsupported boot devices\n");

1175

hang();

1176

hang();

1176

}

1177

}

1177

1178

return 0;

1179

return 0;

1179

}

1180

}

1180

1181

#ifdef CONFIG_FSL_FASTBOOT

1182

#ifdef CONFIG_FSL_FASTBOOT

1182

void board_fastboot_setup(void)

1183

void board_fastboot_setup(void)

1183

{

1184

{

1184

switch (get_boot_device()) {

1185

switch (get_boot_device()) {

1185

#if defined(CONFIG_FASTBOOT_STORAGE_MMC)

1186

#if defined(CONFIG_FASTBOOT_STORAGE_MMC)

1186

case SD1_BOOT:

1187

case SD1_BOOT:

1187

case MMC1_BOOT:

1188

case MMC1_BOOT:

1188

if (!getenv("fastboot_dev"))

1189

if (!getenv("fastboot_dev"))

1189

setenv("fastboot_dev", "mmc0");

1190

setenv("fastboot_dev", "mmc0");

1190

if (!getenv("bootcmd"))

1191

if (!getenv("bootcmd"))

1191

setenv("bootcmd", "boota mmc0");

1192

setenv("bootcmd", "boota mmc0");

1192

break;

1193

break;

1193

case SD3_BOOT:

1194

case SD3_BOOT:

1194

case MMC3_BOOT:

1195

case MMC3_BOOT:

1195

if (!getenv("fastboot_dev"))

1196

if (!getenv("fastboot_dev"))

1196

setenv("fastboot_dev", "mmc1");

1197

setenv("fastboot_dev", "mmc1");

1197

if (!getenv("bootcmd"))

1198

if (!getenv("bootcmd"))

1198

setenv("bootcmd", "boota mmc1");

1199

setenv("bootcmd", "boota mmc1");

1199

break;

1200

break;

1200

#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/

1201

#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/

1201

default:

1202

default:

1202

printf("unsupported boot devices\n");

1203

printf("unsupported boot devices\n");

1203

break;

1204

break;

1204

}

1205

}

1205

}

1206

}

1206

1207

#ifdef CONFIG_ANDROID_RECOVERY

1208

#ifdef CONFIG_ANDROID_RECOVERY

1208

1209

/* Use LID# for recovery key */

1210

/* Use LID# for recovery key */

1210

#define GPIO_VOL_DN_KEY IMX_GPIO_NR(5, 10)

1211

#define GPIO_VOL_DN_KEY IMX_GPIO_NR(5, 10)

1211

iomux_v3_cfg_t const recovery_key_pads[] = {

1212

iomux_v3_cfg_t const recovery_key_pads[] = {

1212

(MX7D_PAD_SD2_WP__GPIO5_IO10 | MUX_PAD_CTRL(BUTTON_PAD_CTRL)),

1213

(MX7D_PAD_SD2_WP__GPIO5_IO10 | MUX_PAD_CTRL(BUTTON_PAD_CTRL)),

1213

};

1214

};

1214

1215

int check_recovery_cmd_file(void)

1216

int check_recovery_cmd_file(void)

1216

{

1217

{

1217

int button_pressed = 0;

1218

int button_pressed = 0;

1218

int recovery_mode = 0;

1219

int recovery_mode = 0;

1219

1220

recovery_mode = recovery_check_and_clean_flag();

1221

recovery_mode = recovery_check_and_clean_flag();

1221

1222

/* Check Recovery Combo Button press or not. */

1223

/* Check Recovery Combo Button press or not. */

1223

imx_iomux_v3_setup_multiple_pads(recovery_key_pads,

1224

imx_iomux_v3_setup_multiple_pads(recovery_key_pads,

1224

ARRAY_SIZE(recovery_key_pads));

1225

ARRAY_SIZE(recovery_key_pads));

1225

1226

gpio_direction_input(GPIO_VOL_DN_KEY);

1227

gpio_direction_input(GPIO_VOL_DN_KEY);

1227

1228

if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */

1229

if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */

1229

button_pressed = 1;

1230

button_pressed = 1;

1230

printf("Recovery key pressed\n");

1231

printf("Recovery key pressed\n");

1231

}

1232

}

1232

1233

return recovery_mode || button_pressed;

1234

return recovery_mode || button_pressed;

1234

}

1235

}

1235

1236

void board_recovery_setup(void)

1237

void board_recovery_setup(void)

1237

{

1238

{

1238

int bootdev = get_boot_device();

1239

int bootdev = get_boot_device();

1239

1240

switch (bootdev) {

1241

switch (bootdev) {

1241

#if defined(CONFIG_FASTBOOT_STORAGE_MMC)

1242

#if defined(CONFIG_FASTBOOT_STORAGE_MMC)

1242

case SD1_BOOT:

1243

case SD1_BOOT:

1243

case MMC1_BOOT:

1244

case MMC1_BOOT:

1244

if (!getenv("bootcmd_android_recovery"))

1245

if (!getenv("bootcmd_android_recovery"))

1245

setenv("bootcmd_android_recovery", "boota mmc0 recovery");

1246

setenv("bootcmd_android_recovery", "boota mmc0 recovery");

1246

break;

1247

break;

1247

case SD3_BOOT:

1248

case SD3_BOOT:

1248

case MMC3_BOOT:

1249

case MMC3_BOOT:

1249

if (!getenv("bootcmd_android_recovery"))

1250

if (!getenv("bootcmd_android_recovery"))

1250

setenv("bootcmd_android_recovery", "boota mmc1 recovery");

1251

setenv("bootcmd_android_recovery", "boota mmc1 recovery");

1251

break;

1252

break;

1252

#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/

1253

#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/

1253

default:

1254

default:

1254

printf("Unsupported bootup device for recovery: dev: %d\n",

1255

printf("Unsupported bootup device for recovery: dev: %d\n",

1255

bootdev);

1256

bootdev);

1256

return;

1257

return;

1257

}

1258

}

1258

1259

printf("setup env for recovery..\n");

1260

printf("setup env for recovery..\n");

1260

setenv("bootcmd", "run bootcmd_android_recovery");

1261

setenv("bootcmd", "run bootcmd_android_recovery");

1261

}

1262

}

1262

#endif /*CONFIG_ANDROID_RECOVERY*/

1263

#endif /*CONFIG_ANDROID_RECOVERY*/

1263

1264

#endif /*CONFIG_FSL_FASTBOOT*/

1265

#endif /*CONFIG_FSL_FASTBOOT*/

GITLAB

Fix pinmux for SMARC-FiMX7 rev. 00B0

 /*
  * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx7-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/boot_mode.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
 #include <fsl_esdhc.h>
 #include <mmc.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <power/pmic.h>
 #include <power/pfuze3000_pmic.h>
 #include "pfuze.h"
 #include <pwm.h>
 #include <i2c.h>
 #include <asm/imx-common/mxc_i2c.h>
 #include <asm/arch/crm_regs.h>
 #include <usb.h>
 #include <usb/ehci-fsl.h>
 #if defined(CONFIG_MXC_EPDC)
 #include <lcd.h>
 #include <mxc_epdc_fb.h>
 #endif
 #include <asm/imx-common/video.h>
 #include "smarcfimx7.h"
 #ifdef CONFIG_FSL_FASTBOOT
 #include <fsl_fastboot.h>
 #ifdef CONFIG_ANDROID_RECOVERY
 #include <recovery.h>
 #endif
 #endif /*CONFIG_FSL_FASTBOOT*/
 DECLARE_GLOBAL_DATA_PTR;
 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
 	PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
 	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
 #define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
 #define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
 #define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
 	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
         PAD_CTL_DSE_3P3V_49OHM)
 #define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
 #define BUTTON_PAD_CTRL    (PAD_CTL_PUS_PU5KOHM | PAD_CTL_DSE_3P3V_98OHM)
 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
 #define EPDC_PAD_CTRL	0x0
 #define WEAK_PULLUP (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM | \
 	PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 /*
  * Read header information from EEPROM into global structure.
  */
 static int read_eeprom(struct smarcfimx7_id *header)
 {
         i2c_set_bus_num(1);
         /* Check if baseboard eeprom is available */
         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
                 puts("Could not probe the EEPROM; something fundamentally "
                         "wrong on the I2C bus.\n");
                 return -ENODEV;
         }
         /* read the eeprom using i2c */
         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
                      sizeof(struct smarcfimx7_id))) {
                 puts("Could not read the EEPROM; something fundamentally"
                         " wrong on the I2C bus.\n");
                 return -EIO;
         }
         if (header->magic != 0xEE3355AA) {
                 /*
                  * read the eeprom using i2c again,
                  * but use only a 1 byte address
                  */
                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
                              sizeof(struct smarcfimx7_id))) {
                         puts("Could not read the EEPROM; something "
                                 "fundamentally wrong on the I2C bus.\n");
                         return -EIO;
                 }
                 if (header->magic != 0xEE3355AA) {
                         printf("Incorrect magic number (0x%x) in EEPROM\n",
                                         header->magic);
                         return -EINVAL;
                 }
         }
         return 0;
 }
 /* I2C1 for PMIC (I2C_PM)*/
 static struct i2c_pads_info i2c_pad_info1 = {
 	.scl = {
 		.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
 		.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
 		.gp = IMX_GPIO_NR(4, 8),
 	},
 	.sda = {
 		.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
 		.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
 		.gp = IMX_GPIO_NR(4, 9),
 	},
 };
 /* I2C2 for I2C_GP */
 static struct i2c_pads_info i2c_pad_info2 = {
         .scl = {
                 .i2c_mode = MX7D_PAD_I2C2_SCL__I2C2_SCL | PC,
                 .gpio_mode = MX7D_PAD_I2C2_SCL__GPIO4_IO10 | PC,
                 .gp = IMX_GPIO_NR(4, 10),
         },
         .sda = {
                 .i2c_mode = MX7D_PAD_I2C2_SDA__I2C2_SDA | PC,
                 .gpio_mode = MX7D_PAD_I2C2_SDA__GPIO4_IO11 | PC,
                 .gp = IMX_GPIO_NR(4, 11),
         },
 };
 /* I2C3 for I2C_LCD */
 static struct i2c_pads_info i2c_pad_info3 = {
 	.scl = {
 		.i2c_mode = MX7D_PAD_I2C3_SCL__I2C3_SCL | PC,
 		.gpio_mode = MX7D_PAD_I2C3_SCL__GPIO4_IO12 | PC,
 		.gp = IMX_GPIO_NR(4, 12),
 	},
 	.sda = {
 		.i2c_mode = MX7D_PAD_I2C3_SDA__I2C3_SDA | PC,
 		.gpio_mode = MX7D_PAD_I2C3_SDA__GPIO4_IO13 | PC,
 		.gp = IMX_GPIO_NR(4, 13),
 	},
 };
 /* I2C4 for I2C_CAM1 */
 static struct i2c_pads_info i2c_pad_info4 = {
         .scl = {
                 .i2c_mode = MX7D_PAD_I2C4_SCL__I2C4_SCL | PC,
                 .gpio_mode = MX7D_PAD_I2C4_SCL__GPIO4_IO14 | PC,
                 .gp = IMX_GPIO_NR(4, 14),
         },
         .sda = {
                 .i2c_mode = MX7D_PAD_I2C4_SDA__I2C4_SDA | PC,
                 .gpio_mode = MX7D_PAD_I2C4_SDA__GPIO4_IO15 | PC,
                 .gp = IMX_GPIO_NR(4, 15),
         },
 };
 #endif
 int dram_init(void)
 {
 	gd->ram_size = PHYS_SDRAM_SIZE;
 	return 0;
 }
 static iomux_v3_cfg_t const wdog_pads[] = {
 	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 /* SER0/UART6 */
 static iomux_v3_cfg_t const uart6_pads[] = {
         MX7D_PAD_EPDC_DATA09__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX7D_PAD_EPDC_DATA08__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 /* SER1/UART2 */
 static iomux_v3_cfg_t const uart2_pads[] = {
         MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 /* SER2/UART7 */
 static iomux_v3_cfg_t const uart7_pads[] = {
         MX7D_PAD_EPDC_DATA13__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX7D_PAD_EPDC_DATA12__UART7_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 /* SER3/UART3 Debug Port */
 static iomux_v3_cfg_t const uart3_pads[] = {
         MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 /* RESET_OUT# */
 static iomux_v3_cfg_t const reset_out_pads[] = {
         MX7D_PAD_EPDC_BDR1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 /* SD Card */
 static iomux_v3_cfg_t const usdhc1_pads[] = {
 	MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 	/*CD */
         MX7D_PAD_SD1_WP__GPIO5_IO1  | MUX_PAD_CTRL(NO_PAD_CTRL), 	/* WP */
 	MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* SDIO_PWR_EN */
 };
 /* eMMC */
 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
 	MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_STROBE__SD3_STROBE	 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 /* SPI0 */
 static iomux_v3_cfg_t const ecspi1_pads[] = {
         MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL),    /*SS0#*/
         MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/
 };
 /* ESPI */
 static iomux_v3_cfg_t const ecspi3_pads[] = {
         MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL),  /*SS0#*/
         MX7D_PAD_SD2_CD_B__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL),      /*SS2#*/
 };
 /* CAN0/FLEXCAN1 */
 static iomux_v3_cfg_t const flexcan1_pads[] = {
         MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX | MUX_PAD_CTRL(WEAK_PULLUP),
         MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX | MUX_PAD_CTRL(WEAK_PULLUP),
 };
 /* CAN1/FLEXCAN2 */
 static iomux_v3_cfg_t const flexcan2_pads[] = {
         MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX | MUX_PAD_CTRL(WEAK_PULLUP),
         MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX | MUX_PAD_CTRL(WEAK_PULLUP),
 };
 /* GPIOs */
 static iomux_v3_cfg_t const gpios_pads[] = {
         MX7D_PAD_EPDC_DATA00__GPIO2_IO0 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO0 */
         MX7D_PAD_EPDC_DATA01__GPIO2_IO1 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO1 */
         MX7D_PAD_EPDC_DATA02__GPIO2_IO2 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO2 */
         MX7D_PAD_EPDC_DATA03__GPIO2_IO3 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO3 */
         MX7D_PAD_EPDC_DATA04__GPIO2_IO4 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO4 */
         MX7D_PAD_EPDC_DATA05__GPIO2_IO5 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO6 */
         MX7D_PAD_EPDC_DATA07__GPIO2_IO7 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO7 */
         MX7D_PAD_EPDC_DATA06__GPIO2_IO6 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO8 */
         MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 | MUX_PAD_CTRL(WEAK_PULLUP),  /* GPIO9 */
         MX7D_PAD_UART3_RTS_B__GPIO4_IO6 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO10 */
         MX7D_PAD_UART3_CTS_B__GPIO4_IO7 | MUX_PAD_CTRL(WEAK_PULLUP),    /* GPIO11 */
 };
 /* LVDS channel selection, set low as single channel LVDS and high as dual channel LVDS */
 static iomux_v3_cfg_t const lvds_ch_sel_pads[] = {
         MX7D_PAD_SD2_CMD__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),       /* LVDS_CH_SEL */
 };
 /* Misc. pins */
 static iomux_v3_cfg_t const misc_pads[] = {
         MX7D_PAD_SD2_DATA0__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),     /* SLEEP# */
-        MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), 	/* CHARGER_PRSNT# */
+        MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(WEAK_PULLUP), 	/* CHARGER_PRSNT# */
         MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(WEAK_PULLUP),     /* CHARGING# */
         MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP),  /* CARRIER_STBY# */
-        MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | MUX_PAD_CTRL(WEAK_PULLUP),  /* CARRIER_PWR_ON# */
         MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),   /* BATLOW# */
 	MX7D_PAD_EPDC_BDR0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),   	/* PCIe_RST# */
         MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),	/* PCIe_WAKE# */
+        MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), 	/* WDT_TIME_OUT# */
 };
 #ifdef CONFIG_VIDEO_MXS
 static iomux_v3_cfg_t const lcd_pads[] = {
 	MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX7D_PAD_LCD_RESET__GPIO3_IO4	| MUX_PAD_CTRL(LCD_PAD_CTRL),
 };
 static iomux_v3_cfg_t const backlight_pads[] = {
         /* Backlight Enable for RGB: S127 */
-	MX7D_PAD_GPIO1_IO02__GPIO1_IO2 | MUX_PAD_CTRL(WEAK_PULLUP),
+        MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | MUX_PAD_CTRL(WEAK_PULLUP),
         /* PWM Backlight Control: S141. Use GPIO for Brightness adjustment, duty cycle = period */
-       	MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
+       	MX7D_PAD_GPIO1_IO02__GPIO1_IO2 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 void do_enable_parallel_lcd(struct display_info_t const *dev)
 {
 	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 	imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
 	/* Reset LCD */
 	gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
 	/* Turn on Backlight */
-        gpio_direction_output(IMX_GPIO_NR(1, 2), 1);
+        gpio_direction_output(IMX_GPIO_NR(6, 17), 1);
         /* Set Brightness to high */
-       	gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
+       	gpio_direction_output(IMX_GPIO_NR(1, 2) , 1);
 }
 /* LVDS Panel for AUO G070VW01 V0 7-inch Color TFT 800x480 Panel Settings */
 struct display_info_t const displays[] = {{
         .bus = ELCDIF1_IPS_BASE_ADDR,
         .addr = 0,
         .pixfmt = 24,
         .detect = NULL,
         .enable = do_enable_parallel_lcd,
         .mode   = {
                 .name          	= "G070VW01",
                 .xres           = 800,
                 .yres           = 480,
                 .pixclock       = 31069,
                 .left_margin    = 64,
                 .right_margin   = 64,
                 .upper_margin   = 12,
                 .lower_margin   = 4,
                 .hsync_len      = 128,
                 .vsync_len      = 12,
                 .sync           = 0,
                 .vmode          = FB_VMODE_NONINTERLACED
 } } };
 size_t display_count = ARRAY_SIZE(displays);
 #endif
 static void setup_iomux_uart6(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));
 }
 static void setup_iomux_uart2(void)
 {
         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 }
 static void setup_iomux_uart7(void)
 {
         imx_iomux_v3_setup_multiple_pads(uart7_pads, ARRAY_SIZE(uart7_pads));
 }
 static void setup_iomux_uart3(void)
 {
         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 }
 static void setup_iomux_reset_out(void)
 {
         imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads));
         /* Set CPU RESET_OUT as Output */
         gpio_direction_output(IMX_GPIO_NR(2, 29) , 0);
 }
 static void setup_iomux_spi1(void)
 {
         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
         gpio_direction_output(IMX_GPIO_NR(4, 19), 0);
         gpio_direction_output(IMX_GPIO_NR(4, 0), 0);
 }
 static void setup_iomux_spi3(void)
 {
         imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
         gpio_direction_output(IMX_GPIO_NR(6, 22), 0);
         gpio_direction_output(IMX_GPIO_NR(5, 9), 0);
 }
 static void setup_iomux_gpios(void)
 {
         imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads));
         gpio_direction_output(IMX_GPIO_NR(2, 0), 0);
         gpio_direction_output(IMX_GPIO_NR(2, 1), 0);
         gpio_direction_output(IMX_GPIO_NR(2, 2), 0);
         gpio_direction_output(IMX_GPIO_NR(2, 3), 0);
         gpio_direction_output(IMX_GPIO_NR(2, 4), 0);
         gpio_direction_input(IMX_GPIO_NR(2, 5));
         gpio_direction_input(IMX_GPIO_NR(2, 7));
         gpio_direction_input(IMX_GPIO_NR(2, 6));
         gpio_direction_input(IMX_GPIO_NR(4, 1));
         gpio_direction_input(IMX_GPIO_NR(4, 6));
         gpio_direction_input(IMX_GPIO_NR(4, 7));
 }
 static void setup_iomux_lvds_ch_sel(void)
 {
         imx_iomux_v3_setup_multiple_pads(lvds_ch_sel_pads, ARRAY_SIZE(lvds_ch_sel_pads));
         gpio_direction_output(IMX_GPIO_NR(5, 13), 0);
 }
 static void setup_iomux_misc(void)
 {
         imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
         gpio_direction_input(IMX_GPIO_NR(5, 14));
         gpio_direction_input(IMX_GPIO_NR(1, 8));
         gpio_direction_input(IMX_GPIO_NR(1, 9));
         gpio_direction_input(IMX_GPIO_NR(5, 11));
         gpio_direction_output(IMX_GPIO_NR(6, 16), 0);
-        gpio_direction_output(IMX_GPIO_NR(6, 17), 0);
         gpio_direction_output(IMX_GPIO_NR(2, 28), 0);
        	udelay(500);
         gpio_direction_output(IMX_GPIO_NR(2, 28), 1);
         gpio_direction_input(IMX_GPIO_NR(2, 31));
+        /* Set WDT_TIME_OUT# as Output High */
+        gpio_direction_output(IMX_GPIO_NR(7, 14), 1);
 }
 static void setup_iomux_flexcan1(void)
 {
         imx_iomux_v3_setup_multiple_pads(flexcan1_pads, ARRAY_SIZE(flexcan1_pads));
 }
 static void setup_iomux_flexcan2(void)
 {
         imx_iomux_v3_setup_multiple_pads(flexcan2_pads, ARRAY_SIZE(flexcan2_pads));
 }
 #ifdef CONFIG_FSL_ESDHC
 #define USDHC1_CD_GPIO	IMX_GPIO_NR(5, 0)
 #define USDHC1_PWR_GPIO	IMX_GPIO_NR(5, 2)
 #define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)
 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 	{USDHC1_BASE_ADDR, 0, 4},
 	{USDHC3_BASE_ADDR},
 };
 int board_mmc_get_env_dev(int devno)
 {
 	if (devno == 2)
 		devno--;
 	return devno;
 }
 int mmc_map_to_kernel_blk(int dev_no)
 {
 	if (dev_no == 1)
 		dev_no++;
 	return dev_no;
 }
 int board_mmc_getcd(struct mmc *mmc)
 {
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	int ret = 0;
 	switch (cfg->esdhc_base) {
 	case USDHC1_BASE_ADDR:
 		ret = !gpio_get_value(USDHC1_CD_GPIO);
 		break;
 	case USDHC3_BASE_ADDR:
 		ret = 1; /* Assume uSDHC3 emmc is always present */
 		break;
 	}
 	return ret;
 }
 int board_mmc_init(bd_t *bis)
 {
 	int i, ret;
 	/*
 	 * According to the board_mmc_init() the following map is done:
 	 * (U-Boot device node)    (Physical Port)
 	 * mmc0                    USDHC1
 	 * mmc2                    USDHC3 (eMMC)
 	 */
 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 		switch (i) {
 		case 0:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 			gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
 			gpio_direction_input(USDHC1_CD_GPIO);
 			gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
 			gpio_direction_output(USDHC1_PWR_GPIO, 0);
 			udelay(500);
 			gpio_direction_output(USDHC1_PWR_GPIO, 1);
 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 			break;
 		case 1:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
 			gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");
 			gpio_direction_output(USDHC3_PWR_GPIO, 0);
 			udelay(500);
 			gpio_direction_output(USDHC3_PWR_GPIO, 1);
 			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 			break;
 		default:
 			printf("Warning: you configured more USDHC controllers"
 				"(%d) than supported by the board\n", i + 1);
 			return -EINVAL;
 			}
 			ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 			if (ret)
 				return ret;
 	}
 	return 0;
 }
 #endif
 #ifdef CONFIG_FEC_MXC
 static iomux_v3_cfg_t const fec1_pads[] = {
 	MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 	MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 };
 static iomux_v3_cfg_t const fec2_pads[] = {
 	MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1  | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2  | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 	MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 	MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 };
 static void setup_iomux_fec(void)
 {
 	if (0 == CONFIG_FEC_ENET_DEV) {
 		imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
         	gpio_direction_input(IMX_GPIO_NR(7, 15));
 	} else {
 		imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
-                gpio_direction_input(IMX_GPIO_NR(7, 14));
+                gpio_direction_input(IMX_GPIO_NR(7, 13));
 	}
 }
 int board_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_MAC_ADDR_IN_EEPROM)
         uchar env_enetaddr[6];
         int enetaddr_found;
         enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr);
         uint8_t enetaddr[8];
         int eeprom_mac_read;
         /* Read Ethernet MAC address from EEPROM */
         eeprom_mac_read = smarcfimx7_read_mac_address(enetaddr);
         /*
          * MAC address not present in the environment
          * try and read the MAC address from EEPROM flash
          * and set it.
          */
         if (!enetaddr_found) {
                 if (eeprom_mac_read)
                         /* Set Ethernet MAC address from EEPROM */
                         smarcfimx7_sync_env_enetaddr(enetaddr);
         } else {
                 /*
                  * MAC address present in environment compare it with
                  * the MAC address in EEPROM and warn on mismatch
                  */
                 if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
                         printf("Warning: MAC address in EEPROM don't match "
                                         "with the MAC address in the environment\n");
                         printf("Default using MAC address from environment\n");
         }
         uchar env_enet1addr[6];
         int enet1addr_found;
         enet1addr_found = eth_getenv_enetaddr("eth1addr", env_enet1addr);
         uint8_t enet1addr[8];
         int eeprom_mac1_read;
         /* Read Ethernet MAC address from EEPROM */
         eeprom_mac1_read = smarcfimx7_read_mac1_address(enet1addr);
         /*
          * MAC address not present in the environment
          * try and read the MAC address from EEPROM flash
          * and set it.
          */
         if (!enet1addr_found) {
                 if (eeprom_mac1_read)
                         /* Set Ethernet MAC address from EEPROM */
                         smarcfimx7_sync_env_enet1addr(enet1addr);
         } else {
                 /*
                  * MAC address present in environment compare it with
                  * the MAC address in EEPROM and warn on mismatch
                  */
                 if (eeprom_mac_read && memcmp(enet1addr, env_enet1addr, 6))
                         printf("Warning: 2nd GBE MAC address in EEPROM don't match "
                                         "with the MAC address in the environment\n");
                         printf("Default using 2nd GBE MAC address from environment\n");
         }
 #endif
 	int ret;
 	setup_iomux_fec();
 	ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
 		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
 	if (ret)
 		printf("FEC1 MXC: %s:failed\n", __func__);
 	return ret;
 }
 static int setup_fec(int fec_id)
 {
         struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
                 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
         if (0 == fec_id) {
                 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
                 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
                         (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
                          IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
         } else {
                 /* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/
                 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
                         (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |
                          IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);
         }
         return set_clk_enet(ENET_125MHz);
 }
 int board_phy_config(struct phy_device *phydev)
 {
         /* enable rgmii rxc skew and phy mode select to RGMII copper */
         /*phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);*/
         if (phydev->drv->config)
                 phydev->drv->config(phydev);
         return 0;
 }
 #endif
 #ifdef CONFIG_MXC_SPI
 /* SPI2 (SPINOR) */
 static iomux_v3_cfg_t const ecspi2_pads[] = {
         MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),	/*SS0#*/
 };
 static void setup_spinor(void)
 {
         imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
         gpio_direction_output(IMX_GPIO_NR(4, 23), 0);
 }
 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 {
         return (bus == 1 && cs == 0) ? (IMX_GPIO_NR(4, 23)) : -1;
 }
 #endif
 #ifdef CONFIG_MXC_EPDC
 static iomux_v3_cfg_t const epdc_enable_pads[] = {
 	MX7D_PAD_EPDC_DATA00__EPDC_DATA0	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_DATA01__EPDC_DATA1	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_DATA02__EPDC_DATA2	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_DATA03__EPDC_DATA3	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_DATA04__EPDC_DATA4	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_DATA05__EPDC_DATA5	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_DATA06__EPDC_DATA6	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_DATA07__EPDC_DATA7	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_SDLE__EPDC_SDLE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_SDOE__EPDC_SDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_GDOE__EPDC_GDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_GDRL__EPDC_GDRL		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_GDSP__EPDC_GDSP		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_BDR0__EPDC_BDR0		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX7D_PAD_EPDC_BDR1__EPDC_BDR1		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 };
 static iomux_v3_cfg_t const epdc_disable_pads[] = {
 	MX7D_PAD_EPDC_DATA00__GPIO2_IO0,
 	MX7D_PAD_EPDC_DATA01__GPIO2_IO1,
 	MX7D_PAD_EPDC_DATA02__GPIO2_IO2,
 	MX7D_PAD_EPDC_DATA03__GPIO2_IO3,
 	MX7D_PAD_EPDC_DATA04__GPIO2_IO4,
 	MX7D_PAD_EPDC_DATA05__GPIO2_IO5,
 	MX7D_PAD_EPDC_DATA06__GPIO2_IO6,
 	MX7D_PAD_EPDC_DATA07__GPIO2_IO7,
 	MX7D_PAD_EPDC_SDCLK__GPIO2_IO16,
 	MX7D_PAD_EPDC_SDLE__GPIO2_IO17,
 	MX7D_PAD_EPDC_SDOE__GPIO2_IO18,
 	MX7D_PAD_EPDC_SDSHR__GPIO2_IO19,
 	MX7D_PAD_EPDC_SDCE0__GPIO2_IO20,
 	MX7D_PAD_EPDC_SDCE1__GPIO2_IO21,
 	MX7D_PAD_EPDC_GDCLK__GPIO2_IO24,
 	MX7D_PAD_EPDC_GDOE__GPIO2_IO25,
 	MX7D_PAD_EPDC_GDRL__GPIO2_IO26,
 	MX7D_PAD_EPDC_GDSP__GPIO2_IO27,
 	MX7D_PAD_EPDC_BDR0__GPIO2_IO28,
 	MX7D_PAD_EPDC_BDR1__GPIO2_IO29,
 };
 vidinfo_t panel_info = {
 	.vl_refresh = 85,
 	.vl_col = 1024,
 	.vl_row = 758,
 	.vl_pixclock = 40000000,
 	.vl_left_margin = 12,
 	.vl_right_margin = 76,
 	.vl_upper_margin = 4,
 	.vl_lower_margin = 5,
 	.vl_hsync = 12,
 	.vl_vsync = 2,
 	.vl_sync = 0,
 	.vl_mode = 0,
 	.vl_flag = 0,
 	.vl_bpix = 3,
 	.cmap = 0,
 };
 struct epdc_timing_params panel_timings = {
 	.vscan_holdoff = 4,
 	.sdoed_width = 10,
 	.sdoed_delay = 20,
 	.sdoez_width = 10,
 	.sdoez_delay = 20,
 	.gdclk_hp_offs = 524,
 	.gdsp_offs = 327,
 	.gdoe_offs = 0,
 	.gdclk_offs = 19,
 	.num_ce = 1,
 };
 static void setup_epdc_power(void)
 {
 	/* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */
 	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
 		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
 	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 		IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0);
 	/* Setup epdc voltage */
 	/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
 	imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	gpio_direction_input(IMX_GPIO_NR(2, 31));
 	/* EPDC_VCOM0 - GPIO4[14] for VCOM control */
 	imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* Set as output */
 	gpio_direction_output(IMX_GPIO_NR(4, 14), 1);
 	/* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */
 	imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* Set as output */
 	gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
 	/* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */
 	imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* Set as output */
 	gpio_direction_output(IMX_GPIO_NR(2, 30), 1);
 }
 static void epdc_enable_pins(void)
 {
 	/* epdc iomux settings */
 	imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
 				ARRAY_SIZE(epdc_enable_pads));
 }
 static void epdc_disable_pins(void)
 {
 	/* Configure MUX settings for EPDC pins to GPIO  and drive to 0 */
 	imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
 				ARRAY_SIZE(epdc_disable_pads));
 }
 static void setup_epdc(void)
 {
 	/*** epdc Maxim PMIC settings ***/
 	/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
 	imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* EPDC_VCOM0 - GPIO4[14] for VCOM control */
 	imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */
 	imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */
 	imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* Set pixel clock rates for EPDC in clock.c */
 	panel_info.epdc_data.wv_modes.mode_init = 0;
 	panel_info.epdc_data.wv_modes.mode_du = 1;
 	panel_info.epdc_data.wv_modes.mode_gc4 = 3;
 	panel_info.epdc_data.wv_modes.mode_gc8 = 2;
 	panel_info.epdc_data.wv_modes.mode_gc16 = 2;
 	panel_info.epdc_data.wv_modes.mode_gc32 = 2;
 	panel_info.epdc_data.epdc_timings = panel_timings;
 	setup_epdc_power();
 }
 void epdc_power_on(void)
 {
 	unsigned int reg;
 	struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
 	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
 	gpio_set_value(IMX_GPIO_NR(2, 30), 1);
 	udelay(1000);
 	/* Enable epdc signal pin */
 	epdc_enable_pins();
 	/* Set PMIC Wakeup to high - enable Display power */
 	gpio_set_value(IMX_GPIO_NR(2, 23), 1);
 	/* Wait for PWRGOOD == 1 */
 	while (1) {
 		reg = readl(&gpio_regs->gpio_psr);
 		if (!(reg & (1 << 31)))
 			break;
 		udelay(100);
 	}
 	/* Enable VCOM */
 	gpio_set_value(IMX_GPIO_NR(4, 14), 1);
 	udelay(500);
 }
 void epdc_power_off(void)
 {
 	/* Set PMIC Wakeup to low - disable Display power */
 	gpio_set_value(IMX_GPIO_NR(2, 23), 0);
 	/* Disable VCOM */
 	gpio_set_value(IMX_GPIO_NR(4, 14), 0);
 	epdc_disable_pins();
 	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
 	gpio_set_value(IMX_GPIO_NR(2, 30), 0);
 }
 #endif
 #ifdef CONFIG_USB_EHCI_MX7
 static iomux_v3_cfg_t const usb_otg1_pads[] = {
         MX7D_PAD_GPIO1_IO12__USB_OTG1_ID | MUX_PAD_CTRL(WEAK_PULLUP),
 	/* OTG1 Power Enable */
         MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 	/* OTG1 Over Current */
         MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(WEAK_PULLUP),
 };
 static iomux_v3_cfg_t const usb_otg2_pads[] = {
         /* OTG2 Power Enable */
         MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
         /* OTG2 Over Current */
         MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(WEAK_PULLUP),
 };
 static void setup_usb(void)
 {
 	imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
 						 ARRAY_SIZE(usb_otg1_pads));
         gpio_direction_input(IMX_GPIO_NR(1, 4));
 	imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
 						 ARRAY_SIZE(usb_otg2_pads));
         gpio_direction_input(IMX_GPIO_NR(1, 6));
 }
 int board_usb_phy_mode(int port)
 {
 	if (port == 0)
 		return usb_phy_mode(port);
 	else
 		return USB_INIT_HOST;
 }
 #endif
 int board_early_init_f(void)
 {
         setup_iomux_reset_out();
 	setup_iomux_uart6();
         setup_iomux_uart2();
         setup_iomux_uart7();
         setup_iomux_uart3();
 #ifdef CONFIG_SYS_I2C_MXC
 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
 #endif
 #ifdef CONFIG_MXC_SPI
         setup_spinor();
 #endif
 #ifdef CONFIG_USB_EHCI_MX7
 	setup_usb();
 #endif
         setup_iomux_spi1();
         setup_iomux_spi3();
         setup_iomux_flexcan1();
         setup_iomux_flexcan2();
         setup_iomux_gpios();
 	setup_iomux_lvds_ch_sel();
         setup_iomux_misc();
 	return 0;
 }
 int board_init(void)
 {
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 #ifdef CONFIG_FEC_MXC
         setup_fec(CONFIG_FEC_ENET_DEV);
 #endif
 #ifdef CONFIG_NAND_MXS
 	setup_gpmi_nand();
 #endif
 #ifdef CONFIG_FSL_QSPI
 	board_qspi_init();
 #endif
 	return 0;
 }
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
 	/* 4 bit bus width */
 	{"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
 	{"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)},
 	/* TODO: Nand */
 	{"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},
 	{NULL,   0},
 };
 #endif
 #ifdef CONFIG_POWER
 #define I2C_PMIC	0
 int power_init_board(void)
 {
 	struct pmic *p;
 	int ret;
 	unsigned int reg, rev_id;
 	ret = power_pfuze3000_init(I2C_PMIC);
 	if (ret)
 		return ret;
 	p = pmic_get("PFUZE3000");
 	ret = pmic_probe(p);
 	if (ret)
 		return ret;
 	pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
 	pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
 	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
 	/* disable Low Power Mode during standby mode */
 	pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
 	reg |= 0x1;
 	pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
 	/* SW1A/1B mode set to APS/APS */
 	reg = 0x8;
 	pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
 	pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
 	/* SW1A/1B standby voltage set to 0.975V */
 	reg = 0xb;
 	pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
 	pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
 	/* decrease SW1B normal voltage to 0.975V */
 	pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
 	reg &= ~0x1f;
 	reg |= PFUZE3000_SW1AB_SETP(975);
 	pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
 	return 0;
 }
 #endif
 int board_late_init(void)
 {
 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
 #endif
 #ifdef CONFIG_ENV_IS_IN_MMC
 	board_late_mmc_env_init();
 #endif
 	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 	set_wdog_reset(wdog);
 /* Check Board Information */
         setup_i2c(1, CONFIG_SYS_I2C_SPEED,
                         0x50, &i2c_pad_info2);
         struct smarcfimx7_id header;
         if (read_eeprom(&header) < 0)
         puts("Could not get board ID.\n");
         puts("---------Embedian SMARC-FiMX7------------\n");
         printf("Board ID:               %.*s\n",
                sizeof(header.name), header.name);
         printf("Board Revision:         %.*s\n",
                sizeof(header.version), header.version);
         printf("Board Serial#:          %.*s\n",
                sizeof(header.serial), header.serial);
         puts("-----------------------------------------\n");
 /* SMARC BOOT_SEL*/
         if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {
                 puts("BOOT_SEL Detected: OFF OFF OFF, unsupported boot up device: SATA...\n");
                 hang();
         } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {
                 puts("BOOT_SEL Detected: OFF OFF ON, unsupported boot up device: NAND...\n");
                 hang();
         } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {
                 puts("BOOT_SEL Detected: OFF ON OFF, unsupported boot up device: Carrier eSPI...\n");
                 hang();
         } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {
                 puts("BOOT_SEL Detected: ON OFF OFF, Load zImage from Carrier SD Card...\n");
                 setenv_ulong("mmcdev", 0);
                 setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");
         } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {
                 puts("BOOT_SEL Detected: OFF ON ON, Load zImage from Module eMMC Flash...\n");
                 setenv_ulong("mmcdev", 1);
                 setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");
         } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 0)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {
                 puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n");
                 setenv("bootcmd", "run netboot;");
         } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 0)) {
                 puts("BOOT_SEL Detected: OFF ON OFF, unsupported boot up device: Carrier SPI...\n");
                 hang();
         } else if ((gpio_get_value(IMX_GPIO_NR(5, 15)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 16)) == 1)&&(gpio_get_value(IMX_GPIO_NR(5, 17)) == 1)) {
                 puts("BOOT_SEL Detected: ON ON ON, MOdule SPI Boot up is Default, Load zImage from Module eMMC...\n");
                 setenv_ulong("mmcdev", 1);
                 setenv("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadzimage; run loadfdt; run mmcboot;");
         } else {
                 puts("unsupported boot devices\n");
                 hang();
         }
         return 0;
 }
 #ifdef CONFIG_FSL_FASTBOOT
 void board_fastboot_setup(void)
 {
 	switch (get_boot_device()) {
 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
 	case SD1_BOOT:
 	case MMC1_BOOT:
 		if (!getenv("fastboot_dev"))
 			setenv("fastboot_dev", "mmc0");
 		if (!getenv("bootcmd"))
 			setenv("bootcmd", "boota mmc0");
 		break;
 	case SD3_BOOT:
 	case MMC3_BOOT:
 		if (!getenv("fastboot_dev"))
 			setenv("fastboot_dev", "mmc1");
 		if (!getenv("bootcmd"))
 			setenv("bootcmd", "boota mmc1");
 		break;
 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
 	default:
 		printf("unsupported boot devices\n");
 		break;
 	}
 }
 #ifdef CONFIG_ANDROID_RECOVERY
 /* Use LID# for recovery key */
 #define GPIO_VOL_DN_KEY IMX_GPIO_NR(5, 10)
 iomux_v3_cfg_t const recovery_key_pads[] = {
 	(MX7D_PAD_SD2_WP__GPIO5_IO10 | MUX_PAD_CTRL(BUTTON_PAD_CTRL)),
 };
 int check_recovery_cmd_file(void)
 {
 	int button_pressed = 0;
 	int recovery_mode = 0;
 	recovery_mode = recovery_check_and_clean_flag();
 	/* Check Recovery Combo Button press or not. */
 	imx_iomux_v3_setup_multiple_pads(recovery_key_pads,
 		ARRAY_SIZE(recovery_key_pads));
 	gpio_direction_input(GPIO_VOL_DN_KEY);
 	if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */
 		button_pressed = 1;
 		printf("Recovery key pressed\n");
 	}
 	return recovery_mode || button_pressed;
 }
 void board_recovery_setup(void)
 {
 	int bootdev = get_boot_device();
 	switch (bootdev) {
 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
 	case SD1_BOOT:
 	case MMC1_BOOT:
 		if (!getenv("bootcmd_android_recovery"))
 			setenv("bootcmd_android_recovery", "boota mmc0 recovery");
 		break;
 	case SD3_BOOT:
 	case MMC3_BOOT:
 		if (!getenv("bootcmd_android_recovery"))
 			setenv("bootcmd_android_recovery", "boota mmc1 recovery");
 		break;
 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
 	default:
 		printf("Unsupported bootup device for recovery: dev: %d\n",
 			bootdev);
 		return;
 	}
 	printf("setup env for recovery..\n");
 	setenv("bootcmd", "run bootcmd_android_recovery");
 }
 #endif /*CONFIG_ANDROID_RECOVERY*/
 #endif /*CONFIG_FSL_FASTBOOT*/