Eric Lee / smarc-uboot

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Commit 6ad39425bbc8b6dcade3ecd4883f624e277588c1

Authored by Peng Fan
1 parent 9af06ef99b
Exists in smarc-imx-l5.0.0_1.0.0-ga

MLK-9933 imx:mx6sxsabresd correct info for PFUZE 

We use PFUZE200 for SX SDB RevB board and PFUZE100 for SX SDB RevA board.
Show correct msg according DeviceID, since PFUZE200 and PFUZE100 have different
DeviceID. PFUZE200's id is 1, while PFUZE100's is 0.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

Showing 1 changed file with 6 additions and 1 deletions Inline Diff

board/freescale/mx6sxsabresd/mx6sxsabresd.c
Diff comments   View file @ 6ad3942
1 /* 1 /*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc. 2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <asm/arch/clock.h> 7 #include <asm/arch/clock.h>
8 #include <asm/arch/iomux.h> 8 #include <asm/arch/iomux.h>
9 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/mx6-pins.h> 10 #include <asm/arch/mx6-pins.h>
11 #include <asm/arch/sys_proto.h> 11 #include <asm/arch/sys_proto.h>
12 #include <asm/gpio.h> 12 #include <asm/gpio.h>
13 #include <asm/imx-common/iomux-v3.h> 13 #include <asm/imx-common/iomux-v3.h>
14 #include <asm/imx-common/boot_mode.h> 14 #include <asm/imx-common/boot_mode.h>
15 #include <asm/io.h> 15 #include <asm/io.h>
16 #include <linux/sizes.h> 16 #include <linux/sizes.h>
17 #include <common.h> 17 #include <common.h>
18 #include <fsl_esdhc.h> 18 #include <fsl_esdhc.h>
19 #include <mmc.h> 19 #include <mmc.h>
20 #include <miiphy.h> 20 #include <miiphy.h>
21 #include <netdev.h> 21 #include <netdev.h>
22 #ifdef CONFIG_SYS_I2C_MXC 22 #ifdef CONFIG_SYS_I2C_MXC
23 #include <i2c.h> 23 #include <i2c.h>
24 #include <asm/imx-common/mxc_i2c.h> 24 #include <asm/imx-common/mxc_i2c.h>
25 #endif 25 #endif
26 #ifdef CONFIG_MXC_RDC 26 #ifdef CONFIG_MXC_RDC
27 #include <asm/imx-common/rdc-sema.h> 27 #include <asm/imx-common/rdc-sema.h>
28 #include <asm/arch/imx-rdc.h> 28 #include <asm/arch/imx-rdc.h>
29 #endif 29 #endif
30 30
31 #ifdef CONFIG_VIDEO_MXS 31 #ifdef CONFIG_VIDEO_MXS
32 #include <linux/fb.h> 32 #include <linux/fb.h>
33 #include <mxsfb.h> 33 #include <mxsfb.h>
34 #endif 34 #endif
35 35
36 #ifdef CONFIG_FASTBOOT 36 #ifdef CONFIG_FASTBOOT
37 #include <fastboot.h> 37 #include <fastboot.h>
38 #ifdef CONFIG_ANDROID_RECOVERY 38 #ifdef CONFIG_ANDROID_RECOVERY
39 #include <recovery.h> 39 #include <recovery.h>
40 #endif 40 #endif
41 #endif /*CONFIG_FASTBOOT*/ 41 #endif /*CONFIG_FASTBOOT*/
42 42
43 43
44 DECLARE_GLOBAL_DATA_PTR; 44 DECLARE_GLOBAL_DATA_PTR;
45 45
46 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 46 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 47 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
48 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 48 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
49 49
50 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 50 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
51 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 51 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
52 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 52 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
53 53
54 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 54 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
55 PAD_CTL_SPEED_HIGH | \ 55 PAD_CTL_SPEED_HIGH | \
56 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) 56 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
57 57
58 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ 58 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
59 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) 59 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
60 60
61 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 61 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
62 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) 62 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
63 63
64 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 64 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
65 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 65 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
66 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 66 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
67 PAD_CTL_ODE) 67 PAD_CTL_ODE)
68 68
69 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 69 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
70 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) 70 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
71 71
72 #define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 72 #define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
73 PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_40ohm) 73 PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_40ohm)
74 74
75 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ 75 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
76 PAD_CTL_DSE_40ohm) 76 PAD_CTL_DSE_40ohm)
77 77
78 #ifdef CONFIG_SYS_I2C_MXC 78 #ifdef CONFIG_SYS_I2C_MXC
79 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 79 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
80 /* I2C1 for PMIC */ 80 /* I2C1 for PMIC */
81 struct i2c_pads_info i2c_pad_info1 = { 81 struct i2c_pads_info i2c_pad_info1 = {
82 .scl = { 82 .scl = {
83 .i2c_mode = MX6SX_PAD_GPIO1_IO00__I2C1_SCL | PC, 83 .i2c_mode = MX6SX_PAD_GPIO1_IO00__I2C1_SCL | PC,
84 .gpio_mode = MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, 84 .gpio_mode = MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
85 .gp = IMX_GPIO_NR(1, 0), 85 .gp = IMX_GPIO_NR(1, 0),
86 }, 86 },
87 .sda = { 87 .sda = {
88 .i2c_mode = MX6SX_PAD_GPIO1_IO01__I2C1_SDA | PC, 88 .i2c_mode = MX6SX_PAD_GPIO1_IO01__I2C1_SDA | PC,
89 .gpio_mode = MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, 89 .gpio_mode = MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
90 .gp = IMX_GPIO_NR(1, 1), 90 .gp = IMX_GPIO_NR(1, 1),
91 }, 91 },
92 }; 92 };
93 93
94 /* I2C2 */ 94 /* I2C2 */
95 struct i2c_pads_info i2c_pad_info2 = { 95 struct i2c_pads_info i2c_pad_info2 = {
96 .scl = { 96 .scl = {
97 .i2c_mode = MX6SX_PAD_GPIO1_IO02__I2C2_SCL | PC, 97 .i2c_mode = MX6SX_PAD_GPIO1_IO02__I2C2_SCL | PC,
98 .gpio_mode = MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 | PC, 98 .gpio_mode = MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
99 .gp = IMX_GPIO_NR(1, 2), 99 .gp = IMX_GPIO_NR(1, 2),
100 }, 100 },
101 .sda = { 101 .sda = {
102 .i2c_mode = MX6SX_PAD_GPIO1_IO03__I2C2_SDA | PC, 102 .i2c_mode = MX6SX_PAD_GPIO1_IO03__I2C2_SDA | PC,
103 .gpio_mode = MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 | PC, 103 .gpio_mode = MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
104 .gp = IMX_GPIO_NR(1, 3), 104 .gp = IMX_GPIO_NR(1, 3),
105 }, 105 },
106 }; 106 };
107 #endif 107 #endif
108 108
109 int dram_init(void) 109 int dram_init(void)
110 { 110 {
111 gd->ram_size = PHYS_SDRAM_SIZE; 111 gd->ram_size = PHYS_SDRAM_SIZE;
112 112
113 return 0; 113 return 0;
114 } 114 }
115 115
116 static iomux_v3_cfg_t const uart1_pads[] = { 116 static iomux_v3_cfg_t const uart1_pads[] = {
117 MX6SX_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 117 MX6SX_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
118 MX6SX_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 118 MX6SX_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
119 }; 119 };
120 120
121 static iomux_v3_cfg_t const usdhc2_pads[] = { 121 static iomux_v3_cfg_t const usdhc2_pads[] = {
122 MX6SX_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 122 MX6SX_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX6SX_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 123 MX6SX_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 124 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 125 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 126 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 127 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 }; 128 };
129 129
130 static iomux_v3_cfg_t const usdhc3_pads[] = { 130 static iomux_v3_cfg_t const usdhc3_pads[] = {
131 MX6SX_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 131 MX6SX_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6SX_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 132 MX6SX_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 133 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 134 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 135 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 136 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 137 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 138 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 139 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 140 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 141
142 /* CD pin */ 142 /* CD pin */
143 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), 143 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
144 144
145 /* RST_B, used for power reset cycle */ 145 /* RST_B, used for power reset cycle */
146 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL), 146 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
147 }; 147 };
148 148
149 static iomux_v3_cfg_t const usdhc4_pads[] = { 149 static iomux_v3_cfg_t const usdhc4_pads[] = {
150 MX6SX_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 150 MX6SX_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151 MX6SX_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 151 MX6SX_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 152 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 153 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 154 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
155 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 155 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
156 156
157 /* CD pin */ 157 /* CD pin */
158 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL), 158 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
159 }; 159 };
160 160
161 static iomux_v3_cfg_t const usdhc4_emmc_pads[] = { 161 static iomux_v3_cfg_t const usdhc4_emmc_pads[] = {
162 MX6SX_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 162 MX6SX_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
163 MX6SX_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 163 MX6SX_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
164 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 164 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
165 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 165 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
166 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 166 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
167 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 167 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
168 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 168 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
169 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 169 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
170 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 170 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
171 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 171 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
172 MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL), 172 MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL),
173 }; 173 };
174 174
175 175
176 static iomux_v3_cfg_t const peri_3v3_pads[] = { 176 static iomux_v3_cfg_t const peri_3v3_pads[] = {
177 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), 177 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
178 }; 178 };
179 179
180 static iomux_v3_cfg_t const wdog_b_pad = { 180 static iomux_v3_cfg_t const wdog_b_pad = {
181 MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), 181 MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
182 }; 182 };
183 183
184 #ifdef CONFIG_FEC_MXC 184 #ifdef CONFIG_FEC_MXC
185 static iomux_v3_cfg_t const fec1_pads[] = { 185 static iomux_v3_cfg_t const fec1_pads[] = {
186 MX6SX_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 186 MX6SX_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
187 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 187 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
188 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 188 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
189 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 189 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
190 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 190 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
191 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 191 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
192 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 192 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
193 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 193 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
194 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 194 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
195 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 195 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
196 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 196 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
197 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 197 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
198 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 198 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
199 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 199 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
200 }; 200 };
201 201
202 static iomux_v3_cfg_t const fec2_pads[] = { 202 static iomux_v3_cfg_t const fec2_pads[] = {
203 MX6SX_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 203 MX6SX_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
204 MX6SX_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 204 MX6SX_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
205 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 205 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
206 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 206 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
207 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 207 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
208 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 208 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
209 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 209 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
210 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 210 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
211 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 211 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
212 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 212 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
213 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 213 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
214 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 214 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
215 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 215 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
216 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 216 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
217 }; 217 };
218 218
219 static iomux_v3_cfg_t const phy_control_pads[] = { 219 static iomux_v3_cfg_t const phy_control_pads[] = {
220 /* Phy 25M Clock */ 220 /* Phy 25M Clock */
221 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 221 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
222 222
223 /* ENET PHY Power */ 223 /* ENET PHY Power */
224 MX6SX_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL), 224 MX6SX_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
225 225
226 /* AR8031 PHY Reset. */ 226 /* AR8031 PHY Reset. */
227 MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL), 227 MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
228 }; 228 };
229 229
230 static void setup_iomux_fec(int fec_id) 230 static void setup_iomux_fec(int fec_id)
231 { 231 {
232 if (0 == fec_id) 232 if (0 == fec_id)
233 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 233 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
234 else 234 else
235 imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); 235 imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
236 } 236 }
237 #endif 237 #endif
238 238
239 static void setup_iomux_uart(void) 239 static void setup_iomux_uart(void)
240 { 240 {
241 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 241 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
242 } 242 }
243 243
244 #ifdef CONFIG_QSPI 244 #ifdef CONFIG_QSPI
245 245
246 #define QSPI_PAD_CTRL1 \ 246 #define QSPI_PAD_CTRL1 \
247 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ 247 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
248 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm) 248 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
249 249
250 static iomux_v3_cfg_t const quadspi_pads[] = { 250 static iomux_v3_cfg_t const quadspi_pads[] = {
251 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 251 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
252 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 252 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
253 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 253 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
254 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 254 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
255 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 255 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
256 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 256 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
257 MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 257 MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
258 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 258 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
259 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 259 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
260 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 260 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
261 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 261 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
262 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 262 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
263 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 263 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
264 MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 264 MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
265 }; 265 };
266 266
267 int board_qspi_init(void) 267 int board_qspi_init(void)
268 { 268 {
269 /* Set the iomux */ 269 /* Set the iomux */
270 imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); 270 imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
271 271
272 /* Set the clock */ 272 /* Set the clock */
273 enable_qspi_clk(1); 273 enable_qspi_clk(1);
274 274
275 return 0; 275 return 0;
276 } 276 }
277 #endif 277 #endif
278 278
279 #ifdef CONFIG_FSL_ESDHC 279 #ifdef CONFIG_FSL_ESDHC
280 static struct fsl_esdhc_cfg usdhc_cfg[3] = { 280 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
281 {USDHC2_BASE_ADDR, 0, 4}, 281 {USDHC2_BASE_ADDR, 0, 4},
282 {USDHC3_BASE_ADDR}, 282 {USDHC3_BASE_ADDR},
283 #ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK 283 #ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
284 {USDHC4_BASE_ADDR, 0, 8}, 284 {USDHC4_BASE_ADDR, 0, 8},
285 #else 285 #else
286 {USDHC4_BASE_ADDR, 0, 4}, 286 {USDHC4_BASE_ADDR, 0, 4},
287 #endif 287 #endif
288 }; 288 };
289 289
290 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) 290 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
291 #define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11) 291 #define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
292 #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21) 292 #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
293 293
294 int mmc_get_env_devno(void) 294 int mmc_get_env_devno(void)
295 { 295 {
296 u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); 296 u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
297 int dev_no; 297 int dev_no;
298 u32 bootsel; 298 u32 bootsel;
299 299
300 bootsel = (soc_sbmr & 0x000000FF) >> 6 ; 300 bootsel = (soc_sbmr & 0x000000FF) >> 6 ;
301 301
302 /* If not boot from sd/mmc, use default value */ 302 /* If not boot from sd/mmc, use default value */
303 if (bootsel != 1) 303 if (bootsel != 1)
304 return CONFIG_SYS_MMC_ENV_DEV; 304 return CONFIG_SYS_MMC_ENV_DEV;
305 305
306 /* BOOT_CFG2[3] and BOOT_CFG2[4] */ 306 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
307 dev_no = (soc_sbmr & 0x00001800) >> 11; 307 dev_no = (soc_sbmr & 0x00001800) >> 11;
308 308
309 /* need ubstract 1 to map to the mmc device id 309 /* need ubstract 1 to map to the mmc device id
310 * see the comments in board_mmc_init function 310 * see the comments in board_mmc_init function
311 */ 311 */
312 312
313 dev_no--; 313 dev_no--;
314 314
315 return dev_no; 315 return dev_no;
316 } 316 }
317 317
318 int mmc_map_to_kernel_blk(int dev_no) 318 int mmc_map_to_kernel_blk(int dev_no)
319 { 319 {
320 return dev_no + 1; 320 return dev_no + 1;
321 } 321 }
322 322
323 int board_mmc_getcd(struct mmc *mmc) 323 int board_mmc_getcd(struct mmc *mmc)
324 { 324 {
325 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 325 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
326 int ret = 0; 326 int ret = 0;
327 327
328 switch (cfg->esdhc_base) { 328 switch (cfg->esdhc_base) {
329 case USDHC2_BASE_ADDR: 329 case USDHC2_BASE_ADDR:
330 ret = 1; /* Assume uSDHC2 is always present */ 330 ret = 1; /* Assume uSDHC2 is always present */
331 break; 331 break;
332 case USDHC3_BASE_ADDR: 332 case USDHC3_BASE_ADDR:
333 ret = !gpio_get_value(USDHC3_CD_GPIO); 333 ret = !gpio_get_value(USDHC3_CD_GPIO);
334 break; 334 break;
335 case USDHC4_BASE_ADDR: 335 case USDHC4_BASE_ADDR:
336 #ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK 336 #ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
337 ret = 1; 337 ret = 1;
338 #else 338 #else
339 ret = !gpio_get_value(USDHC4_CD_GPIO); 339 ret = !gpio_get_value(USDHC4_CD_GPIO);
340 #endif 340 #endif
341 break; 341 break;
342 } 342 }
343 343
344 return ret; 344 return ret;
345 345
346 } 346 }
347 347
348 int board_mmc_init(bd_t *bis) 348 int board_mmc_init(bd_t *bis)
349 { 349 {
350 int i; 350 int i;
351 351
352 /* 352 /*
353 * According to the board_mmc_init() the following map is done: 353 * According to the board_mmc_init() the following map is done:
354 * (U-boot device node) (Physical Port) 354 * (U-boot device node) (Physical Port)
355 * mmc0 USDHC2 355 * mmc0 USDHC2
356 * mmc1 USDHC3 356 * mmc1 USDHC3
357 * mmc2 USDHC4 357 * mmc2 USDHC4
358 */ 358 */
359 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 359 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
360 switch (i) { 360 switch (i) {
361 case 0: 361 case 0:
362 imx_iomux_v3_setup_multiple_pads( 362 imx_iomux_v3_setup_multiple_pads(
363 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 363 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
364 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 364 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
365 break; 365 break;
366 case 1: 366 case 1:
367 imx_iomux_v3_setup_multiple_pads( 367 imx_iomux_v3_setup_multiple_pads(
368 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 368 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
369 gpio_direction_input(USDHC3_CD_GPIO); 369 gpio_direction_input(USDHC3_CD_GPIO);
370 gpio_direction_output(USDHC3_PWR_GPIO, 1); 370 gpio_direction_output(USDHC3_PWR_GPIO, 1);
371 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 371 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
372 break; 372 break;
373 case 2: 373 case 2:
374 #ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK 374 #ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
375 imx_iomux_v3_setup_multiple_pads( 375 imx_iomux_v3_setup_multiple_pads(
376 usdhc4_emmc_pads, ARRAY_SIZE(usdhc4_emmc_pads)); 376 usdhc4_emmc_pads, ARRAY_SIZE(usdhc4_emmc_pads));
377 #else 377 #else
378 imx_iomux_v3_setup_multiple_pads( 378 imx_iomux_v3_setup_multiple_pads(
379 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 379 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
380 gpio_direction_input(USDHC4_CD_GPIO); 380 gpio_direction_input(USDHC4_CD_GPIO);
381 #endif 381 #endif
382 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 382 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
383 break; 383 break;
384 default: 384 default:
385 printf("Warning: you configured more USDHC controllers" 385 printf("Warning: you configured more USDHC controllers"
386 "(%d) than supported by the board\n", i + 1); 386 "(%d) than supported by the board\n", i + 1);
387 return 0; 387 return 0;
388 } 388 }
389 389
390 if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) 390 if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
391 printf("Warning: failed to initialize mmc dev %d\n", i); 391 printf("Warning: failed to initialize mmc dev %d\n", i);
392 } 392 }
393 393
394 return 0; 394 return 0;
395 } 395 }
396 396
397 int check_mmc_autodetect(void) 397 int check_mmc_autodetect(void)
398 { 398 {
399 char *autodetect_str = getenv("mmcautodetect"); 399 char *autodetect_str = getenv("mmcautodetect");
400 400
401 if ((autodetect_str != NULL) && 401 if ((autodetect_str != NULL) &&
402 (strcmp(autodetect_str, "yes") == 0)) { 402 (strcmp(autodetect_str, "yes") == 0)) {
403 return 1; 403 return 1;
404 } 404 }
405 405
406 return 0; 406 return 0;
407 } 407 }
408 408
409 void board_late_mmc_init(void) 409 void board_late_mmc_init(void)
410 { 410 {
411 char cmd[32]; 411 char cmd[32];
412 char mmcblk[32]; 412 char mmcblk[32];
413 u32 dev_no = mmc_get_env_devno(); 413 u32 dev_no = mmc_get_env_devno();
414 414
415 if (!check_mmc_autodetect()) 415 if (!check_mmc_autodetect())
416 return; 416 return;
417 417
418 setenv_ulong("mmcdev", dev_no); 418 setenv_ulong("mmcdev", dev_no);
419 419
420 /* Set mmcblk env */ 420 /* Set mmcblk env */
421 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", 421 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
422 mmc_map_to_kernel_blk(dev_no)); 422 mmc_map_to_kernel_blk(dev_no));
423 setenv("mmcroot", mmcblk); 423 setenv("mmcroot", mmcblk);
424 424
425 sprintf(cmd, "mmc dev %d", dev_no); 425 sprintf(cmd, "mmc dev %d", dev_no);
426 run_command(cmd, 0); 426 run_command(cmd, 0);
427 } 427 }
428 428
429 #endif 429 #endif
430 430
431 #ifdef CONFIG_VIDEO_MXS 431 #ifdef CONFIG_VIDEO_MXS
432 static iomux_v3_cfg_t const lvds_ctrl_pads[] = { 432 static iomux_v3_cfg_t const lvds_ctrl_pads[] = {
433 /* CABC enable */ 433 /* CABC enable */
434 MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL), 434 MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
435 435
436 /* Use GPIO for Brightness adjustment, duty cycle = period */ 436 /* Use GPIO for Brightness adjustment, duty cycle = period */
437 MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 | MUX_PAD_CTRL(NO_PAD_CTRL), 437 MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 | MUX_PAD_CTRL(NO_PAD_CTRL),
438 }; 438 };
439 439
440 static iomux_v3_cfg_t const lcd_pads[] = { 440 static iomux_v3_cfg_t const lcd_pads[] = {
441 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 441 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
442 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 442 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
443 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 443 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
444 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 444 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
445 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL), 445 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
446 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL), 446 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
447 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL), 447 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
448 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL), 448 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
449 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 449 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
450 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL), 450 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
451 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL), 451 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
452 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL), 452 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
453 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL), 453 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
454 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL), 454 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
455 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 455 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
456 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 456 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
457 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 457 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
458 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 458 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
459 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 459 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
460 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 460 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
461 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 461 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
462 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 462 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
463 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL), 463 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
464 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL), 464 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
465 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL), 465 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
466 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL), 466 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
467 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL), 467 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
468 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL), 468 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
469 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL), 469 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
470 470
471 /* Use GPIO for Brightness adjustment, duty cycle = period */ 471 /* Use GPIO for Brightness adjustment, duty cycle = period */
472 MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL), 472 MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
473 }; 473 };
474 474
475 475
476 struct lcd_panel_info_t { 476 struct lcd_panel_info_t {
477 unsigned int lcdif_base_addr; 477 unsigned int lcdif_base_addr;
478 int depth; 478 int depth;
479 void (*enable)(struct lcd_panel_info_t const *dev); 479 void (*enable)(struct lcd_panel_info_t const *dev);
480 struct fb_videomode mode; 480 struct fb_videomode mode;
481 }; 481 };
482 482
483 void do_enable_lvds(struct lcd_panel_info_t const *dev) 483 void do_enable_lvds(struct lcd_panel_info_t const *dev)
484 { 484 {
485 enable_lcdif_clock(dev->lcdif_base_addr); 485 enable_lcdif_clock(dev->lcdif_base_addr);
486 enable_lvds(dev->lcdif_base_addr); 486 enable_lvds(dev->lcdif_base_addr);
487 487
488 imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads, 488 imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads,
489 ARRAY_SIZE(lvds_ctrl_pads)); 489 ARRAY_SIZE(lvds_ctrl_pads));
490 490
491 /* Enable CABC */ 491 /* Enable CABC */
492 gpio_direction_output(IMX_GPIO_NR(4, 18) , 1); 492 gpio_direction_output(IMX_GPIO_NR(4, 18) , 1);
493 493
494 /* Set Brightness to high */ 494 /* Set Brightness to high */
495 gpio_direction_output(IMX_GPIO_NR(6, 3) , 1); 495 gpio_direction_output(IMX_GPIO_NR(6, 3) , 1);
496 } 496 }
497 497
498 void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev) 498 void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev)
499 { 499 {
500 enable_lcdif_clock(dev->lcdif_base_addr); 500 enable_lcdif_clock(dev->lcdif_base_addr);
501 501
502 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 502 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
503 503
504 /* Power up the LCD */ 504 /* Power up the LCD */
505 gpio_direction_output(IMX_GPIO_NR(3, 27) , 1); 505 gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
506 506
507 /* Set Brightness to high */ 507 /* Set Brightness to high */
508 gpio_direction_output(IMX_GPIO_NR(6, 4) , 1); 508 gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
509 } 509 }
510 510
511 static struct lcd_panel_info_t const displays[] = {{ 511 static struct lcd_panel_info_t const displays[] = {{
512 .lcdif_base_addr = LCDIF2_BASE_ADDR, 512 .lcdif_base_addr = LCDIF2_BASE_ADDR,
513 .depth = 18, 513 .depth = 18,
514 .enable = do_enable_lvds, 514 .enable = do_enable_lvds,
515 .mode = { 515 .mode = {
516 .name = "Hannstar-XGA", 516 .name = "Hannstar-XGA",
517 .xres = 1024, 517 .xres = 1024,
518 .yres = 768, 518 .yres = 768,
519 .pixclock = 15385, 519 .pixclock = 15385,
520 .left_margin = 220, 520 .left_margin = 220,
521 .right_margin = 40, 521 .right_margin = 40,
522 .upper_margin = 21, 522 .upper_margin = 21,
523 .lower_margin = 7, 523 .lower_margin = 7,
524 .hsync_len = 60, 524 .hsync_len = 60,
525 .vsync_len = 10, 525 .vsync_len = 10,
526 .sync = 0, 526 .sync = 0,
527 .vmode = FB_VMODE_NONINTERLACED 527 .vmode = FB_VMODE_NONINTERLACED
528 } }, { 528 } }, {
529 .lcdif_base_addr = LCDIF1_BASE_ADDR, 529 .lcdif_base_addr = LCDIF1_BASE_ADDR,
530 .depth = 24, 530 .depth = 24,
531 .enable = do_enable_parallel_lcd, 531 .enable = do_enable_parallel_lcd,
532 .mode = { 532 .mode = {
533 .name = "MCIMX28LCD", 533 .name = "MCIMX28LCD",
534 .xres = 800, 534 .xres = 800,
535 .yres = 480, 535 .yres = 480,
536 .pixclock = 29850, 536 .pixclock = 29850,
537 .left_margin = 89, 537 .left_margin = 89,
538 .right_margin = 164, 538 .right_margin = 164,
539 .upper_margin = 23, 539 .upper_margin = 23,
540 .lower_margin = 10, 540 .lower_margin = 10,
541 .hsync_len = 10, 541 .hsync_len = 10,
542 .vsync_len = 10, 542 .vsync_len = 10,
543 .sync = 0, 543 .sync = 0,
544 .vmode = FB_VMODE_NONINTERLACED 544 .vmode = FB_VMODE_NONINTERLACED
545 } } }; 545 } } };
546 546
547 int board_video_skip(void) 547 int board_video_skip(void)
548 { 548 {
549 int i; 549 int i;
550 int ret; 550 int ret;
551 char const *panel = getenv("panel"); 551 char const *panel = getenv("panel");
552 if (!panel) { 552 if (!panel) {
553 panel = displays[0].mode.name; 553 panel = displays[0].mode.name;
554 printf("No panel detected: default to %s\n", panel); 554 printf("No panel detected: default to %s\n", panel);
555 i = 0; 555 i = 0;
556 } else { 556 } else {
557 for (i = 0; i < ARRAY_SIZE(displays); i++) { 557 for (i = 0; i < ARRAY_SIZE(displays); i++) {
558 if (!strcmp(panel, displays[i].mode.name)) 558 if (!strcmp(panel, displays[i].mode.name))
559 break; 559 break;
560 } 560 }
561 } 561 }
562 if (i < ARRAY_SIZE(displays)) { 562 if (i < ARRAY_SIZE(displays)) {
563 ret = mxs_lcd_panel_setup(displays[i].mode, displays[i].depth, 563 ret = mxs_lcd_panel_setup(displays[i].mode, displays[i].depth,
564 displays[i].lcdif_base_addr); 564 displays[i].lcdif_base_addr);
565 if (!ret) { 565 if (!ret) {
566 if (displays[i].enable) 566 if (displays[i].enable)
567 displays[i].enable(displays+i); 567 displays[i].enable(displays+i);
568 printf("Display: %s (%ux%u)\n", 568 printf("Display: %s (%ux%u)\n",
569 displays[i].mode.name, 569 displays[i].mode.name,
570 displays[i].mode.xres, 570 displays[i].mode.xres,
571 displays[i].mode.yres); 571 displays[i].mode.yres);
572 } else 572 } else
573 printf("LCD %s cannot be configured: %d\n", 573 printf("LCD %s cannot be configured: %d\n",
574 displays[i].mode.name, ret); 574 displays[i].mode.name, ret);
575 } else { 575 } else {
576 printf("unsupported panel %s\n", panel); 576 printf("unsupported panel %s\n", panel);
577 return -EINVAL; 577 return -EINVAL;
578 } 578 }
579 579
580 return 0; 580 return 0;
581 } 581 }
582 #endif 582 #endif
583 583
584 #ifdef CONFIG_FEC_MXC 584 #ifdef CONFIG_FEC_MXC
585 int board_eth_init(bd_t *bis) 585 int board_eth_init(bd_t *bis)
586 { 586 {
587 int ret; 587 int ret;
588 588
589 setup_iomux_fec(CONFIG_FEC_ENET_DEV); 589 setup_iomux_fec(CONFIG_FEC_ENET_DEV);
590 590
591 ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, 591 ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
592 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 592 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
593 if (ret) 593 if (ret)
594 printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); 594 printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
595 595
596 return 0; 596 return 0;
597 } 597 }
598 598
599 static int setup_fec(int fec_id) 599 static int setup_fec(int fec_id)
600 { 600 {
601 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 601 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
602 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; 602 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
603 int ret; 603 int ret;
604 604
605 if (0 == fec_id) 605 if (0 == fec_id)
606 /* Use 125M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ 606 /* Use 125M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
607 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); 607 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
608 else 608 else
609 /* Use 125M anatop loopback REF_CLK1 for ENET2, clear gpr1[14], gpr1[18]*/ 609 /* Use 125M anatop loopback REF_CLK1 for ENET2, clear gpr1[14], gpr1[18]*/
610 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); 610 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
611 611
612 imx_iomux_v3_setup_multiple_pads(phy_control_pads, 612 imx_iomux_v3_setup_multiple_pads(phy_control_pads,
613 ARRAY_SIZE(phy_control_pads)); 613 ARRAY_SIZE(phy_control_pads));
614 614
615 /* Enable the ENET power, active low */ 615 /* Enable the ENET power, active low */
616 gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); 616 gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
617 617
618 /* Reset AR8031 PHY */ 618 /* Reset AR8031 PHY */
619 gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); 619 gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
620 udelay(500); 620 udelay(500);
621 gpio_set_value(IMX_GPIO_NR(2, 7), 1); 621 gpio_set_value(IMX_GPIO_NR(2, 7), 1);
622 622
623 ret = enable_fec_anatop_clock(fec_id, ENET_125MHz); 623 ret = enable_fec_anatop_clock(fec_id, ENET_125MHz);
624 if (ret) 624 if (ret)
625 return ret; 625 return ret;
626 626
627 enable_enet_clock(); 627 enable_enet_clock();
628 628
629 return 0; 629 return 0;
630 } 630 }
631 631
632 int board_phy_config(struct phy_device *phydev) 632 int board_phy_config(struct phy_device *phydev)
633 { 633 {
634 /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on 634 /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
635 Phy control debug reg 0 */ 635 Phy control debug reg 0 */
636 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); 636 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
637 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); 637 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
638 638
639 /* rgmii tx clock delay enable */ 639 /* rgmii tx clock delay enable */
640 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); 640 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
641 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 641 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
642 642
643 if (phydev->drv->config) 643 if (phydev->drv->config)
644 phydev->drv->config(phydev); 644 phydev->drv->config(phydev);
645 645
646 return 0; 646 return 0;
647 } 647 }
648 #endif 648 #endif
649 649
650 #ifdef CONFIG_PFUZE100_PMIC_I2C 650 #ifdef CONFIG_PFUZE100_PMIC_I2C
651 #define PFUZE100_DEVICEID 0x0 651 #define PFUZE100_DEVICEID 0x0
652 #define PFUZE100_REVID 0x3 652 #define PFUZE100_REVID 0x3
653 #define PFUZE100_FABID 0x4 653 #define PFUZE100_FABID 0x4
654 654
655 #define PFUZE100_SW1ABVOL 0x20 655 #define PFUZE100_SW1ABVOL 0x20
656 #define PFUZE100_SW1ABSTBY 0x21 656 #define PFUZE100_SW1ABSTBY 0x21
657 #define PFUZE100_SW1ABCONF 0x24 657 #define PFUZE100_SW1ABCONF 0x24
658 #define PFUZE100_SW1CVOL 0x2e 658 #define PFUZE100_SW1CVOL 0x2e
659 #define PFUZE100_SW1CSTBY 0x2f 659 #define PFUZE100_SW1CSTBY 0x2f
660 #define PFUZE100_SW1CCONF 0x32 660 #define PFUZE100_SW1CCONF 0x32
661 #define PFUZE100_SW1ABC_SETP(x) ((x - 3000) / 250) 661 #define PFUZE100_SW1ABC_SETP(x) ((x - 3000) / 250)
662 #define PFUZE100_VGEN5CTL 0x70 662 #define PFUZE100_VGEN5CTL 0x70
663 663
664 /* set all switches APS in normal and PFM mode in standby */ 664 /* set all switches APS in normal and PFM mode in standby */
665 static int setup_pmic_mode(int chip) 665 static int setup_pmic_mode(int chip)
666 { 666 {
667 unsigned char offset, i, switch_num, value; 667 unsigned char offset, i, switch_num, value;
668 668
669 if (!chip) { 669 if (!chip) {
670 /* pfuze100 */ 670 /* pfuze100 */
671 switch_num = 6; 671 switch_num = 6;
672 offset = 0x31; 672 offset = 0x31;
673 } else { 673 } else {
674 /* pfuze200 */ 674 /* pfuze200 */
675 switch_num = 4; 675 switch_num = 4;
676 offset = 0x38; 676 offset = 0x38;
677 } 677 }
678 678
679 value = 0xc; 679 value = 0xc;
680 if (i2c_write(0x8, 0x23, 1, &value, 1)) { 680 if (i2c_write(0x8, 0x23, 1, &value, 1)) {
681 printf("Set SW1AB mode error!\n"); 681 printf("Set SW1AB mode error!\n");
682 return -1; 682 return -1;
683 } 683 }
684 684
685 for (i = 0; i < switch_num - 1; i++) { 685 for (i = 0; i < switch_num - 1; i++) {
686 if (i2c_write(0x8, offset + i * 7, 1, &value, 1)) { 686 if (i2c_write(0x8, offset + i * 7, 1, &value, 1)) {
687 printf("Set switch%x mode error!\n", offset); 687 printf("Set switch%x mode error!\n", offset);
688 return -1; 688 return -1;
689 } 689 }
690 } 690 }
691 691
692 return 0; 692 return 0;
693 } 693 }
694 694
695 static int setup_pmic_voltages(void) 695 static int setup_pmic_voltages(void)
696 { 696 {
697 unsigned char value, rev_id = 0; 697 unsigned char value, rev_id = 0;
698 698
699 i2c_set_bus_num(CONFIG_PMIC_I2C_BUS); 699 i2c_set_bus_num(CONFIG_PMIC_I2C_BUS);
700 700
701 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_PMIC_I2C_SLAVE); 701 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_PMIC_I2C_SLAVE);
702 if (!i2c_probe(CONFIG_PMIC_I2C_SLAVE)) { 702 if (!i2c_probe(CONFIG_PMIC_I2C_SLAVE)) {
703 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_DEVICEID, 1, &value, 1)) { 703 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_DEVICEID, 1, &value, 1)) {
704 printf("Read device ID error!\n"); 704 printf("Read device ID error!\n");
705 return -1; 705 return -1;
706 } 706 }
707 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_REVID, 1, &rev_id, 1)) { 707 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_REVID, 1, &rev_id, 1)) {
708 printf("Read Rev ID error!\n"); 708 printf("Read Rev ID error!\n");
709 return -1; 709 return -1;
710 } 710 }
711 printf("Found PFUZE100! deviceid 0x%x, revid 0x%x\n", value, rev_id); 711 /*
712 * PFUZE200: Die version 0001 = PF0200
713 * PFUZE100: Die version 0000 = PF0100
714 */
715 printf("Found %s! deviceid 0x%x, revid 0x%x\n", (value & 0xf) ?
716 "PFUZE200" : "PFUZE100", value & 0xf, rev_id);
712 717
713 if (setup_pmic_mode(value & 0xf)) { 718 if (setup_pmic_mode(value & 0xf)) {
714 printf("setup pmic mode error!\n"); 719 printf("setup pmic mode error!\n");
715 return -1; 720 return -1;
716 } 721 }
717 /* set SW1AB standby volatage 0.975V */ 722 /* set SW1AB standby volatage 0.975V */
718 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABSTBY, 1, &value, 1)) { 723 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABSTBY, 1, &value, 1)) {
719 printf("Read SW1ABSTBY error!\n"); 724 printf("Read SW1ABSTBY error!\n");
720 return -1; 725 return -1;
721 } 726 }
722 value &= ~0x3f; 727 value &= ~0x3f;
723 value |= PFUZE100_SW1ABC_SETP(9750); 728 value |= PFUZE100_SW1ABC_SETP(9750);
724 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABSTBY, 1, &value, 1)) { 729 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABSTBY, 1, &value, 1)) {
725 printf("Set SW1ABSTBY error!\n"); 730 printf("Set SW1ABSTBY error!\n");
726 return -1; 731 return -1;
727 } 732 }
728 733
729 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ 734 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
730 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABCONF, 1, &value, 1)) { 735 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABCONF, 1, &value, 1)) {
731 printf("Read SW1ABCONFIG error!\n"); 736 printf("Read SW1ABCONFIG error!\n");
732 return -1; 737 return -1;
733 } 738 }
734 value &= ~0xc0; 739 value &= ~0xc0;
735 value |= 0x40; 740 value |= 0x40;
736 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABCONF, 1, &value, 1)) { 741 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABCONF, 1, &value, 1)) {
737 printf("Set SW1ABCONFIG error!\n"); 742 printf("Set SW1ABCONFIG error!\n");
738 return -1; 743 return -1;
739 } 744 }
740 745
741 /* set SW1C standby volatage 0.975V */ 746 /* set SW1C standby volatage 0.975V */
742 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CSTBY, 1, &value, 1)) { 747 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CSTBY, 1, &value, 1)) {
743 printf("Read SW1CSTBY error!\n"); 748 printf("Read SW1CSTBY error!\n");
744 return -1; 749 return -1;
745 } 750 }
746 value &= ~0x3f; 751 value &= ~0x3f;
747 value |= PFUZE100_SW1ABC_SETP(9750); 752 value |= PFUZE100_SW1ABC_SETP(9750);
748 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CSTBY, 1, &value, 1)) { 753 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CSTBY, 1, &value, 1)) {
749 printf("Set SW1CSTBY error!\n"); 754 printf("Set SW1CSTBY error!\n");
750 return -1; 755 return -1;
751 } 756 }
752 757
753 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ 758 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
754 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CCONF, 1, &value, 1)) { 759 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CCONF, 1, &value, 1)) {
755 printf("Read SW1CCONFIG error!\n"); 760 printf("Read SW1CCONFIG error!\n");
756 return -1; 761 return -1;
757 } 762 }
758 value &= ~0xc0; 763 value &= ~0xc0;
759 value |= 0x40; 764 value |= 0x40;
760 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CCONF, 1, &value, 1)) { 765 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CCONF, 1, &value, 1)) {
761 printf("Set SW1CCONFIG error!\n"); 766 printf("Set SW1CCONFIG error!\n");
762 return -1; 767 return -1;
763 } 768 }
764 769
765 /* Enable power of VGEN5 3V3, needed for SD3 */ 770 /* Enable power of VGEN5 3V3, needed for SD3 */
766 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_VGEN5CTL, 1, &value, 1)) { 771 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_VGEN5CTL, 1, &value, 1)) {
767 printf("Read VGEN5CTL error!\n"); 772 printf("Read VGEN5CTL error!\n");
768 return -1; 773 return -1;
769 } 774 }
770 value &= ~0x1F; 775 value &= ~0x1F;
771 value |= 0x1F; 776 value |= 0x1F;
772 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_VGEN5CTL, 1, &value, 1)) { 777 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_VGEN5CTL, 1, &value, 1)) {
773 printf("Set VGEN5CTL error!\n"); 778 printf("Set VGEN5CTL error!\n");
774 return -1; 779 return -1;
775 } 780 }
776 } 781 }
777 782
778 return 0; 783 return 0;
779 } 784 }
780 785
781 #ifdef CONFIG_LDO_BYPASS_CHECK 786 #ifdef CONFIG_LDO_BYPASS_CHECK
782 void ldo_mode_set(int ldo_bypass) 787 void ldo_mode_set(int ldo_bypass)
783 { 788 {
784 unsigned char value; 789 unsigned char value;
785 int is_400M; 790 int is_400M;
786 u32 vddarm; 791 u32 vddarm;
787 /* switch to ldo_bypass mode */ 792 /* switch to ldo_bypass mode */
788 if (ldo_bypass) { 793 if (ldo_bypass) {
789 prep_anatop_bypass(); 794 prep_anatop_bypass();
790 /* decrease VDDARM to 1.275V */ 795 /* decrease VDDARM to 1.275V */
791 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) { 796 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) {
792 printf("Read SW1AB error!\n"); 797 printf("Read SW1AB error!\n");
793 return; 798 return;
794 } 799 }
795 value &= ~0x3f; 800 value &= ~0x3f;
796 value |= PFUZE100_SW1ABC_SETP(12750); 801 value |= PFUZE100_SW1ABC_SETP(12750);
797 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) { 802 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) {
798 printf("Set SW1AB error!\n"); 803 printf("Set SW1AB error!\n");
799 return; 804 return;
800 } 805 }
801 /* decrease VDDSOC to 1.3V */ 806 /* decrease VDDSOC to 1.3V */
802 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) { 807 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) {
803 printf("Read SW1C error!\n"); 808 printf("Read SW1C error!\n");
804 return; 809 return;
805 } 810 }
806 value &= ~0x3f; 811 value &= ~0x3f;
807 value |= PFUZE100_SW1ABC_SETP(13000); 812 value |= PFUZE100_SW1ABC_SETP(13000);
808 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) { 813 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) {
809 printf("Set SW1C error!\n"); 814 printf("Set SW1C error!\n");
810 return; 815 return;
811 } 816 }
812 817
813 is_400M = set_anatop_bypass(1); 818 is_400M = set_anatop_bypass(1);
814 if (is_400M) 819 if (is_400M)
815 vddarm = PFUZE100_SW1ABC_SETP(10750); 820 vddarm = PFUZE100_SW1ABC_SETP(10750);
816 else 821 else
817 vddarm = PFUZE100_SW1ABC_SETP(11750); 822 vddarm = PFUZE100_SW1ABC_SETP(11750);
818 823
819 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) { 824 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) {
820 printf("Read SW1AB error!\n"); 825 printf("Read SW1AB error!\n");
821 return; 826 return;
822 } 827 }
823 value &= ~0x3f; 828 value &= ~0x3f;
824 value |= vddarm; 829 value |= vddarm;
825 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) { 830 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABVOL, 1, &value, 1)) {
826 printf("Set SW1AB error!\n"); 831 printf("Set SW1AB error!\n");
827 return; 832 return;
828 } 833 }
829 834
830 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) { 835 if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) {
831 printf("Read SW1C error!\n"); 836 printf("Read SW1C error!\n");
832 return; 837 return;
833 } 838 }
834 value &= ~0x3f; 839 value &= ~0x3f;
835 value |= PFUZE100_SW1ABC_SETP(11750); 840 value |= PFUZE100_SW1ABC_SETP(11750);
836 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) { 841 if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CVOL, 1, &value, 1)) {
837 printf("Set SW1C error!\n"); 842 printf("Set SW1C error!\n");
838 return; 843 return;
839 } 844 }
840 845
841 finish_anatop_bypass(); 846 finish_anatop_bypass();
842 printf("switch to ldo_bypass mode!\n"); 847 printf("switch to ldo_bypass mode!\n");
843 } 848 }
844 849
845 } 850 }
846 #endif 851 #endif
847 #endif 852 #endif
848 853
849 #ifdef CONFIG_MXC_RDC 854 #ifdef CONFIG_MXC_RDC
850 static rdc_peri_cfg_t const shared_resources[] = { 855 static rdc_peri_cfg_t const shared_resources[] = {
851 (RDC_PER_GPIO1 | RDC_DOMAIN(0) | RDC_DOMAIN(1)), 856 (RDC_PER_GPIO1 | RDC_DOMAIN(0) | RDC_DOMAIN(1)),
852 }; 857 };
853 #endif 858 #endif
854 859
855 int board_early_init_f(void) 860 int board_early_init_f(void)
856 { 861 {
857 #ifdef CONFIG_MXC_RDC 862 #ifdef CONFIG_MXC_RDC
858 imx_rdc_setup_peripherals(shared_resources, ARRAY_SIZE(shared_resources)); 863 imx_rdc_setup_peripherals(shared_resources, ARRAY_SIZE(shared_resources));
859 #endif 864 #endif
860 865
861 #ifdef CONFIG_SYS_AUXCORE_FASTUP 866 #ifdef CONFIG_SYS_AUXCORE_FASTUP
862 arch_auxiliary_core_up(0, CONFIG_SYS_AUXCORE_BOOTDATA); 867 arch_auxiliary_core_up(0, CONFIG_SYS_AUXCORE_BOOTDATA);
863 #endif 868 #endif
864 869
865 setup_iomux_uart(); 870 setup_iomux_uart();
866 return 0; 871 return 0;
867 } 872 }
868 873
869 int board_init(void) 874 int board_init(void)
870 { 875 {
871 /* Address of boot parameters */ 876 /* Address of boot parameters */
872 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 877 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
873 878
874 /* 879 /*
875 * Because kernel set WDOG_B mux before pad with the commone pinctrl 880 * Because kernel set WDOG_B mux before pad with the commone pinctrl
876 * framwork now and wdog reset will be triggered once set WDOG_B mux 881 * framwork now and wdog reset will be triggered once set WDOG_B mux
877 * with default pad setting, we set pad setting here to workaround this. 882 * with default pad setting, we set pad setting here to workaround this.
878 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set 883 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
879 * as GPIO mux firstly here to workaround it. 884 * as GPIO mux firstly here to workaround it.
880 */ 885 */
881 imx_iomux_v3_setup_pad(wdog_b_pad); 886 imx_iomux_v3_setup_pad(wdog_b_pad);
882 887
883 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ 888 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
884 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, ARRAY_SIZE(peri_3v3_pads)); 889 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, ARRAY_SIZE(peri_3v3_pads));
885 890
886 /* Active high for ncp692 */ 891 /* Active high for ncp692 */
887 gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); 892 gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
888 893
889 #ifdef CONFIG_SYS_I2C_MXC 894 #ifdef CONFIG_SYS_I2C_MXC
890 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 895 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
891 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 896 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
892 #endif 897 #endif
893 898
894 #ifdef CONFIG_FEC_MXC 899 #ifdef CONFIG_FEC_MXC
895 setup_fec(CONFIG_FEC_ENET_DEV); 900 setup_fec(CONFIG_FEC_ENET_DEV);
896 #endif 901 #endif
897 902
898 #ifdef CONFIG_QSPI 903 #ifdef CONFIG_QSPI
899 board_qspi_init(); 904 board_qspi_init();
900 #endif 905 #endif
901 906
902 return 0; 907 return 0;
903 } 908 }
904 909
905 #ifdef CONFIG_CMD_BMODE 910 #ifdef CONFIG_CMD_BMODE
906 static const struct boot_mode board_boot_modes[] = { 911 static const struct boot_mode board_boot_modes[] = {
907 /* 4 bit bus width */ 912 /* 4 bit bus width */
908 {"sd3", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)}, 913 {"sd3", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
909 {"sd4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, 914 {"sd4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
910 {"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)}, 915 {"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)},
911 {NULL, 0}, 916 {NULL, 0},
912 }; 917 };
913 #endif 918 #endif
914 919
915 int board_late_init(void) 920 int board_late_init(void)
916 { 921 {
917 #ifdef CONFIG_CMD_BMODE 922 #ifdef CONFIG_CMD_BMODE
918 add_board_boot_modes(board_boot_modes); 923 add_board_boot_modes(board_boot_modes);
919 #endif 924 #endif
920 925
921 #ifdef CONFIG_PFUZE100_PMIC_I2C 926 #ifdef CONFIG_PFUZE100_PMIC_I2C
922 int ret = 0; 927 int ret = 0;
923 928
924 ret = setup_pmic_voltages(); 929 ret = setup_pmic_voltages();
925 if (ret) 930 if (ret)
926 return -1; 931 return -1;
927 #endif 932 #endif
928 933
929 #ifdef CONFIG_ENV_IS_IN_MMC 934 #ifdef CONFIG_ENV_IS_IN_MMC
930 board_late_mmc_init(); 935 board_late_mmc_init();
931 #endif 936 #endif
932 937
933 return 0; 938 return 0;
934 } 939 }
935 940
936 u32 get_board_rev(void) 941 u32 get_board_rev(void)
937 { 942 {
938 return get_cpu_rev(); 943 return get_cpu_rev();
939 } 944 }
940 945
941 int checkboard(void) 946 int checkboard(void)
942 { 947 {
943 puts("Board: MX6SX SABRE SDB\n"); 948 puts("Board: MX6SX SABRE SDB\n");
944 949
945 return 0; 950 return 0;
946 } 951 }
947 952
948 #ifdef CONFIG_USB_EHCI_MX6 953 #ifdef CONFIG_USB_EHCI_MX6
949 iomux_v3_cfg_t const usb_otg1_pads[] = { 954 iomux_v3_cfg_t const usb_otg1_pads[] = {
950 MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 955 MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
951 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL) 956 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL)
952 }; 957 };
953 958
954 iomux_v3_cfg_t const usb_otg2_pads[] = { 959 iomux_v3_cfg_t const usb_otg2_pads[] = {
955 MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 960 MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
956 }; 961 };
957 962
958 int board_ehci_hcd_init(int port) 963 int board_ehci_hcd_init(int port)
959 { 964 {
960 switch (port) { 965 switch (port) {
961 case 0: 966 case 0:
962 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, 967 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
963 ARRAY_SIZE(usb_otg1_pads)); 968 ARRAY_SIZE(usb_otg1_pads));
964 break; 969 break;
965 case 1: 970 case 1:
966 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, 971 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
967 ARRAY_SIZE(usb_otg2_pads)); 972 ARRAY_SIZE(usb_otg2_pads));
968 break; 973 break;
969 default: 974 default:
970 printf("MXC USB port %d not yet supported\n", port); 975 printf("MXC USB port %d not yet supported\n", port);
971 return 1; 976 return 1;
972 } 977 }
973 return 0; 978 return 0;
974 } 979 }
975 #endif 980 #endif
976 981
977 #ifdef CONFIG_FASTBOOT 982 #ifdef CONFIG_FASTBOOT
978 983
979 void board_fastboot_setup(void) 984 void board_fastboot_setup(void)
980 { 985 {
981 switch (get_boot_device()) { 986 switch (get_boot_device()) {
982 #if defined(CONFIG_FASTBOOT_STORAGE_MMC) 987 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
983 case SD2_BOOT: 988 case SD2_BOOT:
984 case MMC2_BOOT: 989 case MMC2_BOOT:
985 if (!getenv("fastboot_dev")) 990 if (!getenv("fastboot_dev"))
986 setenv("fastboot_dev", "mmc0"); 991 setenv("fastboot_dev", "mmc0");
987 if (!getenv("bootcmd")) 992 if (!getenv("bootcmd"))
988 setenv("bootcmd", "booti mmc0"); 993 setenv("bootcmd", "booti mmc0");
989 break; 994 break;
990 case SD3_BOOT: 995 case SD3_BOOT:
991 case MMC3_BOOT: 996 case MMC3_BOOT:
992 if (!getenv("fastboot_dev")) 997 if (!getenv("fastboot_dev"))
993 setenv("fastboot_dev", "mmc1"); 998 setenv("fastboot_dev", "mmc1");
994 if (!getenv("bootcmd")) 999 if (!getenv("bootcmd"))
995 setenv("bootcmd", "booti mmc1"); 1000 setenv("bootcmd", "booti mmc1");
996 break; 1001 break;
997 case SD4_BOOT: 1002 case SD4_BOOT:
998 case MMC4_BOOT: 1003 case MMC4_BOOT:
999 if (!getenv("fastboot_dev")) 1004 if (!getenv("fastboot_dev"))
1000 setenv("fastboot_dev", "mmc2"); 1005 setenv("fastboot_dev", "mmc2");
1001 if (!getenv("bootcmd")) 1006 if (!getenv("bootcmd"))
1002 setenv("bootcmd", "booti mmc2"); 1007 setenv("bootcmd", "booti mmc2");
1003 break; 1008 break;
1004 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ 1009 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
1005 default: 1010 default:
1006 printf("unsupported boot devices\n"); 1011 printf("unsupported boot devices\n");
1007 break; 1012 break;
1008 } 1013 }
1009 } 1014 }
1010 1015
1011 #ifdef CONFIG_ANDROID_RECOVERY 1016 #ifdef CONFIG_ANDROID_RECOVERY
1012 1017
1013 #define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 19) 1018 #define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 19)
1014 iomux_v3_cfg_t const recovery_key_pads[] = { 1019 iomux_v3_cfg_t const recovery_key_pads[] = {
1015 (MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 | MUX_PAD_CTRL(BUTTON_PAD_CTRL)), 1020 (MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 | MUX_PAD_CTRL(BUTTON_PAD_CTRL)),
1016 }; 1021 };
1017 1022
1018 int check_recovery_cmd_file(void) 1023 int check_recovery_cmd_file(void)
1019 { 1024 {
1020 int button_pressed = 0; 1025 int button_pressed = 0;
1021 int recovery_mode = 0; 1026 int recovery_mode = 0;
1022 1027
1023 recovery_mode = recovery_check_and_clean_flag(); 1028 recovery_mode = recovery_check_and_clean_flag();
1024 1029
1025 /* Check Recovery Combo Button press or not. */ 1030 /* Check Recovery Combo Button press or not. */
1026 imx_iomux_v3_setup_multiple_pads(recovery_key_pads, 1031 imx_iomux_v3_setup_multiple_pads(recovery_key_pads,
1027 ARRAY_SIZE(recovery_key_pads)); 1032 ARRAY_SIZE(recovery_key_pads));
1028 1033
1029 gpio_direction_input(GPIO_VOL_DN_KEY); 1034 gpio_direction_input(GPIO_VOL_DN_KEY);
1030 1035
1031 if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ 1036 if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */
1032 button_pressed = 1; 1037 button_pressed = 1;
1033 printf("Recovery key pressed\n"); 1038 printf("Recovery key pressed\n");
1034 } 1039 }
1035 1040
1036 return recovery_mode || button_pressed; 1041 return recovery_mode || button_pressed;
1037 } 1042 }
1038 1043
1039 void board_recovery_setup(void) 1044 void board_recovery_setup(void)
1040 { 1045 {
1041 int bootdev = get_boot_device(); 1046 int bootdev = get_boot_device();
1042 1047
1043 switch (bootdev) { 1048 switch (bootdev) {
1044 #if defined(CONFIG_FASTBOOT_STORAGE_MMC) 1049 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
1045 case SD2_BOOT: 1050 case SD2_BOOT:
1046 case MMC2_BOOT: 1051 case MMC2_BOOT:
1047 if (!getenv("bootcmd_android_recovery")) 1052 if (!getenv("bootcmd_android_recovery"))
1048 setenv("bootcmd_android_recovery", "booti mmc0 recovery"); 1053 setenv("bootcmd_android_recovery", "booti mmc0 recovery");
1049 break; 1054 break;
1050 case SD3_BOOT: 1055 case SD3_BOOT:
1051 case MMC3_BOOT: 1056 case MMC3_BOOT:
1052 if (!getenv("bootcmd_android_recovery")) 1057 if (!getenv("bootcmd_android_recovery"))
1053 setenv("bootcmd_android_recovery", "booti mmc1 recovery"); 1058 setenv("bootcmd_android_recovery", "booti mmc1 recovery");
1054 break; 1059 break;
1055 case SD4_BOOT: 1060 case SD4_BOOT:
1056 case MMC4_BOOT: 1061 case MMC4_BOOT:
1057 if (!getenv("bootcmd_android_recovery")) 1062 if (!getenv("bootcmd_android_recovery"))
1058 setenv("bootcmd_android_recovery", "booti mmc2 recovery"); 1063 setenv("bootcmd_android_recovery", "booti mmc2 recovery");
1059 break; 1064 break;
1060 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ 1065 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
1061 default: 1066 default:
1062 printf("Unsupported bootup device for recovery: dev: %d\n", 1067 printf("Unsupported bootup device for recovery: dev: %d\n",
1063 bootdev); 1068 bootdev);
1064 return; 1069 return;
1065 } 1070 }
1066 1071
1067 printf("setup env for recovery..\n"); 1072 printf("setup env for recovery..\n");
1068 setenv("bootcmd", "run bootcmd_android_recovery"); 1073 setenv("bootcmd", "run bootcmd_android_recovery");
1069 } 1074 }
1070 #endif /*CONFIG_ANDROID_RECOVERY*/ 1075 #endif /*CONFIG_ANDROID_RECOVERY*/
1071 1076
1072 #endif /*CONFIG_FASTBOOT*/ 1077 #endif /*CONFIG_FASTBOOT*/
1073 1078
1074 #ifdef CONFIG_IMX_UDC 1079 #ifdef CONFIG_IMX_UDC
1075 iomux_v3_cfg_t const otg_udc_pads[] = { 1080 iomux_v3_cfg_t const otg_udc_pads[] = {
1076 (MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), 1081 (MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
1077 }; 1082 };
1078 void udc_pins_setting(void) 1083 void udc_pins_setting(void)
1079 { 1084 {
1080 imx_iomux_v3_setup_multiple_pads(otg_udc_pads, 1085 imx_iomux_v3_setup_multiple_pads(otg_udc_pads,
1081 ARRAY_SIZE(otg_udc_pads)); 1086 ARRAY_SIZE(otg_udc_pads));
1082 } 1087 }
1083 1088
1084 #endif /*CONFIG_IMX_UDC*/ 1089 #endif /*CONFIG_IMX_UDC*/
1085 1090