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Commit 6b9408edd3f6af6e91bcc0eebd4aedc0aca28934

Authored by Marek Vasut
Committed by Albert ARIBAUD
1 parent c3dfe70776
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

i.MX28: Add cache support to MXS NAND driver 

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

Showing 1 changed file with 50 additions and 3 deletions Inline Diff

drivers/mtd/nand/mxs_nand.c
Diff comments   View file @ 6b9408e
1 /* 1 /*
2 * Freescale i.MX28 NAND flash driver 2 * Freescale i.MX28 NAND flash driver
3 * 3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH 5 * on behalf of DENX Software Engineering GmbH
6 * 6 *
7 * Based on code from LTIB: 7 * Based on code from LTIB:
8 * Freescale GPMI NFC NAND Flash Driver 8 * Freescale GPMI NFC NAND Flash Driver
9 * 9 *
10 * Copyright (C) 2010 Freescale Semiconductor, Inc. 10 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 * Copyright (C) 2008 Embedded Alley Solutions, Inc. 11 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
12 * 12 *
13 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by 14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or 15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version. 16 * (at your option) any later version.
17 * 17 *
18 * This program is distributed in the hope that it will be useful, 18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details. 21 * GNU General Public License for more details.
22 * 22 *
23 * You should have received a copy of the GNU General Public License along 23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc., 24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 25 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
26 */ 26 */
27 27
28 #include <linux/mtd/mtd.h> 28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/nand.h> 29 #include <linux/mtd/nand.h>
30 #include <linux/types.h> 30 #include <linux/types.h>
31 #include <common.h> 31 #include <common.h>
32 #include <malloc.h> 32 #include <malloc.h>
33 #include <asm/errno.h> 33 #include <asm/errno.h>
34 #include <asm/io.h> 34 #include <asm/io.h>
35 #include <asm/arch/clock.h> 35 #include <asm/arch/clock.h>
36 #include <asm/arch/imx-regs.h> 36 #include <asm/arch/imx-regs.h>
37 #include <asm/arch/sys_proto.h> 37 #include <asm/arch/sys_proto.h>
38 #include <asm/arch/dma.h> 38 #include <asm/arch/dma.h>
39 39
40 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4 40 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
41 41
42 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512 42 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
43 #define MXS_NAND_METADATA_SIZE 10 43 #define MXS_NAND_METADATA_SIZE 10
44 44
45 #define MXS_NAND_COMMAND_BUFFER_SIZE 32 45 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
46 46
47 #define MXS_NAND_BCH_TIMEOUT 10000 47 #define MXS_NAND_BCH_TIMEOUT 10000
48 48
49 struct mxs_nand_info { 49 struct mxs_nand_info {
50 int cur_chip; 50 int cur_chip;
51 51
52 uint32_t cmd_queue_len; 52 uint32_t cmd_queue_len;
53 uint32_t data_buf_size;
53 54
54 uint8_t *cmd_buf; 55 uint8_t *cmd_buf;
55 uint8_t *data_buf; 56 uint8_t *data_buf;
56 uint8_t *oob_buf; 57 uint8_t *oob_buf;
57 58
58 uint8_t marking_block_bad; 59 uint8_t marking_block_bad;
59 uint8_t raw_oob_mode; 60 uint8_t raw_oob_mode;
60 61
61 /* Functions with altered behaviour */ 62 /* Functions with altered behaviour */
62 int (*hooked_read_oob)(struct mtd_info *mtd, 63 int (*hooked_read_oob)(struct mtd_info *mtd,
63 loff_t from, struct mtd_oob_ops *ops); 64 loff_t from, struct mtd_oob_ops *ops);
64 int (*hooked_write_oob)(struct mtd_info *mtd, 65 int (*hooked_write_oob)(struct mtd_info *mtd,
65 loff_t to, struct mtd_oob_ops *ops); 66 loff_t to, struct mtd_oob_ops *ops);
66 int (*hooked_block_markbad)(struct mtd_info *mtd, 67 int (*hooked_block_markbad)(struct mtd_info *mtd,
67 loff_t ofs); 68 loff_t ofs);
68 69
69 /* DMA descriptors */ 70 /* DMA descriptors */
70 struct mxs_dma_desc **desc; 71 struct mxs_dma_desc **desc;
71 uint32_t desc_index; 72 uint32_t desc_index;
72 }; 73 };
73 74
74 struct nand_ecclayout fake_ecc_layout; 75 struct nand_ecclayout fake_ecc_layout;
75 76
77 /*
78 * Cache management functions
79 */
80 #ifndef CONFIG_SYS_DCACHE_OFF
81 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
82 {
83 uint32_t addr = (uint32_t)info->data_buf;
84
85 flush_dcache_range(addr, addr + info->data_buf_size);
86 }
87
88 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
89 {
90 uint32_t addr = (uint32_t)info->data_buf;
91
92 invalidate_dcache_range(addr, addr + info->data_buf_size);
93 }
94
95 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
96 {
97 uint32_t addr = (uint32_t)info->cmd_buf;
98
99 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
100 }
101 #else
102 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
103 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
104 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
105 #endif
106
76 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info) 107 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
77 { 108 {
78 struct mxs_dma_desc *desc; 109 struct mxs_dma_desc *desc;
79 110
80 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) { 111 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
81 printf("MXS NAND: Too many DMA descriptors requested\n"); 112 printf("MXS NAND: Too many DMA descriptors requested\n");
82 return NULL; 113 return NULL;
83 } 114 }
84 115
85 desc = info->desc[info->desc_index]; 116 desc = info->desc[info->desc_index];
86 info->desc_index++; 117 info->desc_index++;
87 118
88 return desc; 119 return desc;
89 } 120 }
90 121
91 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info) 122 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
92 { 123 {
93 int i; 124 int i;
94 struct mxs_dma_desc *desc; 125 struct mxs_dma_desc *desc;
95 126
96 for (i = 0; i < info->desc_index; i++) { 127 for (i = 0; i < info->desc_index; i++) {
97 desc = info->desc[i]; 128 desc = info->desc[i];
98 memset(desc, 0, sizeof(struct mxs_dma_desc)); 129 memset(desc, 0, sizeof(struct mxs_dma_desc));
99 desc->address = (dma_addr_t)desc; 130 desc->address = (dma_addr_t)desc;
100 } 131 }
101 132
102 info->desc_index = 0; 133 info->desc_index = 0;
103 } 134 }
104 135
105 static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size) 136 static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)
106 { 137 {
107 return page_data_size / MXS_NAND_CHUNK_DATA_CHUNK_SIZE; 138 return page_data_size / MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
108 } 139 }
109 140
110 static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength) 141 static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
111 { 142 {
112 return ecc_strength * 13; 143 return ecc_strength * 13;
113 } 144 }
114 145
115 static uint32_t mxs_nand_aux_status_offset(void) 146 static uint32_t mxs_nand_aux_status_offset(void)
116 { 147 {
117 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3; 148 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
118 } 149 }
119 150
120 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size, 151 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
121 uint32_t page_oob_size) 152 uint32_t page_oob_size)
122 { 153 {
123 if (page_data_size == 2048) 154 if (page_data_size == 2048)
124 return 8; 155 return 8;
125 156
126 if (page_data_size == 4096) { 157 if (page_data_size == 4096) {
127 if (page_oob_size == 128) 158 if (page_oob_size == 128)
128 return 8; 159 return 8;
129 160
130 if (page_oob_size == 218) 161 if (page_oob_size == 218)
131 return 16; 162 return 16;
132 } 163 }
133 164
134 return 0; 165 return 0;
135 } 166 }
136 167
137 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size, 168 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
138 uint32_t ecc_strength) 169 uint32_t ecc_strength)
139 { 170 {
140 uint32_t chunk_data_size_in_bits; 171 uint32_t chunk_data_size_in_bits;
141 uint32_t chunk_ecc_size_in_bits; 172 uint32_t chunk_ecc_size_in_bits;
142 uint32_t chunk_total_size_in_bits; 173 uint32_t chunk_total_size_in_bits;
143 uint32_t block_mark_chunk_number; 174 uint32_t block_mark_chunk_number;
144 uint32_t block_mark_chunk_bit_offset; 175 uint32_t block_mark_chunk_bit_offset;
145 uint32_t block_mark_bit_offset; 176 uint32_t block_mark_bit_offset;
146 177
147 chunk_data_size_in_bits = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 8; 178 chunk_data_size_in_bits = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 8;
148 chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength); 179 chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
149 180
150 chunk_total_size_in_bits = 181 chunk_total_size_in_bits =
151 chunk_data_size_in_bits + chunk_ecc_size_in_bits; 182 chunk_data_size_in_bits + chunk_ecc_size_in_bits;
152 183
153 /* Compute the bit offset of the block mark within the physical page. */ 184 /* Compute the bit offset of the block mark within the physical page. */
154 block_mark_bit_offset = page_data_size * 8; 185 block_mark_bit_offset = page_data_size * 8;
155 186
156 /* Subtract the metadata bits. */ 187 /* Subtract the metadata bits. */
157 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8; 188 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
158 189
159 /* 190 /*
160 * Compute the chunk number (starting at zero) in which the block mark 191 * Compute the chunk number (starting at zero) in which the block mark
161 * appears. 192 * appears.
162 */ 193 */
163 block_mark_chunk_number = 194 block_mark_chunk_number =
164 block_mark_bit_offset / chunk_total_size_in_bits; 195 block_mark_bit_offset / chunk_total_size_in_bits;
165 196
166 /* 197 /*
167 * Compute the bit offset of the block mark within its chunk, and 198 * Compute the bit offset of the block mark within its chunk, and
168 * validate it. 199 * validate it.
169 */ 200 */
170 block_mark_chunk_bit_offset = block_mark_bit_offset - 201 block_mark_chunk_bit_offset = block_mark_bit_offset -
171 (block_mark_chunk_number * chunk_total_size_in_bits); 202 (block_mark_chunk_number * chunk_total_size_in_bits);
172 203
173 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits) 204 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
174 return 1; 205 return 1;
175 206
176 /* 207 /*
177 * Now that we know the chunk number in which the block mark appears, 208 * Now that we know the chunk number in which the block mark appears,
178 * we can subtract all the ECC bits that appear before it. 209 * we can subtract all the ECC bits that appear before it.
179 */ 210 */
180 block_mark_bit_offset -= 211 block_mark_bit_offset -=
181 block_mark_chunk_number * chunk_ecc_size_in_bits; 212 block_mark_chunk_number * chunk_ecc_size_in_bits;
182 213
183 return block_mark_bit_offset; 214 return block_mark_bit_offset;
184 } 215 }
185 216
186 static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd) 217 static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
187 { 218 {
188 uint32_t ecc_strength; 219 uint32_t ecc_strength;
189 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize); 220 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
190 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3; 221 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
191 } 222 }
192 223
193 static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd) 224 static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
194 { 225 {
195 uint32_t ecc_strength; 226 uint32_t ecc_strength;
196 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize); 227 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
197 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7; 228 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
198 } 229 }
199 230
200 /* 231 /*
201 * Wait for BCH complete IRQ and clear the IRQ 232 * Wait for BCH complete IRQ and clear the IRQ
202 */ 233 */
203 static int mxs_nand_wait_for_bch_complete(void) 234 static int mxs_nand_wait_for_bch_complete(void)
204 { 235 {
205 struct mx28_bch_regs *bch_regs = (struct mx28_bch_regs *)MXS_BCH_BASE; 236 struct mx28_bch_regs *bch_regs = (struct mx28_bch_regs *)MXS_BCH_BASE;
206 int timeout = MXS_NAND_BCH_TIMEOUT; 237 int timeout = MXS_NAND_BCH_TIMEOUT;
207 int ret; 238 int ret;
208 239
209 ret = mx28_wait_mask_set(&bch_regs->hw_bch_ctrl_reg, 240 ret = mx28_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
210 BCH_CTRL_COMPLETE_IRQ, timeout); 241 BCH_CTRL_COMPLETE_IRQ, timeout);
211 242
212 writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr); 243 writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
213 244
214 return ret; 245 return ret;
215 } 246 }
216 247
217 /* 248 /*
218 * This is the function that we install in the cmd_ctrl function pointer of the 249 * This is the function that we install in the cmd_ctrl function pointer of the
219 * owning struct nand_chip. The only functions in the reference implementation 250 * owning struct nand_chip. The only functions in the reference implementation
220 * that use these functions pointers are cmdfunc and select_chip. 251 * that use these functions pointers are cmdfunc and select_chip.
221 * 252 *
222 * In this driver, we implement our own select_chip, so this function will only 253 * In this driver, we implement our own select_chip, so this function will only
223 * be called by the reference implementation's cmdfunc. For this reason, we can 254 * be called by the reference implementation's cmdfunc. For this reason, we can
224 * ignore the chip enable bit and concentrate only on sending bytes to the NAND 255 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
225 * Flash. 256 * Flash.
226 */ 257 */
227 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl) 258 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
228 { 259 {
229 struct nand_chip *nand = mtd->priv; 260 struct nand_chip *nand = mtd->priv;
230 struct mxs_nand_info *nand_info = nand->priv; 261 struct mxs_nand_info *nand_info = nand->priv;
231 struct mxs_dma_desc *d; 262 struct mxs_dma_desc *d;
232 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; 263 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
233 int ret; 264 int ret;
234 265
235 /* 266 /*
236 * If this condition is true, something is _VERY_ wrong in MTD 267 * If this condition is true, something is _VERY_ wrong in MTD
237 * subsystem! 268 * subsystem!
238 */ 269 */
239 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) { 270 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
240 printf("MXS NAND: Command queue too long\n"); 271 printf("MXS NAND: Command queue too long\n");
241 return; 272 return;
242 } 273 }
243 274
244 /* 275 /*
245 * Every operation begins with a command byte and a series of zero or 276 * Every operation begins with a command byte and a series of zero or
246 * more address bytes. These are distinguished by either the Address 277 * more address bytes. These are distinguished by either the Address
247 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being 278 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
248 * asserted. When MTD is ready to execute the command, it will 279 * asserted. When MTD is ready to execute the command, it will
249 * deasert both latch enables. 280 * deasert both latch enables.
250 * 281 *
251 * Rather than run a separate DMA operation for every single byte, we 282 * Rather than run a separate DMA operation for every single byte, we
252 * queue them up and run a single DMA operation for the entire series 283 * queue them up and run a single DMA operation for the entire series
253 * of command and data bytes. 284 * of command and data bytes.
254 */ 285 */
255 if (ctrl & (NAND_ALE | NAND_CLE)) { 286 if (ctrl & (NAND_ALE | NAND_CLE)) {
256 if (data != NAND_CMD_NONE) 287 if (data != NAND_CMD_NONE)
257 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data; 288 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
258 return; 289 return;
259 } 290 }
260 291
261 /* 292 /*
262 * If control arrives here, MTD has deasserted both the ALE and CLE, 293 * If control arrives here, MTD has deasserted both the ALE and CLE,
263 * which means it's ready to run an operation. Check if we have any 294 * which means it's ready to run an operation. Check if we have any
264 * bytes to send. 295 * bytes to send.
265 */ 296 */
266 if (nand_info->cmd_queue_len == 0) 297 if (nand_info->cmd_queue_len == 0)
267 return; 298 return;
268 299
269 /* Compile the DMA descriptor -- a descriptor that sends command. */ 300 /* Compile the DMA descriptor -- a descriptor that sends command. */
270 d = mxs_nand_get_dma_desc(nand_info); 301 d = mxs_nand_get_dma_desc(nand_info);
271 d->cmd.data = 302 d->cmd.data =
272 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ | 303 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
273 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM | 304 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
274 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | 305 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
275 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET); 306 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
276 307
277 d->cmd.address = (dma_addr_t)nand_info->cmd_buf; 308 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
278 309
279 d->cmd.pio_words[0] = 310 d->cmd.pio_words[0] =
280 GPMI_CTRL0_COMMAND_MODE_WRITE | 311 GPMI_CTRL0_COMMAND_MODE_WRITE |
281 GPMI_CTRL0_WORD_LENGTH | 312 GPMI_CTRL0_WORD_LENGTH |
282 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | 313 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
283 GPMI_CTRL0_ADDRESS_NAND_CLE | 314 GPMI_CTRL0_ADDRESS_NAND_CLE |
284 GPMI_CTRL0_ADDRESS_INCREMENT | 315 GPMI_CTRL0_ADDRESS_INCREMENT |
285 nand_info->cmd_queue_len; 316 nand_info->cmd_queue_len;
286 317
287 mxs_dma_desc_append(channel, d); 318 mxs_dma_desc_append(channel, d);
288 319
320 /* Flush caches */
321 mxs_nand_flush_cmd_buf(nand_info);
322
289 /* Execute the DMA chain. */ 323 /* Execute the DMA chain. */
290 ret = mxs_dma_go(channel); 324 ret = mxs_dma_go(channel);
291 if (ret) 325 if (ret)
292 printf("MXS NAND: Error sending command\n"); 326 printf("MXS NAND: Error sending command\n");
293 327
294 mxs_nand_return_dma_descs(nand_info); 328 mxs_nand_return_dma_descs(nand_info);
295 329
296 /* Reset the command queue. */ 330 /* Reset the command queue. */
297 nand_info->cmd_queue_len = 0; 331 nand_info->cmd_queue_len = 0;
298 } 332 }
299 333
300 /* 334 /*
301 * Test if the NAND flash is ready. 335 * Test if the NAND flash is ready.
302 */ 336 */
303 static int mxs_nand_device_ready(struct mtd_info *mtd) 337 static int mxs_nand_device_ready(struct mtd_info *mtd)
304 { 338 {
305 struct nand_chip *chip = mtd->priv; 339 struct nand_chip *chip = mtd->priv;
306 struct mxs_nand_info *nand_info = chip->priv; 340 struct mxs_nand_info *nand_info = chip->priv;
307 struct mx28_gpmi_regs *gpmi_regs = 341 struct mx28_gpmi_regs *gpmi_regs =
308 (struct mx28_gpmi_regs *)MXS_GPMI_BASE; 342 (struct mx28_gpmi_regs *)MXS_GPMI_BASE;
309 uint32_t tmp; 343 uint32_t tmp;
310 344
311 tmp = readl(&gpmi_regs->hw_gpmi_stat); 345 tmp = readl(&gpmi_regs->hw_gpmi_stat);
312 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip); 346 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
313 347
314 return tmp & 1; 348 return tmp & 1;
315 } 349 }
316 350
317 /* 351 /*
318 * Select the NAND chip. 352 * Select the NAND chip.
319 */ 353 */
320 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip) 354 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
321 { 355 {
322 struct nand_chip *nand = mtd->priv; 356 struct nand_chip *nand = mtd->priv;
323 struct mxs_nand_info *nand_info = nand->priv; 357 struct mxs_nand_info *nand_info = nand->priv;
324 358
325 nand_info->cur_chip = chip; 359 nand_info->cur_chip = chip;
326 } 360 }
327 361
328 /* 362 /*
329 * Handle block mark swapping. 363 * Handle block mark swapping.
330 * 364 *
331 * Note that, when this function is called, it doesn't know whether it's 365 * Note that, when this function is called, it doesn't know whether it's
332 * swapping the block mark, or swapping it *back* -- but it doesn't matter 366 * swapping the block mark, or swapping it *back* -- but it doesn't matter
333 * because the the operation is the same. 367 * because the the operation is the same.
334 */ 368 */
335 static void mxs_nand_swap_block_mark(struct mtd_info *mtd, 369 static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
336 uint8_t *data_buf, uint8_t *oob_buf) 370 uint8_t *data_buf, uint8_t *oob_buf)
337 { 371 {
338 uint32_t bit_offset; 372 uint32_t bit_offset;
339 uint32_t buf_offset; 373 uint32_t buf_offset;
340 374
341 uint32_t src; 375 uint32_t src;
342 uint32_t dst; 376 uint32_t dst;
343 377
344 bit_offset = mxs_nand_mark_bit_offset(mtd); 378 bit_offset = mxs_nand_mark_bit_offset(mtd);
345 buf_offset = mxs_nand_mark_byte_offset(mtd); 379 buf_offset = mxs_nand_mark_byte_offset(mtd);
346 380
347 /* 381 /*
348 * Get the byte from the data area that overlays the block mark. Since 382 * Get the byte from the data area that overlays the block mark. Since
349 * the ECC engine applies its own view to the bits in the page, the 383 * the ECC engine applies its own view to the bits in the page, the
350 * physical block mark won't (in general) appear on a byte boundary in 384 * physical block mark won't (in general) appear on a byte boundary in
351 * the data. 385 * the data.
352 */ 386 */
353 src = data_buf[buf_offset] >> bit_offset; 387 src = data_buf[buf_offset] >> bit_offset;
354 src |= data_buf[buf_offset + 1] << (8 - bit_offset); 388 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
355 389
356 dst = oob_buf[0]; 390 dst = oob_buf[0];
357 391
358 oob_buf[0] = src; 392 oob_buf[0] = src;
359 393
360 data_buf[buf_offset] &= ~(0xff << bit_offset); 394 data_buf[buf_offset] &= ~(0xff << bit_offset);
361 data_buf[buf_offset + 1] &= 0xff << bit_offset; 395 data_buf[buf_offset + 1] &= 0xff << bit_offset;
362 396
363 data_buf[buf_offset] |= dst << bit_offset; 397 data_buf[buf_offset] |= dst << bit_offset;
364 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset); 398 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
365 } 399 }
366 400
367 /* 401 /*
368 * Read data from NAND. 402 * Read data from NAND.
369 */ 403 */
370 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length) 404 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
371 { 405 {
372 struct nand_chip *nand = mtd->priv; 406 struct nand_chip *nand = mtd->priv;
373 struct mxs_nand_info *nand_info = nand->priv; 407 struct mxs_nand_info *nand_info = nand->priv;
374 struct mxs_dma_desc *d; 408 struct mxs_dma_desc *d;
375 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; 409 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
376 int ret; 410 int ret;
377 411
378 if (length > NAND_MAX_PAGESIZE) { 412 if (length > NAND_MAX_PAGESIZE) {
379 printf("MXS NAND: DMA buffer too big\n"); 413 printf("MXS NAND: DMA buffer too big\n");
380 return; 414 return;
381 } 415 }
382 416
383 if (!buf) { 417 if (!buf) {
384 printf("MXS NAND: DMA buffer is NULL\n"); 418 printf("MXS NAND: DMA buffer is NULL\n");
385 return; 419 return;
386 } 420 }
387 421
388 /* Compile the DMA descriptor - a descriptor that reads data. */ 422 /* Compile the DMA descriptor - a descriptor that reads data. */
389 d = mxs_nand_get_dma_desc(nand_info); 423 d = mxs_nand_get_dma_desc(nand_info);
390 d->cmd.data = 424 d->cmd.data =
391 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ | 425 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
392 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | 426 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
393 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | 427 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
394 (length << MXS_DMA_DESC_BYTES_OFFSET); 428 (length << MXS_DMA_DESC_BYTES_OFFSET);
395 429
396 d->cmd.address = (dma_addr_t)nand_info->data_buf; 430 d->cmd.address = (dma_addr_t)nand_info->data_buf;
397 431
398 d->cmd.pio_words[0] = 432 d->cmd.pio_words[0] =
399 GPMI_CTRL0_COMMAND_MODE_READ | 433 GPMI_CTRL0_COMMAND_MODE_READ |
400 GPMI_CTRL0_WORD_LENGTH | 434 GPMI_CTRL0_WORD_LENGTH |
401 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | 435 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
402 GPMI_CTRL0_ADDRESS_NAND_DATA | 436 GPMI_CTRL0_ADDRESS_NAND_DATA |
403 length; 437 length;
404 438
405 mxs_dma_desc_append(channel, d); 439 mxs_dma_desc_append(channel, d);
406 440
407 /* 441 /*
408 * A DMA descriptor that waits for the command to end and the chip to 442 * A DMA descriptor that waits for the command to end and the chip to
409 * become ready. 443 * become ready.
410 * 444 *
411 * I think we actually should *not* be waiting for the chip to become 445 * I think we actually should *not* be waiting for the chip to become
412 * ready because, after all, we don't care. I think the original code 446 * ready because, after all, we don't care. I think the original code
413 * did that and no one has re-thought it yet. 447 * did that and no one has re-thought it yet.
414 */ 448 */
415 d = mxs_nand_get_dma_desc(nand_info); 449 d = mxs_nand_get_dma_desc(nand_info);
416 d->cmd.data = 450 d->cmd.data =
417 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ | 451 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
418 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM | 452 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
419 MXS_DMA_DESC_WAIT4END | (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET); 453 MXS_DMA_DESC_WAIT4END | (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
420 454
421 d->cmd.address = 0; 455 d->cmd.address = 0;
422 456
423 d->cmd.pio_words[0] = 457 d->cmd.pio_words[0] =
424 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY | 458 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
425 GPMI_CTRL0_WORD_LENGTH | 459 GPMI_CTRL0_WORD_LENGTH |
426 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | 460 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
427 GPMI_CTRL0_ADDRESS_NAND_DATA; 461 GPMI_CTRL0_ADDRESS_NAND_DATA;
428 462
429 mxs_dma_desc_append(channel, d); 463 mxs_dma_desc_append(channel, d);
430 464
431 /* Execute the DMA chain. */ 465 /* Execute the DMA chain. */
432 ret = mxs_dma_go(channel); 466 ret = mxs_dma_go(channel);
433 if (ret) { 467 if (ret) {
434 printf("MXS NAND: DMA read error\n"); 468 printf("MXS NAND: DMA read error\n");
435 goto rtn; 469 goto rtn;
436 } 470 }
437 471
472 /* Invalidate caches */
473 mxs_nand_inval_data_buf(nand_info);
474
438 memcpy(buf, nand_info->data_buf, length); 475 memcpy(buf, nand_info->data_buf, length);
439 476
440 rtn: 477 rtn:
441 mxs_nand_return_dma_descs(nand_info); 478 mxs_nand_return_dma_descs(nand_info);
442 } 479 }
443 480
444 /* 481 /*
445 * Write data to NAND. 482 * Write data to NAND.
446 */ 483 */
447 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, 484 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
448 int length) 485 int length)
449 { 486 {
450 struct nand_chip *nand = mtd->priv; 487 struct nand_chip *nand = mtd->priv;
451 struct mxs_nand_info *nand_info = nand->priv; 488 struct mxs_nand_info *nand_info = nand->priv;
452 struct mxs_dma_desc *d; 489 struct mxs_dma_desc *d;
453 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; 490 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
454 int ret; 491 int ret;
455 492
456 if (length > NAND_MAX_PAGESIZE) { 493 if (length > NAND_MAX_PAGESIZE) {
457 printf("MXS NAND: DMA buffer too big\n"); 494 printf("MXS NAND: DMA buffer too big\n");
458 return; 495 return;
459 } 496 }
460 497
461 if (!buf) { 498 if (!buf) {
462 printf("MXS NAND: DMA buffer is NULL\n"); 499 printf("MXS NAND: DMA buffer is NULL\n");
463 return; 500 return;
464 } 501 }
465 502
466 memcpy(nand_info->data_buf, buf, length); 503 memcpy(nand_info->data_buf, buf, length);
467 504
468 /* Compile the DMA descriptor - a descriptor that writes data. */ 505 /* Compile the DMA descriptor - a descriptor that writes data. */
469 d = mxs_nand_get_dma_desc(nand_info); 506 d = mxs_nand_get_dma_desc(nand_info);
470 d->cmd.data = 507 d->cmd.data =
471 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ | 508 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
472 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | 509 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
473 (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | 510 (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
474 (length << MXS_DMA_DESC_BYTES_OFFSET); 511 (length << MXS_DMA_DESC_BYTES_OFFSET);
475 512
476 d->cmd.address = (dma_addr_t)nand_info->data_buf; 513 d->cmd.address = (dma_addr_t)nand_info->data_buf;
477 514
478 d->cmd.pio_words[0] = 515 d->cmd.pio_words[0] =
479 GPMI_CTRL0_COMMAND_MODE_WRITE | 516 GPMI_CTRL0_COMMAND_MODE_WRITE |
480 GPMI_CTRL0_WORD_LENGTH | 517 GPMI_CTRL0_WORD_LENGTH |
481 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | 518 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
482 GPMI_CTRL0_ADDRESS_NAND_DATA | 519 GPMI_CTRL0_ADDRESS_NAND_DATA |
483 length; 520 length;
484 521
485 mxs_dma_desc_append(channel, d); 522 mxs_dma_desc_append(channel, d);
486 523
524 /* Flush caches */
525 mxs_nand_flush_data_buf(nand_info);
526
487 /* Execute the DMA chain. */ 527 /* Execute the DMA chain. */
488 ret = mxs_dma_go(channel); 528 ret = mxs_dma_go(channel);
489 if (ret) 529 if (ret)
490 printf("MXS NAND: DMA write error\n"); 530 printf("MXS NAND: DMA write error\n");
491 531
492 mxs_nand_return_dma_descs(nand_info); 532 mxs_nand_return_dma_descs(nand_info);
493 } 533 }
494 534
495 /* 535 /*
496 * Read a single byte from NAND. 536 * Read a single byte from NAND.
497 */ 537 */
498 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd) 538 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
499 { 539 {
500 uint8_t buf; 540 uint8_t buf;
501 mxs_nand_read_buf(mtd, &buf, 1); 541 mxs_nand_read_buf(mtd, &buf, 1);
502 return buf; 542 return buf;
503 } 543 }
504 544
505 /* 545 /*
506 * Read a page from NAND. 546 * Read a page from NAND.
507 */ 547 */
508 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, 548 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
509 uint8_t *buf, int page) 549 uint8_t *buf, int page)
510 { 550 {
511 struct mxs_nand_info *nand_info = nand->priv; 551 struct mxs_nand_info *nand_info = nand->priv;
512 struct mxs_dma_desc *d; 552 struct mxs_dma_desc *d;
513 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; 553 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
514 uint32_t corrected = 0, failed = 0; 554 uint32_t corrected = 0, failed = 0;
515 uint8_t *status; 555 uint8_t *status;
516 int i, ret; 556 int i, ret;
517 557
518 /* Compile the DMA descriptor - wait for ready. */ 558 /* Compile the DMA descriptor - wait for ready. */
519 d = mxs_nand_get_dma_desc(nand_info); 559 d = mxs_nand_get_dma_desc(nand_info);
520 d->cmd.data = 560 d->cmd.data =
521 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | 561 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
522 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END | 562 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
523 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET); 563 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
524 564
525 d->cmd.address = 0; 565 d->cmd.address = 0;
526 566
527 d->cmd.pio_words[0] = 567 d->cmd.pio_words[0] =
528 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY | 568 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
529 GPMI_CTRL0_WORD_LENGTH | 569 GPMI_CTRL0_WORD_LENGTH |
530 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | 570 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
531 GPMI_CTRL0_ADDRESS_NAND_DATA; 571 GPMI_CTRL0_ADDRESS_NAND_DATA;
532 572
533 mxs_dma_desc_append(channel, d); 573 mxs_dma_desc_append(channel, d);
534 574
535 /* Compile the DMA descriptor - enable the BCH block and read. */ 575 /* Compile the DMA descriptor - enable the BCH block and read. */
536 d = mxs_nand_get_dma_desc(nand_info); 576 d = mxs_nand_get_dma_desc(nand_info);
537 d->cmd.data = 577 d->cmd.data =
538 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | 578 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
539 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET); 579 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
540 580
541 d->cmd.address = 0; 581 d->cmd.address = 0;
542 582
543 d->cmd.pio_words[0] = 583 d->cmd.pio_words[0] =
544 GPMI_CTRL0_COMMAND_MODE_READ | 584 GPMI_CTRL0_COMMAND_MODE_READ |
545 GPMI_CTRL0_WORD_LENGTH | 585 GPMI_CTRL0_WORD_LENGTH |
546 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | 586 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
547 GPMI_CTRL0_ADDRESS_NAND_DATA | 587 GPMI_CTRL0_ADDRESS_NAND_DATA |
548 (mtd->writesize + mtd->oobsize); 588 (mtd->writesize + mtd->oobsize);
549 d->cmd.pio_words[1] = 0; 589 d->cmd.pio_words[1] = 0;
550 d->cmd.pio_words[2] = 590 d->cmd.pio_words[2] =
551 GPMI_ECCCTRL_ENABLE_ECC | 591 GPMI_ECCCTRL_ENABLE_ECC |
552 GPMI_ECCCTRL_ECC_CMD_DECODE | 592 GPMI_ECCCTRL_ECC_CMD_DECODE |
553 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE; 593 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
554 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize; 594 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
555 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf; 595 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
556 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf; 596 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
557 597
558 mxs_dma_desc_append(channel, d); 598 mxs_dma_desc_append(channel, d);
559 599
560 /* Compile the DMA descriptor - disable the BCH block. */ 600 /* Compile the DMA descriptor - disable the BCH block. */
561 d = mxs_nand_get_dma_desc(nand_info); 601 d = mxs_nand_get_dma_desc(nand_info);
562 d->cmd.data = 602 d->cmd.data =
563 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | 603 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
564 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END | 604 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
565 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET); 605 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
566 606
567 d->cmd.address = 0; 607 d->cmd.address = 0;
568 608
569 d->cmd.pio_words[0] = 609 d->cmd.pio_words[0] =
570 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY | 610 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
571 GPMI_CTRL0_WORD_LENGTH | 611 GPMI_CTRL0_WORD_LENGTH |
572 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | 612 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
573 GPMI_CTRL0_ADDRESS_NAND_DATA | 613 GPMI_CTRL0_ADDRESS_NAND_DATA |
574 (mtd->writesize + mtd->oobsize); 614 (mtd->writesize + mtd->oobsize);
575 d->cmd.pio_words[1] = 0; 615 d->cmd.pio_words[1] = 0;
576 d->cmd.pio_words[2] = 0; 616 d->cmd.pio_words[2] = 0;
577 617
578 mxs_dma_desc_append(channel, d); 618 mxs_dma_desc_append(channel, d);
579 619
580 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */ 620 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
581 d = mxs_nand_get_dma_desc(nand_info); 621 d = mxs_nand_get_dma_desc(nand_info);
582 d->cmd.data = 622 d->cmd.data =
583 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ | 623 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
584 MXS_DMA_DESC_DEC_SEM; 624 MXS_DMA_DESC_DEC_SEM;
585 625
586 d->cmd.address = 0; 626 d->cmd.address = 0;
587 627
588 mxs_dma_desc_append(channel, d); 628 mxs_dma_desc_append(channel, d);
589 629
590 /* Execute the DMA chain. */ 630 /* Execute the DMA chain. */
591 ret = mxs_dma_go(channel); 631 ret = mxs_dma_go(channel);
592 if (ret) { 632 if (ret) {
593 printf("MXS NAND: DMA read error\n"); 633 printf("MXS NAND: DMA read error\n");
594 goto rtn; 634 goto rtn;
595 } 635 }
596 636
597 ret = mxs_nand_wait_for_bch_complete(); 637 ret = mxs_nand_wait_for_bch_complete();
598 if (ret) { 638 if (ret) {
599 printf("MXS NAND: BCH read timeout\n"); 639 printf("MXS NAND: BCH read timeout\n");
600 goto rtn; 640 goto rtn;
601 } 641 }
602 642
643 /* Invalidate caches */
644 mxs_nand_inval_data_buf(nand_info);
645
603 /* Read DMA completed, now do the mark swapping. */ 646 /* Read DMA completed, now do the mark swapping. */
604 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf); 647 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
605 648
606 /* Loop over status bytes, accumulating ECC status. */ 649 /* Loop over status bytes, accumulating ECC status. */
607 status = nand_info->oob_buf + mxs_nand_aux_status_offset(); 650 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
608 for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) { 651 for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) {
609 if (status[i] == 0x00) 652 if (status[i] == 0x00)
610 continue; 653 continue;
611 654
612 if (status[i] == 0xff) 655 if (status[i] == 0xff)
613 continue; 656 continue;
614 657
615 if (status[i] == 0xfe) { 658 if (status[i] == 0xfe) {
616 failed++; 659 failed++;
617 continue; 660 continue;
618 } 661 }
619 662
620 corrected += status[i]; 663 corrected += status[i];
621 } 664 }
622 665
623 /* Propagate ECC status to the owning MTD. */ 666 /* Propagate ECC status to the owning MTD. */
624 mtd->ecc_stats.failed += failed; 667 mtd->ecc_stats.failed += failed;
625 mtd->ecc_stats.corrected += corrected; 668 mtd->ecc_stats.corrected += corrected;
626 669
627 /* 670 /*
628 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for 671 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
629 * details about our policy for delivering the OOB. 672 * details about our policy for delivering the OOB.
630 * 673 *
631 * We fill the caller's buffer with set bits, and then copy the block 674 * We fill the caller's buffer with set bits, and then copy the block
632 * mark to the caller's buffer. Note that, if block mark swapping was 675 * mark to the caller's buffer. Note that, if block mark swapping was
633 * necessary, it has already been done, so we can rely on the first 676 * necessary, it has already been done, so we can rely on the first
634 * byte of the auxiliary buffer to contain the block mark. 677 * byte of the auxiliary buffer to contain the block mark.
635 */ 678 */
636 memset(nand->oob_poi, 0xff, mtd->oobsize); 679 memset(nand->oob_poi, 0xff, mtd->oobsize);
637 680
638 nand->oob_poi[0] = nand_info->oob_buf[0]; 681 nand->oob_poi[0] = nand_info->oob_buf[0];
639 682
640 memcpy(buf, nand_info->data_buf, mtd->writesize); 683 memcpy(buf, nand_info->data_buf, mtd->writesize);
641 684
642 rtn: 685 rtn:
643 mxs_nand_return_dma_descs(nand_info); 686 mxs_nand_return_dma_descs(nand_info);
644 687
645 return ret; 688 return ret;
646 } 689 }
647 690
648 /* 691 /*
649 * Write a page to NAND. 692 * Write a page to NAND.
650 */ 693 */
651 static void mxs_nand_ecc_write_page(struct mtd_info *mtd, 694 static void mxs_nand_ecc_write_page(struct mtd_info *mtd,
652 struct nand_chip *nand, const uint8_t *buf) 695 struct nand_chip *nand, const uint8_t *buf)
653 { 696 {
654 struct mxs_nand_info *nand_info = nand->priv; 697 struct mxs_nand_info *nand_info = nand->priv;
655 struct mxs_dma_desc *d; 698 struct mxs_dma_desc *d;
656 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; 699 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
657 int ret; 700 int ret;
658 701
659 memcpy(nand_info->data_buf, buf, mtd->writesize); 702 memcpy(nand_info->data_buf, buf, mtd->writesize);
660 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize); 703 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
661 704
662 /* Handle block mark swapping. */ 705 /* Handle block mark swapping. */
663 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf); 706 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
664 707
665 /* Compile the DMA descriptor - write data. */ 708 /* Compile the DMA descriptor - write data. */
666 d = mxs_nand_get_dma_desc(nand_info); 709 d = mxs_nand_get_dma_desc(nand_info);
667 d->cmd.data = 710 d->cmd.data =
668 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ | 711 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
669 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | 712 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
670 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET); 713 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
671 714
672 d->cmd.address = 0; 715 d->cmd.address = 0;
673 716
674 d->cmd.pio_words[0] = 717 d->cmd.pio_words[0] =
675 GPMI_CTRL0_COMMAND_MODE_WRITE | 718 GPMI_CTRL0_COMMAND_MODE_WRITE |
676 GPMI_CTRL0_WORD_LENGTH | 719 GPMI_CTRL0_WORD_LENGTH |
677 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | 720 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
678 GPMI_CTRL0_ADDRESS_NAND_DATA; 721 GPMI_CTRL0_ADDRESS_NAND_DATA;
679 d->cmd.pio_words[1] = 0; 722 d->cmd.pio_words[1] = 0;
680 d->cmd.pio_words[2] = 723 d->cmd.pio_words[2] =
681 GPMI_ECCCTRL_ENABLE_ECC | 724 GPMI_ECCCTRL_ENABLE_ECC |
682 GPMI_ECCCTRL_ECC_CMD_ENCODE | 725 GPMI_ECCCTRL_ECC_CMD_ENCODE |
683 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE; 726 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
684 d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize); 727 d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
685 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf; 728 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
686 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf; 729 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
687 730
688 mxs_dma_desc_append(channel, d); 731 mxs_dma_desc_append(channel, d);
689 732
733 /* Flush caches */
734 mxs_nand_flush_data_buf(nand_info);
735
690 /* Execute the DMA chain. */ 736 /* Execute the DMA chain. */
691 ret = mxs_dma_go(channel); 737 ret = mxs_dma_go(channel);
692 if (ret) { 738 if (ret) {
693 printf("MXS NAND: DMA write error\n"); 739 printf("MXS NAND: DMA write error\n");
694 goto rtn; 740 goto rtn;
695 } 741 }
696 742
697 ret = mxs_nand_wait_for_bch_complete(); 743 ret = mxs_nand_wait_for_bch_complete();
698 if (ret) { 744 if (ret) {
699 printf("MXS NAND: BCH write timeout\n"); 745 printf("MXS NAND: BCH write timeout\n");
700 goto rtn; 746 goto rtn;
701 } 747 }
702 748
703 rtn: 749 rtn:
704 mxs_nand_return_dma_descs(nand_info); 750 mxs_nand_return_dma_descs(nand_info);
705 } 751 }
706 752
707 /* 753 /*
708 * Read OOB from NAND. 754 * Read OOB from NAND.
709 * 755 *
710 * This function is a veneer that replaces the function originally installed by 756 * This function is a veneer that replaces the function originally installed by
711 * the NAND Flash MTD code. 757 * the NAND Flash MTD code.
712 */ 758 */
713 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from, 759 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
714 struct mtd_oob_ops *ops) 760 struct mtd_oob_ops *ops)
715 { 761 {
716 struct nand_chip *chip = mtd->priv; 762 struct nand_chip *chip = mtd->priv;
717 struct mxs_nand_info *nand_info = chip->priv; 763 struct mxs_nand_info *nand_info = chip->priv;
718 int ret; 764 int ret;
719 765
720 if (ops->mode == MTD_OOB_RAW) 766 if (ops->mode == MTD_OOB_RAW)
721 nand_info->raw_oob_mode = 1; 767 nand_info->raw_oob_mode = 1;
722 else 768 else
723 nand_info->raw_oob_mode = 0; 769 nand_info->raw_oob_mode = 0;
724 770
725 ret = nand_info->hooked_read_oob(mtd, from, ops); 771 ret = nand_info->hooked_read_oob(mtd, from, ops);
726 772
727 nand_info->raw_oob_mode = 0; 773 nand_info->raw_oob_mode = 0;
728 774
729 return ret; 775 return ret;
730 } 776 }
731 777
732 /* 778 /*
733 * Write OOB to NAND. 779 * Write OOB to NAND.
734 * 780 *
735 * This function is a veneer that replaces the function originally installed by 781 * This function is a veneer that replaces the function originally installed by
736 * the NAND Flash MTD code. 782 * the NAND Flash MTD code.
737 */ 783 */
738 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to, 784 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
739 struct mtd_oob_ops *ops) 785 struct mtd_oob_ops *ops)
740 { 786 {
741 struct nand_chip *chip = mtd->priv; 787 struct nand_chip *chip = mtd->priv;
742 struct mxs_nand_info *nand_info = chip->priv; 788 struct mxs_nand_info *nand_info = chip->priv;
743 int ret; 789 int ret;
744 790
745 if (ops->mode == MTD_OOB_RAW) 791 if (ops->mode == MTD_OOB_RAW)
746 nand_info->raw_oob_mode = 1; 792 nand_info->raw_oob_mode = 1;
747 else 793 else
748 nand_info->raw_oob_mode = 0; 794 nand_info->raw_oob_mode = 0;
749 795
750 ret = nand_info->hooked_write_oob(mtd, to, ops); 796 ret = nand_info->hooked_write_oob(mtd, to, ops);
751 797
752 nand_info->raw_oob_mode = 0; 798 nand_info->raw_oob_mode = 0;
753 799
754 return ret; 800 return ret;
755 } 801 }
756 802
757 /* 803 /*
758 * Mark a block bad in NAND. 804 * Mark a block bad in NAND.
759 * 805 *
760 * This function is a veneer that replaces the function originally installed by 806 * This function is a veneer that replaces the function originally installed by
761 * the NAND Flash MTD code. 807 * the NAND Flash MTD code.
762 */ 808 */
763 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs) 809 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
764 { 810 {
765 struct nand_chip *chip = mtd->priv; 811 struct nand_chip *chip = mtd->priv;
766 struct mxs_nand_info *nand_info = chip->priv; 812 struct mxs_nand_info *nand_info = chip->priv;
767 int ret; 813 int ret;
768 814
769 nand_info->marking_block_bad = 1; 815 nand_info->marking_block_bad = 1;
770 816
771 ret = nand_info->hooked_block_markbad(mtd, ofs); 817 ret = nand_info->hooked_block_markbad(mtd, ofs);
772 818
773 nand_info->marking_block_bad = 0; 819 nand_info->marking_block_bad = 0;
774 820
775 return ret; 821 return ret;
776 } 822 }
777 823
778 /* 824 /*
779 * There are several places in this driver where we have to handle the OOB and 825 * There are several places in this driver where we have to handle the OOB and
780 * block marks. This is the function where things are the most complicated, so 826 * block marks. This is the function where things are the most complicated, so
781 * this is where we try to explain it all. All the other places refer back to 827 * this is where we try to explain it all. All the other places refer back to
782 * here. 828 * here.
783 * 829 *
784 * These are the rules, in order of decreasing importance: 830 * These are the rules, in order of decreasing importance:
785 * 831 *
786 * 1) Nothing the caller does can be allowed to imperil the block mark, so all 832 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
787 * write operations take measures to protect it. 833 * write operations take measures to protect it.
788 * 834 *
789 * 2) In read operations, the first byte of the OOB we return must reflect the 835 * 2) In read operations, the first byte of the OOB we return must reflect the
790 * true state of the block mark, no matter where that block mark appears in 836 * true state of the block mark, no matter where that block mark appears in
791 * the physical page. 837 * the physical page.
792 * 838 *
793 * 3) ECC-based read operations return an OOB full of set bits (since we never 839 * 3) ECC-based read operations return an OOB full of set bits (since we never
794 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads 840 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
795 * return). 841 * return).
796 * 842 *
797 * 4) "Raw" read operations return a direct view of the physical bytes in the 843 * 4) "Raw" read operations return a direct view of the physical bytes in the
798 * page, using the conventional definition of which bytes are data and which 844 * page, using the conventional definition of which bytes are data and which
799 * are OOB. This gives the caller a way to see the actual, physical bytes 845 * are OOB. This gives the caller a way to see the actual, physical bytes
800 * in the page, without the distortions applied by our ECC engine. 846 * in the page, without the distortions applied by our ECC engine.
801 * 847 *
802 * What we do for this specific read operation depends on whether we're doing 848 * What we do for this specific read operation depends on whether we're doing
803 * "raw" read, or an ECC-based read. 849 * "raw" read, or an ECC-based read.
804 * 850 *
805 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not 851 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
806 * easy. When reading a page, for example, the NAND Flash MTD code calls our 852 * easy. When reading a page, for example, the NAND Flash MTD code calls our
807 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an 853 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
808 * ECC-based or raw view of the page is implicit in which function it calls 854 * ECC-based or raw view of the page is implicit in which function it calls
809 * (there is a similar pair of ECC-based/raw functions for writing). 855 * (there is a similar pair of ECC-based/raw functions for writing).
810 * 856 *
811 * Since MTD assumes the OOB is not covered by ECC, there is no pair of 857 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
812 * ECC-based/raw functions for reading or or writing the OOB. The fact that the 858 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
813 * caller wants an ECC-based or raw view of the page is not propagated down to 859 * caller wants an ECC-based or raw view of the page is not propagated down to
814 * this driver. 860 * this driver.
815 * 861 *
816 * Since our OOB *is* covered by ECC, we need this information. So, we hook the 862 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
817 * ecc.read_oob and ecc.write_oob function pointers in the owning 863 * ecc.read_oob and ecc.write_oob function pointers in the owning
818 * struct mtd_info with our own functions. These hook functions set the 864 * struct mtd_info with our own functions. These hook functions set the
819 * raw_oob_mode field so that, when control finally arrives here, we'll know 865 * raw_oob_mode field so that, when control finally arrives here, we'll know
820 * what to do. 866 * what to do.
821 */ 867 */
822 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand, 868 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
823 int page, int cmd) 869 int page, int cmd)
824 { 870 {
825 struct mxs_nand_info *nand_info = nand->priv; 871 struct mxs_nand_info *nand_info = nand->priv;
826 872
827 /* 873 /*
828 * First, fill in the OOB buffer. If we're doing a raw read, we need to 874 * First, fill in the OOB buffer. If we're doing a raw read, we need to
829 * get the bytes from the physical page. If we're not doing a raw read, 875 * get the bytes from the physical page. If we're not doing a raw read,
830 * we need to fill the buffer with set bits. 876 * we need to fill the buffer with set bits.
831 */ 877 */
832 if (nand_info->raw_oob_mode) { 878 if (nand_info->raw_oob_mode) {
833 /* 879 /*
834 * If control arrives here, we're doing a "raw" read. Send the 880 * If control arrives here, we're doing a "raw" read. Send the
835 * command to read the conventional OOB and read it. 881 * command to read the conventional OOB and read it.
836 */ 882 */
837 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page); 883 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
838 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize); 884 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
839 } else { 885 } else {
840 /* 886 /*
841 * If control arrives here, we're not doing a "raw" read. Fill 887 * If control arrives here, we're not doing a "raw" read. Fill
842 * the OOB buffer with set bits and correct the block mark. 888 * the OOB buffer with set bits and correct the block mark.
843 */ 889 */
844 memset(nand->oob_poi, 0xff, mtd->oobsize); 890 memset(nand->oob_poi, 0xff, mtd->oobsize);
845 891
846 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page); 892 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
847 mxs_nand_read_buf(mtd, nand->oob_poi, 1); 893 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
848 } 894 }
849 895
850 return 0; 896 return 0;
851 897
852 } 898 }
853 899
854 /* 900 /*
855 * Write OOB data to NAND. 901 * Write OOB data to NAND.
856 */ 902 */
857 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand, 903 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
858 int page) 904 int page)
859 { 905 {
860 struct mxs_nand_info *nand_info = nand->priv; 906 struct mxs_nand_info *nand_info = nand->priv;
861 uint8_t block_mark = 0; 907 uint8_t block_mark = 0;
862 908
863 /* 909 /*
864 * There are fundamental incompatibilities between the i.MX GPMI NFC and 910 * There are fundamental incompatibilities between the i.MX GPMI NFC and
865 * the NAND Flash MTD model that make it essentially impossible to write 911 * the NAND Flash MTD model that make it essentially impossible to write
866 * the out-of-band bytes. 912 * the out-of-band bytes.
867 * 913 *
868 * We permit *ONE* exception. If the *intent* of writing the OOB is to 914 * We permit *ONE* exception. If the *intent* of writing the OOB is to
869 * mark a block bad, we can do that. 915 * mark a block bad, we can do that.
870 */ 916 */
871 917
872 if (!nand_info->marking_block_bad) { 918 if (!nand_info->marking_block_bad) {
873 printf("NXS NAND: Writing OOB isn't supported\n"); 919 printf("NXS NAND: Writing OOB isn't supported\n");
874 return -EIO; 920 return -EIO;
875 } 921 }
876 922
877 /* Write the block mark. */ 923 /* Write the block mark. */
878 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); 924 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
879 nand->write_buf(mtd, &block_mark, 1); 925 nand->write_buf(mtd, &block_mark, 1);
880 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 926 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
881 927
882 /* Check if it worked. */ 928 /* Check if it worked. */
883 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL) 929 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
884 return -EIO; 930 return -EIO;
885 931
886 return 0; 932 return 0;
887 } 933 }
888 934
889 /* 935 /*
890 * Claims all blocks are good. 936 * Claims all blocks are good.
891 * 937 *
892 * In principle, this function is *only* called when the NAND Flash MTD system 938 * In principle, this function is *only* called when the NAND Flash MTD system
893 * isn't allowed to keep an in-memory bad block table, so it is forced to ask 939 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
894 * the driver for bad block information. 940 * the driver for bad block information.
895 * 941 *
896 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so 942 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
897 * this function is *only* called when we take it away. 943 * this function is *only* called when we take it away.
898 * 944 *
899 * Thus, this function is only called when we want *all* blocks to look good, 945 * Thus, this function is only called when we want *all* blocks to look good,
900 * so it *always* return success. 946 * so it *always* return success.
901 */ 947 */
902 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) 948 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
903 { 949 {
904 return 0; 950 return 0;
905 } 951 }
906 952
907 /* 953 /*
908 * Nominally, the purpose of this function is to look for or create the bad 954 * Nominally, the purpose of this function is to look for or create the bad
909 * block table. In fact, since the we call this function at the very end of 955 * block table. In fact, since the we call this function at the very end of
910 * the initialization process started by nand_scan(), and we doesn't have a 956 * the initialization process started by nand_scan(), and we doesn't have a
911 * more formal mechanism, we "hook" this function to continue init process. 957 * more formal mechanism, we "hook" this function to continue init process.
912 * 958 *
913 * At this point, the physical NAND Flash chips have been identified and 959 * At this point, the physical NAND Flash chips have been identified and
914 * counted, so we know the physical geometry. This enables us to make some 960 * counted, so we know the physical geometry. This enables us to make some
915 * important configuration decisions. 961 * important configuration decisions.
916 * 962 *
917 * The return value of this function propogates directly back to this driver's 963 * The return value of this function propogates directly back to this driver's
918 * call to nand_scan(). Anything other than zero will cause this driver to 964 * call to nand_scan(). Anything other than zero will cause this driver to
919 * tear everything down and declare failure. 965 * tear everything down and declare failure.
920 */ 966 */
921 static int mxs_nand_scan_bbt(struct mtd_info *mtd) 967 static int mxs_nand_scan_bbt(struct mtd_info *mtd)
922 { 968 {
923 struct nand_chip *nand = mtd->priv; 969 struct nand_chip *nand = mtd->priv;
924 struct mxs_nand_info *nand_info = nand->priv; 970 struct mxs_nand_info *nand_info = nand->priv;
925 struct mx28_bch_regs *bch_regs = (struct mx28_bch_regs *)MXS_BCH_BASE; 971 struct mx28_bch_regs *bch_regs = (struct mx28_bch_regs *)MXS_BCH_BASE;
926 uint32_t tmp; 972 uint32_t tmp;
927 973
928 /* Configure BCH and set NFC geometry */ 974 /* Configure BCH and set NFC geometry */
929 mx28_reset_block(&bch_regs->hw_bch_ctrl_reg); 975 mx28_reset_block(&bch_regs->hw_bch_ctrl_reg);
930 976
931 /* Configure layout 0 */ 977 /* Configure layout 0 */
932 tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1) 978 tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
933 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET; 979 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
934 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET; 980 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
935 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1) 981 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
936 << BCH_FLASHLAYOUT0_ECC0_OFFSET; 982 << BCH_FLASHLAYOUT0_ECC0_OFFSET;
937 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE; 983 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
938 writel(tmp, &bch_regs->hw_bch_flash0layout0); 984 writel(tmp, &bch_regs->hw_bch_flash0layout0);
939 985
940 tmp = (mtd->writesize + mtd->oobsize) 986 tmp = (mtd->writesize + mtd->oobsize)
941 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET; 987 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
942 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1) 988 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
943 << BCH_FLASHLAYOUT1_ECCN_OFFSET; 989 << BCH_FLASHLAYOUT1_ECCN_OFFSET;
944 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE; 990 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
945 writel(tmp, &bch_regs->hw_bch_flash0layout1); 991 writel(tmp, &bch_regs->hw_bch_flash0layout1);
946 992
947 /* Set *all* chip selects to use layout 0 */ 993 /* Set *all* chip selects to use layout 0 */
948 writel(0, &bch_regs->hw_bch_layoutselect); 994 writel(0, &bch_regs->hw_bch_layoutselect);
949 995
950 /* Enable BCH complete interrupt */ 996 /* Enable BCH complete interrupt */
951 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set); 997 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
952 998
953 /* Hook some operations at the MTD level. */ 999 /* Hook some operations at the MTD level. */
954 if (mtd->read_oob != mxs_nand_hook_read_oob) { 1000 if (mtd->read_oob != mxs_nand_hook_read_oob) {
955 nand_info->hooked_read_oob = mtd->read_oob; 1001 nand_info->hooked_read_oob = mtd->read_oob;
956 mtd->read_oob = mxs_nand_hook_read_oob; 1002 mtd->read_oob = mxs_nand_hook_read_oob;
957 } 1003 }
958 1004
959 if (mtd->write_oob != mxs_nand_hook_write_oob) { 1005 if (mtd->write_oob != mxs_nand_hook_write_oob) {
960 nand_info->hooked_write_oob = mtd->write_oob; 1006 nand_info->hooked_write_oob = mtd->write_oob;
961 mtd->write_oob = mxs_nand_hook_write_oob; 1007 mtd->write_oob = mxs_nand_hook_write_oob;
962 } 1008 }
963 1009
964 if (mtd->block_markbad != mxs_nand_hook_block_markbad) { 1010 if (mtd->block_markbad != mxs_nand_hook_block_markbad) {
965 nand_info->hooked_block_markbad = mtd->block_markbad; 1011 nand_info->hooked_block_markbad = mtd->block_markbad;
966 mtd->block_markbad = mxs_nand_hook_block_markbad; 1012 mtd->block_markbad = mxs_nand_hook_block_markbad;
967 } 1013 }
968 1014
969 /* We use the reference implementation for bad block management. */ 1015 /* We use the reference implementation for bad block management. */
970 return nand_default_bbt(mtd); 1016 return nand_default_bbt(mtd);
971 } 1017 }
972 1018
973 /* 1019 /*
974 * Allocate DMA buffers 1020 * Allocate DMA buffers
975 */ 1021 */
976 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info) 1022 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
977 { 1023 {
978 uint8_t *buf; 1024 uint8_t *buf;
979 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE; 1025 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
980 1026
1027 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1028
981 /* DMA buffers */ 1029 /* DMA buffers */
982 buf = memalign(MXS_DMA_ALIGNMENT, size); 1030 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
983 if (!buf) { 1031 if (!buf) {
984 printf("MXS NAND: Error allocating DMA buffers\n"); 1032 printf("MXS NAND: Error allocating DMA buffers\n");
985 return -ENOMEM; 1033 return -ENOMEM;
986 } 1034 }
987 1035
988 memset(buf, 0, size); 1036 memset(buf, 0, nand_info->data_buf_size);
989 1037
990 nand_info->data_buf = buf; 1038 nand_info->data_buf = buf;
991 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE; 1039 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
992
993 /* Command buffers */ 1040 /* Command buffers */
994 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT, 1041 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
995 MXS_NAND_COMMAND_BUFFER_SIZE); 1042 MXS_NAND_COMMAND_BUFFER_SIZE);
996 if (!nand_info->cmd_buf) { 1043 if (!nand_info->cmd_buf) {
997 free(buf); 1044 free(buf);
998 printf("MXS NAND: Error allocating command buffers\n"); 1045 printf("MXS NAND: Error allocating command buffers\n");
999 return -ENOMEM; 1046 return -ENOMEM;
1000 } 1047 }
1001 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE); 1048 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1002 nand_info->cmd_queue_len = 0; 1049 nand_info->cmd_queue_len = 0;
1003 1050
1004 return 0; 1051 return 0;
1005 } 1052 }
1006 1053
1007 /* 1054 /*
1008 * Initializes the NFC hardware. 1055 * Initializes the NFC hardware.
1009 */ 1056 */
1010 int mxs_nand_init(struct mxs_nand_info *info) 1057 int mxs_nand_init(struct mxs_nand_info *info)
1011 { 1058 {
1012 struct mx28_gpmi_regs *gpmi_regs = 1059 struct mx28_gpmi_regs *gpmi_regs =
1013 (struct mx28_gpmi_regs *)MXS_GPMI_BASE; 1060 (struct mx28_gpmi_regs *)MXS_GPMI_BASE;
1014 int i = 0; 1061 int i = 0;
1015 1062
1016 info->desc = malloc(sizeof(struct mxs_dma_desc *) * 1063 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1017 MXS_NAND_DMA_DESCRIPTOR_COUNT); 1064 MXS_NAND_DMA_DESCRIPTOR_COUNT);
1018 if (!info->desc) 1065 if (!info->desc)
1019 goto err1; 1066 goto err1;
1020 1067
1021 /* Allocate the DMA descriptors. */ 1068 /* Allocate the DMA descriptors. */
1022 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) { 1069 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1023 info->desc[i] = mxs_dma_desc_alloc(); 1070 info->desc[i] = mxs_dma_desc_alloc();
1024 if (!info->desc[i]) 1071 if (!info->desc[i])
1025 goto err2; 1072 goto err2;
1026 } 1073 }
1027 1074
1028 /* Init the DMA controller. */ 1075 /* Init the DMA controller. */
1029 mxs_dma_init(); 1076 mxs_dma_init();
1030 1077
1031 /* Reset the GPMI block. */ 1078 /* Reset the GPMI block. */
1032 mx28_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg); 1079 mx28_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
1033 1080
1034 /* 1081 /*
1035 * Choose NAND mode, set IRQ polarity, disable write protection and 1082 * Choose NAND mode, set IRQ polarity, disable write protection and
1036 * select BCH ECC. 1083 * select BCH ECC.
1037 */ 1084 */
1038 clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1, 1085 clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
1039 GPMI_CTRL1_GPMI_MODE, 1086 GPMI_CTRL1_GPMI_MODE,
1040 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET | 1087 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
1041 GPMI_CTRL1_BCH_MODE); 1088 GPMI_CTRL1_BCH_MODE);
1042 1089
1043 return 0; 1090 return 0;
1044 1091
1045 err2: 1092 err2:
1046 free(info->desc); 1093 free(info->desc);
1047 err1: 1094 err1:
1048 for (--i; i >= 0; i--) 1095 for (--i; i >= 0; i--)
1049 mxs_dma_desc_free(info->desc[i]); 1096 mxs_dma_desc_free(info->desc[i]);
1050 printf("MXS NAND: Unable to allocate DMA descriptors\n"); 1097 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1051 return -ENOMEM; 1098 return -ENOMEM;
1052 } 1099 }
1053 1100
1054 /*! 1101 /*!
1055 * This function is called during the driver binding process. 1102 * This function is called during the driver binding process.
1056 * 1103 *
1057 * @param pdev the device structure used to store device specific 1104 * @param pdev the device structure used to store device specific
1058 * information that is used by the suspend, resume and 1105 * information that is used by the suspend, resume and
1059 * remove functions 1106 * remove functions
1060 * 1107 *
1061 * @return The function always returns 0. 1108 * @return The function always returns 0.
1062 */ 1109 */
1063 int board_nand_init(struct nand_chip *nand) 1110 int board_nand_init(struct nand_chip *nand)
1064 { 1111 {
1065 struct mxs_nand_info *nand_info; 1112 struct mxs_nand_info *nand_info;
1066 int err; 1113 int err;
1067 1114
1068 nand_info = malloc(sizeof(struct mxs_nand_info)); 1115 nand_info = malloc(sizeof(struct mxs_nand_info));
1069 if (!nand_info) { 1116 if (!nand_info) {
1070 printf("MXS NAND: Failed to allocate private data\n"); 1117 printf("MXS NAND: Failed to allocate private data\n");
1071 return -ENOMEM; 1118 return -ENOMEM;
1072 } 1119 }
1073 memset(nand_info, 0, sizeof(struct mxs_nand_info)); 1120 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1074 1121
1075 err = mxs_nand_alloc_buffers(nand_info); 1122 err = mxs_nand_alloc_buffers(nand_info);
1076 if (err) 1123 if (err)
1077 goto err1; 1124 goto err1;
1078 1125
1079 err = mxs_nand_init(nand_info); 1126 err = mxs_nand_init(nand_info);
1080 if (err) 1127 if (err)
1081 goto err2; 1128 goto err2;
1082 1129
1083 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout)); 1130 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1084 1131
1085 nand->priv = nand_info; 1132 nand->priv = nand_info;
1086 nand->options |= NAND_NO_SUBPAGE_WRITE; 1133 nand->options |= NAND_NO_SUBPAGE_WRITE;
1087 1134
1088 nand->cmd_ctrl = mxs_nand_cmd_ctrl; 1135 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1089 1136
1090 nand->dev_ready = mxs_nand_device_ready; 1137 nand->dev_ready = mxs_nand_device_ready;
1091 nand->select_chip = mxs_nand_select_chip; 1138 nand->select_chip = mxs_nand_select_chip;
1092 nand->block_bad = mxs_nand_block_bad; 1139 nand->block_bad = mxs_nand_block_bad;
1093 nand->scan_bbt = mxs_nand_scan_bbt; 1140 nand->scan_bbt = mxs_nand_scan_bbt;
1094 1141
1095 nand->read_byte = mxs_nand_read_byte; 1142 nand->read_byte = mxs_nand_read_byte;
1096 1143
1097 nand->read_buf = mxs_nand_read_buf; 1144 nand->read_buf = mxs_nand_read_buf;
1098 nand->write_buf = mxs_nand_write_buf; 1145 nand->write_buf = mxs_nand_write_buf;
1099 1146
1100 nand->ecc.read_page = mxs_nand_ecc_read_page; 1147 nand->ecc.read_page = mxs_nand_ecc_read_page;
1101 nand->ecc.write_page = mxs_nand_ecc_write_page; 1148 nand->ecc.write_page = mxs_nand_ecc_write_page;
1102 nand->ecc.read_oob = mxs_nand_ecc_read_oob; 1149 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1103 nand->ecc.write_oob = mxs_nand_ecc_write_oob; 1150 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1104 1151
1105 nand->ecc.layout = &fake_ecc_layout; 1152 nand->ecc.layout = &fake_ecc_layout;
1106 nand->ecc.mode = NAND_ECC_HW; 1153 nand->ecc.mode = NAND_ECC_HW;
1107 nand->ecc.bytes = 9; 1154 nand->ecc.bytes = 9;
1108 nand->ecc.size = 512; 1155 nand->ecc.size = 512;
1109 1156
1110 return 0; 1157 return 0;
1111 1158
1112 err2: 1159 err2:
1113 free(nand_info->data_buf); 1160 free(nand_info->data_buf);
1114 free(nand_info->cmd_buf); 1161 free(nand_info->cmd_buf);
1115 err1: 1162 err1:
1116 free(nand_info); 1163 free(nand_info);
1117 return err; 1164 return err;
1118 } 1165 }