Eric Lee / smarc-uboot

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Commit 6baaad39acc031cdb93a5e5a68a26c3fbc25c88f

Authored by Haibo Chen
1 parent b68f4a1fc4
Exists in smarc-imx-l5.0.0_1.0.0-ga

MLK-10215 Add elan init in i.MX6SL-EVK board 

EPDC board contain a elan touch screen, this screen is a i2c
slave. If this EPDC board connect to i.MX6SL-EVK board, after
uboot boot up, if we do i2c operation, like i2c probe, then
the i2c bus block. This is due to the elan touch screen i2c slave.
This device needs to do some initialization opearation before its
i2c operation, otherwise this i2c device pull down the i2c clk line,
and make the i2c bus hang. This means elan needs a special flow on
i2c before its address is acked, otherwise the i2c bus will be hang.

This patch is a workaround, it add a void function which is defined
as a weak symbol in i2c driver, and it is called before every i2c
operation. In mx6slevk, this function was overwrite to execute elan
initialization. So that, for mx6slevk board, it will  initialize
elan before every i2c operation, but for other boards, it just work
as before.

Signed-off-by: Haibo Chen <haibo.chen@freescale.com>

Showing 3 changed files with 56 additions and 1 deletions Inline Diff

arch/arm/include/asm/arch-mx6/mx6sl_pins.h
Diff comments   View file @ 6baaad3
1 /* 1 /*
2 * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. All Rights Reserved.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __ASM_ARCH_MX6_MX6SL_PINS_H__ 7 #ifndef __ASM_ARCH_MX6_MX6SL_PINS_H__
8 #define __ASM_ARCH_MX6_MX6SL_PINS_H__ 8 #define __ASM_ARCH_MX6_MX6SL_PINS_H__
9 9
10 #include <asm/imx-common/iomux-v3.h> 10 #include <asm/imx-common/iomux-v3.h>
11 11
12 enum { 12 enum {
13 MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, 0), 13 MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, 0),
14 MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, 0), 14 MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, 0),
15 MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, 0), 15 MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, 0),
16 MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, 0), 16 MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, 0),
17 MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, 0), 17 MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, 0),
18 MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0), 18 MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0),
19 MX6_PAD_SD1_DAT4__USDHC1_DAT4 = IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0), 19 MX6_PAD_SD1_DAT4__USDHC1_DAT4 = IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0),
20 MX6_PAD_SD1_DAT5__USDHC1_DAT5 = IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0), 20 MX6_PAD_SD1_DAT5__USDHC1_DAT5 = IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0),
21 MX6_PAD_SD1_DAT6__USDHC1_DAT6 = IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0), 21 MX6_PAD_SD1_DAT6__USDHC1_DAT6 = IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0),
22 MX6_PAD_SD1_DAT7__USDHC1_DAT7 = IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0), 22 MX6_PAD_SD1_DAT7__USDHC1_DAT7 = IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0),
23 MX6_PAD_KEY_ROW7__GPIO_4_7 = IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0), 23 MX6_PAD_KEY_ROW7__GPIO_4_7 = IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0),
24 24
25 MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0), 25 MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0),
26 MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0), 26 MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0),
27 MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0), 27 MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0),
28 MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0), 28 MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
29 MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0), 29 MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
30 MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0), 30 MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
31 MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0), 31 MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0),
32 32
33 MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0), 33 MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0),
34 MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0), 34 MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0),
35 MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0), 35 MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0),
36 MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, 0), 36 MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, 0),
37 MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, 0), 37 MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, 0),
38 MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, 0), 38 MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, 0),
39 MX6_PAD_REF_CLK_32K__GPIO_3_22 = IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, 0), 39 MX6_PAD_REF_CLK_32K__GPIO_3_22 = IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, 0),
40 40
41 MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0), 41 MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0),
42 MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0), 42 MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0),
43 43
44 MX6_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x41c, 0x12c, 0, 0x000, 0, 0), 44 MX6_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x41c, 0x12c, 0, 0x000, 0, 0),
45 MX6_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x420, 0x130, 0, 0x6f4, 1, 0), 45 MX6_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x420, 0x130, 0, 0x6f4, 1, 0),
46 MX6_PAD_FEC_CRS_DV__FEC_RX_DV = IOMUX_PAD(0x418, 0x128, 0, 0x704, 1, 0), 46 MX6_PAD_FEC_CRS_DV__FEC_RX_DV = IOMUX_PAD(0x418, 0x128, 0, 0x704, 1, 0),
47 MX6_PAD_FEC_RXD0__FEC_RX_DATA0 = IOMUX_PAD(0x42c, 0x13c, 0, 0x6f8, 0, 0), 47 MX6_PAD_FEC_RXD0__FEC_RX_DATA0 = IOMUX_PAD(0x42c, 0x13c, 0, 0x6f8, 0, 0),
48 MX6_PAD_FEC_RXD1__FEC_RX_DATA1 = IOMUX_PAD(0x430, 0x140, 0, 0x6fc, 1, 0), 48 MX6_PAD_FEC_RXD1__FEC_RX_DATA1 = IOMUX_PAD(0x430, 0x140, 0, 0x6fc, 1, 0),
49 MX6_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x438, 0x148, 0, 0x000, 0, 0), 49 MX6_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x438, 0x148, 0, 0x000, 0, 0),
50 MX6_PAD_FEC_TXD0__FEC_TX_DATA0 = IOMUX_PAD(0x43c, 0x14c, 0, 0x000, 0, 0), 50 MX6_PAD_FEC_TXD0__FEC_TX_DATA0 = IOMUX_PAD(0x43c, 0x14c, 0, 0x000, 0, 0),
51 MX6_PAD_FEC_TXD1__FEC_TX_DATA1 = IOMUX_PAD(0x440, 0x150, 0, 0x000, 0, 0), 51 MX6_PAD_FEC_TXD1__FEC_TX_DATA1 = IOMUX_PAD(0x440, 0x150, 0, 0x000, 0, 0),
52 MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0), 52 MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
53 MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0), 53 MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
54 MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0), 54 MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
55 55
56 MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0), 56 MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0),
57 MX6_PAD_I2C1_SDA__GPIO_3_13 = IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0), 57 MX6_PAD_I2C1_SDA__GPIO_3_13 = IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0),
58 MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0), 58 MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0),
59 MX6_PAD_I2C1_SCL__GPIO_3_12 = IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0), 59 MX6_PAD_I2C1_SCL__GPIO_3_12 = IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0),
60 60 MX6_PAD_EPDC_PWRCTRL2__GPIO_2_9 = IOMUX_PAD(0x03DC, 0x00EC, 5, 0x0000, 0, 0),
61 MX6_PAD_EPDC_PWRCTRL3__GPIO_2_10 = IOMUX_PAD(0x03E0, 0x00F0, 5, 0x0000, 0, 0),
61 MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 = IOMUX_PAD(0x03E8, 0x00F8, 5, 0x0000, 0, 0), 62 MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 = IOMUX_PAD(0x03E8, 0x00F8, 5, 0x0000, 0, 0),
62 MX6_PAD_EPDC_VCOM0__GPIO_2_3 = IOMUX_PAD(0x0410, 0x0120, 5, 0x0000, 0, 0), 63 MX6_PAD_EPDC_VCOM0__GPIO_2_3 = IOMUX_PAD(0x0410, 0x0120, 5, 0x0000, 0, 0),
63 MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 = IOMUX_PAD(0x03EC, 0x00FC, 5, 0x0000, 0, 0), 64 MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 = IOMUX_PAD(0x03EC, 0x00FC, 5, 0x0000, 0, 0),
64 MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 = IOMUX_PAD(0x03D4, 0x00E4, 5, 0x0000, 0, 0), 65 MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 = IOMUX_PAD(0x03D4, 0x00E4, 5, 0x0000, 0, 0),
65 MX6_PAD_EPDC_D0__EPDC_SDDO_0 = IOMUX_PAD(0x0380, 0x0090, 0, 0x0000, 0, 0), 66 MX6_PAD_EPDC_D0__EPDC_SDDO_0 = IOMUX_PAD(0x0380, 0x0090, 0, 0x0000, 0, 0),
66 MX6_PAD_EPDC_D1__EPDC_SDDO_1 = IOMUX_PAD(0x0384, 0x0094, 0, 0x0000, 0, 0), 67 MX6_PAD_EPDC_D1__EPDC_SDDO_1 = IOMUX_PAD(0x0384, 0x0094, 0, 0x0000, 0, 0),
67 MX6_PAD_EPDC_D2__EPDC_SDDO_2 = IOMUX_PAD(0x03A0, 0x00B0, 0, 0x0000, 0, 0), 68 MX6_PAD_EPDC_D2__EPDC_SDDO_2 = IOMUX_PAD(0x03A0, 0x00B0, 0, 0x0000, 0, 0),
68 MX6_PAD_EPDC_D3__EPDC_SDDO_3 = IOMUX_PAD(0x03A4, 0x00B4, 0, 0x0000, 0, 0), 69 MX6_PAD_EPDC_D3__EPDC_SDDO_3 = IOMUX_PAD(0x03A4, 0x00B4, 0, 0x0000, 0, 0),
69 MX6_PAD_EPDC_D4__EPDC_SDDO_4 = IOMUX_PAD(0x03A8, 0x00B8, 0, 0x0000, 0, 0), 70 MX6_PAD_EPDC_D4__EPDC_SDDO_4 = IOMUX_PAD(0x03A8, 0x00B8, 0, 0x0000, 0, 0),
70 MX6_PAD_EPDC_D5__EPDC_SDDO_5 = IOMUX_PAD(0x03AC, 0x00BC, 0, 0x0000, 0, 0), 71 MX6_PAD_EPDC_D5__EPDC_SDDO_5 = IOMUX_PAD(0x03AC, 0x00BC, 0, 0x0000, 0, 0),
71 MX6_PAD_EPDC_D6__EPDC_SDDO_6 = IOMUX_PAD(0x03B0, 0x00C0, 0, 0x0000, 0, 0), 72 MX6_PAD_EPDC_D6__EPDC_SDDO_6 = IOMUX_PAD(0x03B0, 0x00C0, 0, 0x0000, 0, 0),
72 MX6_PAD_EPDC_D7__EPDC_SDDO_7 = IOMUX_PAD(0x03B4, 0x00C4, 0, 0x0000, 0, 0), 73 MX6_PAD_EPDC_D7__EPDC_SDDO_7 = IOMUX_PAD(0x03B4, 0x00C4, 0, 0x0000, 0, 0),
73 MX6_PAD_EPDC_GDCLK__EPDC_GDCLK = IOMUX_PAD(0x03C0, 0x00D0, 0, 0x0000, 0, 0), 74 MX6_PAD_EPDC_GDCLK__EPDC_GDCLK = IOMUX_PAD(0x03C0, 0x00D0, 0, 0x0000, 0, 0),
74 MX6_PAD_EPDC_GDSP__EPDC_GDSP = IOMUX_PAD(0x03CC, 0x00DC, 0, 0x0000, 0, 0), 75 MX6_PAD_EPDC_GDSP__EPDC_GDSP = IOMUX_PAD(0x03CC, 0x00DC, 0, 0x0000, 0, 0),
75 MX6_PAD_EPDC_GDOE__EPDC_GDOE = IOMUX_PAD(0x03C4, 0x00D4, 0, 0x0000, 0, 0), 76 MX6_PAD_EPDC_GDOE__EPDC_GDOE = IOMUX_PAD(0x03C4, 0x00D4, 0, 0x0000, 0, 0),
76 MX6_PAD_EPDC_GDRL__EPDC_GDRL = IOMUX_PAD(0x03C8, 0x00D8, 0, 0x0000, 0, 0), 77 MX6_PAD_EPDC_GDRL__EPDC_GDRL = IOMUX_PAD(0x03C8, 0x00D8, 0, 0x0000, 0, 0),
77 MX6_PAD_EPDC_SDCLK__EPDC_SDCLK = IOMUX_PAD(0x0400, 0x0110, 0, 0x0000, 0, 0), 78 MX6_PAD_EPDC_SDCLK__EPDC_SDCLK = IOMUX_PAD(0x0400, 0x0110, 0, 0x0000, 0, 0),
78 MX6_PAD_EPDC_SDOE__EPDC_SDOE = IOMUX_PAD(0x0408, 0x0118, 0, 0x0000, 0, 0), 79 MX6_PAD_EPDC_SDOE__EPDC_SDOE = IOMUX_PAD(0x0408, 0x0118, 0, 0x0000, 0, 0),
79 MX6_PAD_EPDC_SDLE__EPDC_SDLE = IOMUX_PAD(0x0404, 0x0114, 0, 0x0000, 0, 0), 80 MX6_PAD_EPDC_SDLE__EPDC_SDLE = IOMUX_PAD(0x0404, 0x0114, 0, 0x0000, 0, 0),
80 MX6_PAD_EPDC_SDSHR__EPDC_SDSHR = IOMUX_PAD(0x040C, 0x011C, 0, 0x0000, 0, 0), 81 MX6_PAD_EPDC_SDSHR__EPDC_SDSHR = IOMUX_PAD(0x040C, 0x011C, 0, 0x0000, 0, 0),
81 MX6_PAD_EPDC_BDR0__EPDC_BDR_0 = IOMUX_PAD(0x0378, 0x0088, 0, 0x0000, 0, 0), 82 MX6_PAD_EPDC_BDR0__EPDC_BDR_0 = IOMUX_PAD(0x0378, 0x0088, 0, 0x0000, 0, 0),
82 MX6_PAD_EPDC_SDCE0__EPDC_SDCE_0 = IOMUX_PAD(0x03F0, 0x0100, 0, 0x0000, 0, 0), 83 MX6_PAD_EPDC_SDCE0__EPDC_SDCE_0 = IOMUX_PAD(0x03F0, 0x0100, 0, 0x0000, 0, 0),
83 MX6_PAD_EPDC_SDCE1__EPDC_SDCE_1 = IOMUX_PAD(0x03F4, 0x0104, 0, 0x0000, 0, 0), 84 MX6_PAD_EPDC_SDCE1__EPDC_SDCE_1 = IOMUX_PAD(0x03F4, 0x0104, 0, 0x0000, 0, 0),
84 MX6_PAD_EPDC_SDCE2__EPDC_SDCE_2 = IOMUX_PAD(0x03F8, 0x0108, 0, 0x0000, 0, 0), 85 MX6_PAD_EPDC_SDCE2__EPDC_SDCE_2 = IOMUX_PAD(0x03F8, 0x0108, 0, 0x0000, 0, 0),
85 MX6_PAD_EPDC_D0__GPIO_1_7 = IOMUX_PAD(0x0380, 0x0090, 5, 0x0000, 0, 0), 86 MX6_PAD_EPDC_D0__GPIO_1_7 = IOMUX_PAD(0x0380, 0x0090, 5, 0x0000, 0, 0),
86 MX6_PAD_EPDC_D1__GPIO_1_8 = IOMUX_PAD(0x0384, 0x0094, 5, 0x0000, 0, 0), 87 MX6_PAD_EPDC_D1__GPIO_1_8 = IOMUX_PAD(0x0384, 0x0094, 5, 0x0000, 0, 0),
87 MX6_PAD_EPDC_D2__GPIO_1_9 = IOMUX_PAD(0x03A0, 0x00B0, 5, 0x0000, 0, 0), 88 MX6_PAD_EPDC_D2__GPIO_1_9 = IOMUX_PAD(0x03A0, 0x00B0, 5, 0x0000, 0, 0),
88 MX6_PAD_EPDC_D3__GPIO_1_10 = IOMUX_PAD(0x03A4, 0x00B4, 5, 0x0000, 0, 0), 89 MX6_PAD_EPDC_D3__GPIO_1_10 = IOMUX_PAD(0x03A4, 0x00B4, 5, 0x0000, 0, 0),
89 MX6_PAD_EPDC_D4__GPIO_1_11 = IOMUX_PAD(0x03A8, 0x00B8, 5, 0x0000, 0, 0), 90 MX6_PAD_EPDC_D4__GPIO_1_11 = IOMUX_PAD(0x03A8, 0x00B8, 5, 0x0000, 0, 0),
90 MX6_PAD_EPDC_D5__GPIO_1_12 = IOMUX_PAD(0x03AC, 0x00BC, 5, 0x0000, 0, 0), 91 MX6_PAD_EPDC_D5__GPIO_1_12 = IOMUX_PAD(0x03AC, 0x00BC, 5, 0x0000, 0, 0),
91 MX6_PAD_EPDC_D6__GPIO_1_13 = IOMUX_PAD(0x03B0, 0x00C0, 5, 0x0000, 0, 0), 92 MX6_PAD_EPDC_D6__GPIO_1_13 = IOMUX_PAD(0x03B0, 0x00C0, 5, 0x0000, 0, 0),
92 MX6_PAD_EPDC_D7__GPIO_1_14 = IOMUX_PAD(0x03B4, 0x00C4, 5, 0x0000, 0, 0), 93 MX6_PAD_EPDC_D7__GPIO_1_14 = IOMUX_PAD(0x03B4, 0x00C4, 5, 0x0000, 0, 0),
93 MX6_PAD_EPDC_GDCLK__GPIO_1_31 = IOMUX_PAD(0x03C0, 0x00D0, 5, 0x0000, 0, 0), 94 MX6_PAD_EPDC_GDCLK__GPIO_1_31 = IOMUX_PAD(0x03C0, 0x00D0, 5, 0x0000, 0, 0),
94 MX6_PAD_EPDC_GDSP__GPIO_2_2 = IOMUX_PAD(0x03CC, 0x00DC, 5, 0x0000, 0, 0), 95 MX6_PAD_EPDC_GDSP__GPIO_2_2 = IOMUX_PAD(0x03CC, 0x00DC, 5, 0x0000, 0, 0),
95 MX6_PAD_EPDC_GDOE__GPIO_2_0 = IOMUX_PAD(0x03C4, 0x00D4, 5, 0x0000, 0, 0), 96 MX6_PAD_EPDC_GDOE__GPIO_2_0 = IOMUX_PAD(0x03C4, 0x00D4, 5, 0x0000, 0, 0),
96 MX6_PAD_EPDC_GDRL__GPIO_2_1 = IOMUX_PAD(0x03C8, 0x00D8, 5, 0x0000, 0, 0), 97 MX6_PAD_EPDC_GDRL__GPIO_2_1 = IOMUX_PAD(0x03C8, 0x00D8, 5, 0x0000, 0, 0),
97 MX6_PAD_EPDC_SDCLK__GPIO_1_23 = IOMUX_PAD(0x0400, 0x0110, 5, 0x0000, 0, 0), 98 MX6_PAD_EPDC_SDCLK__GPIO_1_23 = IOMUX_PAD(0x0400, 0x0110, 5, 0x0000, 0, 0),
98 MX6_PAD_EPDC_SDOE__GPIO_1_25 = IOMUX_PAD(0x0408, 0x0118, 5, 0x0000, 0, 0), 99 MX6_PAD_EPDC_SDOE__GPIO_1_25 = IOMUX_PAD(0x0408, 0x0118, 5, 0x0000, 0, 0),
99 MX6_PAD_EPDC_SDLE__GPIO_1_24 = IOMUX_PAD(0x0404, 0x0114, 5, 0x0000, 0, 0), 100 MX6_PAD_EPDC_SDLE__GPIO_1_24 = IOMUX_PAD(0x0404, 0x0114, 5, 0x0000, 0, 0),
100 MX6_PAD_EPDC_SDSHR__GPIO_1_26 = IOMUX_PAD(0x040C, 0x011C, 5, 0x0000, 0, 0), 101 MX6_PAD_EPDC_SDSHR__GPIO_1_26 = IOMUX_PAD(0x040C, 0x011C, 5, 0x0000, 0, 0),
101 MX6_PAD_EPDC_BDR0__GPIO_2_5 = IOMUX_PAD(0x0378, 0x0088, 5, 0x0000, 0, 0), 102 MX6_PAD_EPDC_BDR0__GPIO_2_5 = IOMUX_PAD(0x0378, 0x0088, 5, 0x0000, 0, 0),
102 MX6_PAD_EPDC_SDCE0__GPIO_1_27 = IOMUX_PAD(0x03F0, 0x0100, 5, 0x0000, 0, 0), 103 MX6_PAD_EPDC_SDCE0__GPIO_1_27 = IOMUX_PAD(0x03F0, 0x0100, 5, 0x0000, 0, 0),
103 MX6_PAD_EPDC_SDCE1__GPIO_1_28 = IOMUX_PAD(0x03F4, 0x0104, 5, 0x0000, 0, 0), 104 MX6_PAD_EPDC_SDCE1__GPIO_1_28 = IOMUX_PAD(0x03F4, 0x0104, 5, 0x0000, 0, 0),
104 MX6_PAD_EPDC_SDCE2__GPIO_1_29 = IOMUX_PAD(0x03F8, 0x0108, 5, 0x0000, 0, 0), 105 MX6_PAD_EPDC_SDCE2__GPIO_1_29 = IOMUX_PAD(0x03F8, 0x0108, 5, 0x0000, 0, 0),
105 MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0), 106 MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0),
106 107
107 MX6_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x0474, 0x016C, 0, 0x0734, 0, 0), 108 MX6_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x0474, 0x016C, 0, 0x0734, 0, 0),
108 MX6_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x0478, 0x0170, 0, 0x0738, 0, 0), 109 MX6_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x0478, 0x0170, 0, 0x0738, 0, 0),
109 MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x047C, 0x0174, 0, 0x073C, 0, 0), 110 MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x047C, 0x0174, 0, 0x073C, 0, 0),
110 MX6_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x0480, 0x0178, 0, 0x0740, 0, 0), 111 MX6_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x0480, 0x0178, 0, 0x0740, 0, 0),
111 MX6_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x0494, 0x018C, 0, 0x0754, 0, 0), 112 MX6_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x0494, 0x018C, 0, 0x0754, 0, 0),
112 MX6_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x0498, 0x0190, 0, 0x0758, 0, 0), 113 MX6_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x0498, 0x0190, 0, 0x0758, 0, 0),
113 MX6_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x049C, 0x0194, 0, 0x075C, 0, 0), 114 MX6_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x049C, 0x0194, 0, 0x075C, 0, 0),
114 MX6_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x04A0, 0x0198, 0, 0x0760, 0, 0), 115 MX6_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x04A0, 0x0198, 0, 0x0760, 0, 0),
115 116
116 MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0), 117 MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0),
117 MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0), 118 MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0),
118 119
120 MX6_PAD_KEY_COL6__GPIO_4_4 = IOMUX_PAD(0x048C, 0x0184, 5, 0x0000, 0, 0),
119 MX6_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0), 121 MX6_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0),
120 MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0), 122 MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0),
121 MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0), 123 MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0),
122 MX6_PAD_ECSPI1_SS0__GPIO_4_11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0), 124 MX6_PAD_ECSPI1_SS0__GPIO_4_11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0),
123 }; 125 };
124 #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */ 126 #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
125 127
board/freescale/mx6slevk/mx6slevk.c
Diff comments   View file @ 6baaad3
1 /* 1 /*
2 * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. 2 * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
3 * 3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #include <asm/arch/clock.h> 9 #include <asm/arch/clock.h>
10 #include <asm/arch/iomux.h> 10 #include <asm/arch/iomux.h>
11 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h> 12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/mx6-pins.h> 13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h> 14 #include <asm/arch/sys_proto.h>
15 #include <asm/gpio.h> 15 #include <asm/gpio.h>
16 #include <asm/imx-common/iomux-v3.h> 16 #include <asm/imx-common/iomux-v3.h>
17 #include <asm/imx-common/boot_mode.h> 17 #include <asm/imx-common/boot_mode.h>
18 #include <asm/io.h> 18 #include <asm/io.h>
19 #include <linux/sizes.h> 19 #include <linux/sizes.h>
20 #include <common.h> 20 #include <common.h>
21 #include <fsl_esdhc.h> 21 #include <fsl_esdhc.h>
22 #include <mmc.h> 22 #include <mmc.h>
23 #include <netdev.h> 23 #include <netdev.h>
24 #ifdef CONFIG_SYS_I2C_MXC 24 #ifdef CONFIG_SYS_I2C_MXC
25 #include <i2c.h> 25 #include <i2c.h>
26 #include <asm/imx-common/mxc_i2c.h> 26 #include <asm/imx-common/mxc_i2c.h>
27 #endif 27 #endif
28 #if defined(CONFIG_MXC_EPDC) 28 #if defined(CONFIG_MXC_EPDC)
29 #include <lcd.h> 29 #include <lcd.h>
30 #include <mxc_epdc_fb.h> 30 #include <mxc_epdc_fb.h>
31 #endif 31 #endif
32 #ifdef CONFIG_FASTBOOT 32 #ifdef CONFIG_FASTBOOT
33 #include <fastboot.h> 33 #include <fastboot.h>
34 #ifdef CONFIG_ANDROID_RECOVERY 34 #ifdef CONFIG_ANDROID_RECOVERY
35 #include <recovery.h> 35 #include <recovery.h>
36 #endif 36 #endif
37 #endif /*CONFIG_FASTBOOT*/ 37 #endif /*CONFIG_FASTBOOT*/
38 38
39 39
40 DECLARE_GLOBAL_DATA_PTR; 40 DECLARE_GLOBAL_DATA_PTR;
41 41
42 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 42 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
43 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 43 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
44 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 44 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45 45
46 #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ 46 #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
47 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 47 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
48 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 48 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
49 49
50 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 50 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
51 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 51 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
52 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 52 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
53 53
54 #define SPI_PAD_CTRL (PAD_CTL_HYS | \ 54 #define SPI_PAD_CTRL (PAD_CTL_HYS | \
55 PAD_CTL_SPEED_MED | \ 55 PAD_CTL_SPEED_MED | \
56 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 56 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
57 57
58 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 58 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
59 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 59 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
60 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 60 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
61 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 61 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
62 62
63 #define ELAN_INTR_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_HYS)
64
63 #define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ 65 #define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
64 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 66 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
65 67
66 #define ETH_PHY_RESET IMX_GPIO_NR(4, 21) 68 #define ETH_PHY_RESET IMX_GPIO_NR(4, 21)
67 69
68 #ifdef CONFIG_SYS_I2C_MXC 70 #ifdef CONFIG_SYS_I2C_MXC
69 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 71 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
70 /* I2C1 for PMIC */ 72 /* I2C1 for PMIC */
71 struct i2c_pads_info i2c_pad_info0 = { 73 struct i2c_pads_info i2c_pad_info0 = {
72 .sda = { 74 .sda = {
73 .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC, 75 .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
74 .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC, 76 .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
75 .gp = IMX_GPIO_NR(3, 13), 77 .gp = IMX_GPIO_NR(3, 13),
76 }, 78 },
77 .scl = { 79 .scl = {
78 .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC, 80 .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
79 .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC, 81 .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
80 .gp = IMX_GPIO_NR(3, 12), 82 .gp = IMX_GPIO_NR(3, 12),
81 }, 83 },
82 }; 84 };
83 #endif 85 #endif
84 86
85 int dram_init(void) 87 int dram_init(void)
86 { 88 {
87 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 89 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
88 90
89 return 0; 91 return 0;
90 } 92 }
91 93
92 static iomux_v3_cfg_t const uart1_pads[] = { 94 static iomux_v3_cfg_t const uart1_pads[] = {
93 MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), 95 MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
94 MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), 96 MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
95 }; 97 };
96 98
97 static iomux_v3_cfg_t const usdhc1_pads[] = { 99 static iomux_v3_cfg_t const usdhc1_pads[] = {
98 /* 8 bit SD */ 100 /* 8 bit SD */
99 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 101 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 102 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101 MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 103 MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 104 MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 105 MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 106 MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 107 MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 108 MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 109 MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 110 MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 111
110 /*CD pin*/ 112 /*CD pin*/
111 MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL), 113 MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
112 }; 114 };
113 115
114 static iomux_v3_cfg_t const usdhc2_pads[] = { 116 static iomux_v3_cfg_t const usdhc2_pads[] = {
115 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 117 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 118 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 119 MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 120 MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 121 MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 122 MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 123
122 /*CD pin*/ 124 /*CD pin*/
123 MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL), 125 MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
124 }; 126 };
125 127
126 static iomux_v3_cfg_t const usdhc3_pads[] = { 128 static iomux_v3_cfg_t const usdhc3_pads[] = {
127 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 129 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 130 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 131 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 132 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 133 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 134 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 135
134 /*CD pin*/ 136 /*CD pin*/
135 MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL), 137 MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
136 }; 138 };
137 139
138 static iomux_v3_cfg_t const fec_pads[] = { 140 static iomux_v3_cfg_t const fec_pads[] = {
139 MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 141 MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
140 MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 142 MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
141 MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL), 143 MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
142 MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 144 MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
143 MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 145 MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
144 MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 146 MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
145 MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 147 MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
146 MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 148 MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
147 MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), 149 MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
148 MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL), 150 MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL),
149 MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL), 151 MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
150 }; 152 };
151 153
154 static iomux_v3_cfg_t const elan_pads[] = {
155 MX6_PAD_EPDC_PWRCTRL2__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
156 MX6_PAD_EPDC_PWRCTRL3__GPIO_2_10 | MUX_PAD_CTRL(ELAN_INTR_PAD_CTRL),
157 MX6_PAD_KEY_COL6__GPIO_4_4 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
158 };
159
152 static iomux_v3_cfg_t const epdc_enable_pads[] = { 160 static iomux_v3_cfg_t const epdc_enable_pads[] = {
153 MX6_PAD_EPDC_D0__EPDC_SDDO_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 161 MX6_PAD_EPDC_D0__EPDC_SDDO_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
154 MX6_PAD_EPDC_D1__EPDC_SDDO_1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 162 MX6_PAD_EPDC_D1__EPDC_SDDO_1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
155 MX6_PAD_EPDC_D2__EPDC_SDDO_2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 163 MX6_PAD_EPDC_D2__EPDC_SDDO_2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
156 MX6_PAD_EPDC_D3__EPDC_SDDO_3 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 164 MX6_PAD_EPDC_D3__EPDC_SDDO_3 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
157 MX6_PAD_EPDC_D4__EPDC_SDDO_4 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 165 MX6_PAD_EPDC_D4__EPDC_SDDO_4 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
158 MX6_PAD_EPDC_D5__EPDC_SDDO_5 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 166 MX6_PAD_EPDC_D5__EPDC_SDDO_5 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
159 MX6_PAD_EPDC_D6__EPDC_SDDO_6 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 167 MX6_PAD_EPDC_D6__EPDC_SDDO_6 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
160 MX6_PAD_EPDC_D7__EPDC_SDDO_7 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 168 MX6_PAD_EPDC_D7__EPDC_SDDO_7 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
161 MX6_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), 169 MX6_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
162 MX6_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), 170 MX6_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),
163 MX6_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), 171 MX6_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
164 MX6_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), 172 MX6_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),
165 MX6_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), 173 MX6_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
166 MX6_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), 174 MX6_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
167 MX6_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), 175 MX6_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
168 MX6_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), 176 MX6_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),
169 MX6_PAD_EPDC_BDR0__EPDC_BDR_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 177 MX6_PAD_EPDC_BDR0__EPDC_BDR_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
170 MX6_PAD_EPDC_SDCE0__EPDC_SDCE_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 178 MX6_PAD_EPDC_SDCE0__EPDC_SDCE_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
171 MX6_PAD_EPDC_SDCE1__EPDC_SDCE_1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 179 MX6_PAD_EPDC_SDCE1__EPDC_SDCE_1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
172 MX6_PAD_EPDC_SDCE2__EPDC_SDCE_2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 180 MX6_PAD_EPDC_SDCE2__EPDC_SDCE_2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
173 }; 181 };
174 182
175 static iomux_v3_cfg_t const epdc_disable_pads[] = { 183 static iomux_v3_cfg_t const epdc_disable_pads[] = {
176 MX6_PAD_EPDC_D0__GPIO_1_7, 184 MX6_PAD_EPDC_D0__GPIO_1_7,
177 MX6_PAD_EPDC_D1__GPIO_1_8, 185 MX6_PAD_EPDC_D1__GPIO_1_8,
178 MX6_PAD_EPDC_D2__GPIO_1_9, 186 MX6_PAD_EPDC_D2__GPIO_1_9,
179 MX6_PAD_EPDC_D3__GPIO_1_10, 187 MX6_PAD_EPDC_D3__GPIO_1_10,
180 MX6_PAD_EPDC_D4__GPIO_1_11, 188 MX6_PAD_EPDC_D4__GPIO_1_11,
181 MX6_PAD_EPDC_D5__GPIO_1_12, 189 MX6_PAD_EPDC_D5__GPIO_1_12,
182 MX6_PAD_EPDC_D6__GPIO_1_13, 190 MX6_PAD_EPDC_D6__GPIO_1_13,
183 MX6_PAD_EPDC_D7__GPIO_1_14, 191 MX6_PAD_EPDC_D7__GPIO_1_14,
184 MX6_PAD_EPDC_GDCLK__GPIO_1_31, 192 MX6_PAD_EPDC_GDCLK__GPIO_1_31,
185 MX6_PAD_EPDC_GDSP__GPIO_2_2, 193 MX6_PAD_EPDC_GDSP__GPIO_2_2,
186 MX6_PAD_EPDC_GDOE__GPIO_2_0, 194 MX6_PAD_EPDC_GDOE__GPIO_2_0,
187 MX6_PAD_EPDC_GDRL__GPIO_2_1, 195 MX6_PAD_EPDC_GDRL__GPIO_2_1,
188 MX6_PAD_EPDC_SDCLK__GPIO_1_23, 196 MX6_PAD_EPDC_SDCLK__GPIO_1_23,
189 MX6_PAD_EPDC_SDOE__GPIO_1_25, 197 MX6_PAD_EPDC_SDOE__GPIO_1_25,
190 MX6_PAD_EPDC_SDLE__GPIO_1_24, 198 MX6_PAD_EPDC_SDLE__GPIO_1_24,
191 MX6_PAD_EPDC_SDSHR__GPIO_1_26, 199 MX6_PAD_EPDC_SDSHR__GPIO_1_26,
192 MX6_PAD_EPDC_BDR0__GPIO_2_5, 200 MX6_PAD_EPDC_BDR0__GPIO_2_5,
193 MX6_PAD_EPDC_SDCE0__GPIO_1_27, 201 MX6_PAD_EPDC_SDCE0__GPIO_1_27,
194 MX6_PAD_EPDC_SDCE1__GPIO_1_28, 202 MX6_PAD_EPDC_SDCE1__GPIO_1_28,
195 MX6_PAD_EPDC_SDCE2__GPIO_1_29, 203 MX6_PAD_EPDC_SDCE2__GPIO_1_29,
196 }; 204 };
197 205
198 static void setup_iomux_uart(void) 206 static void setup_iomux_uart(void)
199 { 207 {
200 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 208 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
201 } 209 }
202 210
203 static void setup_iomux_fec(void) 211 static void setup_iomux_fec(void)
204 { 212 {
205 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); 213 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
206 214
207 /* Reset LAN8720 PHY */ 215 /* Reset LAN8720 PHY */
208 gpio_direction_output(ETH_PHY_RESET , 0); 216 gpio_direction_output(ETH_PHY_RESET , 0);
209 udelay(1000); 217 udelay(1000);
210 gpio_set_value(ETH_PHY_RESET, 1); 218 gpio_set_value(ETH_PHY_RESET, 1);
211 } 219 }
212 220
213 #ifdef CONFIG_SYS_USE_SPINOR 221 #ifdef CONFIG_SYS_USE_SPINOR
214 iomux_v3_cfg_t const ecspi1_pads[] = { 222 iomux_v3_cfg_t const ecspi1_pads[] = {
215 MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 223 MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
216 MX6_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 224 MX6_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
217 MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 225 MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
218 MX6_PAD_ECSPI1_SS0__GPIO_4_11 | MUX_PAD_CTRL(NO_PAD_CTRL), 226 MX6_PAD_ECSPI1_SS0__GPIO_4_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
219 }; 227 };
220 228
221 void setup_spinor(void) 229 void setup_spinor(void)
222 { 230 {
223 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, 231 imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
224 ARRAY_SIZE(ecspi1_pads)); 232 ARRAY_SIZE(ecspi1_pads));
225 gpio_direction_output(IMX_GPIO_NR(4, 11), 0); 233 gpio_direction_output(IMX_GPIO_NR(4, 11), 0);
226 } 234 }
227 #endif 235 #endif
228 236
229 #ifdef CONFIG_FSL_ESDHC 237 #ifdef CONFIG_FSL_ESDHC
230 238
231 #define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7) 239 #define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
232 #define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0) 240 #define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0)
233 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22) 241 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
234 242
235 static struct fsl_esdhc_cfg usdhc_cfg[3] = { 243 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
236 {USDHC1_BASE_ADDR}, 244 {USDHC1_BASE_ADDR},
237 {USDHC2_BASE_ADDR, 0, 4}, 245 {USDHC2_BASE_ADDR, 0, 4},
238 {USDHC3_BASE_ADDR, 0, 4}, 246 {USDHC3_BASE_ADDR, 0, 4},
239 }; 247 };
240 248
241 int mmc_get_env_devno(void) 249 int mmc_get_env_devno(void)
242 { 250 {
243 u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); 251 u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
244 u32 dev_no; 252 u32 dev_no;
245 u32 bootsel; 253 u32 bootsel;
246 254
247 bootsel = (soc_sbmr & 0x000000FF) >> 6 ; 255 bootsel = (soc_sbmr & 0x000000FF) >> 6 ;
248 256
249 /* If not boot from sd/mmc, use default value */ 257 /* If not boot from sd/mmc, use default value */
250 if (bootsel != 1) 258 if (bootsel != 1)
251 return CONFIG_SYS_MMC_ENV_DEV; 259 return CONFIG_SYS_MMC_ENV_DEV;
252 260
253 /* BOOT_CFG2[3] and BOOT_CFG2[4] */ 261 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
254 dev_no = (soc_sbmr & 0x00001800) >> 11; 262 dev_no = (soc_sbmr & 0x00001800) >> 11;
255 263
256 return dev_no; 264 return dev_no;
257 } 265 }
258 266
259 int mmc_map_to_kernel_blk(int dev_no) 267 int mmc_map_to_kernel_blk(int dev_no)
260 { 268 {
261 return dev_no; 269 return dev_no;
262 } 270 }
263 271
264 int board_mmc_getcd(struct mmc *mmc) 272 int board_mmc_getcd(struct mmc *mmc)
265 { 273 {
266 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 274 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
267 int ret = 0; 275 int ret = 0;
268 276
269 switch (cfg->esdhc_base) { 277 switch (cfg->esdhc_base) {
270 case USDHC1_BASE_ADDR: 278 case USDHC1_BASE_ADDR:
271 ret = !gpio_get_value(USDHC1_CD_GPIO); 279 ret = !gpio_get_value(USDHC1_CD_GPIO);
272 break; 280 break;
273 case USDHC2_BASE_ADDR: 281 case USDHC2_BASE_ADDR:
274 ret = !gpio_get_value(USDHC2_CD_GPIO); 282 ret = !gpio_get_value(USDHC2_CD_GPIO);
275 break; 283 break;
276 case USDHC3_BASE_ADDR: 284 case USDHC3_BASE_ADDR:
277 ret = !gpio_get_value(USDHC3_CD_GPIO); 285 ret = !gpio_get_value(USDHC3_CD_GPIO);
278 break; 286 break;
279 } 287 }
280 288
281 return ret; 289 return ret;
282 } 290 }
283 291
284 int board_mmc_init(bd_t *bis) 292 int board_mmc_init(bd_t *bis)
285 { 293 {
286 int i; 294 int i;
287 295
288 /* 296 /*
289 * According to the board_mmc_init() the following map is done: 297 * According to the board_mmc_init() the following map is done:
290 * (U-boot device node) (Physical Port) 298 * (U-boot device node) (Physical Port)
291 * mmc0 USDHC1 299 * mmc0 USDHC1
292 * mmc1 USDHC2 300 * mmc1 USDHC2
293 * mmc2 USDHC3 301 * mmc2 USDHC3
294 */ 302 */
295 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 303 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
296 switch (i) { 304 switch (i) {
297 case 0: 305 case 0:
298 imx_iomux_v3_setup_multiple_pads( 306 imx_iomux_v3_setup_multiple_pads(
299 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 307 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
300 gpio_direction_input(USDHC1_CD_GPIO); 308 gpio_direction_input(USDHC1_CD_GPIO);
301 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 309 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
302 break; 310 break;
303 case 1: 311 case 1:
304 imx_iomux_v3_setup_multiple_pads( 312 imx_iomux_v3_setup_multiple_pads(
305 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 313 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
306 gpio_direction_input(USDHC2_CD_GPIO); 314 gpio_direction_input(USDHC2_CD_GPIO);
307 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 315 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
308 break; 316 break;
309 case 2: 317 case 2:
310 imx_iomux_v3_setup_multiple_pads( 318 imx_iomux_v3_setup_multiple_pads(
311 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 319 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
312 gpio_direction_input(USDHC3_CD_GPIO); 320 gpio_direction_input(USDHC3_CD_GPIO);
313 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 321 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
314 break; 322 break;
315 default: 323 default:
316 printf("Warning: you configured more USDHC controllers" 324 printf("Warning: you configured more USDHC controllers"
317 "(%d) than supported by the board\n", i + 1); 325 "(%d) than supported by the board\n", i + 1);
318 return 0; 326 return 0;
319 } 327 }
320 328
321 if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) 329 if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
322 printf("Warning: failed to initialize mmc dev %d\n", i); 330 printf("Warning: failed to initialize mmc dev %d\n", i);
323 } 331 }
324 332
325 return 0; 333 return 0;
326 } 334 }
327 335
328 int check_mmc_autodetect(void) 336 int check_mmc_autodetect(void)
329 { 337 {
330 char *autodetect_str = getenv("mmcautodetect"); 338 char *autodetect_str = getenv("mmcautodetect");
331 339
332 if ((autodetect_str != NULL) && 340 if ((autodetect_str != NULL) &&
333 (strcmp(autodetect_str, "yes") == 0)) { 341 (strcmp(autodetect_str, "yes") == 0)) {
334 return 1; 342 return 1;
335 } 343 }
336 344
337 return 0; 345 return 0;
338 } 346 }
339 347
340 void board_late_mmc_env_init(void) 348 void board_late_mmc_env_init(void)
341 { 349 {
342 char cmd[32]; 350 char cmd[32];
343 char mmcblk[32]; 351 char mmcblk[32];
344 u32 dev_no = mmc_get_env_devno(); 352 u32 dev_no = mmc_get_env_devno();
345 353
346 if (!check_mmc_autodetect()) 354 if (!check_mmc_autodetect())
347 return; 355 return;
348 356
349 setenv_ulong("mmcdev", dev_no); 357 setenv_ulong("mmcdev", dev_no);
350 358
351 /* Set mmcblk env */ 359 /* Set mmcblk env */
352 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", 360 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
353 mmc_map_to_kernel_blk(dev_no)); 361 mmc_map_to_kernel_blk(dev_no));
354 setenv("mmcroot", mmcblk); 362 setenv("mmcroot", mmcblk);
355 363
356 sprintf(cmd, "mmc dev %d", dev_no); 364 sprintf(cmd, "mmc dev %d", dev_no);
357 run_command(cmd, 0); 365 run_command(cmd, 0);
358 } 366 }
359 #endif 367 #endif
360 368
361 #ifdef CONFIG_MXC_EPDC 369 #ifdef CONFIG_MXC_EPDC
362 #ifdef CONFIG_SPLASH_SCREEN 370 #ifdef CONFIG_SPLASH_SCREEN
363 extern int mmc_get_env_devno(void); 371 extern int mmc_get_env_devno(void);
364 int setup_splash_img(void) 372 int setup_splash_img(void)
365 { 373 {
366 #ifdef CONFIG_SPLASH_IS_IN_MMC 374 #ifdef CONFIG_SPLASH_IS_IN_MMC
367 int mmc_dev = mmc_get_env_devno(); 375 int mmc_dev = mmc_get_env_devno();
368 ulong offset = CONFIG_SPLASH_IMG_OFFSET; 376 ulong offset = CONFIG_SPLASH_IMG_OFFSET;
369 ulong size = CONFIG_SPLASH_IMG_SIZE; 377 ulong size = CONFIG_SPLASH_IMG_SIZE;
370 ulong addr = 0; 378 ulong addr = 0;
371 char *s = NULL; 379 char *s = NULL;
372 struct mmc *mmc = find_mmc_device(mmc_dev); 380 struct mmc *mmc = find_mmc_device(mmc_dev);
373 uint blk_start, blk_cnt, n; 381 uint blk_start, blk_cnt, n;
374 382
375 s = getenv("splashimage"); 383 s = getenv("splashimage");
376 384
377 if (NULL == s) { 385 if (NULL == s) {
378 puts("env splashimage not found!\n"); 386 puts("env splashimage not found!\n");
379 return -1; 387 return -1;
380 } 388 }
381 addr = simple_strtoul(s, NULL, 16); 389 addr = simple_strtoul(s, NULL, 16);
382 390
383 if (!mmc) { 391 if (!mmc) {
384 printf("MMC Device %d not found\n", mmc_dev); 392 printf("MMC Device %d not found\n", mmc_dev);
385 return -1; 393 return -1;
386 } 394 }
387 395
388 if (mmc_init(mmc)) { 396 if (mmc_init(mmc)) {
389 puts("MMC init failed\n"); 397 puts("MMC init failed\n");
390 return -1; 398 return -1;
391 } 399 }
392 400
393 blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; 401 blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
394 blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; 402 blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
395 n = mmc->block_dev.block_read(mmc_dev, blk_start, 403 n = mmc->block_dev.block_read(mmc_dev, blk_start,
396 blk_cnt, (u_char *)addr); 404 blk_cnt, (u_char *)addr);
397 flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len); 405 flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
398 406
399 return (n == blk_cnt) ? 0 : -1; 407 return (n == blk_cnt) ? 0 : -1;
400 #endif 408 #endif
401 409
402 return 0; 410 return 0;
403 } 411 }
404 #endif 412 #endif
405 413
406 vidinfo_t panel_info = { 414 vidinfo_t panel_info = {
407 .vl_refresh = 85, 415 .vl_refresh = 85,
408 .vl_col = 800, 416 .vl_col = 800,
409 .vl_row = 600, 417 .vl_row = 600,
410 .vl_pixclock = 26666667, 418 .vl_pixclock = 26666667,
411 .vl_left_margin = 8, 419 .vl_left_margin = 8,
412 .vl_right_margin = 100, 420 .vl_right_margin = 100,
413 .vl_upper_margin = 4, 421 .vl_upper_margin = 4,
414 .vl_lower_margin = 8, 422 .vl_lower_margin = 8,
415 .vl_hsync = 4, 423 .vl_hsync = 4,
416 .vl_vsync = 1, 424 .vl_vsync = 1,
417 .vl_sync = 0, 425 .vl_sync = 0,
418 .vl_mode = 0, 426 .vl_mode = 0,
419 .vl_flag = 0, 427 .vl_flag = 0,
420 .vl_bpix = 3, 428 .vl_bpix = 3,
421 .cmap = 0, 429 .cmap = 0,
422 }; 430 };
423 431
424 struct epdc_timing_params panel_timings = { 432 struct epdc_timing_params panel_timings = {
425 .vscan_holdoff = 4, 433 .vscan_holdoff = 4,
426 .sdoed_width = 10, 434 .sdoed_width = 10,
427 .sdoed_delay = 20, 435 .sdoed_delay = 20,
428 .sdoez_width = 10, 436 .sdoez_width = 10,
429 .sdoez_delay = 20, 437 .sdoez_delay = 20,
430 .gdclk_hp_offs = 419, 438 .gdclk_hp_offs = 419,
431 .gdsp_offs = 20, 439 .gdsp_offs = 20,
432 .gdoe_offs = 0, 440 .gdoe_offs = 0,
433 .gdclk_offs = 5, 441 .gdclk_offs = 5,
434 .num_ce = 1, 442 .num_ce = 1,
435 }; 443 };
436 444
437 static void setup_epdc_power(void) 445 static void setup_epdc_power(void)
438 { 446 {
439 /* Setup epdc voltage */ 447 /* Setup epdc voltage */
440 448
441 /* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */ 449 /* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */
442 imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 | 450 imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 |
443 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 451 MUX_PAD_CTRL(EPDC_PAD_CTRL));
444 gpio_direction_input(IMX_GPIO_NR(2, 13)); 452 gpio_direction_input(IMX_GPIO_NR(2, 13));
445 453
446 /* EPDC_VCOM0 - GPIO2[3] for VCOM control */ 454 /* EPDC_VCOM0 - GPIO2[3] for VCOM control */
447 imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO_2_3 | 455 imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO_2_3 |
448 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 456 MUX_PAD_CTRL(EPDC_PAD_CTRL));
449 457
450 /* Set as output */ 458 /* Set as output */
451 gpio_direction_output(IMX_GPIO_NR(2, 3), 1); 459 gpio_direction_output(IMX_GPIO_NR(2, 3), 1);
452 460
453 /* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */ 461 /* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */
454 imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 | 462 imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 |
455 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 463 MUX_PAD_CTRL(EPDC_PAD_CTRL));
456 /* Set as output */ 464 /* Set as output */
457 gpio_direction_output(IMX_GPIO_NR(2, 14), 1); 465 gpio_direction_output(IMX_GPIO_NR(2, 14), 1);
458 466
459 /* EPDC_PWRCTRL0 - GPIO2[7] for EPD PWR CTL0 */ 467 /* EPDC_PWRCTRL0 - GPIO2[7] for EPD PWR CTL0 */
460 imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 | 468 imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 |
461 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 469 MUX_PAD_CTRL(EPDC_PAD_CTRL));
462 /* Set as output */ 470 /* Set as output */
463 gpio_direction_output(IMX_GPIO_NR(2, 7), 1); 471 gpio_direction_output(IMX_GPIO_NR(2, 7), 1);
464 } 472 }
465 473
466 int setup_waveform_file(void) 474 int setup_waveform_file(void)
467 { 475 {
468 #ifdef CONFIG_WAVEFORM_FILE_IN_MMC 476 #ifdef CONFIG_WAVEFORM_FILE_IN_MMC
469 int mmc_dev = mmc_get_env_devno(); 477 int mmc_dev = mmc_get_env_devno();
470 ulong offset = CONFIG_WAVEFORM_FILE_OFFSET; 478 ulong offset = CONFIG_WAVEFORM_FILE_OFFSET;
471 ulong size = CONFIG_WAVEFORM_FILE_SIZE; 479 ulong size = CONFIG_WAVEFORM_FILE_SIZE;
472 ulong addr = CONFIG_WAVEFORM_BUF_ADDR; 480 ulong addr = CONFIG_WAVEFORM_BUF_ADDR;
473 struct mmc *mmc = find_mmc_device(mmc_dev); 481 struct mmc *mmc = find_mmc_device(mmc_dev);
474 uint blk_start, blk_cnt, n; 482 uint blk_start, blk_cnt, n;
475 483
476 if (!mmc) { 484 if (!mmc) {
477 printf("MMC Device %d not found\n", mmc_dev); 485 printf("MMC Device %d not found\n", mmc_dev);
478 return -1; 486 return -1;
479 } 487 }
480 488
481 if (mmc_init(mmc)) { 489 if (mmc_init(mmc)) {
482 puts("MMC init failed\n"); 490 puts("MMC init failed\n");
483 return -1; 491 return -1;
484 } 492 }
485 493
486 blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; 494 blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
487 blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; 495 blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
488 n = mmc->block_dev.block_read(mmc_dev, blk_start, 496 n = mmc->block_dev.block_read(mmc_dev, blk_start,
489 blk_cnt, (u_char *)addr); 497 blk_cnt, (u_char *)addr);
490 flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len); 498 flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
491 499
492 return (n == blk_cnt) ? 0 : -1; 500 return (n == blk_cnt) ? 0 : -1;
493 #else 501 #else
494 return -1; 502 return -1;
495 #endif 503 #endif
496 } 504 }
497 505
498 static void epdc_enable_pins(void) 506 static void epdc_enable_pins(void)
499 { 507 {
500 /* epdc iomux settings */ 508 /* epdc iomux settings */
501 imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, 509 imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
502 ARRAY_SIZE(epdc_enable_pads)); 510 ARRAY_SIZE(epdc_enable_pads));
503 } 511 }
504 512
505 static void epdc_disable_pins(void) 513 static void epdc_disable_pins(void)
506 { 514 {
507 /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ 515 /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */
508 imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, 516 imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
509 ARRAY_SIZE(epdc_disable_pads)); 517 ARRAY_SIZE(epdc_disable_pads));
510 } 518 }
511 519
512 static void setup_epdc(void) 520 static void setup_epdc(void)
513 { 521 {
514 unsigned int reg; 522 unsigned int reg;
515 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 523 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
516 524
517 /*** epdc Maxim PMIC settings ***/ 525 /*** epdc Maxim PMIC settings ***/
518 526
519 /* EPDC PWRSTAT - GPIO2[13] for PWR_GOOD status */ 527 /* EPDC PWRSTAT - GPIO2[13] for PWR_GOOD status */
520 imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 | 528 imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 |
521 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 529 MUX_PAD_CTRL(EPDC_PAD_CTRL));
522 530
523 /* EPDC VCOM0 - GPIO2[3] for VCOM control */ 531 /* EPDC VCOM0 - GPIO2[3] for VCOM control */
524 imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO_2_3 | 532 imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO_2_3 |
525 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 533 MUX_PAD_CTRL(EPDC_PAD_CTRL));
526 534
527 /* UART4 TXD - GPIO2[14] for EPD PMIC WAKEUP */ 535 /* UART4 TXD - GPIO2[14] for EPD PMIC WAKEUP */
528 imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 | 536 imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 |
529 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 537 MUX_PAD_CTRL(EPDC_PAD_CTRL));
530 538
531 /* EIM_A18 - GPIO2[7] for EPD PWR CTL0 */ 539 /* EIM_A18 - GPIO2[7] for EPD PWR CTL0 */
532 imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 | 540 imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 |
533 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 541 MUX_PAD_CTRL(EPDC_PAD_CTRL));
534 542
535 /*** Set pixel clock rates for EPDC ***/ 543 /*** Set pixel clock rates for EPDC ***/
536 544
537 /* EPDC AXI clk from PFD_400M, set to 396/2 = 198MHz */ 545 /* EPDC AXI clk from PFD_400M, set to 396/2 = 198MHz */
538 reg = readl(&ccm_regs->chsccdr); 546 reg = readl(&ccm_regs->chsccdr);
539 reg &= ~0x3F000; 547 reg &= ~0x3F000;
540 reg |= (0x4 << 15) | (1 << 12); 548 reg |= (0x4 << 15) | (1 << 12);
541 writel(reg, &ccm_regs->chsccdr); 549 writel(reg, &ccm_regs->chsccdr);
542 550
543 /* EPDC AXI clk enable */ 551 /* EPDC AXI clk enable */
544 reg = readl(&ccm_regs->CCGR3); 552 reg = readl(&ccm_regs->CCGR3);
545 reg |= 0x0030; 553 reg |= 0x0030;
546 writel(reg, &ccm_regs->CCGR3); 554 writel(reg, &ccm_regs->CCGR3);
547 555
548 /* EPDC PIX clk from PFD_540M, set to 540/4/5 = 27MHz */ 556 /* EPDC PIX clk from PFD_540M, set to 540/4/5 = 27MHz */
549 reg = readl(&ccm_regs->cscdr2); 557 reg = readl(&ccm_regs->cscdr2);
550 reg &= ~0x03F000; 558 reg &= ~0x03F000;
551 reg |= (0x5 << 15) | (4 << 12); 559 reg |= (0x5 << 15) | (4 << 12);
552 writel(reg, &ccm_regs->cscdr2); 560 writel(reg, &ccm_regs->cscdr2);
553 561
554 reg = readl(&ccm_regs->cbcmr); 562 reg = readl(&ccm_regs->cbcmr);
555 reg &= ~0x03800000; 563 reg &= ~0x03800000;
556 reg |= (0x3 << 23); 564 reg |= (0x3 << 23);
557 writel(reg, &ccm_regs->cbcmr); 565 writel(reg, &ccm_regs->cbcmr);
558 566
559 /* EPDC PIX clk enable */ 567 /* EPDC PIX clk enable */
560 reg = readl(&ccm_regs->CCGR3); 568 reg = readl(&ccm_regs->CCGR3);
561 reg |= 0x0C00; 569 reg |= 0x0C00;
562 writel(reg, &ccm_regs->CCGR3); 570 writel(reg, &ccm_regs->CCGR3);
563 571
564 panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR; 572 panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR;
565 panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR; 573 panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR;
566 574
567 panel_info.epdc_data.wv_modes.mode_init = 0; 575 panel_info.epdc_data.wv_modes.mode_init = 0;
568 panel_info.epdc_data.wv_modes.mode_du = 1; 576 panel_info.epdc_data.wv_modes.mode_du = 1;
569 panel_info.epdc_data.wv_modes.mode_gc4 = 3; 577 panel_info.epdc_data.wv_modes.mode_gc4 = 3;
570 panel_info.epdc_data.wv_modes.mode_gc8 = 2; 578 panel_info.epdc_data.wv_modes.mode_gc8 = 2;
571 panel_info.epdc_data.wv_modes.mode_gc16 = 2; 579 panel_info.epdc_data.wv_modes.mode_gc16 = 2;
572 panel_info.epdc_data.wv_modes.mode_gc32 = 2; 580 panel_info.epdc_data.wv_modes.mode_gc32 = 2;
573 581
574 panel_info.epdc_data.epdc_timings = panel_timings; 582 panel_info.epdc_data.epdc_timings = panel_timings;
575 583
576 setup_epdc_power(); 584 setup_epdc_power();
577 585
578 /* Assign fb_base */ 586 /* Assign fb_base */
579 gd->fb_base = CONFIG_FB_BASE; 587 gd->fb_base = CONFIG_FB_BASE;
580 } 588 }
581 589
582 void epdc_power_on(void) 590 void epdc_power_on(void)
583 { 591 {
584 unsigned int reg; 592 unsigned int reg;
585 struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; 593 struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
586 594
587 /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ 595 /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
588 gpio_set_value(IMX_GPIO_NR(2, 7), 1); 596 gpio_set_value(IMX_GPIO_NR(2, 7), 1);
589 udelay(1000); 597 udelay(1000);
590 598
591 /* Enable epdc signal pin */ 599 /* Enable epdc signal pin */
592 epdc_enable_pins(); 600 epdc_enable_pins();
593 601
594 /* Set PMIC Wakeup to high - enable Display power */ 602 /* Set PMIC Wakeup to high - enable Display power */
595 gpio_set_value(IMX_GPIO_NR(2, 14), 1); 603 gpio_set_value(IMX_GPIO_NR(2, 14), 1);
596 604
597 /* Wait for PWRGOOD == 1 */ 605 /* Wait for PWRGOOD == 1 */
598 while (1) { 606 while (1) {
599 reg = readl(&gpio_regs->gpio_psr); 607 reg = readl(&gpio_regs->gpio_psr);
600 if (!(reg & (1 << 13))) 608 if (!(reg & (1 << 13)))
601 break; 609 break;
602 610
603 udelay(100); 611 udelay(100);
604 } 612 }
605 613
606 /* Enable VCOM */ 614 /* Enable VCOM */
607 gpio_set_value(IMX_GPIO_NR(2, 3), 1); 615 gpio_set_value(IMX_GPIO_NR(2, 3), 1);
608 616
609 udelay(500); 617 udelay(500);
610 } 618 }
611 619
612 void epdc_power_off(void) 620 void epdc_power_off(void)
613 { 621 {
614 /* Set PMIC Wakeup to low - disable Display power */ 622 /* Set PMIC Wakeup to low - disable Display power */
615 gpio_set_value(IMX_GPIO_NR(2, 14), 0); 623 gpio_set_value(IMX_GPIO_NR(2, 14), 0);
616 624
617 /* Disable VCOM */ 625 /* Disable VCOM */
618 gpio_set_value(IMX_GPIO_NR(2, 3), 0); 626 gpio_set_value(IMX_GPIO_NR(2, 3), 0);
619 627
620 epdc_disable_pins(); 628 epdc_disable_pins();
621 629
622 /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ 630 /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
623 gpio_set_value(IMX_GPIO_NR(2, 7), 0); 631 gpio_set_value(IMX_GPIO_NR(2, 7), 0);
624 } 632 }
625 #endif 633 #endif
626 634
627 #ifdef CONFIG_FEC_MXC 635 #ifdef CONFIG_FEC_MXC
628 int board_eth_init(bd_t *bis) 636 int board_eth_init(bd_t *bis)
629 { 637 {
630 setup_iomux_fec(); 638 setup_iomux_fec();
631 639
632 return cpu_eth_init(bis); 640 return cpu_eth_init(bis);
633 } 641 }
634 642
635 static int setup_fec(void) 643 static int setup_fec(void)
636 { 644 {
637 struct iomuxc_base_regs *iomuxc_regs = 645 struct iomuxc_base_regs *iomuxc_regs =
638 (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; 646 (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
639 int ret; 647 int ret;
640 648
641 /* clear gpr1[14], gpr1[18:17] to select anatop clock */ 649 /* clear gpr1[14], gpr1[18:17] to select anatop clock */
642 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); 650 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
643 651
644 ret = enable_fec_anatop_clock(0, ENET_50MHz); 652 ret = enable_fec_anatop_clock(0, ENET_50MHz);
645 if (ret) 653 if (ret)
646 return ret; 654 return ret;
647 655
648 return 0; 656 return 0;
649 } 657 }
650 #endif 658 #endif
651 659
652 #ifdef CONFIG_SYS_I2C_MXC 660 #ifdef CONFIG_SYS_I2C_MXC
653 /* set all switches APS in normal and PFM mode in standby */ 661 /* set all switches APS in normal and PFM mode in standby */
654 static int setup_pmic_mode(int chip) 662 static int setup_pmic_mode(int chip)
655 { 663 {
656 unsigned char offset, i, switch_num, value; 664 unsigned char offset, i, switch_num, value;
657 665
658 if (!chip) { 666 if (!chip) {
659 /* pfuze100 */ 667 /* pfuze100 */
660 switch_num = 6; 668 switch_num = 6;
661 offset = 0x31; 669 offset = 0x31;
662 } else { 670 } else {
663 /* pfuze200 */ 671 /* pfuze200 */
664 switch_num = 4; 672 switch_num = 4;
665 offset = 0x38; 673 offset = 0x38;
666 } 674 }
667 675
668 value = 0xc; 676 value = 0xc;
669 if (i2c_write(0x8, 0x23, 1, &value, 1)) { 677 if (i2c_write(0x8, 0x23, 1, &value, 1)) {
670 printf("Set SW1AB mode error!\n"); 678 printf("Set SW1AB mode error!\n");
671 return -1; 679 return -1;
672 } 680 }
673 681
674 for (i = 0; i < switch_num - 1; i++) { 682 for (i = 0; i < switch_num - 1; i++) {
675 if (i2c_write(0x8, offset + i * 7, 1, &value, 1)) { 683 if (i2c_write(0x8, offset + i * 7, 1, &value, 1)) {
676 printf("Set switch%x mode error!\n", offset); 684 printf("Set switch%x mode error!\n", offset);
677 return -1; 685 return -1;
678 } 686 }
679 } 687 }
680 688
681 return 0; 689 return 0;
682 } 690 }
683 691
684 static int setup_pmic_voltages(void) 692 static int setup_pmic_voltages(void)
685 { 693 {
686 unsigned char value, rev_id = 0; 694 unsigned char value, rev_id = 0;
687 695
688 i2c_set_bus_num(0); 696 i2c_set_bus_num(0);
689 if (!i2c_probe(0x8)) { 697 if (!i2c_probe(0x8)) {
690 if (i2c_read(0x8, 0, 1, &value, 1)) { 698 if (i2c_read(0x8, 0, 1, &value, 1)) {
691 printf("Read device ID error!\n"); 699 printf("Read device ID error!\n");
692 return -1; 700 return -1;
693 } 701 }
694 if (i2c_read(0x8, 3, 1, &rev_id, 1)) { 702 if (i2c_read(0x8, 3, 1, &rev_id, 1)) {
695 printf("Read Rev ID error!\n"); 703 printf("Read Rev ID error!\n");
696 return -1; 704 return -1;
697 } 705 }
698 printf("Found PFUZE%s deviceid=%x,revid=%x\n", 706 printf("Found PFUZE%s deviceid=%x,revid=%x\n",
699 ((value & 0xf) == 0) ? "100" : "200", value, rev_id); 707 ((value & 0xf) == 0) ? "100" : "200", value, rev_id);
700 708
701 if (setup_pmic_mode(value & 0xf)) { 709 if (setup_pmic_mode(value & 0xf)) {
702 printf("setup pmic mode error!\n"); 710 printf("setup pmic mode error!\n");
703 return -1; 711 return -1;
704 } 712 }
705 /* set SW1AB staby volatage 0.975V */ 713 /* set SW1AB staby volatage 0.975V */
706 if (i2c_read(0x8, 0x21, 1, &value, 1)) { 714 if (i2c_read(0x8, 0x21, 1, &value, 1)) {
707 printf("Read SW1ABSTBY error!\n"); 715 printf("Read SW1ABSTBY error!\n");
708 return -1; 716 return -1;
709 } 717 }
710 value &= ~0x3f; 718 value &= ~0x3f;
711 value |= 0x1b; 719 value |= 0x1b;
712 if (i2c_write(0x8, 0x21, 1, &value, 1)) { 720 if (i2c_write(0x8, 0x21, 1, &value, 1)) {
713 printf("Set SW1ABSTBY error!\n"); 721 printf("Set SW1ABSTBY error!\n");
714 return -1; 722 return -1;
715 } 723 }
716 724
717 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ 725 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
718 if (i2c_read(0x8, 0x24, 1, &value, 1)) { 726 if (i2c_read(0x8, 0x24, 1, &value, 1)) {
719 printf("Read SW1ABCONFIG error!\n"); 727 printf("Read SW1ABCONFIG error!\n");
720 return -1; 728 return -1;
721 } 729 }
722 value &= ~0xc0; 730 value &= ~0xc0;
723 value |= 0x40; 731 value |= 0x40;
724 if (i2c_write(0x8, 0x24, 1, &value, 1)) { 732 if (i2c_write(0x8, 0x24, 1, &value, 1)) {
725 printf("Set SW1ABCONFIG error!\n"); 733 printf("Set SW1ABCONFIG error!\n");
726 return -1; 734 return -1;
727 } 735 }
728 736
729 /* set SW1C staby volatage 0.975V */ 737 /* set SW1C staby volatage 0.975V */
730 if (i2c_read(0x8, 0x2f, 1, &value, 1)) { 738 if (i2c_read(0x8, 0x2f, 1, &value, 1)) {
731 printf("Read SW1CSTBY error!\n"); 739 printf("Read SW1CSTBY error!\n");
732 return -1; 740 return -1;
733 } 741 }
734 value &= ~0x3f; 742 value &= ~0x3f;
735 value |= 0x1b; 743 value |= 0x1b;
736 if (i2c_write(0x8, 0x2f, 1, &value, 1)) { 744 if (i2c_write(0x8, 0x2f, 1, &value, 1)) {
737 printf("Set SW1CSTBY error!\n"); 745 printf("Set SW1CSTBY error!\n");
738 return -1; 746 return -1;
739 } 747 }
740 748
741 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ 749 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
742 if (i2c_read(0x8, 0x32, 1, &value, 1)) { 750 if (i2c_read(0x8, 0x32, 1, &value, 1)) {
743 printf("Read SW1CCONFIG error!\n"); 751 printf("Read SW1CCONFIG error!\n");
744 return -1; 752 return -1;
745 } 753 }
746 value &= ~0xc0; 754 value &= ~0xc0;
747 value |= 0x40; 755 value |= 0x40;
748 if (i2c_write(0x8, 0x32, 1, &value, 1)) { 756 if (i2c_write(0x8, 0x32, 1, &value, 1)) {
749 printf("Set SW1CCONFIG error!\n"); 757 printf("Set SW1CCONFIG error!\n");
750 return -1; 758 return -1;
751 } 759 }
752 } 760 }
753 761
754 return 0; 762 return 0;
755 } 763 }
756 764
757 #ifdef CONFIG_LDO_BYPASS_CHECK 765 #ifdef CONFIG_LDO_BYPASS_CHECK
758 void ldo_mode_set(int ldo_bypass) 766 void ldo_mode_set(int ldo_bypass)
759 { 767 {
760 unsigned char value; 768 unsigned char value;
761 int is_400M; 769 int is_400M;
762 770
763 /* swith to ldo_bypass mode */ 771 /* swith to ldo_bypass mode */
764 if (ldo_bypass) { 772 if (ldo_bypass) {
765 prep_anatop_bypass(); 773 prep_anatop_bypass();
766 774
767 /* decrease VDDARM to 1.1V */ 775 /* decrease VDDARM to 1.1V */
768 if (i2c_read(0x8, 0x20, 1, &value, 1)) { 776 if (i2c_read(0x8, 0x20, 1, &value, 1)) {
769 printf("Read SW1AB error!\n"); 777 printf("Read SW1AB error!\n");
770 return; 778 return;
771 } 779 }
772 value &= ~0x3f; 780 value &= ~0x3f;
773 value |= 0x20; 781 value |= 0x20;
774 if (i2c_write(0x8, 0x20, 1, &value, 1)) { 782 if (i2c_write(0x8, 0x20, 1, &value, 1)) {
775 printf("Set SW1AB error!\n"); 783 printf("Set SW1AB error!\n");
776 return; 784 return;
777 } 785 }
778 /* increase VDDSOC to 1.3V */ 786 /* increase VDDSOC to 1.3V */
779 if (i2c_read(0x8, 0x2e, 1, &value, 1)) { 787 if (i2c_read(0x8, 0x2e, 1, &value, 1)) {
780 printf("Read SW1C error!\n"); 788 printf("Read SW1C error!\n");
781 return; 789 return;
782 } 790 }
783 value &= ~0x3f; 791 value &= ~0x3f;
784 value |= 0x28; 792 value |= 0x28;
785 if (i2c_write(0x8, 0x2e, 1, &value, 1)) { 793 if (i2c_write(0x8, 0x2e, 1, &value, 1)) {
786 printf("Set SW1C error!\n"); 794 printf("Set SW1C error!\n");
787 return; 795 return;
788 } 796 }
789 797
790 is_400M = set_anatop_bypass(0); 798 is_400M = set_anatop_bypass(0);
791 799
792 /* 800 /*
793 * MX6SL: VDDARM:1.175V@800M; VDDSOC:1.175V@800M 801 * MX6SL: VDDARM:1.175V@800M; VDDSOC:1.175V@800M
794 * VDDARM:0.975V@400M; VDDSOC:1.175V@400M 802 * VDDARM:0.975V@400M; VDDSOC:1.175V@400M
795 */ 803 */
796 if (i2c_read(0x8, 0x20, 1, &value, 1)) { 804 if (i2c_read(0x8, 0x20, 1, &value, 1)) {
797 printf("Read SW1AB error!\n"); 805 printf("Read SW1AB error!\n");
798 return; 806 return;
799 } 807 }
800 value &= ~0x3f; 808 value &= ~0x3f;
801 if (is_400M) 809 if (is_400M)
802 value |= 0x1b; 810 value |= 0x1b;
803 else 811 else
804 value |= 0x23; 812 value |= 0x23;
805 if (i2c_write(0x8, 0x20, 1, &value, 1)) { 813 if (i2c_write(0x8, 0x20, 1, &value, 1)) {
806 printf("Set SW1AB error!\n"); 814 printf("Set SW1AB error!\n");
807 return; 815 return;
808 } 816 }
809 817
810 /* decrease VDDSOC to 1.175V */ 818 /* decrease VDDSOC to 1.175V */
811 if (i2c_read(0x8, 0x2e, 1, &value, 1)) { 819 if (i2c_read(0x8, 0x2e, 1, &value, 1)) {
812 printf("Read SW1C error!\n"); 820 printf("Read SW1C error!\n");
813 return; 821 return;
814 } 822 }
815 value &= ~0x3f; 823 value &= ~0x3f;
816 value |= 0x23; 824 value |= 0x23;
817 if (i2c_write(0x8, 0x2e, 1, &value, 1)) { 825 if (i2c_write(0x8, 0x2e, 1, &value, 1)) {
818 printf("Set SW1C error!\n"); 826 printf("Set SW1C error!\n");
819 return; 827 return;
820 } 828 }
821 829
822 finish_anatop_bypass(); 830 finish_anatop_bypass();
823 printf("switch to ldo_bypass mode!\n"); 831 printf("switch to ldo_bypass mode!\n");
824 } 832 }
825 833
826 } 834 }
827 #endif 835 #endif
828 #endif 836 #endif
829 837
830 int board_early_init_f(void) 838 int board_early_init_f(void)
831 { 839 {
832 setup_iomux_uart(); 840 setup_iomux_uart();
833 841
834 #ifdef CONFIG_SYS_USE_SPINOR 842 #ifdef CONFIG_SYS_USE_SPINOR
835 setup_spinor(); 843 setup_spinor();
836 #endif 844 #endif
837 845
838 return 0; 846 return 0;
839 } 847 }
840 848
841 int board_init(void) 849 int board_init(void)
842 { 850 {
843 /* address of boot parameters */ 851 /* address of boot parameters */
844 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 852 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
845 853
846 #ifdef CONFIG_FEC_MXC 854 #ifdef CONFIG_FEC_MXC
847 setup_fec(); 855 setup_fec();
848 #endif 856 #endif
849 857
850 #ifdef CONFIG_MXC_EPDC 858 #ifdef CONFIG_MXC_EPDC
851 setup_epdc(); 859 setup_epdc();
852 #endif 860 #endif
853 return 0; 861 return 0;
854 } 862 }
855 863
864 void setup_elan_pads(void)
865 {
866 #define TOUCH_CS IMX_GPIO_NR(2, 9)
867 #define TOUCH_INT IMX_GPIO_NR(2, 10)
868 #define TOUCH_RST IMX_GPIO_NR(4, 4)
869 imx_iomux_v3_setup_multiple_pads(elan_pads, ARRAY_SIZE(elan_pads));
870 }
871
872 void elan_init(void)
873 {
874 gpio_direction_input(TOUCH_INT);
875 gpio_direction_output(TOUCH_CS , 1);
876 gpio_set_value(TOUCH_CS, 0);
877 gpio_direction_output(TOUCH_RST , 1);
878 gpio_set_value(TOUCH_RST, 0);
879 mdelay(10);
880 gpio_set_value(TOUCH_RST, 1);
881 gpio_set_value(TOUCH_CS, 1);
882 mdelay(100);
883 }
884
885 /*
886 * This function overwrite the function defined in
887 * drivers/i2c/mxc_i2c.c, which is a weak symbol
888 */
889 void i2c_force_reset_slave(void)
890 {
891 elan_init();
892 }
893
856 int board_late_init(void) 894 int board_late_init(void)
857 { 895 {
858 int ret = 0; 896 int ret = 0;
859 897
860 #ifdef CONFIG_SYS_I2C_MXC 898 #ifdef CONFIG_SYS_I2C_MXC
861 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 899 setup_i2c(0, CONFIG_SYS_I2C_SPEED,
862 0x7f, &i2c_pad_info0); 900 0x7f, &i2c_pad_info0);
901 setup_elan_pads();
863 ret = setup_pmic_voltages(); 902 ret = setup_pmic_voltages();
864 if (ret) 903 if (ret)
865 return -1; 904 return -1;
866 #endif 905 #endif
867 906
868 #ifdef CONFIG_ENV_IS_IN_MMC 907 #ifdef CONFIG_ENV_IS_IN_MMC
869 board_late_mmc_env_init(); 908 board_late_mmc_env_init();
870 #endif 909 #endif
871 910
872 return 0; 911 return 0;
873 } 912 }
874 913
875 u32 get_board_rev(void) 914 u32 get_board_rev(void)
876 { 915 {
877 return get_cpu_rev(); 916 return get_cpu_rev();
878 } 917 }
879 918
880 #ifdef CONFIG_FASTBOOT 919 #ifdef CONFIG_FASTBOOT
881 920
882 void board_fastboot_setup(void) 921 void board_fastboot_setup(void)
883 { 922 {
884 switch (get_boot_device()) { 923 switch (get_boot_device()) {
885 #if defined(CONFIG_FASTBOOT_STORAGE_MMC) 924 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
886 case SD1_BOOT: 925 case SD1_BOOT:
887 case MMC1_BOOT: 926 case MMC1_BOOT:
888 if (!getenv("fastboot_dev")) 927 if (!getenv("fastboot_dev"))
889 setenv("fastboot_dev", "mmc0"); 928 setenv("fastboot_dev", "mmc0");
890 if (!getenv("bootcmd")) 929 if (!getenv("bootcmd"))
891 setenv("bootcmd", "booti mmc0"); 930 setenv("bootcmd", "booti mmc0");
892 break; 931 break;
893 case SD2_BOOT: 932 case SD2_BOOT:
894 case MMC2_BOOT: 933 case MMC2_BOOT:
895 if (!getenv("fastboot_dev")) 934 if (!getenv("fastboot_dev"))
896 setenv("fastboot_dev", "mmc1"); 935 setenv("fastboot_dev", "mmc1");
897 if (!getenv("bootcmd")) 936 if (!getenv("bootcmd"))
898 setenv("bootcmd", "booti mmc1"); 937 setenv("bootcmd", "booti mmc1");
899 break; 938 break;
900 case SD3_BOOT: 939 case SD3_BOOT:
901 case MMC3_BOOT: 940 case MMC3_BOOT:
902 if (!getenv("fastboot_dev")) 941 if (!getenv("fastboot_dev"))
903 setenv("fastboot_dev", "mmc2"); 942 setenv("fastboot_dev", "mmc2");
904 if (!getenv("bootcmd")) 943 if (!getenv("bootcmd"))
905 setenv("bootcmd", "booti mmc2"); 944 setenv("bootcmd", "booti mmc2");
906 break; 945 break;
907 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ 946 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
908 default: 947 default:
909 printf("unsupported boot devices\n"); 948 printf("unsupported boot devices\n");
910 break; 949 break;
911 } 950 }
912 951
913 } 952 }
914 953
915 #ifdef CONFIG_ANDROID_RECOVERY 954 #ifdef CONFIG_ANDROID_RECOVERY
916 int check_recovery_cmd_file(void) 955 int check_recovery_cmd_file(void)
917 { 956 {
918 return recovery_check_and_clean_flag(); 957 return recovery_check_and_clean_flag();
919 } 958 }
920 959
921 void board_recovery_setup(void) 960 void board_recovery_setup(void)
922 { 961 {
923 int bootdev = get_boot_device(); 962 int bootdev = get_boot_device();
924 963
925 /*current uboot BSP only supports USDHC2*/ 964 /*current uboot BSP only supports USDHC2*/
926 switch (bootdev) { 965 switch (bootdev) {
927 #if defined(CONFIG_FASTBOOT_STORAGE_MMC) 966 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
928 case SD1_BOOT: 967 case SD1_BOOT:
929 case MMC1_BOOT: 968 case MMC1_BOOT:
930 if (!getenv("bootcmd_android_recovery")) 969 if (!getenv("bootcmd_android_recovery"))
931 setenv("bootcmd_android_recovery", 970 setenv("bootcmd_android_recovery",
932 "booti mmc0 recovery"); 971 "booti mmc0 recovery");
933 break; 972 break;
934 case SD2_BOOT: 973 case SD2_BOOT:
935 case MMC2_BOOT: 974 case MMC2_BOOT:
936 if (!getenv("bootcmd_android_recovery")) 975 if (!getenv("bootcmd_android_recovery"))
937 setenv("bootcmd_android_recovery", 976 setenv("bootcmd_android_recovery",
938 "booti mmc1 recovery"); 977 "booti mmc1 recovery");
939 break; 978 break;
940 case SD3_BOOT: 979 case SD3_BOOT:
941 case MMC3_BOOT: 980 case MMC3_BOOT:
942 if (!getenv("bootcmd_android_recovery")) 981 if (!getenv("bootcmd_android_recovery"))
943 setenv("bootcmd_android_recovery", 982 setenv("bootcmd_android_recovery",
944 "booti mmc2 recovery"); 983 "booti mmc2 recovery");
945 break; 984 break;
946 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ 985 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
947 default: 986 default:
948 printf("Unsupported bootup device for recovery: dev: %d\n", 987 printf("Unsupported bootup device for recovery: dev: %d\n",
949 bootdev); 988 bootdev);
950 return; 989 return;
951 } 990 }
952 991
953 printf("setup env for recovery..\n"); 992 printf("setup env for recovery..\n");
954 setenv("bootcmd", "run bootcmd_android_recovery"); 993 setenv("bootcmd", "run bootcmd_android_recovery");
955 } 994 }
956 995
957 #endif /*CONFIG_ANDROID_RECOVERY*/ 996 #endif /*CONFIG_ANDROID_RECOVERY*/
958 997
959 #endif /*CONFIG_FASTBOOT*/ 998 #endif /*CONFIG_FASTBOOT*/
960 999
961 1000
962 #ifdef CONFIG_MXC_KPD 1001 #ifdef CONFIG_MXC_KPD
963 #define MX6SL_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ 1002 #define MX6SL_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
964 PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_120ohm) 1003 PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_120ohm)
965 1004
966 iomux_v3_cfg_t const mxc_kpd_pads[] = { 1005 iomux_v3_cfg_t const mxc_kpd_pads[] = {
967 (MX6_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL)), 1006 (MX6_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL)),
968 (MX6_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL)), 1007 (MX6_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL)),
969 (MX6_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL)), 1008 (MX6_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL)),
970 (MX6_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)), 1009 (MX6_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)),
971 1010
972 (MX6_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)), 1011 (MX6_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)),
973 (MX6_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)), 1012 (MX6_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)),
974 (MX6_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)), 1013 (MX6_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)),
975 (MX6_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)), 1014 (MX6_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)),
976 }; 1015 };
977 int setup_mxc_kpd(void) 1016 int setup_mxc_kpd(void)
978 { 1017 {
979 imx_iomux_v3_setup_multiple_pads(mxc_kpd_pads, 1018 imx_iomux_v3_setup_multiple_pads(mxc_kpd_pads,
980 ARRAY_SIZE(mxc_kpd_pads)); 1019 ARRAY_SIZE(mxc_kpd_pads));
981 1020
982 return 0; 1021 return 0;
983 } 1022 }
984 #endif /*CONFIG_MXC_KPD*/ 1023 #endif /*CONFIG_MXC_KPD*/
985 1024
986 #ifdef CONFIG_IMX_UDC 1025 #ifdef CONFIG_IMX_UDC
987 iomux_v3_cfg_t const otg_udc_pads[] = { 1026 iomux_v3_cfg_t const otg_udc_pads[] = {
988 (MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), 1027 (MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
989 }; 1028 };
990 void udc_pins_setting(void) 1029 void udc_pins_setting(void)
991 { 1030 {
992 imx_iomux_v3_setup_multiple_pads(otg_udc_pads, 1031 imx_iomux_v3_setup_multiple_pads(otg_udc_pads,
993 ARRAY_SIZE(otg_udc_pads)); 1032 ARRAY_SIZE(otg_udc_pads));
994 } 1033 }
995 #endif /*CONFIG_IMX_UDC*/ 1034 #endif /*CONFIG_IMX_UDC*/
996 1035
997 int checkboard(void) 1036 int checkboard(void)
998 { 1037 {
999 puts("Board: MX6SLEVK\n"); 1038 puts("Board: MX6SLEVK\n");
1000 1039
1001 return 0; 1040 return 0;
1002 } 1041 }
1003 1042
1004 #ifdef CONFIG_USB_EHCI_MX6 1043 #ifdef CONFIG_USB_EHCI_MX6
1005 iomux_v3_cfg_t const usb_otg1_pads[] = { 1044 iomux_v3_cfg_t const usb_otg1_pads[] = {
1006 MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 1045 MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
1007 MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL) 1046 MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL)
1008 }; 1047 };
1009 1048
1010 iomux_v3_cfg_t const usb_otg2_pads[] = { 1049 iomux_v3_cfg_t const usb_otg2_pads[] = {
1011 MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 1050 MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
1012 }; 1051 };
1013 1052
1014 int board_ehci_hcd_init(int port) 1053 int board_ehci_hcd_init(int port)
1015 { 1054 {
1016 switch (port) { 1055 switch (port) {
1017 case 0: 1056 case 0:
1018 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, 1057 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
1019 ARRAY_SIZE(usb_otg1_pads)); 1058 ARRAY_SIZE(usb_otg1_pads));
1020 break; 1059 break;
1021 case 1: 1060 case 1:
1022 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, 1061 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
1023 ARRAY_SIZE(usb_otg2_pads)); 1062 ARRAY_SIZE(usb_otg2_pads));
1024 break; 1063 break;
1025 default: 1064 default:
1026 printf("MXC USB port %d not yet supported\n", port); 1065 printf("MXC USB port %d not yet supported\n", port);
1027 return 1; 1066 return 1;
1028 } 1067 }
1029 return 0; 1068 return 0;
1030 } 1069 }
1031 #endif 1070 #endif
1032 1071
drivers/i2c/mxc_i2c.c
Diff comments   View file @ 6baaad3
1 /* 1 /*
2 * i2c driver for Freescale i.MX series 2 * i2c driver for Freescale i.MX series
3 * 3 *
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * 6 *
7 * Based on i2c-imx.c from linux kernel: 7 * Based on i2c-imx.c from linux kernel:
8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> 8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> 9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
10 * Copyright (C) 2007 RightHand Technologies, Inc. 10 * Copyright (C) 2007 RightHand Technologies, Inc.
11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
12 * 12 *
13 * 13 *
14 * SPDX-License-Identifier: GPL-2.0+ 14 * SPDX-License-Identifier: GPL-2.0+
15 */ 15 */
16 16
17 #include <common.h> 17 #include <common.h>
18 #include <asm/arch/clock.h> 18 #include <asm/arch/clock.h>
19 #include <asm/arch/imx-regs.h> 19 #include <asm/arch/imx-regs.h>
20 #include <asm/errno.h> 20 #include <asm/errno.h>
21 #include <asm/io.h> 21 #include <asm/io.h>
22 #include <i2c.h> 22 #include <i2c.h>
23 #include <watchdog.h> 23 #include <watchdog.h>
24 24
25 #ifdef I2C_QUIRK_REG 25 #ifdef I2C_QUIRK_REG
26 struct mxc_i2c_regs { 26 struct mxc_i2c_regs {
27 uint8_t iadr; 27 uint8_t iadr;
28 uint8_t ifdr; 28 uint8_t ifdr;
29 uint8_t i2cr; 29 uint8_t i2cr;
30 uint8_t i2sr; 30 uint8_t i2sr;
31 uint8_t i2dr; 31 uint8_t i2dr;
32 }; 32 };
33 #else 33 #else
34 struct mxc_i2c_regs { 34 struct mxc_i2c_regs {
35 uint32_t iadr; 35 uint32_t iadr;
36 uint32_t ifdr; 36 uint32_t ifdr;
37 uint32_t i2cr; 37 uint32_t i2cr;
38 uint32_t i2sr; 38 uint32_t i2sr;
39 uint32_t i2dr; 39 uint32_t i2dr;
40 }; 40 };
41 #endif 41 #endif
42 42
43 #define I2CR_IIEN (1 << 6) 43 #define I2CR_IIEN (1 << 6)
44 #define I2CR_MSTA (1 << 5) 44 #define I2CR_MSTA (1 << 5)
45 #define I2CR_MTX (1 << 4) 45 #define I2CR_MTX (1 << 4)
46 #define I2CR_TX_NO_AK (1 << 3) 46 #define I2CR_TX_NO_AK (1 << 3)
47 #define I2CR_RSTA (1 << 2) 47 #define I2CR_RSTA (1 << 2)
48 48
49 #define I2SR_ICF (1 << 7) 49 #define I2SR_ICF (1 << 7)
50 #define I2SR_IBB (1 << 5) 50 #define I2SR_IBB (1 << 5)
51 #define I2SR_IAL (1 << 4) 51 #define I2SR_IAL (1 << 4)
52 #define I2SR_IIF (1 << 1) 52 #define I2SR_IIF (1 << 1)
53 #define I2SR_RX_NO_AK (1 << 0) 53 #define I2SR_RX_NO_AK (1 << 0)
54 54
55 #ifdef I2C_QUIRK_REG 55 #ifdef I2C_QUIRK_REG
56 #define I2CR_IEN (0 << 7) 56 #define I2CR_IEN (0 << 7)
57 #define I2CR_IDIS (1 << 7) 57 #define I2CR_IDIS (1 << 7)
58 #define I2SR_IIF_CLEAR (1 << 1) 58 #define I2SR_IIF_CLEAR (1 << 1)
59 #else 59 #else
60 #define I2CR_IEN (1 << 7) 60 #define I2CR_IEN (1 << 7)
61 #define I2CR_IDIS (0 << 7) 61 #define I2CR_IDIS (0 << 7)
62 #define I2SR_IIF_CLEAR (0 << 1) 62 #define I2SR_IIF_CLEAR (0 << 1)
63 #endif 63 #endif
64 64
65 #if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE) 65 #if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
66 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver" 66 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
67 #endif 67 #endif
68 68
69 #ifdef I2C_QUIRK_REG 69 #ifdef I2C_QUIRK_REG
70 static u16 i2c_clk_div[60][2] = { 70 static u16 i2c_clk_div[60][2] = {
71 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 71 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
72 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 72 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
73 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 73 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
74 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 74 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
75 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 75 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
76 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 76 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
77 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 77 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
78 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 78 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
79 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 79 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
80 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 80 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
81 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 81 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
82 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 82 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
83 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 83 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
84 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 84 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
85 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 85 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
86 }; 86 };
87 #else 87 #else
88 static u16 i2c_clk_div[50][2] = { 88 static u16 i2c_clk_div[50][2] = {
89 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 89 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
90 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 90 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
91 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 91 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
92 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 92 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
93 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 93 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
94 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 94 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
95 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 95 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
96 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 96 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
97 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 97 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
98 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 98 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
99 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 99 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
100 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 100 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
101 { 3072, 0x1E }, { 3840, 0x1F } 101 { 3072, 0x1E }, { 3840, 0x1F }
102 }; 102 };
103 #endif 103 #endif
104 104
105 105
106 #ifndef CONFIG_SYS_MXC_I2C1_SPEED 106 #ifndef CONFIG_SYS_MXC_I2C1_SPEED
107 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 107 #define CONFIG_SYS_MXC_I2C1_SPEED 100000
108 #endif 108 #endif
109 #ifndef CONFIG_SYS_MXC_I2C2_SPEED 109 #ifndef CONFIG_SYS_MXC_I2C2_SPEED
110 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 110 #define CONFIG_SYS_MXC_I2C2_SPEED 100000
111 #endif 111 #endif
112 #ifndef CONFIG_SYS_MXC_I2C3_SPEED 112 #ifndef CONFIG_SYS_MXC_I2C3_SPEED
113 #define CONFIG_SYS_MXC_I2C3_SPEED 100000 113 #define CONFIG_SYS_MXC_I2C3_SPEED 100000
114 #endif 114 #endif
115 115
116 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE 116 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
117 #define CONFIG_SYS_MXC_I2C1_SLAVE 0 117 #define CONFIG_SYS_MXC_I2C1_SLAVE 0
118 #endif 118 #endif
119 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE 119 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE
120 #define CONFIG_SYS_MXC_I2C2_SLAVE 0 120 #define CONFIG_SYS_MXC_I2C2_SLAVE 0
121 #endif 121 #endif
122 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE 122 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
123 #define CONFIG_SYS_MXC_I2C3_SLAVE 0 123 #define CONFIG_SYS_MXC_I2C3_SLAVE 0
124 #endif 124 #endif
125 125
126 126
127 /* 127 /*
128 * Calculate and set proper clock divider 128 * Calculate and set proper clock divider
129 */ 129 */
130 static uint8_t i2c_imx_get_clk(unsigned int rate) 130 static uint8_t i2c_imx_get_clk(unsigned int rate)
131 { 131 {
132 unsigned int i2c_clk_rate; 132 unsigned int i2c_clk_rate;
133 unsigned int div; 133 unsigned int div;
134 u8 clk_div; 134 u8 clk_div;
135 135
136 #if defined(CONFIG_MX31) 136 #if defined(CONFIG_MX31)
137 struct clock_control_regs *sc_regs = 137 struct clock_control_regs *sc_regs =
138 (struct clock_control_regs *)CCM_BASE; 138 (struct clock_control_regs *)CCM_BASE;
139 139
140 /* start the required I2C clock */ 140 /* start the required I2C clock */
141 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET), 141 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
142 &sc_regs->cgr0); 142 &sc_regs->cgr0);
143 #endif 143 #endif
144 144
145 /* Divider value calculation */ 145 /* Divider value calculation */
146 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK); 146 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
147 div = (i2c_clk_rate + rate - 1) / rate; 147 div = (i2c_clk_rate + rate - 1) / rate;
148 if (div < i2c_clk_div[0][0]) 148 if (div < i2c_clk_div[0][0])
149 clk_div = 0; 149 clk_div = 0;
150 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 150 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
151 clk_div = ARRAY_SIZE(i2c_clk_div) - 1; 151 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
152 else 152 else
153 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) 153 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
154 ; 154 ;
155 155
156 /* Store divider value */ 156 /* Store divider value */
157 return clk_div; 157 return clk_div;
158 } 158 }
159 159
160 /* 160 /*
161 * Set I2C Bus speed 161 * Set I2C Bus speed
162 */ 162 */
163 static int bus_i2c_set_bus_speed(void *base, int speed) 163 static int bus_i2c_set_bus_speed(void *base, int speed)
164 { 164 {
165 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 165 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
166 u8 clk_idx = i2c_imx_get_clk(speed); 166 u8 clk_idx = i2c_imx_get_clk(speed);
167 u8 idx = i2c_clk_div[clk_idx][1]; 167 u8 idx = i2c_clk_div[clk_idx][1];
168 168
169 /* Store divider value */ 169 /* Store divider value */
170 writeb(idx, &i2c_regs->ifdr); 170 writeb(idx, &i2c_regs->ifdr);
171 171
172 /* Reset module */ 172 /* Reset module */
173 writeb(I2CR_IDIS, &i2c_regs->i2cr); 173 writeb(I2CR_IDIS, &i2c_regs->i2cr);
174 writeb(0, &i2c_regs->i2sr); 174 writeb(0, &i2c_regs->i2sr);
175 return 0; 175 return 0;
176 } 176 }
177 177
178 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8)) 178 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
179 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8)) 179 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
180 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8)) 180 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
181 181
182 static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state) 182 static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state)
183 { 183 {
184 unsigned sr; 184 unsigned sr;
185 ulong elapsed; 185 ulong elapsed;
186 ulong start_time = get_timer(0); 186 ulong start_time = get_timer(0);
187 for (;;) { 187 for (;;) {
188 sr = readb(&i2c_regs->i2sr); 188 sr = readb(&i2c_regs->i2sr);
189 if (sr & I2SR_IAL) { 189 if (sr & I2SR_IAL) {
190 #ifdef I2C_QUIRK_REG 190 #ifdef I2C_QUIRK_REG
191 writeb(sr | I2SR_IAL, &i2c_regs->i2sr); 191 writeb(sr | I2SR_IAL, &i2c_regs->i2sr);
192 #else 192 #else
193 writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr); 193 writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr);
194 #endif 194 #endif
195 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n", 195 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
196 __func__, sr, readb(&i2c_regs->i2cr), state); 196 __func__, sr, readb(&i2c_regs->i2cr), state);
197 return -ERESTART; 197 return -ERESTART;
198 } 198 }
199 if ((sr & (state >> 8)) == (unsigned char)state) 199 if ((sr & (state >> 8)) == (unsigned char)state)
200 return sr; 200 return sr;
201 WATCHDOG_RESET(); 201 WATCHDOG_RESET();
202 elapsed = get_timer(start_time); 202 elapsed = get_timer(start_time);
203 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */ 203 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
204 break; 204 break;
205 } 205 }
206 printf("%s: failed sr=%x cr=%x state=%x\n", __func__, 206 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
207 sr, readb(&i2c_regs->i2cr), state); 207 sr, readb(&i2c_regs->i2cr), state);
208 return -ETIMEDOUT; 208 return -ETIMEDOUT;
209 } 209 }
210 210
211 static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte) 211 static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
212 { 212 {
213 int ret; 213 int ret;
214 214
215 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 215 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
216 writeb(byte, &i2c_regs->i2dr); 216 writeb(byte, &i2c_regs->i2dr);
217 ret = wait_for_sr_state(i2c_regs, ST_IIF); 217 ret = wait_for_sr_state(i2c_regs, ST_IIF);
218 if (ret < 0) 218 if (ret < 0)
219 return ret; 219 return ret;
220 if (ret & I2SR_RX_NO_AK) 220 if (ret & I2SR_RX_NO_AK)
221 return -ENODEV; 221 return -ENODEV;
222 return 0; 222 return 0;
223 } 223 }
224 224
225 /* 225 /*
226 * Stop I2C transaction 226 * Stop I2C transaction
227 */ 227 */
228 static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs) 228 static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs)
229 { 229 {
230 int ret; 230 int ret;
231 unsigned int temp = readb(&i2c_regs->i2cr); 231 unsigned int temp = readb(&i2c_regs->i2cr);
232 232
233 temp &= ~(I2CR_MSTA | I2CR_MTX); 233 temp &= ~(I2CR_MSTA | I2CR_MTX);
234 writeb(temp, &i2c_regs->i2cr); 234 writeb(temp, &i2c_regs->i2cr);
235 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE); 235 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
236 if (ret < 0) 236 if (ret < 0)
237 printf("%s:trigger stop failed\n", __func__); 237 printf("%s:trigger stop failed\n", __func__);
238 } 238 }
239 239
240 /* 240 /*
241 * Stub implementations for outer i2c slave operations
242 * Any board has special requirement (i.mx6slevk) can
243 * overwrite the function
244 */
245 void __i2c_force_reset_slave(void)
246 {
247 }
248 void i2c_force_reset_slave(void)
249 __attribute__((weak, alias("__i2c_force_reset_slave")));
250
251 /*
241 * Send start signal, chip address and 252 * Send start signal, chip address and
242 * write register address 253 * write register address
243 */ 254 */
244 static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs, 255 static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs,
245 uchar chip, uint addr, int alen) 256 uchar chip, uint addr, int alen)
246 { 257 {
247 unsigned int temp; 258 unsigned int temp;
248 int ret; 259 int ret;
260
261 /* Reset i2c slave */
262 i2c_force_reset_slave();
249 263
250 /* Enable I2C controller */ 264 /* Enable I2C controller */
251 #ifdef I2C_QUIRK_REG 265 #ifdef I2C_QUIRK_REG
252 if (readb(&i2c_regs->i2cr) & I2CR_IDIS) { 266 if (readb(&i2c_regs->i2cr) & I2CR_IDIS) {
253 #else 267 #else
254 if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) { 268 if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) {
255 #endif 269 #endif
256 writeb(I2CR_IEN, &i2c_regs->i2cr); 270 writeb(I2CR_IEN, &i2c_regs->i2cr);
257 /* Wait for controller to be stable */ 271 /* Wait for controller to be stable */
258 udelay(50); 272 udelay(50);
259 } 273 }
260 if (readb(&i2c_regs->iadr) == (chip << 1)) 274 if (readb(&i2c_regs->iadr) == (chip << 1))
261 writeb((chip << 1) ^ 2, &i2c_regs->iadr); 275 writeb((chip << 1) ^ 2, &i2c_regs->iadr);
262 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 276 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
263 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE); 277 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
264 if (ret < 0) 278 if (ret < 0)
265 return ret; 279 return ret;
266 280
267 /* Start I2C transaction */ 281 /* Start I2C transaction */
268 temp = readb(&i2c_regs->i2cr); 282 temp = readb(&i2c_regs->i2cr);
269 temp |= I2CR_MSTA; 283 temp |= I2CR_MSTA;
270 writeb(temp, &i2c_regs->i2cr); 284 writeb(temp, &i2c_regs->i2cr);
271 285
272 ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY); 286 ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
273 if (ret < 0) 287 if (ret < 0)
274 return ret; 288 return ret;
275 289
276 temp |= I2CR_MTX | I2CR_TX_NO_AK; 290 temp |= I2CR_MTX | I2CR_TX_NO_AK;
277 writeb(temp, &i2c_regs->i2cr); 291 writeb(temp, &i2c_regs->i2cr);
278 292
279 /* write slave address */ 293 /* write slave address */
280 ret = tx_byte(i2c_regs, chip << 1); 294 ret = tx_byte(i2c_regs, chip << 1);
281 if (ret < 0) 295 if (ret < 0)
282 return ret; 296 return ret;
283 297
284 while (alen--) { 298 while (alen--) {
285 ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff); 299 ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
286 if (ret < 0) 300 if (ret < 0)
287 return ret; 301 return ret;
288 } 302 }
289 return 0; 303 return 0;
290 } 304 }
291 305
292 static int i2c_idle_bus(void *base); 306 static int i2c_idle_bus(void *base);
293 307
294 static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs, 308 static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
295 uchar chip, uint addr, int alen) 309 uchar chip, uint addr, int alen)
296 { 310 {
297 int retry; 311 int retry;
298 int ret; 312 int ret;
299 for (retry = 0; retry < 3; retry++) { 313 for (retry = 0; retry < 3; retry++) {
300 ret = i2c_init_transfer_(i2c_regs, chip, addr, alen); 314 ret = i2c_init_transfer_(i2c_regs, chip, addr, alen);
301 if (ret >= 0) 315 if (ret >= 0)
302 return 0; 316 return 0;
303 i2c_imx_stop(i2c_regs); 317 i2c_imx_stop(i2c_regs);
304 if (ret == -ENODEV) 318 if (ret == -ENODEV)
305 return ret; 319 return ret;
306 320
307 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip, 321 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
308 retry); 322 retry);
309 if (ret != -ERESTART) 323 if (ret != -ERESTART)
310 /* Disable controller */ 324 /* Disable controller */
311 writeb(I2CR_IDIS, &i2c_regs->i2cr); 325 writeb(I2CR_IDIS, &i2c_regs->i2cr);
312 udelay(100); 326 udelay(100);
313 if (i2c_idle_bus(i2c_regs) < 0) 327 if (i2c_idle_bus(i2c_regs) < 0)
314 break; 328 break;
315 } 329 }
316 printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs); 330 printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs);
317 return ret; 331 return ret;
318 } 332 }
319 333
320 /* 334 /*
321 * Read data from I2C device 335 * Read data from I2C device
322 */ 336 */
323 int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf, 337 int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf,
324 int len) 338 int len)
325 { 339 {
326 int ret; 340 int ret;
327 unsigned int temp; 341 unsigned int temp;
328 int i; 342 int i;
329 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 343 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
330 344
331 ret = i2c_init_transfer(i2c_regs, chip, addr, alen); 345 ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
332 if (ret < 0) 346 if (ret < 0)
333 return ret; 347 return ret;
334 348
335 temp = readb(&i2c_regs->i2cr); 349 temp = readb(&i2c_regs->i2cr);
336 temp |= I2CR_RSTA; 350 temp |= I2CR_RSTA;
337 writeb(temp, &i2c_regs->i2cr); 351 writeb(temp, &i2c_regs->i2cr);
338 352
339 ret = tx_byte(i2c_regs, (chip << 1) | 1); 353 ret = tx_byte(i2c_regs, (chip << 1) | 1);
340 if (ret < 0) { 354 if (ret < 0) {
341 i2c_imx_stop(i2c_regs); 355 i2c_imx_stop(i2c_regs);
342 return ret; 356 return ret;
343 } 357 }
344 358
345 /* setup bus to read data */ 359 /* setup bus to read data */
346 temp = readb(&i2c_regs->i2cr); 360 temp = readb(&i2c_regs->i2cr);
347 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); 361 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
348 if (len == 1) 362 if (len == 1)
349 temp |= I2CR_TX_NO_AK; 363 temp |= I2CR_TX_NO_AK;
350 writeb(temp, &i2c_regs->i2cr); 364 writeb(temp, &i2c_regs->i2cr);
351 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 365 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
352 readb(&i2c_regs->i2dr); /* dummy read to clear ICF */ 366 readb(&i2c_regs->i2dr); /* dummy read to clear ICF */
353 367
354 /* read data */ 368 /* read data */
355 for (i = 0; i < len; i++) { 369 for (i = 0; i < len; i++) {
356 ret = wait_for_sr_state(i2c_regs, ST_IIF); 370 ret = wait_for_sr_state(i2c_regs, ST_IIF);
357 if (ret < 0) { 371 if (ret < 0) {
358 i2c_imx_stop(i2c_regs); 372 i2c_imx_stop(i2c_regs);
359 return ret; 373 return ret;
360 } 374 }
361 375
362 /* 376 /*
363 * It must generate STOP before read I2DR to prevent 377 * It must generate STOP before read I2DR to prevent
364 * controller from generating another clock cycle 378 * controller from generating another clock cycle
365 */ 379 */
366 if (i == (len - 1)) { 380 if (i == (len - 1)) {
367 i2c_imx_stop(i2c_regs); 381 i2c_imx_stop(i2c_regs);
368 } else if (i == (len - 2)) { 382 } else if (i == (len - 2)) {
369 temp = readb(&i2c_regs->i2cr); 383 temp = readb(&i2c_regs->i2cr);
370 temp |= I2CR_TX_NO_AK; 384 temp |= I2CR_TX_NO_AK;
371 writeb(temp, &i2c_regs->i2cr); 385 writeb(temp, &i2c_regs->i2cr);
372 } 386 }
373 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 387 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
374 buf[i] = readb(&i2c_regs->i2dr); 388 buf[i] = readb(&i2c_regs->i2dr);
375 } 389 }
376 i2c_imx_stop(i2c_regs); 390 i2c_imx_stop(i2c_regs);
377 return 0; 391 return 0;
378 } 392 }
379 393
380 /* 394 /*
381 * Write data to I2C device 395 * Write data to I2C device
382 */ 396 */
383 int bus_i2c_write(void *base, uchar chip, uint addr, int alen, 397 int bus_i2c_write(void *base, uchar chip, uint addr, int alen,
384 const uchar *buf, int len) 398 const uchar *buf, int len)
385 { 399 {
386 int ret; 400 int ret;
387 int i; 401 int i;
388 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 402 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
389 403
390 ret = i2c_init_transfer(i2c_regs, chip, addr, alen); 404 ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
391 if (ret < 0) 405 if (ret < 0)
392 return ret; 406 return ret;
393 407
394 for (i = 0; i < len; i++) { 408 for (i = 0; i < len; i++) {
395 ret = tx_byte(i2c_regs, buf[i]); 409 ret = tx_byte(i2c_regs, buf[i]);
396 if (ret < 0) 410 if (ret < 0)
397 break; 411 break;
398 } 412 }
399 i2c_imx_stop(i2c_regs); 413 i2c_imx_stop(i2c_regs);
400 return ret; 414 return ret;
401 } 415 }
402 416
403 struct i2c_parms { 417 struct i2c_parms {
404 void *base; 418 void *base;
405 void *idle_bus_data; 419 void *idle_bus_data;
406 int (*idle_bus_fn)(void *p); 420 int (*idle_bus_fn)(void *p);
407 }; 421 };
408 422
409 struct sram_data { 423 struct sram_data {
410 unsigned curr_i2c_bus; 424 unsigned curr_i2c_bus;
411 struct i2c_parms i2c_data[3]; 425 struct i2c_parms i2c_data[3];
412 }; 426 };
413 427
414 /* 428 /*
415 * For SPL boot some boards need i2c before SDRAM is initialized so force 429 * For SPL boot some boards need i2c before SDRAM is initialized so force
416 * variables to live in SRAM 430 * variables to live in SRAM
417 */ 431 */
418 static struct sram_data __attribute__((section(".data"))) srdata; 432 static struct sram_data __attribute__((section(".data"))) srdata;
419 433
420 static void * const i2c_bases[] = { 434 static void * const i2c_bases[] = {
421 #if defined(CONFIG_MX25) 435 #if defined(CONFIG_MX25)
422 (void *)IMX_I2C_BASE, 436 (void *)IMX_I2C_BASE,
423 (void *)IMX_I2C2_BASE, 437 (void *)IMX_I2C2_BASE,
424 (void *)IMX_I2C3_BASE 438 (void *)IMX_I2C3_BASE
425 #elif defined(CONFIG_MX27) 439 #elif defined(CONFIG_MX27)
426 (void *)IMX_I2C1_BASE, 440 (void *)IMX_I2C1_BASE,
427 (void *)IMX_I2C2_BASE 441 (void *)IMX_I2C2_BASE
428 #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \ 442 #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
429 defined(CONFIG_MX51) || defined(CONFIG_MX53) || \ 443 defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
430 defined(CONFIG_MX6) 444 defined(CONFIG_MX6)
431 (void *)I2C1_BASE_ADDR, 445 (void *)I2C1_BASE_ADDR,
432 (void *)I2C2_BASE_ADDR, 446 (void *)I2C2_BASE_ADDR,
433 (void *)I2C3_BASE_ADDR 447 (void *)I2C3_BASE_ADDR
434 #elif defined(CONFIG_VF610) 448 #elif defined(CONFIG_VF610)
435 (void *)I2C0_BASE_ADDR 449 (void *)I2C0_BASE_ADDR
436 #else 450 #else
437 #error "architecture not supported" 451 #error "architecture not supported"
438 #endif 452 #endif
439 }; 453 };
440 454
441 void *i2c_get_base(struct i2c_adapter *adap) 455 void *i2c_get_base(struct i2c_adapter *adap)
442 { 456 {
443 return i2c_bases[adap->hwadapnr]; 457 return i2c_bases[adap->hwadapnr];
444 } 458 }
445 459
446 static struct i2c_parms *i2c_get_parms(void *base) 460 static struct i2c_parms *i2c_get_parms(void *base)
447 { 461 {
448 int i = 0; 462 int i = 0;
449 struct i2c_parms *p = srdata.i2c_data; 463 struct i2c_parms *p = srdata.i2c_data;
450 while (i < ARRAY_SIZE(srdata.i2c_data)) { 464 while (i < ARRAY_SIZE(srdata.i2c_data)) {
451 if (p->base == base) 465 if (p->base == base)
452 return p; 466 return p;
453 p++; 467 p++;
454 i++; 468 i++;
455 } 469 }
456 printf("Invalid I2C base: %p\n", base); 470 printf("Invalid I2C base: %p\n", base);
457 return NULL; 471 return NULL;
458 } 472 }
459 473
460 static int i2c_idle_bus(void *base) 474 static int i2c_idle_bus(void *base)
461 { 475 {
462 struct i2c_parms *p = i2c_get_parms(base); 476 struct i2c_parms *p = i2c_get_parms(base);
463 if (p && p->idle_bus_fn) 477 if (p && p->idle_bus_fn)
464 return p->idle_bus_fn(p->idle_bus_data); 478 return p->idle_bus_fn(p->idle_bus_data);
465 return 0; 479 return 0;
466 } 480 }
467 481
468 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip, 482 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
469 uint addr, int alen, uint8_t *buffer, 483 uint addr, int alen, uint8_t *buffer,
470 int len) 484 int len)
471 { 485 {
472 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len); 486 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
473 } 487 }
474 488
475 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip, 489 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
476 uint addr, int alen, uint8_t *buffer, 490 uint addr, int alen, uint8_t *buffer,
477 int len) 491 int len)
478 { 492 {
479 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len); 493 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
480 } 494 }
481 495
482 /* 496 /*
483 * Test if a chip at a given address responds (probe the chip) 497 * Test if a chip at a given address responds (probe the chip)
484 */ 498 */
485 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip) 499 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
486 { 500 {
487 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0); 501 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
488 } 502 }
489 503
490 void bus_i2c_init(void *base, int speed, int unused, 504 void bus_i2c_init(void *base, int speed, int unused,
491 int (*idle_bus_fn)(void *p), void *idle_bus_data) 505 int (*idle_bus_fn)(void *p), void *idle_bus_data)
492 { 506 {
493 int i = 0; 507 int i = 0;
494 struct i2c_parms *p = srdata.i2c_data; 508 struct i2c_parms *p = srdata.i2c_data;
495 if (!base) 509 if (!base)
496 return; 510 return;
497 for (;;) { 511 for (;;) {
498 if (!p->base || (p->base == base)) { 512 if (!p->base || (p->base == base)) {
499 p->base = base; 513 p->base = base;
500 if (idle_bus_fn) { 514 if (idle_bus_fn) {
501 p->idle_bus_fn = idle_bus_fn; 515 p->idle_bus_fn = idle_bus_fn;
502 p->idle_bus_data = idle_bus_data; 516 p->idle_bus_data = idle_bus_data;
503 } 517 }
504 break; 518 break;
505 } 519 }
506 p++; 520 p++;
507 i++; 521 i++;
508 if (i >= ARRAY_SIZE(srdata.i2c_data)) 522 if (i >= ARRAY_SIZE(srdata.i2c_data))
509 return; 523 return;
510 } 524 }
511 bus_i2c_set_bus_speed(base, speed); 525 bus_i2c_set_bus_speed(base, speed);
512 } 526 }
513 527
514 /* 528 /*
515 * Init I2C Bus 529 * Init I2C Bus
516 */ 530 */
517 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) 531 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
518 { 532 {
519 bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL); 533 bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL);
520 } 534 }
521 535
522 /* 536 /*
523 * Set I2C Speed 537 * Set I2C Speed
524 */ 538 */
525 static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) 539 static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
526 { 540 {
527 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed); 541 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
528 } 542 }
529 543
530 /* 544 /*
531 * Register mxc i2c adapters 545 * Register mxc i2c adapters
532 */ 546 */
533 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe, 547 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
534 mxc_i2c_read, mxc_i2c_write, 548 mxc_i2c_read, mxc_i2c_write,
535 mxc_i2c_set_bus_speed, 549 mxc_i2c_set_bus_speed,
536 CONFIG_SYS_MXC_I2C1_SPEED, 550 CONFIG_SYS_MXC_I2C1_SPEED,
537 CONFIG_SYS_MXC_I2C1_SLAVE, 0) 551 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
538 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe, 552 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
539 mxc_i2c_read, mxc_i2c_write, 553 mxc_i2c_read, mxc_i2c_write,
540 mxc_i2c_set_bus_speed, 554 mxc_i2c_set_bus_speed,
541 CONFIG_SYS_MXC_I2C2_SPEED, 555 CONFIG_SYS_MXC_I2C2_SPEED,
542 CONFIG_SYS_MXC_I2C2_SLAVE, 1) 556 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
543 #if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\ 557 #if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
544 defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\ 558 defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
545 defined(CONFIG_MX6) 559 defined(CONFIG_MX6)
546 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe, 560 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
547 mxc_i2c_read, mxc_i2c_write, 561 mxc_i2c_read, mxc_i2c_write,
548 mxc_i2c_set_bus_speed, 562 mxc_i2c_set_bus_speed,
549 CONFIG_SYS_MXC_I2C3_SPEED, 563 CONFIG_SYS_MXC_I2C3_SPEED,
550 CONFIG_SYS_MXC_I2C3_SLAVE, 2) 564 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
551 #endif 565 #endif
552 566