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Commit 6c4c9a7c0fc54760370ad0b09fba11fd2bc9717f

Authored by David Müller (ELSOFT AG)
Committed by Tom Rini
1 parent 13bd4d8776
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

PATI: convert to generic board 

Signed-off-by: David Müller <d.mueller@elsoft.ch>

Showing 1 changed file with 2 additions and 0 deletions Inline Diff

include/configs/PATI.h
Diff comments   View file @ 6c4c9a7
1 /* 1 /*
2 * (C) Copyright 2003 2 * (C) Copyright 2003
3 * Denis Peter d.peter@mpl.ch 3 * Denis Peter d.peter@mpl.ch
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 /* 8 /*
9 * File: PATI.h 9 * File: PATI.h
10 */ 10 */
11 11
12 #ifndef __CONFIG_H 12 #ifndef __CONFIG_H
13 #define __CONFIG_H 13 #define __CONFIG_H
14 14
15 /* 15 /*
16 * High Level Configuration Options 16 * High Level Configuration Options
17 */ 17 */
18 18
19 #define CONFIG_MPC555 1 /* This is an MPC555 CPU */ 19 #define CONFIG_MPC555 1 /* This is an MPC555 CPU */
20 #define CONFIG_PATI 1 /* ...On a PATI board */ 20 #define CONFIG_PATI 1 /* ...On a PATI board */
21 21
22 #define CONFIG_SYS_TEXT_BASE 0xFFF00000 22 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
23 23
24 #define CONFIG_SYS_GENERIC_BOARD
25
24 /* Serial Console Configuration */ 26 /* Serial Console Configuration */
25 #define CONFIG_5xx_CONS_SCI1 27 #define CONFIG_5xx_CONS_SCI1
26 #undef CONFIG_5xx_CONS_SCI2 28 #undef CONFIG_5xx_CONS_SCI2
27 29
28 #define CONFIG_BAUDRATE 9600 30 #define CONFIG_BAUDRATE 9600
29 31
30 32
31 /* 33 /*
32 * BOOTP options 34 * BOOTP options
33 */ 35 */
34 #define CONFIG_BOOTP_BOOTFILESIZE 36 #define CONFIG_BOOTP_BOOTFILESIZE
35 #define CONFIG_BOOTP_BOOTPATH 37 #define CONFIG_BOOTP_BOOTPATH
36 #define CONFIG_BOOTP_GATEWAY 38 #define CONFIG_BOOTP_GATEWAY
37 #define CONFIG_BOOTP_HOSTNAME 39 #define CONFIG_BOOTP_HOSTNAME
38 40
39 41
40 /* 42 /*
41 * Command line configuration. 43 * Command line configuration.
42 */ 44 */
43 #define CONFIG_CMD_MEMORY 45 #define CONFIG_CMD_MEMORY
44 #define CONFIG_CMD_LOADB 46 #define CONFIG_CMD_LOADB
45 #define CONFIG_CMD_REGINFO 47 #define CONFIG_CMD_REGINFO
46 #define CONFIG_CMD_FLASH 48 #define CONFIG_CMD_FLASH
47 #define CONFIG_CMD_LOADS 49 #define CONFIG_CMD_LOADS
48 #define CONFIG_CMD_SAVEENV 50 #define CONFIG_CMD_SAVEENV
49 #define CONFIG_CMD_REGINFO 51 #define CONFIG_CMD_REGINFO
50 #define CONFIG_CMD_BDI 52 #define CONFIG_CMD_BDI
51 #define CONFIG_CMD_CONSOLE 53 #define CONFIG_CMD_CONSOLE
52 #define CONFIG_CMD_RUN 54 #define CONFIG_CMD_RUN
53 #define CONFIG_CMD_BSP 55 #define CONFIG_CMD_BSP
54 #define CONFIG_CMD_IMI 56 #define CONFIG_CMD_IMI
55 #define CONFIG_CMD_EEPROM 57 #define CONFIG_CMD_EEPROM
56 #define CONFIG_CMD_IRQ 58 #define CONFIG_CMD_IRQ
57 #define CONFIG_CMD_MISC 59 #define CONFIG_CMD_MISC
58 60
59 61
60 #if 0 62 #if 0
61 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 63 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
62 #else 64 #else
63 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 65 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
64 #endif 66 #endif
65 #define CONFIG_BOOTCOMMAND "" /* autoboot command */ 67 #define CONFIG_BOOTCOMMAND "" /* autoboot command */
66 68
67 #define CONFIG_BOOTARGS "" /* */ 69 #define CONFIG_BOOTARGS "" /* */
68 70
69 #define CONFIG_WATCHDOG /* turn on platform specific watchdog */ 71 #define CONFIG_WATCHDOG /* turn on platform specific watchdog */
70 72
71 /*#define CONFIG_STATUS_LED 1 */ /* Enable status led */ 73 /*#define CONFIG_STATUS_LED 1 */ /* Enable status led */
72 74
73 #define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ 75 #define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
74 76
75 /* 77 /*
76 * Miscellaneous configurable options 78 * Miscellaneous configurable options
77 */ 79 */
78 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ 80 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
79 #define CONFIG_PREBOOT 81 #define CONFIG_PREBOOT
80 82
81 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 83 #define CONFIG_SYS_LONGHELP /* undef to save memory */
82 #define CONFIG_SYS_PROMPT "pati=> " /* Monitor Command Prompt */ 84 #define CONFIG_SYS_PROMPT "pati=> " /* Monitor Command Prompt */
83 #if defined(CONFIG_CMD_KGDB) 85 #if defined(CONFIG_CMD_KGDB)
84 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 86 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
85 #else 87 #else
86 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 88 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
87 #endif 89 #endif
88 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 90 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
89 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 91 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
90 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 92 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
91 93
92 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */ 94 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */
93 #define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */ 95 #define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */
94 96
95 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 97 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
96 98
97 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } 99 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
98 100
99 101
100 /*********************************************************************** 102 /***********************************************************************
101 * Last Stage Init 103 * Last Stage Init
102 ***********************************************************************/ 104 ***********************************************************************/
103 #define CONFIG_LAST_STAGE_INIT 105 #define CONFIG_LAST_STAGE_INIT
104 106
105 /* 107 /*
106 * Low Level Configuration Settings 108 * Low Level Configuration Settings
107 */ 109 */
108 110
109 /* 111 /*
110 * Internal Memory Mapped (This is not the IMMR content) 112 * Internal Memory Mapped (This is not the IMMR content)
111 */ 113 */
112 #define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */ 114 #define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */
113 115
114 /* 116 /*
115 * Definitions for initial stack pointer and data area 117 * Definitions for initial stack pointer and data area
116 */ 118 */
117 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ 119 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
118 #define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ 120 #define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
119 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */ 121 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
120 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */ 122 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */
121 /* 123 /*
122 * Start addresses for the final memory configuration 124 * Start addresses for the final memory configuration
123 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 125 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
124 */ 126 */
125 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ 127 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
126 #define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */ 128 #define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */
127 #define PCI_BASE 0x03000000 /* PCI Base (CS2) */ 129 #define PCI_BASE 0x03000000 /* PCI Base (CS2) */
128 #define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ 130 #define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */
129 #define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ 131 #define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */
130 132
131 #define CONFIG_SYS_MONITOR_BASE 0xFFF00000 133 #define CONFIG_SYS_MONITOR_BASE 0xFFF00000
132 /* CONFIG_SYS_FLASH_BASE */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */ 134 /* CONFIG_SYS_FLASH_BASE */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */
133 /* This adress is given to the linker with -Ttext to */ 135 /* This adress is given to the linker with -Ttext to */
134 /* locate the text section at this adress. */ 136 /* locate the text section at this adress. */
135 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ 137 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */
136 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 138 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
137 139
138 #define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */ 140 #define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */
139 141
140 /* 142 /*
141 * For booting Linux, the board info and command line data 143 * For booting Linux, the board info and command line data
142 * have to be in the first 8 MB of memory, since this is 144 * have to be in the first 8 MB of memory, since this is
143 * the maximum mapped by the Linux kernel during initialization. 145 * the maximum mapped by the Linux kernel during initialization.
144 */ 146 */
145 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 147 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
146 148
147 149
148 /*----------------------------------------------------------------------- 150 /*-----------------------------------------------------------------------
149 * FLASH organization 151 * FLASH organization
150 *----------------------------------------------------------------------- 152 *-----------------------------------------------------------------------
151 * 153 *
152 */ 154 */
153 155
154 #define CONFIG_SYS_FLASH_PROTECTION 156 #define CONFIG_SYS_FLASH_PROTECTION
155 #define CONFIG_SYS_FLASH_EMPTY_INFO 157 #define CONFIG_SYS_FLASH_EMPTY_INFO
156 158
157 #define CONFIG_SYS_FLASH_CFI 159 #define CONFIG_SYS_FLASH_CFI
158 #define CONFIG_FLASH_CFI_DRIVER 160 #define CONFIG_FLASH_CFI_DRIVER
159 161
160 #define CONFIG_FLASH_SHOW_PROGRESS 45 162 #define CONFIG_FLASH_SHOW_PROGRESS 45
161 163
162 #define CONFIG_SYS_MAX_FLASH_BANKS 1 164 #define CONFIG_SYS_MAX_FLASH_BANKS 1
163 #define CONFIG_SYS_MAX_FLASH_SECT 128 165 #define CONFIG_SYS_MAX_FLASH_SECT 128
164 166
165 #define CONFIG_ENV_IS_IN_EEPROM 167 #define CONFIG_ENV_IS_IN_EEPROM
166 #ifdef CONFIG_ENV_IS_IN_EEPROM 168 #ifdef CONFIG_ENV_IS_IN_EEPROM
167 #define CONFIG_ENV_OFFSET 0 169 #define CONFIG_ENV_OFFSET 0
168 #define CONFIG_ENV_SIZE 2048 170 #define CONFIG_ENV_SIZE 2048
169 #endif 171 #endif
170 172
171 #undef CONFIG_ENV_IS_IN_FLASH 173 #undef CONFIG_ENV_IS_IN_FLASH
172 #ifdef CONFIG_ENV_IS_IN_FLASH 174 #ifdef CONFIG_ENV_IS_IN_FLASH
173 #define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */ 175 #define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */
174 #define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */ 176 #define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */
175 #endif 177 #endif
176 178
177 179
178 #define CONFIG_SPI 1 180 #define CONFIG_SPI 1
179 #define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */ 181 #define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */
180 #define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */ 182 #define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */
181 #define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */ 183 #define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */
182 /*----------------------------------------------------------------------- 184 /*-----------------------------------------------------------------------
183 * SYPCR - System Protection Control 185 * SYPCR - System Protection Control
184 * SYPCR can only be written once after reset! 186 * SYPCR can only be written once after reset!
185 *----------------------------------------------------------------------- 187 *-----------------------------------------------------------------------
186 * SW Watchdog freeze 188 * SW Watchdog freeze
187 */ 189 */
188 #undef CONFIG_WATCHDOG 190 #undef CONFIG_WATCHDOG
189 #if defined(CONFIG_WATCHDOG) 191 #if defined(CONFIG_WATCHDOG)
190 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 192 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
191 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 193 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
192 #else 194 #else
193 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 195 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
194 SYPCR_SWP) 196 SYPCR_SWP)
195 #endif /* CONFIG_WATCHDOG */ 197 #endif /* CONFIG_WATCHDOG */
196 198
197 /*----------------------------------------------------------------------- 199 /*-----------------------------------------------------------------------
198 * TBSCR - Time Base Status and Control 200 * TBSCR - Time Base Status and Control
199 *----------------------------------------------------------------------- 201 *-----------------------------------------------------------------------
200 * Clear Reference Interrupt Status, Timebase freezing enabled 202 * Clear Reference Interrupt Status, Timebase freezing enabled
201 */ 203 */
202 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 204 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
203 205
204 /*----------------------------------------------------------------------- 206 /*-----------------------------------------------------------------------
205 * PISCR - Periodic Interrupt Status and Control 207 * PISCR - Periodic Interrupt Status and Control
206 *----------------------------------------------------------------------- 208 *-----------------------------------------------------------------------
207 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 209 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
208 */ 210 */
209 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 211 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
210 212
211 /*----------------------------------------------------------------------- 213 /*-----------------------------------------------------------------------
212 * SCCR - System Clock and reset Control Register 214 * SCCR - System Clock and reset Control Register
213 *----------------------------------------------------------------------- 215 *-----------------------------------------------------------------------
214 * Set clock output, timebase and RTC source and divider, 216 * Set clock output, timebase and RTC source and divider,
215 * power management and some other internal clocks 217 * power management and some other internal clocks
216 */ 218 */
217 #define SCCR_MASK SCCR_EBDF00 219 #define SCCR_MASK SCCR_EBDF00
218 #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ 220 #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
219 SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000) 221 SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000)
220 222
221 /*----------------------------------------------------------------------- 223 /*-----------------------------------------------------------------------
222 * SIUMCR - SIU Module Configuration 224 * SIUMCR - SIU Module Configuration
223 *----------------------------------------------------------------------- 225 *-----------------------------------------------------------------------
224 * Data show cycle 226 * Data show cycle
225 */ 227 */
226 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ 228 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */
227 229
228 /*----------------------------------------------------------------------- 230 /*-----------------------------------------------------------------------
229 * PLPRCR - PLL, Low-Power, and Reset Control Register 231 * PLPRCR - PLL, Low-Power, and Reset Control Register
230 *----------------------------------------------------------------------- 232 *-----------------------------------------------------------------------
231 * Set all bits to 40 Mhz 233 * Set all bits to 40 Mhz
232 * 234 *
233 */ 235 */
234 #define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ 236 #define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
235 237
236 238
237 #define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) 239 #define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
238 240
239 /*----------------------------------------------------------------------- 241 /*-----------------------------------------------------------------------
240 * UMCR - UIMB Module Configuration Register 242 * UMCR - UIMB Module Configuration Register
241 *----------------------------------------------------------------------- 243 *-----------------------------------------------------------------------
242 * 244 *
243 */ 245 */
244 #define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ 246 #define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
245 247
246 /*----------------------------------------------------------------------- 248 /*-----------------------------------------------------------------------
247 * ICTRL - I-Bus Support Control Register 249 * ICTRL - I-Bus Support Control Register
248 */ 250 */
249 #define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ 251 #define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
250 252
251 /*----------------------------------------------------------------------- 253 /*-----------------------------------------------------------------------
252 * USIU - Memory Controller Register 254 * USIU - Memory Controller Register
253 *----------------------------------------------------------------------- 255 *-----------------------------------------------------------------------
254 */ 256 */
255 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA) 257 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
256 #define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */ 258 #define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */
257 /* SDRAM */ 259 /* SDRAM */
258 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) 260 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
259 #define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */ 261 #define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
260 /* PCI */ 262 /* PCI */
261 #define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA) 263 #define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
262 #define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF) 264 #define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF)
263 /* config registers: */ 265 /* config registers: */
264 #define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) 266 #define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
265 #define CONFIG_SYS_OR3_PRELIM (0xffff0000) 267 #define CONFIG_SYS_OR3_PRELIM (0xffff0000)
266 268
267 #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */ 269 #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */
268 270
269 /*----------------------------------------------------------------------- 271 /*-----------------------------------------------------------------------
270 * DER - Timer Decrementer 272 * DER - Timer Decrementer
271 *----------------------------------------------------------------------- 273 *-----------------------------------------------------------------------
272 * Initialise to zero 274 * Initialise to zero
273 */ 275 */
274 #define CONFIG_SYS_DER 0x00000000 276 #define CONFIG_SYS_DER 0x00000000
275 277
276 #define VERSION_TAG "released" 278 #define VERSION_TAG "released"
277 #define CONFIG_ISO_STRING "MEV-10084-001" 279 #define CONFIG_ISO_STRING "MEV-10084-001"
278 280
279 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG 281 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
280 282
281 #endif /* __CONFIG_H */ 283 #endif /* __CONFIG_H */
282 284