Eric Lee / smarc-uboot

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/*

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/*

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*

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*

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* 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.

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* 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.

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* Changes for multibus/multiadapter I2C support.

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* Changes for multibus/multiadapter I2C support.

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*

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*

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* This program is free software; you can redistribute it and/or

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* This program is free software; you can redistribute it and/or

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* modify it under the terms of the GNU General Public License

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* modify it under the terms of the GNU General Public License

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* Version 2 as published by the Free Software Foundation.

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* Version 2 as published by the Free Software Foundation.

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*

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*

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* This program is distributed in the hope that it will be useful,

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* This program is distributed in the hope that it will be useful,

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

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* GNU General Public License for more details.

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*

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*

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* You should have received a copy of the GNU General Public License

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* You should have received a copy of the GNU General Public License

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* along with this program; if not, write to the Free Software

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* along with this program; if not, write to the Free Software

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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,

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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,

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* MA 02111-1307 USA

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* MA 02111-1307 USA

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*/

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*/

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#include <common.h>

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#include <common.h>

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#include <command.h>

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#include <command.h>

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#include <i2c.h> /* Functional interface */

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#include <i2c.h> /* Functional interface */

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#include <asm/io.h>

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#include <asm/io.h>

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#include <asm/fsl_i2c.h> /* HW definitions */

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#include <asm/fsl_i2c.h> /* HW definitions */

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/* The maximum number of microseconds we will wait until another master has

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/* The maximum number of microseconds we will wait until another master has

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* released the bus. If not defined in the board header file, then use a

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* released the bus. If not defined in the board header file, then use a

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* generic value.

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* generic value.

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*/

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*/

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#ifndef CONFIG_I2C_MBB_TIMEOUT

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#ifndef CONFIG_I2C_MBB_TIMEOUT

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#define CONFIG_I2C_MBB_TIMEOUT 100000

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#define CONFIG_I2C_MBB_TIMEOUT 100000

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#endif

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#endif

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36

/* The maximum number of microseconds we will wait for a read or write

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/* The maximum number of microseconds we will wait for a read or write

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* operation to complete. If not defined in the board header file, then use a

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* operation to complete. If not defined in the board header file, then use a

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* generic value.

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* generic value.

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*/

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*/

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#ifndef CONFIG_I2C_TIMEOUT

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#ifndef CONFIG_I2C_TIMEOUT

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#define CONFIG_I2C_TIMEOUT 10000

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#define CONFIG_I2C_TIMEOUT 100000

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#endif

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#endif

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#define I2C_READ_BIT 1

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#define I2C_READ_BIT 1

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#define I2C_WRITE_BIT 0

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#define I2C_WRITE_BIT 0

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DECLARE_GLOBAL_DATA_PTR;

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DECLARE_GLOBAL_DATA_PTR;

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static const struct fsl_i2c *i2c_dev[4] = {

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static const struct fsl_i2c *i2c_dev[4] = {

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(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),

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(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),

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#ifdef CONFIG_SYS_FSL_I2C2_OFFSET

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#ifdef CONFIG_SYS_FSL_I2C2_OFFSET

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(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),

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(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),

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#endif

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#endif

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#ifdef CONFIG_SYS_FSL_I2C3_OFFSET

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#ifdef CONFIG_SYS_FSL_I2C3_OFFSET

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(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),

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(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),

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#endif

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#endif

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#ifdef CONFIG_SYS_FSL_I2C4_OFFSET

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#ifdef CONFIG_SYS_FSL_I2C4_OFFSET

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(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)

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(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)

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#endif

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#endif

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};

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};

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/* I2C speed map for a DFSR value of 1 */

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/* I2C speed map for a DFSR value of 1 */

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/*

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/*

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* Map I2C frequency dividers to FDR and DFSR values

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* Map I2C frequency dividers to FDR and DFSR values

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*

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*

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* This structure is used to define the elements of a table that maps I2C

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* This structure is used to define the elements of a table that maps I2C

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* frequency divider (I2C clock rate divided by I2C bus speed) to a value to be

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* frequency divider (I2C clock rate divided by I2C bus speed) to a value to be

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* programmed into the Frequency Divider Ratio (FDR) and Digital Filter

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* programmed into the Frequency Divider Ratio (FDR) and Digital Filter

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* Sampling Rate (DFSR) registers.

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* Sampling Rate (DFSR) registers.

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*

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*

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* The actual table should be defined in the board file, and it must be called

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* The actual table should be defined in the board file, and it must be called

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* fsl_i2c_speed_map[].

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* fsl_i2c_speed_map[].

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*

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*

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* The last entry of the table must have a value of {-1, X}, where X is same

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* The last entry of the table must have a value of {-1, X}, where X is same

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* FDR/DFSR values as the second-to-last entry. This guarantees that any

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* FDR/DFSR values as the second-to-last entry. This guarantees that any

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* search through the array will always find a match.

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* search through the array will always find a match.

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*

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*

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* The values of the divider must be in increasing numerical order, i.e.

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* The values of the divider must be in increasing numerical order, i.e.

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* fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.

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* fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.

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*

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*

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* For this table, the values are based on a value of 1 for the DFSR

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* For this table, the values are based on a value of 1 for the DFSR

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* register. See the application note AN2919 "Determining the I2C Frequency

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* register. See the application note AN2919 "Determining the I2C Frequency

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* Divider Ratio for SCL"

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* Divider Ratio for SCL"

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*

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*

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* ColdFire I2C frequency dividers for FDR values are different from

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* ColdFire I2C frequency dividers for FDR values are different from

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* PowerPC. The protocol to use the I2C module is still the same.

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* PowerPC. The protocol to use the I2C module is still the same.

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* A different table is defined and are based on MCF5xxx user manual.

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* A different table is defined and are based on MCF5xxx user manual.

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*

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*

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*/

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*/

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static const struct {

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static const struct {

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unsigned short divider;

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unsigned short divider;

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u8 fdr;

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u8 fdr;

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} fsl_i2c_speed_map[] = {

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} fsl_i2c_speed_map[] = {

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#ifdef __M68K__

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#ifdef __M68K__

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{20, 32}, {22, 33}, {24, 34}, {26, 35},

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{20, 32}, {22, 33}, {24, 34}, {26, 35},

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{28, 0}, {28, 36}, {30, 1}, {32, 37},

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{28, 0}, {28, 36}, {30, 1}, {32, 37},

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{34, 2}, {36, 38}, {40, 3}, {40, 39},

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{34, 2}, {36, 38}, {40, 3}, {40, 39},

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{44, 4}, {48, 5}, {48, 40}, {56, 6},

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{44, 4}, {48, 5}, {48, 40}, {56, 6},

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{56, 41}, {64, 42}, {68, 7}, {72, 43},

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{56, 41}, {64, 42}, {68, 7}, {72, 43},

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{80, 8}, {80, 44}, {88, 9}, {96, 41},

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{80, 8}, {80, 44}, {88, 9}, {96, 41},

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{104, 10}, {112, 42}, {128, 11}, {128, 43},

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{104, 10}, {112, 42}, {128, 11}, {128, 43},

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{144, 12}, {160, 13}, {160, 48}, {192, 14},

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{144, 12}, {160, 13}, {160, 48}, {192, 14},

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{192, 49}, {224, 50}, {240, 15}, {256, 51},

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{192, 49}, {224, 50}, {240, 15}, {256, 51},

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{288, 16}, {320, 17}, {320, 52}, {384, 18},

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{288, 16}, {320, 17}, {320, 52}, {384, 18},

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{384, 53}, {448, 54}, {480, 19}, {512, 55},

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{384, 53}, {448, 54}, {480, 19}, {512, 55},

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{576, 20}, {640, 21}, {640, 56}, {768, 22},

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{576, 20}, {640, 21}, {640, 56}, {768, 22},

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{768, 57}, {960, 23}, {896, 58}, {1024, 59},

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{768, 57}, {960, 23}, {896, 58}, {1024, 59},

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{1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},

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{1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},

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{1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},

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{1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},

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{2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},

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{2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},

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{-1, 31}

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{-1, 31}

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#endif

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#endif

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};

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};

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116

/**

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/**

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* Set the I2C bus speed for a given I2C device

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* Set the I2C bus speed for a given I2C device

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*

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*

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* @param dev: the I2C device

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* @param dev: the I2C device

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* @i2c_clk: I2C bus clock frequency

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* @i2c_clk: I2C bus clock frequency

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* @speed: the desired speed of the bus

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* @speed: the desired speed of the bus

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*

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*

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* The I2C device must be stopped before calling this function.

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* The I2C device must be stopped before calling this function.

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*

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*

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* The return value is the actual bus speed that is set.

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* The return value is the actual bus speed that is set.

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*/

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*/

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static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,

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static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,

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unsigned int i2c_clk, unsigned int speed)

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unsigned int i2c_clk, unsigned int speed)

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{

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{

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unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);

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unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);

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/*

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/*

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* We want to choose an FDR/DFSR that generates an I2C bus speed that

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* We want to choose an FDR/DFSR that generates an I2C bus speed that

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* is equal to or lower than the requested speed. That means that we

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* is equal to or lower than the requested speed. That means that we

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* want the first divider that is equal to or greater than the

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* want the first divider that is equal to or greater than the

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* calculated divider.

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* calculated divider.

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*/

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*/

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#ifdef __PPC__

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#ifdef __PPC__

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u8 dfsr, fdr = 0x31; /* Default if no FDR found */

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u8 dfsr, fdr = 0x31; /* Default if no FDR found */

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/* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */

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/* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */

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unsigned short a, b, ga, gb;

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unsigned short a, b, ga, gb;

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unsigned long c_div, est_div;

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unsigned long c_div, est_div;

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#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR

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#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR

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dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;

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dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;

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#else

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#else

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/* Condition 1: dfsr <= 50/T */

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/* Condition 1: dfsr <= 50/T */

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dfsr = (5 * (i2c_clk / 1000)) / 100000;

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dfsr = (5 * (i2c_clk / 1000)) / 100000;

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#endif

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#endif

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#ifdef CONFIG_FSL_I2C_CUSTOM_FDR

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#ifdef CONFIG_FSL_I2C_CUSTOM_FDR

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fdr = CONFIG_FSL_I2C_CUSTOM_FDR;

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fdr = CONFIG_FSL_I2C_CUSTOM_FDR;

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speed = i2c_clk / divider; /* Fake something */

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speed = i2c_clk / divider; /* Fake something */

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#else

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#else

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debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);

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debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);

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if (!dfsr)

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if (!dfsr)

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dfsr = 1;

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dfsr = 1;

157

158

est_div = ~0;

158

est_div = ~0;

159

for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {

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for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {

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for (gb = 0; gb < 8; gb++) {

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for (gb = 0; gb < 8; gb++) {

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b = 16 << gb;

161

b = 16 << gb;

162

c_div = b * (a + ((3*dfsr)/b)*2);

162

c_div = b * (a + ((3*dfsr)/b)*2);

163

if ((c_div > divider) && (c_div < est_div)) {

163

if ((c_div > divider) && (c_div < est_div)) {

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unsigned short bin_gb, bin_ga;

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unsigned short bin_gb, bin_ga;

165

166

est_div = c_div;

166

est_div = c_div;

167

bin_gb = gb << 2;

167

bin_gb = gb << 2;

168

bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);

168

bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);

169

fdr = bin_gb | bin_ga;

169

fdr = bin_gb | bin_ga;

170

speed = i2c_clk / est_div;

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speed = i2c_clk / est_div;

171

debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, "

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debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, "

172

"a:%d, b:%d, speed:%d\n",

172

"a:%d, b:%d, speed:%d\n",

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fdr, est_div, ga, gb, a, b, speed);

173

fdr, est_div, ga, gb, a, b, speed);

174

/* Condition 2 not accounted for */

174

/* Condition 2 not accounted for */

175

debug("Tr <= %d ns\n",

175

debug("Tr <= %d ns\n",

176

(b - 3 * dfsr) * 1000000 /

176

(b - 3 * dfsr) * 1000000 /

177

(i2c_clk / 1000));

177

(i2c_clk / 1000));

178

}

178

}

179

}

179

}

180

if (a == 20)

180

if (a == 20)

181

a += 2;

181

a += 2;

182

if (a == 24)

182

if (a == 24)

183

a += 4;

183

a += 4;

184

}

184

}

185

debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);

185

debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);

186

debug("FDR:0x%.2x, speed:%d\n", fdr, speed);

186

debug("FDR:0x%.2x, speed:%d\n", fdr, speed);

187

#endif

187

#endif

188

writeb(dfsr, &dev->dfsrr); /* set default filter */

188

writeb(dfsr, &dev->dfsrr); /* set default filter */

189

writeb(fdr, &dev->fdr); /* set bus speed */

189

writeb(fdr, &dev->fdr); /* set bus speed */

190

#else

190

#else

191

unsigned int i;

191

unsigned int i;

192

193

for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)

193

for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)

194

if (fsl_i2c_speed_map[i].divider >= divider) {

194

if (fsl_i2c_speed_map[i].divider >= divider) {

195

u8 fdr;

195

u8 fdr;

196

197

fdr = fsl_i2c_speed_map[i].fdr;

197

fdr = fsl_i2c_speed_map[i].fdr;

198

speed = i2c_clk / fsl_i2c_speed_map[i].divider;

198

speed = i2c_clk / fsl_i2c_speed_map[i].divider;

199

writeb(fdr, &dev->fdr); /* set bus speed */

199

writeb(fdr, &dev->fdr); /* set bus speed */

200

201

break;

201

break;

202

}

202

}

203

#endif

203

#endif

204

return speed;

204

return speed;

205

}

205

}

206

207

static unsigned int get_i2c_clock(int bus)

207

static unsigned int get_i2c_clock(int bus)

208

{

208

{

209

if (bus)

209

if (bus)

210

return gd->arch.i2c2_clk; /* I2C2 clock */

210

return gd->arch.i2c2_clk; /* I2C2 clock */

211

else

211

else

212

return gd->arch.i2c1_clk; /* I2C1 clock */

212

return gd->arch.i2c1_clk; /* I2C1 clock */

213

}

213

}

214

215

static int fsl_i2c_fixup(const struct fsl_i2c *dev)

215

static int fsl_i2c_fixup(const struct fsl_i2c *dev)

216

{

216

{

217

const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);

217

const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);

218

unsigned long long timeval = 0;

218

unsigned long long timeval = 0;

219

int ret = -1;

219

int ret = -1;

220

unsigned int flags = 0;

220

unsigned int flags = 0;

221

222

#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447

222

#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447

223

unsigned int svr = get_svr();

223

unsigned int svr = get_svr();

224

if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||

224

if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||

225

(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))

225

(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))

226

flags = I2C_CR_BIT6;

226

flags = I2C_CR_BIT6;

227

#endif

227

#endif

228

229

writeb(I2C_CR_MEN | I2C_CR_MSTA, &dev->cr);

229

writeb(I2C_CR_MEN | I2C_CR_MSTA, &dev->cr);

230

231

timeval = get_ticks();

231

timeval = get_ticks();

232

while (!(readb(&dev->sr) & I2C_SR_MBB)) {

232

while (!(readb(&dev->sr) & I2C_SR_MBB)) {

233

if ((get_ticks() - timeval) > timeout)

233

if ((get_ticks() - timeval) > timeout)

234

goto err;

234

goto err;

235

}

235

}

236

237

if (readb(&dev->sr) & I2C_SR_MAL) {

237

if (readb(&dev->sr) & I2C_SR_MAL) {

238

/* SDA is stuck low */

238

/* SDA is stuck low */

239

writeb(0, &dev->cr);

239

writeb(0, &dev->cr);

240

udelay(100);

240

udelay(100);

241

writeb(I2C_CR_MSTA | flags, &dev->cr);

241

writeb(I2C_CR_MSTA | flags, &dev->cr);

242

writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &dev->cr);

242

writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &dev->cr);

243

}

243

}

244

245

readb(&dev->dr);

245

readb(&dev->dr);

246

247

timeval = get_ticks();

247

timeval = get_ticks();

248

while (!(readb(&dev->sr) & I2C_SR_MIF)) {

248

while (!(readb(&dev->sr) & I2C_SR_MIF)) {

249

if ((get_ticks() - timeval) > timeout)

249

if ((get_ticks() - timeval) > timeout)

250

goto err;

250

goto err;

251

}

251

}

252

ret = 0;

252

ret = 0;

253

254

err:

254

err:

255

writeb(I2C_CR_MEN | flags, &dev->cr);

255

writeb(I2C_CR_MEN | flags, &dev->cr);

256

writeb(0, &dev->sr);

256

writeb(0, &dev->sr);

257

udelay(100);

257

udelay(100);

258

259

return ret;

259

return ret;

260

}

260

}

261

262

static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)

262

static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)

263

{

263

{

264

const struct fsl_i2c *dev;

264

const struct fsl_i2c *dev;

265

const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);

265

const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);

266

unsigned long long timeval;

266

unsigned long long timeval;

267

268

#ifdef CONFIG_SYS_I2C_INIT_BOARD

268

#ifdef CONFIG_SYS_I2C_INIT_BOARD

269

/* Call board specific i2c bus reset routine before accessing the

269

/* Call board specific i2c bus reset routine before accessing the

270

* environment, which might be in a chip on that bus. For details

270

* environment, which might be in a chip on that bus. For details

271

* about this problem see doc/I2C_Edge_Conditions.

271

* about this problem see doc/I2C_Edge_Conditions.

272

*/

272

*/

273

i2c_init_board();

273

i2c_init_board();

274

#endif

274

#endif

275

dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

275

dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

276

277

writeb(0, &dev->cr); /* stop I2C controller */

277

writeb(0, &dev->cr); /* stop I2C controller */

278

udelay(5); /* let it shutdown in peace */

278

udelay(5); /* let it shutdown in peace */

279

set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);

279

set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);

280

writeb(slaveadd << 1, &dev->adr);/* write slave address */

280

writeb(slaveadd << 1, &dev->adr);/* write slave address */

281

writeb(0x0, &dev->sr); /* clear status register */

281

writeb(0x0, &dev->sr); /* clear status register */

282

writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */

282

writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */

283

284

timeval = get_ticks();

284

timeval = get_ticks();

285

while (readb(&dev->sr) & I2C_SR_MBB) {

285

while (readb(&dev->sr) & I2C_SR_MBB) {

286

if ((get_ticks() - timeval) < timeout)

286

if ((get_ticks() - timeval) < timeout)

287

continue;

287

continue;

288

289

if (fsl_i2c_fixup(dev))

289

if (fsl_i2c_fixup(dev))

290

debug("i2c_init: BUS#%d failed to init\n",

290

debug("i2c_init: BUS#%d failed to init\n",

291

adap->hwadapnr);

291

adap->hwadapnr);

292

293

break;

293

break;

294

}

294

}

295

296

#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT

296

#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT

297

/* Call board specific i2c bus reset routine AFTER the bus has been

297

/* Call board specific i2c bus reset routine AFTER the bus has been

298

* initialized. Use either this callpoint or i2c_init_board;

298

* initialized. Use either this callpoint or i2c_init_board;

299

* which is called before i2c_init operations.

299

* which is called before i2c_init operations.

300

* For details about this problem see doc/I2C_Edge_Conditions.

300

* For details about this problem see doc/I2C_Edge_Conditions.

301

*/

301

*/

302

i2c_board_late_init();

302

i2c_board_late_init();

303

#endif

303

#endif

304

}

304

}

305

306

static int

306

static int

307

i2c_wait4bus(struct i2c_adapter *adap)

307

i2c_wait4bus(struct i2c_adapter *adap)

308

{

308

{

309

struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

309

struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

310

unsigned long long timeval = get_ticks();

310

unsigned long long timeval = get_ticks();

311

const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);

311

const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);

312

313

while (readb(&dev->sr) & I2C_SR_MBB) {

313

while (readb(&dev->sr) & I2C_SR_MBB) {

314

if ((get_ticks() - timeval) > timeout)

314

if ((get_ticks() - timeval) > timeout)

315

return -1;

315

return -1;

316

}

316

}

317

318

return 0;

318

return 0;

319

}

319

}

320

321

static __inline__ int

321

static __inline__ int

322

i2c_wait(struct i2c_adapter *adap, int write)

322

i2c_wait(struct i2c_adapter *adap, int write)

323

{

323

{

324

u32 csr;

324

u32 csr;

325

unsigned long long timeval = get_ticks();

325

unsigned long long timeval = get_ticks();

326

const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);

326

const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);

327

struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

327

struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

328

329

do {

329

do {

330

csr = readb(&dev->sr);

330

csr = readb(&dev->sr);

331

if (!(csr & I2C_SR_MIF))

331

if (!(csr & I2C_SR_MIF))

332

continue;

332

continue;

333

/* Read again to allow register to stabilise */

333

/* Read again to allow register to stabilise */

334

csr = readb(&dev->sr);

334

csr = readb(&dev->sr);

335

336

writeb(0x0, &dev->sr);

336

writeb(0x0, &dev->sr);

337

338

if (csr & I2C_SR_MAL) {

338

if (csr & I2C_SR_MAL) {

339

debug("i2c_wait: MAL\n");

339

debug("i2c_wait: MAL\n");

340

return -1;

340

return -1;

341

}

341

}

342

343

if (!(csr & I2C_SR_MCF)) {

343

if (!(csr & I2C_SR_MCF)) {

344

debug("i2c_wait: unfinished\n");

344

debug("i2c_wait: unfinished\n");

345

return -1;

345

return -1;

346

}

346

}

347

348

if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {

348

if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {

349

debug("i2c_wait: No RXACK\n");

349

debug("i2c_wait: No RXACK\n");

350

return -1;

350

return -1;

351

}

351

}

352

353

return 0;

353

return 0;

354

} while ((get_ticks() - timeval) < timeout);

354

} while ((get_ticks() - timeval) < timeout);

355

356

debug("i2c_wait: timed out\n");

356

debug("i2c_wait: timed out\n");

357

return -1;

357

return -1;

358

}

358

}

359

360

static __inline__ int

360

static __inline__ int

361

i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)

361

i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)

362

{

362

{

363

struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

363

struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

364

365

writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX

365

writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX

366

| (rsta ? I2C_CR_RSTA : 0),

366

| (rsta ? I2C_CR_RSTA : 0),

367

&device->cr);

367

&device->cr);

368

369

writeb((dev << 1) | dir, &device->dr);

369

writeb((dev << 1) | dir, &device->dr);

370

371

if (i2c_wait(adap, I2C_WRITE_BIT) < 0)

371

if (i2c_wait(adap, I2C_WRITE_BIT) < 0)

372

return 0;

372

return 0;

373

374

return 1;

374

return 1;

375

}

375

}

376

377

static __inline__ int

377

static __inline__ int

378

__i2c_write(struct i2c_adapter *adap, u8 *data, int length)

378

__i2c_write(struct i2c_adapter *adap, u8 *data, int length)

379

{

379

{

380

struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

380

struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

381

int i;

381

int i;

382

383

for (i = 0; i < length; i++) {

383

for (i = 0; i < length; i++) {

384

writeb(data[i], &dev->dr);

384

writeb(data[i], &dev->dr);

385

386

if (i2c_wait(adap, I2C_WRITE_BIT) < 0)

386

if (i2c_wait(adap, I2C_WRITE_BIT) < 0)

387

break;

387

break;

388

}

388

}

389

390

return i;

390

return i;

391

}

391

}

392

393

static __inline__ int

393

static __inline__ int

394

__i2c_read(struct i2c_adapter *adap, u8 *data, int length)

394

__i2c_read(struct i2c_adapter *adap, u8 *data, int length)

395

{

395

{

396

struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

396

struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

397

int i;

397

int i;

398

399

writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),

399

writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),

400

&dev->cr);

400

&dev->cr);

401

402

/* dummy read */

402

/* dummy read */

403

readb(&dev->dr);

403

readb(&dev->dr);

404

405

for (i = 0; i < length; i++) {

405

for (i = 0; i < length; i++) {

406

if (i2c_wait(adap, I2C_READ_BIT) < 0)

406

if (i2c_wait(adap, I2C_READ_BIT) < 0)

407

break;

407

break;

408

409

/* Generate ack on last next to last byte */

409

/* Generate ack on last next to last byte */

410

if (i == length - 2)

410

if (i == length - 2)

411

writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,

411

writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,

412

&dev->cr);

412

&dev->cr);

413

414

/* Do not generate stop on last byte */

414

/* Do not generate stop on last byte */

415

if (i == length - 1)

415

if (i == length - 1)

416

writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,

416

writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,

417

&dev->cr);

417

&dev->cr);

418

419

data[i] = readb(&dev->dr);

419

data[i] = readb(&dev->dr);

420

}

420

}

421

422

return i;

422

return i;

423

}

423

}

424

425

static int

425

static int

426

fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,

426

fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,

427

int length)

427

int length)

428

{

428

{

429

struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

429

struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

430

int i = -1; /* signal error */

430

int i = -1; /* signal error */

431

u8 *a = (u8*)&addr;

431

u8 *a = (u8*)&addr;

432

int len = alen * -1;

432

int len = alen * -1;

433

434

if (i2c_wait4bus(adap) < 0)

434

if (i2c_wait4bus(adap) < 0)

435

return -1;

435

return -1;

436

437

/* To handle the need of I2C devices that require to write few bytes

437

/* To handle the need of I2C devices that require to write few bytes

438

* (more than 4 bytes of address as in the case of else part)

438

* (more than 4 bytes of address as in the case of else part)

439

* of data before reading, Negative equivalent of length(bytes to write)

439

* of data before reading, Negative equivalent of length(bytes to write)

440

* is passed, but used the +ve part of len for writing data

440

* is passed, but used the +ve part of len for writing data

441

*/

441

*/

442

if (alen < 0) {

442

if (alen < 0) {

443

/* Generate a START and send the Address and

443

/* Generate a START and send the Address and

444

* the Tx Bytes to the slave.

444

* the Tx Bytes to the slave.

445

* "START: Address: Write bytes data[len]"

445

* "START: Address: Write bytes data[len]"

446

* IF part supports writing any number of bytes in contrast

446

* IF part supports writing any number of bytes in contrast

447

* to the else part, which supports writing address offset

447

* to the else part, which supports writing address offset

448

* of upto 4 bytes only.

448

* of upto 4 bytes only.

449

* bytes that need to be written are passed in

449

* bytes that need to be written are passed in

450

* "data", which will eventually keep the data READ,

450

* "data", which will eventually keep the data READ,

451

* after writing the len bytes out of it

451

* after writing the len bytes out of it

452

*/

452

*/

453

if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0)

453

if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0)

454

i = __i2c_write(adap, data, len);

454

i = __i2c_write(adap, data, len);

455

456

if (i != len)

456

if (i != len)

457

return -1;

457

return -1;

458

459

if (length && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0)

459

if (length && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0)

460

i = __i2c_read(adap, data, length);

460

i = __i2c_read(adap, data, length);

461

} else {

461

} else {

462

if ((!length || alen > 0) &&

462

if ((!length || alen > 0) &&

463

i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&

463

i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&

464

__i2c_write(adap, &a[4 - alen], alen) == alen)

464

__i2c_write(adap, &a[4 - alen], alen) == alen)

465

i = 0; /* No error so far */

465

i = 0; /* No error so far */

466

467

if (length &&

467

if (length &&

468

i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)

468

i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)

469

i = __i2c_read(adap, data, length);

469

i = __i2c_read(adap, data, length);

470

}

470

}

471

472

writeb(I2C_CR_MEN, &device->cr);

472

writeb(I2C_CR_MEN, &device->cr);

473

474

if (i2c_wait4bus(adap)) /* Wait until STOP */

474

if (i2c_wait4bus(adap)) /* Wait until STOP */

475

debug("i2c_read: wait4bus timed out\n");

475

debug("i2c_read: wait4bus timed out\n");

476

477

if (i == length)

477

if (i == length)

478

return 0;

478

return 0;

479

480

return -1;

480

return -1;

481

}

481

}

482

483

static int

483

static int

484

fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,

484

fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,

485

u8 *data, int length)

485

u8 *data, int length)

486

{

486

{

487

struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

487

struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

488

int i = -1; /* signal error */

488

int i = -1; /* signal error */

489

u8 *a = (u8*)&addr;

489

u8 *a = (u8*)&addr;

490

491

if (i2c_wait4bus(adap) < 0)

491

if (i2c_wait4bus(adap) < 0)

492

return -1;

492

return -1;

493

494

if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&

494

if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&

495

__i2c_write(adap, &a[4 - alen], alen) == alen) {

495

__i2c_write(adap, &a[4 - alen], alen) == alen) {

496

i = __i2c_write(adap, data, length);

496

i = __i2c_write(adap, data, length);

497

}

497

}

498

499

writeb(I2C_CR_MEN, &device->cr);

499

writeb(I2C_CR_MEN, &device->cr);

500

if (i2c_wait4bus(adap)) /* Wait until STOP */

500

if (i2c_wait4bus(adap)) /* Wait until STOP */

501

debug("i2c_write: wait4bus timed out\n");

501

debug("i2c_write: wait4bus timed out\n");

502

503

if (i == length)

503

if (i == length)

504

return 0;

504

return 0;

505

506

return -1;

506

return -1;

507

}

507

}

508

509

static int

509

static int

510

fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)

510

fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)

511

{

511

{

512

struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

512

struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

513

/* For unknow reason the controller will ACK when

513

/* For unknow reason the controller will ACK when

514

* probing for a slave with the same address, so skip

514

* probing for a slave with the same address, so skip

515

* it.

515

* it.

516

*/

516

*/

517

if (chip == (readb(&dev->adr) >> 1))

517

if (chip == (readb(&dev->adr) >> 1))

518

return -1;

518

return -1;

519

520

return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);

520

return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);

521

}

521

}

522

523

static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,

523

static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,

524

unsigned int speed)

524

unsigned int speed)

525

{

525

{

526

struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

526

struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];

527

528

writeb(0, &dev->cr); /* stop controller */

528

writeb(0, &dev->cr); /* stop controller */

529

set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);

529

set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);

530

writeb(I2C_CR_MEN, &dev->cr); /* start controller */

530

writeb(I2C_CR_MEN, &dev->cr); /* start controller */

531

532

return 0;

532

return 0;

533

}

533

}

534

535

/*

535

/*

536

* Register fsl i2c adapters

536

* Register fsl i2c adapters

537

*/

537

*/

538

U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,

538

U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,

539

fsl_i2c_write, fsl_i2c_set_bus_speed,

539

fsl_i2c_write, fsl_i2c_set_bus_speed,

540

CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,

540

CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,

541

0)

541

0)

542

#ifdef CONFIG_SYS_FSL_I2C2_OFFSET

542

#ifdef CONFIG_SYS_FSL_I2C2_OFFSET

543

U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,

543

U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,

544

fsl_i2c_write, fsl_i2c_set_bus_speed,

544

fsl_i2c_write, fsl_i2c_set_bus_speed,

545

CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,

545

CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,

546

1)

546

1)

547

#endif

547

#endif

548

#ifdef CONFIG_SYS_FSL_I2C3_OFFSET

548

#ifdef CONFIG_SYS_FSL_I2C3_OFFSET

549

U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,

549

U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,

550

fsl_i2c_write, fsl_i2c_set_bus_speed,

550

fsl_i2c_write, fsl_i2c_set_bus_speed,

551

CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,

551

CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,

552

2)

552

2)

553

#endif

553

#endif

554

#ifdef CONFIG_SYS_FSL_I2C4_OFFSET

554

#ifdef CONFIG_SYS_FSL_I2C4_OFFSET

555

U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,

555

U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,

556

fsl_i2c_write, fsl_i2c_set_bus_speed,

556

fsl_i2c_write, fsl_i2c_set_bus_speed,

557

CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,

557

CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,

558

3)

558

3)

559

#endif

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#endif

560

GITLAB

drivers/i2c/fsl_i2c: Change CONFIG_I2C_TIMEOUT to 100ms