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Commit 6ec7af8eedb5ce34979eaaeb2cf2634fe759e697

Authored by Ye Li
1 parent ec1f64b420
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

MLK-25291-2 misc: ocotp: Update OCOTP driver for iMX8MQ B2 

i.MX8MQ B2 also has fixed value in OCOTP_READ_FUSE_DATA register,
so it does not support "fuse sense" command like B1.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 357cf646bc3b9fc8d3b4f760e030545e83df2cdf)

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

drivers/misc/mxc_ocotp.c
Diff comments   View file @ 6ec7af8
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * (C) Copyright 2013 ADVANSEE 3 * (C) Copyright 2013 ADVANSEE
4 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com> 4 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
5 * 5 *
6 * Based on Dirk Behme's 6 * Based on Dirk Behme's
7 * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c, 7 * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
8 * which is based on Freescale's 8 * which is based on Freescale's
9 * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6, 9 * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
10 * which is: 10 * which is:
11 * Copyright (C) 2011 Freescale Semiconductor, Inc. 11 * Copyright (C) 2011 Freescale Semiconductor, Inc.
12 */ 12 */
13 13
14 #include <common.h> 14 #include <common.h>
15 #include <fuse.h> 15 #include <fuse.h>
16 #include <linux/errno.h> 16 #include <linux/errno.h>
17 #include <asm/io.h> 17 #include <asm/io.h>
18 #include <asm/arch/clock.h> 18 #include <asm/arch/clock.h>
19 #include <asm/arch/imx-regs.h> 19 #include <asm/arch/imx-regs.h>
20 #include <asm/mach-imx/sys_proto.h> 20 #include <asm/mach-imx/sys_proto.h>
21 21
22 #define BO_CTRL_WR_UNLOCK 16 22 #define BO_CTRL_WR_UNLOCK 16
23 #define BM_CTRL_WR_UNLOCK 0xffff0000 23 #define BM_CTRL_WR_UNLOCK 0xffff0000
24 #define BV_CTRL_WR_UNLOCK_KEY 0x3e77 24 #define BV_CTRL_WR_UNLOCK_KEY 0x3e77
25 #define BM_CTRL_ERROR 0x00000200 25 #define BM_CTRL_ERROR 0x00000200
26 #define BM_CTRL_BUSY 0x00000100 26 #define BM_CTRL_BUSY 0x00000100
27 #define BO_CTRL_ADDR 0 27 #define BO_CTRL_ADDR 0
28 #ifdef CONFIG_MX7 28 #ifdef CONFIG_MX7
29 #define BM_CTRL_ADDR 0x0000000f 29 #define BM_CTRL_ADDR 0x0000000f
30 #define BM_CTRL_RELOAD 0x00000400 30 #define BM_CTRL_RELOAD 0x00000400
31 #elif defined(CONFIG_MX7ULP) 31 #elif defined(CONFIG_MX7ULP)
32 #define BM_CTRL_ADDR 0x000000FF 32 #define BM_CTRL_ADDR 0x000000FF
33 #define BM_CTRL_RELOAD 0x00000400 33 #define BM_CTRL_RELOAD 0x00000400
34 #define BM_OUT_STATUS_DED 0x00000400 34 #define BM_OUT_STATUS_DED 0x00000400
35 #define BM_OUT_STATUS_LOCKED 0x00000800 35 #define BM_OUT_STATUS_LOCKED 0x00000800
36 #define BM_OUT_STATUS_PROGFAIL 0x00001000 36 #define BM_OUT_STATUS_PROGFAIL 0x00001000
37 #elif defined(CONFIG_IMX8M) 37 #elif defined(CONFIG_IMX8M)
38 #ifdef CONFIG_IMX8MP 38 #ifdef CONFIG_IMX8MP
39 #undef BM_CTRL_ADDR 39 #undef BM_CTRL_ADDR
40 #undef BM_CTRL_ERROR 40 #undef BM_CTRL_ERROR
41 #undef BM_CTRL_BUSY 41 #undef BM_CTRL_BUSY
42 #define BM_CTRL_ADDR 0x000001ff 42 #define BM_CTRL_ADDR 0x000001ff
43 #define BM_CTRL_ERROR 0x00000400 43 #define BM_CTRL_ERROR 0x00000400
44 #define BM_CTRL_BUSY 0x00000200 44 #define BM_CTRL_BUSY 0x00000200
45 #else 45 #else
46 #define BM_CTRL_ADDR 0x000000ff 46 #define BM_CTRL_ADDR 0x000000ff
47 #endif 47 #endif
48 #else 48 #else
49 #define BM_CTRL_ADDR 0x0000007f 49 #define BM_CTRL_ADDR 0x0000007f
50 #endif 50 #endif
51 51
52 #ifdef CONFIG_MX7 52 #ifdef CONFIG_MX7
53 #define BO_TIMING_FSOURCE 12 53 #define BO_TIMING_FSOURCE 12
54 #define BM_TIMING_FSOURCE 0x0007f000 54 #define BM_TIMING_FSOURCE 0x0007f000
55 #define BV_TIMING_FSOURCE_NS 1001 55 #define BV_TIMING_FSOURCE_NS 1001
56 #define BO_TIMING_PROG 0 56 #define BO_TIMING_PROG 0
57 #define BM_TIMING_PROG 0x00000fff 57 #define BM_TIMING_PROG 0x00000fff
58 #define BV_TIMING_PROG_US 10 58 #define BV_TIMING_PROG_US 10
59 #else 59 #else
60 #define BO_TIMING_STROBE_READ 16 60 #define BO_TIMING_STROBE_READ 16
61 #define BM_TIMING_STROBE_READ 0x003f0000 61 #define BM_TIMING_STROBE_READ 0x003f0000
62 #define BV_TIMING_STROBE_READ_NS 37 62 #define BV_TIMING_STROBE_READ_NS 37
63 #define BO_TIMING_RELAX 12 63 #define BO_TIMING_RELAX 12
64 #define BM_TIMING_RELAX 0x0000f000 64 #define BM_TIMING_RELAX 0x0000f000
65 #define BV_TIMING_RELAX_NS 17 65 #define BV_TIMING_RELAX_NS 17
66 #define BO_TIMING_STROBE_PROG 0 66 #define BO_TIMING_STROBE_PROG 0
67 #define BM_TIMING_STROBE_PROG 0x00000fff 67 #define BM_TIMING_STROBE_PROG 0x00000fff
68 #define BV_TIMING_STROBE_PROG_US 10 68 #define BV_TIMING_STROBE_PROG_US 10
69 #endif 69 #endif
70 70
71 #define BM_READ_CTRL_READ_FUSE 0x00000001 71 #define BM_READ_CTRL_READ_FUSE 0x00000001
72 72
73 #define BF(value, field) (((value) << BO_##field) & BM_##field) 73 #define BF(value, field) (((value) << BO_##field) & BM_##field)
74 74
75 #define WRITE_POSTAMBLE_US 2 75 #define WRITE_POSTAMBLE_US 2
76 76
77 #if defined(CONFIG_MX6) || defined(CONFIG_VF610) 77 #if defined(CONFIG_MX6) || defined(CONFIG_VF610)
78 #define FUSE_BANK_SIZE 0x80 78 #define FUSE_BANK_SIZE 0x80
79 #ifdef CONFIG_MX6SL 79 #ifdef CONFIG_MX6SL
80 #define FUSE_BANKS 8 80 #define FUSE_BANKS 8
81 #elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL) 81 #elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
82 #define FUSE_BANKS 9 82 #define FUSE_BANKS 9
83 #else 83 #else
84 #define FUSE_BANKS 16 84 #define FUSE_BANKS 16
85 #endif 85 #endif
86 #elif defined CONFIG_MX7 86 #elif defined CONFIG_MX7
87 #define FUSE_BANK_SIZE 0x40 87 #define FUSE_BANK_SIZE 0x40
88 #define FUSE_BANKS 16 88 #define FUSE_BANKS 16
89 #elif defined(CONFIG_MX7ULP) 89 #elif defined(CONFIG_MX7ULP)
90 #define FUSE_BANK_SIZE 0x80 90 #define FUSE_BANK_SIZE 0x80
91 #define FUSE_BANKS 31 91 #define FUSE_BANKS 31
92 #elif defined(CONFIG_IMX8M) 92 #elif defined(CONFIG_IMX8M)
93 #define FUSE_BANK_SIZE 0x40 93 #define FUSE_BANK_SIZE 0x40
94 #ifdef CONFIG_IMX8MP 94 #ifdef CONFIG_IMX8MP
95 #define FUSE_BANKS 96 95 #define FUSE_BANKS 96
96 #else 96 #else
97 #define FUSE_BANKS 64 97 #define FUSE_BANKS 64
98 #endif 98 #endif
99 #else 99 #else
100 #error "Unsupported architecture\n" 100 #error "Unsupported architecture\n"
101 #endif 101 #endif
102 102
103 #if defined(CONFIG_MX6) 103 #if defined(CONFIG_MX6)
104 104
105 /* 105 /*
106 * There is a hole in shadow registers address map of size 0x100 106 * There is a hole in shadow registers address map of size 0x100
107 * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX, 107 * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX,
108 * iMX6UL, i.MX6ULL and i.MX6SLL. 108 * iMX6UL, i.MX6ULL and i.MX6SLL.
109 * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, 109 * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
110 * we should account for this hole in address space. 110 * we should account for this hole in address space.
111 * 111 *
112 * Similar hole exists between bank 14 and bank 15 of size 112 * Similar hole exists between bank 14 and bank 15 of size
113 * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. 113 * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
114 * Note: iMX6SL has only 0-7 banks and there is no hole. 114 * Note: iMX6SL has only 0-7 banks and there is no hole.
115 * Note: iMX6UL doesn't have this one. 115 * Note: iMX6UL doesn't have this one.
116 * 116 *
117 * This function is to covert user input to physical bank index. 117 * This function is to covert user input to physical bank index.
118 * Only needed when read fuse, because we use register offset, so 118 * Only needed when read fuse, because we use register offset, so
119 * need to calculate real register offset. 119 * need to calculate real register offset.
120 * When write, no need to consider hole, always use the bank/word 120 * When write, no need to consider hole, always use the bank/word
121 * index from fuse map. 121 * index from fuse map.
122 */ 122 */
123 u32 fuse_bank_physical(int index) 123 u32 fuse_bank_physical(int index)
124 { 124 {
125 u32 phy_index; 125 u32 phy_index;
126 126
127 if (is_mx6sl() || is_mx7ulp()) { 127 if (is_mx6sl() || is_mx7ulp()) {
128 phy_index = index; 128 phy_index = index;
129 } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) { 129 } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
130 if ((is_mx6ull() || is_mx6sll()) && index == 8) 130 if ((is_mx6ull() || is_mx6sll()) && index == 8)
131 index = 7; 131 index = 7;
132 132
133 if (index >= 6) 133 if (index >= 6)
134 phy_index = fuse_bank_physical(5) + (index - 6) + 3; 134 phy_index = fuse_bank_physical(5) + (index - 6) + 3;
135 else 135 else
136 phy_index = index; 136 phy_index = index;
137 } else { 137 } else {
138 if (index >= 15) 138 if (index >= 15)
139 phy_index = fuse_bank_physical(14) + (index - 15) + 2; 139 phy_index = fuse_bank_physical(14) + (index - 15) + 2;
140 else if (index >= 6) 140 else if (index >= 6)
141 phy_index = fuse_bank_physical(5) + (index - 6) + 3; 141 phy_index = fuse_bank_physical(5) + (index - 6) + 3;
142 else 142 else
143 phy_index = index; 143 phy_index = index;
144 } 144 }
145 return phy_index; 145 return phy_index;
146 } 146 }
147 147
148 u32 fuse_word_physical(u32 bank, u32 word_index) 148 u32 fuse_word_physical(u32 bank, u32 word_index)
149 { 149 {
150 if (is_mx6ull() || is_mx6sll()) { 150 if (is_mx6ull() || is_mx6sll()) {
151 if (bank == 8) 151 if (bank == 8)
152 word_index = word_index + 4; 152 word_index = word_index + 4;
153 } 153 }
154 154
155 return word_index; 155 return word_index;
156 } 156 }
157 #else 157 #else
158 u32 fuse_bank_physical(int index) 158 u32 fuse_bank_physical(int index)
159 { 159 {
160 return index; 160 return index;
161 } 161 }
162 162
163 u32 fuse_word_physical(u32 bank, u32 word_index) 163 u32 fuse_word_physical(u32 bank, u32 word_index)
164 { 164 {
165 return word_index; 165 return word_index;
166 } 166 }
167 167
168 #endif 168 #endif
169 169
170 static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us) 170 static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
171 { 171 {
172 while (readl(&regs->ctrl) & BM_CTRL_BUSY) 172 while (readl(&regs->ctrl) & BM_CTRL_BUSY)
173 udelay(delay_us); 173 udelay(delay_us);
174 } 174 }
175 175
176 static void clear_error(struct ocotp_regs *regs) 176 static void clear_error(struct ocotp_regs *regs)
177 { 177 {
178 writel(BM_CTRL_ERROR, &regs->ctrl_clr); 178 writel(BM_CTRL_ERROR, &regs->ctrl_clr);
179 } 179 }
180 180
181 static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word, 181 static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
182 int assert, const char *caller) 182 int assert, const char *caller)
183 { 183 {
184 *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR; 184 *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;
185 185
186 if (bank >= FUSE_BANKS || 186 if (bank >= FUSE_BANKS ||
187 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 || 187 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
188 !assert) { 188 !assert) {
189 printf("mxc_ocotp %s(): Invalid argument\n", caller); 189 printf("mxc_ocotp %s(): Invalid argument\n", caller);
190 return -EINVAL; 190 return -EINVAL;
191 } 191 }
192 192
193 if (is_mx6ull() || is_mx6sll()) { 193 if (is_mx6ull() || is_mx6sll()) {
194 if ((bank == 7 || bank == 8) && 194 if ((bank == 7 || bank == 8) &&
195 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) { 195 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) {
196 printf("mxc_ocotp %s(): Invalid argument\n", caller); 196 printf("mxc_ocotp %s(): Invalid argument\n", caller);
197 return -EINVAL; 197 return -EINVAL;
198 } 198 }
199 } 199 }
200 200
201 enable_ocotp_clk(1); 201 enable_ocotp_clk(1);
202 202
203 wait_busy(*regs, 1); 203 wait_busy(*regs, 1);
204 clear_error(*regs); 204 clear_error(*regs);
205 205
206 return 0; 206 return 0;
207 } 207 }
208 208
209 static int finish_access(struct ocotp_regs *regs, const char *caller) 209 static int finish_access(struct ocotp_regs *regs, const char *caller)
210 { 210 {
211 u32 err; 211 u32 err;
212 212
213 err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR); 213 err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
214 clear_error(regs); 214 clear_error(regs);
215 215
216 #ifdef CONFIG_MX7ULP 216 #ifdef CONFIG_MX7ULP
217 /* Need to power down the OTP memory */ 217 /* Need to power down the OTP memory */
218 writel(1, &regs->pdn); 218 writel(1, &regs->pdn);
219 #endif 219 #endif
220 if (err) { 220 if (err) {
221 printf("mxc_ocotp %s(): Access protect error\n", caller); 221 printf("mxc_ocotp %s(): Access protect error\n", caller);
222 return -EIO; 222 return -EIO;
223 } 223 }
224 224
225 return 0; 225 return 0;
226 } 226 }
227 227
228 static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val, 228 static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
229 const char *caller) 229 const char *caller)
230 { 230 {
231 return prepare_access(regs, bank, word, val != NULL, caller); 231 return prepare_access(regs, bank, word, val != NULL, caller);
232 } 232 }
233 233
234 int fuse_read(u32 bank, u32 word, u32 *val) 234 int fuse_read(u32 bank, u32 word, u32 *val)
235 { 235 {
236 struct ocotp_regs *regs; 236 struct ocotp_regs *regs;
237 int ret; 237 int ret;
238 u32 phy_bank; 238 u32 phy_bank;
239 u32 phy_word; 239 u32 phy_word;
240 240
241 ret = prepare_read(&regs, bank, word, val, __func__); 241 ret = prepare_read(&regs, bank, word, val, __func__);
242 if (ret) 242 if (ret)
243 return ret; 243 return ret;
244 244
245 phy_bank = fuse_bank_physical(bank); 245 phy_bank = fuse_bank_physical(bank);
246 phy_word = fuse_word_physical(bank, word); 246 phy_word = fuse_word_physical(bank, word);
247 247
248 *val = readl(&regs->bank[phy_bank].fuse_regs[phy_word << 2]); 248 *val = readl(&regs->bank[phy_bank].fuse_regs[phy_word << 2]);
249 249
250 #ifdef CONFIG_MX7ULP 250 #ifdef CONFIG_MX7ULP
251 if (readl(&regs->out_status) & BM_OUT_STATUS_DED) { 251 if (readl(&regs->out_status) & BM_OUT_STATUS_DED) {
252 writel(BM_OUT_STATUS_DED, &regs->out_status_clr); 252 writel(BM_OUT_STATUS_DED, &regs->out_status_clr);
253 printf("mxc_ocotp %s(): fuse read wrong\n", __func__); 253 printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
254 return -EIO; 254 return -EIO;
255 } 255 }
256 #endif 256 #endif
257 return finish_access(regs, __func__); 257 return finish_access(regs, __func__);
258 } 258 }
259 259
260 #ifdef CONFIG_MX7 260 #ifdef CONFIG_MX7
261 static void set_timing(struct ocotp_regs *regs) 261 static void set_timing(struct ocotp_regs *regs)
262 { 262 {
263 u32 ipg_clk; 263 u32 ipg_clk;
264 u32 fsource, prog; 264 u32 fsource, prog;
265 u32 timing; 265 u32 timing;
266 266
267 ipg_clk = mxc_get_clock(MXC_IPG_CLK); 267 ipg_clk = mxc_get_clock(MXC_IPG_CLK);
268 268
269 fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS, 269 fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS,
270 + 1000000) + 1; 270 + 1000000) + 1;
271 prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1; 271 prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1;
272 272
273 timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG); 273 timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG);
274 274
275 clrsetbits_le32(&regs->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG, 275 clrsetbits_le32(&regs->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG,
276 timing); 276 timing);
277 } 277 }
278 #elif defined(CONFIG_MX7ULP) 278 #elif defined(CONFIG_MX7ULP)
279 static void set_timing(struct ocotp_regs *regs) 279 static void set_timing(struct ocotp_regs *regs)
280 { 280 {
281 /* No timing set for MX7ULP */ 281 /* No timing set for MX7ULP */
282 } 282 }
283 283
284 #else 284 #else
285 static void set_timing(struct ocotp_regs *regs) 285 static void set_timing(struct ocotp_regs *regs)
286 { 286 {
287 u32 ipg_clk; 287 u32 ipg_clk;
288 u32 relax, strobe_read, strobe_prog; 288 u32 relax, strobe_read, strobe_prog;
289 u32 timing; 289 u32 timing;
290 290
291 ipg_clk = mxc_get_clock(MXC_IPG_CLK); 291 ipg_clk = mxc_get_clock(MXC_IPG_CLK);
292 292
293 relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1; 293 relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
294 strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS, 294 strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
295 1000000000) + 2 * (relax + 1) - 1; 295 1000000000) + 2 * (relax + 1) - 1;
296 strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US, 296 strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US,
297 1000000) + 2 * (relax + 1) - 1; 297 1000000) + 2 * (relax + 1) - 1;
298 298
299 timing = BF(strobe_read, TIMING_STROBE_READ) | 299 timing = BF(strobe_read, TIMING_STROBE_READ) |
300 BF(relax, TIMING_RELAX) | 300 BF(relax, TIMING_RELAX) |
301 BF(strobe_prog, TIMING_STROBE_PROG); 301 BF(strobe_prog, TIMING_STROBE_PROG);
302 302
303 clrsetbits_le32(&regs->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX | 303 clrsetbits_le32(&regs->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
304 BM_TIMING_STROBE_PROG, timing); 304 BM_TIMING_STROBE_PROG, timing);
305 } 305 }
306 #endif 306 #endif
307 307
308 static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word, 308 static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
309 int write) 309 int write)
310 { 310 {
311 u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0; 311 u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
312 #ifdef CONFIG_MX7 312 #ifdef CONFIG_MX7
313 u32 addr = bank; 313 u32 addr = bank;
314 #elif defined CONFIG_IMX8M 314 #elif defined CONFIG_IMX8M
315 u32 addr = bank << 2 | word; 315 u32 addr = bank << 2 | word;
316 #else 316 #else
317 u32 addr; 317 u32 addr;
318 /* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */ 318 /* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
319 if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) { 319 if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) {
320 bank = bank - 1; 320 bank = bank - 1;
321 word += 4; 321 word += 4;
322 } 322 }
323 addr = bank << 3 | word; 323 addr = bank << 3 | word;
324 #endif 324 #endif
325 325
326 set_timing(regs); 326 set_timing(regs);
327 clrsetbits_le32(&regs->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR, 327 clrsetbits_le32(&regs->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
328 BF(wr_unlock, CTRL_WR_UNLOCK) | 328 BF(wr_unlock, CTRL_WR_UNLOCK) |
329 BF(addr, CTRL_ADDR)); 329 BF(addr, CTRL_ADDR));
330 } 330 }
331 331
332 int fuse_sense(u32 bank, u32 word, u32 *val) 332 int fuse_sense(u32 bank, u32 word, u32 *val)
333 { 333 {
334 struct ocotp_regs *regs; 334 struct ocotp_regs *regs;
335 int ret; 335 int ret;
336 336
337 if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1)) { 337 if (is_imx8mq() && (soc_rev() >= CHIP_REV_2_1)) {
338 printf("mxc_ocotp %s(): fuse sense is disabled\n", __func__); 338 printf("mxc_ocotp %s(): fuse sense is disabled\n", __func__);
339 return -EPERM; 339 return -EPERM;
340 } 340 }
341 341
342 ret = prepare_read(&regs, bank, word, val, __func__); 342 ret = prepare_read(&regs, bank, word, val, __func__);
343 if (ret) 343 if (ret)
344 return ret; 344 return ret;
345 345
346 setup_direct_access(regs, bank, word, false); 346 setup_direct_access(regs, bank, word, false);
347 writel(BM_READ_CTRL_READ_FUSE, &regs->read_ctrl); 347 writel(BM_READ_CTRL_READ_FUSE, &regs->read_ctrl);
348 wait_busy(regs, 1); 348 wait_busy(regs, 1);
349 #ifdef CONFIG_MX7 349 #ifdef CONFIG_MX7
350 *val = readl((&regs->read_fuse_data0) + (word << 2)); 350 *val = readl((&regs->read_fuse_data0) + (word << 2));
351 #else 351 #else
352 *val = readl(&regs->read_fuse_data); 352 *val = readl(&regs->read_fuse_data);
353 #endif 353 #endif
354 354
355 #ifdef CONFIG_MX7ULP 355 #ifdef CONFIG_MX7ULP
356 if (readl(&regs->out_status) & BM_OUT_STATUS_DED) { 356 if (readl(&regs->out_status) & BM_OUT_STATUS_DED) {
357 writel(BM_OUT_STATUS_DED, &regs->out_status_clr); 357 writel(BM_OUT_STATUS_DED, &regs->out_status_clr);
358 printf("mxc_ocotp %s(): fuse read wrong\n", __func__); 358 printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
359 return -EIO; 359 return -EIO;
360 } 360 }
361 #endif 361 #endif
362 362
363 return finish_access(regs, __func__); 363 return finish_access(regs, __func__);
364 } 364 }
365 365
366 static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word, 366 static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
367 const char *caller) 367 const char *caller)
368 { 368 {
369 #ifdef CONFIG_MX7ULP 369 #ifdef CONFIG_MX7ULP
370 u32 val; 370 u32 val;
371 int ret; 371 int ret;
372 372
373 /* Only bank 0 and 1 are redundancy mode, others are ECC mode */ 373 /* Only bank 0 and 1 are redundancy mode, others are ECC mode */
374 if (bank != 0 && bank != 1) { 374 if (bank != 0 && bank != 1) {
375 if ((soc_rev() < CHIP_REV_2_0) || 375 if ((soc_rev() < CHIP_REV_2_0) ||
376 ((soc_rev() >= CHIP_REV_2_0) && 376 ((soc_rev() >= CHIP_REV_2_0) &&
377 bank != 9 && bank != 10 && bank != 28)) { 377 bank != 9 && bank != 10 && bank != 28)) {
378 ret = fuse_sense(bank, word, &val); 378 ret = fuse_sense(bank, word, &val);
379 if (ret) 379 if (ret)
380 return ret; 380 return ret;
381 381
382 if (val != 0) { 382 if (val != 0) {
383 printf("mxc_ocotp: The word has been programmed, no more write\n"); 383 printf("mxc_ocotp: The word has been programmed, no more write\n");
384 return -EPERM; 384 return -EPERM;
385 } 385 }
386 } 386 }
387 } 387 }
388 #endif 388 #endif
389 389
390 return prepare_access(regs, bank, word, true, caller); 390 return prepare_access(regs, bank, word, true, caller);
391 } 391 }
392 392
393 int fuse_prog(u32 bank, u32 word, u32 val) 393 int fuse_prog(u32 bank, u32 word, u32 val)
394 { 394 {
395 struct ocotp_regs *regs; 395 struct ocotp_regs *regs;
396 int ret; 396 int ret;
397 397
398 ret = prepare_write(&regs, bank, word, __func__); 398 ret = prepare_write(&regs, bank, word, __func__);
399 if (ret) 399 if (ret)
400 return ret; 400 return ret;
401 401
402 setup_direct_access(regs, bank, word, true); 402 setup_direct_access(regs, bank, word, true);
403 #ifdef CONFIG_MX7 403 #ifdef CONFIG_MX7
404 switch (word) { 404 switch (word) {
405 case 0: 405 case 0:
406 writel(0, &regs->data1); 406 writel(0, &regs->data1);
407 writel(0, &regs->data2); 407 writel(0, &regs->data2);
408 writel(0, &regs->data3); 408 writel(0, &regs->data3);
409 writel(val, &regs->data0); 409 writel(val, &regs->data0);
410 break; 410 break;
411 case 1: 411 case 1:
412 writel(val, &regs->data1); 412 writel(val, &regs->data1);
413 writel(0, &regs->data2); 413 writel(0, &regs->data2);
414 writel(0, &regs->data3); 414 writel(0, &regs->data3);
415 writel(0, &regs->data0); 415 writel(0, &regs->data0);
416 break; 416 break;
417 case 2: 417 case 2:
418 writel(0, &regs->data1); 418 writel(0, &regs->data1);
419 writel(val, &regs->data2); 419 writel(val, &regs->data2);
420 writel(0, &regs->data3); 420 writel(0, &regs->data3);
421 writel(0, &regs->data0); 421 writel(0, &regs->data0);
422 break; 422 break;
423 case 3: 423 case 3:
424 writel(0, &regs->data1); 424 writel(0, &regs->data1);
425 writel(0, &regs->data2); 425 writel(0, &regs->data2);
426 writel(val, &regs->data3); 426 writel(val, &regs->data3);
427 writel(0, &regs->data0); 427 writel(0, &regs->data0);
428 break; 428 break;
429 } 429 }
430 wait_busy(regs, BV_TIMING_PROG_US); 430 wait_busy(regs, BV_TIMING_PROG_US);
431 #else 431 #else
432 writel(val, &regs->data); 432 writel(val, &regs->data);
433 wait_busy(regs, BV_TIMING_STROBE_PROG_US); 433 wait_busy(regs, BV_TIMING_STROBE_PROG_US);
434 #endif 434 #endif
435 udelay(WRITE_POSTAMBLE_US); 435 udelay(WRITE_POSTAMBLE_US);
436 436
437 #ifdef CONFIG_MX7ULP 437 #ifdef CONFIG_MX7ULP
438 if (readl(&regs->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) { 438 if (readl(&regs->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
439 writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), &regs->out_status_clr); 439 writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), &regs->out_status_clr);
440 printf("mxc_ocotp %s(): fuse write is failed\n", __func__); 440 printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
441 return -EIO; 441 return -EIO;
442 } 442 }
443 #endif 443 #endif
444 444
445 return finish_access(regs, __func__); 445 return finish_access(regs, __func__);
446 } 446 }
447 447
448 int fuse_override(u32 bank, u32 word, u32 val) 448 int fuse_override(u32 bank, u32 word, u32 val)
449 { 449 {
450 struct ocotp_regs *regs; 450 struct ocotp_regs *regs;
451 int ret; 451 int ret;
452 u32 phy_bank; 452 u32 phy_bank;
453 u32 phy_word; 453 u32 phy_word;
454 454
455 ret = prepare_write(&regs, bank, word, __func__); 455 ret = prepare_write(&regs, bank, word, __func__);
456 if (ret) 456 if (ret)
457 return ret; 457 return ret;
458 458
459 phy_bank = fuse_bank_physical(bank); 459 phy_bank = fuse_bank_physical(bank);
460 phy_word = fuse_word_physical(bank, word); 460 phy_word = fuse_word_physical(bank, word);
461 461
462 writel(val, &regs->bank[phy_bank].fuse_regs[phy_word << 2]); 462 writel(val, &regs->bank[phy_bank].fuse_regs[phy_word << 2]);
463 463
464 #ifdef CONFIG_MX7ULP 464 #ifdef CONFIG_MX7ULP
465 if (readl(&regs->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) { 465 if (readl(&regs->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
466 writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), &regs->out_status_clr); 466 writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), &regs->out_status_clr);
467 printf("mxc_ocotp %s(): fuse write is failed\n", __func__); 467 printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
468 return -EIO; 468 return -EIO;
469 } 469 }
470 #endif 470 #endif
471 471
472 return finish_access(regs, __func__); 472 return finish_access(regs, __func__);
473 } 473 }
474 474