Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 71d64c0e4fa5910c15eca175a8f3b0e1c1d6711c

Authored by Stefano Babic
Committed by Tom Rix
1 parent 67adcee0e0
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

serial_mxc: add support for MX51 processor 

The patch adds support for the Freescale mx51 processor.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fred Fan <fanyefeng@gmail.com>

Showing 1 changed file with 12 additions and 6 deletions Inline Diff

drivers/serial/serial_mxc.c
Diff comments   View file @ 71d64c0
1 /* 1 /*
2 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de> 2 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by 5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or 6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version. 7 * (at your option) any later version.
8 * 8 *
9 * This program is distributed in the hope that it will be useful, 9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License 14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 * 17 *
18 */ 18 */
19 19
20 #include <common.h> 20 #include <common.h>
21 #ifdef CONFIG_MX31 21 #ifdef CONFIG_MX31
22 #include <asm/arch/mx31.h> 22 #include <asm/arch/mx31.h>
23 #else 23 #else
24 #include <asm/arch/imx-regs.h> 24 #include <asm/arch/imx-regs.h>
25 #include <asm/arch/clock.h> 25 #include <asm/arch/clock.h>
26 #endif 26 #endif
27 27
28 #define __REG(x) (*((volatile u32 *)(x))) 28 #define __REG(x) (*((volatile u32 *)(x)))
29 29
30 #ifdef CONFIG_SYS_MX31_UART1 30 #ifdef CONFIG_SYS_MX31_UART1
31 #define UART_PHYS 0x43f90000 31 #define UART_PHYS 0x43f90000
32 #elif defined(CONFIG_SYS_MX31_UART2) 32 #elif defined(CONFIG_SYS_MX31_UART2)
33 #define UART_PHYS 0x43f94000 33 #define UART_PHYS 0x43f94000
34 #elif defined(CONFIG_SYS_MX31_UART3) 34 #elif defined(CONFIG_SYS_MX31_UART3)
35 #define UART_PHYS 0x5000c000 35 #define UART_PHYS 0x5000c000
36 #elif defined(CONFIG_SYS_MX31_UART4) 36 #elif defined(CONFIG_SYS_MX31_UART4)
37 #define UART_PHYS 0x43fb0000 37 #define UART_PHYS 0x43fb0000
38 #elif defined(CONFIG_SYS_MX31_UART5) 38 #elif defined(CONFIG_SYS_MX31_UART5)
39 #define UART_PHYS 0x43fb4000 39 #define UART_PHYS 0x43fb4000
40 #elif defined(CONFIG_SYS_MX27_UART1) 40 #elif defined(CONFIG_SYS_MX27_UART1)
41 #define UART_PHYS 0x1000a000 41 #define UART_PHYS 0x1000a000
42 #elif defined(CONFIG_SYS_MX27_UART2) 42 #elif defined(CONFIG_SYS_MX27_UART2)
43 #define UART_PHYS 0x1000b000 43 #define UART_PHYS 0x1000b000
44 #elif defined(CONFIG_SYS_MX27_UART3) 44 #elif defined(CONFIG_SYS_MX27_UART3)
45 #define UART_PHYS 0x1000c000 45 #define UART_PHYS 0x1000c000
46 #elif defined(CONFIG_SYS_MX27_UART4) 46 #elif defined(CONFIG_SYS_MX27_UART4)
47 #define UART_PHYS 0x1000d000 47 #define UART_PHYS 0x1000d000
48 #elif defined(CONFIG_SYS_MX27_UART5) 48 #elif defined(CONFIG_SYS_MX27_UART5)
49 #define UART_PHYS 0x1001b000 49 #define UART_PHYS 0x1001b000
50 #elif defined(CONFIG_SYS_MX27_UART6) 50 #elif defined(CONFIG_SYS_MX27_UART6)
51 #define UART_PHYS 0x1001c000 51 #define UART_PHYS 0x1001c000
52 #elif defined(CONFIG_SYS_MX51_UART1)
53 #define UART_PHYS UART1_BASE_ADDR
54 #elif defined(CONFIG_SYS_MX51_UART2)
55 #define UART_PHYS UART2_BASE_ADDR
56 #elif defined(CONFIG_SYS_MX51_UART3)
57 #define UART_PHYS UART3_BASE_ADDR
52 #else 58 #else
53 #error "define CONFIG_SYS_MX31_UARTx to use the mx31 UART driver" 59 #error "define CONFIG_SYS_MXxx_UARTx to use the MXC UART driver"
54 #endif 60 #endif
55 61
62 #ifdef CONFIG_SERIAL_MULTI
63 #warning "MXC driver does not support MULTI serials."
64 #endif
65
56 /* Register definitions */ 66 /* Register definitions */
57 #define URXD 0x0 /* Receiver Register */ 67 #define URXD 0x0 /* Receiver Register */
58 #define UTXD 0x40 /* Transmitter Register */ 68 #define UTXD 0x40 /* Transmitter Register */
59 #define UCR1 0x80 /* Control Register 1 */ 69 #define UCR1 0x80 /* Control Register 1 */
60 #define UCR2 0x84 /* Control Register 2 */ 70 #define UCR2 0x84 /* Control Register 2 */
61 #define UCR3 0x88 /* Control Register 3 */ 71 #define UCR3 0x88 /* Control Register 3 */
62 #define UCR4 0x8c /* Control Register 4 */ 72 #define UCR4 0x8c /* Control Register 4 */
63 #define UFCR 0x90 /* FIFO Control Register */ 73 #define UFCR 0x90 /* FIFO Control Register */
64 #define USR1 0x94 /* Status Register 1 */ 74 #define USR1 0x94 /* Status Register 1 */
65 #define USR2 0x98 /* Status Register 2 */ 75 #define USR2 0x98 /* Status Register 2 */
66 #define UESC 0x9c /* Escape Character Register */ 76 #define UESC 0x9c /* Escape Character Register */
67 #define UTIM 0xa0 /* Escape Timer Register */ 77 #define UTIM 0xa0 /* Escape Timer Register */
68 #define UBIR 0xa4 /* BRM Incremental Register */ 78 #define UBIR 0xa4 /* BRM Incremental Register */
69 #define UBMR 0xa8 /* BRM Modulator Register */ 79 #define UBMR 0xa8 /* BRM Modulator Register */
70 #define UBRC 0xac /* Baud Rate Count Register */ 80 #define UBRC 0xac /* Baud Rate Count Register */
71 #define UTS 0xb4 /* UART Test Register (mx31) */ 81 #define UTS 0xb4 /* UART Test Register (mx31) */
72 82
73 /* UART Control Register Bit Fields.*/ 83 /* UART Control Register Bit Fields.*/
74 #define URXD_CHARRDY (1<<15) 84 #define URXD_CHARRDY (1<<15)
75 #define URXD_ERR (1<<14) 85 #define URXD_ERR (1<<14)
76 #define URXD_OVRRUN (1<<13) 86 #define URXD_OVRRUN (1<<13)
77 #define URXD_FRMERR (1<<12) 87 #define URXD_FRMERR (1<<12)
78 #define URXD_BRK (1<<11) 88 #define URXD_BRK (1<<11)
79 #define URXD_PRERR (1<<10) 89 #define URXD_PRERR (1<<10)
80 #define URXD_RX_DATA (0xFF) 90 #define URXD_RX_DATA (0xFF)
81 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ 91 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
82 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 92 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 93 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 94 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 95 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 96 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 97 #define UCR1_IREN (1<<7) /* Infrared interface enable */
88 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 98 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 99 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90 #define UCR1_SNDBRK (1<<4) /* Send break */ 100 #define UCR1_SNDBRK (1<<4) /* Send break */
91 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 101 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ 102 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
93 #define UCR1_DOZE (1<<1) /* Doze */ 103 #define UCR1_DOZE (1<<1) /* Doze */
94 #define UCR1_UARTEN (1<<0) /* UART enabled */ 104 #define UCR1_UARTEN (1<<0) /* UART enabled */
95 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 105 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 106 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97 #define UCR2_CTSC (1<<13) /* CTS pin control */ 107 #define UCR2_CTSC (1<<13) /* CTS pin control */
98 #define UCR2_CTS (1<<12) /* Clear to send */ 108 #define UCR2_CTS (1<<12) /* Clear to send */
99 #define UCR2_ESCEN (1<<11) /* Escape enable */ 109 #define UCR2_ESCEN (1<<11) /* Escape enable */
100 #define UCR2_PREN (1<<8) /* Parity enable */ 110 #define UCR2_PREN (1<<8) /* Parity enable */
101 #define UCR2_PROE (1<<7) /* Parity odd/even */ 111 #define UCR2_PROE (1<<7) /* Parity odd/even */
102 #define UCR2_STPB (1<<6) /* Stop */ 112 #define UCR2_STPB (1<<6) /* Stop */
103 #define UCR2_WS (1<<5) /* Word size */ 113 #define UCR2_WS (1<<5) /* Word size */
104 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 114 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 115 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
106 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 116 #define UCR2_RXEN (1<<1) /* Receiver enabled */
107 #define UCR2_SRST (1<<0) /* SW reset */ 117 #define UCR2_SRST (1<<0) /* SW reset */
108 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 118 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
109 #define UCR3_PARERREN (1<<12) /* Parity enable */ 119 #define UCR3_PARERREN (1<<12) /* Parity enable */
110 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 120 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
111 #define UCR3_DSR (1<<10) /* Data set ready */ 121 #define UCR3_DSR (1<<10) /* Data set ready */
112 #define UCR3_DCD (1<<9) /* Data carrier detect */ 122 #define UCR3_DCD (1<<9) /* Data carrier detect */
113 #define UCR3_RI (1<<8) /* Ring indicator */ 123 #define UCR3_RI (1<<8) /* Ring indicator */
114 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ 124 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
115 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 125 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
116 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 126 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
117 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 127 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
118 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ 128 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
119 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ 129 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
120 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 130 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
121 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 131 #define UCR3_BPEN (1<<0) /* Preset registers enable */
122 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ 132 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
123 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 133 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
124 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 134 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 135 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 136 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127 #define UCR4_IRSC (1<<5) /* IR special case */ 137 #define UCR4_IRSC (1<<5) /* IR special case */
128 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 138 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 139 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 140 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 141 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
132 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 142 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 143 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
134 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 144 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
135 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 145 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
136 #define USR1_RTSS (1<<14) /* RTS pin status */ 146 #define USR1_RTSS (1<<14) /* RTS pin status */
137 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 147 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
138 #define USR1_RTSD (1<<12) /* RTS delta */ 148 #define USR1_RTSD (1<<12) /* RTS delta */
139 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 149 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
140 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 150 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
141 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 151 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
142 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 152 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
143 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 153 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
144 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 154 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
145 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 155 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
146 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 156 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
147 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 157 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
148 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 158 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
149 #define USR2_IDLE (1<<12) /* Idle condition */ 159 #define USR2_IDLE (1<<12) /* Idle condition */
150 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 160 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
151 #define USR2_WAKE (1<<7) /* Wake */ 161 #define USR2_WAKE (1<<7) /* Wake */
152 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 162 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
153 #define USR2_TXDC (1<<3) /* Transmitter complete */ 163 #define USR2_TXDC (1<<3) /* Transmitter complete */
154 #define USR2_BRCD (1<<2) /* Break condition */ 164 #define USR2_BRCD (1<<2) /* Break condition */
155 #define USR2_ORE (1<<1) /* Overrun error */ 165 #define USR2_ORE (1<<1) /* Overrun error */
156 #define USR2_RDR (1<<0) /* Recv data ready */ 166 #define USR2_RDR (1<<0) /* Recv data ready */
157 #define UTS_FRCPERR (1<<13) /* Force parity error */ 167 #define UTS_FRCPERR (1<<13) /* Force parity error */
158 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 168 #define UTS_LOOP (1<<12) /* Loop tx and rx */
159 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 169 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
160 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 170 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
161 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 171 #define UTS_TXFULL (1<<4) /* TxFIFO full */
162 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 172 #define UTS_RXFULL (1<<3) /* RxFIFO full */
163 #define UTS_SOFTRST (1<<0) /* Software reset */ 173 #define UTS_SOFTRST (1<<0) /* Software reset */
164 174
165 DECLARE_GLOBAL_DATA_PTR; 175 DECLARE_GLOBAL_DATA_PTR;
166 176
167 void serial_setbrg (void) 177 void serial_setbrg (void)
168 { 178 {
169 #ifdef CONFIG_MX31 179 u32 clk = imx_get_uartclk();
170 u32 clk = mx31_get_ipg_clk();
171 #else
172 u32 clk = imx_get_perclk1();
173 #endif
174 180
175 if (!gd->baudrate) 181 if (!gd->baudrate)
176 gd->baudrate = CONFIG_BAUDRATE; 182 gd->baudrate = CONFIG_BAUDRATE;
177 183
178 __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ 184 __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
179 __REG(UART_PHYS + UBIR) = 0xf; 185 __REG(UART_PHYS + UBIR) = 0xf;
180 __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); 186 __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
181 187
182 } 188 }
183 189
184 int serial_getc (void) 190 int serial_getc (void)
185 { 191 {
186 while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); 192 while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
187 return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */ 193 return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
188 } 194 }
189 195
190 void serial_putc (const char c) 196 void serial_putc (const char c)
191 { 197 {
192 __REG(UART_PHYS + UTXD) = c; 198 __REG(UART_PHYS + UTXD) = c;
193 199
194 /* wait for transmitter to be ready */ 200 /* wait for transmitter to be ready */
195 while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)); 201 while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY));
196 202
197 /* If \n, also do \r */ 203 /* If \n, also do \r */
198 if (c == '\n') 204 if (c == '\n')
199 serial_putc ('\r'); 205 serial_putc ('\r');
200 } 206 }
201 207
202 /* 208 /*
203 * Test whether a character is in the RX buffer 209 * Test whether a character is in the RX buffer
204 */ 210 */
205 int serial_tstc (void) 211 int serial_tstc (void)
206 { 212 {
207 /* If receive fifo is empty, return false */ 213 /* If receive fifo is empty, return false */
208 if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) 214 if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
209 return 0; 215 return 0;
210 return 1; 216 return 1;
211 } 217 }
212 218
213 void 219 void
214 serial_puts (const char *s) 220 serial_puts (const char *s)
215 { 221 {
216 while (*s) { 222 while (*s) {
217 serial_putc (*s++); 223 serial_putc (*s++);
218 } 224 }
219 } 225 }
220 226
221 /* 227 /*
222 * Initialise the serial port with the given baudrate. The settings 228 * Initialise the serial port with the given baudrate. The settings
223 * are always 8 data bits, no parity, 1 stop bit, no start bits. 229 * are always 8 data bits, no parity, 1 stop bit, no start bits.
224 * 230 *
225 */ 231 */
226 int serial_init (void) 232 int serial_init (void)
227 { 233 {
228 __REG(UART_PHYS + UCR1) = 0x0; 234 __REG(UART_PHYS + UCR1) = 0x0;
229 __REG(UART_PHYS + UCR2) = 0x0; 235 __REG(UART_PHYS + UCR2) = 0x0;
230 236
231 while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)); 237 while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
232 238
233 __REG(UART_PHYS + UCR3) = 0x0704; 239 __REG(UART_PHYS + UCR3) = 0x0704;
234 __REG(UART_PHYS + UCR4) = 0x8000; 240 __REG(UART_PHYS + UCR4) = 0x8000;
235 __REG(UART_PHYS + UESC) = 0x002b; 241 __REG(UART_PHYS + UESC) = 0x002b;
236 __REG(UART_PHYS + UTIM) = 0x0; 242 __REG(UART_PHYS + UTIM) = 0x0;
237 243
238 __REG(UART_PHYS + UTS) = 0x0; 244 __REG(UART_PHYS + UTS) = 0x0;
239 245
240 serial_setbrg(); 246 serial_setbrg();
241 247
242 __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; 248 __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
243 249
244 __REG(UART_PHYS + UCR1) = UCR1_UARTEN; 250 __REG(UART_PHYS + UCR1) = UCR1_UARTEN;