Eric Lee / smarc-uboot

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Commit 73545f75b66d5bd68076742f082a5b7fdfb5b086

Authored by Ian Campbell
Committed by Tom Rini
1 parent b946322670
Exists in v2017.01-smarct4x and in 48 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ahci: wait longer for link. 

I have observed timeouts on a cubietruck.

The increase to 40ms is completely arbitrary and Works For Me(tm). I
couldn't find a good reference for how long you are supposed to wait,
although googling around it seems like tens of ms rather than single
digits is more common. I don't think there is any harm in waiting a bit
longer.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

drivers/block/ahci.c
Diff comments   View file @ 73545f7
1 /* 1 /*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com> 3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com> 4 * Zhang Wei<wei.zhang@freescale.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 * 7 *
8 * with the reference on libata and ahci drvier in kernel 8 * with the reference on libata and ahci drvier in kernel
9 */ 9 */
10 #include <common.h> 10 #include <common.h>
11 11
12 #include <command.h> 12 #include <command.h>
13 #include <pci.h> 13 #include <pci.h>
14 #include <asm/processor.h> 14 #include <asm/processor.h>
15 #include <asm/errno.h> 15 #include <asm/errno.h>
16 #include <asm/io.h> 16 #include <asm/io.h>
17 #include <malloc.h> 17 #include <malloc.h>
18 #include <scsi.h> 18 #include <scsi.h>
19 #include <libata.h> 19 #include <libata.h>
20 #include <linux/ctype.h> 20 #include <linux/ctype.h>
21 #include <ahci.h> 21 #include <ahci.h>
22 22
23 static int ata_io_flush(u8 port); 23 static int ata_io_flush(u8 port);
24 24
25 struct ahci_probe_ent *probe_ent = NULL; 25 struct ahci_probe_ent *probe_ent = NULL;
26 u16 *ataid[AHCI_MAX_PORTS]; 26 u16 *ataid[AHCI_MAX_PORTS];
27 27
28 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) 28 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
29 29
30 /* 30 /*
31 * Some controllers limit number of blocks they can read/write at once. 31 * Some controllers limit number of blocks they can read/write at once.
32 * Contemporary SSD devices work much faster if the read/write size is aligned 32 * Contemporary SSD devices work much faster if the read/write size is aligned
33 * to a power of 2. Let's set default to 128 and allowing to be overwritten if 33 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
34 * needed. 34 * needed.
35 */ 35 */
36 #ifndef MAX_SATA_BLOCKS_READ_WRITE 36 #ifndef MAX_SATA_BLOCKS_READ_WRITE
37 #define MAX_SATA_BLOCKS_READ_WRITE 0x80 37 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
38 #endif 38 #endif
39 39
40 /* Maximum timeouts for each event */ 40 /* Maximum timeouts for each event */
41 #define WAIT_MS_SPINUP 20000 41 #define WAIT_MS_SPINUP 20000
42 #define WAIT_MS_DATAIO 5000 42 #define WAIT_MS_DATAIO 5000
43 #define WAIT_MS_FLUSH 5000 43 #define WAIT_MS_FLUSH 5000
44 #define WAIT_MS_LINKUP 4 44 #define WAIT_MS_LINKUP 40
45 45
46 static inline u32 ahci_port_base(u32 base, u32 port) 46 static inline u32 ahci_port_base(u32 base, u32 port)
47 { 47 {
48 return base + 0x100 + (port * 0x80); 48 return base + 0x100 + (port * 0x80);
49 } 49 }
50 50
51 51
52 static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, 52 static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
53 unsigned int port_idx) 53 unsigned int port_idx)
54 { 54 {
55 base = ahci_port_base(base, port_idx); 55 base = ahci_port_base(base, port_idx);
56 56
57 port->cmd_addr = base; 57 port->cmd_addr = base;
58 port->scr_addr = base + PORT_SCR; 58 port->scr_addr = base + PORT_SCR;
59 } 59 }
60 60
61 61
62 #define msleep(a) udelay(a * 1000) 62 #define msleep(a) udelay(a * 1000)
63 63
64 static void ahci_dcache_flush_range(unsigned begin, unsigned len) 64 static void ahci_dcache_flush_range(unsigned begin, unsigned len)
65 { 65 {
66 const unsigned long start = begin; 66 const unsigned long start = begin;
67 const unsigned long end = start + len; 67 const unsigned long end = start + len;
68 68
69 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end); 69 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
70 flush_dcache_range(start, end); 70 flush_dcache_range(start, end);
71 } 71 }
72 72
73 /* 73 /*
74 * SATA controller DMAs to physical RAM. Ensure data from the 74 * SATA controller DMAs to physical RAM. Ensure data from the
75 * controller is invalidated from dcache; next access comes from 75 * controller is invalidated from dcache; next access comes from
76 * physical RAM. 76 * physical RAM.
77 */ 77 */
78 static void ahci_dcache_invalidate_range(unsigned begin, unsigned len) 78 static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
79 { 79 {
80 const unsigned long start = begin; 80 const unsigned long start = begin;
81 const unsigned long end = start + len; 81 const unsigned long end = start + len;
82 82
83 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end); 83 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
84 invalidate_dcache_range(start, end); 84 invalidate_dcache_range(start, end);
85 } 85 }
86 86
87 /* 87 /*
88 * Ensure data for SATA controller is flushed out of dcache and 88 * Ensure data for SATA controller is flushed out of dcache and
89 * written to physical memory. 89 * written to physical memory.
90 */ 90 */
91 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp) 91 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
92 { 92 {
93 ahci_dcache_flush_range((unsigned long)pp->cmd_slot, 93 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
94 AHCI_PORT_PRIV_DMA_SZ); 94 AHCI_PORT_PRIV_DMA_SZ);
95 } 95 }
96 96
97 static int waiting_for_cmd_completed(volatile u8 *offset, 97 static int waiting_for_cmd_completed(volatile u8 *offset,
98 int timeout_msec, 98 int timeout_msec,
99 u32 sign) 99 u32 sign)
100 { 100 {
101 int i; 101 int i;
102 u32 status; 102 u32 status;
103 103
104 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) 104 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
105 msleep(1); 105 msleep(1);
106 106
107 return (i < timeout_msec) ? 0 : -1; 107 return (i < timeout_msec) ? 0 : -1;
108 } 108 }
109 109
110 int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port) 110 int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port)
111 { 111 {
112 u32 tmp; 112 u32 tmp;
113 int j = 0; 113 int j = 0;
114 u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; 114 u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
115 115
116 /* 116 /*
117 * Bring up SATA link. 117 * Bring up SATA link.
118 * SATA link bringup time is usually less than 1 ms; only very 118 * SATA link bringup time is usually less than 1 ms; only very
119 * rarely has it taken between 1-2 ms. Never seen it above 2 ms. 119 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
120 */ 120 */
121 while (j < WAIT_MS_LINKUP) { 121 while (j < WAIT_MS_LINKUP) {
122 tmp = readl(port_mmio + PORT_SCR_STAT); 122 tmp = readl(port_mmio + PORT_SCR_STAT);
123 tmp &= PORT_SCR_STAT_DET_MASK; 123 tmp &= PORT_SCR_STAT_DET_MASK;
124 if (tmp == PORT_SCR_STAT_DET_PHYRDY) 124 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
125 return 0; 125 return 0;
126 udelay(1000); 126 udelay(1000);
127 j++; 127 j++;
128 } 128 }
129 return 1; 129 return 1;
130 } 130 }
131 131
132 static int ahci_host_init(struct ahci_probe_ent *probe_ent) 132 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
133 { 133 {
134 #ifndef CONFIG_SCSI_AHCI_PLAT 134 #ifndef CONFIG_SCSI_AHCI_PLAT
135 pci_dev_t pdev = probe_ent->dev; 135 pci_dev_t pdev = probe_ent->dev;
136 u16 tmp16; 136 u16 tmp16;
137 unsigned short vendor; 137 unsigned short vendor;
138 #endif 138 #endif
139 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; 139 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
140 u32 tmp, cap_save, cmd; 140 u32 tmp, cap_save, cmd;
141 int i, j, ret; 141 int i, j, ret;
142 volatile u8 *port_mmio; 142 volatile u8 *port_mmio;
143 u32 port_map; 143 u32 port_map;
144 144
145 debug("ahci_host_init: start\n"); 145 debug("ahci_host_init: start\n");
146 146
147 cap_save = readl(mmio + HOST_CAP); 147 cap_save = readl(mmio + HOST_CAP);
148 cap_save &= ((1 << 28) | (1 << 17)); 148 cap_save &= ((1 << 28) | (1 << 17));
149 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ 149 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
150 150
151 /* global controller reset */ 151 /* global controller reset */
152 tmp = readl(mmio + HOST_CTL); 152 tmp = readl(mmio + HOST_CTL);
153 if ((tmp & HOST_RESET) == 0) 153 if ((tmp & HOST_RESET) == 0)
154 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); 154 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
155 155
156 /* reset must complete within 1 second, or 156 /* reset must complete within 1 second, or
157 * the hardware should be considered fried. 157 * the hardware should be considered fried.
158 */ 158 */
159 i = 1000; 159 i = 1000;
160 do { 160 do {
161 udelay(1000); 161 udelay(1000);
162 tmp = readl(mmio + HOST_CTL); 162 tmp = readl(mmio + HOST_CTL);
163 if (!i--) { 163 if (!i--) {
164 debug("controller reset failed (0x%x)\n", tmp); 164 debug("controller reset failed (0x%x)\n", tmp);
165 return -1; 165 return -1;
166 } 166 }
167 } while (tmp & HOST_RESET); 167 } while (tmp & HOST_RESET);
168 168
169 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); 169 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
170 writel(cap_save, mmio + HOST_CAP); 170 writel(cap_save, mmio + HOST_CAP);
171 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); 171 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
172 172
173 #ifndef CONFIG_SCSI_AHCI_PLAT 173 #ifndef CONFIG_SCSI_AHCI_PLAT
174 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); 174 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
175 175
176 if (vendor == PCI_VENDOR_ID_INTEL) { 176 if (vendor == PCI_VENDOR_ID_INTEL) {
177 u16 tmp16; 177 u16 tmp16;
178 pci_read_config_word(pdev, 0x92, &tmp16); 178 pci_read_config_word(pdev, 0x92, &tmp16);
179 tmp16 |= 0xf; 179 tmp16 |= 0xf;
180 pci_write_config_word(pdev, 0x92, tmp16); 180 pci_write_config_word(pdev, 0x92, tmp16);
181 } 181 }
182 #endif 182 #endif
183 probe_ent->cap = readl(mmio + HOST_CAP); 183 probe_ent->cap = readl(mmio + HOST_CAP);
184 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); 184 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
185 port_map = probe_ent->port_map; 185 port_map = probe_ent->port_map;
186 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; 186 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
187 187
188 debug("cap 0x%x port_map 0x%x n_ports %d\n", 188 debug("cap 0x%x port_map 0x%x n_ports %d\n",
189 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); 189 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
190 190
191 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID) 191 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
192 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID; 192 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
193 193
194 for (i = 0; i < probe_ent->n_ports; i++) { 194 for (i = 0; i < probe_ent->n_ports; i++) {
195 if (!(port_map & (1 << i))) 195 if (!(port_map & (1 << i)))
196 continue; 196 continue;
197 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); 197 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
198 port_mmio = (u8 *) probe_ent->port[i].port_mmio; 198 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
199 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); 199 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
200 200
201 /* make sure port is not active */ 201 /* make sure port is not active */
202 tmp = readl(port_mmio + PORT_CMD); 202 tmp = readl(port_mmio + PORT_CMD);
203 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | 203 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
204 PORT_CMD_FIS_RX | PORT_CMD_START)) { 204 PORT_CMD_FIS_RX | PORT_CMD_START)) {
205 debug("Port %d is active. Deactivating.\n", i); 205 debug("Port %d is active. Deactivating.\n", i);
206 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | 206 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
207 PORT_CMD_FIS_RX | PORT_CMD_START); 207 PORT_CMD_FIS_RX | PORT_CMD_START);
208 writel_with_flush(tmp, port_mmio + PORT_CMD); 208 writel_with_flush(tmp, port_mmio + PORT_CMD);
209 209
210 /* spec says 500 msecs for each bit, so 210 /* spec says 500 msecs for each bit, so
211 * this is slightly incorrect. 211 * this is slightly incorrect.
212 */ 212 */
213 msleep(500); 213 msleep(500);
214 } 214 }
215 215
216 /* Add the spinup command to whatever mode bits may 216 /* Add the spinup command to whatever mode bits may
217 * already be on in the command register. 217 * already be on in the command register.
218 */ 218 */
219 cmd = readl(port_mmio + PORT_CMD); 219 cmd = readl(port_mmio + PORT_CMD);
220 cmd |= PORT_CMD_FIS_RX; 220 cmd |= PORT_CMD_FIS_RX;
221 cmd |= PORT_CMD_SPIN_UP; 221 cmd |= PORT_CMD_SPIN_UP;
222 writel_with_flush(cmd, port_mmio + PORT_CMD); 222 writel_with_flush(cmd, port_mmio + PORT_CMD);
223 223
224 /* Bring up SATA link. */ 224 /* Bring up SATA link. */
225 ret = ahci_link_up(probe_ent, i); 225 ret = ahci_link_up(probe_ent, i);
226 if (ret) { 226 if (ret) {
227 printf("SATA link %d timeout.\n", i); 227 printf("SATA link %d timeout.\n", i);
228 continue; 228 continue;
229 } else { 229 } else {
230 debug("SATA link ok.\n"); 230 debug("SATA link ok.\n");
231 } 231 }
232 232
233 /* Clear error status */ 233 /* Clear error status */
234 tmp = readl(port_mmio + PORT_SCR_ERR); 234 tmp = readl(port_mmio + PORT_SCR_ERR);
235 if (tmp) 235 if (tmp)
236 writel(tmp, port_mmio + PORT_SCR_ERR); 236 writel(tmp, port_mmio + PORT_SCR_ERR);
237 237
238 debug("Spinning up device on SATA port %d... ", i); 238 debug("Spinning up device on SATA port %d... ", i);
239 239
240 j = 0; 240 j = 0;
241 while (j < WAIT_MS_SPINUP) { 241 while (j < WAIT_MS_SPINUP) {
242 tmp = readl(port_mmio + PORT_TFDATA); 242 tmp = readl(port_mmio + PORT_TFDATA);
243 if (!(tmp & (ATA_BUSY | ATA_DRQ))) 243 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
244 break; 244 break;
245 udelay(1000); 245 udelay(1000);
246 tmp = readl(port_mmio + PORT_SCR_STAT); 246 tmp = readl(port_mmio + PORT_SCR_STAT);
247 tmp &= PORT_SCR_STAT_DET_MASK; 247 tmp &= PORT_SCR_STAT_DET_MASK;
248 if (tmp == PORT_SCR_STAT_DET_PHYRDY) 248 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
249 break; 249 break;
250 j++; 250 j++;
251 } 251 }
252 252
253 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK; 253 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
254 if (tmp == PORT_SCR_STAT_DET_COMINIT) { 254 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
255 debug("SATA link %d down (COMINIT received), retrying...\n", i); 255 debug("SATA link %d down (COMINIT received), retrying...\n", i);
256 i--; 256 i--;
257 continue; 257 continue;
258 } 258 }
259 259
260 printf("Target spinup took %d ms.\n", j); 260 printf("Target spinup took %d ms.\n", j);
261 if (j == WAIT_MS_SPINUP) 261 if (j == WAIT_MS_SPINUP)
262 debug("timeout.\n"); 262 debug("timeout.\n");
263 else 263 else
264 debug("ok.\n"); 264 debug("ok.\n");
265 265
266 tmp = readl(port_mmio + PORT_SCR_ERR); 266 tmp = readl(port_mmio + PORT_SCR_ERR);
267 debug("PORT_SCR_ERR 0x%x\n", tmp); 267 debug("PORT_SCR_ERR 0x%x\n", tmp);
268 writel(tmp, port_mmio + PORT_SCR_ERR); 268 writel(tmp, port_mmio + PORT_SCR_ERR);
269 269
270 /* ack any pending irq events for this port */ 270 /* ack any pending irq events for this port */
271 tmp = readl(port_mmio + PORT_IRQ_STAT); 271 tmp = readl(port_mmio + PORT_IRQ_STAT);
272 debug("PORT_IRQ_STAT 0x%x\n", tmp); 272 debug("PORT_IRQ_STAT 0x%x\n", tmp);
273 if (tmp) 273 if (tmp)
274 writel(tmp, port_mmio + PORT_IRQ_STAT); 274 writel(tmp, port_mmio + PORT_IRQ_STAT);
275 275
276 writel(1 << i, mmio + HOST_IRQ_STAT); 276 writel(1 << i, mmio + HOST_IRQ_STAT);
277 277
278 /* set irq mask (enables interrupts) */ 278 /* set irq mask (enables interrupts) */
279 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); 279 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
280 280
281 /* register linkup ports */ 281 /* register linkup ports */
282 tmp = readl(port_mmio + PORT_SCR_STAT); 282 tmp = readl(port_mmio + PORT_SCR_STAT);
283 debug("SATA port %d status: 0x%x\n", i, tmp); 283 debug("SATA port %d status: 0x%x\n", i, tmp);
284 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY) 284 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
285 probe_ent->link_port_map |= (0x01 << i); 285 probe_ent->link_port_map |= (0x01 << i);
286 } 286 }
287 287
288 tmp = readl(mmio + HOST_CTL); 288 tmp = readl(mmio + HOST_CTL);
289 debug("HOST_CTL 0x%x\n", tmp); 289 debug("HOST_CTL 0x%x\n", tmp);
290 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 290 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
291 tmp = readl(mmio + HOST_CTL); 291 tmp = readl(mmio + HOST_CTL);
292 debug("HOST_CTL 0x%x\n", tmp); 292 debug("HOST_CTL 0x%x\n", tmp);
293 #ifndef CONFIG_SCSI_AHCI_PLAT 293 #ifndef CONFIG_SCSI_AHCI_PLAT
294 pci_read_config_word(pdev, PCI_COMMAND, &tmp16); 294 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
295 tmp |= PCI_COMMAND_MASTER; 295 tmp |= PCI_COMMAND_MASTER;
296 pci_write_config_word(pdev, PCI_COMMAND, tmp16); 296 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
297 #endif 297 #endif
298 return 0; 298 return 0;
299 } 299 }
300 300
301 301
302 static void ahci_print_info(struct ahci_probe_ent *probe_ent) 302 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
303 { 303 {
304 #ifndef CONFIG_SCSI_AHCI_PLAT 304 #ifndef CONFIG_SCSI_AHCI_PLAT
305 pci_dev_t pdev = probe_ent->dev; 305 pci_dev_t pdev = probe_ent->dev;
306 u16 cc; 306 u16 cc;
307 #endif 307 #endif
308 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; 308 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
309 u32 vers, cap, cap2, impl, speed; 309 u32 vers, cap, cap2, impl, speed;
310 const char *speed_s; 310 const char *speed_s;
311 const char *scc_s; 311 const char *scc_s;
312 312
313 vers = readl(mmio + HOST_VERSION); 313 vers = readl(mmio + HOST_VERSION);
314 cap = probe_ent->cap; 314 cap = probe_ent->cap;
315 cap2 = readl(mmio + HOST_CAP2); 315 cap2 = readl(mmio + HOST_CAP2);
316 impl = probe_ent->port_map; 316 impl = probe_ent->port_map;
317 317
318 speed = (cap >> 20) & 0xf; 318 speed = (cap >> 20) & 0xf;
319 if (speed == 1) 319 if (speed == 1)
320 speed_s = "1.5"; 320 speed_s = "1.5";
321 else if (speed == 2) 321 else if (speed == 2)
322 speed_s = "3"; 322 speed_s = "3";
323 else if (speed == 3) 323 else if (speed == 3)
324 speed_s = "6"; 324 speed_s = "6";
325 else 325 else
326 speed_s = "?"; 326 speed_s = "?";
327 327
328 #ifdef CONFIG_SCSI_AHCI_PLAT 328 #ifdef CONFIG_SCSI_AHCI_PLAT
329 scc_s = "SATA"; 329 scc_s = "SATA";
330 #else 330 #else
331 pci_read_config_word(pdev, 0x0a, &cc); 331 pci_read_config_word(pdev, 0x0a, &cc);
332 if (cc == 0x0101) 332 if (cc == 0x0101)
333 scc_s = "IDE"; 333 scc_s = "IDE";
334 else if (cc == 0x0106) 334 else if (cc == 0x0106)
335 scc_s = "SATA"; 335 scc_s = "SATA";
336 else if (cc == 0x0104) 336 else if (cc == 0x0104)
337 scc_s = "RAID"; 337 scc_s = "RAID";
338 else 338 else
339 scc_s = "unknown"; 339 scc_s = "unknown";
340 #endif 340 #endif
341 printf("AHCI %02x%02x.%02x%02x " 341 printf("AHCI %02x%02x.%02x%02x "
342 "%u slots %u ports %s Gbps 0x%x impl %s mode\n", 342 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
343 (vers >> 24) & 0xff, 343 (vers >> 24) & 0xff,
344 (vers >> 16) & 0xff, 344 (vers >> 16) & 0xff,
345 (vers >> 8) & 0xff, 345 (vers >> 8) & 0xff,
346 vers & 0xff, 346 vers & 0xff,
347 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); 347 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
348 348
349 printf("flags: " 349 printf("flags: "
350 "%s%s%s%s%s%s%s" 350 "%s%s%s%s%s%s%s"
351 "%s%s%s%s%s%s%s" 351 "%s%s%s%s%s%s%s"
352 "%s%s%s%s%s%s\n", 352 "%s%s%s%s%s%s\n",
353 cap & (1 << 31) ? "64bit " : "", 353 cap & (1 << 31) ? "64bit " : "",
354 cap & (1 << 30) ? "ncq " : "", 354 cap & (1 << 30) ? "ncq " : "",
355 cap & (1 << 28) ? "ilck " : "", 355 cap & (1 << 28) ? "ilck " : "",
356 cap & (1 << 27) ? "stag " : "", 356 cap & (1 << 27) ? "stag " : "",
357 cap & (1 << 26) ? "pm " : "", 357 cap & (1 << 26) ? "pm " : "",
358 cap & (1 << 25) ? "led " : "", 358 cap & (1 << 25) ? "led " : "",
359 cap & (1 << 24) ? "clo " : "", 359 cap & (1 << 24) ? "clo " : "",
360 cap & (1 << 19) ? "nz " : "", 360 cap & (1 << 19) ? "nz " : "",
361 cap & (1 << 18) ? "only " : "", 361 cap & (1 << 18) ? "only " : "",
362 cap & (1 << 17) ? "pmp " : "", 362 cap & (1 << 17) ? "pmp " : "",
363 cap & (1 << 16) ? "fbss " : "", 363 cap & (1 << 16) ? "fbss " : "",
364 cap & (1 << 15) ? "pio " : "", 364 cap & (1 << 15) ? "pio " : "",
365 cap & (1 << 14) ? "slum " : "", 365 cap & (1 << 14) ? "slum " : "",
366 cap & (1 << 13) ? "part " : "", 366 cap & (1 << 13) ? "part " : "",
367 cap & (1 << 7) ? "ccc " : "", 367 cap & (1 << 7) ? "ccc " : "",
368 cap & (1 << 6) ? "ems " : "", 368 cap & (1 << 6) ? "ems " : "",
369 cap & (1 << 5) ? "sxs " : "", 369 cap & (1 << 5) ? "sxs " : "",
370 cap2 & (1 << 2) ? "apst " : "", 370 cap2 & (1 << 2) ? "apst " : "",
371 cap2 & (1 << 1) ? "nvmp " : "", 371 cap2 & (1 << 1) ? "nvmp " : "",
372 cap2 & (1 << 0) ? "boh " : ""); 372 cap2 & (1 << 0) ? "boh " : "");
373 } 373 }
374 374
375 #ifndef CONFIG_SCSI_AHCI_PLAT 375 #ifndef CONFIG_SCSI_AHCI_PLAT
376 static int ahci_init_one(pci_dev_t pdev) 376 static int ahci_init_one(pci_dev_t pdev)
377 { 377 {
378 u16 vendor; 378 u16 vendor;
379 int rc; 379 int rc;
380 380
381 probe_ent = malloc(sizeof(struct ahci_probe_ent)); 381 probe_ent = malloc(sizeof(struct ahci_probe_ent));
382 if (!probe_ent) { 382 if (!probe_ent) {
383 printf("%s: No memory for probe_ent\n", __func__); 383 printf("%s: No memory for probe_ent\n", __func__);
384 return -ENOMEM; 384 return -ENOMEM;
385 } 385 }
386 386
387 memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); 387 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
388 probe_ent->dev = pdev; 388 probe_ent->dev = pdev;
389 389
390 probe_ent->host_flags = ATA_FLAG_SATA 390 probe_ent->host_flags = ATA_FLAG_SATA
391 | ATA_FLAG_NO_LEGACY 391 | ATA_FLAG_NO_LEGACY
392 | ATA_FLAG_MMIO 392 | ATA_FLAG_MMIO
393 | ATA_FLAG_PIO_DMA 393 | ATA_FLAG_PIO_DMA
394 | ATA_FLAG_NO_ATAPI; 394 | ATA_FLAG_NO_ATAPI;
395 probe_ent->pio_mask = 0x1f; 395 probe_ent->pio_mask = 0x1f;
396 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ 396 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
397 397
398 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base); 398 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
399 debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base); 399 debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
400 400
401 /* Take from kernel: 401 /* Take from kernel:
402 * JMicron-specific fixup: 402 * JMicron-specific fixup:
403 * make sure we're in AHCI mode 403 * make sure we're in AHCI mode
404 */ 404 */
405 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); 405 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
406 if (vendor == 0x197b) 406 if (vendor == 0x197b)
407 pci_write_config_byte(pdev, 0x41, 0xa1); 407 pci_write_config_byte(pdev, 0x41, 0xa1);
408 408
409 /* initialize adapter */ 409 /* initialize adapter */
410 rc = ahci_host_init(probe_ent); 410 rc = ahci_host_init(probe_ent);
411 if (rc) 411 if (rc)
412 goto err_out; 412 goto err_out;
413 413
414 ahci_print_info(probe_ent); 414 ahci_print_info(probe_ent);
415 415
416 return 0; 416 return 0;
417 417
418 err_out: 418 err_out:
419 return rc; 419 return rc;
420 } 420 }
421 #endif 421 #endif
422 422
423 #define MAX_DATA_BYTE_COUNT (4*1024*1024) 423 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
424 424
425 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) 425 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
426 { 426 {
427 struct ahci_ioports *pp = &(probe_ent->port[port]); 427 struct ahci_ioports *pp = &(probe_ent->port[port]);
428 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; 428 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
429 u32 sg_count; 429 u32 sg_count;
430 int i; 430 int i;
431 431
432 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; 432 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
433 if (sg_count > AHCI_MAX_SG) { 433 if (sg_count > AHCI_MAX_SG) {
434 printf("Error:Too much sg!\n"); 434 printf("Error:Too much sg!\n");
435 return -1; 435 return -1;
436 } 436 }
437 437
438 for (i = 0; i < sg_count; i++) { 438 for (i = 0; i < sg_count; i++) {
439 ahci_sg->addr = 439 ahci_sg->addr =
440 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); 440 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
441 ahci_sg->addr_hi = 0; 441 ahci_sg->addr_hi = 0;
442 ahci_sg->flags_size = cpu_to_le32(0x3fffff & 442 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
443 (buf_len < MAX_DATA_BYTE_COUNT 443 (buf_len < MAX_DATA_BYTE_COUNT
444 ? (buf_len - 1) 444 ? (buf_len - 1)
445 : (MAX_DATA_BYTE_COUNT - 1))); 445 : (MAX_DATA_BYTE_COUNT - 1)));
446 ahci_sg++; 446 ahci_sg++;
447 buf_len -= MAX_DATA_BYTE_COUNT; 447 buf_len -= MAX_DATA_BYTE_COUNT;
448 } 448 }
449 449
450 return sg_count; 450 return sg_count;
451 } 451 }
452 452
453 453
454 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) 454 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
455 { 455 {
456 pp->cmd_slot->opts = cpu_to_le32(opts); 456 pp->cmd_slot->opts = cpu_to_le32(opts);
457 pp->cmd_slot->status = 0; 457 pp->cmd_slot->status = 0;
458 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); 458 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
459 pp->cmd_slot->tbl_addr_hi = 0; 459 pp->cmd_slot->tbl_addr_hi = 0;
460 } 460 }
461 461
462 462
463 #ifdef CONFIG_AHCI_SETFEATURES_XFER 463 #ifdef CONFIG_AHCI_SETFEATURES_XFER
464 static void ahci_set_feature(u8 port) 464 static void ahci_set_feature(u8 port)
465 { 465 {
466 struct ahci_ioports *pp = &(probe_ent->port[port]); 466 struct ahci_ioports *pp = &(probe_ent->port[port]);
467 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; 467 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
468 u32 cmd_fis_len = 5; /* five dwords */ 468 u32 cmd_fis_len = 5; /* five dwords */
469 u8 fis[20]; 469 u8 fis[20];
470 470
471 /* set feature */ 471 /* set feature */
472 memset(fis, 0, sizeof(fis)); 472 memset(fis, 0, sizeof(fis));
473 fis[0] = 0x27; 473 fis[0] = 0x27;
474 fis[1] = 1 << 7; 474 fis[1] = 1 << 7;
475 fis[2] = ATA_CMD_SET_FEATURES; 475 fis[2] = ATA_CMD_SET_FEATURES;
476 fis[3] = SETFEATURES_XFER; 476 fis[3] = SETFEATURES_XFER;
477 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; 477 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
478 478
479 memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis)); 479 memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));
480 ahci_fill_cmd_slot(pp, cmd_fis_len); 480 ahci_fill_cmd_slot(pp, cmd_fis_len);
481 ahci_dcache_flush_sata_cmd(pp); 481 ahci_dcache_flush_sata_cmd(pp);
482 writel(1, port_mmio + PORT_CMD_ISSUE); 482 writel(1, port_mmio + PORT_CMD_ISSUE);
483 readl(port_mmio + PORT_CMD_ISSUE); 483 readl(port_mmio + PORT_CMD_ISSUE);
484 484
485 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 485 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
486 WAIT_MS_DATAIO, 0x1)) { 486 WAIT_MS_DATAIO, 0x1)) {
487 printf("set feature error on port %d!\n", port); 487 printf("set feature error on port %d!\n", port);
488 } 488 }
489 } 489 }
490 #endif 490 #endif
491 491
492 492
493 static int ahci_port_start(u8 port) 493 static int ahci_port_start(u8 port)
494 { 494 {
495 struct ahci_ioports *pp = &(probe_ent->port[port]); 495 struct ahci_ioports *pp = &(probe_ent->port[port]);
496 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; 496 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
497 u32 port_status; 497 u32 port_status;
498 u32 mem; 498 u32 mem;
499 499
500 debug("Enter start port: %d\n", port); 500 debug("Enter start port: %d\n", port);
501 port_status = readl(port_mmio + PORT_SCR_STAT); 501 port_status = readl(port_mmio + PORT_SCR_STAT);
502 debug("Port %d status: %x\n", port, port_status); 502 debug("Port %d status: %x\n", port, port_status);
503 if ((port_status & 0xf) != 0x03) { 503 if ((port_status & 0xf) != 0x03) {
504 printf("No Link on this port!\n"); 504 printf("No Link on this port!\n");
505 return -1; 505 return -1;
506 } 506 }
507 507
508 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); 508 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
509 if (!mem) { 509 if (!mem) {
510 free(pp); 510 free(pp);
511 printf("%s: No mem for table!\n", __func__); 511 printf("%s: No mem for table!\n", __func__);
512 return -ENOMEM; 512 return -ENOMEM;
513 } 513 }
514 514
515 mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ 515 mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
516 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); 516 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
517 517
518 /* 518 /*
519 * First item in chunk of DMA memory: 32-slot command table, 519 * First item in chunk of DMA memory: 32-slot command table,
520 * 32 bytes each in size 520 * 32 bytes each in size
521 */ 521 */
522 pp->cmd_slot = 522 pp->cmd_slot =
523 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem); 523 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
524 debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot); 524 debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
525 mem += (AHCI_CMD_SLOT_SZ + 224); 525 mem += (AHCI_CMD_SLOT_SZ + 224);
526 526
527 /* 527 /*
528 * Second item: Received-FIS area 528 * Second item: Received-FIS area
529 */ 529 */
530 pp->rx_fis = virt_to_phys((void *)mem); 530 pp->rx_fis = virt_to_phys((void *)mem);
531 mem += AHCI_RX_FIS_SZ; 531 mem += AHCI_RX_FIS_SZ;
532 532
533 /* 533 /*
534 * Third item: data area for storing a single command 534 * Third item: data area for storing a single command
535 * and its scatter-gather table 535 * and its scatter-gather table
536 */ 536 */
537 pp->cmd_tbl = virt_to_phys((void *)mem); 537 pp->cmd_tbl = virt_to_phys((void *)mem);
538 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); 538 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
539 539
540 mem += AHCI_CMD_TBL_HDR; 540 mem += AHCI_CMD_TBL_HDR;
541 pp->cmd_tbl_sg = 541 pp->cmd_tbl_sg =
542 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); 542 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
543 543
544 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); 544 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
545 545
546 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); 546 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
547 547
548 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | 548 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
549 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | 549 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
550 PORT_CMD_START, port_mmio + PORT_CMD); 550 PORT_CMD_START, port_mmio + PORT_CMD);
551 551
552 debug("Exit start port %d\n", port); 552 debug("Exit start port %d\n", port);
553 553
554 return 0; 554 return 0;
555 } 555 }
556 556
557 557
558 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, 558 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
559 int buf_len, u8 is_write) 559 int buf_len, u8 is_write)
560 { 560 {
561 561
562 struct ahci_ioports *pp = &(probe_ent->port[port]); 562 struct ahci_ioports *pp = &(probe_ent->port[port]);
563 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; 563 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
564 u32 opts; 564 u32 opts;
565 u32 port_status; 565 u32 port_status;
566 int sg_count; 566 int sg_count;
567 567
568 debug("Enter %s: for port %d\n", __func__, port); 568 debug("Enter %s: for port %d\n", __func__, port);
569 569
570 if (port > probe_ent->n_ports) { 570 if (port > probe_ent->n_ports) {
571 printf("Invalid port number %d\n", port); 571 printf("Invalid port number %d\n", port);
572 return -1; 572 return -1;
573 } 573 }
574 574
575 port_status = readl(port_mmio + PORT_SCR_STAT); 575 port_status = readl(port_mmio + PORT_SCR_STAT);
576 if ((port_status & 0xf) != 0x03) { 576 if ((port_status & 0xf) != 0x03) {
577 debug("No Link on port %d!\n", port); 577 debug("No Link on port %d!\n", port);
578 return -1; 578 return -1;
579 } 579 }
580 580
581 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); 581 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
582 582
583 sg_count = ahci_fill_sg(port, buf, buf_len); 583 sg_count = ahci_fill_sg(port, buf, buf_len);
584 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6); 584 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
585 ahci_fill_cmd_slot(pp, opts); 585 ahci_fill_cmd_slot(pp, opts);
586 586
587 ahci_dcache_flush_sata_cmd(pp); 587 ahci_dcache_flush_sata_cmd(pp);
588 ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len); 588 ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);
589 589
590 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); 590 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
591 591
592 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 592 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
593 WAIT_MS_DATAIO, 0x1)) { 593 WAIT_MS_DATAIO, 0x1)) {
594 printf("timeout exit!\n"); 594 printf("timeout exit!\n");
595 return -1; 595 return -1;
596 } 596 }
597 597
598 ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len); 598 ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);
599 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status); 599 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
600 600
601 return 0; 601 return 0;
602 } 602 }
603 603
604 604
605 static char *ata_id_strcpy(u16 *target, u16 *src, int len) 605 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
606 { 606 {
607 int i; 607 int i;
608 for (i = 0; i < len / 2; i++) 608 for (i = 0; i < len / 2; i++)
609 target[i] = swab16(src[i]); 609 target[i] = swab16(src[i]);
610 return (char *)target; 610 return (char *)target;
611 } 611 }
612 612
613 /* 613 /*
614 * SCSI INQUIRY command operation. 614 * SCSI INQUIRY command operation.
615 */ 615 */
616 static int ata_scsiop_inquiry(ccb *pccb) 616 static int ata_scsiop_inquiry(ccb *pccb)
617 { 617 {
618 static const u8 hdr[] = { 618 static const u8 hdr[] = {
619 0, 619 0,
620 0, 620 0,
621 0x5, /* claim SPC-3 version compatibility */ 621 0x5, /* claim SPC-3 version compatibility */
622 2, 622 2,
623 95 - 4, 623 95 - 4,
624 }; 624 };
625 u8 fis[20]; 625 u8 fis[20];
626 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS); 626 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
627 u8 port; 627 u8 port;
628 628
629 /* Clean ccb data buffer */ 629 /* Clean ccb data buffer */
630 memset(pccb->pdata, 0, pccb->datalen); 630 memset(pccb->pdata, 0, pccb->datalen);
631 631
632 memcpy(pccb->pdata, hdr, sizeof(hdr)); 632 memcpy(pccb->pdata, hdr, sizeof(hdr));
633 633
634 if (pccb->datalen <= 35) 634 if (pccb->datalen <= 35)
635 return 0; 635 return 0;
636 636
637 memset(fis, 0, sizeof(fis)); 637 memset(fis, 0, sizeof(fis));
638 /* Construct the FIS */ 638 /* Construct the FIS */
639 fis[0] = 0x27; /* Host to device FIS. */ 639 fis[0] = 0x27; /* Host to device FIS. */
640 fis[1] = 1 << 7; /* Command FIS. */ 640 fis[1] = 1 << 7; /* Command FIS. */
641 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */ 641 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
642 642
643 /* Read id from sata */ 643 /* Read id from sata */
644 port = pccb->target; 644 port = pccb->target;
645 645
646 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid, 646 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid,
647 ATA_ID_WORDS * 2, 0)) { 647 ATA_ID_WORDS * 2, 0)) {
648 debug("scsi_ahci: SCSI inquiry command failure.\n"); 648 debug("scsi_ahci: SCSI inquiry command failure.\n");
649 return -EIO; 649 return -EIO;
650 } 650 }
651 651
652 if (ataid[port]) 652 if (ataid[port])
653 free(ataid[port]); 653 free(ataid[port]);
654 ataid[port] = tmpid; 654 ataid[port] = tmpid;
655 ata_swap_buf_le16(tmpid, ATA_ID_WORDS); 655 ata_swap_buf_le16(tmpid, ATA_ID_WORDS);
656 656
657 memcpy(&pccb->pdata[8], "ATA ", 8); 657 memcpy(&pccb->pdata[8], "ATA ", 8);
658 ata_id_strcpy((u16 *) &pccb->pdata[16], &tmpid[ATA_ID_PROD], 16); 658 ata_id_strcpy((u16 *) &pccb->pdata[16], &tmpid[ATA_ID_PROD], 16);
659 ata_id_strcpy((u16 *) &pccb->pdata[32], &tmpid[ATA_ID_FW_REV], 4); 659 ata_id_strcpy((u16 *) &pccb->pdata[32], &tmpid[ATA_ID_FW_REV], 4);
660 660
661 #ifdef DEBUG 661 #ifdef DEBUG
662 ata_dump_id(tmpid); 662 ata_dump_id(tmpid);
663 #endif 663 #endif
664 return 0; 664 return 0;
665 } 665 }
666 666
667 667
668 /* 668 /*
669 * SCSI READ10/WRITE10 command operation. 669 * SCSI READ10/WRITE10 command operation.
670 */ 670 */
671 static int ata_scsiop_read_write(ccb *pccb, u8 is_write) 671 static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
672 { 672 {
673 u32 lba = 0; 673 u32 lba = 0;
674 u16 blocks = 0; 674 u16 blocks = 0;
675 u8 fis[20]; 675 u8 fis[20];
676 u8 *user_buffer = pccb->pdata; 676 u8 *user_buffer = pccb->pdata;
677 u32 user_buffer_size = pccb->datalen; 677 u32 user_buffer_size = pccb->datalen;
678 678
679 /* Retrieve the base LBA number from the ccb structure. */ 679 /* Retrieve the base LBA number from the ccb structure. */
680 memcpy(&lba, pccb->cmd + 2, sizeof(lba)); 680 memcpy(&lba, pccb->cmd + 2, sizeof(lba));
681 lba = be32_to_cpu(lba); 681 lba = be32_to_cpu(lba);
682 682
683 /* 683 /*
684 * And the number of blocks. 684 * And the number of blocks.
685 * 685 *
686 * For 10-byte and 16-byte SCSI R/W commands, transfer 686 * For 10-byte and 16-byte SCSI R/W commands, transfer
687 * length 0 means transfer 0 block of data. 687 * length 0 means transfer 0 block of data.
688 * However, for ATA R/W commands, sector count 0 means 688 * However, for ATA R/W commands, sector count 0 means
689 * 256 or 65536 sectors, not 0 sectors as in SCSI. 689 * 256 or 65536 sectors, not 0 sectors as in SCSI.
690 * 690 *
691 * WARNING: one or two older ATA drives treat 0 as 0... 691 * WARNING: one or two older ATA drives treat 0 as 0...
692 */ 692 */
693 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); 693 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
694 694
695 debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n", 695 debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
696 is_write ? "write" : "read", (unsigned)lba, blocks); 696 is_write ? "write" : "read", (unsigned)lba, blocks);
697 697
698 /* Preset the FIS */ 698 /* Preset the FIS */
699 memset(fis, 0, sizeof(fis)); 699 memset(fis, 0, sizeof(fis));
700 fis[0] = 0x27; /* Host to device FIS. */ 700 fis[0] = 0x27; /* Host to device FIS. */
701 fis[1] = 1 << 7; /* Command FIS. */ 701 fis[1] = 1 << 7; /* Command FIS. */
702 /* Command byte (read/write). */ 702 /* Command byte (read/write). */
703 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT; 703 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
704 704
705 while (blocks) { 705 while (blocks) {
706 u16 now_blocks; /* number of blocks per iteration */ 706 u16 now_blocks; /* number of blocks per iteration */
707 u32 transfer_size; /* number of bytes per iteration */ 707 u32 transfer_size; /* number of bytes per iteration */
708 708
709 now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks); 709 now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
710 710
711 transfer_size = ATA_SECT_SIZE * now_blocks; 711 transfer_size = ATA_SECT_SIZE * now_blocks;
712 if (transfer_size > user_buffer_size) { 712 if (transfer_size > user_buffer_size) {
713 printf("scsi_ahci: Error: buffer too small.\n"); 713 printf("scsi_ahci: Error: buffer too small.\n");
714 return -EIO; 714 return -EIO;
715 } 715 }
716 716
717 /* LBA48 SATA command but only use 32bit address range within 717 /* LBA48 SATA command but only use 32bit address range within
718 * that. The next smaller command range (28bit) is too small. 718 * that. The next smaller command range (28bit) is too small.
719 */ 719 */
720 fis[4] = (lba >> 0) & 0xff; 720 fis[4] = (lba >> 0) & 0xff;
721 fis[5] = (lba >> 8) & 0xff; 721 fis[5] = (lba >> 8) & 0xff;
722 fis[6] = (lba >> 16) & 0xff; 722 fis[6] = (lba >> 16) & 0xff;
723 fis[7] = 1 << 6; /* device reg: set LBA mode */ 723 fis[7] = 1 << 6; /* device reg: set LBA mode */
724 fis[8] = ((lba >> 24) & 0xff); 724 fis[8] = ((lba >> 24) & 0xff);
725 fis[3] = 0xe0; /* features */ 725 fis[3] = 0xe0; /* features */
726 726
727 /* Block (sector) count */ 727 /* Block (sector) count */
728 fis[12] = (now_blocks >> 0) & 0xff; 728 fis[12] = (now_blocks >> 0) & 0xff;
729 fis[13] = (now_blocks >> 8) & 0xff; 729 fis[13] = (now_blocks >> 8) & 0xff;
730 730
731 /* Read/Write from ahci */ 731 /* Read/Write from ahci */
732 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis), 732 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
733 user_buffer, user_buffer_size, 733 user_buffer, user_buffer_size,
734 is_write)) { 734 is_write)) {
735 debug("scsi_ahci: SCSI %s10 command failure.\n", 735 debug("scsi_ahci: SCSI %s10 command failure.\n",
736 is_write ? "WRITE" : "READ"); 736 is_write ? "WRITE" : "READ");
737 return -EIO; 737 return -EIO;
738 } 738 }
739 739
740 /* If this transaction is a write, do a following flush. 740 /* If this transaction is a write, do a following flush.
741 * Writes in u-boot are so rare, and the logic to know when is 741 * Writes in u-boot are so rare, and the logic to know when is
742 * the last write and do a flush only there is sufficiently 742 * the last write and do a flush only there is sufficiently
743 * difficult. Just do a flush after every write. This incurs, 743 * difficult. Just do a flush after every write. This incurs,
744 * usually, one extra flush when the rare writes do happen. 744 * usually, one extra flush when the rare writes do happen.
745 */ 745 */
746 if (is_write) { 746 if (is_write) {
747 if (-EIO == ata_io_flush(pccb->target)) 747 if (-EIO == ata_io_flush(pccb->target))
748 return -EIO; 748 return -EIO;
749 } 749 }
750 user_buffer += transfer_size; 750 user_buffer += transfer_size;
751 user_buffer_size -= transfer_size; 751 user_buffer_size -= transfer_size;
752 blocks -= now_blocks; 752 blocks -= now_blocks;
753 lba += now_blocks; 753 lba += now_blocks;
754 } 754 }
755 755
756 return 0; 756 return 0;
757 } 757 }
758 758
759 759
760 /* 760 /*
761 * SCSI READ CAPACITY10 command operation. 761 * SCSI READ CAPACITY10 command operation.
762 */ 762 */
763 static int ata_scsiop_read_capacity10(ccb *pccb) 763 static int ata_scsiop_read_capacity10(ccb *pccb)
764 { 764 {
765 u32 cap; 765 u32 cap;
766 u64 cap64; 766 u64 cap64;
767 u32 block_size; 767 u32 block_size;
768 768
769 if (!ataid[pccb->target]) { 769 if (!ataid[pccb->target]) {
770 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " 770 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
771 "\tNo ATA info!\n" 771 "\tNo ATA info!\n"
772 "\tPlease run SCSI commmand INQUIRY firstly!\n"); 772 "\tPlease run SCSI commmand INQUIRY firstly!\n");
773 return -EPERM; 773 return -EPERM;
774 } 774 }
775 775
776 cap64 = ata_id_n_sectors(ataid[pccb->target]); 776 cap64 = ata_id_n_sectors(ataid[pccb->target]);
777 if (cap64 > 0x100000000ULL) 777 if (cap64 > 0x100000000ULL)
778 cap64 = 0xffffffff; 778 cap64 = 0xffffffff;
779 779
780 cap = cpu_to_be32(cap64); 780 cap = cpu_to_be32(cap64);
781 memcpy(pccb->pdata, &cap, sizeof(cap)); 781 memcpy(pccb->pdata, &cap, sizeof(cap));
782 782
783 block_size = cpu_to_be32((u32)512); 783 block_size = cpu_to_be32((u32)512);
784 memcpy(&pccb->pdata[4], &block_size, 4); 784 memcpy(&pccb->pdata[4], &block_size, 4);
785 785
786 return 0; 786 return 0;
787 } 787 }
788 788
789 789
790 /* 790 /*
791 * SCSI READ CAPACITY16 command operation. 791 * SCSI READ CAPACITY16 command operation.
792 */ 792 */
793 static int ata_scsiop_read_capacity16(ccb *pccb) 793 static int ata_scsiop_read_capacity16(ccb *pccb)
794 { 794 {
795 u64 cap; 795 u64 cap;
796 u64 block_size; 796 u64 block_size;
797 797
798 if (!ataid[pccb->target]) { 798 if (!ataid[pccb->target]) {
799 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. " 799 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
800 "\tNo ATA info!\n" 800 "\tNo ATA info!\n"
801 "\tPlease run SCSI commmand INQUIRY firstly!\n"); 801 "\tPlease run SCSI commmand INQUIRY firstly!\n");
802 return -EPERM; 802 return -EPERM;
803 } 803 }
804 804
805 cap = ata_id_n_sectors(ataid[pccb->target]); 805 cap = ata_id_n_sectors(ataid[pccb->target]);
806 cap = cpu_to_be64(cap); 806 cap = cpu_to_be64(cap);
807 memcpy(pccb->pdata, &cap, sizeof(cap)); 807 memcpy(pccb->pdata, &cap, sizeof(cap));
808 808
809 block_size = cpu_to_be64((u64)512); 809 block_size = cpu_to_be64((u64)512);
810 memcpy(&pccb->pdata[8], &block_size, 8); 810 memcpy(&pccb->pdata[8], &block_size, 8);
811 811
812 return 0; 812 return 0;
813 } 813 }
814 814
815 815
816 /* 816 /*
817 * SCSI TEST UNIT READY command operation. 817 * SCSI TEST UNIT READY command operation.
818 */ 818 */
819 static int ata_scsiop_test_unit_ready(ccb *pccb) 819 static int ata_scsiop_test_unit_ready(ccb *pccb)
820 { 820 {
821 return (ataid[pccb->target]) ? 0 : -EPERM; 821 return (ataid[pccb->target]) ? 0 : -EPERM;
822 } 822 }
823 823
824 824
825 int scsi_exec(ccb *pccb) 825 int scsi_exec(ccb *pccb)
826 { 826 {
827 int ret; 827 int ret;
828 828
829 switch (pccb->cmd[0]) { 829 switch (pccb->cmd[0]) {
830 case SCSI_READ10: 830 case SCSI_READ10:
831 ret = ata_scsiop_read_write(pccb, 0); 831 ret = ata_scsiop_read_write(pccb, 0);
832 break; 832 break;
833 case SCSI_WRITE10: 833 case SCSI_WRITE10:
834 ret = ata_scsiop_read_write(pccb, 1); 834 ret = ata_scsiop_read_write(pccb, 1);
835 break; 835 break;
836 case SCSI_RD_CAPAC10: 836 case SCSI_RD_CAPAC10:
837 ret = ata_scsiop_read_capacity10(pccb); 837 ret = ata_scsiop_read_capacity10(pccb);
838 break; 838 break;
839 case SCSI_RD_CAPAC16: 839 case SCSI_RD_CAPAC16:
840 ret = ata_scsiop_read_capacity16(pccb); 840 ret = ata_scsiop_read_capacity16(pccb);
841 break; 841 break;
842 case SCSI_TST_U_RDY: 842 case SCSI_TST_U_RDY:
843 ret = ata_scsiop_test_unit_ready(pccb); 843 ret = ata_scsiop_test_unit_ready(pccb);
844 break; 844 break;
845 case SCSI_INQUIRY: 845 case SCSI_INQUIRY:
846 ret = ata_scsiop_inquiry(pccb); 846 ret = ata_scsiop_inquiry(pccb);
847 break; 847 break;
848 default: 848 default:
849 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); 849 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
850 return false; 850 return false;
851 } 851 }
852 852
853 if (ret) { 853 if (ret) {
854 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); 854 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
855 return false; 855 return false;
856 } 856 }
857 return true; 857 return true;
858 858
859 } 859 }
860 860
861 861
862 void scsi_low_level_init(int busdevfunc) 862 void scsi_low_level_init(int busdevfunc)
863 { 863 {
864 int i; 864 int i;
865 u32 linkmap; 865 u32 linkmap;
866 866
867 #ifndef CONFIG_SCSI_AHCI_PLAT 867 #ifndef CONFIG_SCSI_AHCI_PLAT
868 ahci_init_one(busdevfunc); 868 ahci_init_one(busdevfunc);
869 #endif 869 #endif
870 870
871 linkmap = probe_ent->link_port_map; 871 linkmap = probe_ent->link_port_map;
872 872
873 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { 873 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
874 if (((linkmap >> i) & 0x01)) { 874 if (((linkmap >> i) & 0x01)) {
875 if (ahci_port_start((u8) i)) { 875 if (ahci_port_start((u8) i)) {
876 printf("Can not start port %d\n", i); 876 printf("Can not start port %d\n", i);
877 continue; 877 continue;
878 } 878 }
879 #ifdef CONFIG_AHCI_SETFEATURES_XFER 879 #ifdef CONFIG_AHCI_SETFEATURES_XFER
880 ahci_set_feature((u8) i); 880 ahci_set_feature((u8) i);
881 #endif 881 #endif
882 } 882 }
883 } 883 }
884 } 884 }
885 885
886 #ifdef CONFIG_SCSI_AHCI_PLAT 886 #ifdef CONFIG_SCSI_AHCI_PLAT
887 int ahci_init(u32 base) 887 int ahci_init(u32 base)
888 { 888 {
889 int i, rc = 0; 889 int i, rc = 0;
890 u32 linkmap; 890 u32 linkmap;
891 891
892 probe_ent = malloc(sizeof(struct ahci_probe_ent)); 892 probe_ent = malloc(sizeof(struct ahci_probe_ent));
893 if (!probe_ent) { 893 if (!probe_ent) {
894 printf("%s: No memory for probe_ent\n", __func__); 894 printf("%s: No memory for probe_ent\n", __func__);
895 return -ENOMEM; 895 return -ENOMEM;
896 } 896 }
897 897
898 memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); 898 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
899 899
900 probe_ent->host_flags = ATA_FLAG_SATA 900 probe_ent->host_flags = ATA_FLAG_SATA
901 | ATA_FLAG_NO_LEGACY 901 | ATA_FLAG_NO_LEGACY
902 | ATA_FLAG_MMIO 902 | ATA_FLAG_MMIO
903 | ATA_FLAG_PIO_DMA 903 | ATA_FLAG_PIO_DMA
904 | ATA_FLAG_NO_ATAPI; 904 | ATA_FLAG_NO_ATAPI;
905 probe_ent->pio_mask = 0x1f; 905 probe_ent->pio_mask = 0x1f;
906 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ 906 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
907 907
908 probe_ent->mmio_base = base; 908 probe_ent->mmio_base = base;
909 909
910 /* initialize adapter */ 910 /* initialize adapter */
911 rc = ahci_host_init(probe_ent); 911 rc = ahci_host_init(probe_ent);
912 if (rc) 912 if (rc)
913 goto err_out; 913 goto err_out;
914 914
915 ahci_print_info(probe_ent); 915 ahci_print_info(probe_ent);
916 916
917 linkmap = probe_ent->link_port_map; 917 linkmap = probe_ent->link_port_map;
918 918
919 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { 919 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
920 if (((linkmap >> i) & 0x01)) { 920 if (((linkmap >> i) & 0x01)) {
921 if (ahci_port_start((u8) i)) { 921 if (ahci_port_start((u8) i)) {
922 printf("Can not start port %d\n", i); 922 printf("Can not start port %d\n", i);
923 continue; 923 continue;
924 } 924 }
925 #ifdef CONFIG_AHCI_SETFEATURES_XFER 925 #ifdef CONFIG_AHCI_SETFEATURES_XFER
926 ahci_set_feature((u8) i); 926 ahci_set_feature((u8) i);
927 #endif 927 #endif
928 } 928 }
929 } 929 }
930 err_out: 930 err_out:
931 return rc; 931 return rc;
932 } 932 }
933 933
934 void __weak scsi_init(void) 934 void __weak scsi_init(void)
935 { 935 {
936 } 936 }
937 937
938 #endif 938 #endif
939 939
940 /* 940 /*
941 * In the general case of generic rotating media it makes sense to have a 941 * In the general case of generic rotating media it makes sense to have a
942 * flush capability. It probably even makes sense in the case of SSDs because 942 * flush capability. It probably even makes sense in the case of SSDs because
943 * one cannot always know for sure what kind of internal cache/flush mechanism 943 * one cannot always know for sure what kind of internal cache/flush mechanism
944 * is embodied therein. At first it was planned to invoke this after the last 944 * is embodied therein. At first it was planned to invoke this after the last
945 * write to disk and before rebooting. In practice, knowing, a priori, which 945 * write to disk and before rebooting. In practice, knowing, a priori, which
946 * is the last write is difficult. Because writing to the disk in u-boot is 946 * is the last write is difficult. Because writing to the disk in u-boot is
947 * very rare, this flush command will be invoked after every block write. 947 * very rare, this flush command will be invoked after every block write.
948 */ 948 */
949 static int ata_io_flush(u8 port) 949 static int ata_io_flush(u8 port)
950 { 950 {
951 u8 fis[20]; 951 u8 fis[20];
952 struct ahci_ioports *pp = &(probe_ent->port[port]); 952 struct ahci_ioports *pp = &(probe_ent->port[port]);
953 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; 953 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
954 u32 cmd_fis_len = 5; /* five dwords */ 954 u32 cmd_fis_len = 5; /* five dwords */
955 955
956 /* Preset the FIS */ 956 /* Preset the FIS */
957 memset(fis, 0, 20); 957 memset(fis, 0, 20);
958 fis[0] = 0x27; /* Host to device FIS. */ 958 fis[0] = 0x27; /* Host to device FIS. */
959 fis[1] = 1 << 7; /* Command FIS. */ 959 fis[1] = 1 << 7; /* Command FIS. */
960 fis[2] = ATA_CMD_FLUSH_EXT; 960 fis[2] = ATA_CMD_FLUSH_EXT;
961 961
962 memcpy((unsigned char *)pp->cmd_tbl, fis, 20); 962 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
963 ahci_fill_cmd_slot(pp, cmd_fis_len); 963 ahci_fill_cmd_slot(pp, cmd_fis_len);
964 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); 964 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
965 965
966 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 966 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
967 WAIT_MS_FLUSH, 0x1)) { 967 WAIT_MS_FLUSH, 0x1)) {
968 debug("scsi_ahci: flush command timeout on port %d.\n", port); 968 debug("scsi_ahci: flush command timeout on port %d.\n", port);
969 return -EIO; 969 return -EIO;
970 } 970 }
971 971
972 return 0; 972 return 0;
973 } 973 }
974 974
975 975
976 void scsi_bus_reset(void) 976 void scsi_bus_reset(void)
977 { 977 {
978 /*Not implement*/ 978 /*Not implement*/
979 } 979 }
980 980
981 981
982 void scsi_print_error(ccb * pccb) 982 void scsi_print_error(ccb * pccb)
983 { 983 {
984 /*The ahci error info can be read in the ahci driver*/ 984 /*The ahci error info can be read in the ahci driver*/
985 } 985 }
986 986