Eric Lee / smarc-uboot

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/*

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/*

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* Copyright (C) Freescale Semiconductor, Inc. 2006.

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* Copyright (C) Freescale Semiconductor, Inc. 2006.

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* Author: Jason Jin<Jason.jin@freescale.com>

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* Author: Jason Jin<Jason.jin@freescale.com>

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* Zhang Wei<wei.zhang@freescale.com>

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* Zhang Wei<wei.zhang@freescale.com>

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*

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*

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* SPDX-License-Identifier: GPL-2.0+

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* SPDX-License-Identifier: GPL-2.0+

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*

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*

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* with the reference on libata and ahci drvier in kernel

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* with the reference on libata and ahci drvier in kernel

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*/

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*/

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#include <common.h>

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#include <common.h>

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#include <command.h>

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#include <command.h>

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#include <pci.h>

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#include <pci.h>

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#include <asm/processor.h>

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#include <asm/processor.h>

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#include <asm/errno.h>

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#include <asm/errno.h>

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#include <asm/io.h>

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#include <asm/io.h>

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#include <malloc.h>

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#include <malloc.h>

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#include <scsi.h>

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#include <scsi.h>

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#include <ata.h>

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#include <ata.h>

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#include <linux/ctype.h>

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#include <linux/ctype.h>

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#include <ahci.h>

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#include <ahci.h>

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static int ata_io_flush(u8 port);

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static int ata_io_flush(u8 port);

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struct ahci_probe_ent *probe_ent = NULL;

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struct ahci_probe_ent *probe_ent = NULL;

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hd_driveid_t *ataid[AHCI_MAX_PORTS];

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hd_driveid_t *ataid[AHCI_MAX_PORTS];

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#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)

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#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)

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/*

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/*

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* Some controllers limit number of blocks they can read/write at once.

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* Some controllers limit number of blocks they can read/write at once.

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* Contemporary SSD devices work much faster if the read/write size is aligned

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* Contemporary SSD devices work much faster if the read/write size is aligned

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* to a power of 2. Let's set default to 128 and allowing to be overwritten if

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* to a power of 2. Let's set default to 128 and allowing to be overwritten if

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* needed.

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* needed.

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*/

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*/

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#ifndef MAX_SATA_BLOCKS_READ_WRITE

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#ifndef MAX_SATA_BLOCKS_READ_WRITE

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#define MAX_SATA_BLOCKS_READ_WRITE 0x80

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#define MAX_SATA_BLOCKS_READ_WRITE 0x80

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#endif

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#endif

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/* Maximum timeouts for each event */

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/* Maximum timeouts for each event */

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#define WAIT_MS_SPINUP 10000

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#define WAIT_MS_SPINUP 20000

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#define WAIT_MS_DATAIO 5000

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#define WAIT_MS_DATAIO 5000

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#define WAIT_MS_FLUSH 5000

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#define WAIT_MS_FLUSH 5000

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#define WAIT_MS_LINKUP 4

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#define WAIT_MS_LINKUP 4

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static inline u32 ahci_port_base(u32 base, u32 port)

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static inline u32 ahci_port_base(u32 base, u32 port)

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{

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{

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return base + 0x100 + (port * 0x80);

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return base + 0x100 + (port * 0x80);

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}

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}

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static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,

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static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,

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unsigned int port_idx)

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unsigned int port_idx)

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{

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{

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base = ahci_port_base(base, port_idx);

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base = ahci_port_base(base, port_idx);

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port->cmd_addr = base;

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port->cmd_addr = base;

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port->scr_addr = base + PORT_SCR;

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port->scr_addr = base + PORT_SCR;

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}

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}

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#define msleep(a) udelay(a * 1000)

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#define msleep(a) udelay(a * 1000)

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static void ahci_dcache_flush_range(unsigned begin, unsigned len)

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static void ahci_dcache_flush_range(unsigned begin, unsigned len)

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{

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{

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const unsigned long start = begin;

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const unsigned long start = begin;

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const unsigned long end = start + len;

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const unsigned long end = start + len;

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debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);

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debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);

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flush_dcache_range(start, end);

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flush_dcache_range(start, end);

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}

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}

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/*

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/*

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* SATA controller DMAs to physical RAM. Ensure data from the

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* SATA controller DMAs to physical RAM. Ensure data from the

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* controller is invalidated from dcache; next access comes from

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* controller is invalidated from dcache; next access comes from

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* physical RAM.

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* physical RAM.

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*/

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*/

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static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)

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static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)

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{

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{

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const unsigned long start = begin;

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const unsigned long start = begin;

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const unsigned long end = start + len;

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const unsigned long end = start + len;

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debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);

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debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);

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invalidate_dcache_range(start, end);

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invalidate_dcache_range(start, end);

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}

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}

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/*

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/*

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* Ensure data for SATA controller is flushed out of dcache and

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* Ensure data for SATA controller is flushed out of dcache and

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* written to physical memory.

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* written to physical memory.

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*/

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*/

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static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)

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static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)

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{

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{

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ahci_dcache_flush_range((unsigned long)pp->cmd_slot,

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ahci_dcache_flush_range((unsigned long)pp->cmd_slot,

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AHCI_PORT_PRIV_DMA_SZ);

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AHCI_PORT_PRIV_DMA_SZ);

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}

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}

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static int waiting_for_cmd_completed(volatile u8 *offset,

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static int waiting_for_cmd_completed(volatile u8 *offset,

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int timeout_msec,

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int timeout_msec,

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u32 sign)

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u32 sign)

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{

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{

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int i;

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int i;

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u32 status;

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u32 status;

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for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)

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for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)

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msleep(1);

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msleep(1);

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return (i < timeout_msec) ? 0 : -1;

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return (i < timeout_msec) ? 0 : -1;

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}

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}

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int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port)

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int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port)

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{

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{

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u32 tmp;

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u32 tmp;

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int j = 0;

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int j = 0;

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u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;

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u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;

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/*

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/*

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* Bring up SATA link.

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* Bring up SATA link.

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* SATA link bringup time is usually less than 1 ms; only very

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* SATA link bringup time is usually less than 1 ms; only very

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* rarely has it taken between 1-2 ms. Never seen it above 2 ms.

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* rarely has it taken between 1-2 ms. Never seen it above 2 ms.

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*/

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*/

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while (j < WAIT_MS_LINKUP) {

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while (j < WAIT_MS_LINKUP) {

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tmp = readl(port_mmio + PORT_SCR_STAT);

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tmp = readl(port_mmio + PORT_SCR_STAT);

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tmp &= PORT_SCR_STAT_DET_MASK;

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tmp &= PORT_SCR_STAT_DET_MASK;

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if (tmp == PORT_SCR_STAT_DET_PHYRDY)

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if (tmp == PORT_SCR_STAT_DET_PHYRDY)

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return 0;

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return 0;

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udelay(1000);

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udelay(1000);

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j++;

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j++;

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}

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}

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return 1;

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return 1;

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}

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}

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static int ahci_host_init(struct ahci_probe_ent *probe_ent)

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static int ahci_host_init(struct ahci_probe_ent *probe_ent)

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{

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{

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#ifndef CONFIG_SCSI_AHCI_PLAT

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#ifndef CONFIG_SCSI_AHCI_PLAT

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pci_dev_t pdev = probe_ent->dev;

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pci_dev_t pdev = probe_ent->dev;

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u16 tmp16;

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u16 tmp16;

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unsigned short vendor;

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unsigned short vendor;

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#endif

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#endif

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volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;

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volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;

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u32 tmp, cap_save, cmd;

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u32 tmp, cap_save, cmd;

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int i, j, ret;

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int i, j, ret;

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volatile u8 *port_mmio;

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volatile u8 *port_mmio;

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u32 port_map;

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u32 port_map;

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debug("ahci_host_init: start\n");

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debug("ahci_host_init: start\n");

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cap_save = readl(mmio + HOST_CAP);

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cap_save = readl(mmio + HOST_CAP);

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cap_save &= ((1 << 28) | (1 << 17));

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cap_save &= ((1 << 28) | (1 << 17));

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cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */

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cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */

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/* global controller reset */

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/* global controller reset */

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tmp = readl(mmio + HOST_CTL);

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tmp = readl(mmio + HOST_CTL);

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if ((tmp & HOST_RESET) == 0)

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if ((tmp & HOST_RESET) == 0)

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writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);

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writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);

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/* reset must complete within 1 second, or

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/* reset must complete within 1 second, or

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* the hardware should be considered fried.

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* the hardware should be considered fried.

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*/

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*/

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i = 1000;

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i = 1000;

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do {

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do {

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udelay(1000);

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udelay(1000);

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tmp = readl(mmio + HOST_CTL);

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tmp = readl(mmio + HOST_CTL);

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if (!i--) {

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if (!i--) {

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debug("controller reset failed (0x%x)\n", tmp);

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debug("controller reset failed (0x%x)\n", tmp);

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return -1;

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return -1;

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}

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}

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} while (tmp & HOST_RESET);

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} while (tmp & HOST_RESET);

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writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);

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writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);

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writel(cap_save, mmio + HOST_CAP);

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writel(cap_save, mmio + HOST_CAP);

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writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);

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writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);

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#ifndef CONFIG_SCSI_AHCI_PLAT

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#ifndef CONFIG_SCSI_AHCI_PLAT

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pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);

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pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);

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if (vendor == PCI_VENDOR_ID_INTEL) {

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if (vendor == PCI_VENDOR_ID_INTEL) {

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u16 tmp16;

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u16 tmp16;

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pci_read_config_word(pdev, 0x92, &tmp16);

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pci_read_config_word(pdev, 0x92, &tmp16);

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tmp16 |= 0xf;

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tmp16 |= 0xf;

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pci_write_config_word(pdev, 0x92, tmp16);

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pci_write_config_word(pdev, 0x92, tmp16);

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}

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}

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#endif

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#endif

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probe_ent->cap = readl(mmio + HOST_CAP);

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probe_ent->cap = readl(mmio + HOST_CAP);

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probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);

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probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);

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port_map = probe_ent->port_map;

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port_map = probe_ent->port_map;

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probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;

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probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;

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debug("cap 0x%x port_map 0x%x n_ports %d\n",

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debug("cap 0x%x port_map 0x%x n_ports %d\n",

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probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);

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probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);

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if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)

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if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)

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probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;

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probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;

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for (i = 0; i < probe_ent->n_ports; i++) {

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for (i = 0; i < probe_ent->n_ports; i++) {

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if (!(port_map & (1 << i)))

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if (!(port_map & (1 << i)))

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continue;

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continue;

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probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);

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probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);

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port_mmio = (u8 *) probe_ent->port[i].port_mmio;

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port_mmio = (u8 *) probe_ent->port[i].port_mmio;

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ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);

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ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);

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/* make sure port is not active */

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/* make sure port is not active */

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tmp = readl(port_mmio + PORT_CMD);

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tmp = readl(port_mmio + PORT_CMD);

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if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |

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if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |

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PORT_CMD_FIS_RX | PORT_CMD_START)) {

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PORT_CMD_FIS_RX | PORT_CMD_START)) {

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debug("Port %d is active. Deactivating.\n", i);

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debug("Port %d is active. Deactivating.\n", i);

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tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |

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tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |

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PORT_CMD_FIS_RX | PORT_CMD_START);

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PORT_CMD_FIS_RX | PORT_CMD_START);

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writel_with_flush(tmp, port_mmio + PORT_CMD);

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writel_with_flush(tmp, port_mmio + PORT_CMD);

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/* spec says 500 msecs for each bit, so

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/* spec says 500 msecs for each bit, so

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* this is slightly incorrect.

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* this is slightly incorrect.

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*/

212

*/

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msleep(500);

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msleep(500);

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}

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}

215

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/* Add the spinup command to whatever mode bits may

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/* Add the spinup command to whatever mode bits may

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* already be on in the command register.

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* already be on in the command register.

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*/

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*/

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cmd = readl(port_mmio + PORT_CMD);

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cmd = readl(port_mmio + PORT_CMD);

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cmd |= PORT_CMD_FIS_RX;

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cmd |= PORT_CMD_FIS_RX;

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cmd |= PORT_CMD_SPIN_UP;

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cmd |= PORT_CMD_SPIN_UP;

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writel_with_flush(cmd, port_mmio + PORT_CMD);

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writel_with_flush(cmd, port_mmio + PORT_CMD);

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/* Bring up SATA link. */

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/* Bring up SATA link. */

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ret = ahci_link_up(probe_ent, i);

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ret = ahci_link_up(probe_ent, i);

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if (ret) {

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if (ret) {

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printf("SATA link %d timeout.\n", i);

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printf("SATA link %d timeout.\n", i);

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continue;

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continue;

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} else {

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} else {

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debug("SATA link ok.\n");

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debug("SATA link ok.\n");

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}

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}

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/* Clear error status */

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/* Clear error status */

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tmp = readl(port_mmio + PORT_SCR_ERR);

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tmp = readl(port_mmio + PORT_SCR_ERR);

235

if (tmp)

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if (tmp)

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writel(tmp, port_mmio + PORT_SCR_ERR);

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writel(tmp, port_mmio + PORT_SCR_ERR);

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debug("Spinning up device on SATA port %d... ", i);

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debug("Spinning up device on SATA port %d... ", i);

239

240

j = 0;

240

j = 0;

241

while (j < WAIT_MS_SPINUP) {

241

while (j < WAIT_MS_SPINUP) {

242

tmp = readl(port_mmio + PORT_TFDATA);

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tmp = readl(port_mmio + PORT_TFDATA);

243

if (!(tmp & (ATA_STAT_BUSY | ATA_STAT_DRQ)))

243

if (!(tmp & (ATA_STAT_BUSY | ATA_STAT_DRQ)))

244

break;

244

break;

245

udelay(1000);

245

udelay(1000);

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tmp = readl(port_mmio + PORT_SCR_STAT);

246

tmp = readl(port_mmio + PORT_SCR_STAT);

247

tmp &= PORT_SCR_STAT_DET_MASK;

247

tmp &= PORT_SCR_STAT_DET_MASK;

248

if (tmp == PORT_SCR_STAT_DET_PHYRDY)

248

if (tmp == PORT_SCR_STAT_DET_PHYRDY)

249

break;

249

break;

250

j++;

250

j++;

251

}

251

}

252

253

tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;

253

tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;

254

if (tmp == PORT_SCR_STAT_DET_COMINIT) {

254

if (tmp == PORT_SCR_STAT_DET_COMINIT) {

255

debug("SATA link %d down (COMINIT received), retrying...\n", i);

255

debug("SATA link %d down (COMINIT received), retrying...\n", i);

256

i--;

256

i--;

257

continue;

257

continue;

258

}

258

}

259

260

printf("Target spinup took %d ms.\n", j);

260

printf("Target spinup took %d ms.\n", j);

261

if (j == WAIT_MS_SPINUP)

261

if (j == WAIT_MS_SPINUP)

262

debug("timeout.\n");

262

debug("timeout.\n");

263

else

263

else

264

debug("ok.\n");

264

debug("ok.\n");

265

266

tmp = readl(port_mmio + PORT_SCR_ERR);

266

tmp = readl(port_mmio + PORT_SCR_ERR);

267

debug("PORT_SCR_ERR 0x%x\n", tmp);

267

debug("PORT_SCR_ERR 0x%x\n", tmp);

268

writel(tmp, port_mmio + PORT_SCR_ERR);

268

writel(tmp, port_mmio + PORT_SCR_ERR);

269

270

/* ack any pending irq events for this port */

270

/* ack any pending irq events for this port */

271

tmp = readl(port_mmio + PORT_IRQ_STAT);

271

tmp = readl(port_mmio + PORT_IRQ_STAT);

272

debug("PORT_IRQ_STAT 0x%x\n", tmp);

272

debug("PORT_IRQ_STAT 0x%x\n", tmp);

273

if (tmp)

273

if (tmp)

274

writel(tmp, port_mmio + PORT_IRQ_STAT);

274

writel(tmp, port_mmio + PORT_IRQ_STAT);

275

276

writel(1 << i, mmio + HOST_IRQ_STAT);

276

writel(1 << i, mmio + HOST_IRQ_STAT);

277

278

/* set irq mask (enables interrupts) */

278

/* set irq mask (enables interrupts) */

279

writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);

279

writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);

280

281

/* register linkup ports */

281

/* register linkup ports */

282

tmp = readl(port_mmio + PORT_SCR_STAT);

282

tmp = readl(port_mmio + PORT_SCR_STAT);

283

debug("SATA port %d status: 0x%x\n", i, tmp);

283

debug("SATA port %d status: 0x%x\n", i, tmp);

284

if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)

284

if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)

285

probe_ent->link_port_map |= (0x01 << i);

285

probe_ent->link_port_map |= (0x01 << i);

286

}

286

}

287

288

tmp = readl(mmio + HOST_CTL);

288

tmp = readl(mmio + HOST_CTL);

289

debug("HOST_CTL 0x%x\n", tmp);

289

debug("HOST_CTL 0x%x\n", tmp);

290

writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);

290

writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);

291

tmp = readl(mmio + HOST_CTL);

291

tmp = readl(mmio + HOST_CTL);

292

debug("HOST_CTL 0x%x\n", tmp);

292

debug("HOST_CTL 0x%x\n", tmp);

293

#ifndef CONFIG_SCSI_AHCI_PLAT

293

#ifndef CONFIG_SCSI_AHCI_PLAT

294

pci_read_config_word(pdev, PCI_COMMAND, &tmp16);

294

pci_read_config_word(pdev, PCI_COMMAND, &tmp16);

295

tmp |= PCI_COMMAND_MASTER;

295

tmp |= PCI_COMMAND_MASTER;

296

pci_write_config_word(pdev, PCI_COMMAND, tmp16);

296

pci_write_config_word(pdev, PCI_COMMAND, tmp16);

297

#endif

297

#endif

298

return 0;

298

return 0;

299

}

299

}

300

301

302

static void ahci_print_info(struct ahci_probe_ent *probe_ent)

302

static void ahci_print_info(struct ahci_probe_ent *probe_ent)

303

{

303

{

304

#ifndef CONFIG_SCSI_AHCI_PLAT

304

#ifndef CONFIG_SCSI_AHCI_PLAT

305

pci_dev_t pdev = probe_ent->dev;

305

pci_dev_t pdev = probe_ent->dev;

306

u16 cc;

306

u16 cc;

307

#endif

307

#endif

308

volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;

308

volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;

309

u32 vers, cap, cap2, impl, speed;

309

u32 vers, cap, cap2, impl, speed;

310

const char *speed_s;

310

const char *speed_s;

311

const char *scc_s;

311

const char *scc_s;

312

313

vers = readl(mmio + HOST_VERSION);

313

vers = readl(mmio + HOST_VERSION);

314

cap = probe_ent->cap;

314

cap = probe_ent->cap;

315

cap2 = readl(mmio + HOST_CAP2);

315

cap2 = readl(mmio + HOST_CAP2);

316

impl = probe_ent->port_map;

316

impl = probe_ent->port_map;

317

318

speed = (cap >> 20) & 0xf;

318

speed = (cap >> 20) & 0xf;

319

if (speed == 1)

319

if (speed == 1)

320

speed_s = "1.5";

320

speed_s = "1.5";

321

else if (speed == 2)

321

else if (speed == 2)

322

speed_s = "3";

322

speed_s = "3";

323

else if (speed == 3)

323

else if (speed == 3)

324

speed_s = "6";

324

speed_s = "6";

325

else

325

else

326

speed_s = "?";

326

speed_s = "?";

327

328

#ifdef CONFIG_SCSI_AHCI_PLAT

328

#ifdef CONFIG_SCSI_AHCI_PLAT

329

scc_s = "SATA";

329

scc_s = "SATA";

330

#else

330

#else

331

pci_read_config_word(pdev, 0x0a, &cc);

331

pci_read_config_word(pdev, 0x0a, &cc);

332

if (cc == 0x0101)

332

if (cc == 0x0101)

333

scc_s = "IDE";

333

scc_s = "IDE";

334

else if (cc == 0x0106)

334

else if (cc == 0x0106)

335

scc_s = "SATA";

335

scc_s = "SATA";

336

else if (cc == 0x0104)

336

else if (cc == 0x0104)

337

scc_s = "RAID";

337

scc_s = "RAID";

338

else

338

else

339

scc_s = "unknown";

339

scc_s = "unknown";

340

#endif

340

#endif

341

printf("AHCI %02x%02x.%02x%02x "

341

printf("AHCI %02x%02x.%02x%02x "

342

"%u slots %u ports %s Gbps 0x%x impl %s mode\n",

342

"%u slots %u ports %s Gbps 0x%x impl %s mode\n",

343

(vers >> 24) & 0xff,

343

(vers >> 24) & 0xff,

344

(vers >> 16) & 0xff,

344

(vers >> 16) & 0xff,

345

(vers >> 8) & 0xff,

345

(vers >> 8) & 0xff,

346

vers & 0xff,

346

vers & 0xff,

347

((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);

347

((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);

348

349

printf("flags: "

349

printf("flags: "

350

"%s%s%s%s%s%s%s"

350

"%s%s%s%s%s%s%s"

351

"%s%s%s%s%s%s%s"

351

"%s%s%s%s%s%s%s"

352

"%s%s%s%s%s%s\n",

352

"%s%s%s%s%s%s\n",

353

cap & (1 << 31) ? "64bit " : "",

353

cap & (1 << 31) ? "64bit " : "",

354

cap & (1 << 30) ? "ncq " : "",

354

cap & (1 << 30) ? "ncq " : "",

355

cap & (1 << 28) ? "ilck " : "",

355

cap & (1 << 28) ? "ilck " : "",

356

cap & (1 << 27) ? "stag " : "",

356

cap & (1 << 27) ? "stag " : "",

357

cap & (1 << 26) ? "pm " : "",

357

cap & (1 << 26) ? "pm " : "",

358

cap & (1 << 25) ? "led " : "",

358

cap & (1 << 25) ? "led " : "",

359

cap & (1 << 24) ? "clo " : "",

359

cap & (1 << 24) ? "clo " : "",

360

cap & (1 << 19) ? "nz " : "",

360

cap & (1 << 19) ? "nz " : "",

361

cap & (1 << 18) ? "only " : "",

361

cap & (1 << 18) ? "only " : "",

362

cap & (1 << 17) ? "pmp " : "",

362

cap & (1 << 17) ? "pmp " : "",

363

cap & (1 << 16) ? "fbss " : "",

363

cap & (1 << 16) ? "fbss " : "",

364

cap & (1 << 15) ? "pio " : "",

364

cap & (1 << 15) ? "pio " : "",

365

cap & (1 << 14) ? "slum " : "",

365

cap & (1 << 14) ? "slum " : "",

366

cap & (1 << 13) ? "part " : "",

366

cap & (1 << 13) ? "part " : "",

367

cap & (1 << 7) ? "ccc " : "",

367

cap & (1 << 7) ? "ccc " : "",

368

cap & (1 << 6) ? "ems " : "",

368

cap & (1 << 6) ? "ems " : "",

369

cap & (1 << 5) ? "sxs " : "",

369

cap & (1 << 5) ? "sxs " : "",

370

cap2 & (1 << 2) ? "apst " : "",

370

cap2 & (1 << 2) ? "apst " : "",

371

cap2 & (1 << 1) ? "nvmp " : "",

371

cap2 & (1 << 1) ? "nvmp " : "",

372

cap2 & (1 << 0) ? "boh " : "");

372

cap2 & (1 << 0) ? "boh " : "");

373

}

373

}

374

375

#ifndef CONFIG_SCSI_AHCI_PLAT

375

#ifndef CONFIG_SCSI_AHCI_PLAT

376

static int ahci_init_one(pci_dev_t pdev)

376

static int ahci_init_one(pci_dev_t pdev)

377

{

377

{

378

u16 vendor;

378

u16 vendor;

379

int rc;

379

int rc;

380

381

memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);

381

memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);

382

383

probe_ent = malloc(sizeof(struct ahci_probe_ent));

383

probe_ent = malloc(sizeof(struct ahci_probe_ent));

384

memset(probe_ent, 0, sizeof(struct ahci_probe_ent));

384

memset(probe_ent, 0, sizeof(struct ahci_probe_ent));

385

probe_ent->dev = pdev;

385

probe_ent->dev = pdev;

386

387

probe_ent->host_flags = ATA_FLAG_SATA

387

probe_ent->host_flags = ATA_FLAG_SATA

388

| ATA_FLAG_NO_LEGACY

388

| ATA_FLAG_NO_LEGACY

389

| ATA_FLAG_MMIO

389

| ATA_FLAG_MMIO

390

| ATA_FLAG_PIO_DMA

390

| ATA_FLAG_PIO_DMA

391

| ATA_FLAG_NO_ATAPI;

391

| ATA_FLAG_NO_ATAPI;

392

probe_ent->pio_mask = 0x1f;

392

probe_ent->pio_mask = 0x1f;

393

probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */

393

probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */

394

395

pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);

395

pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);

396

debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);

396

debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);

397

398

/* Take from kernel:

398

/* Take from kernel:

399

* JMicron-specific fixup:

399

* JMicron-specific fixup:

400

* make sure we're in AHCI mode

400

* make sure we're in AHCI mode

401

*/

401

*/

402

pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);

402

pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);

403

if (vendor == 0x197b)

403

if (vendor == 0x197b)

404

pci_write_config_byte(pdev, 0x41, 0xa1);

404

pci_write_config_byte(pdev, 0x41, 0xa1);

405

406

/* initialize adapter */

406

/* initialize adapter */

407

rc = ahci_host_init(probe_ent);

407

rc = ahci_host_init(probe_ent);

408

if (rc)

408

if (rc)

409

goto err_out;

409

goto err_out;

410

411

ahci_print_info(probe_ent);

411

ahci_print_info(probe_ent);

412

413

return 0;

413

return 0;

414

415

err_out:

415

err_out:

416

return rc;

416

return rc;

417

}

417

}

418

#endif

418

#endif

419

420

#define MAX_DATA_BYTE_COUNT (4*1024*1024)

420

#define MAX_DATA_BYTE_COUNT (4*1024*1024)

421

422

static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)

422

static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)

423

{

423

{

424

struct ahci_ioports *pp = &(probe_ent->port[port]);

424

struct ahci_ioports *pp = &(probe_ent->port[port]);

425

struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;

425

struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;

426

u32 sg_count;

426

u32 sg_count;

427

int i;

427

int i;

428

429

sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;

429

sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;

430

if (sg_count > AHCI_MAX_SG) {

430

if (sg_count > AHCI_MAX_SG) {

431

printf("Error:Too much sg!\n");

431

printf("Error:Too much sg!\n");

432

return -1;

432

return -1;

433

}

433

}

434

435

for (i = 0; i < sg_count; i++) {

435

for (i = 0; i < sg_count; i++) {

436

ahci_sg->addr =

436

ahci_sg->addr =

437

cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);

437

cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);

438

ahci_sg->addr_hi = 0;

438

ahci_sg->addr_hi = 0;

439

ahci_sg->flags_size = cpu_to_le32(0x3fffff &

439

ahci_sg->flags_size = cpu_to_le32(0x3fffff &

440

(buf_len < MAX_DATA_BYTE_COUNT

440

(buf_len < MAX_DATA_BYTE_COUNT

441

? (buf_len - 1)

441

? (buf_len - 1)

442

: (MAX_DATA_BYTE_COUNT - 1)));

442

: (MAX_DATA_BYTE_COUNT - 1)));

443

ahci_sg++;

443

ahci_sg++;

444

buf_len -= MAX_DATA_BYTE_COUNT;

444

buf_len -= MAX_DATA_BYTE_COUNT;

445

}

445

}

446

447

return sg_count;

447

return sg_count;

448

}

448

}

449

450

451

static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)

451

static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)

452

{

452

{

453

pp->cmd_slot->opts = cpu_to_le32(opts);

453

pp->cmd_slot->opts = cpu_to_le32(opts);

454

pp->cmd_slot->status = 0;

454

pp->cmd_slot->status = 0;

455

pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);

455

pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);

456

pp->cmd_slot->tbl_addr_hi = 0;

456

pp->cmd_slot->tbl_addr_hi = 0;

457

}

457

}

458

459

460

#ifdef CONFIG_AHCI_SETFEATURES_XFER

460

#ifdef CONFIG_AHCI_SETFEATURES_XFER

461

static void ahci_set_feature(u8 port)

461

static void ahci_set_feature(u8 port)

462

{

462

{

463

struct ahci_ioports *pp = &(probe_ent->port[port]);

463

struct ahci_ioports *pp = &(probe_ent->port[port]);

464

volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;

464

volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;

465

u32 cmd_fis_len = 5; /* five dwords */

465

u32 cmd_fis_len = 5; /* five dwords */

466

u8 fis[20];

466

u8 fis[20];

467

468

/* set feature */

468

/* set feature */

469

memset(fis, 0, sizeof(fis));

469

memset(fis, 0, sizeof(fis));

470

fis[0] = 0x27;

470

fis[0] = 0x27;

471

fis[1] = 1 << 7;

471

fis[1] = 1 << 7;

472

fis[2] = ATA_CMD_SETF;

472

fis[2] = ATA_CMD_SETF;

473

fis[3] = SETFEATURES_XFER;

473

fis[3] = SETFEATURES_XFER;

474

fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;

474

fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;

475

476

memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));

476

memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));

477

ahci_fill_cmd_slot(pp, cmd_fis_len);

477

ahci_fill_cmd_slot(pp, cmd_fis_len);

478

ahci_dcache_flush_sata_cmd(pp);

478

ahci_dcache_flush_sata_cmd(pp);

479

writel(1, port_mmio + PORT_CMD_ISSUE);

479

writel(1, port_mmio + PORT_CMD_ISSUE);

480

readl(port_mmio + PORT_CMD_ISSUE);

480

readl(port_mmio + PORT_CMD_ISSUE);

481

482

if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,

482

if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,

483

WAIT_MS_DATAIO, 0x1)) {

483

WAIT_MS_DATAIO, 0x1)) {

484

printf("set feature error on port %d!\n", port);

484

printf("set feature error on port %d!\n", port);

485

}

485

}

486

}

486

}

487

#endif

487

#endif

488

489

490

static int ahci_port_start(u8 port)

490

static int ahci_port_start(u8 port)

491

{

491

{

492

struct ahci_ioports *pp = &(probe_ent->port[port]);

492

struct ahci_ioports *pp = &(probe_ent->port[port]);

493

volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;

493

volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;

494

u32 port_status;

494

u32 port_status;

495

u32 mem;

495

u32 mem;

496

497

debug("Enter start port: %d\n", port);

497

debug("Enter start port: %d\n", port);

498

port_status = readl(port_mmio + PORT_SCR_STAT);

498

port_status = readl(port_mmio + PORT_SCR_STAT);

499

debug("Port %d status: %x\n", port, port_status);

499

debug("Port %d status: %x\n", port, port_status);

500

if ((port_status & 0xf) != 0x03) {

500

if ((port_status & 0xf) != 0x03) {

501

printf("No Link on this port!\n");

501

printf("No Link on this port!\n");

502

return -1;

502

return -1;

503

}

503

}

504

505

mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);

505

mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);

506

if (!mem) {

506

if (!mem) {

507

free(pp);

507

free(pp);

508

printf("No mem for table!\n");

508

printf("No mem for table!\n");

509

return -ENOMEM;

509

return -ENOMEM;

510

}

510

}

511

512

mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */

512

mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */

513

memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);

513

memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);

514

515

/*

515

/*

516

* First item in chunk of DMA memory: 32-slot command table,

516

* First item in chunk of DMA memory: 32-slot command table,

517

* 32 bytes each in size

517

* 32 bytes each in size

518

*/

518

*/

519

pp->cmd_slot =

519

pp->cmd_slot =

520

(struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);

520

(struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);

521

debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);

521

debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);

522

mem += (AHCI_CMD_SLOT_SZ + 224);

522

mem += (AHCI_CMD_SLOT_SZ + 224);

523

524

/*

524

/*

525

* Second item: Received-FIS area

525

* Second item: Received-FIS area

526

*/

526

*/

527

pp->rx_fis = virt_to_phys((void *)mem);

527

pp->rx_fis = virt_to_phys((void *)mem);

528

mem += AHCI_RX_FIS_SZ;

528

mem += AHCI_RX_FIS_SZ;

529

530

/*

530

/*

531

* Third item: data area for storing a single command

531

* Third item: data area for storing a single command

532

* and its scatter-gather table

532

* and its scatter-gather table

533

*/

533

*/

534

pp->cmd_tbl = virt_to_phys((void *)mem);

534

pp->cmd_tbl = virt_to_phys((void *)mem);

535

debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);

535

debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);

536

537

mem += AHCI_CMD_TBL_HDR;

537

mem += AHCI_CMD_TBL_HDR;

538

pp->cmd_tbl_sg =

538

pp->cmd_tbl_sg =

539

(struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);

539

(struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);

540

541

writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);

541

writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);

542

543

writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);

543

writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);

544

545

writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |

545

writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |

546

PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |

546

PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |

547

PORT_CMD_START, port_mmio + PORT_CMD);

547

PORT_CMD_START, port_mmio + PORT_CMD);

548

549

debug("Exit start port %d\n", port);

549

debug("Exit start port %d\n", port);

550

551

return 0;

551

return 0;

552

}

552

}

553

554

555

static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,

555

static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,

556

int buf_len, u8 is_write)

556

int buf_len, u8 is_write)

557

{

557

{

558

559

struct ahci_ioports *pp = &(probe_ent->port[port]);

559

struct ahci_ioports *pp = &(probe_ent->port[port]);

560

volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;

560

volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;

561

u32 opts;

561

u32 opts;

562

u32 port_status;

562

u32 port_status;

563

int sg_count;

563

int sg_count;

564

565

debug("Enter %s: for port %d\n", __func__, port);

565

debug("Enter %s: for port %d\n", __func__, port);

566

567

if (port > probe_ent->n_ports) {

567

if (port > probe_ent->n_ports) {

568

printf("Invalid port number %d\n", port);

568

printf("Invalid port number %d\n", port);

569

return -1;

569

return -1;

570

}

570

}

571

572

port_status = readl(port_mmio + PORT_SCR_STAT);

572

port_status = readl(port_mmio + PORT_SCR_STAT);

573

if ((port_status & 0xf) != 0x03) {

573

if ((port_status & 0xf) != 0x03) {

574

debug("No Link on port %d!\n", port);

574

debug("No Link on port %d!\n", port);

575

return -1;

575

return -1;

576

}

576

}

577

578

memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);

578

memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);

579

580

sg_count = ahci_fill_sg(port, buf, buf_len);

580

sg_count = ahci_fill_sg(port, buf, buf_len);

581

opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);

581

opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);

582

ahci_fill_cmd_slot(pp, opts);

582

ahci_fill_cmd_slot(pp, opts);

583

584

ahci_dcache_flush_sata_cmd(pp);

584

ahci_dcache_flush_sata_cmd(pp);

585

ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);

585

ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);

586

587

writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);

587

writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);

588

589

if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,

589

if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,

590

WAIT_MS_DATAIO, 0x1)) {

590

WAIT_MS_DATAIO, 0x1)) {

591

printf("timeout exit!\n");

591

printf("timeout exit!\n");

592

return -1;

592

return -1;

593

}

593

}

594

595

ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);

595

ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);

596

debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);

596

debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);

597

598

return 0;

598

return 0;

599

}

599

}

600

601

602

static char *ata_id_strcpy(u16 *target, u16 *src, int len)

602

static char *ata_id_strcpy(u16 *target, u16 *src, int len)

603

{

603

{

604

int i;

604

int i;

605

for (i = 0; i < len / 2; i++)

605

for (i = 0; i < len / 2; i++)

606

target[i] = swab16(src[i]);

606

target[i] = swab16(src[i]);

607

return (char *)target;

607

return (char *)target;

608

}

608

}

609

610

611

static void dump_ataid(hd_driveid_t *ataid)

611

static void dump_ataid(hd_driveid_t *ataid)

612

{

612

{

613

debug("(49)ataid->capability = 0x%x\n", ataid->capability);

613

debug("(49)ataid->capability = 0x%x\n", ataid->capability);

614

debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);

614

debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);

615

debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);

615

debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);

616

debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);

616

debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);

617

debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);

617

debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);

618

debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);

618

debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);

619

debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);

619

debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);

620

debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);

620

debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);

621

debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);

621

debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);

622

debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);

622

debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);

623

debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);

623

debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);

624

debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);

624

debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);

625

debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);

625

debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);

626

debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);

626

debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);

627

debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);

627

debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);

628

}

628

}

629

630

631

/*

631

/*

632

* SCSI INQUIRY command operation.

632

* SCSI INQUIRY command operation.

633

*/

633

*/

634

static int ata_scsiop_inquiry(ccb *pccb)

634

static int ata_scsiop_inquiry(ccb *pccb)

635

{

635

{

636

static const u8 hdr[] = {

636

static const u8 hdr[] = {

637

0,

637

0,

638

0,

638

0,

639

0x5, /* claim SPC-3 version compatibility */

639

0x5, /* claim SPC-3 version compatibility */

640

2,

640

2,

641

95 - 4,

641

95 - 4,

642

};

642

};

643

u8 fis[20];

643

u8 fis[20];

644

u8 *tmpid;

644

u8 *tmpid;

645

u8 port;

645

u8 port;

646

647

/* Clean ccb data buffer */

647

/* Clean ccb data buffer */

648

memset(pccb->pdata, 0, pccb->datalen);

648

memset(pccb->pdata, 0, pccb->datalen);

649

650

memcpy(pccb->pdata, hdr, sizeof(hdr));

650

memcpy(pccb->pdata, hdr, sizeof(hdr));

651

652

if (pccb->datalen <= 35)

652

if (pccb->datalen <= 35)

653

return 0;

653

return 0;

654

655

memset(fis, 0, sizeof(fis));

655

memset(fis, 0, sizeof(fis));

656

/* Construct the FIS */

656

/* Construct the FIS */

657

fis[0] = 0x27; /* Host to device FIS. */

657

fis[0] = 0x27; /* Host to device FIS. */

658

fis[1] = 1 << 7; /* Command FIS. */

658

fis[1] = 1 << 7; /* Command FIS. */

659

fis[2] = ATA_CMD_IDENT; /* Command byte. */

659

fis[2] = ATA_CMD_IDENT; /* Command byte. */

660

661

/* Read id from sata */

661

/* Read id from sata */

662

port = pccb->target;

662

port = pccb->target;

663

if (!(tmpid = malloc(sizeof(hd_driveid_t))))

663

if (!(tmpid = malloc(sizeof(hd_driveid_t))))

664

return -ENOMEM;

664

return -ENOMEM;

665

666

if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid,

666

if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid,

667

sizeof(hd_driveid_t), 0)) {

667

sizeof(hd_driveid_t), 0)) {

668

debug("scsi_ahci: SCSI inquiry command failure.\n");

668

debug("scsi_ahci: SCSI inquiry command failure.\n");

669

free(tmpid);

669

free(tmpid);

670

return -EIO;

670

return -EIO;

671

}

671

}

672

673

if (ataid[port])

673

if (ataid[port])

674

free(ataid[port]);

674

free(ataid[port]);

675

ataid[port] = (hd_driveid_t *) tmpid;

675

ataid[port] = (hd_driveid_t *) tmpid;

676

677

memcpy(&pccb->pdata[8], "ATA ", 8);

677

memcpy(&pccb->pdata[8], "ATA ", 8);

678

ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);

678

ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);

679

ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);

679

ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);

680

681

dump_ataid(ataid[port]);

681

dump_ataid(ataid[port]);

682

return 0;

682

return 0;

683

}

683

}

684

685

686

/*

686

/*

687

* SCSI READ10/WRITE10 command operation.

687

* SCSI READ10/WRITE10 command operation.

688

*/

688

*/

689

static int ata_scsiop_read_write(ccb *pccb, u8 is_write)

689

static int ata_scsiop_read_write(ccb *pccb, u8 is_write)

690

{

690

{

691

u32 lba = 0;

691

u32 lba = 0;

692

u16 blocks = 0;

692

u16 blocks = 0;

693

u8 fis[20];

693

u8 fis[20];

694

u8 *user_buffer = pccb->pdata;

694

u8 *user_buffer = pccb->pdata;

695

u32 user_buffer_size = pccb->datalen;

695

u32 user_buffer_size = pccb->datalen;

696

697

/* Retrieve the base LBA number from the ccb structure. */

697

/* Retrieve the base LBA number from the ccb structure. */

698

memcpy(&lba, pccb->cmd + 2, sizeof(lba));

698

memcpy(&lba, pccb->cmd + 2, sizeof(lba));

699

lba = be32_to_cpu(lba);

699

lba = be32_to_cpu(lba);

700

701

/*

701

/*

702

* And the number of blocks.

702

* And the number of blocks.

703

*

703

*

704

* For 10-byte and 16-byte SCSI R/W commands, transfer

704

* For 10-byte and 16-byte SCSI R/W commands, transfer

705

* length 0 means transfer 0 block of data.

705

* length 0 means transfer 0 block of data.

706

* However, for ATA R/W commands, sector count 0 means

706

* However, for ATA R/W commands, sector count 0 means

707

* 256 or 65536 sectors, not 0 sectors as in SCSI.

707

* 256 or 65536 sectors, not 0 sectors as in SCSI.

708

*

708

*

709

* WARNING: one or two older ATA drives treat 0 as 0...

709

* WARNING: one or two older ATA drives treat 0 as 0...

710

*/

710

*/

711

blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);

711

blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);

712

713

debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",

713

debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",

714

is_write ? "write" : "read", (unsigned)lba, blocks);

714

is_write ? "write" : "read", (unsigned)lba, blocks);

715

716

/* Preset the FIS */

716

/* Preset the FIS */

717

memset(fis, 0, sizeof(fis));

717

memset(fis, 0, sizeof(fis));

718

fis[0] = 0x27; /* Host to device FIS. */

718

fis[0] = 0x27; /* Host to device FIS. */

719

fis[1] = 1 << 7; /* Command FIS. */

719

fis[1] = 1 << 7; /* Command FIS. */

720

/* Command byte (read/write). */

720

/* Command byte (read/write). */

721

fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;

721

fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;

722

723

while (blocks) {

723

while (blocks) {

724

u16 now_blocks; /* number of blocks per iteration */

724

u16 now_blocks; /* number of blocks per iteration */

725

u32 transfer_size; /* number of bytes per iteration */

725

u32 transfer_size; /* number of bytes per iteration */

726

727

now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);

727

now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);

728

729

transfer_size = ATA_BLOCKSIZE * now_blocks;

729

transfer_size = ATA_BLOCKSIZE * now_blocks;

730

if (transfer_size > user_buffer_size) {

730

if (transfer_size > user_buffer_size) {

731

printf("scsi_ahci: Error: buffer too small.\n");

731

printf("scsi_ahci: Error: buffer too small.\n");

732

return -EIO;

732

return -EIO;

733

}

733

}

734

735

/* LBA48 SATA command but only use 32bit address range within

735

/* LBA48 SATA command but only use 32bit address range within

736

* that. The next smaller command range (28bit) is too small.

736

* that. The next smaller command range (28bit) is too small.

737

*/

737

*/

738

fis[4] = (lba >> 0) & 0xff;

738

fis[4] = (lba >> 0) & 0xff;

739

fis[5] = (lba >> 8) & 0xff;

739

fis[5] = (lba >> 8) & 0xff;

740

fis[6] = (lba >> 16) & 0xff;

740

fis[6] = (lba >> 16) & 0xff;

741

fis[7] = 1 << 6; /* device reg: set LBA mode */

741

fis[7] = 1 << 6; /* device reg: set LBA mode */

742

fis[8] = ((lba >> 24) & 0xff);

742

fis[8] = ((lba >> 24) & 0xff);

743

fis[3] = 0xe0; /* features */

743

fis[3] = 0xe0; /* features */

744

745

/* Block (sector) count */

745

/* Block (sector) count */

746

fis[12] = (now_blocks >> 0) & 0xff;

746

fis[12] = (now_blocks >> 0) & 0xff;

747

fis[13] = (now_blocks >> 8) & 0xff;

747

fis[13] = (now_blocks >> 8) & 0xff;

748

749

/* Read/Write from ahci */

749

/* Read/Write from ahci */

750

if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),

750

if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),

751

user_buffer, user_buffer_size,

751

user_buffer, user_buffer_size,

752

is_write)) {

752

is_write)) {

753

debug("scsi_ahci: SCSI %s10 command failure.\n",

753

debug("scsi_ahci: SCSI %s10 command failure.\n",

754

is_write ? "WRITE" : "READ");

754

is_write ? "WRITE" : "READ");

755

return -EIO;

755

return -EIO;

756

}

756

}

757

758

/* If this transaction is a write, do a following flush.

758

/* If this transaction is a write, do a following flush.

759

* Writes in u-boot are so rare, and the logic to know when is

759

* Writes in u-boot are so rare, and the logic to know when is

760

* the last write and do a flush only there is sufficiently

760

* the last write and do a flush only there is sufficiently

761

* difficult. Just do a flush after every write. This incurs,

761

* difficult. Just do a flush after every write. This incurs,

762

* usually, one extra flush when the rare writes do happen.

762

* usually, one extra flush when the rare writes do happen.

763

*/

763

*/

764

if (is_write) {

764

if (is_write) {

765

if (-EIO == ata_io_flush(pccb->target))

765

if (-EIO == ata_io_flush(pccb->target))

766

return -EIO;

766

return -EIO;

767

}

767

}

768

user_buffer += transfer_size;

768

user_buffer += transfer_size;

769

user_buffer_size -= transfer_size;

769

user_buffer_size -= transfer_size;

770

blocks -= now_blocks;

770

blocks -= now_blocks;

771

lba += now_blocks;

771

lba += now_blocks;

772

}

772

}

773

774

return 0;

774

return 0;

775

}

775

}

776

777

778

/*

778

/*

779

* SCSI READ CAPACITY10 command operation.

779

* SCSI READ CAPACITY10 command operation.

780

*/

780

*/

781

static int ata_scsiop_read_capacity10(ccb *pccb)

781

static int ata_scsiop_read_capacity10(ccb *pccb)

782

{

782

{

783

u32 cap;

783

u32 cap;

784

u32 block_size;

784

u32 block_size;

785

786

if (!ataid[pccb->target]) {

786

if (!ataid[pccb->target]) {

787

printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "

787

printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "

788

"\tNo ATA info!\n"

788

"\tNo ATA info!\n"

789

"\tPlease run SCSI commmand INQUIRY firstly!\n");

789

"\tPlease run SCSI commmand INQUIRY firstly!\n");

790

return -EPERM;

790

return -EPERM;

791

}

791

}

792

793

cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);

793

cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);

794

if (cap == 0xfffffff) {

794

if (cap == 0xfffffff) {

795

unsigned short *cap48 = ataid[pccb->target]->lba48_capacity;

795

unsigned short *cap48 = ataid[pccb->target]->lba48_capacity;

796

if (cap48[2] || cap48[3]) {

796

if (cap48[2] || cap48[3]) {

797

cap = 0xffffffff;

797

cap = 0xffffffff;

798

} else {

798

} else {

799

cap = (le16_to_cpu(cap48[1]) << 16) |

799

cap = (le16_to_cpu(cap48[1]) << 16) |

800

(le16_to_cpu(cap48[0]));

800

(le16_to_cpu(cap48[0]));

801

}

801

}

802

}

802

}

803

804

cap = cpu_to_be32(cap);

804

cap = cpu_to_be32(cap);

805

memcpy(pccb->pdata, &cap, sizeof(cap));

805

memcpy(pccb->pdata, &cap, sizeof(cap));

806

807

block_size = cpu_to_be32((u32)512);

807

block_size = cpu_to_be32((u32)512);

808

memcpy(&pccb->pdata[4], &block_size, 4);

808

memcpy(&pccb->pdata[4], &block_size, 4);

809

810

return 0;

810

return 0;

811

}

811

}

812

813

814

/*

814

/*

815

* SCSI READ CAPACITY16 command operation.

815

* SCSI READ CAPACITY16 command operation.

816

*/

816

*/

817

static int ata_scsiop_read_capacity16(ccb *pccb)

817

static int ata_scsiop_read_capacity16(ccb *pccb)

818

{

818

{

819

u64 cap;

819

u64 cap;

820

u64 block_size;

820

u64 block_size;

821

822

if (!ataid[pccb->target]) {

822

if (!ataid[pccb->target]) {

823

printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "

823

printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "

824

"\tNo ATA info!\n"

824

"\tNo ATA info!\n"

825

"\tPlease run SCSI commmand INQUIRY firstly!\n");

825

"\tPlease run SCSI commmand INQUIRY firstly!\n");

826

return -EPERM;

826

return -EPERM;

827

}

827

}

828

829

cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);

829

cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);

830

if (cap == 0xfffffff) {

830

if (cap == 0xfffffff) {

831

memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap));

831

memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap));

832

cap = le64_to_cpu(cap);

832

cap = le64_to_cpu(cap);

833

}

833

}

834

835

cap = cpu_to_be64(cap);

835

cap = cpu_to_be64(cap);

836

memcpy(pccb->pdata, &cap, sizeof(cap));

836

memcpy(pccb->pdata, &cap, sizeof(cap));

837

838

block_size = cpu_to_be64((u64)512);

838

block_size = cpu_to_be64((u64)512);

839

memcpy(&pccb->pdata[8], &block_size, 8);

839

memcpy(&pccb->pdata[8], &block_size, 8);

840

841

return 0;

841

return 0;

842

}

842

}

843

844

845

/*

845

/*

846

* SCSI TEST UNIT READY command operation.

846

* SCSI TEST UNIT READY command operation.

847

*/

847

*/

848

static int ata_scsiop_test_unit_ready(ccb *pccb)

848

static int ata_scsiop_test_unit_ready(ccb *pccb)

849

{

849

{

850

return (ataid[pccb->target]) ? 0 : -EPERM;

850

return (ataid[pccb->target]) ? 0 : -EPERM;

851

}

851

}

852

853

854

int scsi_exec(ccb *pccb)

854

int scsi_exec(ccb *pccb)

855

{

855

{

856

int ret;

856

int ret;

857

858

switch (pccb->cmd[0]) {

858

switch (pccb->cmd[0]) {

859

case SCSI_READ10:

859

case SCSI_READ10:

860

ret = ata_scsiop_read_write(pccb, 0);

860

ret = ata_scsiop_read_write(pccb, 0);

861

break;

861

break;

862

case SCSI_WRITE10:

862

case SCSI_WRITE10:

863

ret = ata_scsiop_read_write(pccb, 1);

863

ret = ata_scsiop_read_write(pccb, 1);

864

break;

864

break;

865

case SCSI_RD_CAPAC10:

865

case SCSI_RD_CAPAC10:

866

ret = ata_scsiop_read_capacity10(pccb);

866

ret = ata_scsiop_read_capacity10(pccb);

867

break;

867

break;

868

case SCSI_RD_CAPAC16:

868

case SCSI_RD_CAPAC16:

869

ret = ata_scsiop_read_capacity16(pccb);

869

ret = ata_scsiop_read_capacity16(pccb);

870

break;

870

break;

871

case SCSI_TST_U_RDY:

871

case SCSI_TST_U_RDY:

872

ret = ata_scsiop_test_unit_ready(pccb);

872

ret = ata_scsiop_test_unit_ready(pccb);

873

break;

873

break;

874

case SCSI_INQUIRY:

874

case SCSI_INQUIRY:

875

ret = ata_scsiop_inquiry(pccb);

875

ret = ata_scsiop_inquiry(pccb);

876

break;

876

break;

877

default:

877

default:

878

printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);

878

printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);

879

return false;

879

return false;

880

}

880

}

881

882

if (ret) {

882

if (ret) {

883

debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);

883

debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);

884

return false;

884

return false;

885

}

885

}

886

return true;

886

return true;

887

888

}

888

}

889

890

891

void scsi_low_level_init(int busdevfunc)

891

void scsi_low_level_init(int busdevfunc)

892

{

892

{

893

int i;

893

int i;

894

u32 linkmap;

894

u32 linkmap;

895

896

#ifndef CONFIG_SCSI_AHCI_PLAT

896

#ifndef CONFIG_SCSI_AHCI_PLAT

897

ahci_init_one(busdevfunc);

897

ahci_init_one(busdevfunc);

898

#endif

898

#endif

899

900

linkmap = probe_ent->link_port_map;

900

linkmap = probe_ent->link_port_map;

901

902

for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {

902

for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {

903

if (((linkmap >> i) & 0x01)) {

903

if (((linkmap >> i) & 0x01)) {

904

if (ahci_port_start((u8) i)) {

904

if (ahci_port_start((u8) i)) {

905

printf("Can not start port %d\n", i);

905

printf("Can not start port %d\n", i);

906

continue;

906

continue;

907

}

907

}

908

#ifdef CONFIG_AHCI_SETFEATURES_XFER

908

#ifdef CONFIG_AHCI_SETFEATURES_XFER

909

ahci_set_feature((u8) i);

909

ahci_set_feature((u8) i);

910

#endif

910

#endif

911

}

911

}

912

}

912

}

913

}

913

}

914

915

#ifdef CONFIG_SCSI_AHCI_PLAT

915

#ifdef CONFIG_SCSI_AHCI_PLAT

916

int ahci_init(u32 base)

916

int ahci_init(u32 base)

917

{

917

{

918

int i, rc = 0;

918

int i, rc = 0;

919

u32 linkmap;

919

u32 linkmap;

920

921

memset(ataid, 0, sizeof(ataid));

921

memset(ataid, 0, sizeof(ataid));

922

923

probe_ent = malloc(sizeof(struct ahci_probe_ent));

923

probe_ent = malloc(sizeof(struct ahci_probe_ent));

924

memset(probe_ent, 0, sizeof(struct ahci_probe_ent));

924

memset(probe_ent, 0, sizeof(struct ahci_probe_ent));

925

926

probe_ent->host_flags = ATA_FLAG_SATA

926

probe_ent->host_flags = ATA_FLAG_SATA

927

| ATA_FLAG_NO_LEGACY

927

| ATA_FLAG_NO_LEGACY

928

| ATA_FLAG_MMIO

928

| ATA_FLAG_MMIO

929

| ATA_FLAG_PIO_DMA

929

| ATA_FLAG_PIO_DMA

930

| ATA_FLAG_NO_ATAPI;

930

| ATA_FLAG_NO_ATAPI;

931

probe_ent->pio_mask = 0x1f;

931

probe_ent->pio_mask = 0x1f;

932

probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */

932

probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */

933

934

probe_ent->mmio_base = base;

934

probe_ent->mmio_base = base;

935

936

/* initialize adapter */

936

/* initialize adapter */

937

rc = ahci_host_init(probe_ent);

937

rc = ahci_host_init(probe_ent);

938

if (rc)

938

if (rc)

939

goto err_out;

939

goto err_out;

940

941

ahci_print_info(probe_ent);

941

ahci_print_info(probe_ent);

942

943

linkmap = probe_ent->link_port_map;

943

linkmap = probe_ent->link_port_map;

944

945

for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {

945

for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {

946

if (((linkmap >> i) & 0x01)) {

946

if (((linkmap >> i) & 0x01)) {

947

if (ahci_port_start((u8) i)) {

947

if (ahci_port_start((u8) i)) {

948

printf("Can not start port %d\n", i);

948

printf("Can not start port %d\n", i);

949

continue;

949

continue;

950

}

950

}

951

#ifdef CONFIG_AHCI_SETFEATURES_XFER

951

#ifdef CONFIG_AHCI_SETFEATURES_XFER

952

ahci_set_feature((u8) i);

952

ahci_set_feature((u8) i);

953

#endif

953

#endif

954

}

954

}

955

}

955

}

956

err_out:

956

err_out:

957

return rc;

957

return rc;

958

}

958

}

959

#endif

959

#endif

960

961

/*

961

/*

962

* In the general case of generic rotating media it makes sense to have a

962

* In the general case of generic rotating media it makes sense to have a

963

* flush capability. It probably even makes sense in the case of SSDs because

963

* flush capability. It probably even makes sense in the case of SSDs because

964

* one cannot always know for sure what kind of internal cache/flush mechanism

964

* one cannot always know for sure what kind of internal cache/flush mechanism

965

* is embodied therein. At first it was planned to invoke this after the last

965

* is embodied therein. At first it was planned to invoke this after the last

966

* write to disk and before rebooting. In practice, knowing, a priori, which

966

* write to disk and before rebooting. In practice, knowing, a priori, which

967

* is the last write is difficult. Because writing to the disk in u-boot is

967

* is the last write is difficult. Because writing to the disk in u-boot is

968

* very rare, this flush command will be invoked after every block write.

968

* very rare, this flush command will be invoked after every block write.

969

*/

969

*/

970

static int ata_io_flush(u8 port)

970

static int ata_io_flush(u8 port)

971

{

971

{

972

u8 fis[20];

972

u8 fis[20];

973

struct ahci_ioports *pp = &(probe_ent->port[port]);

973

struct ahci_ioports *pp = &(probe_ent->port[port]);

974

volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;

974

volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;

975

u32 cmd_fis_len = 5; /* five dwords */

975

u32 cmd_fis_len = 5; /* five dwords */

976

977

/* Preset the FIS */

977

/* Preset the FIS */

978

memset(fis, 0, 20);

978

memset(fis, 0, 20);

979

fis[0] = 0x27; /* Host to device FIS. */

979

fis[0] = 0x27; /* Host to device FIS. */

980

fis[1] = 1 << 7; /* Command FIS. */

980

fis[1] = 1 << 7; /* Command FIS. */

981

fis[2] = ATA_CMD_FLUSH_EXT;

981

fis[2] = ATA_CMD_FLUSH_EXT;

982

983

memcpy((unsigned char *)pp->cmd_tbl, fis, 20);

983

memcpy((unsigned char *)pp->cmd_tbl, fis, 20);

984

ahci_fill_cmd_slot(pp, cmd_fis_len);

984

ahci_fill_cmd_slot(pp, cmd_fis_len);

985

writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);

985

writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);

986

987

if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,

987

if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,

988

WAIT_MS_FLUSH, 0x1)) {

988

WAIT_MS_FLUSH, 0x1)) {

989

debug("scsi_ahci: flush command timeout on port %d.\n", port);

989

debug("scsi_ahci: flush command timeout on port %d.\n", port);

990

return -EIO;

990

return -EIO;

991

}

991

}

992

993

return 0;

993

return 0;

994

}

994

}

995

996

997

void scsi_bus_reset(void)

997

void scsi_bus_reset(void)

998

{

998

{

999

/*Not implement*/

999

/*Not implement*/

1000

}

1000

}

1001

1002

1003

void scsi_print_error(ccb * pccb)

1003

void scsi_print_error(ccb * pccb)

1004

{

1004

{

1005

/*The ahci error info can be read in the ahci driver*/

1005

/*The ahci error info can be read in the ahci driver*/

1006

}

1006

}

1007

GITLAB

ahci: increase spin-up timeout to 20 sec